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reports/20260413_120809_analysis.html
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<html lang="en">
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<head>
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0469–0498</title>
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<body>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 2 of 30 display load sessions (7%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0476</td><td>20260413_115521</td><td>dat</td><td style='color:red'>0.2 ns</td><td>347.8 ns</td><td>1.015 V</td></tr><tr><td>0480</td><td>20260413_115648</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.3 ns</td><td>1.014 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0469</td><td>20260413_115249</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0470</td><td>20260413_115311</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0471</td><td>20260413_115333</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0472</td><td>20260413_115354</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0473</td><td>20260413_115416</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0474</td><td>20260413_115438</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0475</td><td>20260413_115500</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0476</td><td>20260413_115521</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0477</td><td>20260413_115543</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0478</td><td>20260413_115605</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0479</td><td>20260413_115626</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0480</td><td>20260413_115648</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0481</td><td>20260413_115710</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0482</td><td>20260413_115732</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0483</td><td>20260413_115753</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0484</td><td>20260413_115815</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0485</td><td>20260413_115836</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0486</td><td>20260413_115858</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0487</td><td>20260413_115920</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0488</td><td>20260413_115941</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0489</td><td>20260413_120003</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0490</td><td>20260413_120025</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0491</td><td>20260413_120046</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0492</td><td>20260413_120108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0493</td><td>20260413_120130</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0494</td><td>20260413_120151</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0495</td><td>20260413_120213</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0496</td><td>20260413_120235</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0497</td><td>20260413_120256</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0498</td><td>20260413_120318</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-13 12:08:09 |
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<strong>Scope:</strong> Captures 0469–0498 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0469–0498</p>
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<p>## 1. Consistent Spec Concerns</p>
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<p>### Register Timing Violations (100% of captures — systemic)<br>All 30 captures show identical register values confirming the system is running <strong>'Round Best' mode</strong> with <strong>5 D-PHY v1.1 violations</strong>:</p>
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<p>| Parameter | Measured | Spec Min | Deficit | Severity |<br>|---|---|---|---|---|<br>| THS_EXIT | 92.6 ns | 100.0 ns | −7.4 ns (7.4%) | <strong>High — SoT critical</strong> |<br>| TCLK_PREPARE | 37.0 ns | 38.0 ns | −1.0 ns (2.6%) | <strong>High — clock SoT</strong> |<br>| TCLK_TRAIL | 55.6 ns | 60.0 ns | −4.4 ns (7.3%) | Moderate |<br>| TCLK_PREPARE+TCLK_ZERO | 296.3 ns | 300.0 ns | −3.7 ns (1.2%) | <strong>High — clock SoT</strong> |<br>| THS_PREPARE+THS_ZERO | 166.7 ns | 168.2 ns | −1.5 ns (0.9%) | <strong>High — data SoT</strong> |</p>
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<p><strong>These are the root cause of the intermittent flicker.</strong> All five violations affect the SoT handshake sequence, and all shortfalls are within ~1 byte-clock (18.5 ns) of the spec minimum — small enough that PVT (process/voltage/temperature) variation and internal clock jitter make the outcome non-deterministic, exactly matching the observed bistable behaviour.</p>
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<p>### LP Exit Duration — Universally Violated<br>- <strong>26 of 27 measurable captures</strong> show LP exit → HS of <strong>0–4 ns</strong> (spec ≥ 50 ns). Only 4 captures (0470, 0485, 0487, 0496) show ~113 ns, and Capture 0494 shows ~348 ns.<br>- This means the LP-01 → LP-00 intermediate states are being traversed in ≤ 4 ns rather than the required ≥ 50 ns. The PHY is skipping or compressing the SoT escape sequence.<br>- <strong>Direct cause:</strong> THS_EXIT = 5 bc (92.6 ns) is below the 100 ns minimum, and the too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns) means the data lane does not hold LP-00 long enough for the bridge to recognise SoT.</p>
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<p>### LP-Low Plateau — Bimodal Distribution<br>The LP-low plateau clusters at three values:<br>- <strong>~108 ns</strong> (14 captures) — marginal but functional<br>- <strong>~343 ns</strong> (13 captures) — comfortable<br>- <strong>0 ns</strong> (2 captures: <strong>0476 and 0480</strong>) — <strong>both are confirmed flicker events</strong></p>
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<p>The 0 ns plateau means the SN65DSI83 never sees LP-00 at all. With THS_PREPARE+THS_ZERO only 1.5 ns under spec, the PHY occasionally produces a prepare+zero sequence so short that LP-00 vanishes entirely from the wire. The bridge cannot detect SoT, never locks to the HS data stream, and flickers indefinitely.</p>
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<p>### HS Voltage Below 140 mV Threshold<br>Every capture shows some samples below the 140 mV D-PHY minimum:<br>- <strong>CLK lane:</strong> 15–269 sub-threshold samples per capture (consistent, moderate)<br>- <strong>DAT0 lane:</strong> 2–9142 sub-threshold samples (highly variable)</p>
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<p>The data lane violation count is notably higher in flicker captures: <strong>0476 has 2357, 0480 has 7209</strong> (the two worst after 0486's 9142). This suggests that when the SoT sequence is malformed, the bridge misaligns to the HS stream and the receiver samples data at sub-optimal points, inflating the below-140 mV count. This is likely a consequence of SoT failure, not a cause.</p>
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<p>### LP-11 Voltage — Consistently Low<br>- Range: <strong>1.014–1.016 V</strong> across all captures<br>- D-PHY spec: <strong>1.0–1.45 V</strong> → technically passing but at the <strong>absolute floor</strong> of the valid range<br>- Expected LP-11 with 1.8 V VDDIO: ~1.2 V (with typical LP driver divider)<br>- <strong>1.015 V is 200 mV below expected</strong>, suggesting either excessive resistive drop in the LP driver path, impedance mismatch on the LP lines, or a weak pull-up/driver configuration in the PHY.<br>- While within spec, this low LP-11 voltage reduces the noise margin for LP state detection by the SN65DSI83 to only <strong>~15 mV</strong> above the LP-11 recognition threshold. This further degrades the reliability of LP state transitions during SoT.</p>
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<p>## 2. Trends Across Captures</p>
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<p>### No Significant Drift<br>| Parameter | Range | Trend |<br>|---|---|---|<br>| CLK Vdiff amplitude | 165.4–166.0 mV | Flat — no degradation |<br>| DAT0 Vdiff amplitude | 186.5–199.8 mV | Flat — normal variation |<br>| CLK jitter (RMS) | 53.2–56.4 ps | Flat |<br>| CLK jitter (p-p) | 142.6–178.4 ps | Flat |<br>| Rise time (CLK/DAT) | 147.9–184.6 ps | Flat |<br>| LP-11 voltage | 1.014–1.016 V | Flat |<br>| 1.8 V supply mean | 1.7645–1.7705 V | Flat |<br>| 1.8 V supply min | 1.7520–1.7600 V | Flat |<br>| Droop depth | 8.5–12.6 mV | Flat |</p>
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<p><strong>No temperature drift, ageing, or supply degradation is observed.</strong> The problem is purely timing non-determinism at each SoT event, consistent with the bistable description.</p>
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<p>### Clock Frequency Variation<br>Most captures report ~216 MHz but several show 212.7–219.1 MHz. This ±1.5% spread is within PLL settling tolerance and likely reflects measurement window position (capturing during PLL lock). Not a direct concern but indicates the measurement sometimes catches the very first HS bursts.</p>
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<p>## 3. Anomalies</p>
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<p>### Flicker Events (Captures 0476 and 0480)<br>| | Capture 0476 | Capture 0480 |<br>|---|---|---|<br>| LP-low plateau | <strong>0 ns</strong> | <strong>0 ns</strong> |<br>| LP exit → HS | 348 ns ✓ | 3 ns ✗ |<br>| HS amplitude (SE) | 108 mV | 110 mV |<br>| DAT0 below-140mV | 2357 | <strong>7209</strong> |<br>| CLK jitter p-p | <strong>174.2 ps</strong> | <strong>178.4 ps</strong> |<br>| Supply droop | 9.4 mV | 8.5 mV |</p>
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<p><strong>Key observation:</strong> Capture 0476 shows a long LP exit (348 ns) but <strong>zero LP-low plateau</strong> — the line transitioned from LP-11 directly to HS without dwelling in LP-00. This is a classic symptom of THS_PREPARE being executed but THS_ZERO being so short that LP-00 is never asserted on the wire. The 1.5 ns shortfall in THS_PREPARE+THS_ZERO (166.7 vs 168.2 ns) means the PHY's internal counter is right at the rounding boundary; internal clock jitter (~55 ps RMS → ~330 ps 6σ) can easily push it 1–2 ns shorter on some attempts.</p>
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<p><strong>Capture 0480</strong> additionally has the shortest LP exit (3 ns) AND zero LP-low plateau — a double failure where both the LP-01 and LP-00 states were essentially skipped.</p>
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<p>Both flicker captures show slightly elevated CLK jitter p-p (174, 178 ps vs batch median ~160 ps), which could reflect the PHY operating with marginal internal timing at the moment of SoT.</p>
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<p>### DAT0 sig Captures — Intermittent "No HS Signal"<br>Captures 0469, 0471, 0479, 0486, 0498 show DAT0 sig amplitude = 0.0 mV ("No HS signal detected"). This occurs because the high-res sig capture window is very narrow and the data lane is between HS bursts (LP or idle) at that instant. Not a hardware fault — the proto captures always show valid DAT0 amplitude.</p>
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<p>### DAT0 "Only Negative Swings"<br>Approximately 60% of captures show DAT0 with only negative differential swings in the sig/proto window. This indicates the trigger point consistently lands on a data pattern dominated by one polarity (e.g., a run of 0x00 or 0xFF bytes). Not a signal integrity concern — the full differential amplitude is still 186–200 mV.</p>
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<p>### CLK Common Mode Offset<br>The CLK lane shows a consistent <strong>+29 mV common mode offset</strong>. D-PHY spec allows ±25 mV variation around Vcm; at +29 mV this is slightly out of family but the absolute Vcm is within the receiver's 200 mV tolerance band. <strong>Not a direct flicker cause</strong> but indicates slight impedance asymmetry in the CLK pair routing.</p>
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<p>### Capture 0497 — LP DAT Processing Error<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, and the analysis script attempted to read past the end. This means the LP→HS transition occurred very late in the capture window, or the HS burst extended to the end of the buffer. <strong>Not a hardware fault</strong> — adjust trigger position or increase buffer depth to avoid this.</p>
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<p>## 4. Supply Correlation Analysis</p>
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<p>### 1.8 V Supply vs. LP Anomalies</p>
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<p>| Parameter | Flicker (0476/0480) | Non-flicker (all others) |<br>|---|---|---|<br>| Mean 1.8 V | 1.765 / 1.765 V | 1.764–1.771 V |<br>| Min 1.8 V | 1.756 / 1.756 V | 1.752–1.760 V |<br>| Droop | 9.4 / 8.5 mV | 8.5–12.6 mV |<br>| Ripple RMS | 5.65 / 5.38 mV | 5.24–6.14 mV |</p>
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<p><strong>There is no correlation between supply droop/ripple and flicker.</strong> The flicker captures have average-to-good supply metrics. The worst droop (12.6 mV, Capture 0470) produced a clean SoT with 113 ns LP exit. The supply is solidly within spec at all times (min 1.752 V vs 1.71 V spec floor).</p>
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<p><strong>Conclusion: The 1.8 V supply is not the flicker trigger.</strong> The root cause is purely the PHY timing register configuration, with the probabilistic outcome determined by internal PHY clock jitter at the SoT moment.</p>
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<p>### LP-11 Voltage vs. Supply<br>LP-11 at ~1.015 V with VDDIO at ~1.765 V gives a ratio of 0.575, well below the expected ~0.67. This suggests the LP driver output impedance is higher than expected or there is a series resistance in the LP signal path. However, this is constant across all captures and does not differentiate flicker from non-flicker events.</p>
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<p>## 5. Warning/Error Explanations</p>
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<p>| Warning | Count | Likely Cause | Action |<br>|---|---|---|---|<br>| "LP exit duration N ns below spec min 50 ns" | 23/27 | <strong>THS_EXIT=5 bc (92.6 ns) and THS_PREPARE+THS_ZERO shortfall</strong> — PHY compresses LP-01→LP-00 states below detection threshold | <strong>Switch to 'Round Up' registers</strong> |<br>| "FLICKER SUSPECT: LP-low plateau absent" | 2/27 | THS_PREPARE+THS_ZERO ~1.5 ns short; internal jitter occasionally eliminates LP-00 entirely | <strong>Switch to 'Round Up' registers</strong> |<br>| "No HS signal detected" on DAT0 sig | 5/30 | Narrow capture window landed during LP/idle; data is bursty (video mode) | Widen sig capture window or trigger on HS preamble |<br>| "Only negative swings in capture window" | ~18/30 | Capture window hits a run of identical data bits | Not a concern — normal for video data |<br>| "Settled samples below 140 mV" on CLK | 30/30 | CLK amplitude ~166 mV with ~55 ps RMS jitter means crossing transitions occasionally dip below 140 mV | Moderate concern — increase CLK drive strength if possible |<br>| "Settled samples below 140 mV" on DAT0 | 29/30 | ISI from data transitions + ~1.5 ns short zero state → sampling during transition | Will improve with compliant timing |<br>| "index 200000 out of bounds" (0497) | 1/30 | Analysis buffer overflow — LP→HS transition at edge of capture window | Move trigger earlier or extend buffer |</p>
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<p>## 6. Actionable Recommendations</p>
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<p>### CRITICAL — Fix Immediately</p>
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<p><strong>① Switch to 'Round Up' PHY timing registers.</strong> This is the single change that will eliminate the flicker:</p>
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<p>```<br># Apply via memtool, device tree, or driver patch:<br>DSIM_PHYTIMING (0x32e100b4) = 0x00000306 # THS_EXIT=6 → 111.1 ns ✓<br>DSIM_PHYTIMING1 (0x32e100b8) = 0x030f0a04 # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓<br>DSIM_PHYTIMING2 (0x32e100bc) = 0x00030706 # THS_ZERO=7, THS_TRAIL=6 ✓<br>```</p>
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<p>This adds exactly <strong>1 byte-clock (18.5 ns) of margin</strong> to each violated parameter, bringing all five into full D-PHY v1.1 compliance. The cost is ~18–37 ns additional latency per SoT sequence — completely negligible for a 60 Hz video stream.</p>
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<p><strong>Driver-level fix:</strong> In the samsung-dsim (or sec-dsim) driver, the timing calculation function uses `DIV_ROUND_UP()` vs. truncating division for these fields. Ensure the driver is configured for ceiling rounding. On NXP BSPs, check `imx8mm-{board}.dts` for `samsung,phy-timing` overrides, or patch `samsung_dsim_set_phy_timing()` in `drivers/gpu/drm/bridge/samsung-dsim.c` to always round up.</p>
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<p><strong>② Verify the fix eliminates LP-low = 0 ns events.</strong> After applying Round Up registers, re-run 50+ pipeline load cycles and confirm:<br>- LP-low plateau ≥ 50 ns on every capture<br>- LP exit → HS ≥ 50 ns on every capture<br>- Zero flicker events</p>
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<p>### IMPORTANT — Address After Fix</p>
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<p><strong>③ Investigate low LP-11 voltage (1.015 V).</strong> While in-spec, this is anomalously low:<br>- Check for series resistance in LP signal path (ferrite beads, ESD protection, connector contact resistance)<br>- Verify VDDIO_MIPI is directly connected to 1.8 V rail (not through a long trace or shared via)<br>- Confirm the PHY LP driver strength setting is correct for the load</p>
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<p><strong>④ Address CLK lane common-mode offset (+29 mV).</strong> This suggests:<br>- Slight trace length mismatch on CLK± pair (~0.3 mm at 216 MHz)<br>- Or asymmetric loading (e.g., one CLK line has a test point or probe stub the other doesn't)<br>- Verify CLK± differential pair routing is tightly coupled with matched lengths</p>
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<p><strong>⑤ Consider adding margin beyond bare minimum.</strong> The 'Round Up' values are still close to spec minimums. For production robustness, consider adding</p>
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<p class="tokens">Tokens: 45337 in / 4096 out</p>
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</html>
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