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This commit is contained in:
david rice
2026-04-13 15:03:47 +01:00
parent 17d393cbd1
commit fa96fef9ea
11 changed files with 724 additions and 37 deletions
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77
analyze_captures.py
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@@ -38,27 +38,31 @@ REPORTS_DIR = Path(__file__).parent / "reports"
# HS bit UI = 1 / 432e6 ≈ 2.315 ns
# Byte clock = 432 / 8 = 54 MHz → 18.518 ns/byte
#
# MIPI D-PHY v1.1 minimum timings at 432 Mbit/s:
# T_LPX ≥ 50 ns
# T_HS-PREPARE 40+4·UI → 85+6·UI = 49.3–98.9 ns
# T_HS-ZERO ≥ 145+10·UI = 168.2 ns
# T_HS-TRAIL ≥ max(8·UI, 60+4·UI) = 69.3 ns
# T_HS-EXIT ≥ 100 ns
# T_CLK-PREPARE 38–95 ns
# T_CLK-ZERO ≥ 300 ns
# T_CLK-POST ≥ 60+52·UI = 180.4 ns
# T_CLK-TRAIL ≥ 60 ns
# MIPI D-PHY v1.1 Table 14 timing constraints at 432 Mbit/s (UI = 2.315 ns):
# T_LPX ≥ 50 ns
# T_HS-PREPARE 40+4·UI → 85+6·UI = 49.3–98.9 ns (individual range)
# T_HS-PREPARE+T_HS-ZERO ≥ 145+10·UI = 168.2 ns (combined minimum; no per-field min on T_HS-ZERO)
# T_HS-TRAIL ≥ max(8·UI, 60+4·UI) = 69.3 ns
# T_HS-EXIT ≥ 100 ns
# T_CLK-PREPARE 38–95 ns (individual range)
# T_CLK-PREPARE+T_CLK-ZERO ≥ 300 ns (combined minimum; no per-field min on T_CLK-ZERO)
# T_CLK-POST ≥ 60+52·UI = 180.4 ns
# T_CLK-TRAIL ≥ 60 ns
#
# In byte-clock units (÷ 18.518 ns, round up):
# TLPX = 3 (55.6 ns)
# THS_PREPARE = 3 (55.6 ns — within 49.3–98.9 ns window)
# THS_ZERO = 10 (185.2 ns ≥ 168.2 ns ✓)
# THS_TRAIL = 4 (74.1 ns ≥ 69.3 ns ✓)
# THS_EXIT = 6 (111.1 ns ≥ 100 ns ✓)
# TCLK_PREPARE = 3 (55.6 ns — within 38–95 ns ✓)
# TCLK_ZERO = 17 (314.8 ns ≥ 300 ns ✓)
# TCLK_POST = 10 (185.2 ns ≥ 180.4 ns ✓)
# TCLK_TRAIL = 4 (74.1 ns ≥ 60 ns ✓)
# Samsung DSIM field mapping (verified against kernel log output):
# PHYTIMING (0xb4): [15:8]=TLPX, [7:0]=THS_EXIT
# PHYTIMING1 (0xb8): [31:24]=TCLK_PREPARE, [23:16]=TCLK_ZERO,
# [15:8]=TCLK_POST, [7:0]=TCLK_TRAIL
# PHYTIMING2 (0xbc): [23:16]=THS_PREPARE, [15:8]=THS_ZERO, [7:0]=THS_TRAIL
#
# Kernel driver computes: clk_zero = 300 − 38 = 262 ns minimum;
# hs_zero = 145 + 10·UI − (40 + 4·UI) = 105 + 6·UI = 118.9 ns minimum
#
# Actual register values programmed by samsung-dsim driver (samsung_dsim_set_phy_ctrl):
# "Round Best" (default): PHY_TIMING=00000305, PHY_TIMING1=020e0a03, PHY_TIMING2=00030605
# → MULTIPLE D-PHY SPEC VIOLATIONS (see dsim_phytiming_round_best below)
# "Round Up": PHY_TIMING=00000306, PHY_TIMING1=030f0a04, PHY_TIMING2=00030706
# → ALL fields spec-compliant
DEVICE_CONFIG = {
"dsi_host": "NXP i.MX 8M Mini (Samsung DSIM IP, sec-dsim/samsung-dsim driver)",
"dsi_bridge": "Texas Instruments SN65DSI83 (MIPI-to-LVDS)",
@@ -75,16 +79,18 @@ DEVICE_CONFIG = {
"byte_clock_mhz": 54, # 432 / 8
"byte_period_ns": 18.518,
"vddio_v": 1.8,
# Samsung DSIM PHY timing field mapping (sec_mipi_dsim.c / samsung-dsim.c):
# PHYTIMING (0xb4): [15:8]=TLPX, [7:0]=THS_EXIT
# PHYTIMING1 (0xb8): [31:24]=TCLK_PREPARE, [23:16]=TCLK_ZERO,
# [15:8]=TCLK_POST, [7:0]=TCLK_TRAIL
# PHYTIMING2 (0xbc): [23:16]=THS_TRAIL, [15:8]=THS_ZERO, [7:0]=THS_PREPARE
# All fields in byte-clock units (÷ 18.518 ns, rounded up) per MIPI D-PHY v1.1:
"dsim_phytiming_target": {
"PHYTIMING (0xb4)": "0x00000306 (TLPX=3→55.6ns ≥50ns ✓, THS_EXIT=6→111ns ≥100ns ✓)",
"PHYTIMING1 (0xb8)": "0x03110A04 (TCLK_PREPARE=3→55.6ns, TCLK_ZERO=17→315ns ≥300ns ✓, TCLK_POST=10→185ns ≥180ns ✓, TCLK_TRAIL=4→74ns ≥60ns ✓)",
"PHYTIMING2 (0xbc)": "0x00040A03 (THS_TRAIL=4→74ns ≥69ns ✓, THS_ZERO=10→185ns ≥168ns ✓, THS_PREPARE=3→56ns within 49-99ns ✓)",
# Actual register values from kernel (samsung_dsim_set_phy_ctrl) — two rounding modes:
"dsim_phytiming_round_best": {
"PHYTIMING (0xb4)": "0x00000305 (TLPX=3→55.6ns ✓, THS_EXIT=5→92.6ns < 100ns ✗)",
"PHYTIMING1 (0xb8)": "0x020e0a03 (TCLK_PREPARE=2→37.0ns < 38ns ✗, TCLK_ZERO=14, PREP+ZERO=16bc→296ns < 300ns ✗, TCLK_POST=10→185ns ✓, TCLK_TRAIL=3→55.6ns < 60ns ✗)",
"PHYTIMING2 (0xbc)": "0x00030605 (THS_PREPARE=3→55.6ns ✓, THS_ZERO=6, PREP+ZERO=9bc→166.7ns < 168.2ns ✗, THS_TRAIL=5→92.6ns ✓)",
"verdict": "NON-COMPLIANT — 5 D-PHY violations; flicker risk at SoT",
},
"dsim_phytiming_round_up": {
"PHYTIMING (0xb4)": "0x00000306 (TLPX=3→55.6ns ✓, THS_EXIT=6→111.1ns ✓)",
"PHYTIMING1 (0xb8)": "0x030f0a04 (TCLK_PREPARE=3→55.6ns ✓, TCLK_ZERO=15, PREP+ZERO=18bc→333ns ✓, TCLK_POST=10→185ns ✓, TCLK_TRAIL=4→74.1ns ✓)",
"PHYTIMING2 (0xbc)": "0x00030706 (THS_PREPARE=3→55.6ns ✓, THS_ZERO=7, PREP+ZERO=10bc→185.2ns ✓, THS_TRAIL=6→111.1ns ✓)",
"verdict": "FULLY COMPLIANT with D-PHY v1.1 Table 14",
},
}
@@ -207,7 +213,8 @@ def process_capture(
def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
flicker_count: int = 0, total_sessions: int = 0) -> str:
cfg = DEVICE_CONFIG
target = cfg["dsim_phytiming_target"]
best = cfg["dsim_phytiming_round_best"]
up = cfg["dsim_phytiming_round_up"]
config_section = (
f"Device under test:\n"
f" DSI host: {cfg['dsi_host']}\n"
@@ -222,8 +229,12 @@ def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
f" HS UI: {cfg['hs_ui_ns']:.3f} ns\n"
f" Byte clock: {cfg['byte_clock_mhz']} MHz ({cfg['byte_period_ns']:.3f} ns/byte)\n"
f" VDDIO: {cfg['vddio_v']} V\n"
f" Target DSIM PHY timing registers (byte-clock units, MIPI D-PHY v1.1 compliant):\n"
+ "\n".join(f" {k}: {v}" for k, v in target.items())
f" DSIM PHY timing — 'Round Best' mode (D-PHY v1.1 non-compliant):\n"
+ "\n".join(f" {k}: {v}" for k, v in best.items())
+ f"\n DSIM PHY timing — 'Round Up' mode (D-PHY v1.1 fully compliant):\n"
+ "\n".join(f" {k}: {v}" for k, v in up.items())
+ f"\n NOTE: Compare captured register values against both modes above. "
f"'Round Best' has 5 spec violations that could cause non-deterministic SoT failures."
)
body = "\n\n".join(all_summaries)