Updated

mipi_test.py

@@ -32,8 +32,11 @@ SIG_SCALE  = 2e-9       # 2 ns/div → 20 ns window
 SIG_POINTS = 500_000    # 500 k pts → ~25 GSa/s
 
 # Pass 2 — protocol/frame structure: shows LP↔HS transitions and burst envelope
-PROTO_SCALE  = 1e-6     # 1 µs/div → 10 µs window
-PROTO_POINTS = 500_000  # 500 k pts → 50 MSa/s (enough to see burst structure)
+# 1280×800 24bpp 4-lane: full HS burst ≈ 18 µs. 4 µs/div → 40 µs window captures
+# the complete line payload for DSI packet decode. 500 k pts @ 40 µs = 80 ps/sample
+# (~28 samples/bit at 430 Mbps) — adequate for bit-level decoding.
+PROTO_SCALE  = 4e-6     # 4 µs/div → 40 µs window (was 1 µs/div)
+PROTO_POINTS = 500_000  # 500 k pts
 
 # Pass 3 — LP state capture: widens vertical range to show LP-11 (~1.2 V)
 # Channels reconfigured to 200 mV/div, offset +0.6 V → display spans −0.2 V to 1.4 V.
@@ -353,13 +356,18 @@ def dual_capture(iteration):
     else:
         print("  SKIPPING SIG SAVE.")
 
-    # ── Pass 3: frame/protocol structure ──────────────────────────────────
-    print("  PASS 3: FRAME STRUCTURE...")
+    # ── Pass 3: frame/protocol structure (LP-triggered differential) ─────────
+    # Re-apply LP trigger so the LP-00 → HS transition lands near t=0 in F2.
+    # This gives a fixed byte-framing anchor: HS sync byte 0xB8 appears at
+    # t≈380 ns, followed by DI, WC, ECC, then the full pixel payload.
+    print("  PASS 3: FRAME STRUCTURE (LP-triggered differential)...")
+    _configure_for_lp()
     _set_timebase(PROTO_SCALE, PROTO_POINTS)
     if _arm_and_wait():
         _save_pass("proto", iteration, ts)
     else:
         print("  SKIPPING PROTO SAVE.")
+    _restore_hs_config()
 
     # ── Fetch DSI register snapshot from device ───────────────────────────
     # Display is still ON here; registers reflect the active pipeline state.