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david rice
2026-04-20 10:34:42 +01:00
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<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Interactive Flicker Test &mdash; 2026-04-20 07:46:57</title>
<style>
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
h2 { color: #1a3a5c; margin-top: 32px; }
h3 { color: #333; }
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
tr:nth-child(even) { background: #fafafa; }
pre { margin: 0; }
</style>
</head>
<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-20 07:46:57 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">2 false alarm(s)</div>
<div class="stat s-claude-no">0 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+1</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 94.1</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+1</td><td><strong>5</strong></td><td>92.59</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+3</td><td><strong>17</strong></td><td>314.81</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x03110a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=17 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00040605</code></td>
<td>hs_prepare=4 &nbsp; hs_zero=6 &nbsp;
hs_trail=5</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x03110a04 clk_prepare=3 clk_zero=17 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00040605 hs_prepare=4 hs_zero=6 hs_trail=5
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
# Extra PHY cycles above Round-Up minimum
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-hs-prepare=1&quot;
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-hs-trail=1&quot;
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-clk-zero=3&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<table>
<tr>
<th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th>
<th>Claude: flicker?</th><th>Outcome</th>
</tr>
<tr><td>0002</td><td>20260420_074452</td><td>dat</td><td>107.8 ns</td><td>3.1 ns</td><td>1.017 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0004</td><td>20260420_074554</td><td>dat</td><td>107.4 ns</td><td>1.2 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr>
</table>
<h2>Claude Assessments</h2><h3>Capture 0002 [20260420_074452] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau at ~108 ns exceeds the 50 ns minimum, but the critical failure here is the **LP exit → HS transition of only 3 ns**, far below the 50 ns specification minimum. This means the LP-01 and LP-00 states that constitute the SoT preamble are essentially absent or too brief for the SN65DSI83 to reliably detect. Additionally, the **HS amplitude of 30 mV** is well below the normal 105–122 mV range and falls under the 50 mV &quot;absent&quot; threshold, indicating the bridge likely never locked onto the HS data. Together, the collapsed LP-exit timing and effectively absent HS signaling strongly indicate a missed SoT event that would produce visible flicker.</pre><h3>Capture 0004 [20260420_074554] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The HS amplitude of only 32 mV (well below the 50 mV &quot;absent&quot; threshold and far from the normal 105–122 mV range) indicates the HS data burst was essentially not received by the SN65DSI83, even though the LP-low plateau at 107 ns nominally meets the ≥50 ns requirement. Critically, the LP exit → HS transition time of only 1 ns (spec ≥50 ns) means the LP-01/LP-00 states were not properly held long enough for the bridge to recognize the SoT preamble — the pre-processor itself flagged this as below spec. The combination of a collapsed LP-exit duration and an effectively absent HS swing strongly indicates the bridge missed start-of-transmission on this frame, which would produce visible flicker.</pre>
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<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Interactive Flicker Test &mdash; 2026-04-20 09:10:26</title>
<style>
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
h2 { color: #1a3a5c; margin-top: 32px; }
h3 { color: #333; }
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
tr:nth-child(even) { background: #fafafa; }
pre { margin: 0; }
</style>
</head>
<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-20 09:10:26 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">4 false alarm(s)</div>
<div class="stat s-claude-no">0 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+1</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 94.1</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+1</td><td><strong>5</strong></td><td>92.59</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+3</td><td><strong>17</strong></td><td>314.81</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x03110a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=17 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00040605</code></td>
<td>hs_prepare=4 &nbsp; hs_zero=6 &nbsp;
hs_trail=5</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x03110a04 clk_prepare=3 clk_zero=17 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00040605 hs_prepare=4 hs_zero=6 hs_trail=5
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
# Extra PHY cycles above Round-Up minimum
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-hs-prepare=1&quot;
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-hs-trail=1&quot;
setenv flb_dtovar &quot;${flb_dtovar} dsi-phy-extra-clk-zero=3&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<table>
<tr>
<th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th>
<th>Claude: flicker?</th><th>Outcome</th>
</tr>
<tr><td>0006</td><td>20260420_090522</td><td>dat</td><td style="color:red">6.4 ns</td><td>0.1 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0007</td><td>20260420_090607</td><td>dat</td><td>108.0 ns</td><td>3.4 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0011</td><td>20260420_090800</td><td>dat</td><td style="color:red">None ns</td><td>None ns</td><td>1.015 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0013</td><td>20260420_090915</td><td>dat</td><td style="color:red">None ns</td><td>0.3 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr>
</table>
<h2>Claude Assessments</h2><h3>Capture 0006 [20260420_090522] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau of 6.4 ns is drastically below the SN65DSI83&#x27;s required ≥ 50 ns minimum for SoT detection, making it virtually certain the bridge missed the start-of-transmission. This is further corroborated by the HS amplitude of only 46 mV—well below the normal 105–122 mV range and below the 50 mV &quot;absent&quot; threshold—indicating the HS data burst was either never properly initiated or was not recognized by the receiver. The follow-up capture shows a recovery to a 108 ns LP-low plateau and a healthy 114 mV HS amplitude, consistent with the pattern where a single corrupted frame causes a visible flicker one frame later while the link re-establishes normal operation.</pre><h3>Capture 0007 [20260420_090607] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the HS amplitude of only 21 mV is far below the normal 105–122 mV range and well under the 50 mV threshold for a valid HS signal. This means the SN65DSI83 bridge almost certainly cannot resolve the differential HS data even if SoT entry were detected. Additionally, the LP exit → HS transition of only 3 ns (spec ≥ 50 ns) indicates the LP-01/LP-00 states are effectively absent or too brief for reliable detection, compounding the problem. The combination of a virtually absent LP exit duration and critically low HS amplitude makes it highly likely the bridge missed or failed to lock onto the HS burst, producing a visible flicker event.</pre><h3>Capture 0011 [20260420_090800] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The primary capture on the DAT0 lane shows an **absent LP-low plateau** (reported as `None`), meaning the transmitter never held LP-00/LP-01 long enough—or at all—for the SN65DSI83 to recognize a valid Start-of-Transmission preamble (≥ 50 ns required). Additionally, the HS amplitude is reported as `None`, confirming no usable HS burst was delivered in this frame. The follow-up capture corroborates the flicker scenario: although it does show an LP-low plateau of 380 ns (adequate timing), the HS amplitude is only **22 mV**—well below the 50 mV minimum detection threshold—meaning the bridge would fail to decode that burst as well. Taken together, the missing SoT preamble in the primary capture and the sub-threshold HS amplitude in the follow-up frame strongly indicate at least one (and likely two) consecutive frames were lost by the bridge, producing visible display flicker.</pre><h3>Capture 0013 [20260420_090915] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The DAT0 lane shows an LP-low plateau of effectively 0 ns (flagged as absent/None), far below the SN65DSI83&#x27;s required ≥ 50 ns minimum for SoT detection. The LP exit → HS transition time of 0 ns confirms that the LP-01/LP-00 preamble states were either entirely skipped or too brief to be resolved, meaning the bridge almost certainly missed the start-of-transmission. The follow-up capture at 090936 corroborates this: no LP-11 state, no LP→HS transition, and no HS bursts were detected, consistent with the bridge having lost synchronization and the link being in a broken/stalled state — exactly the pattern that produces visible flicker (or a blank frame) on the display.</pre>
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7
reports/flicker_log.csv
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@@ -211,3 +211,10 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v
2026-04-17 14:42:52,20260417_144230,0355,dat,108.0,2.0,1.015
2026-04-17 14:44:36,20260417_144415,0359,dat,379.6,384.6,1.015
2026-04-17 14:48:11,20260417_144749,0368,dat,107.8,2.0,1.016
2026-04-20 07:45:14,20260420_074452,0002,dat,107.8,3.1,1.017
2026-04-20 07:46:15,20260420_074554,0004,dat,107.4,1.2,1.016
2026-04-20 09:05:43,20260420_090522,0006,dat,6.4,0.1,1.016
2026-04-20 09:06:29,20260420_090607,0007,dat,108.0,3.4,1.016
2026-04-20 09:08:22,20260420_090800,0011,dat,,,1.015
2026-04-20 09:08:29,20260420_090822,0011,dat,379.6,384.8,1.015
2026-04-20 09:09:36,20260420_090915,0013,dat,,0.3,1.016
1 logged_at capture_ts capture_num channel lp_low_duration_ns lp11_to_hs_ns lp11_voltage_v
211 2026-04-17 14:42:52 20260417_144230 0355 dat 108.0 2.0 1.015
212 2026-04-17 14:44:36 20260417_144415 0359 dat 379.6 384.6 1.015
213 2026-04-17 14:48:11 20260417_144749 0368 dat 107.8 2.0 1.016
214 2026-04-20 07:45:14 20260420_074452 0002 dat 107.8 3.1 1.017
215 2026-04-20 07:46:15 20260420_074554 0004 dat 107.4 1.2 1.016
216 2026-04-20 09:05:43 20260420_090522 0006 dat 6.4 0.1 1.016
217 2026-04-20 09:06:29 20260420_090607 0007 dat 108.0 3.4 1.016
218 2026-04-20 09:08:22 20260420_090800 0011 dat 1.015
219 2026-04-20 09:08:29 20260420_090822 0011 dat 379.6 384.8 1.015
220 2026-04-20 09:09:36 20260420_090915 0013 dat 0.3 1.016

6
reports/interactive_log.csv
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@@ -141,3 +141,9 @@ logged_at,capture_ts,capture_num,claude_said_flicker,user_confirmed,lp_low_ns,re
2026-04-17 14:43:04,20260417_144230,0355,YES,NO,108.0,"YES The LP-low plateau of 108 ns meets the ≥50 ns requirement, but the LP exit-to-HS transition of only 2 ns is critically below the 50 ns spec minim"
2026-04-17 14:44:43,20260417_144415,0359,NO,NOT_ASKED,379.6,NO The LP-low plateau of 379.6 ns and the LP-11→HS transition time of 384.6 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for
2026-04-17 14:48:47,20260417_144749,0368,YES,YES,107.8,YES The HS amplitude of 32 mV is critically low — well below the SN65DSI83's minimum differential detection threshold (typically ~70 mV single-ended
2026-04-20 07:45:30,20260420_074452,0002,YES,NO,107.8,"YES The LP-low plateau at ~108 ns exceeds the 50 ns minimum, but the critical failure here is the **LP exit → HS transition of only 3 ns**, far below"
2026-04-20 07:46:31,20260420_074554,0004,YES,NO,107.4,"YES The HS amplitude of only 32 mV (well below the 50 mV ""absent"" threshold and far from the normal 105–122 mV range) indicates the HS data burst was"
2026-04-20 09:06:06,20260420_090522,0006,YES,NO,6.4,"YES The LP-low plateau of 6.4 ns is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection, making it virtually certain the bri"
2026-04-20 09:06:50,20260420_090607,0007,YES,NO,108.0,"YES Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the HS amplitude of only 21 mV is far below the normal 105–122 mV r"
2026-04-20 09:08:51,20260420_090800,0011,YES,NO,,"YES The primary capture on the DAT0 lane shows an **absent LP-low plateau** (reported as `None`), meaning the transmitter never held LP-00/LP-01 long"
2026-04-20 09:09:58,20260420_090915,0013,YES,NO,,"YES The DAT0 lane shows an LP-low plateau of effectively 0 ns (flagged as absent/None), far below the SN65DSI83's required ≥ 50 ns minimum for SoT de"
1 logged_at capture_ts capture_num claude_said_flicker user_confirmed lp_low_ns reasoning_summary
141 2026-04-17 14:43:04 20260417_144230 0355 YES NO 108.0 YES The LP-low plateau of 108 ns meets the ≥50 ns requirement, but the LP exit-to-HS transition of only 2 ns is critically below the 50 ns spec minim
142 2026-04-17 14:44:43 20260417_144415 0359 NO NOT_ASKED 379.6 NO The LP-low plateau of 379.6 ns and the LP-11→HS transition time of 384.6 ns both comfortably exceed the SN65DSI83's 50 ns minimum requirement for
143 2026-04-17 14:48:47 20260417_144749 0368 YES YES 107.8 YES The HS amplitude of 32 mV is critically low — well below the SN65DSI83's minimum differential detection threshold (typically ~70 mV single-ended
144 2026-04-20 07:45:30 20260420_074452 0002 YES NO 107.8 YES The LP-low plateau at ~108 ns exceeds the 50 ns minimum, but the critical failure here is the **LP exit → HS transition of only 3 ns**, far below
145 2026-04-20 07:46:31 20260420_074554 0004 YES NO 107.4 YES The HS amplitude of only 32 mV (well below the 50 mV "absent" threshold and far from the normal 105–122 mV range) indicates the HS data burst was
146 2026-04-20 09:06:06 20260420_090522 0006 YES NO 6.4 YES The LP-low plateau of 6.4 ns is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection, making it virtually certain the bri
147 2026-04-20 09:06:50 20260420_090607 0007 YES NO 108.0 YES Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the HS amplitude of only 21 mV is far below the normal 105–122 mV r
148 2026-04-20 09:08:51 20260420_090800 0011 YES NO YES The primary capture on the DAT0 lane shows an **absent LP-low plateau** (reported as `None`), meaning the transmitter never held LP-00/LP-01 long
149 2026-04-20 09:09:58 20260420_090915 0013 YES NO YES The DAT0 lane shows an LP-low plateau of effectively 0 ns (flagged as absent/None), far below the SN65DSI83's required ≥ 50 ns minimum for SoT de