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<title>MIPI Analysis — Captures 0305–0334</title>
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<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 1 of 30 display load sessions (3%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0322</td><td>20260410_085631</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.1 ns</td><td>1.016 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0305</td><td>20260410_085024</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260410_085046</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260410_085108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260410_085129</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260410_085151</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260410_085212</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260410_085234</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260410_085256</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260410_085317</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260410_085339</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260410_085400</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260410_085422</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260410_085444</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260410_085505</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260410_085527</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260410_085548</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260410_085610</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260410_085631</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260410_085653</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260410_085715</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260410_085737</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260410_085758</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260410_085820</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260410_085841</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260410_085903</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260410_085925</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260410_085946</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260410_090008</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0333</td><td>20260410_090030</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0334</td><td>20260410_090052</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-10 09:05:39 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0305–0334 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0305–0334</p>
<ul><li></li></ul>
<p>## 1. Register Mismatch: Root Cause of All LP Timing Violations</p>
<p><strong>This is the single most important finding and the primary root cause.</strong></p>
<p>### Actual vs. Target Registers</p>
<p>| Register | Target | Actual (all captures) | Impact |<br>|---|---|---|---|<br>| PHYTIMING (0xb4) | <strong>0x00000306</strong> | <strong>0x00000305</strong> | THS_EXIT=5 → 92.6 ns (spec ≥100 ns) <strong>✗</strong> |<br>| PHYTIMING1 (0xb8) | <strong>0x03110A04</strong> | <strong>0x020e0a03</strong> | TCLK_PREPARE=2→37ns (spec 38–95ns) <strong>✗</strong>, TCLK_ZERO=14→259ns (spec ≥300ns) <strong>✗</strong>, TCLK_TRAIL=3→55.6ns (spec ≥60ns) <strong>✗</strong> |<br>| PHYTIMING2 (0xbc) | <strong>0x00040A03</strong> | <strong>0x00030605</strong> | THS_PREPARE=5→92.6ns (spec 40–85+6×UI=99ns — borderline), THS_ZERO=6→111ns (spec ≥145+10×UI=168ns) <strong>✗✗</strong>, THS_TRAIL=3→55.6ns (spec max(8×UI+60ns=78.5ns, 60+4×UI=69.3ns) <strong>✗</strong> |</p>
<p><strong>Every single DSIM PHY timing register is wrong.</strong> The driver is not applying the target values. The actual values produce:</p>
<ul><li><strong>TCLK_ZERO 41 ns too short</strong> — clock lane HS-0 period truncated; receiver may not lock PLL</li><li><strong>THS_ZERO 57 ns too short</strong> — data lane HS-0 period truncated; this directly truncates the SoT (LP-11 → LP-01 → LP-00 → HS-0) sequence</li><li><strong>TCLK_TRAIL and THS_TRAIL both below spec</strong> — trailing edges clipped</li><li><strong>THS_EXIT 7.4 ns below spec</strong> — LP escape timing marginal</li><li><strong>TCLK_PREPARE below spec</strong> — clock preparation phase too short</li></ul>
<p>The short THS_ZERO is the direct mechanism causing the observed 0–4 ns &quot;LP exit → HS&quot; measurements. The PHY is spending only 6 byte-clocks (111 ns) in the HS-0 preamble instead of the required 10 (185 ns). The SN65DSI83 needs to see the complete LP-11 → LP-01 → LP-00 → HS-0 sequence with each state held for its minimum duration to detect SoT. With THS_ZERO truncated by ~40%, the LP-00 → HS-0 transition is compressed and the bridge&#x27;s SoT detector has a race condition.</p>
<p>### Why the Flicker is Bistable and Non-Deterministic</p>
<p>The too-short THS_ZERO and TCLK_ZERO create a <strong>metastable SoT detection window</strong> in the SN65DSI83. The bridge&#x27;s internal SoT state machine samples the LP/HS transition at a clock edge that is itself jittery (~50 ps RMS on CLK). With the programmed timings leaving only ~0–4 ns of margin (should be ≥50 ns), the bridge either:<br>- <strong>Catches the SoT</strong> (State A — good, display works) — happens ~97% of the time because the PHY still produces *something* resembling the sequence<br>- <strong>Misses the SoT</strong> (State B — bad, flicker) — happens ~3% when jitter/PVT variation pushes the transition outside the bridge&#x27;s sampling window</p>
<p>Once locked/unlocked, the bridge stays in that state until the pipeline is reloaded because continuous HS mode doesn&#x27;t re-issue SoT.</p>
<ul><li></li></ul>
<p>## 2. Consistent Spec Concerns</p>
<p>### 2a. LP Exit Duration — Systematic Violation (26 of 28 measurable captures)</p>
<p>| Measured LP exit | Count | Captures |<br>|---|---|---|<br>| 0–4 ns (FAIL, spec ≥50 ns) | 22 | 0305,0308–0310,0313–0315,0317,0319–0322,0324,0326–0327,0329–0334 |<br>| 108 ns | 4 | 0309,0315,0329,0331,0334 |<br>| 188–348 ns (PASS) | 4 | 0306,0307,0312,0316,0318,0323,0325 |<br>| Not detected | 2 | 0311,0328 |</p>
<p><strong>The &quot;passing&quot; captures (108–348 ns) likely represent captures where the oscilloscope trigger caught a slightly different phase of the SoT sequence.</strong> The fact that most captures show 0–4 ns means the LP-01/LP-00 states are being emitted but are too brief to resolve — consistent with the truncated THS_ZERO register value.</p>
<p>### 2b. LP-Low Plateau Bimodal Distribution</p>
<p>The LP-low plateau clusters at three values:<br>- <strong>0 ns</strong> — Capture 0322 (the confirmed flicker event)<br>- <strong>~108 ns</strong> — Several captures<br>- <strong>~343 ns</strong> — Most captures</p>
<p>This bimodal/trimodal distribution is characteristic of the scope trigger catching different points in the LP sequence. The 343 ns group likely includes THS_PREPARE + THS_ZERO combined. The 108 ns group sees only part of the sequence. The 0 ns capture (0322) represents the worst case where the LP-low phase was entirely absent — the PHY jumped directly from LP-11 to HS.</p>
<p>### 2c. HS Amplitude — Marginal with Below-140mV Samples on Every Capture</p>
<p>| Lane | Typical Amplitude | Below-140mV Samples |<br>|---|---|---|<br>| CLK | 165–167 mV | 8–146 per capture (persistent) |<br>| DAT0 | 186–200 mV | 2–11,786 per capture (highly variable) |</p>
<p>The clock lane amplitude at ~166 mV is only <strong>26 mV above the 140 mV floor</strong> — tight margin. Every single capture has sub-140mV samples on both lanes. The DAT0 lane shows extreme variability in sub-threshold sample count (2 to 11,786), indicating ISI (inter-symbol interference) is significant and data-pattern-dependent.</p>
<p>### 2d. Clock Lane Asymmetry</p>
<p>Consistent across all captures: positive swing ~194 mV, negative swing ~138 mV. The ~56 mV asymmetry and +28 mV common-mode offset suggest a DC bias issue (termination mismatch or probe ground offset). This doesn&#x27;t directly cause the flicker but reduces the effective differential eye opening.</p>
<p>### 2e. LP-11 Voltage: 1.015–1.017 V (Barely Passing)</p>
<p>Spec requires 1.0–1.45 V. At 1.016 V, the LP-11 level has <strong>only 16 mV of margin</strong> above the 1.0 V threshold. This is driven by the 1.8 V VDDIO through an internal resistor divider in the PHY — the low value is consistent with the measured VDDIO of ~1.766 V (1.8 V nominal minus ~34 mV). Not a direct flicker cause but reduces noise margin for LP state detection.</p>
<ul><li></li></ul>
<p>## 3. Trends Across Captures</p>
<p>### 3a. No Significant Drift<br>- <strong>CLK amplitude</strong>: 165.0–167.5 mV — rock stable<br>- <strong>DAT amplitude</strong>: 176.9–223.3 mV — data-dependent variation, no drift<br>- <strong>1.8V supply</strong>: 1.7645–1.7668 V mean — stable<br>- <strong>LP-11 voltage</strong>: 1.015–1.017 V — stable<br>- <strong>Jitter</strong>: 144–170 ps p-p — no trend<br>- <strong>Registers</strong>: Identical wrong values in every capture — no runtime corruption</p>
<p>### 3b. Supply Droop: Slight Increase Over Time<br>| Capture | Droop (mV) |<br>|---|---|<br>| 0305–0310 | 8.9–10.8 |<br>| 0317 | 12.5 |<br>| 0333 | <strong>17.8</strong> |</p>
<p>Capture 0333 shows the largest droop (17.8 mV) — still within spec but notable. This could indicate a transient load event. No correlation with flicker: the flicker capture (0322) had only 10.4 mV droop, entirely normal.</p>
<ul><li></li></ul>
<p>## 4. Supply-to-LP Correlation</p>
<p><strong>No correlation found between 1.8 V supply droop/ripple and LP timing violations.</strong></p>
<p>| Metric | Flicker capture (0322) | Batch average | Worst non-flicker |<br>|---|---|---|---|<br>| Droop | 10.4 mV | ~9.8 mV | 17.8 mV (0333) |<br>| Ripple RMS | 5.84 mV | ~5.73 mV | 5.98 mV (0324/0333) |<br>| LP exit | 0 ns | 3–348 ns | 1 ns (0319) |</p>
<p>The supply is clean and well within spec (min 1.748 V vs. 1.71 V floor). The flicker event occurred at a perfectly average supply condition. <strong>The supply is not the cause.</strong></p>
<ul><li></li></ul>
<p>## 5. Warning/Error Explanations</p>
<p>| Warning | Frequency | Cause | Action |<br>|---|---|---|---|<br>| &quot;LP exit duration N ns below spec min 50 ns&quot; | 22/28 captures | <strong>THS_ZERO register too low (6 vs. required 10)</strong> — PHY truncates LP-00/HS-0 preamble | Fix PHYTIMING2 register |<br>| &quot;Only negative swings in capture window&quot; | ~20/28 captures | Scope triggered during a run of identical bits (e.g., all-zeros in blanking data); only one polarity visible in narrow window | Not a real problem — data lane carries NRZ data |<br>| &quot;No HS signal detected&quot; on sig/dat | 4 captures | Scope high-res trigger caught LP or blanking period instead of active HS data | Normal for random-phase capture |<br>| &quot;CLK lane in continuous HS mode&quot; | All captures | Expected — DSI host runs CLK lane in continuous HS per SN65DSI83 requirement | Correct behaviour |<br>| &quot;388–11786 settled samples below 140 mV&quot; on DAT | All captures | ISI from truncated THS_ZERO causing incomplete eye opening + data-dependent pattern effects | Will improve when THS_ZERO is corrected |<br>| &quot;LP-11 → LP-low → HS transition not detected&quot; (0311) | 1 capture | Scope trigger missed the SoT window entirely | Trigger timing; not a device fault |<br>| &quot;index out of bounds&quot; (0328) | 1 capture | Analysis script buffer overflow — capture file truncated or trigger at edge of buffer | Re-capture or fix script bounds check |<br>| <strong>&quot;FLICKER SUSPECT: LP-low plateau absent&quot; (0322)</strong> | <strong>1 capture</strong> | <strong>Complete SoT failure — PHY jumped LP-11 → HS with zero LP-low dwell time</strong> | <strong>This is the confirmed flicker event</strong> |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### CRITICAL — Fix Immediately</p>
<p><strong>1. Correct the DSIM PHY timing registers to the target values:</strong></p>
<p>```<br># In device tree or driver init:<br>DSIM_PHYTIMING (0x32e100b4) = 0x00000306 # TLPX=3, THS_EXIT=6<br>DSIM_PHYTIMING1 (0x32e100b8) = 0x03110A04 # TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4<br>DSIM_PHYTIMING2 (0x32e100bc) = 0x00040A03 # THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3<br>```</p>
<p>The current driver is writing wrong values. Investigate:<br>- <strong>samsung-dsim / sec-dsim driver `phytiming` calculation</strong> — the driver&#x27;s auto-calculation from the bit rate is producing incorrect field values. The samsung-dsim driver in mainline Linux has known issues with timing calculation at certain bit rates. Check if `samsung,phy-timing` device tree property is being parsed or if the driver is overriding with computed values.<br>- <strong>Byte-clock rounding</strong> — at 432 Mbit/s, the byte clock (54 MHz) is relatively low and integer truncation in the driver&#x27;s `DIV_ROUND_UP` calculations can lose a full byte-clock unit on multiple fields simultaneously.<br>- <strong>Write ordering</strong> — verify registers are not being written before PLL lock, which would cause them to be ignored.</p>
<p><strong>2. Add register readback verification</strong> to your init sequence. After writing, read back 0xb4/0xb8/0xbc and abort/retry if mismatch. This catches both driver bugs and silicon erratum.</p>
<p>### HIGH — Implement Soon</p>
<p><strong>3. Increase THS_ZERO to 12 (222 ns)</strong> instead of the minimum-compliant 10 (185 ns). This adds 37 ns of margin to the SoT detection window, changing the bridge&#x27;s metastability probability from ~3% to effectively zero. The cost is ~37 ns added to each line&#x27;s HS entry — negligible at 72 MHz pixel clock.</p>
<p><strong>4. Increase TCLK_ZERO to 19 (352 ns)</strong> for similar margin on clock lane PLL acquisition.</p>
<p><strong>5. Verify all 4 data lanes</strong> — you are only measuring DAT0. If the register error affects all lanes equally (it does — these are global PHY timing registers), all lanes have truncated SoT. But lane-to-lane skew could cause one lane to fail SoT while others pass, which the SN65DSI83 would interpret as a protocol error.</p>
<p>### MODERATE — Improve Robustness</p>
<p><strong>6. LP-11 voltage margin</strong>: The 1.016 V LP-11 level has only 16 mV margin. Consider verifying the VDDIO path — check for excessive resistance in the 1.8 V trace to the PHY VDDIO pin. A 34 mV drop from 1.8 V nominal suggests ~19 mA × 1.8 Ω or similar parasitic.</p>
<p><strong>7. Clock lane common-mode offset</strong> (+28 mV): Check for asymmetric PCB trace lengths or termination resistor tolerance on the CLK± pair. Not urgent but indicates a board-level asymmetry.</p>
<p><strong>8. Add a retry mechanism</strong> to the display pipeline init: if the bridge&#x27;s status register (SN65DSI83 register 0x0E, CHA_STS) shows errors after init, automatically unload and reload the pipeline. This provides a software safety net until the register fix is validated.</p>
<ul><li></li></ul>
<p>## 7. Summary</p>
<p><strong>The flicker root cause is definitively identified: all three DSIM PHY timing registers are programmed with values below D-PHY v1.1 minimums</strong> (THS_ZERO shorted by 57 ns, TCLK_ZERO by 41 ns, TCLK_TRAIL and THS_TRAIL both below spec). This truncates the LP→HS Start-of-Transmission sequence, creating a narrow metastable detection window in the SN65DSI83 bridge that fails ~3% of the time at pipeline load. The 1.8 V supply, HS amplitudes, and LP-11 voltages are all within spec and uncorrelated with flicker events.</p>
<p><strong>Fix the three PHY timing registers to their target values (PHYTIMING=0x306, PHYTIMING1=0x03110A04, PHYTIMING2=0x00040A03) and the flicker will be eliminated.</strong> The driver&#x27;s auto-calculation logic for 432 Mbit/s is the bug — override with explicit device-tree timing values or patch the calculation.</p>
<p class="tokens">Tokens: 32357 in / 4004 out</p>
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