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<title>MIPI Analysis — Captures 0635–0664</title>
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<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 1 of 30 display load sessions (3%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0646</td><td>20260409_153801</td><td>dat</td><td style='color:red'>1.0 ns</td><td>0.1 ns</td><td>1.015 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0635</td><td>20260409_153403</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0636</td><td>20260409_153425</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0637</td><td>20260409_153446</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0638</td><td>20260409_153508</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0639</td><td>20260409_153529</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0640</td><td>20260409_153551</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0641</td><td>20260409_153612</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0642</td><td>20260409_153634</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0643</td><td>20260409_153656</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0644</td><td>20260409_153717</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0645</td><td>20260409_153739</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0646</td><td>20260409_153801</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0647</td><td>20260409_153823</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0648</td><td>20260409_153844</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0649</td><td>20260409_153906</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0650</td><td>20260409_153928</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0651</td><td>20260409_153950</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0652</td><td>20260409_154011</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0653</td><td>20260409_154033</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0654</td><td>20260409_154055</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0655</td><td>20260409_154116</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0656</td><td>20260409_154138</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0657</td><td>20260409_154200</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0658</td><td>20260409_154222</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0659</td><td>20260409_154243</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0660</td><td>20260409_154305</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0661</td><td>20260409_154327</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0662</td><td>20260409_154349</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0663</td><td>20260409_154410</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0664</td><td>20260409_154432</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-09 15:49:15 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0635–0664 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664</p>
<ul><li></li></ul>
<p>## 1. Register Mismatch: The Primary Root Cause</p>
<p>### Actual vs. Target Register Values</p>
<p>| Register | Target | Actual (all captures) | Impact |<br>|---|---|---|---|<br>| <strong>PHYTIMING (0xb4)</strong> | `0x00000306` | `0x00000305` | <strong>THS_EXIT=5 → 92.6 ns</strong> (spec ≥100 ns) <strong>✗</strong> |<br>| <strong>PHYTIMING1 (0xb8)</strong> | `0x03110A04` | `0x020e0a03` | <strong>TCLK_PREPARE=2 → 37 ns</strong> (spec 38–95 ns) <strong>✗</strong>, <strong>TCLK_ZERO=14 → 259 ns</strong> (spec ≥300 ns) <strong>✗</strong>, <strong>TCLK_TRAIL=3 → 55.6 ns</strong> (spec ≥60 ns) <strong>✗</strong> |<br>| <strong>PHYTIMING2 (0xbc)</strong> | `0x00040A03` | `0x00030605` | <strong>THS_PREPARE=5 → 92.6 ns</strong> (spec 40+4×UI = 49.3–99.3 ns) ✓ but high, <strong>THS_ZERO=6 → 111 ns</strong> (spec ≥145+10×UI = 168.1 ns) <strong>✗</strong>, <strong>THS_TRAIL=3 → 55.6 ns</strong> (spec max(8×UI, 60ns+4×UI) = 69.3 ns) <strong>✗</strong> |</p>
<p><strong>Every single capture shows the wrong register values.</strong> The driver is not applying the target timing. This is the systematic root cause of all LP/SoT violations.</p>
<p>### Critical Decoded Field Comparison</p>
<p>| Field | Target (byte-clk) | Actual (byte-clk) | Target (ns) | Actual (ns) | Spec Min (ns) | Verdict |<br>|---|---|---|---|---|---|---|<br>| TLPX | 3 | 3 | 55.6 | 55.6 | 50 | ✓ |<br>| THS_EXIT | 6 | 5 | 111 | 92.6 | 100 | <strong>✗ FAIL</strong> |<br>| TCLK_PREPARE | 3 | 2 | 55.6 | 37.0 | 38 | <strong>✗ FAIL</strong> |<br>| TCLK_ZERO | 17 | 14 | 315 | 259 | 300 | <strong>✗ FAIL</strong> |<br>| TCLK_POST | 10 | 10 | 185 | 185 | 180 | ✓ (marginal) |<br>| TCLK_TRAIL | 4 | 3 | 74 | 55.6 | 60 | <strong>✗ FAIL</strong> |<br>| THS_PREPARE | 3 | 5 | 55.6 | 92.6 | 49.3 | ✓ (but over-programmed) |<br>| THS_ZERO | 10 | 6 | 185 | 111 | 168.1 | <strong>✗ FAIL</strong> |<br>| THS_TRAIL | 4 | 3 | 55.6 | 55.6 | 69.3 | <strong>✗ FAIL</strong> |</p>
<p><strong>Six of nine timing parameters violate the MIPI D-PHY v1.1 specification.</strong> The registers are static across all 30 captures — the driver is consistently programming wrong values, likely because the samsung-dsim driver is computing timings from a formula rather than using the device-tree overrides you intended.</p>
<ul><li></li></ul>
<p>## 2. LP→HS SoT Analysis: Two Distinct Populations</p>
<p>### LP-Low Plateau Distribution</p>
<p>| LP-low plateau | Count | LP exit→HS | HS amplitude (SE) | Interpretation |<br>|---|---|---|---|---|<br>| <strong>~343 ns</strong> | 11 captures | 2–348 ns | 17–122 mV | Normal SoT — LP-01→LP-00 sequence present |<br>| <strong>~108 ns</strong> | 13 captures | 0–113 ns | 20–42 mV | Truncated SoT — LP states compressed |<br>| <strong>1 ns</strong> | <strong>1 capture (0646)</strong> | <strong>0 ns</strong> | 122 mV | <strong>SoT absent — FLICKER</strong> |<br>| Not detected | 3 captures (0636, 0652, 0660) | — | — | Trigger/capture missed transition entirely |</p>
<p><strong>Key observation:</strong> There is a clear bimodal distribution — ~343 ns vs ~108 ns. The flicker capture (0646) represents the extreme tail where the LP-low state is essentially absent (1 ns). This is a <strong>race condition</strong>, not a supply problem.</p>
<p>### Correlation with HS Amplitude</p>
<p>The 108 ns group consistently shows <strong>very low HS amplitude</strong> (20–42 mV single-ended, i.e. ~40–84 mV differential) during the first HS burst, well below the 140 mV minimum. This suggests:<br>- The 108 ns captures are catching DAT0 during or near a <strong>blanking interval</strong> where the line is in LP-idle or low-power, and the scope sees only the HS ramp-up/ramp-down transient.<br>- The 343 ns captures with high HS amplitude (106–122 mV SE ≈ 212–244 mV differential) are capturing active video data.</p>
<p>The difference between the two populations is <strong>which exact byte-clock edge the SoT lands on relative to the PHY state machine</strong> — this is the non-deterministic element.</p>
<ul><li></li></ul>
<p>## 3. Why Capture 0646 Flickered</p>
<p>Capture 0646 is the extreme case of the 108 ns population pushed to its limit:<br>- <strong>LP-low plateau: 1 ns</strong> — essentially zero. The LP-01→LP-00 SoT entry states are completely absent.<br>- <strong>LP exit→HS: 0 ns</strong> — the data lane jumps directly from LP-11 to HS differential signalling.<br>- <strong>HS amplitude: 122 mV SE (244 mV diff)</strong> — strong signal, so the PHY *did* enter HS mode.<br>- <strong>14,588 proto/dat samples below 140 mV</strong> — massively elevated, confirming the bridge saw corrupted/unsynchronized HS data.</p>
<p><strong>The SN65DSI83 requires a valid LP-11 → LP-01 → LP-00 → HS-0 entry sequence</strong> (per MIPI D-PHY spec, Section 5.1). When this sequence is absent:<br>1. The bridge&#x27;s clock-data training fails.<br>2. It cannot lock onto the HS byte boundary.<br>3. All subsequent video data is interpreted as garbage.<br>4. The bridge stays stuck in this state for the entire session because the CLK lane is in <strong>continuous HS mode</strong> (never returns to LP to re-attempt SoT).</p>
<p>### Why it&#x27;s non-deterministic</p>
<p>The too-short THS_ZERO (111 ns actual vs 168 ns required) and THS_PREPARE (already at the high end) create a window where the combined THS_PREPARE+THS_ZERO duration (204 ns actual vs 217 ns minimum) is <strong>violated</strong>. The PHY state machine exit from LP depends on:<br>1. Phase alignment between the byte clock and the LP state counter<br>2. PLL lock timing at startup<br>3. Internal flip-flop metastability in the LP-to-HS crossover logic</p>
<p>With only ~204 ns total vs ~217 ns required, the margin is <strong>negative 13 ns</strong>. Most of the time the PHY &quot;gets away with it&quot; because internal delays pad the timing. Occasionally (3% of startups), the timing lands in the metastable window and the LP-01/LP-00 states are completely skipped.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Assessment</p>
<p>| Parameter | Range across all captures | Correlation with flicker? |<br>|---|---|---|<br>| Mean 1.8 V | 1.7633–1.7688 V | No — all within spec, no trend |<br>| Min voltage | 1.7480–1.7600 V | No — 0646 min=1.7520 V, identical to non-flicker captures |<br>| Droop depth | 7.6–16.1 mV | No — 0646 droop=11.6 mV, median of the distribution |<br>| Ripple RMS | 4.99–5.95 mV | No — 0646 ripple=5.45 mV, average |</p>
<p><strong>Conclusion: The 1.8 V supply is NOT the cause.</strong> Droop and ripple show no correlation with LP timing violations or flicker events. The supply is stable and well within spec. The LP-11 voltage (1.012–1.016 V) is at the very bottom of the 1.0–1.45 V spec window — consistent with a 1.8 V rail that&#x27;s 2% low — but this is not causing the SoT failure.</p>
<ul><li></li></ul>
<p>## 5. Explanation of Warnings and Errors</p>
<p>| Warning/Error | Count | Likely Cause | Action |<br>|---|---|---|---|<br>| <strong>LP exit duration 0–4 ns below 50 ns</strong> | 23/27 LP captures | <strong>THS_ZERO and TCLK_ZERO under-programmed</strong> — LP-01/LP-00 states are too brief for the scope to resolve at its sample rate, or the PHY genuinely skips them | Fix registers (primary action) |<br>| <strong>CLK lane in continuous HS mode</strong> | All captures | Expected — samsung-dsim runs CLK in continuous HS for video mode panels. Not an error. | Informational only |<br>| <strong>Only negative swings in capture window</strong> | ~20 captures | Scope triggered on a specific data pattern; differential probe captured only one polarity of HS transitions in the narrow sig window. Common for short bursts. | Not a hardware issue — capture artifact |<br>| <strong>No HS signal on dat (sig)</strong> | 3 captures (0636, 0641, 0648) | Sig capture window missed the HS burst — timing jitter in trigger vs data phase | Not a hardware issue |<br>| <strong>index 200000 out of bounds</strong> | 2 captures (0636, 0652) | LP capture buffer exactly full — trigger timing placed the SoT at the buffer boundary | Increase capture depth or adjust trigger position |<br>| <strong>Samples below 140 mV (proto/dat)</strong> | All captures | ISI and transition regions in HS data naturally dip below 140 mV. The 10,000+ counts in captures 0646, 0647, 0652, 0655 suggest <strong>data-dependent jitter</strong> or pattern sensitivity at these margins | Addressed by fixing THS_ZERO to give the receiver more setup time |<br>| <strong>LP-11 → LP-low → HS not detected (0660)</strong> | 1 capture | Trigger fired but no LP transition in the capture window — missed the SoT event entirely | Not a hardware issue — adjust trigger |<br>| <strong>Capture 0649: LP-11 duration 4.99 µs</strong> (vs 1.73 µs typical) | 1 capture | Longer LP-11 idle period before first SoT — likely a software timing variation in display pipeline startup | Informational — no impact |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### CRITICAL — Fix Immediately</p>
<p><strong>1. Apply correct PHY timing registers.</strong></p>
<p>The samsung-dsim driver is computing its own timings and ignoring your target values. You must force the correct values:</p>
<p>```<br>PHYTIMING (0xb4): 0x00000306 → TLPX=3, THS_EXIT=6<br>PHYTIMING1 (0xb8): 0x03110A04 → TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4<br>PHYTIMING2 (0xbc): 0x00040A03 → THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3<br>```</p>
<p><strong>Options to force this:</strong><br>- <strong>Option A (preferred):</strong> Patch the `samsung_dsim_set_phy_timing()` function in `drivers/gpu/drm/bridge/samsung-dsim.c` to use hardcoded values for your bit rate. The driver currently calculates timings using a formula that does not account for the minimum spec values at 432 Mbit/s.<br>- <strong>Option B:</strong> Add a post-init register write via `devmem2` or a custom script after `modprobe` — fragile but validates the fix.<br>- <strong>Option C:</strong> Modify the device tree `phy-timing` properties if your driver version supports them (check for `samsung,phy-timing` bindings).</p>
<p><strong>2. Increase THS_ZERO further for margin.</strong></p>
<p>Even the target value of 10 (185 ns) only gives 17 ns margin over the 168 ns minimum. Consider THS_ZERO=12 (222 ns) for robust margin against PVT variation:<br>```<br>PHYTIMING2 (0xbc): 0x00040C03 → THS_ZERO=12<br>```</p>
<p><strong>3. Increase TCLK_ZERO for margin.</strong></p>
<p>Target of 17 (315 ns) over 300 ns minimum gives only 15 ns margin. Consider TCLK_ZERO=19 (352 ns):<br>```<br>PHYTIMING1 (0xb8): 0x03130A04 → TCLK_ZERO=19<br>```</p>
<p>### IMPORTANT — Verify After Fix</p>
<p><strong>4. Verify register values are applied.</strong></p>
<p>After every pipeline load, read back registers with `memtool md -l 0x32e100b4+0x0c` and confirm they match target values. The current data proves they don&#x27;t — <strong>100% of 30 captures show wrong values</strong>.</p>
<p><strong>5. Re-run the 30-cycle flicker test</strong> with correct registers and confirm:<br>- LP-low plateau consistently ≥200 ns<br>- LP exit→HS consistently ≥50 ns<br>- No bimodal distribution (should be a single population near ~340 ns)<br>- Zero flicker events</p>
<p>### MONITORING — Track These Metrics</p>
<p><strong>6. The LP-11 voltage of 1.015 V is at the spec floor (1.0 V).</strong></p>
<p>While not causing the flicker, this leaves zero margin. The LP-11 voltage is set by the VDDIO supply (1.765 V) and the PHY&#x27;s internal LP driver, which divides VDDIO roughly in half plus series resistance. If VDDIO drifts lower (temperature, load transients), LP-11 could go below 1.0 V. Consider:<br>- Verifying VDDIO regulation target is exactly 1.8 V (currently 2% low at 1.764 V)<br>- Checking if the SOM has a VDDIO trim resistor that can be adjusted</p>
<p><strong>7. The HS clock common mode offset of +13–15 mV</strong> is within spec (±25 mV) but consistently positive. This indicates a slight impedance mismatch on CLK+ vs CLK−. Check:<br>- Trace length matching between CLK+ and CLK− (target ≤2 mil difference)<br>- AC coupling capacitor tolerance matching</p>
<ul><li></li></ul>
<p>## 7. Summary</p>
<p><strong>The intermittent flicker is caused by incorrect DSIM PHY timing register values.</strong> All 30 captures show `PHYTIMING1=0x020e0a03` and `PHYTIMING2=0x00030605` instead of the target values, resulting in six out of nine D-PHY timing parameters violating the MIPI spec. The most critical violations — THS_ZERO at 111 ns (spec ≥168 ns) and TCLK_ZERO at 259 ns (spec ≥300 ns) — create a negative timing margin that causes the LP→HS SoT entry sequence to be non-deterministically truncated or skipped entirely. When the SoT is completely absent (as in capture 0646, LP-low=1 ns), the SN65DSI83 cannot lock onto the HS data stream and the display flickers for the entire session.</p>
<p><strong>The fix is straightforward: force the correct register values into the samsung-dsim driver.</strong> The supply rail, HS signal quality, and board-level signal integrity are all acceptable and are not contributing to the failure. Once correct timings are programmed, the 3% flicker rate should drop to zero.</p>
<p class="tokens">Tokens: 33025 in / 4080 out</p>
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