Updates

analyze_captures.py

@@ -29,6 +29,60 @@ from csv_preprocessor import (
 DATA_DIR    = Path(__file__).parent / "data"
 REPORTS_DIR = Path(__file__).parent / "reports"
 
+# ---------------------------------------------------------------------------
+# Confirmed device configuration — update here if hardware changes
+# ---------------------------------------------------------------------------
+# Derived values (do not edit — calculated from the constants above):
+#   HS bit rate  = PIXEL_CLK_MHZ × COLOR_DEPTH_BPP / DSI_LANES
+#               = 72 × 24 / 4 = 432 Mbit/s per lane
+#   HS bit UI   = 1 / 432e6   ≈ 2.315 ns
+#   Byte clock  = 432 / 8     = 54 MHz  → 18.518 ns/byte
+#
+# MIPI D-PHY v1.1 minimum timings at 432 Mbit/s:
+#   T_LPX       ≥ 50 ns
+#   T_HS-PREPARE  40+4·UI → 85+6·UI  = 49.3–98.9 ns
+#   T_HS-ZERO   ≥ 145+10·UI          = 168.2 ns
+#   T_HS-TRAIL  ≥ max(8·UI, 60+4·UI) = 69.3 ns
+#   T_HS-EXIT   ≥ 100 ns
+#   T_CLK-PREPARE 38–95 ns
+#   T_CLK-ZERO  ≥ 300 ns
+#   T_CLK-POST  ≥ 60+52·UI           = 180.4 ns
+#   T_CLK-TRAIL ≥ 60 ns
+#
+# In byte-clock units (÷ 18.518 ns, round up):
+#   TLPX         = 3   (55.6 ns)
+#   THS_PREPARE  = 3   (55.6 ns — within 49.3–98.9 ns window)
+#   THS_ZERO     = 10  (185.2 ns ≥ 168.2 ns ✓)
+#   THS_TRAIL    = 4   (74.1 ns ≥ 69.3 ns ✓)
+#   THS_EXIT     = 6   (111.1 ns ≥ 100 ns ✓)
+#   TCLK_PREPARE = 3   (55.6 ns — within 38–95 ns ✓)
+#   TCLK_ZERO    = 17  (314.8 ns ≥ 300 ns ✓)
+#   TCLK_POST    = 10  (185.2 ns ≥ 180.4 ns ✓)
+#   TCLK_TRAIL   = 4   (74.1 ns ≥ 60 ns ✓)
+DEVICE_CONFIG = {
+    "dsi_host":         "NXP i.MX 8M Mini (Samsung DSIM IP, sec-dsim/samsung-dsim driver)",
+    "dsi_bridge":       "Texas Instruments SN65DSI83 (MIPI-to-LVDS)",
+    "pixel_clock_mhz":  72,
+    "dsi_lanes":        4,
+    "color_format":     "RGB888 (24 bpp)",
+    "hs_bit_rate_mbps": 432,    # 72 × 24 / 4
+    "hs_ui_ns":         2.315,  # 1 / 432e6
+    "byte_clock_mhz":   54,     # 432 / 8
+    "byte_period_ns":   18.518,
+    "vddio_v":          1.8,
+    # Correct DSIM PHY timing register values (byte-clock units, see derivation above)
+    # Samsung DSIM field mapping (sec_mipi_dsim.c / samsung-dsim.c):
+    #   PHYTIMING  (0xb4): [15:8]=TLPX,         [7:0]=THS_EXIT
+    #   PHYTIMING1 (0xb8): [31:24]=TCLK_PREPARE, [23:16]=TCLK_ZERO,
+    #                      [15:8]=TCLK_POST,     [7:0]=TCLK_TRAIL
+    #   PHYTIMING2 (0xbc): [23:16]=THS_TRAIL,    [15:8]=THS_ZERO, [7:0]=THS_PREPARE
+    "dsim_phytiming_target": {
+        "PHYTIMING  (0xb4)": "0x00000306  (TLPX=3→55.6ns, THS_EXIT=6→111ns)",
+        "PHYTIMING1 (0xb8)": "0x03110A04  (TCLK_PREPARE=3, TCLK_ZERO=17→315ns, TCLK_POST=10→185ns, TCLK_TRAIL=4→74ns)",
+        "PHYTIMING2 (0xbc)": "0x00040A03  (THS_TRAIL=4→74ns, THS_ZERO=10→185ns, THS_PREPARE=3→56ns)",
+    },
+}
+
 CLAUDE_MODEL   = "claude-opus-4-6"
 SYSTEM_PROMPT  = (
     "You are an expert in MIPI D-PHY signal integrity analysis. "
@@ -41,11 +95,10 @@ SYSTEM_PROMPT  = (
     "lp (single-ended LP-11/LP-00/HS burst including SoT sequence), "
     "pwr (1.8 V supply captured during the LP→HS transition), "
     "and reg (DSIM register snapshot — DSIM_PHYTIMING at 0x32e100b4, "
-    "DSIM_PHYTIMING1 at 0xb8, DSIM_PHYTIMING2 at 0xbc control LP state durations "
+    "DSIM_PHYTIMING1 at 0xb8, DSIM_PHYTIMING2 at 0xbc control LP/HS state durations; "
-    "and PHY clock timing; DSIM_CLKCTRL at 0x08 and DSIM_ESCMODE at 0x14 affect "
+    "timing fields are in byte-clock units where 1 unit = 18.518 ns at 432 Mbit/s). "
-    "LP escape mode and HS entry sequencing). "
     "Analyse the data for trends, degradation, anomalies, or consistent spec concerns "
-    "across captures. Correlate register values with observed LP timing violations. "
+    "across captures. Correlate register field values with observed LP timing violations. "
     "Be concise and actionable."
 )
 
@@ -148,6 +201,23 @@ def process_capture(
 
 def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
                  flicker_count: int = 0, total_sessions: int = 0) -> str:
+    cfg = DEVICE_CONFIG
+    target = cfg["dsim_phytiming_target"]
+    config_section = (
+        f"Device under test:\n"
+        f"  DSI host:        {cfg['dsi_host']}\n"
+        f"  DSI bridge:      {cfg['dsi_bridge']}\n"
+        f"  Pixel clock:     {cfg['pixel_clock_mhz']} MHz\n"
+        f"  DSI lanes:       {cfg['dsi_lanes']} data lanes\n"
+        f"  Color format:    {cfg['color_format']}\n"
+        f"  HS bit rate:     {cfg['hs_bit_rate_mbps']} Mbit/s per lane\n"
+        f"  HS UI:           {cfg['hs_ui_ns']:.3f} ns\n"
+        f"  Byte clock:      {cfg['byte_clock_mhz']} MHz ({cfg['byte_period_ns']:.3f} ns/byte)\n"
+        f"  VDDIO:           {cfg['vddio_v']} V\n"
+        f"  Correct DSIM PHY timing register targets (byte-clock units):\n"
+        + "\n".join(f"    {k}: {v}" for k, v in target.items())
+    )
+
     body = "\n\n".join(all_summaries)
 
     flicker_section = ""
@@ -177,11 +247,13 @@ def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
         "Below are pre-processed summaries of MIPI D-PHY captures from a Digi ConnectCore "
         "8M Mini SOM (NXP i.MX 8M Mini) driving a SN65DSI83 MIPI-to-LVDS bridge. "
         "The system occasionally flickers at display pipeline load. "
-        "Each capture has up to four data sets per lane (CLK and DAT0):\n"
+        "Each capture has up to five data sets per lane (CLK and DAT0):\n"
         "  sig   — high-res HS differential (rise/fall times)\n"
         "  proto — long-window HS differential (jitter, clock freq, amplitude)\n"
         "  lp    — single-ended LP state capture at pipeline startup (LP-11, SoT sequence, HS bursts)\n"
         "  pwr   — 1.8 V supply rail captured during LP→HS transition (droop, ripple, spec)\n"
+        "  reg   — DSIM PHY timing register snapshot from running device\n"
+        f"\n{config_section}\n"
         f"{flicker_section}\n"
         f"{body}\n\n"
         "Please:\n"