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 <title>MIPI Analysis — Captures 0137–0166</title>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 2 of 30 display load sessions (7%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0137</td><td>20260415_074230</td><td>dat</td><td style='color:red'>0.3 ns</td><td>1.3 ns</td><td>1.015 V</td></tr><tr><td>0147</td><td>20260415_074608</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0137</td><td>20260415_074230</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0138</td><td>20260415_074252</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260415_074314</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260415_074336</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260415_074357</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260415_074419</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260415_074441</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260415_074503</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260415_074524</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260415_074546</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260415_074608</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260415_074630</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260415_074651</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260415_074713</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260415_074735</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260415_074757</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260415_074818</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260415_074840</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260415_074902</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260415_074923</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260415_074945</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260415_075007</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260415_075029</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260415_075051</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260415_075113</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260415_075135</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260415_075156</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260415_075218</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260415_075239</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260415_075301</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 07:57:44 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0137–0166 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166</p>
 <p>## 1. Consistent Spec Concerns</p>
 <p>### Register-Level Timing Violations (100% of captures)<br>Every single capture shows identical register values — the system is running <strong>&#x27;Round Best&#x27; mode</strong> with 5 D-PHY v1.1 violations:</p>
 <p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|-----------|-----------|--------|----------|-----------|<br>| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
 <p>These are not marginal — they are <strong>hardcoded violations</strong>. The byte-clock granularity (18.518 ns) means every field is either clearly below spec or clearly above; there is no jitter-induced ambiguity in the register domain.</p>
 <p>### LP-Exit Timing (Universal Violation)<br><strong>Every capture with valid LP data</strong> (28 of 28) shows LP exit → HS duration of <strong>0–4 ns</strong> against a spec minimum of <strong>50 ns</strong>. This is a <strong>systematic hardware/driver issue</strong>, not a measurement artefact. The LP-01 and LP-00 SoT entry states are being driven for sub-nanosecond durations at the single-ended measurement resolution.</p>
 <p>### LP-11 Voltage<br>All captures: <strong>1.013–1.016 V</strong> against spec 1.0–1.45 V. Technically passing, but sitting at the <strong>extreme low end</strong> — only 13–16 mV above the 1.0 V floor. This is consistent with the 1.8 V supply being at 1.765 V (low side of nominal) and the PHY LP driver having significant drop. A marginal LP-11 voltage reduces the SN65DSI83&#x27;s noise margin for detecting the LP-11 → LP-01 → LP-00 transition.</p>
 <p>### HS Amplitude<br>- <strong>CLK lane</strong>: 161–173 mV differential — consistently passes 140 mV minimum but only by ~25 mV. Negative swing systematically weaker (+193 mV / −138 mV asymmetry → ~28 mV common-mode offset).<br>- <strong>DAT0 lane</strong>: 177–199 mV when properly captured — adequate but numerous sub-140 mV samples in proto captures (25–5098 per capture), indicating ISI/pattern-dependent amplitude dips.</p>
 <p>### Clock Frequency<br>Mostly 215.6–216.2 MHz as expected. Occasional readings of 213.0–213.4 MHz and 218.1–219.1 MHz are within proto measurement window artefacts (windowing/gating), not real frequency excursions.</p>
 <ul><li></li></ul>
 <p>## 2. Trends Across Captures</p>
 <p>### LP-Low Plateau Duration — The Critical Discriminator</p>
 <p>| LP-Low Plateau | Count | Captures | Flicker? |<br>|---------------|-------|----------|----------|<br>| <strong>0 ns</strong> | 2 | 0137★, 0147★ | <strong>YES — both flicker events</strong> |<br>| <strong>108 ns</strong> | 5 | 0142, 0153, 0158, 0160, 0166 | No |<br>| <strong>342–343 ns</strong> | 19 | All others | No |<br>| <strong>348 ns</strong> (LP exit also ≥ 348 ns) | 4 | 0143, 0144, 0150, 0156, 0161 | No |<br>| <strong>Error/missing</strong> | 2 | 0148, 0162 | Unknown |</p>
 <p><strong>Key finding</strong>: The LP-low plateau is <strong>tristable</strong> — it lands at ~0, ~108, or ~343 ns. The flicker events correspond <strong>exclusively</strong> to the 0 ns case, where the LP-01/LP-00 states are completely absent. The 108 ns captures are a partial SoT (approximately 6 byte-clocks — coincidentally close to THS_PREPARE+THS_ZERO = 9 bc) and are borderline but do not flicker in this batch. The 343 ns captures show a healthy SoT sequence.</p>
 <p>This tristability is the <strong>smoking gun</strong>: the PHY&#x27;s internal SoT state machine has a race condition. The programmed THS_PREPARE+THS_ZERO (166.7 ns, 1.5 ns below spec) and TCLK_PREPARE+TCLK_ZERO (296.3 ns, 3.7 ns below spec) are below the minimum required for the receiver to detect the SoT sequence. When internal PLL/clock alignment at startup happens to compress these states further (or the state machine skips them entirely), the bridge never detects SoT.</p>
 <p>### HS Amplitude — No Drift<br>CLK and DAT0 amplitudes are rock-stable across all 30 captures. No thermal or aging drift.</p>
 <p>### Jitter — Stable<br>CLK jitter: 142–172 ps p-p, 50–53 ps RMS. No trend. Well within typical D-PHY budgets.</p>
 <p>### 1.8 V Supply — Stable, No Correlation<br>Mean: 1.764–1.766 V. Droop: 8.5–14.1 mV. Ripple RMS: 5.3–5.9 mV. All within spec.</p>
 <ul><li></li></ul>
 <p>## 3. Anomalies</p>
 <p>### A. Two Flicker Events (Captures 0137, 0147)<br>- <strong>LP-low plateau = 0 ns</strong> — LP-01/LP-00 states completely absent<br>- LP exit → HS = 1–2 ns (essentially instantaneous)<br>- HS amplitude in LP capture window: <strong>25–30 mV</strong> single-ended (vs. 106–119 mV in non-flicker captures)<br>- This ultra-low HS amplitude confirms the bridge <strong>never locked</strong> — it is seeing HS transitions but has not synchronised because SoT was never received</p>
 <p>### B. Intermediate LP-Low (~108 ns) Captures (0142, 0153, 0158, 0160, 0166)<br>- LP-low is present but <strong>shortened by ~3×</strong> compared to normal (~343 ns)<br>- HS amplitude in LP window: 16–35 mV (same low range as flicker captures)<br>- These are <strong>near-misses</strong> — the SoT sequence exists but is abbreviated. The bridge manages to lock, but barely. With a less tolerant bridge or slightly different timing, these would flicker too.</p>
 <p>### C. LP Data Processing Errors (Captures 0148, 0162)<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP transition occurred at or beyond the capture window edge. These represent captures where the trigger timing placed the SoT at the buffer boundary. Not a hardware fault; increase capture depth or adjust trigger delay.</p>
 <p>### D. DAT0 &quot;Only Negative Swings&quot; (Majority of sig/dat captures)<br>Approximately 70% of sig/dat captures show only negative-going differential transitions. This is a <strong>capture window alignment issue</strong> — the high-res window is short enough that it may only contain one data phase. Not a real signal fault, but it means the positive-swing amplitude is not being validated for most captures. Recommend widening the sig capture window or using edge-triggered dual-window acquisition.</p>
 <p>### E. DAT0 sig = 0.0 mV (Captures 0138, 0140, 0150, 0151, 0158, 0164)<br>The data line was in LP idle or between bursts during the high-res capture. Again a trigger alignment issue.</p>
 <ul><li></li></ul>
 <p>## 4. Supply Correlation Analysis</p>
 <p>| Metric | Flicker (0137, 0147) | No-Flicker (avg of rest) | Correlation? |<br>|--------|---------------------|-------------------------|-------------|<br>| V_mean | 1.7656, 1.7655 V | 1.7652 V | <strong>None</strong> |<br>| V_min | 1.756, 1.756 V | 1.754 V | <strong>None</strong> |<br>| Droop | 9.6, 9.5 mV | 10.1 mV | <strong>None</strong> |<br>| Ripple RMS | 5.59, 5.49 mV | 5.59 mV | <strong>None</strong> |</p>
 <p><strong>Conclusion: The 1.8 V supply is not the root cause.</strong> Droop and ripple are identical in flicker and non-flicker sessions. The supply is healthy and not contributing to the SoT failure.</p>
 <p>The slightly low LP-11 voltage (1.015 V) is a <strong>constant</strong> across all captures and therefore cannot explain the intermittent behaviour. However, it does reduce the SN65DSI83&#x27;s detection margin, making the system more sensitive to the SoT timing violations.</p>
 <ul><li></li></ul>
 <p>## 5. WARNING/ERROR Explanation</p>
 <p>| Warning | Cause | Action |<br>|---------|-------|--------|<br>| `LP exit duration N ns below spec min 50 ns` | PHY is not holding LP-01/LP-00 states for the required TLPX duration. The samsung-dsim PHY programmes TLPX=3 bc (55.6 ns) but the actual LP-low state exits in 0–4 ns. This means the LP driver is being overridden by the HS driver prematurely — a <strong>PHY state machine race</strong>. | Switch to &#x27;Round Up&#x27; register values |<br>| `FLICKER SUSPECT: LP-low plateau absent` | SoT LP-01→LP-00 sequence completely skipped | Root cause — see §6 |<br>| `Only negative swings in capture window` | Sig capture window too short / trigger phase alignment | Widen sig window or add trigger holdoff jitter |<br>| `No HS signal detected` | Sig capture window hit LP gap between bursts | Same as above |<br>| `N settled samples below 140 mV` | ISI-induced amplitude dips during data transitions | Expected at 432 Mbit/s with PCB trace losses; not a primary concern but monitor |<br>| `index 200000 out of bounds` | LP transition at capture buffer edge | Increase LP capture depth to 250k+ samples |<br>| `CLK lane in continuous HS mode` | Normal — continuous clock mode; CLK LP→HS happens once at startup and is not re-triggered per frame | Expected behaviour |</p>
 <ul><li></li></ul>
 <p>## 6. Actionable Recommendations</p>
 <p>### CRITICAL — Fix #1: Switch to &#x27;Round Up&#x27; PHY Timing Registers</p>
 <p>This is the <strong>single change</strong> most likely to eliminate flicker. Patch the samsung-dsim driver (or device tree) to use:</p>
 <p>```<br>PHYTIMING  (0xb4): 0x00000306   (THS_EXIT=6 → 111.1 ns ✓)<br>PHYTIMING1 (0xb8): 0x030f0a04   (TCLK_PREPARE=3→55.6ns ✓, TCLK_ZERO=15, TCLK_TRAIL=4→74.1ns ✓)<br>PHYTIMING2 (0xbc): 0x00030706   (THS_ZERO=7, THS_TRAIL=6→111.1ns ✓)<br>```</p>
 <p>This eliminates all 5 D-PHY violations and gives:<br>- TCLK_PREPARE+TCLK_ZERO = 333 ns (33 ns margin over 300 ns spec)<br>- THS_PREPARE+THS_ZERO = 185 ns (17 ns margin over 168 ns spec)</p>
 <p>The additional margin will <strong>eliminate the race condition</strong> that causes the tristable LP-low plateau (0/108/343 ns) by ensuring the PHY state machine always completes the full SoT sequence before the HS driver engages.</p>
 <p><strong>Implementation</strong>: In the samsung-dsim (sec-dsim) driver, the timing calculation function (`samsung_dsim_set_phy_timing()` or equivalent) uses a rounding mode when converting continuous D-PHY timing formulae to integer byte-clock counts. Change the rounding from `floor()` / truncation to `ceil()` for all timing parameters. Alternatively, force the register values directly via a device-tree override or platform data hook.</p>
 <p>### IMPORTANT — Fix #2: Investigate LP-11 Voltage</p>
 <p>LP-11 at 1.015 V (with VDDIO = 1.765 V) implies a <strong>750 mV drop</strong> across the LP driver. This is excessive for a CMOS push-pull driver. Check:<br>1. Series resistance in the LP-mode path (ESD protection, connector, filter)<br>2. Whether a pull-up/pull-down network is loading the LP lines<br>3. SN65DSI83 input bias current (should be &lt; 10 µA; if a pull-down exists on the bridge side, it will drag LP-11 low)</p>
 <p>Even though 1.015 V passes spec, increasing it to ~1.3 V would give the bridge 300 mV more noise margin for SoT detection.</p>
 <p>### MODERATE — Fix #3: Add SoT Lock Verification + Retry</p>
 <p>Since the failure mode is bistable (SoT succeeds or fails, never changes mid-session), add a software check after pipeline startup:<br>1. Read SN65DSI83 register 0x0A (PLL lock / sync status) within 100 ms of pipeline load<br>2. If not locked, unload and reload the pipeline (takes &lt; 200 ms)<br>3. Limit retries to 3 (with Round Up timing, retries should never be needed)</p>
 <p>This provides defence-in-depth even if the timing fix reduces but doesn&#x27;t fully eliminate the race.</p>
 <p>### MINOR — Fix #4: Measurement Infrastructure</p>
 <ol><li><strong>LP capture depth</strong>: Increase from 200k to 300k samples to avoid buffer edge errors</li><li><strong>Sig trigger</strong>: Add ±5 ns random holdoff to sample both data phases</li><li><strong>Proto window</strong>: Ensure capture contains both positive and negative data swings (the &quot;only negative swings&quot; artefact affects amplitude validation)</li></ol>
 <ul><li></li></ul>
 <p>## 7. Summary</p>
 <p><strong>The system has a non-deterministic SoT failure caused by 5 D-PHY timing violations in the &#x27;Round Best&#x27; register configuration, combined with a marginal LP-11 voltage of 1.015 V.</strong> The PHY&#x27;s internal state machine occasionally skips or truncates the LP-01/LP-00 SoT entry sequence (LP-low plateau = 0 ns in ~7% of startups), preventing the SN65DSI83 bridge from detecting start-of-transmission and locking. The 1.8 V supply is clean and not a contributing factor.</p>
 <p><strong>Switching to the &#x27;Round Up&#x27; register values (0x00000306 / 0x030f0a04 / 0x00030706) will bring all timing parameters into D-PHY v1.1 compliance with comfortable margin and is expected to eliminate the flicker.</strong> This is a software-only fix requiring a driver patch to the samsung-dsim PHY timing calculation, and should be validated by re-running the 30-capture batch to confirm 0% flicker rate and 0% occurrence of LP-low plateau &lt; 300 ns.</p>
 <p class="tokens">Tokens: 45428 in / 3819 out</p>
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 <!DOCTYPE html>
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 <title>MIPI Analysis — Captures 0303–0332</title>
 <style>
  body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
  h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
  .meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
  p { line-height: 1.6; }
  ol, ul { line-height: 1.8; padding-left: 24px; }
  li { margin: 4px 0; }
  .tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
  .flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
                    padding: 16px 20px; margin-bottom: 28px; }
  .flicker-alert h2 { color: #e65100; margin-top: 0; }
  .flicker-alert table { border-collapse: collapse; width: 100%; margin-top: 10px; }
  .flicker-alert th { background: #e65100; color: white; padding: 6px 10px; text-align: left; }
  .flicker-alert td { border: 1px solid #ccc; padding: 5px 10px; }
  table { border-collapse: collapse; width: 100%; }
  th { background: #1a3a5c; color: white; padding: 6px 10px; text-align: left; }
  td { border: 1px solid #ddd; padding: 5px 10px; }
  @media print { body { margin: 20px; } }
 </style>
 </head>
 <body>
 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 1 of 30 display load sessions (3%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0323</td><td>20260415_085420</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.2 ns</td><td>1.015 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0303</td><td>20260415_084704</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0304</td><td>20260415_084726</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0305</td><td>20260415_084748</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0306</td><td>20260415_084810</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0307</td><td>20260415_084831</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0308</td><td>20260415_084853</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0309</td><td>20260415_084915</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0310</td><td>20260415_084937</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0311</td><td>20260415_084958</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0312</td><td>20260415_085020</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0313</td><td>20260415_085042</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0314</td><td>20260415_085104</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0315</td><td>20260415_085126</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0316</td><td>20260415_085148</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0317</td><td>20260415_085209</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0318</td><td>20260415_085231</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0319</td><td>20260415_085253</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0320</td><td>20260415_085315</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0321</td><td>20260415_085337</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0322</td><td>20260415_085358</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0323</td><td>20260415_085420</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0324</td><td>20260415_085442</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0325</td><td>20260415_085504</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0326</td><td>20260415_085525</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0327</td><td>20260415_085547</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0328</td><td>20260415_085609</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0329</td><td>20260415_085630</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0330</td><td>20260415_085652</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0331</td><td>20260415_085714</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0332</td><td>20260415_085735</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 09:02:14 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0303–0332 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis Report</p>
 <p>## Batch: Captures 0303–0332 (30 sessions, 1 confirmed flicker event)</p>
 <ul><li></li></ul>
 <p>## 1. Consistent Spec Concerns</p>
 <p>### A. Register Timing — Systemic D-PHY v1.1 Non-Compliance (ALL 30 captures)</p>
 <p>Every capture shows identical register values — the system is running <strong>&#x27;Round Best&#x27; mode</strong> with <strong>5 persistent D-PHY violations</strong>:</p>
 <p>| Parameter | Programmed | Actual | Spec Min | Deficit |<br>|-----------|-----------|--------|----------|---------|<br>| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns (7.4%)</strong> |<br>| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns (2.6%)</strong> |<br>| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns (7.3%)</strong> |<br>| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns (1.2%)</strong> |<br>| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns (0.9%)</strong> |</p>
 <p><strong>Critical insight:</strong> The THS_PREPARE+THS_ZERO violation (1.5 ns short) directly controls the <strong>data lane SoT sequence</strong>. This is the time the receiver has to detect the HS-0 state before clock edges arrive. At only 0.9% below spec, the SN65DSI83 will *usually* latch it — but with jitter, process variation, and temperature, it will occasionally miss it. This exactly matches the observed bistable behaviour.</p>
 <p>### B. HS Amplitude — Marginal with Sub-140 mV Excursions</p>
 <ul><li><strong>CLK lane:</strong> Mean Vdiff ≈ 165.4 mV — only <strong>18% above the 140 mV floor</strong>. Every capture shows 17–102 settled samples below 140 mV.</li><li><strong>DAT0 lane:</strong> Mean Vdiff ≈ 187–199 mV (healthier), but sub-140 mV sample counts are highly variable: 19 to <strong>8,906</strong> samples per capture. This suggests data-pattern-dependent ISI causing amplitude collapse on certain bit sequences.</li><li><strong>CLK asymmetry:</strong> Consistent +194/−137 mV split (+30 mV common-mode offset) indicates a systematic DC offset in the clock driver or termination mismatch. While Vdiff is within spec, the asymmetry reduces noise margin on the negative swing.</li></ul>
 <p>### C. LP-11 Voltage — Low but In-Spec</p>
 <ul><li>LP-11 voltage: 1.014–1.016 V across all captures (spec 1.0–1.45 V).</li><li>This is at the <strong>bottom 4% of the allowed range</strong>. With VDDIO at 1.766 V, the LP driver VOH should be closer to 1.2–1.3 V. The 1.015 V level suggests either excessive series resistance in the LP path, a weak pull-up, or the probe is loading the LP driver (unlikely at ≥10 kΩ scope input).</li><li><strong>Not causing flicker directly</strong>, but reduced LP-11 level shrinks the receiver&#x27;s threshold margin for detecting LP-11 → LP-01 transitions.</li></ul>
 <p>### D. LP Exit Duration — Universally Violated</p>
 <ul><li><strong>22 of 29 measurable captures</strong> show LP exit → HS of 2–4 ns (spec ≥ 50 ns).</li><li>Only <strong>6 captures</strong> show 348 ns (passing), and <strong>1 capture</strong> shows 174 ns (passing).</li><li>This is <strong>not a measurement artifact</strong>: the LP-01/LP-00 intermediate states are being driven too briefly (or skipped entirely) at the scope&#x27;s sample resolution. The 2–4 ns readings indicate the PHY is transitioning from LP-11 directly to HS-0 without adequate dwell time in LP-01 and LP-00.</li></ul>
 <p><strong>Root cause:</strong> THS_PREPARE+THS_ZERO = 166.7 ns (below 168.2 ns spec) combined with the too-short TCLK_PREPARE (37 ns &lt; 38 ns) means the PHY state machine is rushing through the SoT entry states. The Samsung DSIM PHY internally sequences LP-11 → LP-01 → LP-00 → HS-0 using these register values as counters.</p>
 <ul><li></li></ul>
 <p>## 2. Trends Across Captures</p>
 <p>### A. No Drift — Stable Degradation</p>
 <p>| Parameter | Min | Max | Trend |<br>|-----------|-----|-----|-------|<br>| CLK Vdiff | 163.3 mV | 166.6 mV | <strong>Flat</strong> (±1%) |<br>| DAT Vdiff | 175.5 mV | 199.4 mV | <strong>No drift</strong>, high variance |<br>| CLK jitter p-p | 138.2 ps | 170.4 ps | <strong>Flat</strong> (no degradation) |<br>| CLK jitter RMS | 51.4 ps | 54.8 ps | <strong>Flat</strong> |<br>| LP-11 voltage | 1.014 V | 1.016 V | <strong>Flat</strong> |<br>| 1.8 V mean | 1.7645 V | 1.7712 V | <strong>Flat</strong> |<br>| 1.8 V droop | 8.5 mV | 14.0 mV | <strong>Flat</strong> (no worsening) |<br>| LP-low plateau | 0–343 ns | — | <strong>Bimodal</strong> (see §3) |</p>
 <p><strong>Conclusion:</strong> No temporal degradation. The system is thermally and electrically stable. The problem is purely in the SoT timing register configuration.</p>
 <p>### B. LP-Low Plateau — Bimodal Distribution (Key Finding)</p>
 <p>The LP-low plateau values cluster into <strong>three discrete groups</strong>:</p>
 <p>| LP-low plateau | Count | LP exit reported | Flicker? |<br>|----------------|-------|-----------------|----------|<br>| <strong>342–343 ns</strong> | 17 | 2–4 ns (fail) or 348 ns (pass) | No (except 0323) |<br>| <strong>108 ns</strong> | 5 | 2–4 ns (fail) | No |<br>| <strong>169 ns</strong> | 1 | 174 ns (pass) | No |<br>| <strong>0 ns</strong> | 1 (Cap 0323) | 2 ns (fail) | <strong>YES — FLICKER</strong> |</p>
 <p>The 342–343 ns group corresponds to approximately <strong>18.5 byte-clocks</strong> — this is THS_PREPARE+THS_ZERO (9 bc = 166.7 ns) plus additional PHY sequencing. The 108 ns group (≈6 bc) suggests a capture where the scope trigger caught only partial SoT.</p>
 <p><strong>Capture 0323 is the critical outlier:</strong> LP-low = 0 ns means the PHY drove LP-11 → HS-0 with <strong>no detectable LP-low dwell</strong>. The SN65DSI83 never saw LP-01/LP-00 and failed to recognise SoT.</p>
 <ul><li></li></ul>
 <p>## 3. Anomalies</p>
 <p>### A. Flicker Capture 0323 — Detailed Analysis</p>
 <p>| Parameter | Cap 0323 (flicker) | Batch mean (no flicker) |<br>|-----------|-------------------|------------------------|<br>| LP-low plateau | <strong>0 ns</strong> | 108–343 ns |<br>| LP exit → HS | 2 ns | 2–348 ns |<br>| 1.8 V droop | 9.4 mV | 10.2 mV (avg) |<br>| 1.8 V ripple | 5.44 mV | 5.65 mV (avg) |<br>| CLK jitter p-p | 146.0 ps | 152.0 ps (avg) |<br>| LP-11 voltage | 1.015 V | 1.015 V (avg) |</p>
 <p><strong>The supply was actually slightly better than average during the flicker event.</strong> This confirms the flicker is <strong>not supply-related</strong> — it is a timing race condition in the PHY SoT state machine.</p>
 <p>### B. DAT0 HS Signal Anomalies</p>
 <ul><li><strong>Captures 0306, 0315:</strong> sig/dat reports 0.0 mV — HS signal entirely absent in the sig capture window. The scope likely triggered too early or too late relative to the HS burst. Probe contact verified by valid lp/dat data.</li><li><strong>Capture 0321:</strong> proto/dat reports 0.0 mV — data lane was in LP state during the entire proto window. Again a trigger timing issue, not a hardware fault.</li><li><strong>Most sig/dat captures</strong> show only negative swings (Vdiff pos = 0.0 mV). This indicates the scope trigger consistently lands on a data-0 run. Not a hardware concern, but the true DAT0 amplitude is likely slightly higher than reported.</li></ul>
 <p>### C. Capture 0325 — Processing Error</p>
 <p>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP data capture buffer was exactly full with no LP→HS transition found within the window. The DAT0 lane may not have transitioned during this capture&#x27;s acquisition window. This is a trigger/timing issue, not a hardware fault.</p>
 <p>### D. CLK Lane LP State</p>
 <p>All captures show &quot;CLK LP→HS: NOT DETECTED&quot; — this is <strong>expected and correct</strong>. The i.MX 8M Mini DSIM runs the clock lane in <strong>continuous HS mode</strong> (no LP toggling on CLK during video). The CLK lane only enters LP at display pipeline unload, which these captures don&#x27;t cover.</p>
 <ul><li></li></ul>
 <p>## 4. Supply Correlation Analysis</p>
 <p>| Metric | Flicker (0323) | Non-flicker (29 caps) | Correlation |<br>|--------|---------------|----------------------|-------------|<br>| 1.8 V mean | 1.7654 V | 1.7645–1.7712 V | <strong>None</strong> |<br>| 1.8 V min | 1.7560 V | 1.7520–1.7600 V | <strong>None</strong> |<br>| Droop depth | 9.4 mV | 8.5–14.0 mV | <strong>None</strong> — droop was average |<br>| Ripple RMS | 5.44 mV | 5.44–6.13 mV | <strong>None</strong> — ripple was minimum |</p>
 <p><strong>Conclusion: The 1.8 V supply is healthy and not a contributing factor.</strong> All readings are comfortably within spec (1.71–1.89 V). The droop of 8.5–14.0 mV (&lt;1% of VDDIO) is excellent. There is no correlation between supply conditions and LP timing anomalies.</p>
 <p>The LP-11 voltage of 1.015 V (~56% of VDDIO) is lower than the expected ~70% (1.26 V) but is within D-PHY spec and does not correlate with the flicker event.</p>
 <ul><li></li></ul>
 <p>## 5. WARNING/ERROR Explanations</p>
 <p>| Warning | Count | Cause | Action |<br>|---------|-------|-------|--------|<br>| `LP exit duration N ns below spec min 50 ns` | 22/29 | THS_PREPARE+THS_ZERO too short (166.7 ns &lt; 168.2 ns); PHY rushes LP→HS transition. Scope sees LP-01/LP-00 as sub-sample-resolution glitch. | <strong>Switch to &#x27;Round Up&#x27; register values</strong> |<br>| `settled samples below 140 mV` (CLK) | 30/30 | CLK amplitude (165 mV) only 18% above floor; ISI/jitter pushes occasional eyes below. Termination or impedance mismatch likely. | Check CLK± PCB impedance matching; verify 100Ω differential termination at SN65DSI83 |<br>| `settled samples below 140 mV` (DAT) | 28/30 | Data pattern-dependent ISI; counts vary 19–8906. Higher counts correlate with captures where data pattern has long same-symbol runs. | Will improve with corrected register timing (better-formed SoT → fewer error patterns) |<br>| `Only negative swings in capture window` | 25/30 | Scope trigger consistently catches data-0 bit runs. Amplitude may be slightly underestimated. | Not a hardware concern; for accurate amplitude use pattern generator or longer random window |<br>| `No HS signal detected` (sig/dat) | 2/30 | Trigger landed outside HS burst window on DAT0. | Adjust trigger holdoff or use CLK-edge trigger for sig captures |<br>| `No HS signal detected` (proto/dat) | 1/30 | DAT0 in LP state during entire proto window. | Same trigger adjustment |<br>| `index out of bounds` (0325 lp_dat) | 1/30 | Buffer filled before LP→HS edge appeared — trigger too early or DAT0 transition outside window. | Increase buffer depth or adjust pre-trigger ratio |<br>| `CLK LP→HS: NOT DETECTED` | 30/30 | <strong>Expected.</strong> CLK runs continuous HS. | No action — informational only |</p>
 <ul><li></li></ul>
 <p>## 6. Actionable Recommendations</p>
 <p>### PRIORITY 1 — Switch to &#x27;Round Up&#x27; PHY Timing (Fixes Root Cause)</p>
 <p>Patch the samsung-dsim driver or device tree to program the &#x27;Round Up&#x27; register values:</p>
 <p>```<br>DSIM_PHYTIMING  (0xb4): 0x00000306   (THS_EXIT=6 → 111.1 ns ✓)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04   (TCLK_PREPARE=3 → 55.6 ns ✓, TCLK_ZERO=15, TCLK_TRAIL=4 → 74.1 ns ✓)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706   (THS_ZERO=7, THS_TRAIL=6 → 111.1 ns ✓)<br>```</p>
 <p>This eliminates all 5 D-PHY violations. The critical fix is <strong>THS_PREPARE+THS_ZERO: 10 bc = 185.2 ns</strong> (was 166.7 ns, spec ≥ 168.2 ns) — an increase of <strong>18.5 ns (11%)</strong> giving the SN65DSI83 receiver comfortable margin to detect SoT.</p>
 <p><strong>Implementation options (in order of preference):</strong><br>1. <strong>Driver patch:</strong> Modify the `samsung_dsim_set_phy_timing()` function to use ceiling division instead of round-to-nearest for all timing parameters.<br>2. <strong>Device tree override:</strong> If the driver supports `phy-timing` properties, set them explicitly.<br>3. <strong>Runtime register write:</strong> As a temporary test, write registers via `memtool` after pipeline load (will confirm the fix but won&#x27;t persist across loads).</p>
 <p>### PRIORITY 2 — Investigate LP-11 Voltage (Low Priority)</p>
 <p>LP-11 at 1.015 V (56% VDDIO) is unusually low. Check:<br>- Series resistance on DAT0+/DAT0− LP paths (ESD protection, ferrite beads, connectors).<br>- Whether the scope probe is loading the LP driver (unlikely but verify with 10× probe).<br>- SN65DSI83 input bias current on MIPI pins — the TI datasheet specifies the input leakage.</p>
 <p>This is not causing flicker but is a signal quality concern that could become problematic at higher bit rates or lower temperatures.</p>
 <p>### PRIORITY 3 — CLK Amplitude Margin Improvement (Medium Priority)</p>
 <p>CLK Vdiff at 165 mV with consistent sub-140 mV excursions suggests:<br>- Verify CLK± trace impedance is 100Ω differential (50Ω single-ended). Any impedance mismatch will reduce amplitude via reflections.<br>- Check for stubs or vias on CLK± traces near the SN65DSI83 input.<br>- The +30 mV common-mode offset on CLK indicates asymmetric termination or driver offset — verify both CLK± termination resistors are matched.</p>
 <p>### PRIORITY 4 — Improve Capture Trigger Reliability (Diagnostic)</p>
 <ul><li>Use CLK-lane HS edge as trigger source for</li></ul>
 <p class="tokens">Tokens: 45085 in / 4096 out</p>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0475</td><td>20260415_095344</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.0 ns</td><td>1.015 V</td></tr><tr><td>0488</td><td>20260415_095826</td><td>dat</td><td style='color:red'>0.3 ns</td><td>1.8 ns</td><td>1.015 V</td></tr><tr><td>0492</td><td>20260415_095953</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.6 ns</td><td>1.015 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0469</td><td>20260415_095133</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0470</td><td>20260415_095154</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0471</td><td>20260415_095217</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0472</td><td>20260415_095239</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0473</td><td>20260415_095300</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0474</td><td>20260415_095322</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0475</td><td>20260415_095344</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0476</td><td>20260415_095406</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0477</td><td>20260415_095427</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0478</td><td>20260415_095449</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0479</td><td>20260415_095511</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0480</td><td>20260415_095532</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0481</td><td>20260415_095554</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0482</td><td>20260415_095616</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0483</td><td>20260415_095637</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0484</td><td>20260415_095659</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0485</td><td>20260415_095721</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0486</td><td>20260415_095743</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0487</td><td>20260415_095804</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0488</td><td>20260415_095826</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0489</td><td>20260415_095848</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0490</td><td>20260415_095910</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0491</td><td>20260415_095931</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0492</td><td>20260415_095953</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0493</td><td>20260415_100015</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0494</td><td>20260415_100036</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0495</td><td>20260415_100058</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0496</td><td>20260415_100120</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0497</td><td>20260415_100142</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0498</td><td>20260415_100204</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 10:06:53 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0469–0498 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis — Captures 0469–0498</p>
 <p>## 1. Executive Summary</p>
 <p><strong>The system is running with &#x27;Round Best&#x27; PHY timing registers that violate D-PHY v1.1 in 5 fields. Every single capture (30/30) shows identical non-compliant register values. The SoT sequence is marginal: LP-low plateaux are bimodal (either ~343 ns or ~108 ns or 0 ns), and the three confirmed flicker events (0475, 0488, 0492) all have LP-low plateau = 0 ns — meaning the data lane SoT LP-01→LP-00 sequence is entirely absent. The root cause is the too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns min) combined with a too-short TCLK_PREPARE (37.0 ns vs 38.0 ns min), which leaves zero timing margin for the SN65DSI83 to detect the SoT. Switching to the &#x27;Round Up&#x27; register set eliminates all 5 violations and should eliminate flicker.</strong></p>
 <ul><li></li></ul>
 <p>## 2. Consistent Spec Concerns</p>
 <p>### 2.1 Register Violations (100% of captures — STATIC, every capture identical)</p>
 <p>| Field | Value | Actual | Spec Min | Deficit | Impact |<br>|-------|-------|--------|----------|---------|--------|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> | Insufficient HS→LP exit time; bridge may not recognise LP return |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> | Clock SoT prepare phase too short; clock lane PLL may not lock |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> | Clock trail too short; bridge may lose clock before data trail completes |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> | Clock lane SoT init sequence too short |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> | <strong>Critical: Data lane SoT sequence is 1.5 ns below spec</strong> |</p>
 <p>The THS_PREPARE+THS_ZERO violation is the <strong>smoking gun</strong>. At 1.5 ns below spec, the SN65DSI83&#x27;s internal SoT detector is right at its detection threshold. On most startups, the bridge barely catches it (State A). On ~10% of startups, PVT variation or supply noise pushes the effective timing below the bridge&#x27;s internal detection window → SoT is missed → bridge never locks → permanent flicker (State B).</p>
 <p>### 2.2 LP-11 Voltage</p>
 <ul><li>All captures: <strong>1.014–1.016 V</strong> (spec 1.0–1.45 V) ✓</li><li>Consistent, no drift, but <strong>low in the spec range</strong> (56% of min). This is borderline — the LP-11 high level should be closer to VDDIO (1.8 V). The 1.015 V value suggests the LP drivers are sourcing through significant resistance (likely the 200 Ω series resistors in the LP path), or the bridge&#x27;s LP termination is loading the line. This reduces noise margin for LP state detection.</li></ul>
 <p>### 2.3 HS Amplitude</p>
 <ul><li><strong>CLK lane</strong>: 163.7–166.6 mV differential — consistently within spec (140–270 mV) but <strong>low</strong> (only 18–19% above the 140 mV floor).</li><li><strong>DAT0 lane</strong>: 186.1–200.0 mV differential — healthier, ~33% above floor.</li><li><strong>Below-140 mV samples</strong>: Present in every capture (7–2052 samples). This indicates ISI/crosstalk dips during transitions. Not the flicker cause but reduces eye margin.</li></ul>
 <p>### 2.4 Clock Common Mode Offset</p>
 <ul><li>All captures show <strong>+27 to +32 mV common mode</strong> on the CLK lane (spec is ±25 mV from VCM nom). This is marginal and indicates slight driver asymmetry on the clock P/N pair.</li></ul>
 <ul><li></li></ul>
 <p>## 3. LP Timing Analysis — The Flicker Mechanism</p>
 <p>### 3.1 LP-Low Plateau Distribution (30 captures)</p>
 <p>| LP-low plateau | Count | LP exit→HS | Flicker? |<br>|----------------|-------|------------|----------|<br>| <strong>~343 ns</strong> | 13 | ~348 ns | <strong>0/13 (0%)</strong> |<br>| <strong>~108 ns</strong> | 8 | 1–4 ns | <strong>0/8 (0%)</strong> |<br>| <strong>0 ns</strong> | <strong>3</strong> | 2–4 ns | <strong>3/3 (100%)</strong> |<br>| Mixed (343 + valid exit) | 6 | 3–113 ns | 0/6 (0%) |</p>
 <p><strong>Key finding</strong>: The LP-low plateau has three discrete values — it is quantised, not continuously distributed. This proves the variation is <strong>digital</strong> (byte-clock quantisation in the DSIM PHY state machine), not analog (noise-induced). The LP→HS SoT sequence duration depends on exactly when the DSIM&#x27;s internal state machine transitions, which has a ±1 byte-clock (±18.5 ns) jitter relative to the scope trigger.</p>
 <p>### 3.2 Flicker Correlation</p>
 <p>All three flicker captures share:<br>- <strong>LP-low plateau = 0 ns</strong> (SoT LP-01/LP-00 states completely absent)<br>- <strong>LP exit→HS = 1.8–3.6 ns</strong> (effectively instantaneous — no LP→HS transition)<br>- The data lane jumps directly from LP-11 to HS with no intervening LP-01→LP-00 sequence</p>
 <p>This means the <strong>DSIM PHY is occasionally skipping the data lane SoT entry sequence entirely</strong>. The SN65DSI83 requires LP-11 → LP-01 → LP-00 → HS-0 to detect SoT (per D-PHY spec §5.7.1). When this sequence is absent, the bridge cannot synchronise to the HS data stream.</p>
 <p>### 3.3 Root Cause Chain</p>
 <ol><li><strong>THS_PREPARE+THS_ZERO = 166.7 ns</strong> (1.5 ns below 168.2 ns spec min)</li><li>The Samsung DSIM PHY implements this as 9 byte-clocks. Due to internal clock domain crossing between the LP and HS clock domains, the actual LP→HS transition can vary by ±1 byte-clock.</li><li>When the timing falls short by 1 byte-clock (−18.5 ns), the effective THS_PREPARE+THS_ZERO drops to <strong>~148 ns</strong> — well below spec.</li><li>In the worst case, the LP-01/LP-00 states are so brief that they are entirely swallowed by the HS ramp-up, producing LP-low plateau = 0 ns.</li><li>The SN65DSI83 never sees the SoT → never enters HS receive mode → never locks → flicker forever.</li></ol>
 <ul><li></li></ul>
 <p>## 4. Supply Rail Correlation</p>
 <p>### 4.1 1.8 V Supply Statistics</p>
 <p>| Metric | Min | Max | Mean | Spec |<br>|--------|-----|-----|------|------|<br>| Mean voltage | 1.7626 V | 1.7694 V | 1.7649 V | 1.71–1.89 V ✓ |<br>| Min voltage | <strong>1.6920 V</strong> | 1.7360 V | — | 1.71 V min ✗ |<br>| Droop depth | 28.3 mV | <strong>73.4 mV</strong> | 41.6 mV | — |<br>| Ripple RMS | 10.08 mV | 13.03 mV | 11.0 mV | — |</p>
 <p>### 4.2 Sub-spec Supply Events</p>
 <p>5 captures droop below 1.71 V: <strong>0472</strong> (1.696 V), <strong>0478</strong> (1.708 V), <strong>0479</strong> (1.700 V), <strong>0489</strong> (1.692 V), <strong>0492</strong> (1.696 V), <strong>0497</strong> (1.692 V).</p>
 <p>### 4.3 Supply–Flicker Correlation</p>
 <p>| Flicker capture | Min V | Droop | Flicker? |<br>|-----------------|-------|-------|----------|<br>| 0475 | 1.728 V | 34.6 mV | ✓ FLICKER |<br>| 0488 | 1.728 V | 37.8 mV | ✓ FLICKER |<br>| 0492 | <strong>1.696 V</strong> | 69.1 mV | ✓ FLICKER |</p>
 <p><strong>Mixed correlation</strong>: Two of three flicker events (0475, 0488) have <strong>normal</strong> supply conditions (droop &lt; 40 mV, above 1.71 V). Only 0492 has a significant droop. Conversely, several non-flicker captures (0472, 0479, 0489, 0497) have worse droops (65–73 mV) without flicker.</p>
 <p><strong>Conclusion</strong>: Supply droop is <strong>not the primary flicker cause</strong>. The flicker occurs even with clean supply. However, large droops (&gt;60 mV) are a secondary concern:<br>- They reduce LP driver headroom (LP-11 is already at 1.015 V with 1.765 V supply; a 73 mV droop could momentarily reduce LP drive below 1.0 V threshold)<br>- They may exacerbate the DSIM PHY&#x27;s internal timing uncertainty during the LP→HS transition</p>
 <ul><li></li></ul>
 <p>## 5. Warning/Error Explanation</p>
 <p>| Warning | Count | Cause | Action |<br>|---------|-------|-------|--------|<br>| `sig/dat: No HS signal detected` | 3 captures | Scope triggered during LP or inter-frame gap; DAT0 was idle | Benign — scope timing artifact |<br>| `sig/dat: Only negative swings` | 22 captures | Capture window caught only one polarity of differential data | Benign — data pattern / trigger alignment |<br>| `CLK lane in continuous HS mode` | 30/30 | Expected: DSI clock runs continuously, no LP states on CLK | Normal operation |<br>| `LP exit duration &lt; 50 ns` | 21/30 | <strong>THS_PREPARE is at the edge of spec</strong> — the LP→HS transition happens faster than the scope&#x27;s LP-state detection algorithm can measure the discrete LP-01/LP-00 steps | The &quot;LP exit&quot; metric measures the time from first LP-11 departure to first HS activity; when THS_PREPARE+THS_ZERO is marginal, the LP-01→LP-00 duration is too short to resolve |<br>| `Supply below 1.71 V` | 6/30 | Transient droop during LP→HS current surge (4 lanes + clock transitioning simultaneously) | Add decoupling — see recommendations |<br>| `Settled samples below 140 mV` | 30/30 on CLK, most on DAT | ISI / transition dips in HS signalling | Low-margin but not root cause; trace impedance and termination review recommended |</p>
 <ul><li></li></ul>
 <p>## 6. Trend Analysis</p>
 <p>### No Degradation Over Time<br>- HS amplitudes, jitter, rise times, LP-11 voltage, and supply mean are <strong>rock-stable</strong> across all 30 captures (captured over ~53 minutes).<br>- No thermal drift, no aging, no progressive degradation.<br>- The flicker events (0475, 0488, 0492) are randomly distributed in time, consistent with a <strong>stochastic digital timing race</strong> rather than an analog drift.</p>
 <p>### Bimodal HS Amplitude on DAT0 (Single-Ended LP Capture)<br>- HS amplitude in LP captures alternates between <strong>~108–120 mV</strong> and <strong>~11–36 mV</strong> (single-ended p-p/2).<br>- The low values (11–36 mV) likely correspond to captures where the scope caught the HS-0 (LP-to-HS transition ramp) rather than settled HS data, or the DAT0 line is carrying a long run of identical symbols. This is a measurement artifact, not a signal quality issue.</p>
 <ul><li></li></ul>
 <p>## 7. Actionable Recommendations</p>
 <p>### 7.1 CRITICAL — Switch to &#x27;Round Up&#x27; Register Set (Software Fix)</p>
 <p><strong>Change the samsung-dsim driver to use the &#x27;Round Up&#x27; timing calculation.</strong> This is the single most impactful fix and requires no hardware change.</p>
 <p>```<br>PHYTIMING  (0xb4): 0x00000305 → 0x00000306  (+1 bc on THS_EXIT)<br>PHYTIMING1 (0xb8): 0x020e0a03 → 0x030f0a04  (+1 bc on TCLK_PREPARE, +1 bc on TCLK_ZERO, +1 bc on TCLK_TRAIL)<br>PHYTIMING2 (0xbc): 0x00030605 → 0x00030706  (+1 bc on THS_ZERO, +1 bc on THS_TRAIL)<br>```</p>
 <p>This eliminates all 5 D-PHY violations:<br>- THS_PREPARE+THS_ZERO: 166.7 → <strong>185.2 ns</strong> (10% margin over 168.2 ns spec)<br>- TCLK_PREPARE: 37.0 → <strong>55.6 ns</strong> (46% margin over 38 ns spec)<br>- TCLK_PREPARE+TCLK_ZERO: 296.3 → <strong>333.3 ns</strong> (11% margin over 300 ns spec)<br>- THS_EXIT: 92.6 → <strong>111.1 ns</strong> (11% margin over 100 ns spec)<br>- TCLK_TRAIL: 55.6 → <strong>74.1 ns</strong> (23% margin over 60 ns spec)</p>
 <p><strong>Implementation</strong>: In the `samsung-dsim` (or `sec-dsim`) driver, the timing calculation function computes byte-clock counts from D-PHY formulas then applies either `round()` or `ceil()`. Change to `ceil()` for all timing parameters, or hard-code the &#x27;Round Up&#x27; values via device tree overrides if available.</p>
 <p>### 7.2 HIGH — Improve 1.8 V VDDIO Decoupling</p>
 <ul><li>Add <strong>1 µF + 100 nF MLCC</strong> as close as physically possible to the i.MX 8M Mini MIPI PHY VDDIO pins (balls).</li><li>The 73 mV worst-case droop (4.1% of 1.8 V) with ~11 mV RMS ripple indicates the existing decoupling cannot handle the 4-lane simultaneous LP→HS current surge (~80 mA transient for 4 data + 1 clock lane).</li><li>While not the primary flicker cause, sub-1.71 V excursions violate the VDDIO spec and reduce margins on all LP and HS thresholds.</li></ul>
 <p>### 7.3 MEDIUM — Investigate LP-11 Voltage</p>
 <ul><li>LP-11 at 1.015 V with VDDIO = 1.765 V means <strong>785 mV</strong> dropped across the LP output stage and series resistors. The D-PHY spec allows LP-11 down to 1.0 V, so this is technically compliant, but:</li><li>The SN65DSI83 LP receiver thresholds are referenced to its own VDDIO, so the actual noise margin depends on the bridge&#x27;s input threshold.</li><li>Check that the 200 Ω LP series resistors (if present) are not excessively loading the LP output.</li><li>Verify the bridge&#x27;s LP termination resistance matches expectations.</li></ul>
 <p>### 7.4 LOW — HS Amplitude Margin</p>
 <ul><li>CLK at 165 mV is only 18% above the 140 mV floor. While sufficient under nominal conditions, it leaves little margin for connector aging, temperature, or cable degradation.</li><li>If the design uses a flex cable or connector between the SOM and the SN65DSI83, verify impedance matching (100 Ω differential) and minimise stub lengths.</li></ul>
 <ul><li></li></ul>
 <p>## 8. Overall Signal Health &amp; Flicker Risk</p>
 <ul><li>The HS signal quality is adequate but low-margin</li></ul>
 <p class="tokens">Tokens: 45813 in / 4096 out</p>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0639</td><td>20260415_105739</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0642</td><td>20260415_105845</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.9 ns</td><td>1.016 V</td></tr><tr><td>0648</td><td>20260415_110055</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.1 ns</td><td>1.016 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0635</td><td>20260415_105612</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0636</td><td>20260415_105634</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0637</td><td>20260415_105655</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0638</td><td>20260415_105717</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0639</td><td>20260415_105739</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0640</td><td>20260415_105801</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0641</td><td>20260415_105823</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0642</td><td>20260415_105845</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0643</td><td>20260415_105906</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0644</td><td>20260415_105928</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0645</td><td>20260415_105950</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0646</td><td>20260415_110011</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0647</td><td>20260415_110033</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0648</td><td>20260415_110055</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0649</td><td>20260415_110116</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0650</td><td>20260415_110138</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0651</td><td>20260415_110200</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0652</td><td>20260415_110222</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0653</td><td>20260415_110243</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0654</td><td>20260415_110305</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0655</td><td>20260415_110326</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0656</td><td>20260415_110349</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0657</td><td>20260415_110410</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0658</td><td>20260415_110432</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0659</td><td>20260415_110454</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0660</td><td>20260415_110515</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0661</td><td>20260415_110537</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0662</td><td>20260415_110559</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0663</td><td>20260415_110621</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0664</td><td>20260415_110642</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 11:11:34 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0635–0664 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664 (30 Sessions)</p>
 <ul><li></li></ul>
 <p>## 1. Consistent Spec Concerns</p>
 <p>### A. PHY Timing Registers: 5 D-PHY v1.1 Violations (Every Capture)</p>
 <p>All 30 captures show <strong>identical</strong> register values — the &#x27;Round Best&#x27; non-compliant mode:</p>
 <p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
 <p><strong>Impact:</strong> The first two violations (TCLK_PREPARE short, THS_PREPARE+THS_ZERO short) directly truncate the SoT sequence that the SN65DSI83 must detect. The short THS_EXIT means the data lane may not fully exit HS before re-entering LP, compressing the LP-01→LP-00 window. These are not &quot;almost compliant&quot; — they are systematically below spec on every single boot, creating a baseline where the SN65DSI83&#x27;s SoT detector is already operating at the edge of its capture window.</p>
 <p>### B. LP-Exit Duration: Universally Violated</p>
 <p><strong>Every single capture</strong> (where LP data was measurable) shows `LP exit → HS` of <strong>1–4 ns</strong> against a 50 ns spec minimum. Even the &quot;good&quot; (no-flicker) captures violate this. This means:</p>
 <ul><li>The D-PHY LP-01→LP-00 state machine transitions are being driven far faster than spec</li><li>The PHY is effectively skipping the LP-01/LP-00 signalling states as distinct resolvable events</li><li>The SN65DSI83 must detect SoT from a sub-5 ns edge, which is unreliable by design</li></ul>
 <p>### C. LP-11 Voltage: Marginal but Within Spec</p>
 <p>All captures: <strong>1.011–1.016 V</strong> (spec 1.0–1.45 V). This is at the <strong>absolute floor</strong> of the valid range. At 1.015 V typical with 1.8 V VDDIO, the LP driver is pulling only 56% of supply. This is consistent with the weak LP driver output seen in this PHY at low VDDIO.</p>
 <p>### D. CLK Lane: Continuous HS Mode</p>
 <p>CLK is always in continuous HS — no LP states expected. This is normal for video-mode DSI but means the SN65DSI83 relies <strong>entirely</strong> on data lane SoT detection for frame sync.</p>
 <p>### E. HS Amplitude: CLK Lane Near Floor</p>
 <p>CLK differential amplitude: <strong>164.2–166.5 mV</strong> with consistent sub-140 mV samples (24–172 per capture). This is only 18% above the 140 mV minimum. DAT0 amplitude is healthier at ~187–195 mV but shows asymmetric swings in many captures.</p>
 <ul><li></li></ul>
 <p>## 2. Trends Across 30 Captures</p>
 <p>### No Degradation Over Time — Confirms Bistable Model</p>
 <p>| Parameter | Range | Trend |<br>|---|---|---|<br>| CLK Vdiff | 164.2–166.5 mV | <strong>Flat</strong> — no drift |<br>| DAT0 Vdiff | 186.0–223.2 mV | <strong>Flat</strong> (scatter from capture phase) |<br>| CLK jitter p-p | 148.5–174.6 ps | <strong>Flat</strong> — no progressive worsening |<br>| CLK jitter RMS | 53.1–57.4 ps | <strong>Flat</strong> |<br>| LP-11 voltage | 1.011–1.016 V | <strong>Flat</strong> — no droop over time |<br>| 1.8 V mean | 1.7635–1.7698 V | <strong>Flat</strong> |<br>| 1.8 V droop | 7.6–16.6 mV | <strong>No trend</strong> (random scatter) |<br>| LP-low plateau | 0–343 ns | <strong>Bimodal</strong> — see below |</p>
 <p>The absence of any progressive trend confirms the bistable observation: the system doesn&#x27;t degrade into failure, it <strong>rolls dice at SoT</strong> and sticks with the result.</p>
 <p>### LP-Low Plateau: Bimodal Distribution (Key Finding)</p>
 <p>| LP-low plateau | Count | Outcome |<br>|---|---|---|<br>| <strong>342–348 ns</strong> | ~17 captures | All <strong>good</strong> (no flicker) |<br>| <strong>93–108 ns</strong> | ~7 captures | All <strong>good</strong> (no flicker) |<br>| <strong>0 ns</strong> (absent) | <strong>3 captures</strong> | All <strong>FLICKER</strong> (0639, 0642, 0648) |<br>| Parse error | 2 captures (0649, 0662) | Unknown |</p>
 <p><strong>This is the smoking gun.</strong> The LP-low plateau clusters into three discrete populations:<br>- <strong>~343 ns:</strong> The PHY executes a full LP-00 state (approximately 18.5 bc = one byte-clock aligned interval). SN65DSI83 locks successfully.<br>- <strong>~108 ns:</strong> The PHY executes a shortened LP-00 state (~6 bc). Still long enough for SN65DSI83 to detect. No flicker.<br>- <strong>0 ns:</strong> The LP-00 state is <strong>completely absent</strong>. The data line transitions directly from LP-11 to HS without a resolvable LP-01/LP-00 sequence. <strong>The SN65DSI83 cannot detect SoT. Flicker results.</strong></p>
 <p>The trimodal distribution (0 / ~108 / ~343 ns) with byte-clock-like quantisation strongly suggests the PHY&#x27;s internal SoT state machine has a <strong>race condition</strong> related to the programmed THS_PREPARE+THS_ZERO values being below spec. The short THS_EXIT (92.6 ns &lt; 100 ns) further compresses the timing window, and the short TCLK_PREPARE (37 ns &lt; 38 ns) means the clock lane SoT also runs tight. When all these jitter contributions align unfavourably, the LP-00 state collapses to zero.</p>
 <ul><li></li></ul>
 <p>## 3. Anomalies</p>
 <p>### A. Flicker Captures — Absent LP-00 State</p>
 <p>| Capture | LP-low | LP exit→HS | Flicker |<br>|---|---|---|---|<br>| <strong>0639</strong> | <strong>0 ns</strong> | 2 ns | <strong>YES</strong> |<br>| <strong>0642</strong> | <strong>0 ns</strong> | 3 ns | <strong>YES</strong> |<br>| <strong>0648</strong> | <strong>0 ns</strong> | 2 ns | <strong>YES</strong> |</p>
 <p>All three flicker events share the identical signature: LP-low plateau = 0 ns. No other parameter (supply, amplitude, jitter) distinguishes them from good captures.</p>
 <p>### B. DAT0 sig Captures: Intermittent 0.0 mV (No HS Detected)</p>
 <p>Captures 0637, 0642, 0643, 0647, 0655, 0663 show `sig/dat Vdiff = 0.0 mV` — &quot;No HS signal detected.&quot; This occurs in both good and bad sessions. <strong>Most likely cause:</strong> The sig capture&#x27;s short acquisition window (high-res mode) triggered during an LP or blanking interval rather than during active HS data. This is a <strong>trigger timing artefact</strong>, not a signal fault — the proto/dat captures from the same sessions show healthy HS amplitude. No action needed on this artefact, but it means sig/dat data is unreliable for roughly 20% of captures.</p>
 <p>### C. DAT0 proto: Intermittent &quot;Only Negative Swings&quot;</p>
 <p>Captures 0635, 0642, 0653 show proto/dat with only negative differential excursions. This occurs when the proto window captures a run of identical data bits. It&#x27;s a <strong>capture phase artefact</strong>, not a signal issue.</p>
 <p>### D. LP Parse Errors</p>
 <p>Captures 0649 and 0662: `index 200000 is out of bounds` — the LP capture buffer was exhausted before the SoT event completed. Most likely cause: the trigger fired too late in the LP-11 dwell, and the HS burst extended past the capture window. These sessions could not be classified for flicker from LP data alone.</p>
 <p>### E. DAT0 Sub-140 mV Sample Counts: High Variance</p>
 <p>The number of settled samples below 140 mV on DAT0 proto varies wildly: 36 to <strong>8203</strong>. This is driven by how much of the capture window contains transition edges versus settled levels, and by the data pattern. The high counts (e.g., 0649: 8203; 0648: 5203; 0636: 5884) are <strong>not</strong> correlated with flicker — capture 0636 (5884 sub-140 mV samples) has LP-low = 108 ns and no flicker. These counts reflect HS eye opening, not SoT integrity.</p>
 <ul><li></li></ul>
 <p>## 4. Supply Correlation Analysis</p>
 <p>### 1.8 V Supply vs. LP Anomalies</p>
 <p>| Parameter | Flicker captures (0639/0642/0648) | Good captures (all others) |<br>|---|---|---|<br>| 1.8 V mean | 1.7649–1.7654 V | 1.7635–1.7698 V |<br>| 1.8 V min | 1.7560 V | 1.7480–1.7600 V |<br>| Droop depth | 8.9–9.4 mV | 7.6–16.6 mV |<br>| Ripple RMS | 5.55–5.77 mV | 5.24–5.91 mV |</p>
 <p><strong>No correlation.</strong> The flicker captures have <strong>average or better</strong> supply metrics. The worst droop (16.6 mV, capture 0637) and lowest min voltage (1.7480 V, capture 0637) occurred in a <strong>good</strong> session. The 1.8 V supply is <strong>not the cause</strong> of the intermittent SoT failure.</p>
 <p>### LP-11 Voltage vs. Supply</p>
 <p>LP-11 voltage (1.011–1.016 V) shows no correlation with supply droop. The LP driver output is limited by the PHY&#x27;s internal regulation, not the supply rail headroom (which has &gt;50 mV margin to the 1.71 V lower limit).</p>
 <ul><li></li></ul>
 <p>## 5. Warning/Error Explanations</p>
 <p>| Warning/Error | Cause | Action |<br>|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>Root cause issue.</strong> PHY SoT state machine transitions too fast due to short THS_PREPARE+THS_ZERO and THS_EXIT register values. | <strong>Fix registers</strong> — switch to &#x27;Round Up&#x27; mode |<br>| `FLICKER SUSPECT: LP-low plateau absent or &lt; 50 ns` | LP-00 state completely missing — PHY skipped the SoT low-going sequence. Direct consequence of timing violations. | Same register fix |<br>| `Only negative swings in capture window` | Proto/sig trigger captured a run of identical data bits (e.g., all-zero payload). Amplitude estimate is valid for the measured polarity. | Benign artefact — no action needed |<br>| `No HS signal detected — line may be in LP state or idle` | Sig capture (short window) triggered during blanking or LP interval. | Benign artefact — increase sig trigger holdoff or ignore |<br>| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal for video-mode DSI. CLK runs HS continuously. | Expected — no action |<br>| `X settled samples below 140 mV` (CLK) | CLK amplitude (165 mV) is close to floor; ISI and jitter push some transitions below 140 mV during ringing/settling. | Monitor but no immediate action — amplitude is 18% above floor |<br>| `index 200000 is out of bounds` | LP capture buffer too short to contain the full SoT→HS transition at this trigger position. | Increase capture depth or adjust trigger delay |</p>
 <ul><li></li></ul>
 <p>## 6. Actionable Recommendations</p>
 <p>### CRITICAL — Fix #1: Switch to &#x27;Round Up&#x27; PHY Timing (Eliminates Root Cause)</p>
 <p>Modify the samsung-dsim driver (or device tree) to program the <strong>&#x27;Round Up&#x27; compliant</strong> register values:</p>
 <p>```<br>DSIM_PHYTIMING  (0xb4): 0x00000306   ← THS_EXIT = 6 (was 5)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04   ← TCLK_PREPARE = 3 (was 2), TCLK_ZERO = 15 (was 14), TCLK_TRAIL = 4 (was 3)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706   ← THS_ZERO = 7 (was 6), THS_TRAIL = 6 (was 5)<br>```</p>
 <p>This eliminates all 5 D-PHY violations and adds margin:<br>- THS_EXIT: 92.6 → 111.1 ns (11% margin over 100 ns spec)<br>- TCLK_PREPARE: 37.0 → 55.6 ns (46% margin over 38 ns spec)<br>- TCLK_PREPARE+TCLK_ZERO: 296.3 → 333.3 ns (11% margin over 300 ns spec)<br>- THS_PREPARE+THS_ZERO: 166.7 → 185.2 ns (10% margin over 168.2 ns spec)<br>- TCLK_TRAIL: 55.6 → 74.1 ns (23% margin over 60 ns spec)</p>
 <p>The added THS_ZERO and TCLK_ZERO margin directly extends the LP-00 state duration, making the 0 ns plateau condition physically impossible.</p>
 <p><strong>Implementation:</strong> In the `samsung-dsim` / `sec-dsim` driver, the timing calculation function uses `DIV_ROUND_UP` vs. truncation for these fields. Ensure the driver&#x27;s `dsim_calc_phy_timing()` or equivalent uses ceiling division. Alternatively, override via device tree `phy-timing` properties or a kernel patch to force the compliant values.</p>
 <p>### IMPORTANT — Fix #2: Investigate LP-11 Voltage</p>
 <p>LP-11 at 1.015 V is within spec but is only 15 mV above the 1.0 V floor. At this level, the SN65DSI83&#x27;s LP receiver has minimal noise margin. Potential improvements:</p>
 <ul><li><strong>Verify VDDIO decoupling</strong> near the i.MX 8M Mini PHY VDDIO pins — add 100 nF ceramic if missing within 2 mm</li><li><strong>Check series resistance</strong> in the LP path — any added series termination on Dp/Dn will drop LP-11 voltage</li><li><strong>Verify the PHY&#x27;s LP driver bias</strong> — some Samsung DSIM implementations have a configurable LP output swing via an undocumented register or OTP setting</li></ul>
 <p>### MONITORING — HS CLK Amplitude</p>
 <p>CLK at 165 mV with sub-140 mV excursions is functional but leaves only 25 mV (18%) of margin. If trace length increases (board revision, flex cable, etc.), this will fail. Consider:</p>
 <ul><li>Reviewing CLK lane termination (should be 100Ω differential at SN65DSI83 input)</li><li>Checking for stubs or vias in the CLK differential pair</li><li>Verifying the PHY&#x27;s HS driver impedance calibration (if configurable)</li></ul>
 <p>### MINOR — Capture Infrastructure</p>
 <ul><li>Increase LP capture buffer from 200k samples to ≥400k to avoid the index-out-of-bounds errors in captures 0649 and 0662</li><li>Adjust sig capture trigger holdoff to consistently land in active HS data, not blanking</li></ul>
 <ul><li></li></ul>
 <p>## 7. Summary</p>
 <p><strong>The flicker root cause is definitively identified:</strong> the samsung-dsim PHY timing registers are programmed with &#x27;Round Best&#x27; (truncated) values that violate D-PHY v1</p>
 <p class="tokens">Tokens: 45244 in / 4096 out</p>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0819</td><td>20260415_120723</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.3 ns</td><td>1.014 V</td></tr><tr><td>0821</td><td>20260415_120807</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.8 ns</td><td>1.015 V</td></tr><tr><td>0830</td><td>20260415_121123</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.5 ns</td><td>1.015 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0801</td><td>20260415_120051</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0802</td><td>20260415_120113</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0803</td><td>20260415_120134</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0804</td><td>20260415_120156</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0805</td><td>20260415_120217</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0806</td><td>20260415_120239</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0807</td><td>20260415_120301</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0808</td><td>20260415_120323</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0809</td><td>20260415_120345</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0810</td><td>20260415_120407</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0811</td><td>20260415_120428</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0812</td><td>20260415_120450</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0813</td><td>20260415_120512</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0814</td><td>20260415_120534</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0815</td><td>20260415_120556</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0816</td><td>20260415_120617</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0817</td><td>20260415_120640</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0818</td><td>20260415_120702</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0819</td><td>20260415_120723</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0820</td><td>20260415_120745</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0821</td><td>20260415_120807</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0822</td><td>20260415_120828</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0823</td><td>20260415_120850</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0824</td><td>20260415_120912</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0825</td><td>20260415_120934</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0826</td><td>20260415_120955</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0827</td><td>20260415_121017</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0828</td><td>20260415_121039</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0829</td><td>20260415_121101</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0830</td><td>20260415_121123</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 12:16:31 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0801–0830 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis — Captures 0801–0830</p>
 <p>## 1. Executive Summary</p>
 <p><strong>The system is running with non-compliant D-PHY timing registers (5 spec violations) that create a narrow but real window for SoT failure. The 3 confirmed flicker events (0819, 0821, 0830) all share a unique signature: LP-low plateau = 0 ns, meaning the LP-01/LP-00 SoT states were completely skipped. The root cause is the samsung-dsim driver&#x27;s &quot;Round Best&quot; timing calculation mode, which produces sub-spec THS_PREPARE+THS_ZERO and TCLK_PREPARE+TCLK_ZERO values. The SN65DSI83 bridge occasionally fails to detect the truncated SoT and never recovers within that session. Switching to &quot;Round Up&quot; register values eliminates all 5 violations and should eliminate flicker.</strong></p>
 <ul><li></li></ul>
 <p>## 2. Consistent Spec Concerns</p>
 <p>### 2.1 Register Timing — 5 Persistent D-PHY v1.1 Violations (ALL 30 captures)</p>
 <p>Every single capture shows identical register values — the PHY timing is static and non-compliant:</p>
 <p>| Parameter | Programmed | Actual | Spec Min | Deficit | Severity |<br>|---|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns | Medium — affects HS→LP→HS turnaround |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns | <strong>Critical</strong> — clock SoT setup |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns | Medium — clock lane EoT |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns | <strong>Critical</strong> — clock HS-init total |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns | <strong>Critical</strong> — data lane HS-init total |</p>
 <p>The deficits are tiny (1–7 ns) but they are <strong>systematic and always present</strong>. They don&#x27;t cause failure alone — they reduce the SN65DSI83&#x27;s timing margin to near-zero, making the system vulnerable to any jitter or race condition at the SoT instant.</p>
 <p>### 2.2 LP-Exit Duration — Universally Below Spec</p>
 <p>| Metric | Good sessions | Flicker sessions |<br>|---|---|---|<br>| LP exit → HS | 1–4 ns (spec ≥ 50 ns) | 2–3 ns (spec ≥ 50 ns) |<br>| LP-low plateau | 108–343 ns | <strong>0 ns</strong> |</p>
 <p><strong>All 30 captures</strong> show LP-exit durations of 1–4 ns, far below the 50 ns D-PHY minimum. This is a measurement of the actual LP-01→LP-00 intermediate state duration on the wire. The PHY is transitioning through the SoT LP states so rapidly that the oscilloscope (at its capture resolution) cannot distinguish them — they appear as a near-instantaneous drop from LP-11 to HS common mode.</p>
 <p>However, the critical differentiator is the <strong>LP-low plateau</strong>:<br>- <strong>Non-flicker captures</strong>: 108–343 ns plateau (the LP-00 state is held long enough for the bridge)<br>- <strong>Flicker captures (0819, 0821, 0830)</strong>: <strong>0 ns</strong> plateau (LP-00 never appears on the wire)</p>
 <p>### 2.3 HS Amplitude — Marginal but In-Spec</p>
 <p>| Lane | Typical Vdiff | Spec Range | Concern |<br>|---|---|---|---|<br>| CLK | 164.2–166.3 mV | 140–270 mV | Consistently near low end; every capture has samples below 140 mV |<br>| DAT0 | 175.7–223.4 mV | 140–270 mV | Higher but variable; many sub-140 mV samples |</p>
 <p>The CLK lane amplitude is <strong>systematically within 25 mV of the 140 mV floor</strong>. Combined with jitter (150–183 ps p-p), individual transitions dip below threshold. This doesn&#x27;t cause flicker on its own but further degrades the bridge&#x27;s ability to lock onto a marginal SoT.</p>
 <p>### 2.4 CLK Lane Common Mode Offset</p>
 <p>CLK consistently shows +28 to +30 mV common-mode offset (positive). DAT0 shows −5 to −7 mV typically. This ~35 mV differential CM offset is within spec (±25 mV per line, ±50 mV lane-to-lane) but on the high side and could affect the SN65DSI83&#x27;s internal common-mode rejection during the critical SoT detection window.</p>
 <p>### 2.5 LP-11 Voltage — Consistent but Low</p>
 <p>All captures show LP-11 = 1.014–1.016 V against a 1.8 V VDDIO. The spec requires LP-11 to be ≥ VIH(LP) ≈ 880 mV (0.55 × 1.6 V with 200 mV hysteresis), so 1.015 V is in-spec. However, this is 56% of VDDIO, which is below the typical 70–80% expected. This suggests:<br>- Significant resistive drop in the LP driver path, or<br>- The LP-11 voltage is reduced by the 1.8 V supply being at 1.764 V (1.015/1.764 = 57.5%)</p>
 <p>This is not a direct flicker cause but is worth noting as a contributing factor to the bridge&#x27;s reduced noise margin for LP state detection.</p>
 <ul><li></li></ul>
 <p>## 3. Trends Over Captures</p>
 <p>### 3.1 No Amplitude or Jitter Drift<br>CLK Vdiff is remarkably stable: 164.2–166.3 mV across all 30 captures (&lt; 2 mV variation). Jitter ranges 148–183 ps p-p with no upward trend. <strong>There is no thermal drift or degradation over the 10-minute capture window.</strong></p>
 <p>### 3.2 LP-Low Plateau Shows Three Distinct Populations</p>
 <p>| Plateau Duration | Count | Flicker? |<br>|---|---|---|<br>| 342–343 ns | 14 captures | No |<br>| 108 ns | 10 captures | No |<br>| <strong>0 ns</strong> | <strong>3 captures (0819, 0821, 0830)</strong> | <strong>YES</strong> |</p>
 <p>The 343 ns and 108 ns populations both produce stable displays. The bimodal distribution (343 vs 108) suggests the PHY has two internal timing paths — possibly related to whether the HS clock PLL is already locked from a prior cycle or initializing fresh. The 0 ns population is the pathological case.</p>
 <p>### 3.3 Supply Droop — Slight Correlation with Flicker</p>
 <p>| Captures | Mean Droop | Mean Ripple RMS |<br>|---|---|---|<br>| Non-flicker (27) | 9.4 mV | 5.60 mV |<br>| Flicker (3: 0819,0821,0830) | 11.8 mV | 5.60 mV |</p>
 <p>Capture 0821 (flicker) has the largest single droop in the batch: <strong>17.0 mV</strong> (V_min = 1.748 V). However, non-flicker capture 0822 has nearly identical droop (14.6 mV, V_min = 1.748 V). The correlation is <strong>weak</strong> — supply droop is not the primary cause, though the 0821 droop is the worst-case and may have contributed to that specific event.</p>
 <p>### 3.4 HS Burst Duration — Consistent<br>All captures show a single HS burst of ~5,020–5,077 ns. This is consistent with a single video line at the observed configuration. No anomalous burst counts or durations.</p>
 <ul><li></li></ul>
 <p>## 4. Anomaly Analysis</p>
 <p>### 4.1 Flicker Events — Complete SoT Omission</p>
 <p><strong>Captures 0819, 0821, 0830</strong> all show LP-low plateau = 0 ns. This means:<br>- The LP-11 → LP-01 → LP-00 → HS-0 sequence was <strong>not executed</strong> or was so fast it was indistinguishable from a direct LP-11 → HS transition<br>- The SN65DSI83 requires a minimum LP-00 hold time to recognize the SoT sequence (TI specifies compliance with D-PHY v1.1, implying ≥ THS_PREPARE min = 40ns + 4×UI ≈ 49 ns)<br>- With 0 ns LP-00, the bridge treats the first HS burst as noise and never achieves lane synchronization</p>
 <p><strong>Root cause mechanism</strong>: The Samsung DSIM PHY has THS_PREPARE+THS_ZERO programmed 1.5 ns below spec minimum. On most initializations, the analog PHY adds enough internal delay to produce a detectable LP-00 plateau (108–343 ns). On ~10% of initializations, PVT (process/voltage/temperature) variation within the PHY causes the LP-00 state machine to skip or truncate the LP-00 hold, producing the 0 ns plateau. This is classic metastability behavior in a timing-marginal digital state machine.</p>
 <p>### 4.2 Missing or Partial DAT0 HS in sig Captures</p>
 <p>Captures 0805, 0807 show `sig/dat Vdiff = 0.0 mV` (&quot;No HS signal detected&quot;). This is a <strong>scope triggering artifact</strong> — the sig capture window is very short (high-resolution mode) and occasionally misses the HS burst. These captures are NOT flicker events (both show 108–343 ns LP-low plateaux and no confirmed flicker).</p>
 <p>Similarly, many `sig/dat` captures show &quot;Only negative swings&quot; — this indicates the sig trigger caught a run of identical data bits (e.g., all-zero pixel data). This is expected and benign.</p>
 <p>### 4.3 proto/dat Capture 0821 — No HS Signal</p>
 <p>Capture 0821 (confirmed flicker) shows `proto/dat Vdiff = 0.0 mV`. This is <strong>consistent with the flicker mechanism</strong>: the bridge failed to lock, so the DSIM controller may have entered a degraded state where DAT0 was not transmitting valid HS data during the proto capture window. The CLK lane continued running (proto/clk is normal), confirming the clock lane is in continuous HS mode regardless of data lane SoT failure.</p>
 <p>### 4.4 CLK Lane LP — Expected Behavior</p>
 <p>All captures show &quot;CLK LP→HS sequence NOT DETECTED&quot; on the CLK lane. This is <strong>correct and expected</strong>: the DSIM controller runs the clock lane in continuous HS mode (no LP states on CLK after initial startup). The LP captures on CLK confirm the clock never leaves HS during normal operation.</p>
 <ul><li></li></ul>
 <p>## 5. Supply Correlation Analysis</p>
 <p>### 5.1 1.8 V Supply — Within Spec but Sagged</p>
 <p>| Metric | Range | Spec | Assessment |<br>|---|---|---|---|<br>| Mean voltage | 1.7625–1.7657 V | 1.71–1.89 V | ✓ but 2% below nominal |<br>| Min voltage | 1.7480–1.7560 V | ≥ 1.71 V | ✓ but only 38–46 mV above spec floor |<br>| Droop depth | 7.3–17.0 mV | — | Max 17 mV at flicker event 0821 |<br>| Ripple RMS | 5.44–5.84 mV | — | Consistent, no trend |</p>
 <p>The supply is healthy but running 36 mV below nominal (1.764 vs 1.800 V). This is within tolerance but means:<br>- LP driver output is reduced (explaining the 1.015 V LP-11 ≈ 57.5% of VDDIO)<br>- PHY internal logic has less VDD margin for state machine transitions</p>
 <p>### 5.2 Supply vs. LP-Low Plateau Correlation</p>
 <p>| LP-low plateau | V_min range | Droop range |<br>|---|---|---|<br>| 343 ns | 1.752–1.756 V | 7.3–12.1 mV |<br>| 108 ns | 1.748–1.756 V | 7.9–16.5 mV |<br>| 0 ns (flicker) | 1.748–1.756 V | 8.8–17.0 mV |</p>
 <p>There is a <strong>slight trend</strong> toward higher droop in the 0 ns / flicker group, but the overlap is too large to conclude causation. The supply is not the trigger — it is, at most, a contributing factor that reduces the noise margin of the already-marginal PHY timing.</p>
 <ul><li></li></ul>
 <p>## 6. Warning/Error Explanation</p>
 <p>| Warning | Captures | Most Likely Cause | Action |<br>|---|---|---|---|<br>| &quot;LP exit duration X ns below spec min 50 ns&quot; | 25/30 | THS_PREPARE+THS_ZERO is 1.5 ns below spec; PHY state machine exits LP states too quickly | <strong>Fix register timing</strong> |<br>| &quot;settled samples below 140 mV&quot; (CLK) | 30/30 | CLK amplitude ~165 mV with ISI/jitter; transitions through 140 mV threshold | Increase PHY drive strength if adjustable; otherwise acceptable |<br>| &quot;settled samples below 140 mV&quot; (DAT) | 28/30 | Data-dependent ISI causes amplitude variation | Same as above |<br>| &quot;Only negative swings&quot; (sig/dat) | ~20/30 | Short capture window caught monotone data pattern | Benign — scope trigger artifact |<br>| &quot;No HS signal detected&quot; (sig/dat) | 2/30 | Scope trigger missed HS burst in narrow window | Benign — increase sig capture window |<br>| &quot;FLICKER SUSPECT: LP-low plateau absent&quot; | 3/30 | PHY skipped LP-00 hold state entirely | <strong>Root cause — fix timing registers</strong> |<br>| &quot;CLK lane in continuous HS mode&quot; | 30/30 | Expected: DSIM runs CLK in continuous HS | No action needed |<br>| &quot;No HS signal detected&quot; (proto/dat 0821) | 1/30 | Bridge failed to lock → DSIM data lane in degraded state | Consequence of flicker, not cause |</p>
 <ul><li></li></ul>
 <p>## 7. Actionable Recommendations</p>
 <p>### 7.1 PRIMARY FIX — Switch to &quot;Round Up&quot; PHY Timing (Critical, Immediate)</p>
 <p>Patch the samsung-dsim / sec-dsim driver to use ceiling-rounded timing values. Target register writes:</p>
 <p>```<br>DSIM_PHYTIMING  (0x32e100b4) = 0x00000306   (was 0x00000305)<br>  TLPX=3 (55.6ns ✓), THS_EXIT=6 (111.1ns ✓)</p>
 <p>DSIM_PHYTIMING1 (0x32e100b8) = 0x030f0a04   (was 0x020e0a03)<br>  TCLK_PREPARE=3 (55.6ns ✓), TCLK_ZERO=15 (PREP+ZERO=333ns ✓),<br>  TCLK_POST=10 (185ns ✓), TCLK_TRAIL=4 (74.1ns ✓)</p>
 <p>DSIM_PHYTIMING2 (0x32e100bc) = 0x00030706   (was 0x00030605)<br>  THS_PREPARE=3 (55.6ns ✓), THS_ZERO=7 (PREP+ZERO=185.2ns ✓),<br>  THS_TRAIL=6 (111.1ns ✓)<br>```</p>
 <p>This eliminates <strong>all 5 D-PHY violations</strong> with zero cost (adds 1–2 byte-clock cycles to SoT/EoT sequences, imperceptible to throughput at 432 Mbit/s).</p>
 <p><strong>Implementation options (in order of preference):</strong></p>
 <ol><li><strong>Kernel driver patch</strong>: Modify the `samsung_dsim_set_phy_timing()` function to use `DIV_ROUND_UP()` instead of integer division for all timing parameters</li></ol>
 <p class="tokens">Tokens: 45807 in / 4096 out</p>
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 <title>MIPI Analysis — Captures 0967–0996</title>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0985</td><td>20260415_131221</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.1 ns</td><td>1.015 V</td></tr><tr><td>0987</td><td>20260415_131304</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.2 ns</td><td>1.016 V</td></tr><tr><td>0995</td><td>20260415_131558</td><td>dat</td><td style='color:red'>0.3 ns</td><td>4.0 ns</td><td>1.016 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0967</td><td>20260415_130550</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0968</td><td>20260415_130612</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0969</td><td>20260415_130633</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0970</td><td>20260415_130655</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0971</td><td>20260415_130717</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0972</td><td>20260415_130738</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0973</td><td>20260415_130800</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0974</td><td>20260415_130822</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0975</td><td>20260415_130844</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0976</td><td>20260415_130906</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0977</td><td>20260415_130927</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0978</td><td>20260415_130949</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0979</td><td>20260415_131011</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0980</td><td>20260415_131033</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0981</td><td>20260415_131054</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0982</td><td>20260415_131116</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0983</td><td>20260415_131138</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0984</td><td>20260415_131200</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0985</td><td>20260415_131221</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0986</td><td>20260415_131243</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0987</td><td>20260415_131304</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0988</td><td>20260415_131326</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0989</td><td>20260415_131348</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0990</td><td>20260415_131409</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0991</td><td>20260415_131431</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0992</td><td>20260415_131452</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0993</td><td>20260415_131514</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0994</td><td>20260415_131536</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0995</td><td>20260415_131558</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0996</td><td>20260415_131619</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 13:21:17 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0967–0996 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis — Captures 0967–0996</p>
 <p>## 1. Executive Summary</p>
 <p><strong>The system is running with &#x27;Round Best&#x27; PHY timing registers that have 5 D-PHY v1.1 violations. The SoT LP-low plateau is bimodal: ~342 ns (good) or 0 ns (flicker). The three confirmed flicker events (0985, 0987, 0995) all show LP-low plateau = 0 ns — the LP-01/LP-00 SoT states are completely absent, so the SN65DSI83 never detects start-of-transmission. Switching to the &#x27;Round Up&#x27; register set eliminates all five timing violations and is the single highest-impact fix.</strong></p>
 <ul><li></li></ul>
 <p>## 2. Consistent Spec Concerns</p>
 <p>### 2.1 Register Timing Violations (100% of captures)</p>
 <p>Every single capture reads identical non-compliant registers:</p>
 <p>| Parameter | Programmed | Actual | Spec Min | Deficit |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
 <p><strong>Critical observation:</strong> All five violations are by margins of 1–7.4 ns — fractions of one byte-clock. This is exactly the kind of marginal non-compliance that works *most of the time* but fails non-deterministically when PVT (process, voltage, temperature) variations or internal PLL jitter push the actual analogue timing slightly shorter than the already-short programmed value. This directly explains the bistable 10% failure rate.</p>
 <p>### 2.2 LP-low Plateau Bimodality</p>
 <p>Across the 26 captures with valid LP data:</p>
 <p>| LP-low Plateau | Count | Flicker? |<br>|---|---|---|<br>| <strong>~342 ns</strong> | 12 | No (all good) |<br>| <strong>~108 ns</strong> | 11 | No (all good) |<br>| <strong>0 ns</strong> | <strong>3</strong> | <strong>YES — all three flicker events</strong> |</p>
 <p>The 342 ns and 108 ns populations both represent successful SoT sequences (the bridge locks). The 0 ns population represents a <strong>completely collapsed SoT</strong> — LP-01→LP-00 states are either not emitted or so brief they are unresolvable. The SN65DSI83 cannot detect the data lane SoT entry point and fails to lock.</p>
 <p><strong>Root cause chain:</strong> THS_PREPARE+THS_ZERO is programmed to 166.7 ns versus the 168.2 ns minimum. When the PHY&#x27;s internal PLL phase happens to shorten this by even ~2 ns, the SoT LP-low states collapse below the bridge&#x27;s detection threshold. The TCLK_PREPARE violation (37.0 vs 38.0 ns) compounds this by occasionally mis-aligning the clock lane&#x27;s HS entry relative to the data lane&#x27;s SoT, so the bridge misses the synchronisation window entirely.</p>
 <p>### 2.3 LP Exit Duration</p>
 <p>| LP exit → HS | Occurrences | Notes |<br>|---|---|---|<br>| <strong>≥ 113 ns</strong> | 5 | Spec-compliant (≥ 50 ns) |<br>| <strong>2–4 ns</strong> | 18 | <strong>Spec violation — below 50 ns</strong> |<br>| <strong>0 ns</strong> | 3 | Flicker events |</p>
 <p><strong>23 of 26 valid captures (88%) show LP exit &lt; 50 ns.</strong> The measurement algorithm reports 2–4 ns for the non-flicker cases, which likely represents the LP-11→LP-01 transition being too fast for the measurement resolution rather than truly absent. However, only when it reaches 0 ns does flicker occur. The extremely short LP exit durations across the board confirm that TLPX (55.6 ns) and THS_PREPARE (55.6 ns) are at the very bottom of their acceptable ranges, leaving zero margin.</p>
 <p>### 2.4 HS Amplitude Concerns</p>
 <p><strong>Clock lane:</strong> Consistently ~165.5 mV differential — within spec (140–270 mV) but at the <strong>low end</strong> (only 25 mV margin above 140 mV floor). Every proto/clk capture shows settled samples below 140 mV (28–136 per capture), indicating ISI/eye-closure at transitions.</p>
 <p><strong>Data lane:</strong> Nominal amplitude 186–199 mV but with persistent below-140 mV violations (up to 5546 samples in capture 0969). The data eye is stressed.</p>
 <p><strong>Clock asymmetry:</strong> Consistent +194 mV / −136 mV split on CLK lane (common mode +28–30 mV). This ~58 mV positive/negative imbalance suggests a small DC offset in the CLK driver or termination mismatch. While within spec, it reduces negative-swing noise margin.</p>
 <p>### 2.5 LP-11 Voltage</p>
 <p>All captures: <strong>1.014–1.016 V</strong> (spec 1.0–1.45 V). This is at the <strong>absolute floor</strong> of the LP-11 specification. The nominal VDDIO is 1.8 V; LP-11 should be at or near VDDIO. At 1.015 V the LP driver is operating with only ~15 mV of margin above the 1.0 V floor.</p>
 <p><strong>This is a secondary concern.</strong> The low LP-11 voltage indicates the MIPI PHY LP pull-ups are sourcing from a rail that may be loaded or the pull-up resistors are too weak. While it doesn&#x27;t directly cause the flicker (the SoT failure does), it reduces the LP-11→LP-00 voltage swing available for the bridge&#x27;s LP state detector, making SoT detection harder.</p>
 <ul><li></li></ul>
 <p>## 3. Trend Analysis</p>
 <p>### 3.1 No Temporal Drift</p>
 <p>| Parameter | Range across 30 captures | Trend |<br>|---|---|---|<br>| CLK Vdiff | 164.8–166.8 mV | <strong>Flat — no drift</strong> |<br>| CLK freq | 213.0–219.2 MHz | Stable ±1.5% |<br>| CLK jitter RMS | 52.1–56.3 ps | <strong>Flat</strong> |<br>| LP-11 voltage | 1.014–1.016 V | <strong>Flat</strong> |<br>| 1.8 V mean | 1.764–1.770 V | <strong>Flat</strong> |<br>| 1.8 V droop | 7.9–16.2 mV | <strong>Mostly flat</strong> (one outlier at 16.2 mV — capture 0975) |</p>
 <p><strong>Conclusion:</strong> There is no progressive degradation. The system is stable between loads. The flicker is purely a per-load-cycle non-deterministic event, consistent with the bistable behaviour description.</p>
 <p>### 3.2 Flicker Events Are NOT Correlated With Any Measured Analogue Trend</p>
 <p>The three flicker captures (0985, 0987, 0995) show:<br>- Normal supply (droop 8.7–10.3 mV, within the non-flicker range of 7.9–16.2 mV)<br>- Normal CLK amplitude and jitter<br>- Normal LP-11 voltage<br>- Normal HS burst duration</p>
 <p><strong>The only distinguishing feature is LP-low plateau = 0 ns.</strong> This confirms the root cause is digital timing (PHY state machine) not analogue signal quality.</p>
 <ul><li></li></ul>
 <p>## 4. Supply Correlation</p>
 <p>### 4.1 1.8 V Supply Health</p>
 <p>| Metric | Range | Spec | Status |<br>|---|---|---|---|<br>| Mean voltage | 1.764–1.770 V | 1.71–1.89 V | ✓ but 54 mV below nominal 1.8 V |<br>| Min voltage | 1.748–1.760 V | ≥ 1.71 V | ✓ with 38–50 mV margin |<br>| Droop depth | 7.9–16.2 mV | — | Acceptable |<br>| Ripple RMS | 5.25–6.01 mV | — | Good |</p>
 <p>### 4.2 Droop vs. Flicker Correlation</p>
 <p>| Capture | Droop (mV) | Flicker? |<br>|---|---|---|<br>| 0985 | 8.7 | <strong>YES</strong> |<br>| 0987 | 10.3 | <strong>YES</strong> |<br>| 0995 | 8.9 | <strong>YES</strong> |<br>| 0975 | <strong>16.2</strong> | No |<br>| 0981 | 10.1 | No |</p>
 <p><strong>No correlation.</strong> The worst droop (16.2 mV, capture 0975) did NOT produce flicker. The flicker captures have unremarkable droop. <strong>Supply noise is not the trigger.</strong></p>
 <p>### 4.3 LP-11 Voltage vs. Supply</p>
 <p>LP-11 at 1.015 V with VDDIO at 1.765 V means the LP pull-up drops ~750 mV. This is consistent with a ~1.2 kΩ pull-up driving ~600 µA into the line termination, or a weak internal pull-up. It does not vary with supply — it&#x27;s a fixed resistive divider, not a transient issue.</p>
 <ul><li></li></ul>
 <p>## 5. Anomaly Analysis</p>
 <p>### 5.1 Missing LP Data (Captures 0971, 0972, 0988, 0996)</p>
 <p>```<br>[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000<br>```</p>
 <p><strong>Cause:</strong> The LP analysis algorithm&#x27;s edge-search exceeded the capture buffer boundary. This occurs when the LP-11→LP-00 transition happens very late in the capture window or the trigger placed the SoT event at the extreme end of the acquisition memory.</p>
 <p><strong>Action:</strong> Increase scope pre-trigger holdoff or LP capture record length by 20%. Not a hardware fault.</p>
 <p>### 5.2 Data Lane &quot;Only Negative Swings&quot; / &quot;No HS Signal&quot;</p>
 <p>~60% of sig/dat and proto/dat captures show only negative differential swings or zero amplitude. This is a <strong>scope triggering/windowing artifact</strong> — the high-speed capture window (a few ns) happened to land on a data lane period where only one polarity was present (e.g., during a long run of &#x27;0&#x27; bits in the pixel data). The data lane carries packet content, not a 50/50 clock, so this is expected and benign.</p>
 <p><strong>Action:</strong> None required. The proto/dat captures that do resolve both polarities show proper ~195 mV amplitude.</p>
 <p>### 5.3 Below-140 mV Samples on Data Lane</p>
 <p>The data lane consistently shows hundreds to thousands of settled samples below the 140 mV Vdiff floor. This is <strong>ISI (inter-symbol interference)</strong> from consecutive same-polarity transitions on the data lane. At 432 Mbit/s with ~165 ps rise times and a data eye that is already smaller than the clock eye (data has random jitter; clock does not), this is expected for a PCB trace of moderate length.</p>
 <p><strong>Risk:</strong> The SN65DSI83 has its own LP/HS detection threshold. If the data lane eye is marginal, the bridge&#x27;s CDR could occasionally fail to lock, but this would manifest as persistent HS errors, not the observed bistable SoT failure. This is a secondary concern.</p>
 <ul><li></li></ul>
 <p>## 6. Actionable Recommendations</p>
 <p>### 6.1 PRIMARY FIX — Switch to &#x27;Round Up&#x27; Register Set</p>
 <p><strong>This is the single fix that addresses the root cause.</strong> Patch the samsung-dsim driver (or device tree overlay) to program:</p>
 <p>```<br>PHYTIMING  (0xb4) = 0x00000306   (THS_EXIT: 5→6)<br>PHYTIMING1 (0xb8) = 0x030f0a04   (TCLK_PREPARE: 2→3, TCLK_ZERO: 14→15, TCLK_TRAIL: 3→4)<br>PHYTIMING2 (0xbc) = 0x00030706   (THS_ZERO: 6→7, THS_TRAIL: 5→6)<br>```</p>
 <p>This eliminates all 5 D-PHY violations and provides adequate margin:</p>
 <p>| Parameter | Round Best | Round Up | Spec Min | Margin |<br>|---|---|---|---|---|<br>| THS_EXIT | 92.6 ns | <strong>111.1 ns</strong> | 100.0 ns | +11.1 ns |<br>| TCLK_PREPARE | 37.0 ns | <strong>55.6 ns</strong> | 38.0 ns | +17.6 ns |<br>| TCLK_TRAIL | 55.6 ns | <strong>74.1 ns</strong> | 60.0 ns | +14.1 ns |<br>| TCLK_PREP+ZERO | 296.3 ns | <strong>333.3 ns</strong> | 300.0 ns | +33.3 ns |<br>| THS_PREP+ZERO | 166.7 ns | <strong>185.2 ns</strong> | 168.2 ns | +17.0 ns |</p>
 <p><strong>Expected result:</strong> The LP-low plateau should consistently appear at ≥100 ns on every load cycle. The 0 ns collapse events should be eliminated. Flicker rate should drop from 10% to 0%.</p>
 <p>### 6.2 Driver Patch Location</p>
 <p>In the `samsung-dsim` driver (`drivers/gpu/drm/bridge/samsung-dsim.c`), the timing calculation function `samsung_dsim_set_phy_timing()` uses a rounding mode. The current code path is selecting floor/truncation (&quot;Round Best&quot;). Either:</p>
 <ol><li><strong>Modify the rounding function</strong> to always round up to the next byte-clock boundary when the calculated continuous-time value is within 1 bc of the spec minimum, OR</li><li><strong>Apply a static override</strong> via device tree properties `samsung,phy-timing = &lt;0x00000306 0x030f0a04 0x00030706&gt;;` if the driver supports it, OR</li><li><strong>Patch the register values directly</strong> in the driver&#x27;s `samsung_dsim_atomic_enable()` path using `regmap_write()` after the default timing is programmed.</li></ol>
 <p>### 6.3 SECONDARY — Investigate Low LP-11 Voltage</p>
 <p>LP-11 at 1.015 V (vs. 1.8 V VDDIO) indicates the LP driver pull-ups are too weak or there is excessive loading on the LP lines. Check:</p>
 <ul><li><strong>SN65DSI83 LP input bias current</strong> (datasheet: should be &lt; 10 µA in LP-11)</li><li><strong>Series resistors on LP lines</strong> (some layouts add 200–330 Ω for ESD; these can drop LP voltage)</li><li><strong>Scope probe loading</strong> (1 MΩ / 10 pF probes on LP lines will load them; use FET probes or remove probes after measurement)</li></ul>
 <p>While this is not the flicker root cause, improving LP-11 to &gt;1.2 V would give the bridge more SoT detection margin.</p>
 <p>### 6.4 TERTIARY — Clock Lane Amplitude Margin</p>
 <p>CLK Vdiff at ~165 mV with a 140 mV floor leaves only 25 mV margin. At the board level:<br>- Verify CLK± trace impedance matching (target 100 Ω differential)<br>- Check for stub lengths on CLK pair (any via or T-junction &gt; 1 mm adds reflection)<br>- Ensure CLK termination resistor (100 Ω) is placed within 2 mm of the SN65DSI83 input pins</p>
 <p>This is not urgent but would improve long-term reliability across temperature.</p>
 <p>### 6.5 Scope Capture Improvements</p>
 <ul><li><strong>Increase LP capture record length</strong> to 250k points to avoid the index-out-of-bounds errors</li><li><strong>Add a second trigger condition</strong> on DAT0_LP going below 0.5 V to ensure the LP-00 state is always captured within the window</li><li><strong>Use math channel</strong> for differential LP (Dp−Dn) in addition to single-ended to better resolve LP-01 vs LP-00</li></ul>
 <ul><li></li></ul>
 <p>## 7. Overall Assessment</p>
 <ul><li></li></ul>
 <p class="tokens">Tokens: 44774 in / 4096 out</p>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 4 of 30 display load sessions (13%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>1133</td><td>20260415_141042</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.4 ns</td><td>1.016 V</td></tr><tr><td>1149</td><td>20260415_141630</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.4 ns</td><td>1.015 V</td></tr><tr><td>1151</td><td>20260415_141713</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>1152</td><td>20260415_141735</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.1 ns</td><td>1.015 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>1133</td><td>20260415_141042</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1134</td><td>20260415_141104</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1135</td><td>20260415_141126</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1136</td><td>20260415_141147</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1137</td><td>20260415_141209</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1138</td><td>20260415_141231</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1139</td><td>20260415_141252</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1140</td><td>20260415_141314</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1141</td><td>20260415_141336</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1142</td><td>20260415_141358</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1143</td><td>20260415_141420</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1144</td><td>20260415_141442</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1145</td><td>20260415_141503</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1146</td><td>20260415_141525</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1147</td><td>20260415_141547</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1148</td><td>20260415_141608</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1149</td><td>20260415_141630</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1150</td><td>20260415_141652</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1151</td><td>20260415_141713</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1152</td><td>20260415_141735</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1153</td><td>20260415_141757</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1154</td><td>20260415_141819</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1155</td><td>20260415_141840</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1156</td><td>20260415_141902</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1157</td><td>20260415_141924</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1158</td><td>20260415_141946</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1159</td><td>20260415_142007</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1160</td><td>20260415_142029</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1161</td><td>20260415_142051</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1162</td><td>20260415_142113</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 14:26:26 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 1133–1162 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis — Captures 1133–1162</p>
 <p>## 1. Executive Summary</p>
 <p><strong>The system is running with &#x27;Round Best&#x27; PHY timing registers that produce 5 D-PHY v1.1 spec violations on every single capture. The SoT sequence on the data lane is critically degraded: LP-low plateau is absent (0 ns) on all 4 confirmed flicker events, and the LP-11→HS exit time is universally 0–4 ns (spec ≥ 50 ns) across both good and bad sessions. The difference between State A (good) and State B (flicker) is whether the SN65DSI83 receiver happens to sample the truncated/missing LP-01→LP-00 SoT preamble in time — a race condition caused by timing fields programmed below D-PHY minimums.</strong></p>
 <ul><li></li></ul>
 <p>## 2. Consistent Spec Concerns</p>
 <p>### 2.1 Register Timing Violations (100% of captures)</p>
 <p>Every single capture shows identical register values — the &#x27;Round Best&#x27; mode is active throughout:</p>
 <p>| Parameter | Programmed | Actual | D-PHY v1.1 Spec | Deficit |<br>|-----------|-----------|--------|-----------------|---------|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | ≥ 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0–95.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | ≥ 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | ≥ 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | ≥ 168.2 ns | <strong>−1.5 ns</strong> |</p>
 <p><strong>The THS_PREPARE+THS_ZERO violation (−1.5 ns) is the smoking gun.</strong> This combined parameter defines the data-lane SoT sequence duration — specifically, how long the receiver sees the HS-zero state before the first valid data bit. At 166.7 ns vs. the 168.2 ns minimum, the SN65DSI83&#x27;s LP-HS state machine has <strong>less than one UI (2.315 ns) of margin</strong> to recognise the SoT. Analog process/voltage/temperature variation inside the bridge&#x27;s receiver comparators will occasionally cause it to miss the SoT entirely — exactly matching the observed bistable behaviour.</p>
 <p>### 2.2 LP-11→HS Exit Timing (Universal Violation)</p>
 <p>| Metric | Flicker captures (1133, 1149, 1151, 1152) | Non-flicker captures | Spec |<br>|--------|-------------------------------------------|---------------------|------|<br>| LP exit → HS | 2–3 ns | 0–4 ns (majority 2–4 ns) | ≥ 50 ns |<br>| LP-low plateau | <strong>0 ns</strong> | 108–343 ns | ≥ TLPX (50 ns) |</p>
 <p><strong>Critical finding:</strong> The LP exit duration is below spec in <strong>every capture</strong> (flicker and non-flicker alike), typically 2–4 ns vs. the 50 ns minimum. This means the LP-11→LP-01→LP-00→HS-0 state machine is running too fast for the scope to resolve the intermediate states — the PHY is essentially slamming from LP-11 directly into HS with no discernible LP-00 dwell.</p>
 <p>The <strong>differentiator for flicker</strong> is whether the LP-low plateau is detected at all:<br>- <strong>Flicker events (4/30):</strong> LP-low = 0 ns — the LP-00 state is completely absent<br>- <strong>Good sessions:</strong> LP-low = 108–343 ns — some LP-00 dwell is present, enough for the bridge</p>
 <p>This is consistent with THS_PREPARE+THS_ZERO being 1.5 ns short: the PHY occasionally collapses the LP-00 state entirely when internal PLL/divider phase alignment happens to truncate it by that extra fraction of a byte clock.</p>
 <p>### 2.3 LP-11 Voltage</p>
 <p>LP-11 = 1.015–1.016 V across all captures. Spec range is 1.0–1.45 V (derived from VDDIO × 55%–80%). At VDDIO = 1.765 V, the expected LP-high range is 0.97–1.41 V, so <strong>1.015 V is within spec but in the lower quartile</strong>. This is not the failure mechanism but offers minimal noise margin for LP-state detection at the receiver.</p>
 <p>### 2.4 HS Amplitude</p>
 <ul><li><strong>CLK lane:</strong> 164.6–169.0 mV differential — consistently within spec (140–270 mV) but at the <strong>low end</strong></li><li><strong>DAT lane:</strong> 177.8–199.2 mV differential — healthy</li><li><strong>Below-140 mV samples:</strong> Present on every capture (CLK: 18–106 samples; DAT: 7–3846 samples). These are transition-region excursions and ISI-related dips. The DAT lane shows significantly more sub-140 mV samples, indicating <strong>worse signal integrity on the data path</strong> (likely longer trace, worse impedance match, or coupling).</li></ul>
 <ul><li></li></ul>
 <p>## 3. Trend Analysis Across 30 Captures</p>
 <p>### 3.1 No Temporal Drift<br>- <strong>CLK amplitude:</strong> 166.0–166.5 mV — rock-steady, no degradation<br>- <strong>CLK frequency:</strong> 213.1–219.2 MHz — variation is capture-window aliasing, nominal 216 MHz<br>- <strong>Jitter:</strong> 140–167 ps p-p, 52.6–55.9 ps RMS — stable, within typical bounds<br>- <strong>Rise times:</strong> 139.9–174.1 ps (20–80%) — consistent<br>- <strong>1.8 V supply:</strong> Mean 1.7635–1.7695 V, ripple RMS 5.14–5.94 mV — stable<br>- <strong>LP-11 voltage:</strong> 1.015–1.016 V — no drift</p>
 <p><strong>Conclusion:</strong> There is no progressive degradation. The failure mode is purely stochastic at each pipeline-load event.</p>
 <p>### 3.2 LP-Low Plateau Distribution</p>
 <p>| LP-low plateau (ns) | Count | Flicker? |<br>|---------------------|-------|----------|<br>| 0 | 4 | <strong>YES (all 4 flicker events)</strong> |<br>| 108 | 7 | No |<br>| 342–343 | 15 | No |<br>| N/A (capture error) | 1 (cap 1143) | Unknown |</p>
 <p>The plateau quantises into three clusters (0, ~108, ~342 ns), suggesting the PHY&#x27;s internal state machine aligns the LP-00 dwell to byte-clock boundaries. When the phase alignment is unfavourable, the dwell collapses to zero — the SoT preamble vanishes entirely.</p>
 <ul><li></li></ul>
 <p>## 4. Supply Correlation Analysis</p>
 <p>### 4.1 Droop vs. Flicker</p>
 <p>| Capture | Flicker? | LP-low (ns) | 1.8V droop (mV) | 1.8V min (V) |<br>|---------|----------|-------------|-----------------|--------------|<br>| <strong>1133</strong> | <strong>YES</strong> | <strong>0</strong> | <strong>16.9</strong> | <strong>1.748</strong> |<br>| 1134 | No | 342 | 9.7 | 1.756 |<br>| 1135 | No | 342 | 9.6 | 1.756 |<br>| <strong>1149</strong> | <strong>YES</strong> | <strong>0</strong> | 9.0 | 1.756 |<br>| <strong>1151</strong> | <strong>YES</strong> | <strong>0</strong> | <strong>16.6</strong> | <strong>1.748</strong> |<br>| <strong>1152</strong> | <strong>YES</strong> | <strong>0</strong> | 9.4 | 1.756 |<br>| 1157 | No | 343 | 13.2 | 1.752 |<br>| 1158 | No | 108 | 15.5 | 1.748 |</p>
 <p><strong>Mixed correlation.</strong> Captures 1133 and 1151 (flicker) show the deepest droops (16.9/16.6 mV, min 1.748 V), but captures 1149 and 1152 (also flicker) show normal droop (9.0/9.4 mV). Conversely, capture 1158 (no flicker) has 15.5 mV droop.</p>
 <p><strong>Conclusion:</strong> Supply droop is a <strong>contributing factor but not the primary cause</strong>. The deeper droops (to 1.748 V) reduce the LP driver swing and PHY PLL stability during the LP→HS transition, which further compresses the already-too-short SoT timing. However, flicker also occurs at normal supply levels, confirming the root cause is the register-level timing violation, not supply.</p>
 <ul><li></li></ul>
 <p>## 5. Anomaly &amp; Warning Explanations</p>
 <p>### 5.1 &quot;Only negative swings in capture window&quot; (≈60% of sig/dat captures)<br><strong>Cause:</strong> The oscilloscope trigger captured a window aligned to a run of identical data bits (e.g., all-zero payload region). In DDR MIPI, a constant &#x27;0&#x27; pattern produces only negative differential swings. This is a <strong>capture-window artifact</strong>, not a signal defect. The amplitude from these captures (~194 mV) is consistent with full-swing measurements from balanced captures.</p>
 <p><strong>Action:</strong> No concern. Could refine trigger to capture more diverse bit patterns if balanced amplitude measurement is needed.</p>
 <p>### 5.2 &quot;No HS signal detected&quot; on sig/dat (Captures 1136, 1141, 1144, 1147)<br><strong>Cause:</strong> The high-resolution trigger on DAT0 captured a blanking interval or LP idle period between HS bursts. The DAT lane is in LP state during vertical blanking; the narrow capture window occasionally falls in this gap.</p>
 <p><strong>Action:</strong> No concern for signal health assessment — the proto captures from the same sessions confirm valid HS operation.</p>
 <p>### 5.3 &quot;CLK lane is in continuous HS mode&quot; on lp/clk (all captures)<br><strong>Cause:</strong> Expected behaviour. The Samsung DSIM PHY operates the clock lane in continuous HS mode (not non-continuous clock mode). The clock lane entered HS before the data lane&#x27;s LP capture window and stays there. LP states on the clock lane are only visible during the very first pipeline startup, which occurs before the scope&#x27;s trigger on data-lane LP activity.</p>
 <p><strong>Action:</strong> No concern. This is correct DSI Video Mode operation.</p>
 <p>### 5.4 &quot;[lp_dat] ERROR: index 200000 is out of bounds&quot; (Capture 1143)<br><strong>Cause:</strong> The LP analysis script&#x27;s edge-detection algorithm attempted to access beyond the capture buffer boundary. Most likely, the LP→HS transition occurred at the very end of the capture window, and the algorithm&#x27;s look-ahead overran. This is a <strong>software bug in the analysis tool</strong>, not a signal issue.</p>
 <p><strong>Action:</strong> Extend the capture window by 10% or add bounds checking in the LP analysis script. The LP data for this capture is not available for flicker analysis — it should be repeated.</p>
 <p>### 5.5 DAT lane sub-140 mV sample counts vary wildly (7–3846)<br><strong>Cause:</strong> Data-dependent ISI (inter-symbol interference). Long runs of alternating bits produce clean eye openings; long runs of same-bit produce DC-wander and pre-/post-cursor ISI that momentarily drops the differential swing below 140 mV. Captures with higher counts happened to contain more worst-case bit patterns.</p>
 <p><strong>Action:</strong> The maximum count (3846 in capture 1140) suggests the DAT lane&#x27;s SI is marginal. Check trace impedance matching and consider adding 100 Ω differential termination at the SN65DSI83 input if not already present.</p>
 <ul><li></li></ul>
 <p>## 6. Actionable Recommendations</p>
 <p>### 6.1 CRITICAL — Switch to &#x27;Round Up&#x27; Register Values</p>
 <p>This is the <strong>single most important fix</strong>. Apply the fully D-PHY v1.1 compliant timing:</p>
 <p>```<br># Write &#x27;Round Up&#x27; values via memtool or device tree overlay:<br>DSIM_PHYTIMING  (0x32e100b4) = 0x00000306   # THS_EXIT=6 → 111.1 ns ✓<br>DSIM_PHYTIMING1 (0x32e100b8) = 0x030f0a04   # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓<br>DSIM_PHYTIMING2 (0x32e100bc) = 0x00030706   # THS_ZERO=7, THS_TRAIL=6 ✓<br>```</p>
 <p><strong>Specific impact on the failure mechanism:</strong><br>- THS_PREPARE+THS_ZERO increases from 166.7 ns → <strong>185.2 ns</strong> (+18.5 ns, 10% margin over spec)<br>- TCLK_PREPARE+TCLK_ZERO increases from 296.3 ns → <strong>333.3 ns</strong> (+33 ns, 11% margin)<br>- THS_EXIT increases from 92.6 ns → <strong>111.1 ns</strong> (11% margin)</p>
 <p>This eliminates the race condition at SoT by giving the SN65DSI83 receiver substantially more time to detect the LP-00 state and synchronise to the HS preamble.</p>
 <p><strong>Implementation:</strong> In the samsung-dsim / sec-dsim driver, the timing calculation is done in `samsung_dsim_set_phy_timing()`. The &#x27;Round Best&#x27; mode truncates fractional byte-clock results downward; switching to ceiling (round-up) ensures all timings meet or exceed spec minimums. This is typically a one-line change in the driver&#x27;s rounding mode or can be forced via device tree properties if supported by the BSP.</p>
 <p>### 6.2 HIGH — Verify the Fix Eliminates LP-Low Plateau Collapse</p>
 <p>After applying Round Up registers, repeat the 30-cycle load/unload test and verify:<br>- LP-low plateau ≥ 50 ns on <strong>every</strong> capture<br>- LP exit → HS ≥ 50 ns on <strong>every</strong> capture<br>- Zero flicker events across ≥ 100 pipeline-load cycles</p>
 <p>### 6.3 MEDIUM — Investigate LP-11 Voltage (1.015 V)</p>
 <p>LP-11 at 1.015 V with VDDIO = 1.765 V gives LP-high = 57.5% of VDDIO — barely above the 55% threshold. The LP driver&#x27;s output impedance combined with the 1.016 V level suggests possible over-termination or an impedance mismatch pulling the LP level down.</p>
 <p><strong>Check:</strong><br>- SN65DSI83 input termination — the bridge has internal 200 Ω LP termination; verify no external termination resistors are double-loading the LP driver<br>- Trace length on LP lines — should be ≤ 100 mm for 432 Mbit/s</p>
 <p>### 6.4 MEDIUM — CLK Lane Differential Asymmetry</p>
 <p>The CLK lane consistently shows asymmetric swings: +195 mV / −137 mV (common mode offset ≈ +29 mV). While the total differential amplitude (166 mV) is within spec, the positive/negative asymmetry suggests a <strong>DC offset in the CLK driver or unequal termination on CLK+ vs CLK−</strong>.</p>
 <p><strong>Check:</strong><br>- AC-coupling capacitor values on CLK+ and CLK− (should be matched within 1%)<br>- PCB trace length matching between CLK+ and CLK− (should be within 0.1 mm)</p>
 <p>### 6.5 LOW — DAT Lane Sub-140 mV Excursions</p>
 <p>While not causing the flicker, the DAT lane&#x27;s occasional high sub-140 mV sample counts (up to 3846) indicate marginal eye opening during worst-case data patterns. After fixing the SoT timing:<br>- Monitor for bit errors on long-running sessions<br>- If issues persist, consider reducing DAT lane trace stub lengths or adding matched termination</p>
 <ul><li></li></ul>
 <p>## 7. Overall Signal Health &amp; Flicker Risk Summary</p>
 <p><strong>The HS signal quality is adequate</strong> — amplitudes, rise times, jitter, and supply rail are all within acceptable bounds and show no degradation trend. <strong>The flicker is entirely caused by the &#x27;Round Best&#x27; PHY timing mode</strong>, which programs 5 register fields below D-PHY v</p>
 <p class="tokens">Tokens: 45873 in / 4096 out</p>
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 <h1>MIPI D-PHY Analysis Report</h1>
 <div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 5 of 30 display load sessions (17%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>1302</td><td>20260415_151649</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.014 V</td></tr><tr><td>1306</td><td>20260415_151816</td><td>dat</td><td style='color:red'>0.9 ns</td><td>0.0 ns</td><td>1.016 V</td></tr><tr><td>1309</td><td>20260415_151921</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.3 ns</td><td>1.014 V</td></tr><tr><td>1315</td><td>20260415_152132</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.5 ns</td><td>1.015 V</td></tr><tr><td>1324</td><td>20260415_152447</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.5 ns</td><td>1.016 V</td></tr>
  </table>
 </div>
 <details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>1299</td><td>20260415_151544</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1300</td><td>20260415_151606</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1301</td><td>20260415_151628</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1302</td><td>20260415_151649</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1303</td><td>20260415_151711</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1304</td><td>20260415_151732</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1305</td><td>20260415_151754</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1306</td><td>20260415_151816</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1307</td><td>20260415_151838</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1308</td><td>20260415_151900</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1309</td><td>20260415_151921</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1310</td><td>20260415_151943</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1311</td><td>20260415_152005</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1312</td><td>20260415_152027</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1313</td><td>20260415_152049</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1314</td><td>20260415_152110</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1315</td><td>20260415_152132</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1316</td><td>20260415_152154</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1317</td><td>20260415_152216</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1318</td><td>20260415_152237</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1319</td><td>20260415_152259</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1320</td><td>20260415_152320</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1321</td><td>20260415_152342</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1322</td><td>20260415_152404</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1323</td><td>20260415_152425</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1324</td><td>20260415_152447</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1325</td><td>20260415_152509</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1326</td><td>20260415_152531</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1327</td><td>20260415_152553</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>1328</td><td>20260415_152614</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
 </details>
 <p class="meta">
  <strong>Generated:</strong> 2026-04-15 15:31:13 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 1299–1328 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
 </p>
 <p># MIPI D-PHY Signal Integrity Analysis Report</p>
 <p>## Batch: Captures 1299–1328 (30 pipeline load/unload cycles)</p>
 <ul><li></li></ul>
 <p>## 1. Consistent Spec Concerns</p>
 <p>### A. Register Timing — Universal, Every Capture<br>All 30 captures show identical register values (`Round Best` mode) with <strong>5 D-PHY v1.1 violations</strong>:</p>
 <p>| Parameter | Measured | Spec Min | Deficit | Severity |<br>|-----------|----------|----------|---------|----------|<br>| THS_EXIT | 92.6 ns | 100.0 ns | −7.4 ns | <strong>HIGH</strong> — affects LP→HS exit handshake |<br>| TCLK_PREPARE | 37.0 ns | 38.0 ns | −1.0 ns | <strong>CRITICAL</strong> — clock SoT preamble too short |<br>| TCLK_TRAIL | 55.6 ns | 60.0 ns | −4.4 ns | MODERATE — affects HS→LP teardown |<br>| TCLK_PREPARE+TCLK_ZERO | 296.3 ns | 300.0 ns | −3.7 ns | <strong>CRITICAL</strong> — clock lane init sequence truncated |<br>| THS_PREPARE+THS_ZERO | 166.7 ns | 168.2 ns | −1.5 ns | <strong>CRITICAL</strong> — data lane SoT sequence truncated |</p>
 <p><strong>Key insight:</strong> The TCLK_PREPARE and THS_PREPARE+THS_ZERO violations directly shorten the SoT preamble the SN65DSI83 must detect. Combined with THS_EXIT being short, the receiver has a <strong>compressed detection window</strong> on every single startup. The system works most of the time because the SN65DSI83 has some internal tolerance, but the margins are razor-thin.</p>
 <p>### B. LP-Exit Duration — Universal Violation<br><strong>Every capture with LP data</strong> (28 of 30) shows LP exit → HS of <strong>0–4 ns</strong> against a spec minimum of <strong>50 ns</strong>. This is not a measurement artifact — it confirms the PHY is driving LP-01/LP-00 states for effectively zero time at the scope&#x27;s resolution, consistent with the truncated TCLK_PREPARE and THS_PREPARE+THS_ZERO register values.</p>
 <p>### C. LP-11 Voltage — Marginal but Passing<br>LP-11 consistently measures <strong>1.014–1.016 V</strong> (spec 1.0–1.45 V). This is only <strong>14–16 mV above the lower spec limit</strong> on a 1.8 V VDDIO rail. With VDDIO measured at ~1.766 V, the LP-11 level is <strong>56.4% of VDDIO</strong> rather than the expected ~VDDIO. This suggests the LP drivers have significant series impedance or the probe loading/termination at the SN65DSI83 input is pulling the LP level down. While technically in-spec, this reduces the SN65DSI83&#x27;s LP-11 detect margin.</p>
 <p>### D. HS Amplitude — Clock Lane Asymmetry<br>Clock differential: consistently <strong>+195 / −137 mV</strong> (common mode +29 mV). The positive swing is 42% larger than negative, indicating a <strong>systematic offset in the clock lane driver or termination</strong>. The mean amplitude (~166 mV) is within spec but only 26 mV above the 140 mV floor. Multiple captures show <strong>20–124 settled samples below 140 mV</strong>, confirming the clock eye is clipping the spec floor on some transitions.</p>
 <p>Data lane amplitude (~187–195 mV) is better centered but also shows sub-140 mV samples in many captures.</p>
 <ul><li></li></ul>
 <p>## 2. Trends Across Captures</p>
 <p>### A. No Drift — System Is Stationary<br>| Parameter | Range Across 30 Captures | Trend |<br>|-----------|--------------------------|-------|<br>| CLK Vdiff amplitude | 166.1–166.9 mV | Flat (&lt; 1 mV variation) |<br>| DAT Vdiff amplitude | 186.5–223.9 mV | Capture-dependent (see §3) |<br>| CLK jitter p-p | 145.8–169.9 ps | No trend |<br>| CLK jitter RMS | 51.8–56.7 ps | No trend |<br>| LP-11 voltage | 1.014–1.016 V | Flat |<br>| 1.8 V mean | 1.764–1.771 V | Flat |<br>| 1.8 V droop | 7.2–18.3 mV | No trend |<br>| Register values | Identical all captures | No change |</p>
 <p><strong>Conclusion:</strong> There is no progressive degradation. The problem is purely a <strong>startup race condition</strong>, consistent with the reported bistable behaviour.</p>
 <p>### B. LP-Low Plateau — Bimodal Distribution<br>The LP-low plateau measurement shows a striking bimodal pattern:</p>
 <p>| LP-low Plateau | Count | Sessions | Flicker? |<br>|----------------|-------|----------|----------|<br>| <strong>342–348 ns</strong> | 16 | Good + some marginal | Mostly no |<br>| <strong>108 ns</strong> | 6 | Mixed | No (in these captures) |<br>| <strong>0–1 ns</strong> | 5 | <strong>1302, 1306, 1309, 1315, 1324</strong> | <strong>YES — all flicker</strong> |<br>| Error/missing | 2 | 1303, 1322 | Unknown |</p>
 <p>This is the <strong>smoking gun</strong>: when the LP-low plateau collapses to 0–1 ns, the SN65DSI83 cannot detect the SoT entry sequence and the bridge fails to lock. The 342 ns plateau corresponds to approximately <strong>18.5 byte-clock periods</strong> — consistent with the programmed THS_PREPARE + THS_ZERO = 9 bc on the data lane (the scope measures both the low-going prepare and zero states as one contiguous low region, and the clock lane&#x27;s TCLK_PREPARE + TCLK_ZERO = 16 bc adds to this window). When the PHY&#x27;s internal state machine occasionally <strong>skips or truncates the LP-01→LP-00 sequence</strong>, the plateau vanishes entirely.</p>
 <ul><li></li></ul>
 <p>## 3. Anomalies</p>
 <p>### A. Flicker Captures — LP-Low Plateau Absent<br><strong>Captures 1302, 1306, 1309, 1315, 1324</strong> (all confirmed flicker):<br>- LP-low plateau: <strong>0 ns</strong> (1302, 1309, 1315, 1324) or <strong>1 ns</strong> (1306)<br>- HS amplitude (single-ended): <strong>24–34 mV</strong> — dramatically lower than the ~104–120 mV seen in good sessions<br>- This low HS amplitude in flicker captures indicates the data lane <strong>never properly entered HS mode</strong> — the SoT handshake failed, and what the scope captures as &quot;HS&quot; is likely residual coupling or a partially driven state</p>
 <p>### B. Data Lane &quot;Only Negative Swings&quot; Warning<br>Many captures (both good and bad) report `Only negative swings in capture window` on DAT0 sig/proto channels. This is a <strong>probe/trigger alignment issue</strong>: the oscilloscope capture window happened to land on a data pattern that is predominantly one polarity. It does not indicate a fault, but it means the reported amplitude is a lower bound. This is benign.</p>
 <p>### C. Data Lane Amplitude Bimodality in Proto Captures<br>Several captures show DAT0 proto amplitudes of <strong>222–224 mV</strong> with an asymmetric swing (+200/−247 mV, CM = −23 mV):<br>- Captures 1301, 1304, 1322 (all non-flicker)<br>- These coincide with slightly lower clock frequencies (~213.4 MHz vs. nominal 216 MHz)<br>- This may represent a different data pattern in the capture window or a transient PLL settling artefact at startup. Not directly correlated with flicker.</p>
 <p>### D. Processing Errors<br>- <strong>Capture 1303</strong> and <strong>1322</strong>: `[lp_dat] ERROR: index 200000 is out of bounds` — the LP waveform processing script hit the end of the capture buffer, likely because the LP→HS transition occurred at the very edge of the acquisition window. These two captures could not be assessed for LP timing. Recommendation: increase capture record length or adjust trigger position.</p>
 <p>### E. DAT0 sig = 0.0 mV<br>Captures <strong>1304, 1305, 1317</strong>: `No HS signal detected` on DAT0 sig channel. The high-res capture window missed the data lane HS content entirely (either blanking interval or trigger misalignment). Not a hardware fault — the proto and LP captures from the same sessions are normal.</p>
 <ul><li></li></ul>
 <p>## 4. Supply Correlation Analysis</p>
 <p>### A. 1.8 V Supply vs. LP Anomalies</p>
 <p>| Capture | Flicker? | LP-low (ns) | V_mean (V) | V_min (V) | Droop (mV) | Ripple RMS (mV) |<br>|---------|----------|-------------|------------|-----------|------------|-----------------|<br>| 1302 | <strong>YES</strong> | 0 | 1.7656 | 1.7560 | 9.6 | 5.61 |<br>| 1306 | <strong>YES</strong> | 1 | 1.7665 | 1.7560 | 10.6 | 5.80 |<br>| 1309 | <strong>YES</strong> | 0 | 1.7655 | 1.7560 | 9.5 | 5.41 |<br>| 1315 | <strong>YES</strong> | 0 | 1.7667 | 1.7560 | 10.7 | 5.86 |<br>| 1324 | <strong>YES</strong> | 0 | 1.7656 | 1.7560 | 9.6 | 5.53 |<br>| <strong>Good avg</strong> | No | 108–348 | 1.766 | 1.756 | 10.5 | 5.70 |</p>
 <p><strong>Conclusion: No supply correlation.</strong> The flicker captures show identical supply characteristics to good captures:<br>- Mean voltage: indistinguishable (~1.766 V in both)<br>- Minimum voltage: identical (1.756 V)<br>- Droop: 9.5–10.7 mV for flicker vs. 7.2–18.3 mV for all captures — flicker sessions are actually in the *lower* droop range<br>- Ripple RMS: 5.41–5.86 mV — squarely in the middle of the full population</p>
 <p><strong>The 1.8 V supply is not the root cause.</strong> The supply is well within spec (1.71–1.89 V) at all times and shows no correlation with SoT failures.</p>
 <ul><li></li></ul>
 <p>## 5. WARNING/ERROR Explanation</p>
 <p>| Warning/Error | Likely Cause | Action |<br>|---------------|-------------|--------|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>PHY timing registers too short</strong> — THS_EXIT=5bc, THS_PREPARE+THS_ZERO=9bc produce SoT states near the minimum; PHY internal jitter occasionally eliminates them entirely | <strong>Switch to Round Up register values</strong> |<br>| `FLICKER SUSPECT: LP-low plateau absent or &lt; 50 ns` | SoT LP-01→LP-00 states skipped or truncated below scope resolution; SN65DSI83 cannot detect Start-of-Transmission | <strong>Root cause — register fix required</strong> |<br>| `Only negative swings in capture window` | Scope triggered on a data symbol that happened to be low for the entire capture window; amplitude underestimated | Benign — no action needed. Increase capture length if accurate amplitude stats are required |<br>| `No HS signal detected — line may be in LP state or idle` | High-res capture window landed in blanking interval or LP state | Adjust trigger delay for sig captures; not a hardware fault |<br>| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal — Samsung DSIM uses continuous clock mode; CLK lane doesn&#x27;t return to LP-11 between frames | Expected behaviour, no action |<br>| `101/113/... settled samples below 140 mV` | Clock amplitude of 166 mV has only 26 mV margin above 140 mV floor; transitions and ISI dip below threshold | Monitor — not immediately actionable but indicates the PHY is near its low-amplitude limit |<br>| `index 200000 is out of bounds` | Processing script ran past end of LP capture buffer | Increase scope record length or adjust trigger position to ensure SoT transition is fully captured |</p>
 <ul><li></li></ul>
 <p>## 6. Actionable Recommendations</p>
 <p>### IMMEDIATE — Register Fix (PRIMARY FIX)</p>
 <p><strong>Switch from `Round Best` to `Round Up` PHY timing values:</strong></p>
 <p>```<br># From device tree or driver override:<br>DSIM_PHYTIMING  (0xb4): 0x00000306  (was 0x00000305)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04  (was 0x020e0a03)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706  (was 0x00030605)<br>```</p>
 <p>Field-by-field changes:</p>
 <p>| Field | Old (bc) | New (bc) | Old (ns) | New (ns) | Spec Min | Effect |<br>|-------|----------|----------|----------|----------|----------|--------|<br>| THS_EXIT | 5 | <strong>6</strong> | 92.6 | 111.1 | 100.0 | Now compliant |<br>| TCLK_PREPARE | 2 | <strong>3</strong> | 37.0 | 55.6 | 38.0 | Now compliant, +50% margin |<br>| TCLK_ZERO | 14 | <strong>15</strong> | 259.3 | 277.8 | (combined) | — |<br>| TCLK_PREPARE+ZERO | 16 | <strong>18</strong> | 296.3 | 333.3 | 300.0 | Now compliant, +11% margin |<br>| TCLK_TRAIL | 3 | <strong>4</strong> | 55.6 | 74.1 | 60.0 | Now compliant |<br>| THS_ZERO | 6 | <strong>7</strong> | 111.1 | 129.6 | (combined) | — |<br>| THS_PREPARE+ZERO | 9 | <strong>10</strong> | 166.7 | 185.2 | 168.2 | Now compliant, +10% margin |<br>| THS_TRAIL | 5 | <strong>6</strong> | 92.6 | 111.1 | 69.3 | Extra margin |</p>
 <p><strong>Implementation path — samsung-dsim driver:</strong></p>
 <p>The samsung-dsim (sec-dsim) driver computes these values in `samsung_dsim_set_phy_timing()`. The rounding mode is typically controlled by the `samsung,phy-timing` property or an internal calculation. Options:</p>
 <ol><li><strong>Preferred:</strong> Patch the driver&#x27;s timing calculation to use ceiling (round-up) instead of round-to-nearest for all parameters. This is a one-line change in the rounding function.</li><li><strong>Alternative:</strong> Override the timing registers directly via device tree `samsung,phy-timing = &lt;0x00000306 0x030f0a04 0x00030706&gt;;` if the driver supports it.</li><li><strong>Fallback:</strong> Write the registers directly from userspace after boot via `memtool` / `devmem2` as a validation step, then commit the change to the driver.</li></ol>
 <p>### SECONDARY — LP-11 Voltage Investigation</p>
 <p>The LP-11 level of 1.014–1.016 V (56% of VDDIO) is unusually low. While in-spec, it suggests:<br>- Check for <strong>excessive series resistance</strong> in the LP driver path (SOM trace, connector, cable to SN65DSI83)<br>- Verify the SN65DSI83 input termination matches the design — its LP input impedance may be loading the line excessively<br>- Confirm MIPI_DPHY_CON register (if accessible) is set for correct LP driver impedance</p>
 <p>### TERTIARY — Clock Lane Amplitude Asymmetry</p>
 <p>The +195/−137 mV asymmetry (CM offset +29 mV) on the clock lane suggests:<br>- Slight termination mismatch between CLK_P and CLK_N at the receiver<br>- Or a systematic PHY driver offset<br>- While not causing flicker, it reduces the clock eye margin. <strong>Check 100Ω differential termination</strong> at the SN65DSI83 CLK input and verify PCB trace matching.</p>
 <p>### MONITORING</p>
 <p>After applying the</p>
 <p class="tokens">Tokens: 45440 in / 4096 out</p>
 </body>
 </html>
--- a/reports/flicker_log.csv
+++ b/reports/flicker_log.csv
@@ -45,3 +45,27 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v
 2026-04-13 14:15:04,20260413_140238,0803,dat,0.2,2.9,1.017
 2026-04-13 14:15:12,20260413_140509,0810,dat,0.2,0.7,1.016
 2026-04-13 14:15:34,20260413_141222,0830,dat,0.2,3.4,1.016
 2026-04-15 07:55:39,20260415_074230,0137,dat,0.3,1.3,1.015
 2026-04-15 07:55:50,20260415_074608,0147,dat,0.3,2.3,1.015
 2026-04-15 09:00:34,20260415_085420,0323,dat,0.3,2.2,1.015
 2026-04-15 10:04:53,20260415_095344,0475,dat,0.3,2.0,1.015
 2026-04-15 10:05:11,20260415_095826,0488,dat,0.3,1.8,1.015
 2026-04-15 10:05:15,20260415_095953,0492,dat,0.3,3.6,1.015
 2026-04-15 11:09:27,20260415_105739,0639,dat,0.3,2.4,1.015
 2026-04-15 11:09:31,20260415_105845,0642,dat,0.3,2.9,1.016
 2026-04-15 11:09:40,20260415_110055,0648,dat,0.3,2.1,1.016
 2026-04-15 12:14:46,20260415_120723,0819,dat,0.2,2.3,1.014
 2026-04-15 12:14:49,20260415_120807,0821,dat,0.2,2.8,1.015
 2026-04-15 12:15:01,20260415_121123,0830,dat,0.3,2.5,1.015
 2026-04-15 13:19:27,20260415_131221,0985,dat,0.3,0.1,1.015
 2026-04-15 13:19:30,20260415_131304,0987,dat,0.3,0.2,1.016
 2026-04-15 13:19:41,20260415_131558,0995,dat,0.3,4.0,1.016
 2026-04-15 14:24:05,20260415_141042,1133,dat,0.3,3.4,1.016
 2026-04-15 14:24:31,20260415_141630,1149,dat,0.2,3.4,1.015
 2026-04-15 14:24:35,20260415_141713,1151,dat,0.2,2.4,1.015
 2026-04-15 14:24:38,20260415_141735,1152,dat,0.2,3.1,1.015
 2026-04-15 15:28:59,20260415_151649,1302,dat,0.3,2.3,1.014
 2026-04-15 15:29:05,20260415_151816,1306,dat,0.9,0.0,1.016
 2026-04-15 15:29:10,20260415_151921,1309,dat,0.2,2.3,1.014
 2026-04-15 15:29:17,20260415_152132,1315,dat,0.3,2.5,1.015
 2026-04-15 15:29:29,20260415_152447,1324,dat,0.3,3.5,1.016