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<title>MIPI Analysis — Captures 0967–0996</title>
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<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0985</td><td>20260415_131221</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.1 ns</td><td>1.015 V</td></tr><tr><td>0987</td><td>20260415_131304</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.2 ns</td><td>1.016 V</td></tr><tr><td>0995</td><td>20260415_131558</td><td>dat</td><td style='color:red'>0.3 ns</td><td>4.0 ns</td><td>1.016 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0967</td><td>20260415_130550</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0968</td><td>20260415_130612</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0969</td><td>20260415_130633</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0970</td><td>20260415_130655</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0971</td><td>20260415_130717</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0972</td><td>20260415_130738</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0973</td><td>20260415_130800</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0974</td><td>20260415_130822</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0975</td><td>20260415_130844</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0976</td><td>20260415_130906</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0977</td><td>20260415_130927</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0978</td><td>20260415_130949</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0979</td><td>20260415_131011</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0980</td><td>20260415_131033</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0981</td><td>20260415_131054</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0982</td><td>20260415_131116</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0983</td><td>20260415_131138</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0984</td><td>20260415_131200</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0985</td><td>20260415_131221</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0986</td><td>20260415_131243</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0987</td><td>20260415_131304</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0988</td><td>20260415_131326</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0989</td><td>20260415_131348</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0990</td><td>20260415_131409</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0991</td><td>20260415_131431</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0992</td><td>20260415_131452</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0993</td><td>20260415_131514</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0994</td><td>20260415_131536</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0995</td><td>20260415_131558</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0996</td><td>20260415_131619</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-15 13:21:17 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0967–0996 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0967–0996</p>
<p>## 1. Executive Summary</p>
<p><strong>The system is running with &#x27;Round Best&#x27; PHY timing registers that have 5 D-PHY v1.1 violations. The SoT LP-low plateau is bimodal: ~342 ns (good) or 0 ns (flicker). The three confirmed flicker events (0985, 0987, 0995) all show LP-low plateau = 0 ns — the LP-01/LP-00 SoT states are completely absent, so the SN65DSI83 never detects start-of-transmission. Switching to the &#x27;Round Up&#x27; register set eliminates all five timing violations and is the single highest-impact fix.</strong></p>
<ul><li></li></ul>
<p>## 2. Consistent Spec Concerns</p>
<p>### 2.1 Register Timing Violations (100% of captures)</p>
<p>Every single capture reads identical non-compliant registers:</p>
<p>| Parameter | Programmed | Actual | Spec Min | Deficit |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
<p><strong>Critical observation:</strong> All five violations are by margins of 1–7.4 ns — fractions of one byte-clock. This is exactly the kind of marginal non-compliance that works *most of the time* but fails non-deterministically when PVT (process, voltage, temperature) variations or internal PLL jitter push the actual analogue timing slightly shorter than the already-short programmed value. This directly explains the bistable 10% failure rate.</p>
<p>### 2.2 LP-low Plateau Bimodality</p>
<p>Across the 26 captures with valid LP data:</p>
<p>| LP-low Plateau | Count | Flicker? |<br>|---|---|---|<br>| <strong>~342 ns</strong> | 12 | No (all good) |<br>| <strong>~108 ns</strong> | 11 | No (all good) |<br>| <strong>0 ns</strong> | <strong>3</strong> | <strong>YES — all three flicker events</strong> |</p>
<p>The 342 ns and 108 ns populations both represent successful SoT sequences (the bridge locks). The 0 ns population represents a <strong>completely collapsed SoT</strong> — LP-01→LP-00 states are either not emitted or so brief they are unresolvable. The SN65DSI83 cannot detect the data lane SoT entry point and fails to lock.</p>
<p><strong>Root cause chain:</strong> THS_PREPARE+THS_ZERO is programmed to 166.7 ns versus the 168.2 ns minimum. When the PHY&#x27;s internal PLL phase happens to shorten this by even ~2 ns, the SoT LP-low states collapse below the bridge&#x27;s detection threshold. The TCLK_PREPARE violation (37.0 vs 38.0 ns) compounds this by occasionally mis-aligning the clock lane&#x27;s HS entry relative to the data lane&#x27;s SoT, so the bridge misses the synchronisation window entirely.</p>
<p>### 2.3 LP Exit Duration</p>
<p>| LP exit → HS | Occurrences | Notes |<br>|---|---|---|<br>| <strong>≥ 113 ns</strong> | 5 | Spec-compliant (≥ 50 ns) |<br>| <strong>2–4 ns</strong> | 18 | <strong>Spec violation — below 50 ns</strong> |<br>| <strong>0 ns</strong> | 3 | Flicker events |</p>
<p><strong>23 of 26 valid captures (88%) show LP exit &lt; 50 ns.</strong> The measurement algorithm reports 2–4 ns for the non-flicker cases, which likely represents the LP-11→LP-01 transition being too fast for the measurement resolution rather than truly absent. However, only when it reaches 0 ns does flicker occur. The extremely short LP exit durations across the board confirm that TLPX (55.6 ns) and THS_PREPARE (55.6 ns) are at the very bottom of their acceptable ranges, leaving zero margin.</p>
<p>### 2.4 HS Amplitude Concerns</p>
<p><strong>Clock lane:</strong> Consistently ~165.5 mV differential — within spec (140–270 mV) but at the <strong>low end</strong> (only 25 mV margin above 140 mV floor). Every proto/clk capture shows settled samples below 140 mV (28–136 per capture), indicating ISI/eye-closure at transitions.</p>
<p><strong>Data lane:</strong> Nominal amplitude 186–199 mV but with persistent below-140 mV violations (up to 5546 samples in capture 0969). The data eye is stressed.</p>
<p><strong>Clock asymmetry:</strong> Consistent +194 mV / −136 mV split on CLK lane (common mode +28–30 mV). This ~58 mV positive/negative imbalance suggests a small DC offset in the CLK driver or termination mismatch. While within spec, it reduces negative-swing noise margin.</p>
<p>### 2.5 LP-11 Voltage</p>
<p>All captures: <strong>1.014–1.016 V</strong> (spec 1.0–1.45 V). This is at the <strong>absolute floor</strong> of the LP-11 specification. The nominal VDDIO is 1.8 V; LP-11 should be at or near VDDIO. At 1.015 V the LP driver is operating with only ~15 mV of margin above the 1.0 V floor.</p>
<p><strong>This is a secondary concern.</strong> The low LP-11 voltage indicates the MIPI PHY LP pull-ups are sourcing from a rail that may be loaded or the pull-up resistors are too weak. While it doesn&#x27;t directly cause the flicker (the SoT failure does), it reduces the LP-11→LP-00 voltage swing available for the bridge&#x27;s LP state detector, making SoT detection harder.</p>
<ul><li></li></ul>
<p>## 3. Trend Analysis</p>
<p>### 3.1 No Temporal Drift</p>
<p>| Parameter | Range across 30 captures | Trend |<br>|---|---|---|<br>| CLK Vdiff | 164.8–166.8 mV | <strong>Flat — no drift</strong> |<br>| CLK freq | 213.0–219.2 MHz | Stable ±1.5% |<br>| CLK jitter RMS | 52.1–56.3 ps | <strong>Flat</strong> |<br>| LP-11 voltage | 1.014–1.016 V | <strong>Flat</strong> |<br>| 1.8 V mean | 1.764–1.770 V | <strong>Flat</strong> |<br>| 1.8 V droop | 7.9–16.2 mV | <strong>Mostly flat</strong> (one outlier at 16.2 mV — capture 0975) |</p>
<p><strong>Conclusion:</strong> There is no progressive degradation. The system is stable between loads. The flicker is purely a per-load-cycle non-deterministic event, consistent with the bistable behaviour description.</p>
<p>### 3.2 Flicker Events Are NOT Correlated With Any Measured Analogue Trend</p>
<p>The three flicker captures (0985, 0987, 0995) show:<br>- Normal supply (droop 8.7–10.3 mV, within the non-flicker range of 7.9–16.2 mV)<br>- Normal CLK amplitude and jitter<br>- Normal LP-11 voltage<br>- Normal HS burst duration</p>
<p><strong>The only distinguishing feature is LP-low plateau = 0 ns.</strong> This confirms the root cause is digital timing (PHY state machine) not analogue signal quality.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation</p>
<p>### 4.1 1.8 V Supply Health</p>
<p>| Metric | Range | Spec | Status |<br>|---|---|---|---|<br>| Mean voltage | 1.764–1.770 V | 1.71–1.89 V | ✓ but 54 mV below nominal 1.8 V |<br>| Min voltage | 1.748–1.760 V | ≥ 1.71 V | ✓ with 38–50 mV margin |<br>| Droop depth | 7.9–16.2 mV | — | Acceptable |<br>| Ripple RMS | 5.25–6.01 mV | — | Good |</p>
<p>### 4.2 Droop vs. Flicker Correlation</p>
<p>| Capture | Droop (mV) | Flicker? |<br>|---|---|---|<br>| 0985 | 8.7 | <strong>YES</strong> |<br>| 0987 | 10.3 | <strong>YES</strong> |<br>| 0995 | 8.9 | <strong>YES</strong> |<br>| 0975 | <strong>16.2</strong> | No |<br>| 0981 | 10.1 | No |</p>
<p><strong>No correlation.</strong> The worst droop (16.2 mV, capture 0975) did NOT produce flicker. The flicker captures have unremarkable droop. <strong>Supply noise is not the trigger.</strong></p>
<p>### 4.3 LP-11 Voltage vs. Supply</p>
<p>LP-11 at 1.015 V with VDDIO at 1.765 V means the LP pull-up drops ~750 mV. This is consistent with a ~1.2 kΩ pull-up driving ~600 µA into the line termination, or a weak internal pull-up. It does not vary with supply — it&#x27;s a fixed resistive divider, not a transient issue.</p>
<ul><li></li></ul>
<p>## 5. Anomaly Analysis</p>
<p>### 5.1 Missing LP Data (Captures 0971, 0972, 0988, 0996)</p>
<p>```<br>[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000<br>```</p>
<p><strong>Cause:</strong> The LP analysis algorithm&#x27;s edge-search exceeded the capture buffer boundary. This occurs when the LP-11→LP-00 transition happens very late in the capture window or the trigger placed the SoT event at the extreme end of the acquisition memory.</p>
<p><strong>Action:</strong> Increase scope pre-trigger holdoff or LP capture record length by 20%. Not a hardware fault.</p>
<p>### 5.2 Data Lane &quot;Only Negative Swings&quot; / &quot;No HS Signal&quot;</p>
<p>~60% of sig/dat and proto/dat captures show only negative differential swings or zero amplitude. This is a <strong>scope triggering/windowing artifact</strong> — the high-speed capture window (a few ns) happened to land on a data lane period where only one polarity was present (e.g., during a long run of &#x27;0&#x27; bits in the pixel data). The data lane carries packet content, not a 50/50 clock, so this is expected and benign.</p>
<p><strong>Action:</strong> None required. The proto/dat captures that do resolve both polarities show proper ~195 mV amplitude.</p>
<p>### 5.3 Below-140 mV Samples on Data Lane</p>
<p>The data lane consistently shows hundreds to thousands of settled samples below the 140 mV Vdiff floor. This is <strong>ISI (inter-symbol interference)</strong> from consecutive same-polarity transitions on the data lane. At 432 Mbit/s with ~165 ps rise times and a data eye that is already smaller than the clock eye (data has random jitter; clock does not), this is expected for a PCB trace of moderate length.</p>
<p><strong>Risk:</strong> The SN65DSI83 has its own LP/HS detection threshold. If the data lane eye is marginal, the bridge&#x27;s CDR could occasionally fail to lock, but this would manifest as persistent HS errors, not the observed bistable SoT failure. This is a secondary concern.</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### 6.1 PRIMARY FIX — Switch to &#x27;Round Up&#x27; Register Set</p>
<p><strong>This is the single fix that addresses the root cause.</strong> Patch the samsung-dsim driver (or device tree overlay) to program:</p>
<p>```<br>PHYTIMING (0xb4) = 0x00000306 (THS_EXIT: 5→6)<br>PHYTIMING1 (0xb8) = 0x030f0a04 (TCLK_PREPARE: 2→3, TCLK_ZERO: 14→15, TCLK_TRAIL: 3→4)<br>PHYTIMING2 (0xbc) = 0x00030706 (THS_ZERO: 6→7, THS_TRAIL: 5→6)<br>```</p>
<p>This eliminates all 5 D-PHY violations and provides adequate margin:</p>
<p>| Parameter | Round Best | Round Up | Spec Min | Margin |<br>|---|---|---|---|---|<br>| THS_EXIT | 92.6 ns | <strong>111.1 ns</strong> | 100.0 ns | +11.1 ns |<br>| TCLK_PREPARE | 37.0 ns | <strong>55.6 ns</strong> | 38.0 ns | +17.6 ns |<br>| TCLK_TRAIL | 55.6 ns | <strong>74.1 ns</strong> | 60.0 ns | +14.1 ns |<br>| TCLK_PREP+ZERO | 296.3 ns | <strong>333.3 ns</strong> | 300.0 ns | +33.3 ns |<br>| THS_PREP+ZERO | 166.7 ns | <strong>185.2 ns</strong> | 168.2 ns | +17.0 ns |</p>
<p><strong>Expected result:</strong> The LP-low plateau should consistently appear at ≥100 ns on every load cycle. The 0 ns collapse events should be eliminated. Flicker rate should drop from 10% to 0%.</p>
<p>### 6.2 Driver Patch Location</p>
<p>In the `samsung-dsim` driver (`drivers/gpu/drm/bridge/samsung-dsim.c`), the timing calculation function `samsung_dsim_set_phy_timing()` uses a rounding mode. The current code path is selecting floor/truncation (&quot;Round Best&quot;). Either:</p>
<ol><li><strong>Modify the rounding function</strong> to always round up to the next byte-clock boundary when the calculated continuous-time value is within 1 bc of the spec minimum, OR</li><li><strong>Apply a static override</strong> via device tree properties `samsung,phy-timing = &lt;0x00000306 0x030f0a04 0x00030706&gt;;` if the driver supports it, OR</li><li><strong>Patch the register values directly</strong> in the driver&#x27;s `samsung_dsim_atomic_enable()` path using `regmap_write()` after the default timing is programmed.</li></ol>
<p>### 6.3 SECONDARY — Investigate Low LP-11 Voltage</p>
<p>LP-11 at 1.015 V (vs. 1.8 V VDDIO) indicates the LP driver pull-ups are too weak or there is excessive loading on the LP lines. Check:</p>
<ul><li><strong>SN65DSI83 LP input bias current</strong> (datasheet: should be &lt; 10 µA in LP-11)</li><li><strong>Series resistors on LP lines</strong> (some layouts add 200–330 Ω for ESD; these can drop LP voltage)</li><li><strong>Scope probe loading</strong> (1 MΩ / 10 pF probes on LP lines will load them; use FET probes or remove probes after measurement)</li></ul>
<p>While this is not the flicker root cause, improving LP-11 to &gt;1.2 V would give the bridge more SoT detection margin.</p>
<p>### 6.4 TERTIARY — Clock Lane Amplitude Margin</p>
<p>CLK Vdiff at ~165 mV with a 140 mV floor leaves only 25 mV margin. At the board level:<br>- Verify CLK± trace impedance matching (target 100 Ω differential)<br>- Check for stub lengths on CLK pair (any via or T-junction &gt; 1 mm adds reflection)<br>- Ensure CLK termination resistor (100 Ω) is placed within 2 mm of the SN65DSI83 input pins</p>
<p>This is not urgent but would improve long-term reliability across temperature.</p>
<p>### 6.5 Scope Capture Improvements</p>
<ul><li><strong>Increase LP capture record length</strong> to 250k points to avoid the index-out-of-bounds errors</li><li><strong>Add a second trigger condition</strong> on DAT0_LP going below 0.5 V to ensure the LP-00 state is always captured within the window</li><li><strong>Use math channel</strong> for differential LP (Dp−Dn) in addition to single-ended to better resolve LP-01 vs LP-00</li></ul>
<ul><li></li></ul>
<p>## 7. Overall Assessment</p>
<ul><li></li></ul>
<p class="tokens">Tokens: 44774 in / 4096 out</p>
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