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<title>MIPI Analysis — Captures 0635–0664</title>
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<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 3 of 30 display load sessions (10%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0639</td><td>20260415_105739</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0642</td><td>20260415_105845</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.9 ns</td><td>1.016 V</td></tr><tr><td>0648</td><td>20260415_110055</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.1 ns</td><td>1.016 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0635</td><td>20260415_105612</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0636</td><td>20260415_105634</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0637</td><td>20260415_105655</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0638</td><td>20260415_105717</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0639</td><td>20260415_105739</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0640</td><td>20260415_105801</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0641</td><td>20260415_105823</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0642</td><td>20260415_105845</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0643</td><td>20260415_105906</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0644</td><td>20260415_105928</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0645</td><td>20260415_105950</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0646</td><td>20260415_110011</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0647</td><td>20260415_110033</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0648</td><td>20260415_110055</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0649</td><td>20260415_110116</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0650</td><td>20260415_110138</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0651</td><td>20260415_110200</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0652</td><td>20260415_110222</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0653</td><td>20260415_110243</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0654</td><td>20260415_110305</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0655</td><td>20260415_110326</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0656</td><td>20260415_110349</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0657</td><td>20260415_110410</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0658</td><td>20260415_110432</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0659</td><td>20260415_110454</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0660</td><td>20260415_110515</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0661</td><td>20260415_110537</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0662</td><td>20260415_110559</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0663</td><td>20260415_110621</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0664</td><td>20260415_110642</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-15 11:11:34 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0635–0664 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664 (30 Sessions)</p>
<ul><li></li></ul>
<p>## 1. Consistent Spec Concerns</p>
<p>### A. PHY Timing Registers: 5 D-PHY v1.1 Violations (Every Capture)</p>
<p>All 30 captures show <strong>identical</strong> register values — the &#x27;Round Best&#x27; non-compliant mode:</p>
<p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|---|---|---|---|---|<br>| <strong>THS_EXIT</strong> | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| <strong>TCLK_PREPARE</strong> | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| <strong>TCLK_TRAIL</strong> | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| <strong>TCLK_PREPARE+TCLK_ZERO</strong> | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| <strong>THS_PREPARE+THS_ZERO</strong> | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
<p><strong>Impact:</strong> The first two violations (TCLK_PREPARE short, THS_PREPARE+THS_ZERO short) directly truncate the SoT sequence that the SN65DSI83 must detect. The short THS_EXIT means the data lane may not fully exit HS before re-entering LP, compressing the LP-01→LP-00 window. These are not &quot;almost compliant&quot; — they are systematically below spec on every single boot, creating a baseline where the SN65DSI83&#x27;s SoT detector is already operating at the edge of its capture window.</p>
<p>### B. LP-Exit Duration: Universally Violated</p>
<p><strong>Every single capture</strong> (where LP data was measurable) shows `LP exit → HS` of <strong>1–4 ns</strong> against a 50 ns spec minimum. Even the &quot;good&quot; (no-flicker) captures violate this. This means:</p>
<ul><li>The D-PHY LP-01→LP-00 state machine transitions are being driven far faster than spec</li><li>The PHY is effectively skipping the LP-01/LP-00 signalling states as distinct resolvable events</li><li>The SN65DSI83 must detect SoT from a sub-5 ns edge, which is unreliable by design</li></ul>
<p>### C. LP-11 Voltage: Marginal but Within Spec</p>
<p>All captures: <strong>1.011–1.016 V</strong> (spec 1.0–1.45 V). This is at the <strong>absolute floor</strong> of the valid range. At 1.015 V typical with 1.8 V VDDIO, the LP driver is pulling only 56% of supply. This is consistent with the weak LP driver output seen in this PHY at low VDDIO.</p>
<p>### D. CLK Lane: Continuous HS Mode</p>
<p>CLK is always in continuous HS — no LP states expected. This is normal for video-mode DSI but means the SN65DSI83 relies <strong>entirely</strong> on data lane SoT detection for frame sync.</p>
<p>### E. HS Amplitude: CLK Lane Near Floor</p>
<p>CLK differential amplitude: <strong>164.2–166.5 mV</strong> with consistent sub-140 mV samples (24–172 per capture). This is only 18% above the 140 mV minimum. DAT0 amplitude is healthier at ~187–195 mV but shows asymmetric swings in many captures.</p>
<ul><li></li></ul>
<p>## 2. Trends Across 30 Captures</p>
<p>### No Degradation Over Time — Confirms Bistable Model</p>
<p>| Parameter | Range | Trend |<br>|---|---|---|<br>| CLK Vdiff | 164.2–166.5 mV | <strong>Flat</strong> — no drift |<br>| DAT0 Vdiff | 186.0–223.2 mV | <strong>Flat</strong> (scatter from capture phase) |<br>| CLK jitter p-p | 148.5–174.6 ps | <strong>Flat</strong> — no progressive worsening |<br>| CLK jitter RMS | 53.1–57.4 ps | <strong>Flat</strong> |<br>| LP-11 voltage | 1.011–1.016 V | <strong>Flat</strong> — no droop over time |<br>| 1.8 V mean | 1.7635–1.7698 V | <strong>Flat</strong> |<br>| 1.8 V droop | 7.6–16.6 mV | <strong>No trend</strong> (random scatter) |<br>| LP-low plateau | 0–343 ns | <strong>Bimodal</strong> — see below |</p>
<p>The absence of any progressive trend confirms the bistable observation: the system doesn&#x27;t degrade into failure, it <strong>rolls dice at SoT</strong> and sticks with the result.</p>
<p>### LP-Low Plateau: Bimodal Distribution (Key Finding)</p>
<p>| LP-low plateau | Count | Outcome |<br>|---|---|---|<br>| <strong>342–348 ns</strong> | ~17 captures | All <strong>good</strong> (no flicker) |<br>| <strong>93–108 ns</strong> | ~7 captures | All <strong>good</strong> (no flicker) |<br>| <strong>0 ns</strong> (absent) | <strong>3 captures</strong> | All <strong>FLICKER</strong> (0639, 0642, 0648) |<br>| Parse error | 2 captures (0649, 0662) | Unknown |</p>
<p><strong>This is the smoking gun.</strong> The LP-low plateau clusters into three discrete populations:<br>- <strong>~343 ns:</strong> The PHY executes a full LP-00 state (approximately 18.5 bc = one byte-clock aligned interval). SN65DSI83 locks successfully.<br>- <strong>~108 ns:</strong> The PHY executes a shortened LP-00 state (~6 bc). Still long enough for SN65DSI83 to detect. No flicker.<br>- <strong>0 ns:</strong> The LP-00 state is <strong>completely absent</strong>. The data line transitions directly from LP-11 to HS without a resolvable LP-01/LP-00 sequence. <strong>The SN65DSI83 cannot detect SoT. Flicker results.</strong></p>
<p>The trimodal distribution (0 / ~108 / ~343 ns) with byte-clock-like quantisation strongly suggests the PHY&#x27;s internal SoT state machine has a <strong>race condition</strong> related to the programmed THS_PREPARE+THS_ZERO values being below spec. The short THS_EXIT (92.6 ns &lt; 100 ns) further compresses the timing window, and the short TCLK_PREPARE (37 ns &lt; 38 ns) means the clock lane SoT also runs tight. When all these jitter contributions align unfavourably, the LP-00 state collapses to zero.</p>
<ul><li></li></ul>
<p>## 3. Anomalies</p>
<p>### A. Flicker Captures — Absent LP-00 State</p>
<p>| Capture | LP-low | LP exit→HS | Flicker |<br>|---|---|---|---|<br>| <strong>0639</strong> | <strong>0 ns</strong> | 2 ns | <strong>YES</strong> |<br>| <strong>0642</strong> | <strong>0 ns</strong> | 3 ns | <strong>YES</strong> |<br>| <strong>0648</strong> | <strong>0 ns</strong> | 2 ns | <strong>YES</strong> |</p>
<p>All three flicker events share the identical signature: LP-low plateau = 0 ns. No other parameter (supply, amplitude, jitter) distinguishes them from good captures.</p>
<p>### B. DAT0 sig Captures: Intermittent 0.0 mV (No HS Detected)</p>
<p>Captures 0637, 0642, 0643, 0647, 0655, 0663 show `sig/dat Vdiff = 0.0 mV` — &quot;No HS signal detected.&quot; This occurs in both good and bad sessions. <strong>Most likely cause:</strong> The sig capture&#x27;s short acquisition window (high-res mode) triggered during an LP or blanking interval rather than during active HS data. This is a <strong>trigger timing artefact</strong>, not a signal fault — the proto/dat captures from the same sessions show healthy HS amplitude. No action needed on this artefact, but it means sig/dat data is unreliable for roughly 20% of captures.</p>
<p>### C. DAT0 proto: Intermittent &quot;Only Negative Swings&quot;</p>
<p>Captures 0635, 0642, 0653 show proto/dat with only negative differential excursions. This occurs when the proto window captures a run of identical data bits. It&#x27;s a <strong>capture phase artefact</strong>, not a signal issue.</p>
<p>### D. LP Parse Errors</p>
<p>Captures 0649 and 0662: `index 200000 is out of bounds` — the LP capture buffer was exhausted before the SoT event completed. Most likely cause: the trigger fired too late in the LP-11 dwell, and the HS burst extended past the capture window. These sessions could not be classified for flicker from LP data alone.</p>
<p>### E. DAT0 Sub-140 mV Sample Counts: High Variance</p>
<p>The number of settled samples below 140 mV on DAT0 proto varies wildly: 36 to <strong>8203</strong>. This is driven by how much of the capture window contains transition edges versus settled levels, and by the data pattern. The high counts (e.g., 0649: 8203; 0648: 5203; 0636: 5884) are <strong>not</strong> correlated with flicker — capture 0636 (5884 sub-140 mV samples) has LP-low = 108 ns and no flicker. These counts reflect HS eye opening, not SoT integrity.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Analysis</p>
<p>### 1.8 V Supply vs. LP Anomalies</p>
<p>| Parameter | Flicker captures (0639/0642/0648) | Good captures (all others) |<br>|---|---|---|<br>| 1.8 V mean | 1.7649–1.7654 V | 1.7635–1.7698 V |<br>| 1.8 V min | 1.7560 V | 1.7480–1.7600 V |<br>| Droop depth | 8.9–9.4 mV | 7.6–16.6 mV |<br>| Ripple RMS | 5.55–5.77 mV | 5.24–5.91 mV |</p>
<p><strong>No correlation.</strong> The flicker captures have <strong>average or better</strong> supply metrics. The worst droop (16.6 mV, capture 0637) and lowest min voltage (1.7480 V, capture 0637) occurred in a <strong>good</strong> session. The 1.8 V supply is <strong>not the cause</strong> of the intermittent SoT failure.</p>
<p>### LP-11 Voltage vs. Supply</p>
<p>LP-11 voltage (1.011–1.016 V) shows no correlation with supply droop. The LP driver output is limited by the PHY&#x27;s internal regulation, not the supply rail headroom (which has &gt;50 mV margin to the 1.71 V lower limit).</p>
<ul><li></li></ul>
<p>## 5. Warning/Error Explanations</p>
<p>| Warning/Error | Cause | Action |<br>|---|---|---|<br>| `LP exit duration X ns below spec min 50 ns` | <strong>Root cause issue.</strong> PHY SoT state machine transitions too fast due to short THS_PREPARE+THS_ZERO and THS_EXIT register values. | <strong>Fix registers</strong> — switch to &#x27;Round Up&#x27; mode |<br>| `FLICKER SUSPECT: LP-low plateau absent or &lt; 50 ns` | LP-00 state completely missing — PHY skipped the SoT low-going sequence. Direct consequence of timing violations. | Same register fix |<br>| `Only negative swings in capture window` | Proto/sig trigger captured a run of identical data bits (e.g., all-zero payload). Amplitude estimate is valid for the measured polarity. | Benign artefact — no action needed |<br>| `No HS signal detected — line may be in LP state or idle` | Sig capture (short window) triggered during blanking or LP interval. | Benign artefact — increase sig trigger holdoff or ignore |<br>| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal for video-mode DSI. CLK runs HS continuously. | Expected — no action |<br>| `X settled samples below 140 mV` (CLK) | CLK amplitude (165 mV) is close to floor; ISI and jitter push some transitions below 140 mV during ringing/settling. | Monitor but no immediate action — amplitude is 18% above floor |<br>| `index 200000 is out of bounds` | LP capture buffer too short to contain the full SoT→HS transition at this trigger position. | Increase capture depth or adjust trigger delay |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### CRITICAL — Fix #1: Switch to &#x27;Round Up&#x27; PHY Timing (Eliminates Root Cause)</p>
<p>Modify the samsung-dsim driver (or device tree) to program the <strong>&#x27;Round Up&#x27; compliant</strong> register values:</p>
<p>```<br>DSIM_PHYTIMING (0xb4): 0x00000306 ← THS_EXIT = 6 (was 5)<br>DSIM_PHYTIMING1 (0xb8): 0x030f0a04 ← TCLK_PREPARE = 3 (was 2), TCLK_ZERO = 15 (was 14), TCLK_TRAIL = 4 (was 3)<br>DSIM_PHYTIMING2 (0xbc): 0x00030706 ← THS_ZERO = 7 (was 6), THS_TRAIL = 6 (was 5)<br>```</p>
<p>This eliminates all 5 D-PHY violations and adds margin:<br>- THS_EXIT: 92.6 → 111.1 ns (11% margin over 100 ns spec)<br>- TCLK_PREPARE: 37.0 → 55.6 ns (46% margin over 38 ns spec)<br>- TCLK_PREPARE+TCLK_ZERO: 296.3 → 333.3 ns (11% margin over 300 ns spec)<br>- THS_PREPARE+THS_ZERO: 166.7 → 185.2 ns (10% margin over 168.2 ns spec)<br>- TCLK_TRAIL: 55.6 → 74.1 ns (23% margin over 60 ns spec)</p>
<p>The added THS_ZERO and TCLK_ZERO margin directly extends the LP-00 state duration, making the 0 ns plateau condition physically impossible.</p>
<p><strong>Implementation:</strong> In the `samsung-dsim` / `sec-dsim` driver, the timing calculation function uses `DIV_ROUND_UP` vs. truncation for these fields. Ensure the driver&#x27;s `dsim_calc_phy_timing()` or equivalent uses ceiling division. Alternatively, override via device tree `phy-timing` properties or a kernel patch to force the compliant values.</p>
<p>### IMPORTANT — Fix #2: Investigate LP-11 Voltage</p>
<p>LP-11 at 1.015 V is within spec but is only 15 mV above the 1.0 V floor. At this level, the SN65DSI83&#x27;s LP receiver has minimal noise margin. Potential improvements:</p>
<ul><li><strong>Verify VDDIO decoupling</strong> near the i.MX 8M Mini PHY VDDIO pins — add 100 nF ceramic if missing within 2 mm</li><li><strong>Check series resistance</strong> in the LP path — any added series termination on Dp/Dn will drop LP-11 voltage</li><li><strong>Verify the PHY&#x27;s LP driver bias</strong> — some Samsung DSIM implementations have a configurable LP output swing via an undocumented register or OTP setting</li></ul>
<p>### MONITORING — HS CLK Amplitude</p>
<p>CLK at 165 mV with sub-140 mV excursions is functional but leaves only 25 mV (18%) of margin. If trace length increases (board revision, flex cable, etc.), this will fail. Consider:</p>
<ul><li>Reviewing CLK lane termination (should be 100Ω differential at SN65DSI83 input)</li><li>Checking for stubs or vias in the CLK differential pair</li><li>Verifying the PHY&#x27;s HS driver impedance calibration (if configurable)</li></ul>
<p>### MINOR — Capture Infrastructure</p>
<ul><li>Increase LP capture buffer from 200k samples to ≥400k to avoid the index-out-of-bounds errors in captures 0649 and 0662</li><li>Adjust sig capture trigger holdoff to consistently land in active HS data, not blanking</li></ul>
<ul><li></li></ul>
<p>## 7. Summary</p>
<p><strong>The flicker root cause is definitively identified:</strong> the samsung-dsim PHY timing registers are programmed with &#x27;Round Best&#x27; (truncated) values that violate D-PHY v1</p>
<p class="tokens">Tokens: 45244 in / 4096 out</p>
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