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<title>MIPI Analysis — Captures 0137–0166</title>
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<h1>MIPI D-PHY Analysis Report</h1>
<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
padding:16px 20px;margin-bottom:28px;">
<h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 2 of 30 display load sessions (7%) flickered</h2>
<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
missed the SoT sequence and dropped a frame.<br>
LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
for the SN65DSI83 bridge to detect start-of-transmission.</p>
<table>
<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
<tr><td>0137</td><td>20260415_074230</td><td>dat</td><td style='color:red'>0.3 ns</td><td>1.3 ns</td><td>1.015 V</td></tr><tr><td>0147</td><td>20260415_074608</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr>
</table>
</div>
<details style="margin-bottom:24px;">
<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
DSI Register Snapshots (30 captures)
</summary>
<div style="overflow-x:auto;margin-top:8px;">
<table>
<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
<tr><td>0137</td><td>20260415_074230</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0138</td><td>20260415_074252</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260415_074314</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260415_074336</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260415_074357</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260415_074419</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260415_074441</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260415_074503</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260415_074524</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260415_074546</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260415_074608</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260415_074630</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260415_074651</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260415_074713</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260415_074735</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260415_074757</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260415_074818</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260415_074840</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260415_074902</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260415_074923</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260415_074945</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260415_075007</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260415_075029</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260415_075051</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260415_075113</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260415_075135</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260415_075156</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260415_075218</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260415_075239</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260415_075301</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
</table>
</div>
</details>
<p class="meta">
<strong>Generated:</strong> 2026-04-15 07:57:44 &nbsp;|&nbsp;
<strong>Scope:</strong> Captures 0137–0166 &nbsp;|&nbsp;
<strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166</p>
<p>## 1. Consistent Spec Concerns</p>
<p>### Register-Level Timing Violations (100% of captures)<br>Every single capture shows identical register values — the system is running <strong>&#x27;Round Best&#x27; mode</strong> with 5 D-PHY v1.1 violations:</p>
<p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|-----------|-----------|--------|----------|-----------|<br>| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
<p>These are not marginal — they are <strong>hardcoded violations</strong>. The byte-clock granularity (18.518 ns) means every field is either clearly below spec or clearly above; there is no jitter-induced ambiguity in the register domain.</p>
<p>### LP-Exit Timing (Universal Violation)<br><strong>Every capture with valid LP data</strong> (28 of 28) shows LP exit → HS duration of <strong>0–4 ns</strong> against a spec minimum of <strong>50 ns</strong>. This is a <strong>systematic hardware/driver issue</strong>, not a measurement artefact. The LP-01 and LP-00 SoT entry states are being driven for sub-nanosecond durations at the single-ended measurement resolution.</p>
<p>### LP-11 Voltage<br>All captures: <strong>1.013–1.016 V</strong> against spec 1.0–1.45 V. Technically passing, but sitting at the <strong>extreme low end</strong> — only 13–16 mV above the 1.0 V floor. This is consistent with the 1.8 V supply being at 1.765 V (low side of nominal) and the PHY LP driver having significant drop. A marginal LP-11 voltage reduces the SN65DSI83&#x27;s noise margin for detecting the LP-11 → LP-01 → LP-00 transition.</p>
<p>### HS Amplitude<br>- <strong>CLK lane</strong>: 161–173 mV differential — consistently passes 140 mV minimum but only by ~25 mV. Negative swing systematically weaker (+193 mV / −138 mV asymmetry → ~28 mV common-mode offset).<br>- <strong>DAT0 lane</strong>: 177–199 mV when properly captured — adequate but numerous sub-140 mV samples in proto captures (25–5098 per capture), indicating ISI/pattern-dependent amplitude dips.</p>
<p>### Clock Frequency<br>Mostly 215.6–216.2 MHz as expected. Occasional readings of 213.0–213.4 MHz and 218.1–219.1 MHz are within proto measurement window artefacts (windowing/gating), not real frequency excursions.</p>
<ul><li></li></ul>
<p>## 2. Trends Across Captures</p>
<p>### LP-Low Plateau Duration — The Critical Discriminator</p>
<p>| LP-Low Plateau | Count | Captures | Flicker? |<br>|---------------|-------|----------|----------|<br>| <strong>0 ns</strong> | 2 | 0137★, 0147★ | <strong>YES — both flicker events</strong> |<br>| <strong>108 ns</strong> | 5 | 0142, 0153, 0158, 0160, 0166 | No |<br>| <strong>342–343 ns</strong> | 19 | All others | No |<br>| <strong>348 ns</strong> (LP exit also ≥ 348 ns) | 4 | 0143, 0144, 0150, 0156, 0161 | No |<br>| <strong>Error/missing</strong> | 2 | 0148, 0162 | Unknown |</p>
<p><strong>Key finding</strong>: The LP-low plateau is <strong>tristable</strong> — it lands at ~0, ~108, or ~343 ns. The flicker events correspond <strong>exclusively</strong> to the 0 ns case, where the LP-01/LP-00 states are completely absent. The 108 ns captures are a partial SoT (approximately 6 byte-clocks — coincidentally close to THS_PREPARE+THS_ZERO = 9 bc) and are borderline but do not flicker in this batch. The 343 ns captures show a healthy SoT sequence.</p>
<p>This tristability is the <strong>smoking gun</strong>: the PHY&#x27;s internal SoT state machine has a race condition. The programmed THS_PREPARE+THS_ZERO (166.7 ns, 1.5 ns below spec) and TCLK_PREPARE+TCLK_ZERO (296.3 ns, 3.7 ns below spec) are below the minimum required for the receiver to detect the SoT sequence. When internal PLL/clock alignment at startup happens to compress these states further (or the state machine skips them entirely), the bridge never detects SoT.</p>
<p>### HS Amplitude — No Drift<br>CLK and DAT0 amplitudes are rock-stable across all 30 captures. No thermal or aging drift.</p>
<p>### Jitter — Stable<br>CLK jitter: 142–172 ps p-p, 50–53 ps RMS. No trend. Well within typical D-PHY budgets.</p>
<p>### 1.8 V Supply — Stable, No Correlation<br>Mean: 1.764–1.766 V. Droop: 8.5–14.1 mV. Ripple RMS: 5.3–5.9 mV. All within spec.</p>
<ul><li></li></ul>
<p>## 3. Anomalies</p>
<p>### A. Two Flicker Events (Captures 0137, 0147)<br>- <strong>LP-low plateau = 0 ns</strong> — LP-01/LP-00 states completely absent<br>- LP exit → HS = 1–2 ns (essentially instantaneous)<br>- HS amplitude in LP capture window: <strong>25–30 mV</strong> single-ended (vs. 106–119 mV in non-flicker captures)<br>- This ultra-low HS amplitude confirms the bridge <strong>never locked</strong> — it is seeing HS transitions but has not synchronised because SoT was never received</p>
<p>### B. Intermediate LP-Low (~108 ns) Captures (0142, 0153, 0158, 0160, 0166)<br>- LP-low is present but <strong>shortened by ~3×</strong> compared to normal (~343 ns)<br>- HS amplitude in LP window: 16–35 mV (same low range as flicker captures)<br>- These are <strong>near-misses</strong> — the SoT sequence exists but is abbreviated. The bridge manages to lock, but barely. With a less tolerant bridge or slightly different timing, these would flicker too.</p>
<p>### C. LP Data Processing Errors (Captures 0148, 0162)<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP transition occurred at or beyond the capture window edge. These represent captures where the trigger timing placed the SoT at the buffer boundary. Not a hardware fault; increase capture depth or adjust trigger delay.</p>
<p>### D. DAT0 &quot;Only Negative Swings&quot; (Majority of sig/dat captures)<br>Approximately 70% of sig/dat captures show only negative-going differential transitions. This is a <strong>capture window alignment issue</strong> — the high-res window is short enough that it may only contain one data phase. Not a real signal fault, but it means the positive-swing amplitude is not being validated for most captures. Recommend widening the sig capture window or using edge-triggered dual-window acquisition.</p>
<p>### E. DAT0 sig = 0.0 mV (Captures 0138, 0140, 0150, 0151, 0158, 0164)<br>The data line was in LP idle or between bursts during the high-res capture. Again a trigger alignment issue.</p>
<ul><li></li></ul>
<p>## 4. Supply Correlation Analysis</p>
<p>| Metric | Flicker (0137, 0147) | No-Flicker (avg of rest) | Correlation? |<br>|--------|---------------------|-------------------------|-------------|<br>| V_mean | 1.7656, 1.7655 V | 1.7652 V | <strong>None</strong> |<br>| V_min | 1.756, 1.756 V | 1.754 V | <strong>None</strong> |<br>| Droop | 9.6, 9.5 mV | 10.1 mV | <strong>None</strong> |<br>| Ripple RMS | 5.59, 5.49 mV | 5.59 mV | <strong>None</strong> |</p>
<p><strong>Conclusion: The 1.8 V supply is not the root cause.</strong> Droop and ripple are identical in flicker and non-flicker sessions. The supply is healthy and not contributing to the SoT failure.</p>
<p>The slightly low LP-11 voltage (1.015 V) is a <strong>constant</strong> across all captures and therefore cannot explain the intermittent behaviour. However, it does reduce the SN65DSI83&#x27;s detection margin, making the system more sensitive to the SoT timing violations.</p>
<ul><li></li></ul>
<p>## 5. WARNING/ERROR Explanation</p>
<p>| Warning | Cause | Action |<br>|---------|-------|--------|<br>| `LP exit duration N ns below spec min 50 ns` | PHY is not holding LP-01/LP-00 states for the required TLPX duration. The samsung-dsim PHY programmes TLPX=3 bc (55.6 ns) but the actual LP-low state exits in 0–4 ns. This means the LP driver is being overridden by the HS driver prematurely — a <strong>PHY state machine race</strong>. | Switch to &#x27;Round Up&#x27; register values |<br>| `FLICKER SUSPECT: LP-low plateau absent` | SoT LP-01→LP-00 sequence completely skipped | Root cause — see §6 |<br>| `Only negative swings in capture window` | Sig capture window too short / trigger phase alignment | Widen sig window or add trigger holdoff jitter |<br>| `No HS signal detected` | Sig capture window hit LP gap between bursts | Same as above |<br>| `N settled samples below 140 mV` | ISI-induced amplitude dips during data transitions | Expected at 432 Mbit/s with PCB trace losses; not a primary concern but monitor |<br>| `index 200000 out of bounds` | LP transition at capture buffer edge | Increase LP capture depth to 250k+ samples |<br>| `CLK lane in continuous HS mode` | Normal — continuous clock mode; CLK LP→HS happens once at startup and is not re-triggered per frame | Expected behaviour |</p>
<ul><li></li></ul>
<p>## 6. Actionable Recommendations</p>
<p>### CRITICAL — Fix #1: Switch to &#x27;Round Up&#x27; PHY Timing Registers</p>
<p>This is the <strong>single change</strong> most likely to eliminate flicker. Patch the samsung-dsim driver (or device tree) to use:</p>
<p>```<br>PHYTIMING (0xb4): 0x00000306 (THS_EXIT=6 → 111.1 ns ✓)<br>PHYTIMING1 (0xb8): 0x030f0a04 (TCLK_PREPARE=3→55.6ns ✓, TCLK_ZERO=15, TCLK_TRAIL=4→74.1ns ✓)<br>PHYTIMING2 (0xbc): 0x00030706 (THS_ZERO=7, THS_TRAIL=6→111.1ns ✓)<br>```</p>
<p>This eliminates all 5 D-PHY violations and gives:<br>- TCLK_PREPARE+TCLK_ZERO = 333 ns (33 ns margin over 300 ns spec)<br>- THS_PREPARE+THS_ZERO = 185 ns (17 ns margin over 168 ns spec)</p>
<p>The additional margin will <strong>eliminate the race condition</strong> that causes the tristable LP-low plateau (0/108/343 ns) by ensuring the PHY state machine always completes the full SoT sequence before the HS driver engages.</p>
<p><strong>Implementation</strong>: In the samsung-dsim (sec-dsim) driver, the timing calculation function (`samsung_dsim_set_phy_timing()` or equivalent) uses a rounding mode when converting continuous D-PHY timing formulae to integer byte-clock counts. Change the rounding from `floor()` / truncation to `ceil()` for all timing parameters. Alternatively, force the register values directly via a device-tree override or platform data hook.</p>
<p>### IMPORTANT — Fix #2: Investigate LP-11 Voltage</p>
<p>LP-11 at 1.015 V (with VDDIO = 1.765 V) implies a <strong>750 mV drop</strong> across the LP driver. This is excessive for a CMOS push-pull driver. Check:<br>1. Series resistance in the LP-mode path (ESD protection, connector, filter)<br>2. Whether a pull-up/pull-down network is loading the LP lines<br>3. SN65DSI83 input bias current (should be &lt; 10 µA; if a pull-down exists on the bridge side, it will drag LP-11 low)</p>
<p>Even though 1.015 V passes spec, increasing it to ~1.3 V would give the bridge 300 mV more noise margin for SoT detection.</p>
<p>### MODERATE — Fix #3: Add SoT Lock Verification + Retry</p>
<p>Since the failure mode is bistable (SoT succeeds or fails, never changes mid-session), add a software check after pipeline startup:<br>1. Read SN65DSI83 register 0x0A (PLL lock / sync status) within 100 ms of pipeline load<br>2. If not locked, unload and reload the pipeline (takes &lt; 200 ms)<br>3. Limit retries to 3 (with Round Up timing, retries should never be needed)</p>
<p>This provides defence-in-depth even if the timing fix reduces but doesn&#x27;t fully eliminate the race.</p>
<p>### MINOR — Fix #4: Measurement Infrastructure</p>
<ol><li><strong>LP capture depth</strong>: Increase from 200k to 300k samples to avoid buffer edge errors</li><li><strong>Sig trigger</strong>: Add ±5 ns random holdoff to sample both data phases</li><li><strong>Proto window</strong>: Ensure capture contains both positive and negative data swings (the &quot;only negative swings&quot; artefact affects amplitude validation)</li></ol>
<ul><li></li></ul>
<p>## 7. Summary</p>
<p><strong>The system has a non-deterministic SoT failure caused by 5 D-PHY timing violations in the &#x27;Round Best&#x27; register configuration, combined with a marginal LP-11 voltage of 1.015 V.</strong> The PHY&#x27;s internal state machine occasionally skips or truncates the LP-01/LP-00 SoT entry sequence (LP-low plateau = 0 ns in ~7% of startups), preventing the SN65DSI83 bridge from detecting start-of-transmission and locking. The 1.8 V supply is clean and not a contributing factor.</p>
<p><strong>Switching to the &#x27;Round Up&#x27; register values (0x00000306 / 0x030f0a04 / 0x00030706) will bring all timing parameters into D-PHY v1.1 compliance with comfortable margin and is expected to eliminate the flicker.</strong> This is a software-only fix requiring a driver patch to the samsung-dsim PHY timing calculation, and should be validated by re-running the 30-capture batch to confirm 0% flicker rate and 0% occurrence of LP-low plateau &lt; 300 ns.</p>
<p class="tokens">Tokens: 45428 in / 3819 out</p>
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