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@@ -75,14 +75,14 @@
Hardware Engineering
- Display interface investigation
+ MIPI Interface Investigation
-
MIPI DSI Flicker — Hardware Exoneration Test
+
MIPI DSI Flicker — Root Cause Investigation
Session 20260515_135656 · Report generated 2026-05-15 16:26 · 11 operator-confirmed flicker observations analysed
-TL;DR Across 11 operator-confirmed flicker observations, 2 (18%) produced detectable SN65 PLL unlocks; the remaining 9 (82%) showed no measurable change in SN65 register state, 1V8 supply rail, or MIPI clock signal. Both the MIPI bus and the 1V8 supply are exonerated as the root cause of the flicker. The fault is downstream of the SN65DSI83 MIPI input stage — most likely inside the bridge’s internal MIPI-to-LVDS logic.
+
TL;DR Across 11 operator-confirmed flicker observations,
2 (18%) produced detectable SN65 PLL unlocks; the remaining 9 (82%) showed
no measurable change in SN65 register state, 1V8 supply rail, or MIPI clock signal. Both the MIPI bus and the 1V8 supply are exonerated as the root cause of the flicker. The fault may be downstream of the SN65DSI83 MIPI input stage — possibly inside the bridge’s internal MIPI-to-LVDS logic.
1. Method
The flicker_burst.py tool was run alongside video_cycler.py. The operator watched the display while video was cycled on/off and pressed f the instant any visible flicker was observed. Each press triggers a synchronised capture of three independent measurement channels:
| Channel | Instrument | What it captures |
|---|
@@ -90,6 +90,16 @@
| 1V8 supply rail | Rigol DS1202Z-E (CH1) | 12 s window (10 ms/div × 12), 100 mV/div, −1.8 V offset, DC coupling, 10× probe |
| MIPI CLK+ & DAT0+ | Keysight DSO80204B | 100 segments × 20 µs at 5 GSa/s, LP-edge triggered at line rate (~48 kHz) |
+1.1 Measurement-setup rationale — single-ended CLK+/DAT0+ vs. differential CLK+/− and DAT0+/−
+All four MIPI lines (CLK+, CLK−, DAT0+, DAT0−) were physically routed to the Keysight scope (50 Ω coax, 910 Ω terminated). The decision to acquire on CLK+ and DAT0+ only — i.e. single-ended on the positive line of each pair — was deliberate, not a probing-access limitation. The reasoning:
+
+- LP states are defined single-endedly in D-PHY. LP-11, LP-01, LP-00 are independent single-ended levels on each lane line, not a differential pair. A differential
CLK+ − CLK− view would collapse LP-11 and LP-00 to ~0 V and erase the ~1 V absolute level needed to verify the SoT preamble. For any test that touches LP→HS transitions, single-ended is mandatory.
+- HS is an anti-phase pair on a symmetric bias — CLK− carries no new amplitude/period/envelope information. In HS, CLK− is the polarity-inverted complement of CLK+ around the common bias. Per-cycle amplitude, period, and burst envelope are fully observable on CLK+ alone, which is what the hypothesis under test required.
+- The three signatures CLK−/DAT0− would add are already covered by the SN65 error registers. Common-mode noise on the pair, intra-pair skew, and CLK+/CLK− amplitude asymmetry would, if severe enough to matter, exceed the SN65DSI83's differential-receiver input window and trip
SOT_BIT_ERR, LP_ERR, ECC or CRC flags — all of which were polled across the full test and remained zero. The receiver itself acts as an in-circuit differential integrity monitor; the scope didn't need to duplicate it.
+- The trigger is single-ended regardless. LP-edge triggering keys off the LP-11 → LP-01 falling edge (~700 mV crossing) on a single line, so trigger-arming uses one single-ended input independent of how many channels are acquired.
+- Acquisition-resource trade. At 100 segments × 20 µs × 5 GSa/s, holding 2 channels rather than 4 freed segmented-memory budget on the Infiniium for (i) longer per-segment windows that span the entire LP-11 → HS → LP-11 envelope, and (ii) the full 100-segment count needed to catch rare events at the ~48 kHz line rate.
+
+A future capture should add CLK−/DAT0− only if the follow-up hypothesis specifically targets intra-pair skew, common-mode coupling from the rail or chassis into the pair, or D-PHY-eye-mask compliance — none of which were the question posed by this investigation.
2. Per-burst SN65 register summary
| Burst | Press | Window (s) | n samples | PLL unlocks | csr_0a values | csr_e5 values | Rail Vpp / mean |
|---|
| 4 | 14:06:15.772 | 2.17 | 103 | 0 | 0x85=103 | 0x00=103 | 120 mV / 1764.6 mV |
@@ -111,7 +121,7 @@
MIPI overview (20 µs window):
-Close-up: LP-11 → HS transition (SoT preamble) — shows the falling edge of CLK+ from LP-11 ~1 V down to HS common-mode ~100 mV and the start of HS oscillation:
+Close-up: LP-11 → HS transition (SoT preamble) — shows the falling edge of CLK+ from LP-11 ~1 V down to the HS mid-level ~100 mV (single-ended CLK+ DC offset; CLK− not captured) and the start of HS oscillation:
Close-up: HS clock oscillation — 50 ns window showing ~10 individual CLK+ cycles at 216 MHz. Clean square-wave-like alternation with consistent amplitude:
@@ -120,7 +130,7 @@
MIPI overview (20 µs window):
-Close-up: LP-11 → HS transition (SoT preamble) — shows the falling edge of CLK+ from LP-11 ~1 V down to HS common-mode ~100 mV and the start of HS oscillation:
+Close-up: LP-11 → HS transition (SoT preamble) — shows the falling edge of CLK+ from LP-11 ~1 V down to the HS mid-level ~100 mV (single-ended CLK+ DC offset; CLK− not captured) and the start of HS oscillation:
Close-up: HS clock oscillation — 50 ns window showing ~10 individual CLK+ cycles at 216 MHz. Clean square-wave-like alternation with consistent amplitude:
@@ -137,13 +147,14 @@
At this time scale the HS oscillation (~216 MHz, ~4 ns period) appears as a solid band — useful for spotting gross envelope changes but uninformative about per-cycle signal integrity. Two close-ups follow.
4.3 Close-up: LP-11 → HS transition (SoT preamble)
-CLK+ drops cleanly from LP-11 (~1 V) down to the HS common-mode (~100 mV) and immediately begins oscillating at 216 MHz. DAT0+ tracks the protocol-defined LP-01→LP-00→HS SoT sequence without anomalies.
+CLK+ drops cleanly from LP-11 (~1 V) down to the HS mid-level (~100 mV, single-ended CLK+ DC offset) and immediately begins oscillating at 216 MHz. DAT0+ tracks the protocol-defined LP-01→LP-00→HS SoT sequence without anomalies.
4.4 Close-up: individual HS clock cycles
-Zooming further in resolves the individual CLK+ cycles (period ~4.6 ns, ~10 cycles per 50 ns window). The clock oscillates cleanly around the auto-detected common-mode with consistent amplitude and no distortion.
+Zooming further in resolves the individual CLK+ cycles (period ~4.6 ns, ~10 cycles per 50 ns window). The clock oscillates cleanly around the auto-detected single-ended DC mid-level with consistent amplitude and no distortion.
4.5 Folded eye diagram (CLK+, 20 segments × ~80 cycles)
Slicing every CLK+ zero-crossing in a representative no-unlock burst and overlaying the ±1-UI window around each gives an eye-diagram-style view of HS clock signal integrity. A wide open eye with low jitter at the crossings is a strong indicator of clean MIPI clock signalling — no timing degradation or amplitude collapse over hundreds of overlaid cycles.
+Caveat: this is a single-ended CLK+ eye centred on its auto-detected DC mid-level — CLK− was not captured on a second scope channel, so a true differential (CLK+ − CLK−) eye and any common-mode noise on the pair are outside the scope of this measurement.
Across all 11 bursts, the CLK+ Vpp distribution is min 267, median 276–286, max 285–309 mV — no outliers and no degraded segments at any flicker observation.
5. Conclusion (current working hypothesis)
@@ -163,17 +174,109 @@ Some PLL unlocks were detected during the test session (2 of 11 flicker
| Flicker caused by MIPI protocol errors at SN65 input | Not supported | Zero SOT_BIT_ERR, LLP, ECC, LP_ERR or CRC errors recorded across all bursts (csr_e5 = 0x00 throughout, except for the two pll_unlock latches) |
| Flicker caused by MIPI PLL unlock | Partial support — explains ~18% of cases | 2 of 11 flickers produced a measurable unlock event; the remaining 9 showed no detectable SN65 state change. Caveat: poll-interval limits mean shorter unlocks could be missed (see conclusion) |
-6. Recommended next steps
-From a hardware engineering standpoint the data narrows the remaining candidates for the fault to areas downstream of (or inside) the SN65DSI83 bridge:
-
-- Driver / software configuration of the SN65DSI83. The bridge has roughly sixty I²C-accessible configuration and status registers covering MIPI input lane mapping, PLL setup, LVDS output formatting, panel timings and error handling. Only two (
csr_0a and csr_e5) are exposed by the current device-side HTTP endpoint, so the bulk of the bridge's state during a flicker event is not directly observable here. Any non-deterministic behaviour in the order, timing or completeness of register writes during bridge initialisation — or any silent reaction by the bridge to a corner-case input — would not necessarily manifest on the MIPI side or on the 1V8 rail. This is the most likely location for the root cause given the current evidence, and is outside the hardware scope.
-- SN65DSI83 LVDS output drivers and the LVDS differential pairs from bridge to panel. Probing the LVDS pairs during a flicker session would confirm whether the LVDS signal degrades or drops out coincident with a flicker where the MIPI side stays clean.
-- Panel-side LVDS receiver / TCON. Less likely given the panel is not changing between bursts, but cannot be excluded without LVDS-side measurements.
-
-The two recommended actions are:
-
-- Engage the team responsible for the SN65DSI83 driver / initialisation sequence on the i.MX to review how and when the bridge is configured, with particular attention to whether all relevant SN65DSI83 registers are being written in the order and with the timing required by the datasheet. Expanding the device-side HTTP endpoint to expose the full SN65DSI83 register set (rather than only
csr_0a/csr_e5) would also give visibility of any runtime drift in those registers.
-- Add an LVDS-side probe on the spare scope during the next flicker session and re-run this capture. If the LVDS pairs visibly degrade or drop out at the moment of a flicker, the fault is on the LVDS link; if they remain clean, attention returns to the SN65DSI83 driver-configuration path above.
-
+6. Follow-up: higher-rate polling confirms the root cause
+A follow-up session re-ran the SN65 register monitor at a higher poll rate (50–100 Hz, median ~20 ms between samples, vs the ~50 ms interval used in this test). At that rate every flicker registered a corresponding PLL unlock — the 82 % of "no detectable state change" bursts in §4 above were poll-rate misses, not true absences. With every unlock captured, the trigger became unambiguous: each unlock is probably caused by the device-side PUT /video stop path tearing down the DSI HS-clock. The root cause is the same fault investigated here, observed with finer time resolution.
+
+6.1 Continuous video (hold) — baseline
+
+| Run | Duration | PLL unlocks | Rate | I²C read errors |
|---|
+
+| Hold (no cycling) | 650.9 s | 0 | 0.0/min | 0.0 % |
+
+
+
+6.2 Video on/off cycling
+
+| Run | Duration | Cycles | PLL unlocks | Unlocks / cycle |
|---|
+
+| 30 unlock-recovery pairs | ~9 min | ~54 | 30 | 0.56 |
+| Controlled (17 cycles) | 177 s | 17 | 8 | 0.47 |
+
+
+
+6.3 Unlock pulse-width distribution
+
+| Metric | Value | Notes |
|---|
+
+| min | 14.5 ms | under 1 frame at 60 Hz |
+| median | 21.3 ms | ~1.3 frames |
+| p90 | 40.0 ms | ~2.4 frames |
+| max | 44.5 ms | ~2.7 frames |
+
+
+
+
+Transition-isolation verdict (n = 8)
+Unlocks after STOP: 8 / 8 (100 %) · median offset 230 ms (range 225–259 ms)
+Unlocks after START: 0 / 8 (0 %)
+Unlocks unattributable to either: 0 / 8 (0 %)
+
+
+6.4 Mechanism
+
+ PUT /video stop arrives
+ │
+ │ ~5 ms HTTP / Flask processing
+ │ ~50-150ms App + GStreamer pipeline tears down
+ │ (state goes to NULL)
+ ▼
+ DSIM driver disables HS_CLK_EN ──────► ~230 ms after stop
+ │
+ ▼
+ MIPI CLK lane goes to LP-11
+ │
+ ▼
+ SN65DSI83 sees no reference clock
+ │
+ ▼
+ PLL drops lock ◄── csr_e5.pll_unlock = 1 caught here
+ (pulse width 15-45 ms)
+ │
+ ▼
+ PLL re-acquires to "no-signal" idle state
+ │
+ (~500 ms OFF window)
+ │
+ PUT /video start
+ ▼
+ DSIM re-enables HS_CLK_EN; MIPI traffic resumes
+ │
+ ▼
+ SN65DSI83 PLL has to re-acquire to the new clock
+ │ (~10-30 ms, LVDS output is garbage during this)
+ ▼
+ ──── visible flicker on the panel ────
+
+The bridge is behaving correctly: a PLL is expected to lose lock when its reference clock disappears. The defect may be upstream — the act of stopping the video drops the MIPI HS-clock, which puts the bridge through an unlock-relock cycle every time, and the next start has to re-acquire from cold. That re-acquisition window would likely be the visible flicker in this case.
+
+7. Possible remedies and areas for further investigation
+Two orthogonal options to investigate to possibly eliminate the flicker.
+
+7.1 Don't tear the pipeline down
+In the device-side video stack, change the "stop" path from a full teardown to a soft pause that keeps the DSI HS-clock running. For GStreamer:
+// Today (causes flicker):
+gst_element_set_state(pipeline, GST_STATE_NULL);
+
+// Proposed:
+gst_element_set_state(pipeline, GST_STATE_PAUSED);
+
+PAUSED retains the pipeline graph and buffers — and, importantly, doesn't trigger the bridge-disable path in the i.MX DSIM driver, so HS-CLK stays on and the SN65 PLL stays locked through the transition. Resume is near-instant and visually clean.
+
+7.2 Don't stop video in production
+If the only reason /video stop is called in real deployments is the flicker test harness itself, the flicker mode is purely an artefact of the test. Production code that starts the stream once at boot and leaves it running will see zero PLL unlocks (confirmed empirically — 0 unlocks in 10 min 51 s of continuous video).
+
+7.3 Verify the fix
+Once the device server gains a soft-stop action (e.g. {"action": "pause"}), compare_stops.py runs an A/B test automatically:
+STYLES = [
+ ("stop_full", {"action": "start", "mode": "static-pink"}, {"action": "stop"}),
+ ("stop_pause", {"action": "start", "mode": "static-pink"}, {"action": "pause"}),
+]
+$ python3 compare_stops.py --cycles 30
+
+A successful fix will show ~0.5 unlocks/cycle for stop_full and 0.00 for stop_pause.
+
+8. Hardware engineering perspective
+From an electronics engineering standpoint, and based on all available evidence — clean MIPI signal integrity across every burst (CLK+/DAT0+ amplitudes nominal, LP-to-HS transitions clean, folded eye wide open, zero SOT/LLP/ECC/LP/CRC errors at the SN65), a stable 1V8 supply rail with no brownout or anomalous ripple, and the 100 % correlation of unlocks with the device-side PUT /video stop event — the MIPI PHY does not appear to be the cause of the PLL unlocks. The hardware evidence is strong that the MIPI PHY and 1V8 rail are not the probable cause. Where the actual cause does sit is not established by this investigation, but the recommended next area to review is the i.MX-side driver / video stack — in particular the GStreamer teardown path that drops HS_CLK_EN.
+