Parked for now
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@@ -49,7 +49,7 @@ GOOD_DIR = DATA_DIR / "good"
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# *only* when the clock lane goes LP for longer than expected,
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# i.e. an actual glitch. Pairs with sn65_monitor.py to
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# capture the wire-side view of a PLL-unlock event.
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TRIGGER_MODE = "CLK_GLITCH" # or "LP_DAT"
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TRIGGER_MODE = "LP_DAT" # or "CLK_GLITCH"
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# Increased from 1 ms to 100 ms. Earlier runs at 1 ms triggered on every
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# V-blank (≈0.5/sec on this display) — far too often to be useful. The
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# observed PLL-unlock event from sn65_monitor is ~150 ms, so 100 ms
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