This commit is contained in:
david rice
2026-04-16 12:08:00 +01:00
parent 6dd4bb8aeb
commit 2659d7a664
5 changed files with 153 additions and 9 deletions

View File

@@ -678,11 +678,12 @@ class LPMetrics:
if self.flicker_suspect:
if (self.hs_amplitude_mv is not None
and self.hs_amplitude_mv < HS_BURST_AMPLITUDE_MIN_MV
and (self.lp_low_duration_ns is None
or self.lp_low_duration_ns >= FLICKER_LP_LOW_MAX_NS)):
and self.lp11_to_hs_ns is not None
and self.lp11_to_hs_ns >= LP_LOW_DUR_MIN_NS):
lines.append(
f" *** FLICKER SUSPECT: HS burst absent "
f"(amplitude {self.hs_amplitude_mv:.0f} mV < {HS_BURST_AMPLITUDE_MIN_MV:.0f} mV) ***"
f"(amplitude {self.hs_amplitude_mv:.0f} mV < {HS_BURST_AMPLITUDE_MIN_MV:.0f} mV, "
f"lp11_to_hs={self.lp11_to_hs_ns:.0f} ns) ***"
)
else:
lines.append(
@@ -851,12 +852,17 @@ def analyze_lp_file(path: Path) -> "LPMetrics":
# check alone produces a false negative.
#
# Only flag DAT lane (CLK is continuous HS — LP states not expected).
# NOTE: lp11_to_hs_ns is NOT used here — on this hardware a consistent noise spike
# at LP-11 exit causes the rolling-std gate to fire at ~3 ns for every capture,
# making it indistinguishable from a genuine flicker (2.8 ns confirmed flicker).
# Guard: require lp11_to_hs_ns >= LP_LOW_DUR_MIN_NS to rule out the consistent
# ~3 ns noise spike at LP-11 exit. On good captures the rolling-std gate fires
# at ~3 ns (hardware artifact); on confirmed flicker it fires at ~347 ns (real
# LP-low completes, then HS never starts → bridge returns to LP-11).
# Without this guard, DC-like HS data (uniform display content) produces low
# amplitude on otherwise good captures and causes false positives.
hs_burst_absent = (
hs_amplitude_mv is not None
and hs_amplitude_mv < HS_BURST_AMPLITUDE_MIN_MV
and lp11_to_hs_ns is not None
and lp11_to_hs_ns >= LP_LOW_DUR_MIN_NS
)
flicker_suspect = (
channel == "dat"

View File

@@ -750,9 +750,9 @@ def analyze_lp_and_ask_claude(
_append_flicker_log(ts, iteration, m)
if (m.hs_amplitude_mv is not None
and m.hs_amplitude_mv < HS_BURST_AMPLITUDE_MIN_MV
and (m.lp_low_duration_ns is None
or m.lp_low_duration_ns >= FLICKER_LP_LOW_MAX_NS)):
reason = f"HS burst absent ({m.hs_amplitude_mv} mV)"
and m.lp11_to_hs_ns is not None
and m.lp11_to_hs_ns >= FLICKER_LP_LOW_MAX_NS):
reason = f"HS burst absent ({m.hs_amplitude_mv:.0f} mV, lp11_to_hs={m.lp11_to_hs_ns:.0f} ns)"
else:
reason = f"lp_low={m.lp_low_duration_ns} ns"
print(f"\n *** FLICKER SUSPECT: capture {iteration:04d} "

View File

@@ -0,0 +1,130 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<title>MIPI Interactive Flicker Test &mdash; 2026-04-16 11:27:08</title>
<style>
body { font-family: Arial, sans-serif; max-width: 1020px; margin: 40px auto;
padding: 0 20px; color: #222; }
h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
h2 { color: #1a3a5c; margin-top: 32px; }
h3 { color: #333; }
.meta { color: #555; font-size: 0.92em; margin-top: -6px; margin-bottom: 20px; }
.stop-box { background: #e8f4fd; border-left: 4px solid #1a3a5c;
padding: 10px 16px; margin: 16px 0 24px; border-radius: 3px; }
.stat { display: inline-block; margin: 0 16px 20px 0; padding: 12px 22px;
border-radius: 6px; font-size: 1.05em; font-weight: bold; }
.s-confirmed { background: #fdecea; border: 2px solid #c62828; color: #c62828; }
.s-false { background: #e8f5e9; border: 2px solid #2e7d32; color: #2e7d32; }
.s-claude-no { background: #fff8e1; border: 2px solid #f9a825; color: #795548; }
table { border-collapse: collapse; width: 100%; margin-top: 8px; }
th { background: #1a3a5c; color: white; padding: 7px 10px; text-align: left; }
td { border: 1px solid #ddd; padding: 5px 10px; }
tr:nth-child(even) { background: #fafafa; }
pre { margin: 0; }
</style>
</head>
<body>
<h1>MIPI Interactive Flicker Test Report</h1>
<p class="meta">
Generated: 2026-04-16 11:27:08 &nbsp;|&nbsp;
Model: claude-opus-4-6
</p>
<div class="stop-box">
<strong>Stop reason:</strong> Test interrupted by operator (Ctrl+C)
</div>
<div>
<div class="stat s-confirmed">0 confirmed flicker(s)</div>
<div class="stat s-false">4 false alarm(s)</div>
<div class="stat s-claude-no">0 Claude said no</div>
</div>
<h2>D-PHY Configuration</h2>
<p>
Pixel clock: <strong>72.0 MHz</strong> &nbsp;|&nbsp;
Bit rate: <strong>432.0 Mbit/s per lane</strong> &nbsp;|&nbsp;
Byte clock: <strong>54.000 MHz</strong>
(18.519&thinsp;ns/byte) &nbsp;|&nbsp;
UI: <strong>2.315 ns</strong>
</p>
<table>
<tr>
<th>Field</th><th>Spec (ns)</th><th>Rnd Best</th><th>Rnd Up</th>
<th>Extra</th><th>Final</th><th>Actual (ns)</th><th>Status</th>
</tr>
<tr><td><code>lpx</code></td><td>&ge; 50.0</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_prepare</code></td><td>49.3 &ndash; 98.9</td><td>3</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>hs_zero</code></td><td>&ge; 112.6</td><td>6</td><td>7</td><td>+0</td><td><strong>7</strong></td><td>129.63</td><td>&#10003;</td></tr>
<tr><td><code>hs_trail</code></td><td>&ge; 69.3</td><td>4</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
<tr><td><code>hs_exit</code></td><td>&ge; 100.0</td><td>5</td><td>6</td><td>+0</td><td><strong>6</strong></td><td>111.11</td><td>&#10003;</td></tr>
<tr><td><code>clk_prepare</code></td><td>38.0 &ndash; 95.0</td><td>2</td><td>3</td><td>+0</td><td><strong>3</strong></td><td>55.56</td><td>&#10003;</td></tr>
<tr><td><code>clk_zero</code></td><td>&ge; 244.4</td><td>13</td><td>14</td><td>+0</td><td><strong>14</strong></td><td>259.26</td><td>&#10003;</td></tr>
<tr><td><code>clk_post</code></td><td>&ge; 180.4</td><td>10</td><td>10</td><td>+0</td><td><strong>10</strong></td><td>185.19</td><td>&#10003;</td></tr>
<tr><td><code>clk_trail</code></td><td>&ge; 60.0</td><td>3</td><td>4</td><td>+0</td><td><strong>4</strong></td><td>74.07</td><td>&#10003;</td></tr>
</table>
<p style="color:#2e7d32">&#10003; All D-PHY v1.1 Table&nbsp;14 constraints satisfied.</p>
<h3>Samsung DSIM Registers</h3>
<table>
<tr><th>Register</th><th>Address</th><th>Value</th><th>Field breakdown</th></tr>
<tr>
<td>PHY_TIMING</td><td><code>0xb4</code></td>
<td><code>0x00000306</code></td>
<td>lpx=3 &nbsp; hs_exit=6</td>
</tr>
<tr>
<td>PHY_TIMING1</td><td><code>0xb8</code></td>
<td><code>0x030e0a04</code></td>
<td>clk_prepare=3 &nbsp; clk_zero=14 &nbsp;
clk_post=10 &nbsp; clk_trail=4</td>
</tr>
<tr>
<td>PHY_TIMING2</td><td><code>0xbc</code></td>
<td><code>0x00030704</code></td>
<td>hs_prepare=3 &nbsp; hs_zero=7 &nbsp;
hs_trail=4</td>
</tr>
</table>
<h3>u-boot Commands</h3>
<pre style="background:#f5f5f5;padding:12px;border-radius:4px;
white-space:pre-wrap;font-size:0.88em"># D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING (0xb4) = 0x00000306 lpx=3 hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04 clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704 hs_prepare=3 hs_zero=7 hs_trail=4
# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar &quot;${flb_dtovar} dsi-tweak=4&quot;
saveenv
boot</pre>
<h2>Event Log</h2>
<table>
<tr>
<th>Capture</th><th>Timestamp</th><th>Channel</th>
<th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th>
<th>Claude: flicker?</th><th>Outcome</th>
</tr>
<tr><td>0001</td><td>20260416_112353</td><td>dat</td><td>342.7 ns</td><td>2.9 ns</td><td>1.017 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0002</td><td>20260416_112431</td><td>dat</td><td>342.6 ns</td><td>3.7 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0004</td><td>20260416_112531</td><td>dat</td><td>342.6 ns</td><td>3.8 ns</td><td>1.016 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr><tr><td>0006</td><td>20260416_112630</td><td>dat</td><td>108.0 ns</td><td>3.3 ns</td><td>1.017 V</td><td>YES</td><td><span style="color:#2e7d32;font-weight:bold">&#10003; FALSE ALARM</span></td></tr>
</table>
<h2>Claude Assessments</h2><h3>Capture 0001 [20260416_112353] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only 3 ns**, far below the 50 ns spec minimum, meaning the LP-01/LP-00 preamble states were essentially skipped or too brief for the SN65DSI83 to reliably sample the SoT sequence. Additionally, the **HS amplitude of only 20 mV** is drastically below the normal 105122 mV range and falls under the 50 mV &quot;absent&quot; threshold, indicating the bridge almost certainly did not detect a valid HS data burst even if it had latched SoT. Together, the absent LP-to-HS preamble and effectively missing HS signaling mean the bridge would fail to decode this frame, producing a visible flicker event.</pre><h3>Capture 0002 [20260416_112431] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
The LP-low plateau at 343 ns is well above the 50 ns SN65DSI83 detection threshold, so the SoT preamble timing itself is not the problem here. However, the HS amplitude of only 24 mV (single-ended) is far below both the normal operating range (105122 mV) and the 50 mV minimum detection threshold, meaning the bridge almost certainly cannot resolve valid differential HS data from this burst. Additionally, the LP exit-to-HS transition of only 4 ns (spec ≥ 50 ns) indicates the LP-01/LP-00 states were too brief for reliable SoT detection by the bridge. The combination of an effectively absent HS burst and a non-compliant LP exit duration makes this a genuine flicker event — the SN65DSI83 likely failed to lock onto the HS data, resulting in a dropped or corrupted video line/frame.</pre><h3>Capture 0004 [20260416_112531] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the HS amplitude of only 17 mV, far below the 50 mV minimum detection threshold and the normal 105122 mV range — effectively meaning the SN65DSI83 sees no valid HS data burst at all. Additionally, the LP-exit-to-HS transition time of only 4 ns (spec ≥ 50 ns) indicates the LP-01/LP-00 states were too brief for the bridge to properly recognize the SoT preamble. Together, these two failures — an undetectable HS burst and a sub-spec LP exit duration — mean the bridge almost certainly missed this transmission, constituting a genuine flicker event.</pre><h3>Capture 0006 [20260416_112630] — FALSE ALARM</h3><pre style="background:#f5f5f5;padding:12px;border-radius:4px;white-space:pre-wrap;font-size:0.88em">YES
Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only 3.3 ns**, far below the 50 ns spec minimum, meaning the LP-01/LP-00 states were essentially skipped or too brief for the SN65DSI83 to reliably detect the SoT preamble. Additionally, the **HS amplitude of 28 mV** is well below the 50 mV threshold and far below the normal 105122 mV range, indicating the bridge almost certainly did not lock onto the HS data burst — effectively an absent HS transmission from the receiver&#x27;s perspective. These two compounding failures — a near-instantaneous LP-to-HS transition and a sub-threshold HS amplitude — make it virtually certain the SN65DSI83 missed this SoT entirely, producing a visible flicker event.</pre>
</body>
</html>

View File

@@ -96,3 +96,7 @@ logged_at,capture_ts,capture_num,channel,lp_low_duration_ns,lp11_to_hs_ns,lp11_v
2026-04-16 10:25:01,20260416_102440,0170,dat,0.3,0.8,1.015
2026-04-16 10:27:34,20260416_102713,0176,dat,0.9,0.1,1.016
2026-04-16 11:12:28,20260416_111206,0065,dat,26.7,4.0,1.016
2026-04-16 11:24:15,20260416_112353,0001,dat,342.7,2.9,1.017
2026-04-16 11:24:53,20260416_112431,0002,dat,342.6,3.7,1.016
2026-04-16 11:25:52,20260416_112531,0004,dat,342.6,3.8,1.016
2026-04-16 11:26:51,20260416_112630,0006,dat,108.0,3.3,1.017
1 logged_at capture_ts capture_num channel lp_low_duration_ns lp11_to_hs_ns lp11_voltage_v
96 2026-04-16 10:25:01 20260416_102440 0170 dat 0.3 0.8 1.015
97 2026-04-16 10:27:34 20260416_102713 0176 dat 0.9 0.1 1.016
98 2026-04-16 11:12:28 20260416_111206 0065 dat 26.7 4.0 1.016
99 2026-04-16 11:24:15 20260416_112353 0001 dat 342.7 2.9 1.017
100 2026-04-16 11:24:53 20260416_112431 0002 dat 342.6 3.7 1.016
101 2026-04-16 11:25:52 20260416_112531 0004 dat 342.6 3.8 1.016
102 2026-04-16 11:26:51 20260416_112630 0006 dat 108.0 3.3 1.017

View File

@@ -26,3 +26,7 @@ logged_at,capture_ts,capture_num,claude_said_flicker,user_confirmed,lp_low_ns,re
2026-04-16 10:25:18,20260416_102440,0170,YES,NO,0.3,YES The LP-low plateau measured at 0.3 ns is effectively absent and falls catastrophically short of the SN65DSI83's required ≥ 50 ns minimum for SoT
2026-04-16 10:27:54,20260416_102713,0176,YES,NO,0.9,YES The LP-low plateau measured at only 0.9 ns is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection — it is essentially ab
2026-04-16 11:12:48,20260416_111206,0065,YES,NO,26.7,"YES The LP-low plateau of 26.7 ns is barely half the SN65DSI83's required ≥ 50 ns minimum, and the LP exit-to-HS transition of only 4 ns is drastical"
2026-04-16 11:24:30,20260416_112353,0001,YES,NO,342.7,"YES Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only 3"
2026-04-16 11:25:07,20260416_112431,0002,YES,NO,342.6,"YES The LP-low plateau at 343 ns is well above the 50 ns SN65DSI83 detection threshold, so the SoT preamble timing itself is not the problem here. Ho"
2026-04-16 11:26:06,20260416_112531,0004,YES,NO,342.6,"YES Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the HS amplitude of only 17 mV, far bel"
2026-04-16 11:27:06,20260416_112630,0006,YES,NO,108.0,"YES Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only "
1 logged_at capture_ts capture_num claude_said_flicker user_confirmed lp_low_ns reasoning_summary
26 2026-04-16 10:25:18 20260416_102440 0170 YES NO 0.3 YES The LP-low plateau measured at 0.3 ns is effectively absent and falls catastrophically short of the SN65DSI83's required ≥ 50 ns minimum for SoT
27 2026-04-16 10:27:54 20260416_102713 0176 YES NO 0.9 YES The LP-low plateau measured at only 0.9 ns is drastically below the SN65DSI83's required ≥ 50 ns minimum for SoT detection — it is essentially ab
28 2026-04-16 11:12:48 20260416_111206 0065 YES NO 26.7 YES The LP-low plateau of 26.7 ns is barely half the SN65DSI83's required ≥ 50 ns minimum, and the LP exit-to-HS transition of only 4 ns is drastical
29 2026-04-16 11:24:30 20260416_112353 0001 YES NO 342.7 YES Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only 3
30 2026-04-16 11:25:07 20260416_112431 0002 YES NO 342.6 YES The LP-low plateau at 343 ns is well above the 50 ns SN65DSI83 detection threshold, so the SoT preamble timing itself is not the problem here. Ho
31 2026-04-16 11:26:06 20260416_112531 0004 YES NO 342.6 YES Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the HS amplitude of only 17 mV, far bel
32 2026-04-16 11:27:06 20260416_112630 0006 YES NO 108.0 YES Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only