From 223df488d641980171cf00cd8e0ba909694b98b8 Mon Sep 17 00:00:00 2001
From: david rice <david.rice@arrive.com>
Date: Thu, 9 Apr 2026 11:22:46 +0100
Subject: [PATCH] Updates

---
 __pycache__/analyze_captures.cpython-312.pyc | Bin 25505 -> 27405 bytes
 analyze_captures.py                          |  46 +++++++++++++------
 2 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/__pycache__/analyze_captures.cpython-312.pyc b/__pycache__/analyze_captures.cpython-312.pyc
index 32f8dd07ea317fc4eed94265ae33dec9e6db807e..ffa5a75ad5071f0e59194fa1ba033ae0904ec42d 100644
GIT binary patch
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diff --git a/analyze_captures.py b/analyze_captures.py
index 9de6d24..a88d137 100644
--- a/analyze_captures.py
+++ b/analyze_captures.py
@@ -65,21 +65,26 @@ DEVICE_CONFIG = {
     "pixel_clock_mhz":  72,
     "dsi_lanes":        4,
     "color_format":     "RGB888 (24 bpp)",
-    "hs_bit_rate_mbps": 432,    # 72 × 24 / 4
+    # DSI clock is LOCKED to pixel clock by format geometry — not independently configurable:
+    #   24 bpp / 4 lanes = 6 bit-clocks per pixel; DDR halves the clock → 3 × pixel clock
+    #   DSI clock (differential CLK pair) = 3 × 72 MHz = 216 MHz
+    #   HS bit rate = 216 MHz × 2 (DDR) = 432 Mbit/s per lane
+    "dsi_clock_mhz":    216,    # 3 × pixel_clock; differential CLK pair frequency
+    "hs_bit_rate_mbps": 432,    # 216 × 2 (DDR) = 72 × 24 / 4
     "hs_ui_ns":         2.315,  # 1 / 432e6
     "byte_clock_mhz":   54,     # 432 / 8
     "byte_period_ns":   18.518,
     "vddio_v":          1.8,
-    # Correct DSIM PHY timing register values (byte-clock units, see derivation above)
-    # Samsung DSIM field mapping (sec_mipi_dsim.c / samsung-dsim.c):
-    #   PHYTIMING  (0xb4): [15:8]=TLPX,         [7:0]=THS_EXIT
+    # Samsung DSIM PHY timing field mapping (sec_mipi_dsim.c / samsung-dsim.c):
+    #   PHYTIMING  (0xb4): [15:8]=TLPX,          [7:0]=THS_EXIT
     #   PHYTIMING1 (0xb8): [31:24]=TCLK_PREPARE, [23:16]=TCLK_ZERO,
-    #                      [15:8]=TCLK_POST,     [7:0]=TCLK_TRAIL
-    #   PHYTIMING2 (0xbc): [23:16]=THS_TRAIL,    [15:8]=THS_ZERO, [7:0]=THS_PREPARE
+    #                      [15:8]=TCLK_POST,      [7:0]=TCLK_TRAIL
+    #   PHYTIMING2 (0xbc): [23:16]=THS_TRAIL,     [15:8]=THS_ZERO,  [7:0]=THS_PREPARE
+    # All fields in byte-clock units (÷ 18.518 ns, rounded up) per MIPI D-PHY v1.1:
     "dsim_phytiming_target": {
-        "PHYTIMING  (0xb4)": "0x00000306  (TLPX=3→55.6ns, THS_EXIT=6→111ns)",
-        "PHYTIMING1 (0xb8)": "0x03110A04  (TCLK_PREPARE=3, TCLK_ZERO=17→315ns, TCLK_POST=10→185ns, TCLK_TRAIL=4→74ns)",
-        "PHYTIMING2 (0xbc)": "0x00040A03  (THS_TRAIL=4→74ns, THS_ZERO=10→185ns, THS_PREPARE=3→56ns)",
+        "PHYTIMING  (0xb4)": "0x00000306  (TLPX=3→55.6ns ≥50ns ✓, THS_EXIT=6→111ns ≥100ns ✓)",
+        "PHYTIMING1 (0xb8)": "0x03110A04  (TCLK_PREPARE=3→55.6ns, TCLK_ZERO=17→315ns ≥300ns ✓, TCLK_POST=10→185ns ≥180ns ✓, TCLK_TRAIL=4→74ns ≥60ns ✓)",
+        "PHYTIMING2 (0xbc)": "0x00040A03  (THS_TRAIL=4→74ns ≥69ns ✓, THS_ZERO=10→185ns ≥168ns ✓, THS_PREPARE=3→56ns within 49-99ns ✓)",
     },
 }
 
@@ -210,11 +215,14 @@ def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
         f"  Pixel clock:     {cfg['pixel_clock_mhz']} MHz\n"
         f"  DSI lanes:       {cfg['dsi_lanes']} data lanes\n"
         f"  Color format:    {cfg['color_format']}\n"
-        f"  HS bit rate:     {cfg['hs_bit_rate_mbps']} Mbit/s per lane\n"
+        f"  DSI clock:       {cfg['dsi_clock_mhz']} MHz  "
+        f"(= 3 × pixel clock; fixed by 24bpp/4lanes/DDR — not independently tunable)\n"
+        f"  HS bit rate:     {cfg['hs_bit_rate_mbps']} Mbit/s per lane  "
+        f"(= DSI clock × 2, DDR)\n"
         f"  HS UI:           {cfg['hs_ui_ns']:.3f} ns\n"
         f"  Byte clock:      {cfg['byte_clock_mhz']} MHz ({cfg['byte_period_ns']:.3f} ns/byte)\n"
         f"  VDDIO:           {cfg['vddio_v']} V\n"
-        f"  Correct DSIM PHY timing register targets (byte-clock units):\n"
+        f"  Target DSIM PHY timing registers (byte-clock units, MIPI D-PHY v1.1 compliant):\n"
         + "\n".join(f"    {k}: {v}" for k, v in target.items())
     )
 
@@ -245,8 +253,20 @@ def build_prompt(all_summaries: list[str], flicker_suspects: list = None,
 
     return (
         "Below are pre-processed summaries of MIPI D-PHY captures from a Digi ConnectCore "
-        "8M Mini SOM (NXP i.MX 8M Mini) driving a SN65DSI83 MIPI-to-LVDS bridge. "
-        "The system occasionally flickers at display pipeline load. "
+        "8M Mini SOM (NXP i.MX 8M Mini) driving a SN65DSI83 MIPI-to-LVDS bridge.\n\n"
+        "Flicker behaviour (confirmed by observation):\n"
+        "  - The system is BISTABLE at initialisation. The state is determined entirely at\n"
+        "    pipeline load (LP→HS SoT sequence) and does not change during a session.\n"
+        "  - State A (good): SoT succeeds → bridge locks → display runs indefinitely, "
+        "perfectly stable, no flicker.\n"
+        "  - State B (bad):  SoT fails → bridge stuck → flickers indefinitely until the\n"
+        "    display pipeline is unloaded and reloaded (no other recovery).\n"
+        "  - After a reset the system is almost always in State A — good state is strongly\n"
+        "    preferred but State B occurs intermittently at pipeline load.\n"
+        "  - Nothing ongoing (supply noise, EMI, temperature drift) causes or ends flicker;\n"
+        "    the root cause is non-deterministic and acts only at the LP→HS SoT moment.\n"
+        "  - The LP pass captures the very first SoT transition at pipeline startup.\n"
+        "    Any LP timing anomaly in these captures is a genuine flicker event, not noise.\n\n"
         "Each capture has up to five data sets per lane (CLK and DAT0):\n"
         "  sig   — high-res HS differential (rise/fall times)\n"
         "  proto — long-window HS differential (jitter, clock freq, amplitude)\n"