354 lines
45 KiB
HTML
354 lines
45 KiB
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<title>MIPI DSI Flicker — Root Cause Investigation</title>
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<div class="who">
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<strong>Hardware Engineering</strong>
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Display interface investigation
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</div>
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<div class="page">
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<h1>MIPI DSI Flicker — Root Cause Investigation</h1>
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<div class="meta">
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Display flicker on i.MX 8M Mini → SN65DSI83 → LVDS panel<br>
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Investigation period: May 7 – May 11, 2026 ·
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Author: David Rice
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</div>
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<div class="tldr">
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<strong>TL;DR.</strong> The flicker is caused by the
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<code>PUT /video stop</code> path on the i.MX, not by signal-integrity
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on the MIPI bus, not by the SN65DSI83 itself, and not by the panel.
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Each video stop tears down the DSI HS-clock; the SN65's PLL loses lock
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for 15–45 ms (1–3 display frames); on the subsequent start, the
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PLL must re-acquire and the LVDS output is briefly garbled — the
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visible flicker. <strong>Fix:</strong> change "stop" semantics so the
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HS-clock keeps running (e.g. GStreamer <code>PAUSED</code> instead of
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<code>NULL</code>), or simply avoid stopping video in production.
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</div>
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<h2>1. The problem</h2>
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<p>
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An i.MX 8M Mini SoC drives a SN65DSI83 MIPI-DSI → LVDS bridge into an
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LCD panel. Under steady-state operation the display sometimes flickers.
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Initial hypothesis: a MIPI bit-error or signal-integrity issue on the
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CLK or data lanes.
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</p>
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<h2>2. Investigation summary</h2>
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<table>
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<thead><tr><th>Phase</th><th>Approach</th><th>Result</th></tr></thead>
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<tbody>
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<tr><td>1 – proto decoder</td>
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<td>Decode raw MIPI bursts from differential captures, look for byte-level anomalies</td>
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<td><span class="fail">Inconclusive.</span> Capture coverage was ~0.0004% of time
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(20 µs windows on a 10 s cycle). Flicker events not captured.</td></tr>
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<tr><td>2 – segmented memory</td>
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<td>Use scope's segmented-memory mode to capture 100 LP-trigger events per acquisition
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(~50× higher coverage), analyse per-segment</td>
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<td><span class="warn">Negative result.</span> Flicker and non-flicker captures
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statistically indistinguishable across all LP-state metrics.</td></tr>
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<tr><td>3 – SN65 register monitor</td>
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<td>High-rate HTTP polling of SN65DSI83's status registers
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(<code>csr_0a</code>, <code>csr_e5</code>) to catch transient PLL events
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the post-event snapshot missed</td>
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<td><span class="pass">Smoking gun found.</span> PLL unlocks during flicker
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sessions, never during good sessions.</td></tr>
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<tr><td>4 – Pulse-width characterisation</td>
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<td>100 Hz polling (median 20 ms) to measure actual unlock pulse width</td>
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<td>Pulse width <strong>15–45 ms</strong> (1–3 display frames). Too short for
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a software-driven clock pause; too short for a brownout-and-restart.
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Consistent with a brief clock-lane disturbance.</td></tr>
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<tr><td>5 – Cycling vs hold</td>
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<td>Compare PLL behaviour under continuous video to behaviour under
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on/off cycling</td>
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<td><span class="pass">Definitive.</span> 0 unlocks in 10 min 51 s of
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continuous video. 30 unlocks in 9 min of cycling. The cycling is
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the trigger.</td></tr>
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<tr><td>6 – Transition isolation</td>
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<td>Time-correlate every unlock against each <code>PUT /video start</code>
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and <code>PUT /video stop</code> event</td>
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<td><span class="pass">Conclusive.</span> 100% of unlocks happen 225–259 ms
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after <code>stop</code>. 0% after <code>start</code>.</td></tr>
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</tbody>
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</table>
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<h2>3. Key data</h2>
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<h3>3.1 Continuous video (hold) — baseline</h3>
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<table>
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<thead><tr><th>Run</th><th class="num">Duration</th><th class="num">PLL unlocks</th>
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<th class="num">Rate</th><th class="num">I²C read errors</th></tr></thead>
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<tbody>
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<tr><td>Hold (no cycling)</td><td class="num">650.9 s</td>
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<td class="num pass">0</td><td class="num pass">0.0/min</td>
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<td class="num pass">0.0%</td></tr>
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</tbody>
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</table>
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<h3>3.2 Video on/off cycling</h3>
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<table>
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<thead><tr><th>Run</th><th class="num">Duration</th><th class="num">Cycles</th>
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<th class="num">PLL unlocks</th><th class="num">Unlocks / cycle</th></tr></thead>
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<tbody>
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<tr><td>May 11 — 30 unlock-recovery pairs</td>
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<td class="num">~9 min</td><td class="num">~54</td>
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<td class="num fail">30</td><td class="num fail">0.56</td></tr>
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<tr><td>May 11 — controlled (17 cycles)</td>
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<td class="num">177 s</td><td class="num">17</td>
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<td class="num fail">8</td><td class="num fail">0.47</td></tr>
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</tbody>
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</table>
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<h3>3.3 Unlock pulse-width distribution</h3>
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<table>
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<thead><tr><th>Metric</th><th class="num">Value</th><th>Notes</th></tr></thead>
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<tbody>
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<tr><td>min</td> <td class="num">14.5 ms</td><td>under 1 frame at 60 Hz</td></tr>
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<tr><td>median</td> <td class="num">21.3 ms</td><td>~1.3 frames</td></tr>
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<tr><td>p90</td> <td class="num">40.0 ms</td><td>~2.4 frames</td></tr>
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|
<tr><td>max</td> <td class="num">44.5 ms</td><td>~2.7 frames</td></tr>
|
|||
|
|
</tbody>
|
|||
|
|
</table>
|
|||
|
|
|
|||
|
|
<div class="verdict">
|
|||
|
|
<strong class="big">Transition-isolation verdict (n = 8)</strong><br><br>
|
|||
|
|
Unlocks <strong>after STOP:</strong> <strong>8 / 8 (100%)</strong> ·
|
|||
|
|
median offset <strong>230 ms</strong> (range 225–259 ms)<br>
|
|||
|
|
Unlocks <strong>after START:</strong> 0 / 8 (0%)<br>
|
|||
|
|
Unlocks unattributable to either: 0 / 8 (0%)
|
|||
|
|
</div>
|
|||
|
|
|
|||
|
|
<h2>4. Mechanism</h2>
|
|||
|
|
|
|||
|
|
<pre class="diagram">
|
|||
|
|
PUT /video stop arrives
|
|||
|
|
│
|
|||
|
|
│ ~5 ms HTTP / Flask processing
|
|||
|
|
│ ~50-150ms App + GStreamer pipeline tears down
|
|||
|
|
│ (state goes to NULL)
|
|||
|
|
▼
|
|||
|
|
DSIM driver disables HS_CLK_EN ──────► ~230 ms after stop
|
|||
|
|
│
|
|||
|
|
▼
|
|||
|
|
MIPI CLK lane goes to LP-11
|
|||
|
|
│
|
|||
|
|
▼
|
|||
|
|
SN65DSI83 sees no reference clock
|
|||
|
|
│
|
|||
|
|
▼
|
|||
|
|
PLL drops lock ◄── csr_e5.pll_unlock = 1 caught here
|
|||
|
|
(pulse width 15-45 ms)
|
|||
|
|
│
|
|||
|
|
▼
|
|||
|
|
PLL re-acquires to "no-signal" idle state
|
|||
|
|
│
|
|||
|
|
(~500 ms OFF window)
|
|||
|
|
│
|
|||
|
|
PUT /video start
|
|||
|
|
▼
|
|||
|
|
DSIM re-enables HS_CLK_EN; MIPI traffic resumes
|
|||
|
|
│
|
|||
|
|
▼
|
|||
|
|
SN65DSI83 PLL has to re-acquire to the new clock
|
|||
|
|
│ (~10-30 ms, LVDS output is garbage during this)
|
|||
|
|
▼
|
|||
|
|
──── visible flicker on the panel ────
|
|||
|
|
</pre>
|
|||
|
|
|
|||
|
|
<p>
|
|||
|
|
The bridge is behaving correctly: a PLL is expected to lose lock when its
|
|||
|
|
reference clock disappears. The defect is upstream — the act of
|
|||
|
|
<em>stopping the video</em> drops the MIPI HS-clock, which puts the bridge
|
|||
|
|
through an unlock-relock cycle every time, and the next start has to
|
|||
|
|
re-acquire from cold. That re-acquisition window is the visible flicker.
|
|||
|
|
</p>
|
|||
|
|
|
|||
|
|
<h2>5. Recommended fix</h2>
|
|||
|
|
|
|||
|
|
<p>Two orthogonal options. Either should eliminate the flicker.</p>
|
|||
|
|
|
|||
|
|
<h3>5.1 Don't tear the pipeline down</h3>
|
|||
|
|
<p>
|
|||
|
|
In the device-side video stack, change the "stop" path from a full
|
|||
|
|
teardown to a soft pause that <strong>keeps the DSI HS-clock running</strong>.
|
|||
|
|
For GStreamer:
|
|||
|
|
</p>
|
|||
|
|
<pre>// Today (causes flicker):
|
|||
|
|
gst_element_set_state(pipeline, GST_STATE_NULL);
|
|||
|
|
|
|||
|
|
// Proposed:
|
|||
|
|
gst_element_set_state(pipeline, GST_STATE_PAUSED);
|
|||
|
|
</pre>
|
|||
|
|
<p>
|
|||
|
|
<code>PAUSED</code> retains the pipeline graph and buffers — and, importantly,
|
|||
|
|
doesn't trigger the bridge-disable path in the i.MX DSIM driver, so HS-CLK
|
|||
|
|
stays on and the SN65 PLL stays locked through the transition. Resume is
|
|||
|
|
near-instant and visually clean.
|
|||
|
|
</p>
|
|||
|
|
|
|||
|
|
<h3>5.2 Don't stop video in production</h3>
|
|||
|
|
<p>
|
|||
|
|
If the only reason <code>/video stop</code> is called in real deployments
|
|||
|
|
is the flicker test harness itself, the flicker mode is purely an artefact
|
|||
|
|
of the test. Production code that starts the stream once at boot and
|
|||
|
|
leaves it running will see <strong>zero</strong> PLL unlocks (confirmed
|
|||
|
|
empirically — 0 unlocks in 10 min 51 s of continuous video).
|
|||
|
|
</p>
|
|||
|
|
|
|||
|
|
<h3>5.3 Verify the fix</h3>
|
|||
|
|
<p>
|
|||
|
|
Once the device server gains a soft-stop action (e.g.
|
|||
|
|
<code>{"action": "pause"}</code>), <code>compare_stops.py</code> in this
|
|||
|
|
repo runs an A/B test automatically:
|
|||
|
|
</p>
|
|||
|
|
<pre>STYLES = [
|
|||
|
|
("stop_full", {"action": "start", "mode": "static-pink"}, {"action": "stop"}),
|
|||
|
|
("stop_pause", {"action": "start", "mode": "static-pink"}, {"action": "pause"}),
|
|||
|
|
]
|
|||
|
|
$ python3 compare_stops.py --cycles 30
|
|||
|
|
</pre>
|
|||
|
|
<p>
|
|||
|
|
A successful fix will show <code>~0.5</code> unlocks/cycle for
|
|||
|
|
<code>stop_full</code> and <code>0.00</code> for <code>stop_pause</code>.
|
|||
|
|
</p>
|
|||
|
|
|
|||
|
|
<h2>6. Tools developed</h2>
|
|||
|
|
<table>
|
|||
|
|
<thead><tr><th>Script</th><th>Purpose</th></tr></thead>
|
|||
|
|
<tbody>
|
|||
|
|
<tr><td><code>sn65_monitor.py</code></td>
|
|||
|
|
<td>Polls SN65 status registers at 50–100 Hz, logs every PLL transition with
|
|||
|
|
millisecond timestamps. Rolling 30 s buffer dumped to JSON on
|
|||
|
|
<code>f</code>/<code>g</code> keypress.</td></tr>
|
|||
|
|
<tr><td><code>video_cycler.py</code></td>
|
|||
|
|
<td>Toggles <code>/video</code> start/stop on the device on a configurable
|
|||
|
|
cadence. Logs every transition to a CSV. Has a <code>--hold</code>
|
|||
|
|
mode for the no-cycling baseline.</td></tr>
|
|||
|
|
<tr><td><code>analyze_session.py</code></td>
|
|||
|
|
<td>Cross-references the latest SN65 log with the latest cycle log,
|
|||
|
|
classifies each unlock as "after_START / after_STOP / neither",
|
|||
|
|
prints a verdict.</td></tr>
|
|||
|
|
<tr><td><code>compare_stops.py</code></td>
|
|||
|
|
<td>Runs a controlled A/B/… test across multiple stop-style payloads.
|
|||
|
|
Polls SN65 inline, attributes unlocks to the active style,
|
|||
|
|
prints a comparison table. Use this to verify the eventual fix.</td></tr>
|
|||
|
|
</tbody>
|
|||
|
|
</table>
|
|||
|
|
|
|||
|
|
<h2>7. Open questions</h2>
|
|||
|
|
<ul class="tight">
|
|||
|
|
<li><strong>The rare catastrophic black-screen mode.</strong> Most unlocks
|
|||
|
|
recover cleanly within ~40 ms. Twice during the investigation a
|
|||
|
|
flicker resulted in a persistent black screen. That is presumably the
|
|||
|
|
same root cause but where PLL re-acquisition fails outright; eliminating
|
|||
|
|
the trigger should eliminate the rare variant too, but worth
|
|||
|
|
confirming with extended runs.</li>
|
|||
|
|
<li><strong>The 8 % of "good" sessions that contained early unlock activity.</strong>
|
|||
|
|
One <code>f</code> press on 11 May (08:33:28) had zero PLL activity in
|
|||
|
|
the preceding minute, suggesting either an observation false-positive
|
|||
|
|
or a separate, sub-poll-rate fault path. Worth keeping the
|
|||
|
|
<code>sn65_monitor</code> running in any future regression testing
|
|||
|
|
to catch.</li>
|
|||
|
|
<li><strong>Device-side endpoint additions.</strong> Three small additions
|
|||
|
|
would close out the diagnostic kit:
|
|||
|
|
<ul>
|
|||
|
|
<li><code>POST /video</code> support for <code>action=pause</code>
|
|||
|
|
(GStreamer <code>GST_STATE_PAUSED</code>)</li>
|
|||
|
|
<li><code>/registers</code> to expose the runtime DSIM registers
|
|||
|
|
<code>DSIM_STATUS</code>, <code>DSIM_CLKCTRL</code>,
|
|||
|
|
<code>DSIM_INTSRC</code>, <code>DSIM_FIFOCTRL</code> alongside the
|
|||
|
|
existing PHY-timing config registers</li>
|
|||
|
|
<li><code>GET /video/state</code> exposing the GStreamer pipeline
|
|||
|
|
state (NULL / READY / PAUSED / PLAYING), which would let us
|
|||
|
|
time-correlate the actual pipeline state transitions with the
|
|||
|
|
PLL unlock window</li>
|
|||
|
|
</ul>
|
|||
|
|
</li>
|
|||
|
|
</ul>
|
|||
|
|
|
|||
|
|
<div class="footnote">
|
|||
|
|
Investigation traces, raw register snapshots, and the analysis scripts
|
|||
|
|
are in this repository under <code>data/sn65_log/</code>,
|
|||
|
|
<code>data/cycle_logs/</code>, and <code>data/compare_logs/</code>.
|
|||
|
|
Each timestamped run is independently reproducible.
|
|||
|
|
</div>
|
|||
|
|
|
|||
|
|
</div> <!-- /.page -->
|
|||
|
|
|
|||
|
|
</body>
|
|||
|
|
</html>
|