reports/20260409_144445_analysis.html

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<title>MIPI Analysis — Captures 0469–0498</title>
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<h1>MIPI D-PHY Analysis Report</h1>

<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
            padding:16px 20px;margin-bottom:28px;">
  <h2 style="color:#e65100;margin-top:0">&#9888; FLICKER DETECTED &mdash; 5 of 30 display load sessions (17%) flickered</h2>
  <p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
     pipeline startup, so a missing or sub-50&nbsp;ns LP-low plateau means the SN65DSI83 bridge
     missed the SoT sequence and dropped a frame.<br>
     LP-low plateau &lt; 50&nbsp;ns means the LP-01/LP-00 SoT states are absent or too brief
     for the SN65DSI83 bridge to detect start-of-transmission.</p>
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
        <th>LP-low plateau</th><th>LP exit&rarr;HS</th><th>LP-11 voltage</th></tr>
    <tr><td>0469</td><td>20260409_142930</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.4 ns</td><td>1.015 V</td></tr><tr><td>0478</td><td>20260409_143246</td><td>dat</td><td style='color:red'>0.3 ns</td><td>0.8 ns</td><td>1.015 V</td></tr><tr><td>0485</td><td>20260409_143518</td><td>dat</td><td style='color:red'>0.2 ns</td><td>3.5 ns</td><td>1.015 V</td></tr><tr><td>0488</td><td>20260409_143623</td><td>dat</td><td style='color:red'>0.3 ns</td><td>3.1 ns</td><td>1.015 V</td></tr><tr><td>0494</td><td>20260409_143834</td><td>dat</td><td style='color:red'>0.2 ns</td><td>2.3 ns</td><td>1.015 V</td></tr>
  </table>
</div>

<details style="margin-bottom:24px;">
  <summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
    DSI Register Snapshots (30 captures)
  </summary>
  <div style="overflow-x:auto;margin-top:8px;">
  <table>
    <tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
    <tr><td>0469</td><td>20260409_142930</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0470</td><td>20260409_142952</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0471</td><td>20260409_143013</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0472</td><td>20260409_143035</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0473</td><td>20260409_143057</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0474</td><td>20260409_143119</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0475</td><td>20260409_143140</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0476</td><td>20260409_143202</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0477</td><td>20260409_143224</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0478</td><td>20260409_143246</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0479</td><td>20260409_143307</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0480</td><td>20260409_143329</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0481</td><td>20260409_143351</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0482</td><td>20260409_143413</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0483</td><td>20260409_143434</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0484</td><td>20260409_143456</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0485</td><td>20260409_143518</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0486</td><td>20260409_143540</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0487</td><td>20260409_143601</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0488</td><td>20260409_143623</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0489</td><td>20260409_143645</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0490</td><td>20260409_143707</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0491</td><td>20260409_143729</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0492</td><td>20260409_143751</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0493</td><td>20260409_143813</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0494</td><td>20260409_143834</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0495</td><td>20260409_143856</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0496</td><td>20260409_143917</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0497</td><td>20260409_143939</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0498</td><td>20260409_144001</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
  </table>
  </div>
</details>
<p class="meta">
  <strong>Generated:</strong> 2026-04-09 14:44:45 &nbsp;|&nbsp;
  <strong>Scope:</strong> Captures 0469–0498 &nbsp;|&nbsp;
  <strong>Model:</strong> claude-opus-4-6
</p>
<p># MIPI D-PHY Signal Integrity Analysis — Captures 0469–0498</p>
<p>## 1. Root Cause: Register Mismatch — Driver Not Programming Target Timings</p>
<p><strong>This is the single most important finding.</strong> Every capture shows the same register values, and they do NOT match the target values:</p>
<p>| Register | Target | Actual | Impact |<br>|---|---|---|---|<br>| PHYTIMING (0xb4) | `0x00000306` | `0x00000305` | <strong>THS_EXIT=5 → 92.6 ns</strong> (spec ≥100 ns) <strong>✗</strong> |<br>| PHYTIMING1 (0xb8) | `0x03110A04` | `0x020e0a03` | <strong>TCLK_PREPARE=2→37ns</strong> (spec 38–95ns) <strong>✗</strong>, <strong>TCLK_ZERO=14→259ns</strong> (spec ≥300ns) <strong>✗</strong>, TCLK_TRAIL=3→55.6ns (spec ≥60ns) <strong>✗</strong> |<br>| PHYTIMING2 (0xbc) | `0x00040A03` | `0x00030605` | <strong>THS_PREPARE=5→92.6ns</strong> (spec max 99ns, marginal ✓ but overshot vs target 3), <strong>THS_ZERO=6→111ns</strong> (spec ≥168ns) <strong>✗</strong>, THS_TRAIL=3→55.6ns (spec ≥69ns) <strong>✗</strong> |</p>
<p>### Critical Field-by-Field Decode (actual registers, at 18.518 ns/unit):</p>
<p><strong>PHYTIMING (0x00000305):</strong><br>- TLPX = 3 → 55.6 ns (spec ≥50 ns) ✓<br>- THS_EXIT = 5 → 92.6 ns (spec ≥100 ns) <strong>✗ VIOLATION</strong></p>
<p><strong>PHYTIMING1 (0x020e0a03):</strong><br>- TCLK_PREPARE = 2 → 37.0 ns (spec 38–95 ns) <strong>✗ VIOLATION by 1 ns</strong><br>- TCLK_ZERO = 0x0e = 14 → 259.3 ns (spec ≥300 ns) <strong>✗ VIOLATION by 41 ns</strong><br>- TCLK_POST = 0x0a = 10 → 185.2 ns (spec ≥60+52×UI ≈ 180 ns) ✓ marginal<br>- TCLK_TRAIL = 3 → 55.6 ns (spec ≥60 ns) <strong>✗ VIOLATION</strong></p>
<p><strong>PHYTIMING2 (0x00030605):</strong><br>- THS_PREPARE = 5 → 92.6 ns (spec 40+4×UI to 85+6×UI ≈ 49–99 ns) ✓ but high<br>- THS_ZERO = 6 → 111.1 ns (spec ≥145+10×UI ≈ 168 ns) <strong>✗ VIOLATION by 57 ns</strong><br>- THS_TRAIL = 3 → 55.6 ns (spec max(8×UI, 60+4×UI) ≈ 69 ns) <strong>✗ VIOLATION</strong></p>
<p><strong>Seven out of eight critical timing fields are either violating spec or marginal.</strong> The driver (samsung-dsim / sec-dsim) is computing these values incorrectly at 432 Mbit/s, or a device-tree override is not being applied.</p>
<ul><li></li></ul>
<p>## 2. LP-Low Plateau Analysis — Flicker Correlation</p>
<p>### Distribution across all captures with LP data:</p>
<p>| LP-low plateau | Count | Flicker? |<br>|---|---|---|<br>| <strong>0 ns (absent)</strong> | 4 (0469, 0478, 0485, 0488, 0494) | <strong>All 5 confirmed flicker</strong> |<br>| 57–108 ns | 7 (0472, 0474, 0479, 0480, 0482, 0487, 0491, 0493, 0496, 0497, 0498) | No flicker |<br>| 343 ns | 9 (0470, 0471, 0473, 0475, 0477, 0481, 0484, 0486, 0495) | No flicker |</p>
<p><strong>Perfect correlation: every confirmed flicker event has LP-low = 0 ns.</strong> The SoT sequence (LP-11 → LP-01 → LP-00 → HS-0) is being completely skipped on data lanes in ~17% of startups. The SN65DSI83 never sees a valid Start-of-Transmission and fails to lock its MIPI receiver.</p>
<p>### Why the LP-low plateau is non-deterministic:</p>
<p>The <strong>THS_ZERO register is programmed to only 6 byte-clocks (111 ns)</strong> vs the required 168 ns minimum. Combined with <strong>TCLK_ZERO at 259 ns</strong> (41 ns short of spec), the CLK-to-DATA timing relationship during SoT is a race condition:</p>
<ol><li>The CLK lane enters HS and starts toggling.</li><li>Data lanes are supposed to execute LP-11 → LP-01 → LP-00 → HS-0 with THS_PREPARE + THS_ZERO defining the low-state duration.</li><li>With THS_ZERO = 6 (111 ns) — <strong>57 ns shorter than spec</strong> — the data lane transitions through LP-00 so fast that it&#x27;s below the scope&#x27;s LP capture resolution on some startups.</li><li>The non-determinism comes from the interaction between the PHY&#x27;s analog startup jitter and the too-short digital timer: sometimes the LP transmitter manages to pull low long enough for the bridge to detect it; sometimes it doesn&#x27;t.</li></ol>
<p>The <strong>LP exit → HS measurement of 1–4 ns</strong> across nearly all captures (even non-flicker ones) confirms that the LP-01 state (where Dp goes low, Dn stays high) is essentially absent — the transition from LP-11 to LP-00 is happening in a single slew, not as two discrete LP state changes. This is consistent with THS_PREPARE being set to 5 (92.6 ns) which is at the very top of the spec window — the PHY holds LP-01 so briefly relative to its transition time that the scope can&#x27;t resolve it.</p>
<ul><li></li></ul>
<p>## 3. Consistent Spec Concerns</p>
<p>### 3a. HS Amplitude — Marginal but Passing<br>- CLK: 175–177 mV consistently. Within spec (140–270 mV) but only 36 mV headroom above minimum.<br>- DAT: 186–199 mV. Healthier margin.<br>- <strong>Asymmetry on CLK</strong>: +191 / -162 mV consistently → ~15 mV common-mode offset. Within ±25 mV spec but persistent.<br>- <strong>Below-140mV sample counts</strong> on proto captures are concerning (up to 7811 on DAT), indicating ISI/transition dips that could cause bit errors at the bridge receiver. This is exacerbated by the short THS_TRAIL (55.6 ns vs 69 ns spec) which doesn&#x27;t allow full settling before the next state.</p>
<p>### 3b. LP-11 Voltage: 1.014–1.016 V<br>- Spec: VOH ≥ 1.0 V for LP (assuming 1.2 V threshold with hysteresis at the receiver).<br>- At 1.015 V, this is <strong>only 15 mV above the absolute minimum</strong>. The SN65DSI83 datasheet specifies LP-high threshold at 880 mV (typ), so 1.015 V provides adequate margin for detection.<br>- However, the 1.015 V level (vs the expected ~1.2 V for a 1.8 V VDDIO driver) suggests the LP driver&#x27;s pull-up impedance and the trace/termination loading are causing significant voltage division. This doesn&#x27;t cause the flicker but reduces noise immunity.</p>
<p>### 3c. HS Single-Ended Amplitude Anomalies<br>Several captures show very low single-ended HS amplitude in LP captures:<br>- 0472: 48 mV, 0473: 36 mV, 0474: 29 mV, 0482: 23 mV, 0487: 36 mV, 0496: 24 mV</p>
<p>These are not flicker-correlated and likely represent the scope capturing a blanking interval or data idle period within the HS burst window, not an actual amplitude problem (the differential proto/sig captures consistently show proper 187–199 mV).</p>
<ul><li></li></ul>
<p>## 4. Trends Across Captures</p>
<p>| Parameter | Trend | Concern |<br>|---|---|---|<br>| CLK amplitude | Flat 176.4–176.9 mV | No drift, but low headroom |<br>| CLK jitter p-p | 98–149 ps | No trend; occasional spikes (0473: 140 ps, 0474: 140 ps, 0486: 149 ps) uncorrelated with flicker |<br>| DAT amplitude | 186–199 mV | No drift |<br>| LP-11 voltage | 1.014–1.016 V | Rock stable, no drift |<br>| 1.8 V supply | 1.7634–1.7656 V mean | No drift |<br>| Registers | Identical across all 30 captures | <strong>Confirming this is a static programming error, not a runtime corruption</strong> |</p>
<ul><li></li></ul>
<p>## 5. Supply Correlation Analysis</p>
<p>| Captures | Supply droop | LP-low plateau | Flicker? |<br>|---|---|---|---|<br>| 0469 (flicker) | 8.9 mV | 0 ns | Yes |<br>| 0478 (flicker) | 8.7 mV | 0 ns | Yes |<br>| 0485 (flicker) | 9.4 mV | 0 ns | Yes |<br>| 0488 (flicker) | 8.3 mV | 0 ns | Yes |<br>| 0494 (flicker) | 8.1 mV | 0 ns | Yes |<br>| 0470 (no flicker) | 17.2 mV | 343 ns | No |<br>| 0471 (no flicker) | 15.7 mV | 343 ns | No |<br>| 0475 (no flicker) | 11.5 mV | 343 ns | No |</p>
<p><strong>There is NO correlation between supply droop and flicker.</strong> In fact, the two largest droops (17.2 mV and 15.7 mV) produced *good* SoT sequences. The supply is clean and well within spec (min 1.748 V vs 1.71 V limit). Ripple RMS is consistently 5.0–5.8 mV — negligible. <strong>The supply is not the cause.</strong></p>
<ul><li></li></ul>
<p>## 6. WARNING/ERROR Explanations</p>
<p>| Warning | Cause | Action |<br>|---|---|---|<br>| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal: samsung-dsim operates CLK in continuous HS mode per configuration. LP transitions only on data lanes. | None needed — expected behavior |<br>| `Only negative swings in capture window` | The sig/dat differential capture window happened to land on a run of identical bits (all-zero data). The DAT line shows only one polarity. | Not a real issue — the proto capture shows proper bidirectional swing |<br>| `No HS signal detected` (0473, 0474, 0487, 0497 sig/dat) | Scope triggered during blanking/LP period on data lane while CLK was active. | Not a real issue |<br>| `index 200000 is out of bounds` (0476, 0483, 0490, 0492) | LP capture buffer overflow — the LP→HS transition occurred outside the capture window, or the trigger was late. | Increase capture depth or adjust trigger position. These captures cannot be assessed for LP timing |<br>| `LP exit duration N ns below spec min 50 ns` | <strong>REAL ISSUE</strong>: THS_PREPARE + transition overlap makes LP-01 state unresolvable. The PHY&#x27;s LP state machine is cycling through LP-01 too quickly due to register misconfiguration | Fix registers (see below) |<br>| `Settled samples below 140 mV` | ISI (inter-symbol interference) causing eye closure during transitions. Exacerbated by short THS_TRAIL not allowing full settling. Up to 7811 samples on DAT in worst case | Fix THS_TRAIL register; consider trace impedance review |</p>
<ul><li></li></ul>
<p>## 7. Actionable Recommendations</p>
<p>### PRIORITY 1 — Fix PHY Timing Registers (CRITICAL)</p>
<p>The samsung-dsim driver is not programming the target values. You must ensure the correct values are written:</p>
<p>```<br># Target values (MIPI D-PHY v1.1 compliant at 432 Mbit/s):<br>PHYTIMING  (0x32e100b4) = 0x00000306   # TLPX=3, THS_EXIT=6<br>PHYTIMING1 (0x32e100b8) = 0x03110A04   # TCLK_PREPARE=3, TCLK_ZERO=17, TCLK_POST=10, TCLK_TRAIL=4<br>PHYTIMING2 (0x32e100bc) = 0x00040A03   # THS_TRAIL=4, THS_ZERO=10, THS_PREPARE=3<br>```</p>
<p><strong>Root cause of the mismatch</strong>: The samsung-dsim driver in mainline Linux computes timings using `samsung_dsim_set_phy_ctrl()` which derives values from the PLL frequency. At 432 Mbit/s (a relatively low rate for this IP), the integer rounding in the driver&#x27;s calculations produces values that are 1 unit too low on multiple fields. The driver was validated at higher bit rates (≥1 Gbps) where the rounding errors are proportionally smaller.</p>
<p><strong>Fix options (in order of preference):</strong></p>
<ol><li><strong>Device-tree override</strong>: The `samsung,burst-clock-frequency` and `samsung,esc-clock-frequency` properties influence the calculation. However, the core computation is in the driver, so DT alone may not fix all fields.</li></ol>
<ol><li><strong>Driver patch</strong>: Modify `samsung_dsim_set_phy_ctrl()` in `drivers/gpu/drm/bridge/samsung-dsim.c` to add +1 to `TCLK_ZERO`, `THS_ZERO`, `THS_EXIT`, `TCLK_TRAIL`, and `THS_TRAIL` calculations — or hardcode the values for this specific bit rate via a DT override mechanism.</li></ol>
<ol><li><strong>Runtime fixup script</strong> (temporary workaround): Write the registers via memtool/devmem *before* enabling the display pipeline:</li><li>```bash</li><li># Before pipeline enable:</li><li>busybox devmem 0x32e100b4 32 0x00000306</li><li>busybox devmem 0x32e100b8 32 0x03110A04</li><li>busybox devmem 0x32e100bc 32 0x00040A03</li><li>```</li><li><strong>Caution</strong>: This must be done after the DSIM block is clocked but before `drm_panel_enable()` / CRTC enable. The driver may overwrite these during `atomic_enable`.</li></ol>
<p>### PRIORITY 2 — Increase THS_ZERO to Eliminate LP-Low Variability</p>
<p>The most direct cause of the bistable flicker is <strong>THS_ZERO = 6 → 111 ns</strong> (actual) vs the required ≥168 ns. Increasing to the target value of 10 → 185 ns gives the SN65DSI83 a full 185 ns window to detect the LP-00 state, eliminating the race condition. Even increasing to 9 (167 ns) would be marginal — use 10 or higher.</p>
<p>### PRIORITY 3 — Consider Further Margin on TCLK_ZERO</p>
<p>The target TCLK_ZERO = 17 → 315 ns is only 15 ns above the 300 ns spec minimum. For a bridge that must lock its clock recovery PLL during this window, consider increasing to 18 or 19 (333–352 ns) for additional margin, especially given the SN65DSI83&#x27;s known sensitivity to SoT timing.</p>
<p>### PRIORITY 4 — Investigate LP-11 Voltage</p>
<ol><li>V from a 1.8 V driver suggests ~785 mV drop across the LP pull-up path. Check:</li></ol>
<p class="tokens">Tokens: 32867 in / 4095 out</p>
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