258 lines
8.6 KiB
Python
258 lines
8.6 KiB
Python
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#!/usr/bin/env python3
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"""
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rail_watch.py — Capture Rigol DS1202Z-E CH1 (1V8 supply rail) every time the
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SN65DSI83 reports a MIPI PLL unlock.
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Architecture
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------------
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- Polls /sn65_registers at ~50 Hz looking for pll_lock True→False transitions.
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- On each unlock, :STOPs the Rigol, reads CH1 waveform via :WAV:DATA?, saves
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to CSV in data/rail_traces/, prints peak-to-peak ripple, then :RUNs again.
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- Press `g` to capture a baseline (clean) trace. Press `q` to quit.
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Rigol setup (do once on the front panel before running):
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* Channel 1 probed on the 1V8 rail derived to the MIPI PHY
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* DC coupling with offset, or AC coupling for ripple-only view
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* Recommended: 20 mV/div, 5–10 ms/div (60–120 ms window)
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* Trigger: AUTO on Channel 1 so the buffer is always recent
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* Memory depth: 12M (or whatever fits the timebase)
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* :RUN the scope so it's continuously acquiring
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"""
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from __future__ import annotations
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import argparse
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import select
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import signal
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import sys
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import termios
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import time
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import tty
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from datetime import datetime
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from pathlib import Path
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import numpy as np
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import requests
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import vxi11
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# ---------------------------------------------------------------------------
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# Config
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# ---------------------------------------------------------------------------
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DEVICE_BASE = "http://192.168.45.8:5000"
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SN65_EP = f"{DEVICE_BASE}/sn65_registers"
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RIGOL_IP = "192.168.45.5"
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DATA_DIR = Path(__file__).parent / "data" / "rail_traces"
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POLL_DT_S = 0.020 # 50 Hz target — coarser than sn65_monitor
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HTTP_TO_S = 0.2
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RIGOL_TO_S = 10.0
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# ---------------------------------------------------------------------------
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# Rigol I/O
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# ---------------------------------------------------------------------------
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def _read_ieee_block(rigol) -> bytes:
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"""Read an IEEE 488.2 binary block from the scope: '#'<n><len><data>[\\n]."""
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head = rigol.read_raw(2)
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if not head.startswith(b"#"):
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idx = head.find(b"#")
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if idx < 0:
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extra = rigol.read_raw(64)
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head += extra
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idx = head.find(b"#")
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head = head[idx:idx + 2]
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ndigits = int(head[1:2])
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length_bytes = rigol.read_raw(ndigits)
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nbytes = int(length_bytes)
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data = b""
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while len(data) < nbytes:
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chunk = rigol.read_raw(nbytes - len(data))
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if not chunk:
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break
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data += chunk
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try:
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rigol.read_raw(1) # trailing newline (may not be present)
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except Exception:
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pass
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return data
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def capture_trace(rigol, label: str) -> tuple[Path, float, float]:
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"""
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:STOP → read CH1 → :RUN. Returns (csv_path, vpp_mV, mean_V).
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"""
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rigol.write(":STOP")
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time.sleep(0.06)
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rigol.write(":WAVeform:SOURce CHANnel1")
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rigol.write(":WAVeform:FORMat BYTE")
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rigol.write(":WAVeform:MODE NORM")
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time.sleep(0.02)
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preamble = rigol.ask(":WAVeform:PREamble?").strip().split(",")
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# format,type,points,count,xinc,xorig,xref,yinc,yorig,yref
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xinc = float(preamble[4]); xorig = float(preamble[5])
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yinc = float(preamble[7]); yorig = float(preamble[8])
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yref = float(preamble[9])
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rigol.write(":WAVeform:DATA?")
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raw = _read_ieee_block(rigol)
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codes = np.frombuffer(raw, dtype=np.uint8)
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volts = (codes.astype(np.float64) - yref - yorig) * yinc
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t = np.arange(len(volts)) * xinc + xorig
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DATA_DIR.mkdir(parents=True, exist_ok=True)
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ts = datetime.now().strftime("%Y%m%d_%H%M%S_%f")[:-3]
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csv_path = DATA_DIR / f"{ts}_{label}.csv"
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np.savetxt(csv_path, np.column_stack([t, volts]),
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delimiter=",", fmt="%.6e")
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rigol.write(":RUN")
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vpp_mV = float((volts.max() - volts.min()) * 1000)
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mean_V = float(volts.mean())
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return csv_path, vpp_mV, mean_V
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# ---------------------------------------------------------------------------
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# SN65 state extraction
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# ---------------------------------------------------------------------------
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def pll_state(data: dict | None):
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if not isinstance(data, dict):
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return None
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regs = data.get("registers", {})
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if not isinstance(regs, dict):
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return None
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csr_0a = regs.get("csr_0a") or {}
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return csr_0a.get("pll_lock")
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# ---------------------------------------------------------------------------
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# Non-blocking keys
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# ---------------------------------------------------------------------------
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class KeyReader:
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def __enter__(self):
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self.fd = sys.stdin.fileno()
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self.old = termios.tcgetattr(self.fd)
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tty.setcbreak(self.fd)
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return self
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def get_key(self) -> str | None:
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if select.select([sys.stdin], [], [], 0)[0]:
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return sys.stdin.read(1).lower()
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return None
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def __exit__(self, *_):
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termios.tcsetattr(self.fd, termios.TCSADRAIN, self.old)
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# ---------------------------------------------------------------------------
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# Main
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# ---------------------------------------------------------------------------
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def main() -> None:
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ap = argparse.ArgumentParser(description=__doc__,
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formatter_class=argparse.RawDescriptionHelpFormatter)
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ap.add_argument("--test", action="store_true",
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help="Take one immediate trace + exit (verifies Rigol comms)")
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args = ap.parse_args()
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DATA_DIR.mkdir(parents=True, exist_ok=True)
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sess = requests.Session()
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print(f"RAIL WATCH")
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print(f" sn65 endpoint: {SN65_EP}")
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print(f" Rigol IP: {RIGOL_IP}")
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print(f" Output dir: {DATA_DIR.relative_to(DATA_DIR.parent.parent)}")
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try:
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rigol = vxi11.Instrument(RIGOL_IP)
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rigol.timeout = RIGOL_TO_S
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idn = rigol.ask("*IDN?").strip()
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print(f" Rigol IDN: {idn}")
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except Exception as e:
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print(f" *** RIGOL CONNECTION FAILED: {e} ***")
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sys.exit(1)
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if args.test:
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print("\n--test: taking one capture now...")
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try:
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path, vpp, mean = capture_trace(rigol, "test")
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print(f" saved {path.name}")
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print(f" Vpp = {vpp:.1f} mV mean = {mean:.3f} V")
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except Exception as e:
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print(f" CAPTURE FAILED: {e}")
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sys.exit(0)
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def _shutdown(*_):
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try:
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rigol.write(":RUN")
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except Exception:
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pass
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print("\nstopped — Rigol restored to RUN")
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sys.exit(0)
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signal.signal(signal.SIGINT, _shutdown)
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signal.signal(signal.SIGTERM, _shutdown)
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print("\nkeys: g=baseline capture q=quit\n", flush=True)
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print(f" {'time':<14} {'event':<12} {'file':<40} {'Vpp':>7} {'mean':>7}")
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print(f" {'-'*14} {'-'*12} {'-'*40} {'-'*7} {'-'*7}")
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last_pll = None
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unlock_count = 0
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baseline_count = 0
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err_count = 0
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with KeyReader() as keys:
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while True:
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t0 = time.time()
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try:
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r = sess.get(SN65_EP, timeout=HTTP_TO_S)
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r.raise_for_status()
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pll = pll_state(r.json())
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err_count = 0
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except Exception:
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pll = None
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err_count += 1
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# Trigger Rigol on True → False (a real unlock). We ignore the
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# True → None case (transient I2C read failure) since it isn't
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# a PLL state change.
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if last_pll is True and pll is False:
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unlock_count += 1
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iso = datetime.now().strftime("%H:%M:%S.%f")[:-3]
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try:
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path, vpp, mean = capture_trace(
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rigol, f"unlock_{unlock_count:04d}")
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print(f" {iso:<14} {'UNLOCK':<12} "
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f"{path.name:<40} {vpp:>5.1f}mV {mean:>5.3f}V",
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flush=True)
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except Exception as e:
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print(f" {iso:<14} UNLOCK CAPTURE FAILED: {e}",
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flush=True)
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last_pll = pll if pll is not None else last_pll
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# Manual baseline capture
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key = keys.get_key()
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if key == "g":
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baseline_count += 1
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iso = datetime.now().strftime("%H:%M:%S.%f")[:-3]
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try:
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path, vpp, mean = capture_trace(
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rigol, f"baseline_{baseline_count:04d}")
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print(f" {iso:<14} {'BASELINE':<12} "
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f"{path.name:<40} {vpp:>5.1f}mV {mean:>5.3f}V",
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flush=True)
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except Exception as e:
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print(f" {iso:<14} BASELINE CAPTURE FAILED: {e}",
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flush=True)
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elif key == "q":
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_shutdown()
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# Pace
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elapsed = time.time() - t0
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if elapsed < POLL_DT_S:
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time.sleep(POLL_DT_S - elapsed)
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if __name__ == "__main__":
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main()
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