107 lines
19 KiB
HTML
107 lines
19 KiB
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<html lang="en">
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<meta charset="UTF-8">
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<title>MIPI Analysis — Captures 0137–0166</title>
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body { font-family: Arial, sans-serif; max-width: 900px; margin: 40px auto; padding: 0 20px; color: #222; }
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h1 { color: #1a3a5c; border-bottom: 2px solid #1a3a5c; padding-bottom: 8px; }
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.meta { color: #555; font-size: 0.95em; margin-top: -8px; margin-bottom: 24px; }
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li { margin: 4px 0; }
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.tokens { color: #888; font-size: 0.8em; margin-top: 32px; border-top: 1px solid #ddd; padding-top: 8px; }
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.flicker-alert { background: #fff3cd; border: 2px solid #e65100; border-radius: 6px;
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padding: 16px 20px; margin-bottom: 28px; }
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</head>
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<h1>MIPI D-PHY Analysis Report</h1>
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<div style="background:#fff3cd;border:2px solid #e65100;border-radius:6px;
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padding:16px 20px;margin-bottom:28px;">
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<h2 style="color:#e65100;margin-top:0">⚠ FLICKER DETECTED — 1 of 30 display load sessions (3%) flickered</h2>
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<p>Each flagged capture is a genuine flicker event (not an artifact) — the LP pass fires at
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pipeline startup, so a missing or sub-50 ns LP-low plateau means the SN65DSI83 bridge
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missed the SoT sequence and dropped a frame.<br>
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LP-low plateau < 50 ns means the LP-01/LP-00 SoT states are absent or too brief
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for the SN65DSI83 bridge to detect start-of-transmission.</p>
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>Channel</th>
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<th>LP-low plateau</th><th>LP exit→HS</th><th>LP-11 voltage</th></tr>
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<tr><td>0164</td><td>20260413_095340</td><td>dat</td><td style='color:red'>0.3 ns</td><td>2.3 ns</td><td>1.015 V</td></tr>
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</table>
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</div>
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<details style="margin-bottom:24px;">
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<summary style="cursor:pointer;font-weight:bold;color:#1a3a5c;font-size:1.05em;">
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DSI Register Snapshots (30 captures)
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</summary>
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<div style="overflow-x:auto;margin-top:8px;">
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<table>
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<tr><th>Capture</th><th>Timestamp</th><th>0x32e100b4<br><small>DSIM_PHYTIMING</small></th><th>0x32e100b8<br><small>DSIM_PHYTIMING1</small></th><th>0x32e100bc<br><small>DSIM_PHYTIMING2</small></th></tr>
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<tr><td>0137</td><td>20260413_094356</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0138</td><td>20260413_094418</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0139</td><td>20260413_094439</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0140</td><td>20260413_094501</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0141</td><td>20260413_094523</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0142</td><td>20260413_094544</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0143</td><td>20260413_094606</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0144</td><td>20260413_094627</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0145</td><td>20260413_094649</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0146</td><td>20260413_094710</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0147</td><td>20260413_094732</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0148</td><td>20260413_094754</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0149</td><td>20260413_094816</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0150</td><td>20260413_094837</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0151</td><td>20260413_094859</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0152</td><td>20260413_094920</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0153</td><td>20260413_094942</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0154</td><td>20260413_095003</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0155</td><td>20260413_095025</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0156</td><td>20260413_095047</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0157</td><td>20260413_095108</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0158</td><td>20260413_095130</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0159</td><td>20260413_095152</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0160</td><td>20260413_095213</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0161</td><td>20260413_095235</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0162</td><td>20260413_095257</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0163</td><td>20260413_095318</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0164</td><td>20260413_095340</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0165</td><td>20260413_095402</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr><tr><td>0166</td><td>20260413_095423</td><td>0x00000305</td><td>0x020e0a03</td><td>0x00030605</td></tr>
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</table>
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</div>
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</details>
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<p class="meta">
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<strong>Generated:</strong> 2026-04-13 09:59:11 |
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<strong>Scope:</strong> Captures 0137–0166 |
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<strong>Model:</strong> claude-opus-4-6
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</p>
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<p># MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166</p>
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<p>## 1. Consistent Spec Concerns</p>
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<p>### Register Timing Violations (100% of captures — systemic)<br>Every single capture shows the <strong>'Round Best' register set</strong> with identical 5 D-PHY v1.1 violations:</p>
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<p>| Parameter | Programmed | Actual | Spec Min | Shortfall |<br>|-----------|-----------|--------|----------|-----------|<br>| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | <strong>−7.4 ns</strong> |<br>| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | <strong>−1.0 ns</strong> |<br>| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | <strong>−4.4 ns</strong> |<br>| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | <strong>−3.7 ns</strong> |<br>| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | <strong>−1.5 ns</strong> |</p>
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<p><strong>Critical insight:</strong> The THS_PREPARE+THS_ZERO violation (1.5 ns short) directly controls the data-lane SoT sequence. This is the interval during which the receiver must detect the HS-0 state and synchronise to the incoming data. Being 1.5 ns short means the SN65DSI83 has ~1% less time to complete bit-sync. Combined with the TCLK_PREPARE+TCLK_ZERO shortfall (3.7 ns), the clock lane's HS entry is also marginal — the receiver may not have a stable clock reference when data arrives.</p>
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<p>### LP Exit Duration (Pervasive)<br><strong>24 of 29 captures with LP data</strong> report LP exit → HS durations of 0–4 ns (spec ≥ 50 ns). This is not a measurement artefact — it reflects the PHY skipping or severely truncating the LP-01 → LP-00 states on the data lane. The programmed THS_PREPARE+THS_ZERO budget is too short to guarantee the LP-00 state is held long enough for the bridge's LP receiver to register it.</p>
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<p>Only 5 captures show compliant LP exit (108–348 ns): 0137, 0139, 0148, 0159, 0166.</p>
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<p>### LP-11 Voltage<br>LP-11 voltage is consistently 1.013–1.016 V across all captures (spec 1.0–1.45 V). This is <strong>at the absolute floor</strong> of the D-PHY spec (VOH ≥ VIH_LP = ~1.0 V). The 1.8 V VDDIO is ~1.765 V (2% below nominal) and the LP drivers are delivering only 56% of VDDIO. This leaves <strong>no noise margin</strong> — any additional drop could cause LP-11 to be misread.</p>
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<p>### HS Amplitude<br>- <strong>CLK lane:</strong> Stable at 165–167 mV differential — passes spec (140–270 mV) but with only ~26 mV margin above the 140 mV floor.<br>- <strong>DAT0 lane:</strong> 186–224 mV nominal, but <strong>persistent sub-140 mV samples</strong> in every capture (16 to 9742 samples). This indicates ISI-induced eye closure during data transitions.<br>- <strong>CLK common mode offset:</strong> Consistently +28–31 mV (positive skew), indicating slight impedance imbalance on CLK±.</p>
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<p>### Single-Ended HS Amplitude (LP capture)<br>Bimodal: captures show either ~106–118 mV or ~16–32 mV single-ended HS amplitude. The low-amplitude group likely represents captures where the scope triggered on a blanking interval or the data lane was in LP-idle between video lines.</p>
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<ul><li></li></ul>
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<p>## 2. Trends Over Captures</p>
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<p>| Parameter | Range | Trend |<br>|-----------|-------|-------|<br>| CLK Vdiff | 165.6–166.8 mV | <strong>Rock stable</strong> — no drift |<br>| DAT0 Vdiff | 186.5–223.6 mV | Occasional jumps (0140, 0153, 0161 show ~224 mV) — likely different data patterns |<br>| CLK jitter p-p | 141.7–177.4 ps | <strong>No trend</strong> — random variation |<br>| CLK jitter RMS | 52.2–56.6 ps | Stable |<br>| LP-11 voltage | 1.013–1.016 V | <strong>No drift</strong> — thermally stable |<br>| 1.8 V mean | 1.7644–1.7705 V | Stable |<br>| 1.8 V droop | 8.4–17.4 mV | No trend, occasional spikes (0137: 13.3, 0144: 17.4, 0154: 13.7, 0163: 13.6, 0165: 13.7) |<br>| LP-low plateau | 0–343 ns | <strong>Trimodal:</strong> 0 ns, ~108 ns, ~343 ns |<br>| DAT0 sub-140mV count | 16–9742 | High variance; spikes in 0141 (3347), 0143 (6189), 0151 (3815), 0166 (9742) |</p>
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<p><strong>No progressive degradation.</strong> The system is thermally and electrically stable during a session. The variation is entirely in the SoT-moment behaviour, consistent with the bistable flicker description.</p>
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<ul><li></li></ul>
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<p>## 3. Anomalies</p>
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<p>### FLICKER EVENT — Capture 0164<br>- <strong>LP-low plateau = 0 ns</strong> — the LP-01/LP-00 SoT states are <strong>completely absent</strong><br>- LP exit → HS = 2 ns (spec ≥ 50 ns)<br>- LP-11 voltage = 1.015 V (normal)<br>- 1.8 V supply: mean 1.7665 V, droop 10.5 mV, ripple 6.01 mV — <strong>nothing abnormal</strong><br>- Register values: identical 'Round Best' violations as all other captures</p>
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<p><strong>This confirms the root cause is timing, not supply:</strong> the SN65DSI83 never saw the LP-00 state, so it could not detect SoT and never locked to the HS data stream.</p>
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<p>### DAT0 sig Capture Anomalies<br>- <strong>0138, 0146, 0152, 0154, 0158, 0165:</strong> sig/dat shows 0.0 mV — "No HS signal detected." These captures caught the data lane during an LP-idle or blanking gap. This is a <strong>trigger timing issue</strong>, not a signal problem.<br>- <strong>0141 sig/dat:</strong> 324.8 mV differential — <strong>exceeds spec max 270 mV.</strong> This is likely an overshoot/ringing event captured during a transition. The CLK lane in the same capture is normal (166.8 mV), confirming the data lane has a reflection or impedance discontinuity that occasionally produces overshoot.</p>
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<p>### DAT0 "Only Negative Swings"<br>Nearly every sig/dat capture shows only negative Vdiff with zero positive swing. This means the <strong>scope capture window consistently catches the same bit pattern</strong> (likely repeated zeros or sync bytes). The amplitude is likely underestimated by ~2×; true differential amplitude is probably ~390 mV, well within spec. However, the capture methodology should be verified — the sig trigger may need adjustment to catch both polarities.</p>
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<p>### LP-Low Plateau Trimodal Distribution<br>| LP-low (ns) | Captures | Interpretation |<br>|-------------|----------|----------------|<br>| 0 | 0164 (flicker) | SoT completely missing — bridge fails to lock |<br>| ~108 | 0139, 0143, 0148, 0155, 0159 | Marginal — ~2 TLPX, borderline for SN65DSI83 |<br>| ~343 | All others | ~6 TLPX — this is the "normal" case |</p>
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<p>The ~108 ns group didn't flicker in this batch but represents a <strong>secondary risk tier</strong>. The quantisation into three discrete values suggests the PHY state machine has a timing race: it either completes the full LP-01→LP-00 sequence (~343 ns), partially completes it (~108 ns), or skips it entirely (0 ns / flicker).</p>
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<p>### Capture 0145 — LP Data Processing Error<br>`[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000` — the LP capture buffer was exactly full, causing an off-by-one indexing error in post-processing. <strong>No LP data for this capture.</strong> This is a script bug, not a signal issue.</p>
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<ul><li></li></ul>
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<p>## 4. Supply Correlation Analysis</p>
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<p>| Metric | Flicker Capture (0164) | Non-Flicker Mean (n=28) | Correlation |<br>|--------|----------------------|------------------------|-------------|<br>| 1.8 V mean | 1.7665 V | 1.7658 V | None |<br>| 1.8 V min | 1.7560 V | 1.7556 V | None |<br>| Droop depth | 10.5 mV | 10.6 mV | None |<br>| Ripple RMS | 6.01 mV | 5.76 mV | None |</p>
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<p><strong>No supply correlation whatsoever.</strong> The 1.8 V rail is well within spec (1.71–1.89 V) in all captures, droop is modest (< 18 mV), and the flicker capture has completely average supply behaviour. The LP-11 voltage at 1.015 V in the flicker capture is indistinguishable from non-flicker captures. <strong>Supply is definitively ruled out as a contributing factor.</strong></p>
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<ul><li></li></ul>
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<p>## 5. WARNING/ERROR Explanation</p>
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<p>| Warning | Cause | Action |<br>|---------|-------|--------|<br>| "CLK lane is in continuous HS mode — LP states not expected on CLK" | Normal — DSIM runs CLK in continuous HS mode per SN65DSI83 requirement | None needed |<br>| "LP exit duration N ns below spec min 50 ns" | THS_PREPARE+THS_ZERO too short (166.7 ns vs 168.2 ns spec); PHY truncates LP-00 state non-deterministically | <strong>Switch to 'Round Up' registers</strong> |<br>| "Only negative swings in capture window" | Repetitive bit pattern in short sig capture window | Widen sig capture window or trigger on random data |<br>| "No HS signal detected — line may be in LP state or idle" | Trigger caught blanking interval | Add trigger holdoff or qualify trigger on active video |<br>| "N settled samples below 140 mV" | ISI eye closure during transitions; amplitude near spec floor | Normal for 432 Mbit/s with this trace geometry |<br>| "Vdiff 325 mV above spec max 270 mV" (0141) | Impedance mismatch causing overshoot on data lane | Check DAT0± trace impedance, termination, via stubs |<br>| "index 200000 out of bounds" (0145) | Off-by-one bug in LP analysis script | Fix: use `< len(array)` not `<= len(array)` |</p>
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<ul><li></li></ul>
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<p>## 6. Actionable Recommendations</p>
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<p>### PRIMARY FIX (Critical — eliminates root cause)<br><strong>Switch from 'Round Best' to 'Round Up' PHY timing registers:</strong></p>
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<p>```<br># In device tree or driver override:<br>DSIM_PHYTIMING (0xb4) = 0x00000306 # THS_EXIT=6 → 111.1 ns ✓<br>DSIM_PHYTIMING1 (0xb8) = 0x030f0a04 # TCLK_PREPARE=3, TCLK_ZERO=15, TCLK_TRAIL=4 ✓<br>DSIM_PHYTIMING2 (0xbc) = 0x00030706 # THS_ZERO=7, THS_TRAIL=6 ✓<br>```</p>
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<p>This eliminates all 5 D-PHY violations. The key change is <strong>THS_PREPARE+THS_ZERO = 10 bc (185.2 ns)</strong> vs the current 9 bc (166.7 ns) — an extra 18.5 ns for the bridge to detect LP-00 and synchronise. This directly addresses the non-deterministic SoT failure.</p>
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<p><strong>Implementation path:</strong> In the `samsung-dsim` driver (`drivers/gpu/drm/bridge/samsung-dsim.c`), the timing calculation function `samsung_dsim_set_phy_ctrl()` uses a rounding mode. The default rounds to the nearest byte-clock ('Round Best'). Override this to always round up:<br>- Patch the driver to use `DIV_ROUND_UP` instead of `DIV_ROUND_CLOSEST` for all timing parameters, OR<br>- Apply the register values directly via device tree `phy-timing` properties if supported by your BSP.</p>
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<p>### SECONDARY (Recommended — improves margin)<br>1. <strong>Investigate LP-11 voltage:</strong> 1.015 V is technically compliant but dangerously low. Check if the VDDIO_MIPI domain has a series resistance or if LP pull-ups are undersized. The SN65DSI83 datasheet specifies VIH_LP ≥ 1.0 V, so 1.015 V gives only 15 mV of noise margin. If possible, ensure VDDIO is at 1.80 V nominal (currently 1.766 V — check LDO/DCDC output voltage setting and load regulation).</p>
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<ol><li><strong>Investigate DAT0 impedance:</strong> The 324.8 mV overshoot in Capture 0141 and the consistent CLK common-mode offset (+29 mV) suggest minor impedance discontinuities. Review:</li><li>DAT0± trace impedance (target 100Ω differential)</li><li>Via stubs at connector transitions</li><li>SN65DSI83 input termination (internal 100Ω)</li></ol>
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<ol><li><strong>Increase CLK amplitude margin:</strong> CLK Vdiff at 166 mV with sub-140 mV samples means the eye is marginal. If the i.MX 8M Mini DPHY allows TX emphasis or amplitude adjustment (DSIM_PLLCTRL or analog trim registers), increase CLK drive strength by one step.</li></ol>
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<p>### TERTIARY (Measurement improvement)<br>4. Fix the LP analysis script off-by-one error (Capture 0145).<br>5. Adjust sig/dat trigger to capture both positive and negative differential swings for accurate amplitude measurement.<br>6. Consider a longer proto capture window to reduce the variability in sub-140 mV sample counts.</p>
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<ul><li></li></ul>
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<p>## 7. Summary</p>
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<p><strong>The system is running non-compliant D-PHY timing ('Round Best' mode) with 5 spec violations that create a narrow, non-deterministic SoT failure window.</strong> The flicker event (Capture 0164, LP-low = 0 ns) is a direct consequence: the programmed THS_PREPARE+THS_ZERO is 1.5 ns short of spec, causing the LP-00 state to be occasionally skipped entirely, which prevents the SN65DSI83 from detecting Start-of-Transmission and locking to HS data. Supply rail, temperature, and HS signal quality are all stable and uncorrelated with the failure.</p>
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<p><strong>Switching to the 'Round Up' register set (0x00000306 / 0x030f0a04 / 0x00030706) will make all timing parameters D-PHY v1.1 compliant and is expected to eliminate the intermittent flicker.</strong> This is a software-only change with no hardware modification required. The 3% flicker rate at current timing margins should drop to 0% with the added ~18.5 ns of THS_ZERO headroom.</p>
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<p class="tokens">Tokens: 45384 in / 3941 out</p>
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</body>
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</html>
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