MIPI D-PHY Analysis Report

Generated: 2026-04-09 12:35:40  |  Scope: Captures 0137–0166  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0137–0166

## 1. Executive Summary

The system has a systematic SoT failure mechanism on the data lane. Every single capture (30/30) shows LP exit → HS timing of 0–4 ns, violating the MIPI D-PHY ≥50 ns TLPX minimum by an order of magnitude. The flicker-correlated captures (6/30, 20%) are distinguished solely by LP-low plateau = 0 ns (completely absent LP-00 state), while non-flicker captures show LP-low plateaux of 108–343 ns. The root registers are wrong — the driver is programming `0x00000305` / `0x020e0a03` / `0x00030605` instead of the target values `0x00000306` / `0x03110A04` / `0x00040A03`, resulting in under-specified TLPX, TCLK_PREPARE, TCLK_ZERO, THS_PREPARE, THS_ZERO, and THS_TRAIL durations. The SN65DSI83 bridge is at the edge of its SoT detection window; when the LP-00 state is entirely absent, the bridge fails to lock.

## 2. Register Analysis — Root Cause

### Actual vs. Target Register Values

| Register | Actual | Target | Status |
|---|---|---|---|
| PHYTIMING (0xb4) | `0x00000305` | `0x00000306` | WRONG |
| PHYTIMING1 (0xb8) | `0x020e0a03` | `0x03110A04` | WRONG |
| PHYTIMING2 (0xbc) | `0x00030605` | `0x00040A03` | WRONG |

### Field-by-Field Decode (all 30 captures identical)

| Field | Actual (byte-clk) | Actual (ns) | Target (byte-clk) | Target (ns) | D-PHY Spec Min | Verdict |
|---|---|---|---|---|---|---|
| TLPX | 3 | 55.6 ns | 3 | 55.6 ns | 50 ns | ✓ marginal |
| THS_EXIT | 5 | 92.6 ns | 6 | 111.1 ns | 100 ns | ✗ FAIL |
| TCLK_PREPARE | 2 | 37.0 ns | 3 | 55.6 ns | 38 ns | ✗ MARGINAL/FAIL |
| TCLK_ZERO | 14 (0x0e) | 259.3 ns | 17 (0x11) | 314.8 ns | 300 ns | ✗ FAIL |
| TCLK_POST | 10 (0x0a) | 185.2 ns | 10 (0x0a) | 185.2 ns | 180 ns | ✓ marginal |
| TCLK_TRAIL | 3 | 55.6 ns | 4 | 74.1 ns | 60 ns | ✗ FAIL |
| THS_PREPARE | 3 | 55.6 ns | 3 | 55.6 ns | 40+4×UI=49.3 ns | ✓ |
| THS_ZERO | 6 | 111.1 ns | 10 (0x0a) | 185.2 ns | 145+10×UI=168.2 ns | ✗ FAIL |
| THS_TRAIL | 5 | 92.6 ns | 4 | 74.1 ns | max(8×UI,60+4×UI)=69.3 ns | ✓ over-spec |

Five fields are out of MIPI D-PHY v1.1 spec. The critical ones for SoT are:

• THS_EXIT = 5 (92.6 ns) < 100 ns spec minimum: The HS-exit-to-LP transition is too short. This directly controls how long the line dwells in LP states before re-entering HS.
• THS_ZERO = 6 (111.1 ns) < 168 ns spec minimum: The HS-0 state before the sync sequence is 34% too short. The receiver has less time to acquire the HS common mode and prepare for data.
• TCLK_ZERO = 14 (259 ns) < 300 ns spec minimum: The clock lane HS-0 preamble is 14% too short.
• TCLK_TRAIL = 3 (55.6 ns) < 60 ns spec minimum: Clock trail is too short.
• TCLK_PREPARE = 2 (37 ns): At the absolute floor of the 38–95 ns window; likely below spec with any layout/probe derating.

### Why The Driver Is Writing Wrong Values

The samsung-dsim driver computes PHY timing from the HS bit rate using a formula with integer truncation. At 432 Mbit/s (a relatively low MIPI rate), several fields truncate to values 1 byte-clock below the spec-compliant minimum. The driver's automatic calculation does not match the target values. This is a known issue with the samsung-dsim / sec-dsim timing computation at low bit rates — the rounding is not conservative enough.

## 3. LP Timing Analysis — Flicker Mechanism

### LP-Low Plateau Distribution

| LP-low plateau (ns) | Count | Flicker? |
|---|---|---|
| 0 (absent) | 6 | ALL 6 FLICKER |
| 108 | 7 | 0 flicker |
| 144 | 1 | 0 flicker |
| 342–343 | 16 | 0 flicker |

Perfect correlation: LP-low plateau = 0 ↔ flicker. No capture with LP-low ≥ 108 ns produced flicker; every capture with LP-low = 0 ns did.

### LP Exit Duration

Every capture shows LP exit → HS of 0–4 ns (spec minimum 50 ns). This is not a measurement artifact — it is a consequence of THS_EXIT = 5 byte-clocks (92.6 ns) which is already below the 100 ns minimum, combined with the oscilloscope's single-ended LP measurement resolving the transition as essentially instantaneous.

### Why LP-Low Is Non-Deterministic

The LP-low plateau clusters into three values (0, ~108, ~343 ns), suggesting the DSIM IP has a race condition between the LP state machine and the HS transmitter enable. The LP-00 state is supposed to persist for THS_PREPARE + THS_ZERO ≈ 167 ns (at target values), but the actual programmed THS_ZERO = 6 (111 ns) is so short that, depending on internal clock-domain synchronization:

• Best case (~60% of captures): LP-00 holds for ~343 ns (≈ TCLK_ZERO + margin) — the clock lane's longer preparation masks the data lane's short state.
• Middle case (~27%): LP-00 holds for ~108 ns (≈ THS_ZERO actual + jitter) — data lane barely completes its sequence.
• Worst case (~20%): LP-00 is completely skipped — the HS transmitter fires before the LP driver has asserted the 00 state. The SN65DSI83 never sees a valid SoT and fails to lock.

This race is exacerbated by:
1. THS_ZERO being 34% below spec (111 ns vs. 168 ns required)
2. THS_EXIT being below spec (92.6 ns vs. 100 ns), leaving insufficient LP-11 dwell time before the next SoT
3. TCLK_ZERO being below spec (259 ns vs. 300 ns), reducing the clock-lane preamble that normally provides timing margin

## 4. HS Signal Quality

### Clock Lane — Stable, Minor Concern
- Amplitude: 175.4–177.9 mV — consistent, well within 140–270 mV spec
- Asymmetry: +190 / −163 mV typical — +27 mV positive bias (common mode +13–15 mV). Acceptable but indicates slight termination mismatch.
- Rise time: 135–154 ps (20–80%) — excellent
- Jitter: 99–138 ps p-p, 26–29 ps RMS — acceptable for 432 Mbit/s
- Sub-140 mV samples: Present in every proto capture (125–1555 samples). These are transition-region samples, not settled violations. The long-window capture catches more edges. Not a concern at this rate.

### Data Lane — Measurement Artifact Dominates
- Only-negative-swing warning appears in 22/30 sig/dat captures: The oscilloscope trigger is catching the same polarity bit pattern consistently. This is a trigger/capture window artifact, not a real asymmetry.
- Zero-amplitude sig/dat in captures 0146, 0148, 0163, 0166: The high-res capture window landed during blanking (LP state or idle). Three of these four are flicker captures — consistent with the bridge not being in HS mode.
- Proto dat sub-140 mV counts vary widely (62 to 16,096): This reflects different data patterns in the long capture window. Not a degradation indicator.
- Settled amplitude: 181–224 mV when valid — healthy.

### No Amplitude Drift
No systematic trend in clock or data amplitude across the 30-capture sequence. The signal path is thermally and electrically stable.

## 5. Supply Rail Analysis

### 1.8 V Rail — Acceptable, No Flicker Correlation

| Metric | Range | Spec | Verdict |
|---|---|---|---|
| Mean | 1.7633–1.7685 V | 1.71–1.89 V | ✓ |
| Min | 1.7480–1.7600 V | ≥1.71 V | ✓ |
| Droop | 7.5–17.1 mV | — | Mild |
| Ripple RMS | 4.98–5.59 mV | — | Low |

Droop vs. Flicker Correlation:

| Capture | Flicker | Droop (mV) |
|---|---|---|
| 0143 | YES | 7.5 |
| 0148 | YES | 12.2 |
| 0152 | YES | 12.5 |
| 0156 | YES | 11.3 |
| 0159 | YES | 8.7 |
| 0166 | YES | 11.9 |
| Flicker mean | | 10.7 |
| Non-flicker mean | | 9.5 |

The difference is negligible (1.2 mV). The largest droop (17.1 mV, capture 0164) did NOT produce flicker. Supply droop is not the cause. The LP-11 voltage is rock-solid at 1.015–1.016 V across all captures — the LP driver pull-ups are healthy.

## 6. Anomaly Summary

| Finding | Severity | Captures Affected | Cause |
|---|---|---|---|
| LP exit 0–4 ns (spec ≥50 ns) | CRITICAL | 30/30 (100%) | THS_EXIT, THS_ZERO under-programmed |
| LP-low plateau = 0 ns | CRITICAL | 6/30 (flicker events) | Race condition from short THS_ZERO |
| THS_EXIT < 100 ns | SPEC VIOLATION | 30/30 | Register 0xb4 field wrong |
| THS_ZERO < 168 ns | SPEC VIOLATION | 30/30 | Register 0xbc field wrong |
| TCLK_ZERO < 300 ns | SPEC VIOLATION | 30/30 | Register 0xb8 field wrong |
| TCLK_TRAIL < 60 ns | SPEC VIOLATION | 30/30 | Register 0xb8 field wrong |
| TCLK_PREPARE at floor | MARGINAL | 30/30 | Register 0xb8 field wrong |
| CLK +27 mV amplitude asymmetry | Minor | 30/30 | Termination/layout mismatch |
| Sig/dat zero amplitude | Info | 4/30 | Capture during blanking |
| Sig/dat only-negative-swing | Info | 22/30 | Trigger alignment artifact |

## 7. Actionable Recommendations

### ① IMMEDIATE — Fix PHY Timing Registers (PRIMARY FIX)

Override the samsung-dsim driver's automatic timing computation and force the target values:

```
DSIM_PHYTIMING (0x32e100b4) = 0x00000306
DSIM_PHYTIMING1 (0x32e100b8) = 0x03110A04
DSIM_PHYTIMING2 (0x32e100bc) = 0x00040A03
```

Implementation options (choose one):

Option A — Device Tree override (preferred):
If the samsung-dsim driver supports `samsung,phy-timing` or equivalent DT properties, set all fields explicitly. Check the binding documentation.

Option B — Driver patch:
In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim`), locate the `samsung_dsim_set_phy_timing()` function and either:
- Add a post-computation fixup that clamps each field to the MIPI spec minimum, OR
- Replace the automatic computation with a lookup table for 432 Mbit/s

Option C — Runtime memtool (test only):
```bash
# Write AFTER the driver initializes, BEFORE enabling video output
memtool mw -l 0x32e100b4=0x00000306
memtool mw -l 0x32e100b8=0x03110A04
memtool mw -l 0x32e100bc=0x00040A03
```
This confirms the fix before committing to a driver change.

### ② Add Margin Beyond Spec Minimums

For production robustness, consider adding 1 byte-clock (18.5 ns) of margin to the most critical fields:

| Field | Target | With Margin | ns |
|---|---|---|---|
| THS_EXIT | 6 | 7 | 129.6 ns |
| THS_ZERO | 10 | 11 | 203.7 ns |
| TCLK_ZERO | 17 | 18 | 333.3 ns |

This eliminates the race condition entirely by ensuring the LP-00 state persists well beyond the SN65DSI83's detection window.

### ③ Verify All 4 Data Lanes

These captures only show DAT0. The other three data lanes share the same PHYTIMING2 register, so they have the same violations. However, verify with a scope that all lanes exhibit the fix after the register change.

### ④ Address Clock Lane Asymmetry (Low Priority)

The +27 mV positive/negative amplitude mismatch on CLK (e.g., +191 / −163 mV) suggests a ~15% termination imbalance. Check:
- 100Ω differential termination resistor tolerance at the SN65DSI83 input
- Any asymmetric stubs or vias on CLK_P vs CLK_N traces
- This is not causing the flicker but may reduce margin at higher bit rates

### ⑤ Measurement Setup Improvement (Low Priority)

• The "only negative swings" artifact on sig/dat suggests the trigger is synced to a specific clock edge that always captures the same data polarity. Use random triggering or a longer capture window.
• The zero-amplitude sig/dat captures during blanking are expected in non-continuous-clock data lane measurements, but consider trigg

Tokens: 34006 in / 4096 out