MIPI Interactive Flicker Test Report
Generated: 2026-04-16 08:33:00 |
Model: claude-opus-4-6
Stop reason: Test interrupted by operator (Ctrl+C)
0 confirmed flicker(s)
2 false alarm(s)
0 Claude said no
Event Log
| Capture | Timestamp | Channel |
LP-low plateau | LP exit→HS | LP-11 voltage |
Claude: flicker? | Outcome |
| 0005 | 20260416_082936 | dat | 0.3 ns | 2.8 ns | 1.015 V | YES | ✓ FALSE ALARM |
| 0010 | 20260416_083201 | dat | 0.3 ns | 348.0 ns | 1.015 V | YES | ✓ FALSE ALARM |
Claude Assessments
Capture 0005 [20260416_082936] — FALSE ALARM
YES
The LP-low plateau measured at effectively 0 ns (reported as 0.3 ns by the flag, 0 ns in the full summary) is drastically below the 50 ns minimum required by the SN65DSI83 to detect the SoT preamble. The LP exit-to-HS transition of only 3 ns confirms that the LP-01/LP-00 states were essentially skipped entirely, meaning the bridge had no opportunity to recognize the start-of-transmission sequence. With the SoT undetectable, the bridge would fail to synchronize to the incoming HS burst, resulting in a missed video frame and visible flicker.
Capture 0010 [20260416_083201] — FALSE ALARM
YES
The LP-low plateau measured only 0.3 ns, which is effectively absent and far below the SN65DSI83's required ≥ 50 ns minimum for reliable SoT detection. Without a properly formed LP-01/LP-00 preamble, the bridge cannot recognize the start-of-transmission, causing it to miss the incoming HS burst entirely. Although the LP-11 voltage (1.015 V) and overall LP-exit-to-HS timing (348 ns) are within spec, the critical SoT signaling is fundamentally broken in this capture, making visible display flicker virtually certain.