MIPI D-PHY Analysis Report

Generated: 2026-04-15 15:31:13  |  Scope: Captures 1299–1328  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis Report

## Batch: Captures 1299–1328 (30 pipeline load/unload cycles)

## 1. Consistent Spec Concerns

### A. Register Timing — Universal, Every Capture
All 30 captures show identical register values (`Round Best` mode) with 5 D-PHY v1.1 violations:

| Parameter | Measured | Spec Min | Deficit | Severity |
|-----------|----------|----------|---------|----------|
| THS_EXIT | 92.6 ns | 100.0 ns | −7.4 ns | HIGH — affects LP→HS exit handshake |
| TCLK_PREPARE | 37.0 ns | 38.0 ns | −1.0 ns | CRITICAL — clock SoT preamble too short |
| TCLK_TRAIL | 55.6 ns | 60.0 ns | −4.4 ns | MODERATE — affects HS→LP teardown |
| TCLK_PREPARE+TCLK_ZERO | 296.3 ns | 300.0 ns | −3.7 ns | CRITICAL — clock lane init sequence truncated |
| THS_PREPARE+THS_ZERO | 166.7 ns | 168.2 ns | −1.5 ns | CRITICAL — data lane SoT sequence truncated |

Key insight: The TCLK_PREPARE and THS_PREPARE+THS_ZERO violations directly shorten the SoT preamble the SN65DSI83 must detect. Combined with THS_EXIT being short, the receiver has a compressed detection window on every single startup. The system works most of the time because the SN65DSI83 has some internal tolerance, but the margins are razor-thin.

### B. LP-Exit Duration — Universal Violation
Every capture with LP data (28 of 30) shows LP exit → HS of 0–4 ns against a spec minimum of 50 ns. This is not a measurement artifact — it confirms the PHY is driving LP-01/LP-00 states for effectively zero time at the scope's resolution, consistent with the truncated TCLK_PREPARE and THS_PREPARE+THS_ZERO register values.

### C. LP-11 Voltage — Marginal but Passing
LP-11 consistently measures 1.014–1.016 V (spec 1.0–1.45 V). This is only 14–16 mV above the lower spec limit on a 1.8 V VDDIO rail. With VDDIO measured at ~1.766 V, the LP-11 level is 56.4% of VDDIO rather than the expected ~VDDIO. This suggests the LP drivers have significant series impedance or the probe loading/termination at the SN65DSI83 input is pulling the LP level down. While technically in-spec, this reduces the SN65DSI83's LP-11 detect margin.

### D. HS Amplitude — Clock Lane Asymmetry
Clock differential: consistently +195 / −137 mV (common mode +29 mV). The positive swing is 42% larger than negative, indicating a systematic offset in the clock lane driver or termination. The mean amplitude (~166 mV) is within spec but only 26 mV above the 140 mV floor. Multiple captures show 20–124 settled samples below 140 mV, confirming the clock eye is clipping the spec floor on some transitions.

Data lane amplitude (~187–195 mV) is better centered but also shows sub-140 mV samples in many captures.

## 2. Trends Across Captures

### A. No Drift — System Is Stationary
| Parameter | Range Across 30 Captures | Trend |
|-----------|--------------------------|-------|
| CLK Vdiff amplitude | 166.1–166.9 mV | Flat (< 1 mV variation) |
| DAT Vdiff amplitude | 186.5–223.9 mV | Capture-dependent (see §3) |
| CLK jitter p-p | 145.8–169.9 ps | No trend |
| CLK jitter RMS | 51.8–56.7 ps | No trend |
| LP-11 voltage | 1.014–1.016 V | Flat |
| 1.8 V mean | 1.764–1.771 V | Flat |
| 1.8 V droop | 7.2–18.3 mV | No trend |
| Register values | Identical all captures | No change |

Conclusion: There is no progressive degradation. The problem is purely a startup race condition, consistent with the reported bistable behaviour.

### B. LP-Low Plateau — Bimodal Distribution
The LP-low plateau measurement shows a striking bimodal pattern:

| LP-low Plateau | Count | Sessions | Flicker? |
|----------------|-------|----------|----------|
| 342–348 ns | 16 | Good + some marginal | Mostly no |
| 108 ns | 6 | Mixed | No (in these captures) |
| 0–1 ns | 5 | 1302, 1306, 1309, 1315, 1324 | YES — all flicker |
| Error/missing | 2 | 1303, 1322 | Unknown |

This is the smoking gun: when the LP-low plateau collapses to 0–1 ns, the SN65DSI83 cannot detect the SoT entry sequence and the bridge fails to lock. The 342 ns plateau corresponds to approximately 18.5 byte-clock periods — consistent with the programmed THS_PREPARE + THS_ZERO = 9 bc on the data lane (the scope measures both the low-going prepare and zero states as one contiguous low region, and the clock lane's TCLK_PREPARE + TCLK_ZERO = 16 bc adds to this window). When the PHY's internal state machine occasionally skips or truncates the LP-01→LP-00 sequence, the plateau vanishes entirely.

## 3. Anomalies

### A. Flicker Captures — LP-Low Plateau Absent
Captures 1302, 1306, 1309, 1315, 1324 (all confirmed flicker):
- LP-low plateau: 0 ns (1302, 1309, 1315, 1324) or 1 ns (1306)
- HS amplitude (single-ended): 24–34 mV — dramatically lower than the ~104–120 mV seen in good sessions
- This low HS amplitude in flicker captures indicates the data lane never properly entered HS mode — the SoT handshake failed, and what the scope captures as "HS" is likely residual coupling or a partially driven state

### B. Data Lane "Only Negative Swings" Warning
Many captures (both good and bad) report `Only negative swings in capture window` on DAT0 sig/proto channels. This is a probe/trigger alignment issue: the oscilloscope capture window happened to land on a data pattern that is predominantly one polarity. It does not indicate a fault, but it means the reported amplitude is a lower bound. This is benign.

### C. Data Lane Amplitude Bimodality in Proto Captures
Several captures show DAT0 proto amplitudes of 222–224 mV with an asymmetric swing (+200/−247 mV, CM = −23 mV):
- Captures 1301, 1304, 1322 (all non-flicker)
- These coincide with slightly lower clock frequencies (~213.4 MHz vs. nominal 216 MHz)
- This may represent a different data pattern in the capture window or a transient PLL settling artefact at startup. Not directly correlated with flicker.

### D. Processing Errors
- Capture 1303 and 1322: `[lp_dat] ERROR: index 200000 is out of bounds` — the LP waveform processing script hit the end of the capture buffer, likely because the LP→HS transition occurred at the very edge of the acquisition window. These two captures could not be assessed for LP timing. Recommendation: increase capture record length or adjust trigger position.

### E. DAT0 sig = 0.0 mV
Captures 1304, 1305, 1317: `No HS signal detected` on DAT0 sig channel. The high-res capture window missed the data lane HS content entirely (either blanking interval or trigger misalignment). Not a hardware fault — the proto and LP captures from the same sessions are normal.

## 4. Supply Correlation Analysis

### A. 1.8 V Supply vs. LP Anomalies

| Capture | Flicker? | LP-low (ns) | V_mean (V) | V_min (V) | Droop (mV) | Ripple RMS (mV) |
|---------|----------|-------------|------------|-----------|------------|-----------------|
| 1302 | YES | 0 | 1.7656 | 1.7560 | 9.6 | 5.61 |
| 1306 | YES | 1 | 1.7665 | 1.7560 | 10.6 | 5.80 |
| 1309 | YES | 0 | 1.7655 | 1.7560 | 9.5 | 5.41 |
| 1315 | YES | 0 | 1.7667 | 1.7560 | 10.7 | 5.86 |
| 1324 | YES | 0 | 1.7656 | 1.7560 | 9.6 | 5.53 |
| Good avg | No | 108–348 | 1.766 | 1.756 | 10.5 | 5.70 |

Conclusion: No supply correlation. The flicker captures show identical supply characteristics to good captures:
- Mean voltage: indistinguishable (~1.766 V in both)
- Minimum voltage: identical (1.756 V)
- Droop: 9.5–10.7 mV for flicker vs. 7.2–18.3 mV for all captures — flicker sessions are actually in the *lower* droop range
- Ripple RMS: 5.41–5.86 mV — squarely in the middle of the full population

The 1.8 V supply is not the root cause. The supply is well within spec (1.71–1.89 V) at all times and shows no correlation with SoT failures.

## 5. WARNING/ERROR Explanation

| Warning/Error | Likely Cause | Action |
|---------------|-------------|--------|
| `LP exit duration X ns below spec min 50 ns` | PHY timing registers too short — THS_EXIT=5bc, THS_PREPARE+THS_ZERO=9bc produce SoT states near the minimum; PHY internal jitter occasionally eliminates them entirely | Switch to Round Up register values |
| `FLICKER SUSPECT: LP-low plateau absent or < 50 ns` | SoT LP-01→LP-00 states skipped or truncated below scope resolution; SN65DSI83 cannot detect Start-of-Transmission | Root cause — register fix required |
| `Only negative swings in capture window` | Scope triggered on a data symbol that happened to be low for the entire capture window; amplitude underestimated | Benign — no action needed. Increase capture length if accurate amplitude stats are required |
| `No HS signal detected — line may be in LP state or idle` | High-res capture window landed in blanking interval or LP state | Adjust trigger delay for sig captures; not a hardware fault |
| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal — Samsung DSIM uses continuous clock mode; CLK lane doesn't return to LP-11 between frames | Expected behaviour, no action |
| `101/113/... settled samples below 140 mV` | Clock amplitude of 166 mV has only 26 mV margin above 140 mV floor; transitions and ISI dip below threshold | Monitor — not immediately actionable but indicates the PHY is near its low-amplitude limit |
| `index 200000 is out of bounds` | Processing script ran past end of LP capture buffer | Increase scope record length or adjust trigger position to ensure SoT transition is fully captured |

## 6. Actionable Recommendations

### IMMEDIATE — Register Fix (PRIMARY FIX)

Switch from `Round Best` to `Round Up` PHY timing values:

```
# From device tree or driver override:
DSIM_PHYTIMING (0xb4): 0x00000306 (was 0x00000305)
DSIM_PHYTIMING1 (0xb8): 0x030f0a04 (was 0x020e0a03)
DSIM_PHYTIMING2 (0xbc): 0x00030706 (was 0x00030605)
```

Field-by-field changes:

| Field | Old (bc) | New (bc) | Old (ns) | New (ns) | Spec Min | Effect |
|-------|----------|----------|----------|----------|----------|--------|
| THS_EXIT | 5 | 6 | 92.6 | 111.1 | 100.0 | Now compliant |
| TCLK_PREPARE | 2 | 3 | 37.0 | 55.6 | 38.0 | Now compliant, +50% margin |
| TCLK_ZERO | 14 | 15 | 259.3 | 277.8 | (combined) | — |
| TCLK_PREPARE+ZERO | 16 | 18 | 296.3 | 333.3 | 300.0 | Now compliant, +11% margin |
| TCLK_TRAIL | 3 | 4 | 55.6 | 74.1 | 60.0 | Now compliant |
| THS_ZERO | 6 | 7 | 111.1 | 129.6 | (combined) | — |
| THS_PREPARE+ZERO | 9 | 10 | 166.7 | 185.2 | 168.2 | Now compliant, +10% margin |
| THS_TRAIL | 5 | 6 | 92.6 | 111.1 | 69.3 | Extra margin |

Implementation path — samsung-dsim driver:

The samsung-dsim (sec-dsim) driver computes these values in `samsung_dsim_set_phy_timing()`. The rounding mode is typically controlled by the `samsung,phy-timing` property or an internal calculation. Options:

1. Preferred: Patch the driver's timing calculation to use ceiling (round-up) instead of round-to-nearest for all parameters. This is a one-line change in the rounding function.
2. Alternative: Override the timing registers directly via device tree `samsung,phy-timing = <0x00000306 0x030f0a04 0x00030706>;` if the driver supports it.
3. Fallback: Write the registers directly from userspace after boot via `memtool` / `devmem2` as a validation step, then commit the change to the driver.

### SECONDARY — LP-11 Voltage Investigation

The LP-11 level of 1.014–1.016 V (56% of VDDIO) is unusually low. While in-spec, it suggests:
- Check for excessive series resistance in the LP driver path (SOM trace, connector, cable to SN65DSI83)
- Verify the SN65DSI83 input termination matches the design — its LP input impedance may be loading the line excessively
- Confirm MIPI_DPHY_CON register (if accessible) is set for correct LP driver impedance

### TERTIARY — Clock Lane Amplitude Asymmetry

The +195/−137 mV asymmetry (CM offset +29 mV) on the clock lane suggests:
- Slight termination mismatch between CLK_P and CLK_N at the receiver
- Or a systematic PHY driver offset
- While not causing flicker, it reduces the clock eye margin. Check 100Ω differential termination at the SN65DSI83 CLK input and verify PCB trace matching.

### MONITORING

After applying the

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