MIPI D-PHY Analysis Report

Generated: 2026-04-15 11:11:34  |  Scope: Captures 0635–0664  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0635–0664 (30 Sessions)

## 1. Consistent Spec Concerns

### A. PHY Timing Registers: 5 D-PHY v1.1 Violations (Every Capture)

All 30 captures show identical register values — the 'Round Best' non-compliant mode:

| Parameter | Programmed | Actual | Spec Min | Shortfall |
|---|---|---|---|---|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns |

Impact: The first two violations (TCLK_PREPARE short, THS_PREPARE+THS_ZERO short) directly truncate the SoT sequence that the SN65DSI83 must detect. The short THS_EXIT means the data lane may not fully exit HS before re-entering LP, compressing the LP-01→LP-00 window. These are not "almost compliant" — they are systematically below spec on every single boot, creating a baseline where the SN65DSI83's SoT detector is already operating at the edge of its capture window.

### B. LP-Exit Duration: Universally Violated

Every single capture (where LP data was measurable) shows `LP exit → HS` of 1–4 ns against a 50 ns spec minimum. Even the "good" (no-flicker) captures violate this. This means:

• The D-PHY LP-01→LP-00 state machine transitions are being driven far faster than spec
• The PHY is effectively skipping the LP-01/LP-00 signalling states as distinct resolvable events
• The SN65DSI83 must detect SoT from a sub-5 ns edge, which is unreliable by design

### C. LP-11 Voltage: Marginal but Within Spec

All captures: 1.011–1.016 V (spec 1.0–1.45 V). This is at the absolute floor of the valid range. At 1.015 V typical with 1.8 V VDDIO, the LP driver is pulling only 56% of supply. This is consistent with the weak LP driver output seen in this PHY at low VDDIO.

### D. CLK Lane: Continuous HS Mode

CLK is always in continuous HS — no LP states expected. This is normal for video-mode DSI but means the SN65DSI83 relies entirely on data lane SoT detection for frame sync.

### E. HS Amplitude: CLK Lane Near Floor

CLK differential amplitude: 164.2–166.5 mV with consistent sub-140 mV samples (24–172 per capture). This is only 18% above the 140 mV minimum. DAT0 amplitude is healthier at ~187–195 mV but shows asymmetric swings in many captures.

## 2. Trends Across 30 Captures

### No Degradation Over Time — Confirms Bistable Model

| Parameter | Range | Trend |
|---|---|---|
| CLK Vdiff | 164.2–166.5 mV | Flat — no drift |
| DAT0 Vdiff | 186.0–223.2 mV | Flat (scatter from capture phase) |
| CLK jitter p-p | 148.5–174.6 ps | Flat — no progressive worsening |
| CLK jitter RMS | 53.1–57.4 ps | Flat |
| LP-11 voltage | 1.011–1.016 V | Flat — no droop over time |
| 1.8 V mean | 1.7635–1.7698 V | Flat |
| 1.8 V droop | 7.6–16.6 mV | No trend (random scatter) |
| LP-low plateau | 0–343 ns | Bimodal — see below |

The absence of any progressive trend confirms the bistable observation: the system doesn't degrade into failure, it rolls dice at SoT and sticks with the result.

### LP-Low Plateau: Bimodal Distribution (Key Finding)

| LP-low plateau | Count | Outcome |
|---|---|---|
| 342–348 ns | ~17 captures | All good (no flicker) |
| 93–108 ns | ~7 captures | All good (no flicker) |
| 0 ns (absent) | 3 captures | All FLICKER (0639, 0642, 0648) |
| Parse error | 2 captures (0649, 0662) | Unknown |

This is the smoking gun. The LP-low plateau clusters into three discrete populations:
- ~343 ns: The PHY executes a full LP-00 state (approximately 18.5 bc = one byte-clock aligned interval). SN65DSI83 locks successfully.
- ~108 ns: The PHY executes a shortened LP-00 state (~6 bc). Still long enough for SN65DSI83 to detect. No flicker.
- 0 ns: The LP-00 state is completely absent. The data line transitions directly from LP-11 to HS without a resolvable LP-01/LP-00 sequence. The SN65DSI83 cannot detect SoT. Flicker results.

The trimodal distribution (0 / ~108 / ~343 ns) with byte-clock-like quantisation strongly suggests the PHY's internal SoT state machine has a race condition related to the programmed THS_PREPARE+THS_ZERO values being below spec. The short THS_EXIT (92.6 ns < 100 ns) further compresses the timing window, and the short TCLK_PREPARE (37 ns < 38 ns) means the clock lane SoT also runs tight. When all these jitter contributions align unfavourably, the LP-00 state collapses to zero.

## 3. Anomalies

### A. Flicker Captures — Absent LP-00 State

| Capture | LP-low | LP exit→HS | Flicker |
|---|---|---|---|
| 0639 | 0 ns | 2 ns | YES |
| 0642 | 0 ns | 3 ns | YES |
| 0648 | 0 ns | 2 ns | YES |

All three flicker events share the identical signature: LP-low plateau = 0 ns. No other parameter (supply, amplitude, jitter) distinguishes them from good captures.

### B. DAT0 sig Captures: Intermittent 0.0 mV (No HS Detected)

Captures 0637, 0642, 0643, 0647, 0655, 0663 show `sig/dat Vdiff = 0.0 mV` — "No HS signal detected." This occurs in both good and bad sessions. Most likely cause: The sig capture's short acquisition window (high-res mode) triggered during an LP or blanking interval rather than during active HS data. This is a trigger timing artefact, not a signal fault — the proto/dat captures from the same sessions show healthy HS amplitude. No action needed on this artefact, but it means sig/dat data is unreliable for roughly 20% of captures.

### C. DAT0 proto: Intermittent "Only Negative Swings"

Captures 0635, 0642, 0653 show proto/dat with only negative differential excursions. This occurs when the proto window captures a run of identical data bits. It's a capture phase artefact, not a signal issue.

### D. LP Parse Errors

Captures 0649 and 0662: `index 200000 is out of bounds` — the LP capture buffer was exhausted before the SoT event completed. Most likely cause: the trigger fired too late in the LP-11 dwell, and the HS burst extended past the capture window. These sessions could not be classified for flicker from LP data alone.

### E. DAT0 Sub-140 mV Sample Counts: High Variance

The number of settled samples below 140 mV on DAT0 proto varies wildly: 36 to 8203. This is driven by how much of the capture window contains transition edges versus settled levels, and by the data pattern. The high counts (e.g., 0649: 8203; 0648: 5203; 0636: 5884) are not correlated with flicker — capture 0636 (5884 sub-140 mV samples) has LP-low = 108 ns and no flicker. These counts reflect HS eye opening, not SoT integrity.

## 4. Supply Correlation Analysis

### 1.8 V Supply vs. LP Anomalies

| Parameter | Flicker captures (0639/0642/0648) | Good captures (all others) |
|---|---|---|
| 1.8 V mean | 1.7649–1.7654 V | 1.7635–1.7698 V |
| 1.8 V min | 1.7560 V | 1.7480–1.7600 V |
| Droop depth | 8.9–9.4 mV | 7.6–16.6 mV |
| Ripple RMS | 5.55–5.77 mV | 5.24–5.91 mV |

No correlation. The flicker captures have average or better supply metrics. The worst droop (16.6 mV, capture 0637) and lowest min voltage (1.7480 V, capture 0637) occurred in a good session. The 1.8 V supply is not the cause of the intermittent SoT failure.

### LP-11 Voltage vs. Supply

LP-11 voltage (1.011–1.016 V) shows no correlation with supply droop. The LP driver output is limited by the PHY's internal regulation, not the supply rail headroom (which has >50 mV margin to the 1.71 V lower limit).

## 5. Warning/Error Explanations

| Warning/Error | Cause | Action |
|---|---|---|
| `LP exit duration X ns below spec min 50 ns` | Root cause issue. PHY SoT state machine transitions too fast due to short THS_PREPARE+THS_ZERO and THS_EXIT register values. | Fix registers — switch to 'Round Up' mode |
| `FLICKER SUSPECT: LP-low plateau absent or < 50 ns` | LP-00 state completely missing — PHY skipped the SoT low-going sequence. Direct consequence of timing violations. | Same register fix |
| `Only negative swings in capture window` | Proto/sig trigger captured a run of identical data bits (e.g., all-zero payload). Amplitude estimate is valid for the measured polarity. | Benign artefact — no action needed |
| `No HS signal detected — line may be in LP state or idle` | Sig capture (short window) triggered during blanking or LP interval. | Benign artefact — increase sig trigger holdoff or ignore |
| `CLK lane is in continuous HS mode — LP states not expected on CLK` | Normal for video-mode DSI. CLK runs HS continuously. | Expected — no action |
| `X settled samples below 140 mV` (CLK) | CLK amplitude (165 mV) is close to floor; ISI and jitter push some transitions below 140 mV during ringing/settling. | Monitor but no immediate action — amplitude is 18% above floor |
| `index 200000 is out of bounds` | LP capture buffer too short to contain the full SoT→HS transition at this trigger position. | Increase capture depth or adjust trigger delay |

## 6. Actionable Recommendations

### CRITICAL — Fix #1: Switch to 'Round Up' PHY Timing (Eliminates Root Cause)

Modify the samsung-dsim driver (or device tree) to program the 'Round Up' compliant register values:

```
DSIM_PHYTIMING (0xb4): 0x00000306 ← THS_EXIT = 6 (was 5)
DSIM_PHYTIMING1 (0xb8): 0x030f0a04 ← TCLK_PREPARE = 3 (was 2), TCLK_ZERO = 15 (was 14), TCLK_TRAIL = 4 (was 3)
DSIM_PHYTIMING2 (0xbc): 0x00030706 ← THS_ZERO = 7 (was 6), THS_TRAIL = 6 (was 5)
```

This eliminates all 5 D-PHY violations and adds margin:
- THS_EXIT: 92.6 → 111.1 ns (11% margin over 100 ns spec)
- TCLK_PREPARE: 37.0 → 55.6 ns (46% margin over 38 ns spec)
- TCLK_PREPARE+TCLK_ZERO: 296.3 → 333.3 ns (11% margin over 300 ns spec)
- THS_PREPARE+THS_ZERO: 166.7 → 185.2 ns (10% margin over 168.2 ns spec)
- TCLK_TRAIL: 55.6 → 74.1 ns (23% margin over 60 ns spec)

The added THS_ZERO and TCLK_ZERO margin directly extends the LP-00 state duration, making the 0 ns plateau condition physically impossible.

Implementation: In the `samsung-dsim` / `sec-dsim` driver, the timing calculation function uses `DIV_ROUND_UP` vs. truncation for these fields. Ensure the driver's `dsim_calc_phy_timing()` or equivalent uses ceiling division. Alternatively, override via device tree `phy-timing` properties or a kernel patch to force the compliant values.

### IMPORTANT — Fix #2: Investigate LP-11 Voltage

LP-11 at 1.015 V is within spec but is only 15 mV above the 1.0 V floor. At this level, the SN65DSI83's LP receiver has minimal noise margin. Potential improvements:

• Verify VDDIO decoupling near the i.MX 8M Mini PHY VDDIO pins — add 100 nF ceramic if missing within 2 mm
• Check series resistance in the LP path — any added series termination on Dp/Dn will drop LP-11 voltage
• Verify the PHY's LP driver bias — some Samsung DSIM implementations have a configurable LP output swing via an undocumented register or OTP setting

### MONITORING — HS CLK Amplitude

CLK at 165 mV with sub-140 mV excursions is functional but leaves only 25 mV (18%) of margin. If trace length increases (board revision, flex cable, etc.), this will fail. Consider:

• Reviewing CLK lane termination (should be 100Ω differential at SN65DSI83 input)
• Checking for stubs or vias in the CLK differential pair
• Verifying the PHY's HS driver impedance calibration (if configurable)

### MINOR — Capture Infrastructure

• Increase LP capture buffer from 200k samples to ≥400k to avoid the index-out-of-bounds errors in captures 0649 and 0662
• Adjust sig capture trigger holdoff to consistently land in active HS data, not blanking

## 7. Summary

The flicker root cause is definitively identified: the samsung-dsim PHY timing registers are programmed with 'Round Best' (truncated) values that violate D-PHY v1

Tokens: 45244 in / 4096 out