MIPI DSI Flicker — Root Cause Investigation

1. Method

The flicker_burst.py tool was run alongside video_cycler.py. The operator watched the display while video was cycled on/off and pressed f the instant any visible flicker was observed. Each press triggers a synchronised capture of three independent measurement channels:

1.1 Measurement-setup rationale — single-ended CLK+/DAT0+ vs. differential CLK+/− and DAT0+/−

All four MIPI lines (CLK+, CLK−, DAT0+, DAT0−) were physically routed to the Keysight scope (50 Ω coax, 910 Ω terminated). The decision to acquire on CLK+ and DAT0+ only — i.e. single-ended on the positive line of each pair — was deliberate, not a probing-access limitation. The reasoning:

• LP states are defined single-endedly in D-PHY. LP-11, LP-01, LP-00 are independent single-ended levels on each lane line, not a differential pair. A differential CLK+ − CLK− view would collapse LP-11 and LP-00 to ~0 V and erase the ~1 V absolute level needed to verify the SoT preamble. For any test that touches LP→HS transitions, single-ended is mandatory.
• HS is an anti-phase pair on a symmetric bias — CLK− carries no new amplitude/period/envelope information. In HS, CLK− is the polarity-inverted complement of CLK+ around the common bias. Per-cycle amplitude, period, and burst envelope are fully observable on CLK+ alone, which is what the hypothesis under test required.
• The three signatures CLK−/DAT0− would add are already covered by the SN65 error registers. Common-mode noise on the pair, intra-pair skew, and CLK+/CLK− amplitude asymmetry would, if severe enough to matter, exceed the SN65DSI83's differential-receiver input window and trip SOT_BIT_ERR, LP_ERR, ECC or CRC flags — all of which were polled across the full test and remained zero. The receiver itself acts as an in-circuit differential integrity monitor; the scope didn't need to duplicate it.
• The trigger is single-ended regardless. LP-edge triggering keys off the LP-11 → LP-01 falling edge (~700 mV crossing) on a single line, so trigger-arming uses one single-ended input independent of how many channels are acquired.
• Acquisition-resource trade. At 100 segments × 20 µs × 5 GSa/s, holding 2 channels rather than 4 freed segmented-memory budget on the Infiniium for (i) longer per-segment windows that span the entire LP-11 → HS → LP-11 envelope, and (ii) the full 100-segment count needed to catch rare events at the ~48 kHz line rate.

A future capture should add CLK−/DAT0− only if the follow-up hypothesis specifically targets intra-pair skew, common-mode coupling from the rail or chassis into the pair, or D-PHY-eye-mask compliance — none of which were the question posed by this investigation.

2. Per-burst SN65 register summary

Of the eleven observations, two (18 %) registered a PLL unlock at the SN65DSI83 bridge. The unlock pulse widths were 20.3 ms and 35.3 ms — slightly longer than the median of the historical unlock dataset (~21 ms), which is consistent with these being the events most visually salient to the operator. No SOT, LLP, ECC, LP, or CRC errors were registered at the SN65 in any burst.

3. Bursts with detected PLL unlocks

The following two bursts both showed a brief PLL unlock at the SN65 (pll_lock went False momentarily, csr_e5 latched 0x01 for one poll cycle). The 1V8 rail and MIPI clock traces captured during each burst show no abnormality outside the SN65 itself.

3.5 Burst 5 — press 14:25:13.600, unlock 14:25:22.382 (20.3 ms)

MIPI overview (20 µs window):

Close-up: LP-11 → HS transition (SoT preamble) — shows the falling edge of CLK+ from LP-11 ~1 V down to the HS mid-level ~100 mV (single-ended CLK+ DC offset; CLK− not captured) and the start of HS oscillation:

Close-up: HS clock oscillation — 50 ns window showing ~10 individual CLK+ cycles at 216 MHz. Clean square-wave-like alternation with consistent amplitude:

The rail remained centred on 1764.0 mV with 124 mV Vpp (within the same range as no-unlock bursts). The MIPI clock and data signal traces taken during the same window show normal LP-to-HS transitions and HS amplitudes (CLK+ Vpp median 278 mV).

3.11 Burst 11 — press 14:42:54.549, unlock 14:42:59.304 (35.3 ms)

MIPI overview (20 µs window):

Close-up: LP-11 → HS transition (SoT preamble) — shows the falling edge of CLK+ from LP-11 ~1 V down to the HS mid-level ~100 mV (single-ended CLK+ DC offset; CLK− not captured) and the start of HS oscillation:

Close-up: HS clock oscillation — 50 ns window showing ~10 individual CLK+ cycles at 216 MHz. Clean square-wave-like alternation with consistent amplitude:

The rail remained centred on 1765.1 mV with 128 mV Vpp (within the same range as no-unlock bursts). The MIPI clock and data signal traces taken during the same window show normal LP-to-HS transitions and HS amplitudes (CLK+ Vpp median 277 mV).

4. Bursts with no detectable SN65 state change

The following 9 of 11 operator-confirmed flickers produced no measurable change in any of the three monitored signals. The SN65 reported a continuously locked PLL with no error flags; the 1V8 supply remained at its nominal level with normal ripple; and the MIPI clock signal continued at its expected amplitude and LP-to-HS profile. A representative trace pair from each measurement is shown below.

4.1 1V8 supply rail — representative trace

Across all 9 no-state-change bursts, the rail mean was 1.764–1.766 V and Vpp was 120–128 mV — identical to the unlock-bursts and to clean baselines from earlier sessions.

4.2 MIPI clock and data signals — representative overlay

Wide overview (20 µs window per segment):

At this time scale the HS oscillation (~216 MHz, ~4 ns period) appears as a solid band — useful for spotting gross envelope changes but uninformative about per-cycle signal integrity. Two close-ups follow.

4.3 Close-up: LP-11 → HS transition (SoT preamble)

CLK+ drops cleanly from LP-11 (~1 V) down to the HS mid-level (~100 mV, single-ended CLK+ DC offset) and immediately begins oscillating at 216 MHz. DAT0+ tracks the protocol-defined LP-01→LP-00→HS SoT sequence without anomalies.

4.4 Close-up: individual HS clock cycles

Zooming further in resolves the individual CLK+ cycles (period ~4.6 ns, ~10 cycles per 50 ns window). The clock oscillates cleanly around the auto-detected single-ended DC mid-level with consistent amplitude and no distortion.

4.5 Folded eye diagram (CLK+, 20 segments × ~80 cycles)

Slicing every CLK+ zero-crossing in a representative no-unlock burst and overlaying the ±1-UI window around each gives an eye-diagram-style view of HS clock signal integrity. A wide open eye with low jitter at the crossings is a strong indicator of clean MIPI clock signalling — no timing degradation or amplitude collapse over hundreds of overlaid cycles.

Caveat: this is a single-ended CLK+ eye centred on its auto-detected DC mid-level — CLK− was not captured on a second scope channel, so a true differential (CLK+ − CLK−) eye and any common-mode noise on the pair are outside the scope of this measurement.

Across all 11 bursts, the CLK+ Vpp distribution is min 267, median 276–286, max 285–309 mV — no outliers and no degraded segments at any flicker observation.

5. Conclusion (current working hypothesis)

5.1 Hypotheses assessed by this test

Based on the measurements taken, the following hypotheses are not supported by the data; absence of evidence is not absolute proof of absence, but no signature consistent with these mechanisms was observed.

6. Follow-up: higher-rate polling confirms the root cause

A follow-up session re-ran the SN65 register monitor at a higher poll rate (50–100 Hz, median ~20 ms between samples, vs the ~50 ms interval used in this test). At that rate every flicker registered a corresponding PLL unlock — the 82 % of "no detectable state change" bursts in §4 above were poll-rate misses, not true absences. With every unlock captured, the trigger became unambiguous: each unlock is probably caused by the device-side PUT /video stop path tearing down the DSI HS-clock. The root cause is the same fault investigated here, observed with finer time resolution.

6.1 Continuous video (hold) — baseline

6.2 Video on/off cycling

6.3 Unlock pulse-width distribution

6.4 Mechanism

                  PUT /video stop arrives
                      │
                      │ ~5 ms     HTTP / Flask processing
                      │ ~50-150ms App + GStreamer pipeline tears down
                      │           (state goes to NULL)
                      ▼
              DSIM driver disables HS_CLK_EN  ──────►  ~230 ms after stop
                      │
                      ▼
              MIPI CLK lane goes to LP-11
                      │
                      ▼
              SN65DSI83 sees no reference clock
                      │
                      ▼
              PLL drops lock          ◄── csr_e5.pll_unlock = 1 caught here
                                            (pulse width 15-45 ms)
                      │
                      ▼
              PLL re-acquires to "no-signal" idle state
                      │
                  (~500 ms OFF window)
                      │
                  PUT /video start
                      ▼
              DSIM re-enables HS_CLK_EN; MIPI traffic resumes
                      │
                      ▼
              SN65DSI83 PLL has to re-acquire to the new clock
                      │      (~10-30 ms, LVDS output is garbage during this)
                      ▼
              ──── visible flicker on the panel ────

The bridge is behaving correctly: a PLL is expected to lose lock when its reference clock disappears. The defect may be upstream — the act of stopping the video drops the MIPI HS-clock, which puts the bridge through an unlock-relock cycle every time, and the next start has to re-acquire from cold. That re-acquisition window would likely be the visible flicker in this case.

7. Possible remedies and areas for further investigation

Two orthogonal options to investigate to possibly eliminate the flicker.

7.1 Don't tear the pipeline down

In the device-side video stack, change the "stop" path from a full teardown to a soft pause that keeps the DSI HS-clock running. For GStreamer:

// Today  (causes flicker):
gst_element_set_state(pipeline, GST_STATE_NULL);

// Proposed:
gst_element_set_state(pipeline, GST_STATE_PAUSED);

PAUSED retains the pipeline graph and buffers — and, importantly, doesn't trigger the bridge-disable path in the i.MX DSIM driver, so HS-CLK stays on and the SN65 PLL stays locked through the transition. Resume is near-instant and visually clean.

7.2 Don't stop video in production

If the only reason /video stop is called in real deployments is the flicker test harness itself, the flicker mode is purely an artefact of the test. Production code that starts the stream once at boot and leaves it running will see zero PLL unlocks (confirmed empirically — 0 unlocks in 10 min 51 s of continuous video).

7.3 Verify the fix

Once the device server gains a soft-stop action (e.g. {"action": "pause"}), compare_stops.py runs an A/B test automatically:

STYLES = [
    ("stop_full",  {"action": "start", "mode": "static-pink"}, {"action": "stop"}),
    ("stop_pause", {"action": "start", "mode": "static-pink"}, {"action": "pause"}),
]
$ python3 compare_stops.py --cycles 30

A successful fix will show ~0.5 unlocks/cycle for stop_full and 0.00 for stop_pause.

8. Hardware engineering perspective

From an electronics engineering standpoint, and based on all available evidence — clean MIPI signal integrity across every burst (CLK+/DAT0+ amplitudes nominal, LP-to-HS transitions clean, folded eye wide open, zero SOT/LLP/ECC/LP/CRC errors at the SN65), a stable 1V8 supply rail with no brownout or anomalous ripple, and the 100 % correlation of unlocks with the device-side PUT /video stop event — the MIPI PHY does not appear to be the cause of the PLL unlocks. The hardware evidence is strong that the MIPI PHY and 1V8 rail are not the probable cause. Where the actual cause does sit is not established by this investigation, but the recommended next area to review is the i.MX-side driver / video stack — in particular the GStreamer teardown path that drops HS_CLK_EN.