MIPI D-PHY Analysis Report

Generated: 2026-04-10 12:46:56  |  Scope: Captures 0305–0334  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0305–0334

## 1. Root Cause Identification

### The Primary Problem: Register Mismatch — Driver Not Applying Target Timing

This is the single most important finding. Every capture shows the same register values:

| Register | Actual (all captures) | Target (spec-compliant) | Delta |
|---|---|---|---|
| PHYTIMING (0xb4) | `0x00000305` | `0x00000306` | THS_EXIT: 5→93 ns vs 6→111 ns |
| PHYTIMING1 (0xb8) | `0x020e0a03` | `0x03110A04` | TCLK_PREPARE: 2→37 ns vs 3→56 ns; TCLK_ZERO: 14→259 ns vs 17→315 ns; TCLK_TRAIL: 3→56 ns vs 4→74 ns |
| PHYTIMING2 (0xbc) | `0x00030605` | `0x00040A03` | THS_PREPARE: 5→93 ns vs 3→56 ns; THS_ZERO: 6→111 ns vs 10→185 ns; THS_TRAIL: 3→56 ns vs 4→74 ns |

Critical field-level decode of actual register 0xbc = `0x00030605`:

| Field | Actual | Duration | D-PHY v1.1 Spec | Status |
|---|---|---|---|---|
| THS_PREPARE | 5 | 92.6 ns | 40+4×UI=49.3 ns … 85+6×UI=98.9 ns | ✓ but at upper edge |
| THS_ZERO | 6 | 111.1 ns | THS_ZERO + THS_PREPARE ≥ 145+10×UI = 168.2 ns → need THS_ZERO ≥ ~4.1 → 5 min | Marginal ✓ (combined = 203.7 ns ≥ 168.2 ns) |
| THS_TRAIL | 3 | 55.6 ns | max(n×8×UI, 60+n×4×UI) = 60+4×2.315 = 69.3 ns | ✗ VIOLATION |

Critical field-level decode of actual register 0xb8 = `0x020e0a03`:

| Field | Actual | Duration | Spec | Status |
|---|---|---|---|---|
| TCLK_PREPARE | 2 | 37.0 ns | 38 ns … 95 ns | ✗ VIOLATION (37 < 38 ns) |
| TCLK_ZERO | 14 (0x0e) | 259.3 ns | TCLK_PREPARE + TCLK_ZERO ≥ 300 ns | ✗ VIOLATION (296.3 < 300 ns) |
| TCLK_POST | 10 (0x0a) | 185.2 ns | 60 + 52×UI = 180.4 ns | ✓ barely |
| TCLK_TRAIL | 3 | 55.6 ns | 60 ns | ✗ VIOLATION (55.6 < 60 ns) |

### Summary of Timing Violations in Running Registers

| Parameter | Required | Actual | Margin | Verdict |
|---|---|---|---|---|
| TCLK_PREPARE | ≥ 38 ns | 37.0 ns | −1 ns | FAIL |
| TCLK_PREPARE + TCLK_ZERO | ≥ 300 ns | 296.3 ns | −3.7 ns | FAIL |
| TCLK_TRAIL | ≥ 60 ns | 55.6 ns | −4.4 ns | FAIL |
| THS_TRAIL | ≥ 69.3 ns | 55.6 ns | −13.7 ns | FAIL |
| THS_EXIT | ≥ 100 ns | 92.6 ns | −7.4 ns | FAIL |
| TLPX | ≥ 50 ns | 55.6 ns | +5.6 ns | ✓ marginal |

Five timing parameters are out of spec. The samsung-dsim driver is computing or applying incorrect values. The target values (which you've verified as compliant) are not reaching the hardware.

## 2. LP SoT Sequence Analysis — The Flicker Mechanism

### LP-Low Plateau Distribution (all captures with valid LP data)

| LP-low plateau | Captures | Flicker? |
|---|---|---|
| ~342–343 ns | 0305, 0306, 0310, 0312, 0316, 0317, 0319, 0321, 0322, 0323, 0324, 0329, 0332, 0333, 0334 | All NO |
| ~108 ns | 0308 (69 ns), 0311, 0315, 0326, 0327, 0328 | All NO |
| 0–1.4 ns | 0313 (1 ns), 0320 (0 ns), 0325 (0 ns) | ALL YES |

The correlation is absolute: Flicker occurs if and only if the LP-low plateau is effectively absent (< ~2 ns). The SN65DSI83 requires a well-formed LP-11 → LP-01 → LP-00 → HS-0 SoT entry sequence on the data lanes. When the LP-low states are compressed to zero, the bridge cannot detect the SoT, fails to lock to the HS data stream, and remains stuck for the entire session.

### Why LP-Low Disappears Intermittently

The LP exit → HS measurement is universally 0–4 ns across all captures (good and bad), meaning the LP-01 transition state is always extremely brief. This is consistent with the TLPX register value of 3 byte-clocks (55.6 ns) — marginally above the 50 ns spec minimum — combined with the fact that TCLK_PREPARE, THS_PREPARE, and THS_EXIT are all either at or below spec limits.

The key observation is that the LP-low plateau shows a trimodal distribution: ~343 ns, ~108 ns, or ~0 ns. This suggests:

1. The PHY state machine has a race condition at the LP→HS transition
2. The combination of marginal/violated timing parameters creates a window where the PHY occasionally skips the LP-00 hold state entirely
3. The ~343 ns cases likely represent a full nominal hold; ~108 ns represents one byte-clock step shorter (≈6 byte-clocks vs ~18.5 byte-clocks); 0 ns represents complete state skip

The THS_TRAIL violation (55.6 ns vs required 69.3 ns) and THS_EXIT violation (92.6 ns vs required 100 ns) are particularly relevant: if the PHY's internal LP state machine uses these timers to sequence the LP-01→LP-00→HS-0 entry, short timers increase the probability that on any given startup, the state machine races through or skips the low states.

## 3. HS Signal Health

### Consistent Concerns

| Parameter | Typical Value | Spec | Assessment |
|---|---|---|---|
| CLK Vdiff | 166.2–167.2 mV | 140–270 mV | ✓ but only 19% above floor — very low margin |
| DAT Vdiff | 186–197 mV | 140–270 mV | ✓ acceptable |
| CLK common mode | +28–32 mV | ±25 mV recommended | Slightly high, minor |
| CLK asymmetry | +196/−136 mV | Should be symmetric | 60 mV offset — significant |
| DAT below-140mV samples | 29–16234 per capture | 0 | Persistent spec violation |
| CLK below-140mV samples | 40–274 per capture | 0 | Persistent spec violation |

The clock amplitude of ~167 mV is only 27 mV above the 140 mV absolute minimum. The persistent sub-140 mV excursions are transition-region violations (ISI/ringing during edge transitions), not a settled-level problem, but they represent genuine eye-closure events.

Clock asymmetry (+196/−136 mV, ~60 mV offset) indicates either a DC offset in the PHY output driver or an impedance mismatch on the CLK+ vs CLK− traces. This doesn't directly cause flicker but reduces noise margin.

### No Significant Trends Over Time

| Parameter | Capture 0305 | Capture 0334 | Trend |
|---|---|---|---|
| CLK Vdiff | 166.5 mV | 166.2 mV | Flat |
| DAT Vdiff | 187.2 mV | 186.4 mV | Flat |
| CLK jitter RMS | 54.6 ps | 53.8 ps | Flat |
| LP-11 voltage | 1.015 V | 1.014 V | Flat |
| 1.8V mean | 1.7663 V | 1.7670 V | Flat |

No thermal drift, aging, or progressive degradation detected across this batch.

## 4. Supply Rail Correlation

### 1.8V Supply Statistics

| Metric | Range | Spec |
|---|---|---|
| Mean | 1.7655–1.7724 V | 1.71–1.89 V ✓ but 34–45 mV below nominal |
| Min | 1.6960–1.7440 V | ≥ 1.71 V |
| Droop | 24.5–69.7 mV | — |

Two captures breach the 1.71 V floor: 0305 (1.700 V, 66 mV droop) and 0314 (1.696 V, 70 mV droop).

### Supply vs Flicker Correlation

| Capture | Flicker? | LP-low | Droop (mV) | Min V |
|---|---|---|---|---|
| 0313 | YES | 1 ns | 35.4 | 1.732 V |
| 0320 | YES | 0 ns | 55.3 | 1.712 V |
| 0325 | YES | 0 ns | 38.2 | 1.728 V |
| 0305 | no | 343 ns | 66.3 | 1.700 V |
| 0314 | no (no LP data) | — | 69.7 | 1.696 V |
| 0329 | no | 343 ns | 50.0 | 1.716 V |

No correlation between supply droop and flicker. Capture 0313 (flicker) has only 35 mV droop, while 0305 and 0314 (no flicker) have the worst droops at 66–70 mV. The flicker mechanism is not supply-droop-driven. However, the supply violations are a separate concern that should be addressed.

## 5. Warning/Error Explanations

| Warning/Error | Frequency | Most Likely Cause | Action |
|---|---|---|---|
| `LP exit duration X ns below spec min 50 ns` | 100% of LP captures | Register TLPX=3 (55.6 ns) is marginal; actual LP-01 state is being measured at single-ended level with limited bandwidth — the 0–4 ns measurement likely reflects the fast single-ended slew between LP-11 and LP-00, not a true timing violation at the protocol level. But the LP-01→LP-00 transition is clearly being squeezed. | Increase TLPX to 4 (74 ns) in target registers |
| `LP-low plateau absent or < 50 ns` (FLICKER) | 3/30 (10%) | PHY state machine race — LP-00 hold state skipped due to marginal/violated timing register values | Apply correct registers (see §6) |
| `Only negative swings in capture window` | ~60% of sig/dat | Oscilloscope trigger or probe captured during a run of consecutive '0' bits (or blanking with HS-0 idle) | Non-actionable — adjust trigger or increase capture window for sig captures |
| `index 200000 out of bounds` | 5 captures | LP data array too short — likely the SoT transition occurred outside the trigger window or the capture didn't include the LP→HS edge | Adjust trigger delay or increase pre-trigger buffer |
| `CLK lane continuous HS mode — LP states not expected` | 100% | Expected — DSI clock lane runs in continuous HS mode (non-burst) at this configuration | Non-actionable, correct behavior |
| `Supply droops below 1.71 V` | 2/30 (7%) | Insufficient bulk + HF decoupling on VDDIO near PHY, combined with LP→HS transient current draw (~tens of mA step) | Add 10 µF + 100 nF ceramic caps close to MIPI PHY VDDIO pins |
| `No HS signal detected` (sig/dat) | 2 captures (0325, 0328, 0332) | Scope captured during blanking interval or LP state on data lane — no HS activity in window | Non-actionable artifact |
| `Settled samples below 140 mV` | 100% of proto captures | ISI-induced eye closure during transitions and during low-amplitude data patterns; clock amplitude is marginal at 167 mV | Monitor; consider trace impedance tuning if layout revision is possible |

## 6. Actionable Recommendations

### CRITICAL — Fix #1: Force Correct PHY Timing Registers

The samsung-dsim driver is not applying your target values. The actual registers show shorter timings that violate D-PHY spec in 5 parameters. This is the root cause of the intermittent flicker.

Option A — Device Tree override (preferred, no driver patch):
In the DSIM node of the device tree, check if `samsung,phy-timing` properties exist. The `sec-dsim` / `samsung-dsim` driver in some BSP versions computes timings from the bit rate using internal formulas that may undercount at 432 Mbit/s. If the DT accepts explicit timing overrides:

```dts
&mipi_dsi {
samsung,phy-timing = <0x00000306 0x03110A04 0x00040A03>;
/* Or individual fields if supported by your BSP version */
};
```

Option B — Direct register poke (validation only):
```bash
# After pipeline load but before enable:
memtool mw -l 0x32e100b4=0x00000306
memtool mw -l 0x32e100b8=0x03110A04
memtool mw -l 0x32e100bc=0x00040A03
```

Option C — Driver patch:
In `drivers/gpu/drm/bridge/samsung-dsim.c` (or `sec-dsim.c` depending on BSP), find the `samsung_dsim_set_phy_timing()` function and either:
- Override the computed values with hardcoded values for your bit rate, or
- Fix the computation formula (the standard formula uses `ceil((ns_value / byte_clk_period) - 1)` which at 432 Mbit/s rounds down for several parameters)

Expected effect: Increasing THS_ZERO from 6→10, THS_TRAIL from 3→4, TCLK_PREPARE from 2→3, TCLK_ZERO from 14→17, and TCLK_TRAIL from 3→4 will bring all parameters into spec. More importantly, the longer THS_ZERO/THS_PREPARE timing combination gives the PHY state machine more time to properly sequence LP

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