MIPI Interactive Flicker Test Report

Generated: 2026-04-20 07:46:57 | Model: claude-opus-4-6

Stop reason: Test interrupted by operator (Ctrl+C)

0 confirmed flicker(s)

2 false alarm(s)

0 Claude said no

D-PHY Configuration

Pixel clock: 72.0 MHz | Bit rate: 432.0 Mbit/s per lane | Byte clock: 54.000 MHz (18.519 ns/byte) | UI: 2.315 ns

Field	Spec (ns)	Rnd Best	Rnd Up	Extra	Final	Actual (ns)	Status
`lpx`	≥ 50.0	3	3	+0	3	55.56	✓
`hs_prepare`	49.3 – 98.9	3	3	+1	4	74.07	✓
`hs_zero`	≥ 94.1	5	6	+0	6	111.11	✓
`hs_trail`	≥ 69.3	4	4	+1	5	92.59	✓
`hs_exit`	≥ 100.0	5	6	+0	6	111.11	✓
`clk_prepare`	38.0 – 95.0	2	3	+0	3	55.56	✓
`clk_zero`	≥ 244.4	13	14	+3	17	314.81	✓
`clk_post`	≥ 180.4	10	10	+0	10	185.19	✓
`clk_trail`	≥ 60.0	3	4	+0	4	74.07	✓

✓ All D-PHY v1.1 Table 14 constraints satisfied.

Samsung DSIM Registers

Register	Address	Value	Field breakdown
PHY_TIMING	`0xb4`	`0x00000306`	lpx=3 hs_exit=6
PHY_TIMING1	`0xb8`	`0x03110a04`	clk_prepare=3 clk_zero=17 clk_post=10 clk_trail=4
PHY_TIMING2	`0xbc`	`0x00040605`	hs_prepare=4 hs_zero=6 hs_trail=5

u-boot Commands

# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
# PHY_TIMING1 (0xb8) = 0x03110a04   clk_prepare=3  clk_zero=17  clk_post=10  clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00040605   hs_prepare=4  hs_zero=6  hs_trail=5

# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"

# Extra PHY cycles above Round-Up minimum
setenv flb_dtovar "${flb_dtovar} dsi-phy-extra-hs-prepare=1"
setenv flb_dtovar "${flb_dtovar} dsi-phy-extra-hs-trail=1"
setenv flb_dtovar "${flb_dtovar} dsi-phy-extra-clk-zero=3"

saveenv
boot

Event Log

Capture	Timestamp	Channel	LP-low plateau	LP exit→HS	LP-11 voltage	Claude: flicker?	Outcome
0002	20260420_074452	dat	107.8 ns	3.1 ns	1.017 V	YES	✓ FALSE ALARM
0004	20260420_074554	dat	107.4 ns	1.2 ns	1.016 V	YES	✓ FALSE ALARM

Claude Assessments

Capture 0002 [20260420_074452] — FALSE ALARM

YES

The LP-low plateau at ~108 ns exceeds the 50 ns minimum, but the critical failure here is the **LP exit → HS transition of only 3 ns**, far below the 50 ns specification minimum. This means the LP-01 and LP-00 states that constitute the SoT preamble are essentially absent or too brief for the SN65DSI83 to reliably detect. Additionally, the **HS amplitude of 30 mV** is well below the normal 105–122 mV range and falls under the 50 mV "absent" threshold, indicating the bridge likely never locked onto the HS data. Together, the collapsed LP-exit timing and effectively absent HS signaling strongly indicate a missed SoT event that would produce visible flicker.

Capture 0004 [20260420_074554] — FALSE ALARM

YES

The HS amplitude of only 32 mV (well below the 50 mV "absent" threshold and far from the normal 105–122 mV range) indicates the HS data burst was essentially not received by the SN65DSI83, even though the LP-low plateau at 107 ns nominally meets the ≥50 ns requirement. Critically, the LP exit → HS transition time of only 1 ns (spec ≥50 ns) means the LP-01/LP-00 states were not properly held long enough for the bridge to recognize the SoT preamble — the pre-processor itself flagged this as below spec. The combination of a collapsed LP-exit duration and an effectively absent HS swing strongly indicates the bridge missed start-of-transmission on this frame, which would produce visible flicker.