MIPI Interactive Flicker Test Report

Generated: 2026-04-17 08:04:39 | Model: claude-opus-4-6

Stop reason: Test interrupted by operator (Ctrl+C)

0 confirmed flicker(s)

0 false alarm(s)

0 Claude said no

D-PHY Configuration

Pixel clock: 72.0 MHz | Bit rate: 432.0 Mbit/s per lane | Byte clock: 54.000 MHz (18.519 ns/byte) | UI: 2.315 ns

Field	Spec (ns)	Rnd Best	Rnd Up	Extra	Final	Actual (ns)	Status
`lpx`	≥ 50.0	3	3	+0	3	55.56	✓
`hs_prepare`	49.3 – 98.9	3	3	+0	3	55.56	✓
`hs_zero`	≥ 112.6	6	7	+0	7	129.63	✓
`hs_trail`	≥ 69.3	4	4	+0	4	74.07	✓
`hs_exit`	≥ 100.0	5	6	+0	6	111.11	✓
`clk_prepare`	38.0 – 95.0	2	3	+0	3	55.56	✓
`clk_zero`	≥ 244.4	13	14	+0	14	259.26	✓
`clk_post`	≥ 180.4	10	10	+0	10	185.19	✓
`clk_trail`	≥ 60.0	3	4	+0	4	74.07	✓

✓ All D-PHY v1.1 Table 14 constraints satisfied.

Samsung DSIM Registers

Register	Address	Value	Field breakdown
PHY_TIMING	`0xb4`	`0x00000306`	lpx=3 hs_exit=6
PHY_TIMING1	`0xb8`	`0x030e0a04`	clk_prepare=3 clk_zero=14 clk_post=10 clk_trail=4
PHY_TIMING2	`0xbc`	`0x00030704`	hs_prepare=3 hs_zero=7 hs_trail=4

u-boot Commands

# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4

# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"

saveenv
boot

Event Log

No flicker suspects were detected during this test run.