MIPI Interactive Flicker Test Report

Generated: 2026-04-16 11:27:08  |  Model: claude-opus-4-6

D-PHY Configuration

Pixel clock: 72.0 MHz  |  Bit rate: 432.0 Mbit/s per lane  |  Byte clock: 54.000 MHz (18.519 ns/byte)  |  UI: 2.315 ns

✓ All D-PHY v1.1 Table 14 constraints satisfied.

Samsung DSIM Registers

u-boot Commands

# D-PHY PHY timing registers (pixel clock 72.0 MHz, 432.0 Mbit/s, byte clock 54.000 MHz)
#
# PHY_TIMING  (0xb4) = 0x00000306   lpx=3  hs_exit=6
# PHY_TIMING1 (0xb8) = 0x030e0a04   clk_prepare=3  clk_zero=14  clk_post=10  clk_trail=4
# PHY_TIMING2 (0xbc) = 0x00030704   hs_prepare=3  hs_zero=7  hs_trail=4

# Enable Round-Up rounding (dsi-tweak bit 2)
setenv flb_dtovar "${flb_dtovar} dsi-tweak=4"

saveenv
boot

Event Log

Claude Assessments

Capture 0001 [20260416_112353] — FALSE ALARM

YES

Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only 3 ns**, far below the 50 ns spec minimum, meaning the LP-01/LP-00 preamble states were essentially skipped or too brief for the SN65DSI83 to reliably sample the SoT sequence. Additionally, the **HS amplitude of only 20 mV** is drastically below the normal 105–122 mV range and falls under the 50 mV "absent" threshold, indicating the bridge almost certainly did not detect a valid HS data burst even if it had latched SoT. Together, the absent LP-to-HS preamble and effectively missing HS signaling mean the bridge would fail to decode this frame, producing a visible flicker event.

Capture 0002 [20260416_112431] — FALSE ALARM

YES

The LP-low plateau at 343 ns is well above the 50 ns SN65DSI83 detection threshold, so the SoT preamble timing itself is not the problem here. However, the HS amplitude of only 24 mV (single-ended) is far below both the normal operating range (105–122 mV) and the 50 mV minimum detection threshold, meaning the bridge almost certainly cannot resolve valid differential HS data from this burst. Additionally, the LP exit-to-HS transition of only 4 ns (spec ≥ 50 ns) indicates the LP-01/LP-00 states were too brief for reliable SoT detection by the bridge. The combination of an effectively absent HS burst and a non-compliant LP exit duration makes this a genuine flicker event — the SN65DSI83 likely failed to lock onto the HS data, resulting in a dropped or corrupted video line/frame.

Capture 0004 [20260416_112531] — FALSE ALARM

YES

Although the LP-low plateau itself is 343 ns (well above the 50 ns minimum), the critical failure here is the HS amplitude of only 17 mV, far below the 50 mV minimum detection threshold and the normal 105–122 mV range — effectively meaning the SN65DSI83 sees no valid HS data burst at all. Additionally, the LP-exit-to-HS transition time of only 4 ns (spec ≥ 50 ns) indicates the LP-01/LP-00 states were too brief for the bridge to properly recognize the SoT preamble. Together, these two failures — an undetectable HS burst and a sub-spec LP exit duration — mean the bridge almost certainly missed this transmission, constituting a genuine flicker event.

Capture 0006 [20260416_112630] — FALSE ALARM

YES

Although the LP-low plateau itself measures 108 ns (above the 50 ns minimum), the critical failure here is the **LP exit → HS transition of only 3.3 ns**, far below the 50 ns spec minimum, meaning the LP-01/LP-00 states were essentially skipped or too brief for the SN65DSI83 to reliably detect the SoT preamble. Additionally, the **HS amplitude of 28 mV** is well below the 50 mV threshold and far below the normal 105–122 mV range, indicating the bridge almost certainly did not lock onto the HS data burst — effectively an absent HS transmission from the receiver's perspective. These two compounding failures — a near-instantaneous LP-to-HS transition and a sub-threshold HS amplitude — make it virtually certain the SN65DSI83 missed this SoT entirely, producing a visible flicker event.