MIPI D-PHY Analysis Report

Generated: 2026-04-15 13:21:17  |  Scope: Captures 0967–0996  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0967–0996

## 1. Executive Summary

The system is running with 'Round Best' PHY timing registers that have 5 D-PHY v1.1 violations. The SoT LP-low plateau is bimodal: ~342 ns (good) or 0 ns (flicker). The three confirmed flicker events (0985, 0987, 0995) all show LP-low plateau = 0 ns — the LP-01/LP-00 SoT states are completely absent, so the SN65DSI83 never detects start-of-transmission. Switching to the 'Round Up' register set eliminates all five timing violations and is the single highest-impact fix.

## 2. Consistent Spec Concerns

### 2.1 Register Timing Violations (100% of captures)

Every single capture reads identical non-compliant registers:

| Parameter | Programmed | Actual | Spec Min | Deficit |
|---|---|---|---|---|
| THS_EXIT | 5 bc | 92.6 ns | 100.0 ns | −7.4 ns |
| TCLK_PREPARE | 2 bc | 37.0 ns | 38.0 ns | −1.0 ns |
| TCLK_TRAIL | 3 bc | 55.6 ns | 60.0 ns | −4.4 ns |
| TCLK_PREPARE+TCLK_ZERO | 16 bc | 296.3 ns | 300.0 ns | −3.7 ns |
| THS_PREPARE+THS_ZERO | 9 bc | 166.7 ns | 168.2 ns | −1.5 ns |

Critical observation: All five violations are by margins of 1–7.4 ns — fractions of one byte-clock. This is exactly the kind of marginal non-compliance that works *most of the time* but fails non-deterministically when PVT (process, voltage, temperature) variations or internal PLL jitter push the actual analogue timing slightly shorter than the already-short programmed value. This directly explains the bistable 10% failure rate.

### 2.2 LP-low Plateau Bimodality

Across the 26 captures with valid LP data:

| LP-low Plateau | Count | Flicker? |
|---|---|---|
| ~342 ns | 12 | No (all good) |
| ~108 ns | 11 | No (all good) |
| 0 ns | 3 | YES — all three flicker events |

The 342 ns and 108 ns populations both represent successful SoT sequences (the bridge locks). The 0 ns population represents a completely collapsed SoT — LP-01→LP-00 states are either not emitted or so brief they are unresolvable. The SN65DSI83 cannot detect the data lane SoT entry point and fails to lock.

Root cause chain: THS_PREPARE+THS_ZERO is programmed to 166.7 ns versus the 168.2 ns minimum. When the PHY's internal PLL phase happens to shorten this by even ~2 ns, the SoT LP-low states collapse below the bridge's detection threshold. The TCLK_PREPARE violation (37.0 vs 38.0 ns) compounds this by occasionally mis-aligning the clock lane's HS entry relative to the data lane's SoT, so the bridge misses the synchronisation window entirely.

### 2.3 LP Exit Duration

| LP exit → HS | Occurrences | Notes |
|---|---|---|
| ≥ 113 ns | 5 | Spec-compliant (≥ 50 ns) |
| 2–4 ns | 18 | Spec violation — below 50 ns |
| 0 ns | 3 | Flicker events |

23 of 26 valid captures (88%) show LP exit < 50 ns. The measurement algorithm reports 2–4 ns for the non-flicker cases, which likely represents the LP-11→LP-01 transition being too fast for the measurement resolution rather than truly absent. However, only when it reaches 0 ns does flicker occur. The extremely short LP exit durations across the board confirm that TLPX (55.6 ns) and THS_PREPARE (55.6 ns) are at the very bottom of their acceptable ranges, leaving zero margin.

### 2.4 HS Amplitude Concerns

Clock lane: Consistently ~165.5 mV differential — within spec (140–270 mV) but at the low end (only 25 mV margin above 140 mV floor). Every proto/clk capture shows settled samples below 140 mV (28–136 per capture), indicating ISI/eye-closure at transitions.

Data lane: Nominal amplitude 186–199 mV but with persistent below-140 mV violations (up to 5546 samples in capture 0969). The data eye is stressed.

Clock asymmetry: Consistent +194 mV / −136 mV split on CLK lane (common mode +28–30 mV). This ~58 mV positive/negative imbalance suggests a small DC offset in the CLK driver or termination mismatch. While within spec, it reduces negative-swing noise margin.

### 2.5 LP-11 Voltage

All captures: 1.014–1.016 V (spec 1.0–1.45 V). This is at the absolute floor of the LP-11 specification. The nominal VDDIO is 1.8 V; LP-11 should be at or near VDDIO. At 1.015 V the LP driver is operating with only ~15 mV of margin above the 1.0 V floor.

This is a secondary concern. The low LP-11 voltage indicates the MIPI PHY LP pull-ups are sourcing from a rail that may be loaded or the pull-up resistors are too weak. While it doesn't directly cause the flicker (the SoT failure does), it reduces the LP-11→LP-00 voltage swing available for the bridge's LP state detector, making SoT detection harder.

## 3. Trend Analysis

### 3.1 No Temporal Drift

| Parameter | Range across 30 captures | Trend |
|---|---|---|
| CLK Vdiff | 164.8–166.8 mV | Flat — no drift |
| CLK freq | 213.0–219.2 MHz | Stable ±1.5% |
| CLK jitter RMS | 52.1–56.3 ps | Flat |
| LP-11 voltage | 1.014–1.016 V | Flat |
| 1.8 V mean | 1.764–1.770 V | Flat |
| 1.8 V droop | 7.9–16.2 mV | Mostly flat (one outlier at 16.2 mV — capture 0975) |

Conclusion: There is no progressive degradation. The system is stable between loads. The flicker is purely a per-load-cycle non-deterministic event, consistent with the bistable behaviour description.

### 3.2 Flicker Events Are NOT Correlated With Any Measured Analogue Trend

The three flicker captures (0985, 0987, 0995) show:
- Normal supply (droop 8.7–10.3 mV, within the non-flicker range of 7.9–16.2 mV)
- Normal CLK amplitude and jitter
- Normal LP-11 voltage
- Normal HS burst duration

The only distinguishing feature is LP-low plateau = 0 ns. This confirms the root cause is digital timing (PHY state machine) not analogue signal quality.

## 4. Supply Correlation

### 4.1 1.8 V Supply Health

| Metric | Range | Spec | Status |
|---|---|---|---|
| Mean voltage | 1.764–1.770 V | 1.71–1.89 V | ✓ but 54 mV below nominal 1.8 V |
| Min voltage | 1.748–1.760 V | ≥ 1.71 V | ✓ with 38–50 mV margin |
| Droop depth | 7.9–16.2 mV | — | Acceptable |
| Ripple RMS | 5.25–6.01 mV | — | Good |

### 4.2 Droop vs. Flicker Correlation

| Capture | Droop (mV) | Flicker? |
|---|---|---|
| 0985 | 8.7 | YES |
| 0987 | 10.3 | YES |
| 0995 | 8.9 | YES |
| 0975 | 16.2 | No |
| 0981 | 10.1 | No |

No correlation. The worst droop (16.2 mV, capture 0975) did NOT produce flicker. The flicker captures have unremarkable droop. Supply noise is not the trigger.

### 4.3 LP-11 Voltage vs. Supply

LP-11 at 1.015 V with VDDIO at 1.765 V means the LP pull-up drops ~750 mV. This is consistent with a ~1.2 kΩ pull-up driving ~600 µA into the line termination, or a weak internal pull-up. It does not vary with supply — it's a fixed resistive divider, not a transient issue.

## 5. Anomaly Analysis

### 5.1 Missing LP Data (Captures 0971, 0972, 0988, 0996)

```
[lp_dat] ERROR: index 200000 is out of bounds for axis 0 with size 200000
```

Cause: The LP analysis algorithm's edge-search exceeded the capture buffer boundary. This occurs when the LP-11→LP-00 transition happens very late in the capture window or the trigger placed the SoT event at the extreme end of the acquisition memory.

Action: Increase scope pre-trigger holdoff or LP capture record length by 20%. Not a hardware fault.

### 5.2 Data Lane "Only Negative Swings" / "No HS Signal"

~60% of sig/dat and proto/dat captures show only negative differential swings or zero amplitude. This is a scope triggering/windowing artifact — the high-speed capture window (a few ns) happened to land on a data lane period where only one polarity was present (e.g., during a long run of '0' bits in the pixel data). The data lane carries packet content, not a 50/50 clock, so this is expected and benign.

Action: None required. The proto/dat captures that do resolve both polarities show proper ~195 mV amplitude.

### 5.3 Below-140 mV Samples on Data Lane

The data lane consistently shows hundreds to thousands of settled samples below the 140 mV Vdiff floor. This is ISI (inter-symbol interference) from consecutive same-polarity transitions on the data lane. At 432 Mbit/s with ~165 ps rise times and a data eye that is already smaller than the clock eye (data has random jitter; clock does not), this is expected for a PCB trace of moderate length.

Risk: The SN65DSI83 has its own LP/HS detection threshold. If the data lane eye is marginal, the bridge's CDR could occasionally fail to lock, but this would manifest as persistent HS errors, not the observed bistable SoT failure. This is a secondary concern.

## 6. Actionable Recommendations

### 6.1 PRIMARY FIX — Switch to 'Round Up' Register Set

This is the single fix that addresses the root cause. Patch the samsung-dsim driver (or device tree overlay) to program:

```
PHYTIMING (0xb4) = 0x00000306 (THS_EXIT: 5→6)
PHYTIMING1 (0xb8) = 0x030f0a04 (TCLK_PREPARE: 2→3, TCLK_ZERO: 14→15, TCLK_TRAIL: 3→4)
PHYTIMING2 (0xbc) = 0x00030706 (THS_ZERO: 6→7, THS_TRAIL: 5→6)
```

This eliminates all 5 D-PHY violations and provides adequate margin:

| Parameter | Round Best | Round Up | Spec Min | Margin |
|---|---|---|---|---|
| THS_EXIT | 92.6 ns | 111.1 ns | 100.0 ns | +11.1 ns |
| TCLK_PREPARE | 37.0 ns | 55.6 ns | 38.0 ns | +17.6 ns |
| TCLK_TRAIL | 55.6 ns | 74.1 ns | 60.0 ns | +14.1 ns |
| TCLK_PREP+ZERO | 296.3 ns | 333.3 ns | 300.0 ns | +33.3 ns |
| THS_PREP+ZERO | 166.7 ns | 185.2 ns | 168.2 ns | +17.0 ns |

Expected result: The LP-low plateau should consistently appear at ≥100 ns on every load cycle. The 0 ns collapse events should be eliminated. Flicker rate should drop from 10% to 0%.

### 6.2 Driver Patch Location

In the `samsung-dsim` driver (`drivers/gpu/drm/bridge/samsung-dsim.c`), the timing calculation function `samsung_dsim_set_phy_timing()` uses a rounding mode. The current code path is selecting floor/truncation ("Round Best"). Either:

1. Modify the rounding function to always round up to the next byte-clock boundary when the calculated continuous-time value is within 1 bc of the spec minimum, OR
2. Apply a static override via device tree properties `samsung,phy-timing = <0x00000306 0x030f0a04 0x00030706>;` if the driver supports it, OR
3. Patch the register values directly in the driver's `samsung_dsim_atomic_enable()` path using `regmap_write()` after the default timing is programmed.

### 6.3 SECONDARY — Investigate Low LP-11 Voltage

LP-11 at 1.015 V (vs. 1.8 V VDDIO) indicates the LP driver pull-ups are too weak or there is excessive loading on the LP lines. Check:

• SN65DSI83 LP input bias current (datasheet: should be < 10 µA in LP-11)
• Series resistors on LP lines (some layouts add 200–330 Ω for ESD; these can drop LP voltage)
• Scope probe loading (1 MΩ / 10 pF probes on LP lines will load them; use FET probes or remove probes after measurement)

While this is not the flicker root cause, improving LP-11 to >1.2 V would give the bridge more SoT detection margin.

### 6.4 TERTIARY — Clock Lane Amplitude Margin

CLK Vdiff at ~165 mV with a 140 mV floor leaves only 25 mV margin. At the board level:
- Verify CLK± trace impedance matching (target 100 Ω differential)
- Check for stub lengths on CLK pair (any via or T-junction > 1 mm adds reflection)
- Ensure CLK termination resistor (100 Ω) is placed within 2 mm of the SN65DSI83 input pins

This is not urgent but would improve long-term reliability across temperature.

### 6.5 Scope Capture Improvements

• Increase LP capture record length to 250k points to avoid the index-out-of-bounds errors
• Add a second trigger condition on DAT0_LP going below 0.5 V to ensure the LP-00 state is always captured within the window
• Use math channel for differential LP (Dp−Dn) in addition to single-ended to better resolve LP-01 vs LP-00

## 7. Overall Assessment

Tokens: 44774 in / 4096 out