MIPI D-PHY Analysis Report

Generated: 2026-04-13 14:17:07  |  Scope: Captures 0801–0830  |  Model: claude-opus-4-6

# MIPI D-PHY Signal Integrity Analysis — Captures 0801–0830

## 1. Executive Summary

The system is running with non-compliant D-PHY timing registers ("Round Best" mode) that violate 5 D-PHY v1.1 Table 14 parameters. The LP→HS SoT sequence on the data lane is systematically degraded across ALL 30 captures — every single capture shows LP exit duration ≤ 4 ns (spec ≥ 50 ns), and the 3 confirmed flicker events (0803, 0810, 0830) correlate perfectly with LP-low plateau = 0 ns, meaning the SoT LP-01/LP-00 states were completely absent. The SN65DSI83 bridge's SoT detector failed to recognise the HS entry because there was no discernible LP-low state to trigger on. Switching to "Round Up" compliant registers is the primary fix; the non-deterministic nature of the failure is explained by the timing margins being so thin that cycle-to-cycle byte-clock jitter pushes the PHY across the detection threshold stochastically.

## 2. Consistent Spec Concerns

### 2.1 Register Timing Violations (ALL 30 captures — identical)

Every capture shows the same "Round Best" register values:

| Parameter | Register Value | Actual | Spec Min | Shortfall | Severity |
|-----------|---------------|--------|----------|-----------|----------|
| THS_EXIT | 5 bc → 92.6 ns | 92.6 ns | 100.0 ns | −7.4 ns (−7.4%) | HIGH — affects LP→HS exit |
| TCLK_PREPARE | 2 bc → 37.0 ns | 37.0 ns | 38.0 ns | −1.0 ns (−2.6%) | HIGH — CLK SoT init |
| TCLK_TRAIL | 3 bc → 55.6 ns | 55.6 ns | 60.0 ns | −4.4 ns (−7.3%) | MEDIUM — affects HS→LP |
| TCLK_PREPARE+TCLK_ZERO | 16 bc → 296.3 ns | 296.3 ns | 300.0 ns | −3.7 ns (−1.2%) | HIGH — CLK lane HS init |
| THS_PREPARE+THS_ZERO | 9 bc → 166.7 ns | 166.7 ns | 168.2 ns | −1.5 ns (−0.9%) | CRITICAL — DATA lane SoT |

Key insight: THS_PREPARE+THS_ZERO is only 1.5 ns below spec. At 54 MHz byte clock, one byte-clock period is 18.5 ns — the quantisation granularity is much larger than the deficit. The PHY hardware implements these as digital counters, but the analog output has process/voltage/temperature variation. The 1.5 ns shortfall means the SN65DSI83's SoT detector is operating at the very edge of its recognition window. Some attempts succeed, some fail — this is the stochastic mechanism.

### 2.2 LP→HS SoT Timing (Universal Degradation)

| Metric | Good Captures (no flicker) | Flicker Captures (0803, 0810, 0830) |
|--------|---------------------------|--------------------------------------|
| LP exit → HS | 1–4 ns (all ✗, spec ≥ 50 ns) | 1–3 ns (all ✗) |
| LP-low plateau | 108–348 ns | 0 ns |
| HS amplitude (SE p-p/2) | 20–113 mV | 33–108 mV |

Critical finding: Even the "good" captures show LP exit durations of 1–4 ns — universally violating the ≥ 50 ns specification. The difference between flicker and no-flicker is whether the LP-low plateau (the LP-00 state that signals SoT to the bridge) is present at all:

• LP-low = 0 ns → FLICKER (bridge cannot detect SoT → stuck → persistent flicker)
• LP-low = 108–348 ns → NO FLICKER (bridge detects SoT despite short LP exit)

This three-valued distribution of LP-low plateaux (0, ~108, ~343 ns) suggests the PHY's internal state machine is quantised — the LP-00 state duration is set by a counter that sometimes loads 0 counts.

### 2.3 HS Differential Amplitude

| Lane | Median Amplitude | Spec Range | Concern |
|------|-----------------|------------|---------|
| CLK | 165.5 mV | 140–270 mV | Marginal low — only 25.5 mV above 140 mV floor |
| DAT0 | 190 mV | 140–270 mV | Acceptable but CLK positive/negative asymmetry: +194/−137 mV |

CLK lane asymmetry: Consistently +194 mV positive, −137 mV negative → common mode offset of ~+29 mV. The negative swing (137 mV) is below 140 mV in many individual samples, explaining the persistent "samples below 140 mV" warnings (18–201 samples per capture on CLK). This is a systematic PHY output imbalance, likely due to termination mismatch or PCB trace asymmetry.

### 2.4 LP-11 Voltage

Consistently 1.015–1.017 V across all captures. Spec is 1.0–1.45 V (for 1.8 V VDDIO, LP-11 should be at VOH ≥ 1.1 V per D-PHY spec for reliable detection). At 1.016 V, this is at the absolute floor — the LP driver output is ~56% of VDDIO rather than the expected ~80%+. This reduces LP-state noise margin and makes SoT detection more susceptible to noise.

Root cause: The LP-11 voltage at 1.016 V (rather than ~1.4–1.5 V) suggests either:
- The LP driver pull-up is fighting a low-impedance termination path to ground on the SN65DSI83 input
- PCB series resistance in the 1.8 V LP supply path
- The measurement is single-ended Dp or Dn only, and the LP voltage divider with the SN65DSI83's internal 200 Ω termination is pulling it down

## 3. Trend Analysis Across Captures

### 3.1 No Temporal Drift
- HS amplitude: CLK 164–167 mV, DAT0 186–223 mV — flat, no drift
- Jitter: CLK p-p 143–180 ps, RMS 51–56 ps — stable
- 1.8 V supply: Mean 1.762–1.769 V, droop 6.7–12.0 mV — stable
- LP-11 voltage: 1.015–1.017 V — dead flat
- LP-11 duration: 1.73 µs — identical across all captures (hardware timer)

### 3.2 LP-low Plateau Distribution (key finding)

Tabulating across all 30 captures with LP data:

| LP-low Plateau | Count | Flicker? |
|----------------|-------|----------|
| 0 ns | 3 (0803, 0810, 0830) | YES — all 3 flicker events |
| ~108 ns | 7 (0808, 0809, 0812, 0815, 0820, 0823, 0827, 0828) | No |
| ~342-348 ns | 17 (0801, 0804, 0806, 0807, 0811, 0813, 0814, 0816, 0817, 0818, 0819, 0821, 0822, 0824, 0825, 0826, 0829) | No |
| No LP data | 2 (0802, 0805) — processing error | Unknown |

This trimodal distribution (0 / 108 / 343 ns) is highly diagnostic. The LP-low plateau appears to be quantised at ~0, ~6, or ~18.5 byte-clock intervals:
- 343 ns ÷ 18.5 ns/bc ≈ 18.5 bc (likely 19 bc counter)
- 108 ns ÷ 18.5 ns/bc ≈ 5.8 bc (likely 6 bc counter)
- 0 ns = counter not loaded / skipped

The trimodal quantisation strongly suggests a race condition in the Samsung DSIM PHY state machine's SoT sequencer. The byte-clock domain loads the LP-state counters, but a metastability event at the boundary between the LP clock domain and the byte-clock domain occasionally causes a counter to load 0 or a reduced value.

The too-short THS_PREPARE+THS_ZERO (166.7 ns vs 168.2 ns spec) narrows the timing window for this counter load, making the race more likely to result in a 0 or reduced count.

## 4. Supply Correlation Analysis

### 4.1 1.8 V Supply vs Flicker Events

| Capture | Flicker? | LP-low (ns) | 1.8V Mean (V) | Droop (mV) | Ripple RMS (mV) |
|---------|----------|-------------|----------------|------------|-----------------|
| 0803 | YES | 0 | 1.7638 | 7.9 | 5.65 |
| 0810 | YES | 0 | 1.7642 | 8.2 | 5.54 |
| 0830 | YES | 0 | 1.7685 | 8.5 | 5.42 |
| 0801 | No | 343 | 1.7644 | 8.4 | 5.40 |
| 0804 | No | 343 | 1.7680 | 12.0 | 5.97 |
| 0825 | No | 343 | 1.7625 | 10.5 | 5.92 |

Conclusion: No supply correlation. The flicker captures have droop/ripple values well within the range of non-flicker captures. Capture 0804 has the *highest* droop (12.0 mV) and *highest* ripple (5.97 mV) yet works perfectly. Capture 0830 (flicker) has the *highest* supply voltage (1.7685 V) in the batch. The supply is not the trigger.

### 4.2 Supply Health
- All captures: Min voltage ≥ 1.752 V (spec 1.71 V) ✓
- Maximum droop: 12.0 mV (< 1% of 1.8 V) ✓
- Ripple RMS: 5.12–5.97 mV — clean
- Supply is healthy and not contributing to the flicker.

## 5. Warning/Error Explanations

### 5.1 "CLK lane is in continuous HS mode — LP states not expected on CLK"
Explanation: Normal. In DSI video mode, the CLK lane enters HS once at pipeline start and remains in continuous HS mode. LP→HS transitions are only expected on data lanes. No action needed.

### 5.2 "Only negative swings in capture window — amplitude may be underestimated"
Explanation: The scope trigger captured a window where DAT0 was sending a long run of one polarity (e.g., a blanking pattern or repeated byte). With DDR signalling, a long run of `0x00` or `0xFF` data would produce only one polarity of differential swing. The reported amplitude (190–195 mV) is consistent with the proto captures, so this is a trigger windowing artefact, not a signal problem. The amplitude is valid as a lower bound.

### 5.3 "No HS signal detected — line may be in LP state or idle" (sig/dat in 0804, 0808, 0811, 0813, 0827)
Explanation: The high-res sig capture triggered during an inter-frame blanking interval when the data lane was in LP-11 or LP-00 idle state. In DSI video mode with non-burst timing, the data lane returns to LP between frames. Trigger timing variability, not a signal fault. Consider triggering sig captures on a specific HS burst.

### 5.4 "[lp_dat] ERROR: index 200000 is out of bounds" (0802, 0805)
Explanation: The LP analysis script's edge-detection algorithm ran off the end of the capture buffer without finding the expected LP→HS transition within the 200k-sample window. Most likely cause: the trigger fired too early or too late relative to the SoT event, placing it outside the capture window. These captures have no LP data — they are neither flicker-confirmed nor flicker-excluded. Increase LP capture depth or adjust trigger holdoff by ±1 µs.

### 5.5 "LP exit duration X ns below spec min 50 ns" (ALL captures with LP data)
Explanation: This is the systemic problem. Every single data-lane LP capture shows LP exit (time from LP-11 falling edge to HS-0 crossing) of 1–4 ns versus the 50 ns minimum. The PHY's LP→HS transition is too fast for the bridge to track. The SN65DSI83's input comparators need time to switch from LP mode (high-voltage, ~1 V common mode) to HS mode (low-voltage, ~200 mV differential). A 1–4 ns transition gives no settling time.

Root cause linkage: This maps directly to the THS_EXIT violation (92.6 ns vs 100 ns spec). But the measured 1–4 ns is far shorter than even the programmed 92.6 ns. This suggests the LP exit metric is measuring a different event — likely the Dp/Dn single-ended fall time from LP-11 (~1.0 V) to 0 V, which is the analog slew rate of the LP driver turning off. The programmed THS_EXIT of 92.6 ns controls how long the PHY stays in LP-00 after LP-01 before asserting HS, but if the LP-01 and LP-00 states are being skipped or truncated (as the 0 ns LP-low plateau confirms), THS_EXIT never executes properly.

### 5.6 "X settled samples below 140 mV" (CLK lane, all captures)
Explanation: CLK differential amplitude has a negative-swing shortfall (−137 mV typical vs −140 mV spec). With noise, ~0.5–5% of settled HS samples dip below 140 mV. This is the CLK common-mode offset (+29 mV) causing asymmetric clipping. While functional, it reduces clock eye margin.

## 6. Detailed Root Cause Analysis

### 6.1 Why the Flicker is Non-Deterministic

The failure mechanism is a digital race condition in the DSIM PHY's SoT state machine, amplified by timing parameters set below spec:

1. At pipeline load, the DSIM controller commands the PHY to execute LP-11 → LP-01 → LP-00 → HS-0 (SoT sequence)
2. The LP-state durations are controlled by byte-clock counters loaded from PHYTIMING/PHYTIMING2 registers
3. THS_PREPARE+THS_ZERO is programmed to 9 byte-clocks (166.7 ns) — 1.5 ns below the 168.2 ns spec minimum
4. The PHY's internal clock-domain crossing between LP and HS domains has a synchronisation window
5. When the counter values are at the spec boundary, the synchroniser occasionally drops a count or skips the LP-00 state entirely
6. This is a classic metastability-induced non-deterministic failure

The trimodal LP-low distribution (0 / 108 /

Tokens: 45448 in / 4096 out