31 lines
2.8 KiB
Plaintext
31 lines
2.8 KiB
Plaintext
|
<EFBFBD>
|
|||
|
|
<00>;<3B>i<EFBFBD> <00> <00> <00> d Z dZdZdZdZddddd <09>Zd
|
|||
|
|
Zd Zd ZdZ d
Z
|
|||
|
|
dZ dZ dZ
dZdZdZdZdZdedefd<16>Z ee<10> Zed Zed Zed Zdedefd<1B>Z ee<19> Z d Z dZ d Z d Z d Z!d Z"d!Z#d"Z$e"e#z e$z Z%d#Z&d$Z'd%Z(dZ)dZ*d&Z+y')(u Central configuration for the MIPI flicker investigation suite.
|
|||
|
|
|
|||
|
|
All IP addresses, register addresses, MIPI D-PHY spec minimums, and probe
|
|||
|
|
calibration constants live here. This is the single tuning surface — modules
|
|||
|
|
should import from here rather than hard-coding values.
|
|||
|
|
z 192.168.45.8i<EFBFBD> z 192.168.45.4z 192.168.45.3<EFBFBD> <00> <00> <00> )<04>CLK_P<5F>CLK_N<5F>DAT0_P<5F>DAT0_Ng3333333@g:<3A>0<EFBFBD><30>y5>i <20> g<><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>?<3F>NEGativegffffff
|
|||
|
|
@g <00>?g @i <00>J<04> <00>pixel_clock_hz<68>returnc <00>B <00> | t z t z }|dz }d|z }|||d<03>S )u<> Recompute DSI/byte clock and UI for a given pixel clock.
|
|||
|
|
|
|||
|
|
Used when --pixel-clock overrides the default — UI feeds into several
|
|||
|
|
DPHY_SPEC minimums, so they must be recomputed from the live value.
|
|||
|
|
<20> g e<><65>A)<03>
|
|||
|
|
DSI_CLK_HZ<EFBFBD> BYTE_CLK_HZ<48>UI_NS)<02>BITS_PER_PIXEL<45> DSI_LANES)r <00>
|
|||
|
|
dsi_clk_hz<EFBFBD> byte_clk_hz<68>ui_nss <20> config.py<70>
derive_clocksr 0 s9 <00> <00> <20>.<2E>0<>I<EFBFBD>=<3D>J<EFBFBD> <1C><01>/<2F>K<EFBFBD> <0F>*<2A> <1C>E<EFBFBD> <20>"<22><16> <06> <06> r r r r c <00>f <00> ddddddd| z z dd| z z d d
|
|||
|
|
| z z t d | z dd| z z <00> d d
<0A>
|
|||
|
|
S )z=Build the MIPI D-PHY v1.1 minimum-timing dict for a given UI.g I@g C@g `p@g <00>r@g N@<40>4 g D@r g b@<40>
|
|||
|
|
r g Y@)
|
|||
|
|
<EFBFBD>t_lpx<70>
t_clk_prepare<72>
|
|||
|
|
t_clk_zero<EFBFBD>t_clk_prepare_plus_zero<72> t_clk_trail<69>
|
|||
|
|
t_clk_post<EFBFBD> t_hs_prepare<72> t_hs_zero<72>
|
|||
|
|
t_hs_trail<EFBFBD> t_hs_exit)<01>max)r s r <00>build_dphy_specr) F s[ <00> <00> <16> <1D><1B>#(<28><1B><1A>R<EFBFBD>%<25>Z<EFBFBD>'<27> <1C>q<EFBFBD>5<EFBFBD>y<EFBFBD>(<28><1A>R<EFBFBD>%<25>Z<EFBFBD>'<27><19>!<21>e<EFBFBD>)<29>T<EFBFBD>A<EFBFBD><05>I<EFBFBD>%5<>6<><1A> <06> r <00>, <00><> r <00> r <00> <00>@ i<> <00>2i<32> <00>2i<32> <00>2<EFBFBD>capturesN),<2C>__doc__<5F> TARGET_IP<49> TARGET_PORT<52>SCOPE_IP<49>PSU_IP<49>SCOPE_CHANNELS<4C>PROBE_ATTENUATION<4F>SCOPE_TIMEBASE<53> SCOPE_POINTS<54>TRIGGER_CHANNEL<45>TRIGGER_LEVEL_V<5F>
TRIGGER_SLOPE<50>PSU_CHANNEL_DISPLAY<41>PSU_DISPLAY_VOLTAGE<47>PSU_DISPLAY_CURRENT<4E>PSU_POWER_CYCLE_DELAY_S<5F>PIXEL_CLOCK_HZr r <00>int<6E>dictr <00>_clocksr r r <00>floatr) <00> DPHY_SPEC<45>
SN65_I2C_ADDR<44> SN65_I2C_BUS<55> SN65_REG_IRQ<52> SN65_REG_PLL<4C> SN65_REG_CLK<4C>SN65_ERR_SYNCH<43> SN65_ERR_SOT<4F> SN65_ERR_UNC<4E>SN65_FLICKER_MASK<53>DSIM_PHYTIMING_BASE<53>DSIM_PHYTIMING1<47>DSIM_PHYTIMING2<47>TWEAK_BIT_FIFO_FLUSH<53>TWEAK_BIT_ROUND_UP<55> CAPTURE_ROOT<4F> r r <00><module>rV s> <00><01><04>
<1B> <09><12> <0B> <19><08> <17><06> <0F>
<0E><0F><0F> <02><0E> <19> <11><15><0E><16> <0C><13><0F><16><0F><1A>
<0A>
|
|||
|
|
<18> <13><19> <13><19> <13> <1D> <17>
|
|||
|
|
<1C><0E>
<0A> <09><13><0E>
<06>#<23>
<06>$<24>
<06> <18><0E>
|
|||
|
|
'<27><07>
<14>\<5C>
"<22>
|
|||
|
|
<EFBFBD><15>m<EFBFBD>$<24> <0B><0F><07><18><05>
<06>5<EFBFBD>
<06>T<EFBFBD>
<06>
<1C>E<EFBFBD> "<22> <09>
|
|||
|
|
<15>
<0A><10> <0C><13> <0C><13> <0C><13> <0C><17><0E><15> <0C><15> <0C>"<22>\<5C>1<>L<EFBFBD>@<40> <11>
|
|||
|
|
!<21> <13> <1C><0F> <1C><0F>
|
|||
|
|
<1E> <14><1B> <12>
|
|||
|
|
<1A> r
|