14081 lines
544 KiB
Plaintext
14081 lines
544 KiB
Plaintext
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HW_DEPT_NEXIO_SIGN.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001d8 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00005604 080001d8 080001d8 000011d8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000324 080057dc 080057dc 000067dc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08005b00 08005b00 00007018 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 08005b00 08005b00 00006b00 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08005b08 08005b08 00007018 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08005b08 08005b08 00006b08 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08005b0c 08005b0c 00006b0c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000018 20000000 08005b10 00007000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00001108 20000018 08005b28 00007018 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20001120 08005b28 00007120 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 00007018 2**0
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CONTENTS, READONLY
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12 .debug_info 0000f68f 00000000 00000000 00007048 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 000020e0 00000000 00000000 000166d7 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000c80 00000000 00000000 000187b8 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 000009b2 00000000 00000000 00019438 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 0001d1ef 00000000 00000000 00019dea 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0000ef3a 00000000 00000000 00036fd9 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000b8906 00000000 00000000 00045f13 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 000fe819 2**0
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CONTENTS, READONLY
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20 .debug_frame 000030b4 00000000 00000000 000fe85c 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000071 00000000 00000000 00101910 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001d8 <__do_global_dtors_aux>:
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80001d8: b510 push {r4, lr}
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80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
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80001dc: 7823 ldrb r3, [r4, #0]
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80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
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80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
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80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
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80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
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80001e6: f3af 8000 nop.w
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80001ea: 2301 movs r3, #1
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80001ec: 7023 strb r3, [r4, #0]
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80001ee: bd10 pop {r4, pc}
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80001f0: 20000018 .word 0x20000018
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80001f4: 00000000 .word 0x00000000
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80001f8: 080057c4 .word 0x080057c4
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080001fc <frame_dummy>:
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80001fc: b508 push {r3, lr}
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80001fe: 4b03 ldr r3, [pc, #12] @ (800020c <frame_dummy+0x10>)
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8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
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8000202: 4903 ldr r1, [pc, #12] @ (8000210 <frame_dummy+0x14>)
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8000204: 4803 ldr r0, [pc, #12] @ (8000214 <frame_dummy+0x18>)
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8000206: f3af 8000 nop.w
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800020a: bd08 pop {r3, pc}
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800020c: 00000000 .word 0x00000000
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8000210: 2000001c .word 0x2000001c
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8000214: 080057c4 .word 0x080057c4
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08000218 <__aeabi_uldivmod>:
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8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18>
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800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18>
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800021c: 2900 cmp r1, #0
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800021e: bf08 it eq
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8000220: 2800 cmpeq r0, #0
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8000222: bf1c itt ne
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8000224: f04f 31ff movne.w r1, #4294967295
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8000228: f04f 30ff movne.w r0, #4294967295
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800022c: f000 b988 b.w 8000540 <__aeabi_idiv0>
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8000230: f1ad 0c08 sub.w ip, sp, #8
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8000234: e96d ce04 strd ip, lr, [sp, #-16]!
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8000238: f000 f806 bl 8000248 <__udivmoddi4>
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800023c: f8dd e004 ldr.w lr, [sp, #4]
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8000240: e9dd 2302 ldrd r2, r3, [sp, #8]
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8000244: b004 add sp, #16
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8000246: 4770 bx lr
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08000248 <__udivmoddi4>:
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8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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800024c: 9d08 ldr r5, [sp, #32]
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800024e: 460f mov r7, r1
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8000250: 4604 mov r4, r0
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8000252: 468c mov ip, r1
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8000254: 2b00 cmp r3, #0
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8000256: d148 bne.n 80002ea <__udivmoddi4+0xa2>
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8000258: 428a cmp r2, r1
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800025a: 4616 mov r6, r2
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800025c: d961 bls.n 8000322 <__udivmoddi4+0xda>
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800025e: fab2 f382 clz r3, r2
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8000262: b14b cbz r3, 8000278 <__udivmoddi4+0x30>
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8000264: f1c3 0220 rsb r2, r3, #32
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8000268: fa01 fc03 lsl.w ip, r1, r3
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800026c: fa20 f202 lsr.w r2, r0, r2
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8000270: 409e lsls r6, r3
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8000272: ea42 0c0c orr.w ip, r2, ip
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8000276: 409c lsls r4, r3
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8000278: ea4f 4e16 mov.w lr, r6, lsr #16
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800027c: b2b7 uxth r7, r6
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800027e: fbbc f1fe udiv r1, ip, lr
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8000282: 0c22 lsrs r2, r4, #16
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8000284: fb0e cc11 mls ip, lr, r1, ip
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8000288: ea42 420c orr.w r2, r2, ip, lsl #16
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800028c: fb01 f007 mul.w r0, r1, r7
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8000290: 4290 cmp r0, r2
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8000292: d909 bls.n 80002a8 <__udivmoddi4+0x60>
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8000294: 18b2 adds r2, r6, r2
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8000296: f101 3cff add.w ip, r1, #4294967295
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800029a: f080 80ee bcs.w 800047a <__udivmoddi4+0x232>
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800029e: 4290 cmp r0, r2
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80002a0: f240 80eb bls.w 800047a <__udivmoddi4+0x232>
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80002a4: 3902 subs r1, #2
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80002a6: 4432 add r2, r6
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80002a8: 1a12 subs r2, r2, r0
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80002aa: b2a4 uxth r4, r4
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80002ac: fbb2 f0fe udiv r0, r2, lr
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80002b0: fb0e 2210 mls r2, lr, r0, r2
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80002b4: ea44 4402 orr.w r4, r4, r2, lsl #16
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80002b8: fb00 f707 mul.w r7, r0, r7
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80002bc: 42a7 cmp r7, r4
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80002be: d909 bls.n 80002d4 <__udivmoddi4+0x8c>
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80002c0: 1934 adds r4, r6, r4
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80002c2: f100 32ff add.w r2, r0, #4294967295
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80002c6: f080 80da bcs.w 800047e <__udivmoddi4+0x236>
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80002ca: 42a7 cmp r7, r4
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80002cc: f240 80d7 bls.w 800047e <__udivmoddi4+0x236>
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80002d0: 4434 add r4, r6
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80002d2: 3802 subs r0, #2
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80002d4: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002d8: 1be4 subs r4, r4, r7
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80002da: 2100 movs r1, #0
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80002dc: b11d cbz r5, 80002e6 <__udivmoddi4+0x9e>
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80002de: 40dc lsrs r4, r3
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80002e0: 2300 movs r3, #0
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80002e2: e9c5 4300 strd r4, r3, [r5]
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80002e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002ea: 428b cmp r3, r1
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80002ec: d906 bls.n 80002fc <__udivmoddi4+0xb4>
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80002ee: b10d cbz r5, 80002f4 <__udivmoddi4+0xac>
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80002f0: e9c5 0100 strd r0, r1, [r5]
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80002f4: 2100 movs r1, #0
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80002f6: 4608 mov r0, r1
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80002f8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002fc: fab3 f183 clz r1, r3
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8000300: 2900 cmp r1, #0
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8000302: d148 bne.n 8000396 <__udivmoddi4+0x14e>
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8000304: 42bb cmp r3, r7
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8000306: d302 bcc.n 800030e <__udivmoddi4+0xc6>
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8000308: 4282 cmp r2, r0
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800030a: f200 8107 bhi.w 800051c <__udivmoddi4+0x2d4>
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800030e: 1a84 subs r4, r0, r2
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8000310: eb67 0203 sbc.w r2, r7, r3
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8000314: 2001 movs r0, #1
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8000316: 4694 mov ip, r2
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8000318: 2d00 cmp r5, #0
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800031a: d0e4 beq.n 80002e6 <__udivmoddi4+0x9e>
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800031c: e9c5 4c00 strd r4, ip, [r5]
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8000320: e7e1 b.n 80002e6 <__udivmoddi4+0x9e>
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8000322: 2a00 cmp r2, #0
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8000324: f000 8092 beq.w 800044c <__udivmoddi4+0x204>
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8000328: fab2 f382 clz r3, r2
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800032c: 2b00 cmp r3, #0
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800032e: f040 80a8 bne.w 8000482 <__udivmoddi4+0x23a>
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8000332: 1a8a subs r2, r1, r2
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8000334: ea4f 4e16 mov.w lr, r6, lsr #16
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8000338: fa1f fc86 uxth.w ip, r6
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800033c: 2101 movs r1, #1
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800033e: 0c20 lsrs r0, r4, #16
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8000340: fbb2 f7fe udiv r7, r2, lr
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8000344: fb0e 2217 mls r2, lr, r7, r2
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8000348: ea40 4202 orr.w r2, r0, r2, lsl #16
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800034c: fb0c f007 mul.w r0, ip, r7
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8000350: 4290 cmp r0, r2
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8000352: d907 bls.n 8000364 <__udivmoddi4+0x11c>
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8000354: 18b2 adds r2, r6, r2
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8000356: f107 38ff add.w r8, r7, #4294967295
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800035a: d202 bcs.n 8000362 <__udivmoddi4+0x11a>
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800035c: 4290 cmp r0, r2
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800035e: f200 80e2 bhi.w 8000526 <__udivmoddi4+0x2de>
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8000362: 4647 mov r7, r8
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8000364: 1a12 subs r2, r2, r0
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8000366: b2a4 uxth r4, r4
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8000368: fbb2 f0fe udiv r0, r2, lr
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800036c: fb0e 2210 mls r2, lr, r0, r2
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8000370: ea44 4402 orr.w r4, r4, r2, lsl #16
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8000374: fb0c fc00 mul.w ip, ip, r0
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8000378: 45a4 cmp ip, r4
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800037a: d907 bls.n 800038c <__udivmoddi4+0x144>
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800037c: 1934 adds r4, r6, r4
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800037e: f100 32ff add.w r2, r0, #4294967295
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8000382: d202 bcs.n 800038a <__udivmoddi4+0x142>
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8000384: 45a4 cmp ip, r4
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8000386: f200 80cb bhi.w 8000520 <__udivmoddi4+0x2d8>
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800038a: 4610 mov r0, r2
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800038c: eba4 040c sub.w r4, r4, ip
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8000390: ea40 4007 orr.w r0, r0, r7, lsl #16
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8000394: e7a2 b.n 80002dc <__udivmoddi4+0x94>
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8000396: f1c1 0620 rsb r6, r1, #32
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800039a: 408b lsls r3, r1
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800039c: fa22 fc06 lsr.w ip, r2, r6
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80003a0: ea4c 0c03 orr.w ip, ip, r3
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80003a4: fa07 f401 lsl.w r4, r7, r1
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80003a8: fa20 f306 lsr.w r3, r0, r6
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80003ac: 40f7 lsrs r7, r6
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80003ae: ea4f 491c mov.w r9, ip, lsr #16
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80003b2: 4323 orrs r3, r4
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80003b4: fa00 f801 lsl.w r8, r0, r1
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80003b8: fa1f fe8c uxth.w lr, ip
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80003bc: fbb7 f0f9 udiv r0, r7, r9
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80003c0: 0c1c lsrs r4, r3, #16
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80003c2: fb09 7710 mls r7, r9, r0, r7
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80003c6: ea44 4407 orr.w r4, r4, r7, lsl #16
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80003ca: fb00 f70e mul.w r7, r0, lr
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80003ce: 42a7 cmp r7, r4
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80003d0: fa02 f201 lsl.w r2, r2, r1
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80003d4: d90a bls.n 80003ec <__udivmoddi4+0x1a4>
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80003d6: eb1c 0404 adds.w r4, ip, r4
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80003da: f100 3aff add.w sl, r0, #4294967295
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80003de: f080 809b bcs.w 8000518 <__udivmoddi4+0x2d0>
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80003e2: 42a7 cmp r7, r4
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80003e4: f240 8098 bls.w 8000518 <__udivmoddi4+0x2d0>
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80003e8: 3802 subs r0, #2
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80003ea: 4464 add r4, ip
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80003ec: 1be4 subs r4, r4, r7
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80003ee: b29f uxth r7, r3
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80003f0: fbb4 f3f9 udiv r3, r4, r9
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80003f4: fb09 4413 mls r4, r9, r3, r4
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80003f8: ea47 4404 orr.w r4, r7, r4, lsl #16
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80003fc: fb03 fe0e mul.w lr, r3, lr
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8000400: 45a6 cmp lr, r4
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8000402: d909 bls.n 8000418 <__udivmoddi4+0x1d0>
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8000404: eb1c 0404 adds.w r4, ip, r4
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8000408: f103 37ff add.w r7, r3, #4294967295
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800040c: f080 8082 bcs.w 8000514 <__udivmoddi4+0x2cc>
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8000410: 45a6 cmp lr, r4
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8000412: d97f bls.n 8000514 <__udivmoddi4+0x2cc>
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8000414: 3b02 subs r3, #2
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8000416: 4464 add r4, ip
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8000418: ea43 4000 orr.w r0, r3, r0, lsl #16
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800041c: eba4 040e sub.w r4, r4, lr
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8000420: fba0 e702 umull lr, r7, r0, r2
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8000424: 42bc cmp r4, r7
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8000426: 4673 mov r3, lr
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8000428: 46b9 mov r9, r7
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800042a: d363 bcc.n 80004f4 <__udivmoddi4+0x2ac>
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800042c: d060 beq.n 80004f0 <__udivmoddi4+0x2a8>
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800042e: b15d cbz r5, 8000448 <__udivmoddi4+0x200>
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8000430: ebb8 0203 subs.w r2, r8, r3
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8000434: eb64 0409 sbc.w r4, r4, r9
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8000438: fa04 f606 lsl.w r6, r4, r6
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800043c: fa22 f301 lsr.w r3, r2, r1
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8000440: 431e orrs r6, r3
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8000442: 40cc lsrs r4, r1
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8000444: e9c5 6400 strd r6, r4, [r5]
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8000448: 2100 movs r1, #0
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800044a: e74c b.n 80002e6 <__udivmoddi4+0x9e>
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800044c: 0862 lsrs r2, r4, #1
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800044e: 0848 lsrs r0, r1, #1
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8000450: ea42 71c1 orr.w r1, r2, r1, lsl #31
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8000454: 0c0b lsrs r3, r1, #16
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8000456: ea43 4300 orr.w r3, r3, r0, lsl #16
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800045a: b28a uxth r2, r1
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800045c: ea42 4203 orr.w r2, r2, r3, lsl #16
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8000460: fbb3 f1f6 udiv r1, r3, r6
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8000464: 07e4 lsls r4, r4, #31
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8000466: 46b4 mov ip, r6
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8000468: 4637 mov r7, r6
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800046a: 46b6 mov lr, r6
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800046c: 231f movs r3, #31
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800046e: fbb0 f0f6 udiv r0, r0, r6
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8000472: 1bd2 subs r2, r2, r7
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8000474: ea41 4100 orr.w r1, r1, r0, lsl #16
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8000478: e761 b.n 800033e <__udivmoddi4+0xf6>
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800047a: 4661 mov r1, ip
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800047c: e714 b.n 80002a8 <__udivmoddi4+0x60>
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800047e: 4610 mov r0, r2
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8000480: e728 b.n 80002d4 <__udivmoddi4+0x8c>
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8000482: f1c3 0120 rsb r1, r3, #32
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8000486: fa20 f201 lsr.w r2, r0, r1
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800048a: 409e lsls r6, r3
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800048c: fa27 f101 lsr.w r1, r7, r1
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8000490: 409f lsls r7, r3
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8000492: 433a orrs r2, r7
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8000494: ea4f 4e16 mov.w lr, r6, lsr #16
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8000498: fa1f fc86 uxth.w ip, r6
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800049c: fbb1 f7fe udiv r7, r1, lr
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80004a0: fb0e 1017 mls r0, lr, r7, r1
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80004a4: 0c11 lsrs r1, r2, #16
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80004a6: ea41 4100 orr.w r1, r1, r0, lsl #16
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80004aa: fb07 f80c mul.w r8, r7, ip
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80004ae: 4588 cmp r8, r1
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80004b0: fa04 f403 lsl.w r4, r4, r3
|
|
80004b4: d93a bls.n 800052c <__udivmoddi4+0x2e4>
|
|
80004b6: 1871 adds r1, r6, r1
|
|
80004b8: f107 30ff add.w r0, r7, #4294967295
|
|
80004bc: d201 bcs.n 80004c2 <__udivmoddi4+0x27a>
|
|
80004be: 4588 cmp r8, r1
|
|
80004c0: d81f bhi.n 8000502 <__udivmoddi4+0x2ba>
|
|
80004c2: eba1 0108 sub.w r1, r1, r8
|
|
80004c6: fbb1 f8fe udiv r8, r1, lr
|
|
80004ca: fb08 f70c mul.w r7, r8, ip
|
|
80004ce: fb0e 1118 mls r1, lr, r8, r1
|
|
80004d2: b292 uxth r2, r2
|
|
80004d4: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004d8: 42ba cmp r2, r7
|
|
80004da: d22f bcs.n 800053c <__udivmoddi4+0x2f4>
|
|
80004dc: 18b2 adds r2, r6, r2
|
|
80004de: f108 31ff add.w r1, r8, #4294967295
|
|
80004e2: d2c6 bcs.n 8000472 <__udivmoddi4+0x22a>
|
|
80004e4: 42ba cmp r2, r7
|
|
80004e6: d2c4 bcs.n 8000472 <__udivmoddi4+0x22a>
|
|
80004e8: f1a8 0102 sub.w r1, r8, #2
|
|
80004ec: 4432 add r2, r6
|
|
80004ee: e7c0 b.n 8000472 <__udivmoddi4+0x22a>
|
|
80004f0: 45f0 cmp r8, lr
|
|
80004f2: d29c bcs.n 800042e <__udivmoddi4+0x1e6>
|
|
80004f4: ebbe 0302 subs.w r3, lr, r2
|
|
80004f8: eb67 070c sbc.w r7, r7, ip
|
|
80004fc: 3801 subs r0, #1
|
|
80004fe: 46b9 mov r9, r7
|
|
8000500: e795 b.n 800042e <__udivmoddi4+0x1e6>
|
|
8000502: eba6 0808 sub.w r8, r6, r8
|
|
8000506: 4441 add r1, r8
|
|
8000508: 1eb8 subs r0, r7, #2
|
|
800050a: fbb1 f8fe udiv r8, r1, lr
|
|
800050e: fb08 f70c mul.w r7, r8, ip
|
|
8000512: e7dc b.n 80004ce <__udivmoddi4+0x286>
|
|
8000514: 463b mov r3, r7
|
|
8000516: e77f b.n 8000418 <__udivmoddi4+0x1d0>
|
|
8000518: 4650 mov r0, sl
|
|
800051a: e767 b.n 80003ec <__udivmoddi4+0x1a4>
|
|
800051c: 4608 mov r0, r1
|
|
800051e: e6fb b.n 8000318 <__udivmoddi4+0xd0>
|
|
8000520: 4434 add r4, r6
|
|
8000522: 3802 subs r0, #2
|
|
8000524: e732 b.n 800038c <__udivmoddi4+0x144>
|
|
8000526: 3f02 subs r7, #2
|
|
8000528: 4432 add r2, r6
|
|
800052a: e71b b.n 8000364 <__udivmoddi4+0x11c>
|
|
800052c: eba1 0108 sub.w r1, r1, r8
|
|
8000530: 4638 mov r0, r7
|
|
8000532: fbb1 f8fe udiv r8, r1, lr
|
|
8000536: fb08 f70c mul.w r7, r8, ip
|
|
800053a: e7c8 b.n 80004ce <__udivmoddi4+0x286>
|
|
800053c: 4641 mov r1, r8
|
|
800053e: e798 b.n 8000472 <__udivmoddi4+0x22a>
|
|
|
|
08000540 <__aeabi_idiv0>:
|
|
8000540: 4770 bx lr
|
|
8000542: bf00 nop
|
|
|
|
08000544 <delay_us>:
|
|
/* ════════════════════════════════════════════════
|
|
Low level display helpers
|
|
════════════════════════════════════════════════ */
|
|
|
|
static void delay_us(uint32_t us)
|
|
{
|
|
8000544: b480 push {r7}
|
|
8000546: b085 sub sp, #20
|
|
8000548: af00 add r7, sp, #0
|
|
800054a: 6078 str r0, [r7, #4]
|
|
uint32_t start = DWT->CYCCNT;
|
|
800054c: 4b0d ldr r3, [pc, #52] @ (8000584 <delay_us+0x40>)
|
|
800054e: 685b ldr r3, [r3, #4]
|
|
8000550: 60fb str r3, [r7, #12]
|
|
uint32_t ticks = (SystemCoreClock / 1000000U) * us;
|
|
8000552: 4b0d ldr r3, [pc, #52] @ (8000588 <delay_us+0x44>)
|
|
8000554: 681b ldr r3, [r3, #0]
|
|
8000556: 4a0d ldr r2, [pc, #52] @ (800058c <delay_us+0x48>)
|
|
8000558: fba2 2303 umull r2, r3, r2, r3
|
|
800055c: 0c9a lsrs r2, r3, #18
|
|
800055e: 687b ldr r3, [r7, #4]
|
|
8000560: fb02 f303 mul.w r3, r2, r3
|
|
8000564: 60bb str r3, [r7, #8]
|
|
while ((DWT->CYCCNT - start) < ticks);
|
|
8000566: bf00 nop
|
|
8000568: 4b06 ldr r3, [pc, #24] @ (8000584 <delay_us+0x40>)
|
|
800056a: 685a ldr r2, [r3, #4]
|
|
800056c: 68fb ldr r3, [r7, #12]
|
|
800056e: 1ad3 subs r3, r2, r3
|
|
8000570: 68ba ldr r2, [r7, #8]
|
|
8000572: 429a cmp r2, r3
|
|
8000574: d8f8 bhi.n 8000568 <delay_us+0x24>
|
|
}
|
|
8000576: bf00 nop
|
|
8000578: bf00 nop
|
|
800057a: 3714 adds r7, #20
|
|
800057c: 46bd mov sp, r7
|
|
800057e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000582: 4770 bx lr
|
|
8000584: e0001000 .word 0xe0001000
|
|
8000588: 2000000c .word 0x2000000c
|
|
800058c: 431bde83 .word 0x431bde83
|
|
|
|
08000590 <all_rows_off>:
|
|
|
|
static void all_rows_off(void)
|
|
{
|
|
8000590: b580 push {r7, lr}
|
|
8000592: b082 sub sp, #8
|
|
8000594: af00 add r7, sp, #0
|
|
for (int i = 0; i < ROWS; i++)
|
|
8000596: 2300 movs r3, #0
|
|
8000598: 607b str r3, [r7, #4]
|
|
800059a: e00f b.n 80005bc <all_rows_off+0x2c>
|
|
HAL_GPIO_WritePin(ROW_PINS[i].port, ROW_PINS[i].pin, GPIO_PIN_SET);
|
|
800059c: 4a0b ldr r2, [pc, #44] @ (80005cc <all_rows_off+0x3c>)
|
|
800059e: 687b ldr r3, [r7, #4]
|
|
80005a0: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
80005a4: 4a09 ldr r2, [pc, #36] @ (80005cc <all_rows_off+0x3c>)
|
|
80005a6: 687b ldr r3, [r7, #4]
|
|
80005a8: 00db lsls r3, r3, #3
|
|
80005aa: 4413 add r3, r2
|
|
80005ac: 889b ldrh r3, [r3, #4]
|
|
80005ae: 2201 movs r2, #1
|
|
80005b0: 4619 mov r1, r3
|
|
80005b2: f001 fcd5 bl 8001f60 <HAL_GPIO_WritePin>
|
|
for (int i = 0; i < ROWS; i++)
|
|
80005b6: 687b ldr r3, [r7, #4]
|
|
80005b8: 3301 adds r3, #1
|
|
80005ba: 607b str r3, [r7, #4]
|
|
80005bc: 687b ldr r3, [r7, #4]
|
|
80005be: 2b06 cmp r3, #6
|
|
80005c0: ddec ble.n 800059c <all_rows_off+0xc>
|
|
}
|
|
80005c2: bf00 nop
|
|
80005c4: bf00 nop
|
|
80005c6: 3708 adds r7, #8
|
|
80005c8: 46bd mov sp, r7
|
|
80005ca: bd80 pop {r7, pc}
|
|
80005cc: 08005814 .word 0x08005814
|
|
|
|
080005d0 <display_refresh>:
|
|
|
|
static void display_refresh(void)
|
|
{
|
|
80005d0: b580 push {r7, lr}
|
|
80005d2: b082 sub sp, #8
|
|
80005d4: af00 add r7, sp, #0
|
|
for (int row = 0; row < ROWS; row++) {
|
|
80005d6: 2300 movs r3, #0
|
|
80005d8: 607b str r3, [r7, #4]
|
|
80005da: e022 b.n 8000622 <display_refresh+0x52>
|
|
all_rows_off();
|
|
80005dc: f7ff ffd8 bl 8000590 <all_rows_off>
|
|
HAL_SPI_Transmit(&hspi1, fb[row], NUM_CHIPS, HAL_MAX_DELAY);
|
|
80005e0: 687a ldr r2, [r7, #4]
|
|
80005e2: 4613 mov r3, r2
|
|
80005e4: 005b lsls r3, r3, #1
|
|
80005e6: 4413 add r3, r2
|
|
80005e8: 009b lsls r3, r3, #2
|
|
80005ea: 4a12 ldr r2, [pc, #72] @ (8000634 <display_refresh+0x64>)
|
|
80005ec: 1899 adds r1, r3, r2
|
|
80005ee: f04f 33ff mov.w r3, #4294967295
|
|
80005f2: 220c movs r2, #12
|
|
80005f4: 4810 ldr r0, [pc, #64] @ (8000638 <display_refresh+0x68>)
|
|
80005f6: f002 fd48 bl 800308a <HAL_SPI_Transmit>
|
|
HAL_GPIO_WritePin(ROW_PINS[row].port, ROW_PINS[row].pin, GPIO_PIN_RESET);
|
|
80005fa: 4a10 ldr r2, [pc, #64] @ (800063c <display_refresh+0x6c>)
|
|
80005fc: 687b ldr r3, [r7, #4]
|
|
80005fe: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8000602: 4a0e ldr r2, [pc, #56] @ (800063c <display_refresh+0x6c>)
|
|
8000604: 687b ldr r3, [r7, #4]
|
|
8000606: 00db lsls r3, r3, #3
|
|
8000608: 4413 add r3, r2
|
|
800060a: 889b ldrh r3, [r3, #4]
|
|
800060c: 2200 movs r2, #0
|
|
800060e: 4619 mov r1, r3
|
|
8000610: f001 fca6 bl 8001f60 <HAL_GPIO_WritePin>
|
|
delay_us(ROW_DWELL);
|
|
8000614: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8000618: f7ff ff94 bl 8000544 <delay_us>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
800061c: 687b ldr r3, [r7, #4]
|
|
800061e: 3301 adds r3, #1
|
|
8000620: 607b str r3, [r7, #4]
|
|
8000622: 687b ldr r3, [r7, #4]
|
|
8000624: 2b06 cmp r3, #6
|
|
8000626: ddd9 ble.n 80005dc <display_refresh+0xc>
|
|
}
|
|
all_rows_off();
|
|
8000628: f7ff ffb2 bl 8000590 <all_rows_off>
|
|
}
|
|
800062c: bf00 nop
|
|
800062e: 3708 adds r7, #8
|
|
8000630: 46bd mov sp, r7
|
|
8000632: bd80 pop {r7, pc}
|
|
8000634: 2000012c .word 0x2000012c
|
|
8000638: 20000034 .word 0x20000034
|
|
800063c: 08005814 .word 0x08005814
|
|
|
|
08000640 <refresh_for>:
|
|
|
|
static void refresh_for(uint32_t ms)
|
|
{
|
|
8000640: b580 push {r7, lr}
|
|
8000642: b084 sub sp, #16
|
|
8000644: af00 add r7, sp, #0
|
|
8000646: 6078 str r0, [r7, #4]
|
|
uint32_t t = HAL_GetTick();
|
|
8000648: f001 f91e bl 8001888 <HAL_GetTick>
|
|
800064c: 60f8 str r0, [r7, #12]
|
|
while ((HAL_GetTick() - t) < ms) { display_refresh(); }
|
|
800064e: e001 b.n 8000654 <refresh_for+0x14>
|
|
8000650: f7ff ffbe bl 80005d0 <display_refresh>
|
|
8000654: f001 f918 bl 8001888 <HAL_GetTick>
|
|
8000658: 4602 mov r2, r0
|
|
800065a: 68fb ldr r3, [r7, #12]
|
|
800065c: 1ad3 subs r3, r2, r3
|
|
800065e: 687a ldr r2, [r7, #4]
|
|
8000660: 429a cmp r2, r3
|
|
8000662: d8f5 bhi.n 8000650 <refresh_for+0x10>
|
|
}
|
|
8000664: bf00 nop
|
|
8000666: bf00 nop
|
|
8000668: 3710 adds r7, #16
|
|
800066a: 46bd mov sp, r7
|
|
800066c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08000670 <check_new_cmd>:
|
|
|
|
/* ── Check if a new command arrived — call from long-running loops ── */
|
|
static uint8_t check_new_cmd(void)
|
|
{
|
|
8000670: b480 push {r7}
|
|
8000672: af00 add r7, sp, #0
|
|
return pending_cmd_rdy;
|
|
8000674: 4b03 ldr r3, [pc, #12] @ (8000684 <check_new_cmd+0x14>)
|
|
8000676: 781b ldrb r3, [r3, #0]
|
|
8000678: b2db uxtb r3, r3
|
|
}
|
|
800067a: 4618 mov r0, r3
|
|
800067c: 46bd mov sp, r7
|
|
800067e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000682: 4770 bx lr
|
|
8000684: 20001013 .word 0x20001013
|
|
|
|
08000688 <fb_set_pixel>:
|
|
/* ════════════════════════════════════════════════
|
|
Framebuffer helpers
|
|
════════════════════════════════════════════════ */
|
|
|
|
static void fb_set_pixel(int col, int row, uint8_t on)
|
|
{
|
|
8000688: b480 push {r7}
|
|
800068a: b087 sub sp, #28
|
|
800068c: af00 add r7, sp, #0
|
|
800068e: 60f8 str r0, [r7, #12]
|
|
8000690: 60b9 str r1, [r7, #8]
|
|
8000692: 4613 mov r3, r2
|
|
8000694: 71fb strb r3, [r7, #7]
|
|
if (col < 0 || col >= COLS || row < 0 || row >= ROWS) return;
|
|
8000696: 68fb ldr r3, [r7, #12]
|
|
8000698: 2b00 cmp r3, #0
|
|
800069a: db5a blt.n 8000752 <fb_set_pixel+0xca>
|
|
800069c: 68fb ldr r3, [r7, #12]
|
|
800069e: 2b5f cmp r3, #95 @ 0x5f
|
|
80006a0: dc57 bgt.n 8000752 <fb_set_pixel+0xca>
|
|
80006a2: 68bb ldr r3, [r7, #8]
|
|
80006a4: 2b00 cmp r3, #0
|
|
80006a6: db54 blt.n 8000752 <fb_set_pixel+0xca>
|
|
80006a8: 68bb ldr r3, [r7, #8]
|
|
80006aa: 2b06 cmp r3, #6
|
|
80006ac: dc51 bgt.n 8000752 <fb_set_pixel+0xca>
|
|
int chip = col / 8;
|
|
80006ae: 68fb ldr r3, [r7, #12]
|
|
80006b0: 2b00 cmp r3, #0
|
|
80006b2: da00 bge.n 80006b6 <fb_set_pixel+0x2e>
|
|
80006b4: 3307 adds r3, #7
|
|
80006b6: 10db asrs r3, r3, #3
|
|
80006b8: 617b str r3, [r7, #20]
|
|
int bit = 7 - (col % 8);
|
|
80006ba: 68fb ldr r3, [r7, #12]
|
|
80006bc: 425a negs r2, r3
|
|
80006be: f003 0307 and.w r3, r3, #7
|
|
80006c2: f002 0207 and.w r2, r2, #7
|
|
80006c6: bf58 it pl
|
|
80006c8: 4253 negpl r3, r2
|
|
80006ca: f1c3 0307 rsb r3, r3, #7
|
|
80006ce: 613b str r3, [r7, #16]
|
|
if (on) fb[row][chip] |= (uint8_t)(1 << bit);
|
|
80006d0: 79fb ldrb r3, [r7, #7]
|
|
80006d2: 2b00 cmp r3, #0
|
|
80006d4: d01c beq.n 8000710 <fb_set_pixel+0x88>
|
|
80006d6: 4922 ldr r1, [pc, #136] @ (8000760 <fb_set_pixel+0xd8>)
|
|
80006d8: 68ba ldr r2, [r7, #8]
|
|
80006da: 4613 mov r3, r2
|
|
80006dc: 005b lsls r3, r3, #1
|
|
80006de: 4413 add r3, r2
|
|
80006e0: 009b lsls r3, r3, #2
|
|
80006e2: 18ca adds r2, r1, r3
|
|
80006e4: 697b ldr r3, [r7, #20]
|
|
80006e6: 4413 add r3, r2
|
|
80006e8: 781a ldrb r2, [r3, #0]
|
|
80006ea: 2101 movs r1, #1
|
|
80006ec: 693b ldr r3, [r7, #16]
|
|
80006ee: fa01 f303 lsl.w r3, r1, r3
|
|
80006f2: b2db uxtb r3, r3
|
|
80006f4: 4313 orrs r3, r2
|
|
80006f6: b2d8 uxtb r0, r3
|
|
80006f8: 4919 ldr r1, [pc, #100] @ (8000760 <fb_set_pixel+0xd8>)
|
|
80006fa: 68ba ldr r2, [r7, #8]
|
|
80006fc: 4613 mov r3, r2
|
|
80006fe: 005b lsls r3, r3, #1
|
|
8000700: 4413 add r3, r2
|
|
8000702: 009b lsls r3, r3, #2
|
|
8000704: 18ca adds r2, r1, r3
|
|
8000706: 697b ldr r3, [r7, #20]
|
|
8000708: 4413 add r3, r2
|
|
800070a: 4602 mov r2, r0
|
|
800070c: 701a strb r2, [r3, #0]
|
|
800070e: e021 b.n 8000754 <fb_set_pixel+0xcc>
|
|
else fb[row][chip] &= ~(uint8_t)(1 << bit);
|
|
8000710: 4913 ldr r1, [pc, #76] @ (8000760 <fb_set_pixel+0xd8>)
|
|
8000712: 68ba ldr r2, [r7, #8]
|
|
8000714: 4613 mov r3, r2
|
|
8000716: 005b lsls r3, r3, #1
|
|
8000718: 4413 add r3, r2
|
|
800071a: 009b lsls r3, r3, #2
|
|
800071c: 18ca adds r2, r1, r3
|
|
800071e: 697b ldr r3, [r7, #20]
|
|
8000720: 4413 add r3, r2
|
|
8000722: 781b ldrb r3, [r3, #0]
|
|
8000724: b25a sxtb r2, r3
|
|
8000726: 2101 movs r1, #1
|
|
8000728: 693b ldr r3, [r7, #16]
|
|
800072a: fa01 f303 lsl.w r3, r1, r3
|
|
800072e: b25b sxtb r3, r3
|
|
8000730: 43db mvns r3, r3
|
|
8000732: b25b sxtb r3, r3
|
|
8000734: 4013 ands r3, r2
|
|
8000736: b25b sxtb r3, r3
|
|
8000738: b2d8 uxtb r0, r3
|
|
800073a: 4909 ldr r1, [pc, #36] @ (8000760 <fb_set_pixel+0xd8>)
|
|
800073c: 68ba ldr r2, [r7, #8]
|
|
800073e: 4613 mov r3, r2
|
|
8000740: 005b lsls r3, r3, #1
|
|
8000742: 4413 add r3, r2
|
|
8000744: 009b lsls r3, r3, #2
|
|
8000746: 18ca adds r2, r1, r3
|
|
8000748: 697b ldr r3, [r7, #20]
|
|
800074a: 4413 add r3, r2
|
|
800074c: 4602 mov r2, r0
|
|
800074e: 701a strb r2, [r3, #0]
|
|
8000750: e000 b.n 8000754 <fb_set_pixel+0xcc>
|
|
if (col < 0 || col >= COLS || row < 0 || row >= ROWS) return;
|
|
8000752: bf00 nop
|
|
}
|
|
8000754: 371c adds r7, #28
|
|
8000756: 46bd mov sp, r7
|
|
8000758: f85d 7b04 ldr.w r7, [sp], #4
|
|
800075c: 4770 bx lr
|
|
800075e: bf00 nop
|
|
8000760: 2000012c .word 0x2000012c
|
|
|
|
08000764 <render_logo>:
|
|
|
|
static void render_logo(int star_col, int text_col, int mask_col)
|
|
{
|
|
8000764: b580 push {r7, lr}
|
|
8000766: b08a sub sp, #40 @ 0x28
|
|
8000768: af00 add r7, sp, #0
|
|
800076a: 60f8 str r0, [r7, #12]
|
|
800076c: 60b9 str r1, [r7, #8]
|
|
800076e: 607a str r2, [r7, #4]
|
|
memset(fb, 0, sizeof(fb));
|
|
8000770: 2254 movs r2, #84 @ 0x54
|
|
8000772: 2100 movs r1, #0
|
|
8000774: 482d ldr r0, [pc, #180] @ (800082c <render_logo+0xc8>)
|
|
8000776: f004 ffeb bl 8005750 <memset>
|
|
for (int row = 0; row < 7; row++) {
|
|
800077a: 2300 movs r3, #0
|
|
800077c: 627b str r3, [r7, #36] @ 0x24
|
|
800077e: e04d b.n 800081c <render_logo+0xb8>
|
|
for (int sc = 0; sc < 11; sc++) {
|
|
8000780: 2300 movs r3, #0
|
|
8000782: 623b str r3, [r7, #32]
|
|
8000784: e01f b.n 80007c6 <render_logo+0x62>
|
|
int col = star_col + sc;
|
|
8000786: 68fa ldr r2, [r7, #12]
|
|
8000788: 6a3b ldr r3, [r7, #32]
|
|
800078a: 4413 add r3, r2
|
|
800078c: 617b str r3, [r7, #20]
|
|
if (STAR[row][sc] && (mask_col < 0 || col >= mask_col))
|
|
800078e: 4928 ldr r1, [pc, #160] @ (8000830 <render_logo+0xcc>)
|
|
8000790: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8000792: 4613 mov r3, r2
|
|
8000794: 009b lsls r3, r3, #2
|
|
8000796: 4413 add r3, r2
|
|
8000798: 005b lsls r3, r3, #1
|
|
800079a: 4413 add r3, r2
|
|
800079c: 18ca adds r2, r1, r3
|
|
800079e: 6a3b ldr r3, [r7, #32]
|
|
80007a0: 4413 add r3, r2
|
|
80007a2: 781b ldrb r3, [r3, #0]
|
|
80007a4: 2b00 cmp r3, #0
|
|
80007a6: d00b beq.n 80007c0 <render_logo+0x5c>
|
|
80007a8: 687b ldr r3, [r7, #4]
|
|
80007aa: 2b00 cmp r3, #0
|
|
80007ac: db03 blt.n 80007b6 <render_logo+0x52>
|
|
80007ae: 697a ldr r2, [r7, #20]
|
|
80007b0: 687b ldr r3, [r7, #4]
|
|
80007b2: 429a cmp r2, r3
|
|
80007b4: db04 blt.n 80007c0 <render_logo+0x5c>
|
|
fb_set_pixel(col, row, 1);
|
|
80007b6: 2201 movs r2, #1
|
|
80007b8: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80007ba: 6978 ldr r0, [r7, #20]
|
|
80007bc: f7ff ff64 bl 8000688 <fb_set_pixel>
|
|
for (int sc = 0; sc < 11; sc++) {
|
|
80007c0: 6a3b ldr r3, [r7, #32]
|
|
80007c2: 3301 adds r3, #1
|
|
80007c4: 623b str r3, [r7, #32]
|
|
80007c6: 6a3b ldr r3, [r7, #32]
|
|
80007c8: 2b0a cmp r3, #10
|
|
80007ca: dddc ble.n 8000786 <render_logo+0x22>
|
|
}
|
|
for (int tc = 0; tc < 36; tc++) {
|
|
80007cc: 2300 movs r3, #0
|
|
80007ce: 61fb str r3, [r7, #28]
|
|
80007d0: e01e b.n 8000810 <render_logo+0xac>
|
|
int col = text_col + tc;
|
|
80007d2: 68ba ldr r2, [r7, #8]
|
|
80007d4: 69fb ldr r3, [r7, #28]
|
|
80007d6: 4413 add r3, r2
|
|
80007d8: 61bb str r3, [r7, #24]
|
|
if (ARRIVE_GLYPH[row][tc] && (mask_col < 0 || col >= mask_col))
|
|
80007da: 4916 ldr r1, [pc, #88] @ (8000834 <render_logo+0xd0>)
|
|
80007dc: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80007de: 4613 mov r3, r2
|
|
80007e0: 00db lsls r3, r3, #3
|
|
80007e2: 4413 add r3, r2
|
|
80007e4: 009b lsls r3, r3, #2
|
|
80007e6: 18ca adds r2, r1, r3
|
|
80007e8: 69fb ldr r3, [r7, #28]
|
|
80007ea: 4413 add r3, r2
|
|
80007ec: 781b ldrb r3, [r3, #0]
|
|
80007ee: 2b00 cmp r3, #0
|
|
80007f0: d00b beq.n 800080a <render_logo+0xa6>
|
|
80007f2: 687b ldr r3, [r7, #4]
|
|
80007f4: 2b00 cmp r3, #0
|
|
80007f6: db03 blt.n 8000800 <render_logo+0x9c>
|
|
80007f8: 69ba ldr r2, [r7, #24]
|
|
80007fa: 687b ldr r3, [r7, #4]
|
|
80007fc: 429a cmp r2, r3
|
|
80007fe: db04 blt.n 800080a <render_logo+0xa6>
|
|
fb_set_pixel(col, row, 1);
|
|
8000800: 2201 movs r2, #1
|
|
8000802: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8000804: 69b8 ldr r0, [r7, #24]
|
|
8000806: f7ff ff3f bl 8000688 <fb_set_pixel>
|
|
for (int tc = 0; tc < 36; tc++) {
|
|
800080a: 69fb ldr r3, [r7, #28]
|
|
800080c: 3301 adds r3, #1
|
|
800080e: 61fb str r3, [r7, #28]
|
|
8000810: 69fb ldr r3, [r7, #28]
|
|
8000812: 2b23 cmp r3, #35 @ 0x23
|
|
8000814: dddd ble.n 80007d2 <render_logo+0x6e>
|
|
for (int row = 0; row < 7; row++) {
|
|
8000816: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8000818: 3301 adds r3, #1
|
|
800081a: 627b str r3, [r7, #36] @ 0x24
|
|
800081c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800081e: 2b06 cmp r3, #6
|
|
8000820: ddae ble.n 8000780 <render_logo+0x1c>
|
|
}
|
|
}
|
|
}
|
|
8000822: bf00 nop
|
|
8000824: bf00 nop
|
|
8000826: 3728 adds r7, #40 @ 0x28
|
|
8000828: 46bd mov sp, r7
|
|
800082a: bd80 pop {r7, pc}
|
|
800082c: 2000012c .word 0x2000012c
|
|
8000830: 08005974 .word 0x08005974
|
|
8000834: 080059c4 .word 0x080059c4
|
|
|
|
08000838 <render_logo_rows>:
|
|
|
|
static void render_logo_rows(int star_col, int text_col, uint8_t row_mask)
|
|
{
|
|
8000838: b580 push {r7, lr}
|
|
800083a: b08a sub sp, #40 @ 0x28
|
|
800083c: af00 add r7, sp, #0
|
|
800083e: 60f8 str r0, [r7, #12]
|
|
8000840: 60b9 str r1, [r7, #8]
|
|
8000842: 4613 mov r3, r2
|
|
8000844: 71fb strb r3, [r7, #7]
|
|
memset(fb, 0, sizeof(fb));
|
|
8000846: 2254 movs r2, #84 @ 0x54
|
|
8000848: 2100 movs r1, #0
|
|
800084a: 482c ldr r0, [pc, #176] @ (80008fc <render_logo_rows+0xc4>)
|
|
800084c: f004 ff80 bl 8005750 <memset>
|
|
for (int row = 0; row < 7; row++) {
|
|
8000850: 2300 movs r3, #0
|
|
8000852: 627b str r3, [r7, #36] @ 0x24
|
|
8000854: e049 b.n 80008ea <render_logo_rows+0xb2>
|
|
if (!(row_mask & (1 << row))) continue;
|
|
8000856: 79fa ldrb r2, [r7, #7]
|
|
8000858: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800085a: fa42 f303 asr.w r3, r2, r3
|
|
800085e: f003 0301 and.w r3, r3, #1
|
|
8000862: 2b00 cmp r3, #0
|
|
8000864: d03d beq.n 80008e2 <render_logo_rows+0xaa>
|
|
for (int sc = 0; sc < 11; sc++) {
|
|
8000866: 2300 movs r3, #0
|
|
8000868: 623b str r3, [r7, #32]
|
|
800086a: e018 b.n 800089e <render_logo_rows+0x66>
|
|
int col = star_col + sc;
|
|
800086c: 68fa ldr r2, [r7, #12]
|
|
800086e: 6a3b ldr r3, [r7, #32]
|
|
8000870: 4413 add r3, r2
|
|
8000872: 617b str r3, [r7, #20]
|
|
if (STAR[row][sc]) fb_set_pixel(col, row, 1);
|
|
8000874: 4922 ldr r1, [pc, #136] @ (8000900 <render_logo_rows+0xc8>)
|
|
8000876: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
8000878: 4613 mov r3, r2
|
|
800087a: 009b lsls r3, r3, #2
|
|
800087c: 4413 add r3, r2
|
|
800087e: 005b lsls r3, r3, #1
|
|
8000880: 4413 add r3, r2
|
|
8000882: 18ca adds r2, r1, r3
|
|
8000884: 6a3b ldr r3, [r7, #32]
|
|
8000886: 4413 add r3, r2
|
|
8000888: 781b ldrb r3, [r3, #0]
|
|
800088a: 2b00 cmp r3, #0
|
|
800088c: d004 beq.n 8000898 <render_logo_rows+0x60>
|
|
800088e: 2201 movs r2, #1
|
|
8000890: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
8000892: 6978 ldr r0, [r7, #20]
|
|
8000894: f7ff fef8 bl 8000688 <fb_set_pixel>
|
|
for (int sc = 0; sc < 11; sc++) {
|
|
8000898: 6a3b ldr r3, [r7, #32]
|
|
800089a: 3301 adds r3, #1
|
|
800089c: 623b str r3, [r7, #32]
|
|
800089e: 6a3b ldr r3, [r7, #32]
|
|
80008a0: 2b0a cmp r3, #10
|
|
80008a2: dde3 ble.n 800086c <render_logo_rows+0x34>
|
|
}
|
|
for (int tc = 0; tc < 36; tc++) {
|
|
80008a4: 2300 movs r3, #0
|
|
80008a6: 61fb str r3, [r7, #28]
|
|
80008a8: e017 b.n 80008da <render_logo_rows+0xa2>
|
|
int col = text_col + tc;
|
|
80008aa: 68ba ldr r2, [r7, #8]
|
|
80008ac: 69fb ldr r3, [r7, #28]
|
|
80008ae: 4413 add r3, r2
|
|
80008b0: 61bb str r3, [r7, #24]
|
|
if (ARRIVE_GLYPH[row][tc]) fb_set_pixel(col, row, 1);
|
|
80008b2: 4914 ldr r1, [pc, #80] @ (8000904 <render_logo_rows+0xcc>)
|
|
80008b4: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80008b6: 4613 mov r3, r2
|
|
80008b8: 00db lsls r3, r3, #3
|
|
80008ba: 4413 add r3, r2
|
|
80008bc: 009b lsls r3, r3, #2
|
|
80008be: 18ca adds r2, r1, r3
|
|
80008c0: 69fb ldr r3, [r7, #28]
|
|
80008c2: 4413 add r3, r2
|
|
80008c4: 781b ldrb r3, [r3, #0]
|
|
80008c6: 2b00 cmp r3, #0
|
|
80008c8: d004 beq.n 80008d4 <render_logo_rows+0x9c>
|
|
80008ca: 2201 movs r2, #1
|
|
80008cc: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80008ce: 69b8 ldr r0, [r7, #24]
|
|
80008d0: f7ff feda bl 8000688 <fb_set_pixel>
|
|
for (int tc = 0; tc < 36; tc++) {
|
|
80008d4: 69fb ldr r3, [r7, #28]
|
|
80008d6: 3301 adds r3, #1
|
|
80008d8: 61fb str r3, [r7, #28]
|
|
80008da: 69fb ldr r3, [r7, #28]
|
|
80008dc: 2b23 cmp r3, #35 @ 0x23
|
|
80008de: dde4 ble.n 80008aa <render_logo_rows+0x72>
|
|
80008e0: e000 b.n 80008e4 <render_logo_rows+0xac>
|
|
if (!(row_mask & (1 << row))) continue;
|
|
80008e2: bf00 nop
|
|
for (int row = 0; row < 7; row++) {
|
|
80008e4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80008e6: 3301 adds r3, #1
|
|
80008e8: 627b str r3, [r7, #36] @ 0x24
|
|
80008ea: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80008ec: 2b06 cmp r3, #6
|
|
80008ee: ddb2 ble.n 8000856 <render_logo_rows+0x1e>
|
|
}
|
|
}
|
|
}
|
|
80008f0: bf00 nop
|
|
80008f2: bf00 nop
|
|
80008f4: 3728 adds r7, #40 @ 0x28
|
|
80008f6: 46bd mov sp, r7
|
|
80008f8: bd80 pop {r7, pc}
|
|
80008fa: bf00 nop
|
|
80008fc: 2000012c .word 0x2000012c
|
|
8000900: 08005974 .word 0x08005974
|
|
8000904: 080059c4 .word 0x080059c4
|
|
|
|
08000908 <render_text_to_fb>:
|
|
|
|
/* ── Draw text string into fb at given x offset, return end col ── */
|
|
static int render_text_to_fb(const char *txt, int x_offset)
|
|
{
|
|
8000908: b580 push {r7, lr}
|
|
800090a: b088 sub sp, #32
|
|
800090c: af00 add r7, sp, #0
|
|
800090e: 6078 str r0, [r7, #4]
|
|
8000910: 6039 str r1, [r7, #0]
|
|
int col = x_offset;
|
|
8000912: 683b ldr r3, [r7, #0]
|
|
8000914: 61fb str r3, [r7, #28]
|
|
while (*txt) {
|
|
8000916: e045 b.n 80009a4 <render_text_to_fb+0x9c>
|
|
uint8_t c = (uint8_t)*txt++;
|
|
8000918: 687b ldr r3, [r7, #4]
|
|
800091a: 1c5a adds r2, r3, #1
|
|
800091c: 607a str r2, [r7, #4]
|
|
800091e: 781b ldrb r3, [r3, #0]
|
|
8000920: 76fb strb r3, [r7, #27]
|
|
if (c >= 'a' && c <= 'z') c -= 32;
|
|
8000922: 7efb ldrb r3, [r7, #27]
|
|
8000924: 2b60 cmp r3, #96 @ 0x60
|
|
8000926: d905 bls.n 8000934 <render_text_to_fb+0x2c>
|
|
8000928: 7efb ldrb r3, [r7, #27]
|
|
800092a: 2b7a cmp r3, #122 @ 0x7a
|
|
800092c: d802 bhi.n 8000934 <render_text_to_fb+0x2c>
|
|
800092e: 7efb ldrb r3, [r7, #27]
|
|
8000930: 3b20 subs r3, #32
|
|
8000932: 76fb strb r3, [r7, #27]
|
|
if (c >= 32 && c <= 90) {
|
|
8000934: 7efb ldrb r3, [r7, #27]
|
|
8000936: 2b1f cmp r3, #31
|
|
8000938: d931 bls.n 800099e <render_text_to_fb+0x96>
|
|
800093a: 7efb ldrb r3, [r7, #27]
|
|
800093c: 2b5a cmp r3, #90 @ 0x5a
|
|
800093e: d82e bhi.n 800099e <render_text_to_fb+0x96>
|
|
const uint8_t *g = FONT[c - 32];
|
|
8000940: 7efb ldrb r3, [r7, #27]
|
|
8000942: f1a3 0220 sub.w r2, r3, #32
|
|
8000946: 4613 mov r3, r2
|
|
8000948: 009b lsls r3, r3, #2
|
|
800094a: 4413 add r3, r2
|
|
800094c: 4a1a ldr r2, [pc, #104] @ (80009b8 <render_text_to_fb+0xb0>)
|
|
800094e: 4413 add r3, r2
|
|
8000950: 60fb str r3, [r7, #12]
|
|
for (int i = 0; i < 5; i++, col++) {
|
|
8000952: 2300 movs r3, #0
|
|
8000954: 617b str r3, [r7, #20]
|
|
8000956: e01f b.n 8000998 <render_text_to_fb+0x90>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000958: 2300 movs r3, #0
|
|
800095a: 613b str r3, [r7, #16]
|
|
800095c: e013 b.n 8000986 <render_text_to_fb+0x7e>
|
|
if (g[i] & (1 << row)) fb_set_pixel(col, row, 1);
|
|
800095e: 697b ldr r3, [r7, #20]
|
|
8000960: 68fa ldr r2, [r7, #12]
|
|
8000962: 4413 add r3, r2
|
|
8000964: 781b ldrb r3, [r3, #0]
|
|
8000966: 461a mov r2, r3
|
|
8000968: 693b ldr r3, [r7, #16]
|
|
800096a: fa42 f303 asr.w r3, r2, r3
|
|
800096e: f003 0301 and.w r3, r3, #1
|
|
8000972: 2b00 cmp r3, #0
|
|
8000974: d004 beq.n 8000980 <render_text_to_fb+0x78>
|
|
8000976: 2201 movs r2, #1
|
|
8000978: 6939 ldr r1, [r7, #16]
|
|
800097a: 69f8 ldr r0, [r7, #28]
|
|
800097c: f7ff fe84 bl 8000688 <fb_set_pixel>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000980: 693b ldr r3, [r7, #16]
|
|
8000982: 3301 adds r3, #1
|
|
8000984: 613b str r3, [r7, #16]
|
|
8000986: 693b ldr r3, [r7, #16]
|
|
8000988: 2b06 cmp r3, #6
|
|
800098a: dde8 ble.n 800095e <render_text_to_fb+0x56>
|
|
for (int i = 0; i < 5; i++, col++) {
|
|
800098c: 697b ldr r3, [r7, #20]
|
|
800098e: 3301 adds r3, #1
|
|
8000990: 617b str r3, [r7, #20]
|
|
8000992: 69fb ldr r3, [r7, #28]
|
|
8000994: 3301 adds r3, #1
|
|
8000996: 61fb str r3, [r7, #28]
|
|
8000998: 697b ldr r3, [r7, #20]
|
|
800099a: 2b04 cmp r3, #4
|
|
800099c: dddc ble.n 8000958 <render_text_to_fb+0x50>
|
|
}
|
|
}
|
|
}
|
|
col++;
|
|
800099e: 69fb ldr r3, [r7, #28]
|
|
80009a0: 3301 adds r3, #1
|
|
80009a2: 61fb str r3, [r7, #28]
|
|
while (*txt) {
|
|
80009a4: 687b ldr r3, [r7, #4]
|
|
80009a6: 781b ldrb r3, [r3, #0]
|
|
80009a8: 2b00 cmp r3, #0
|
|
80009aa: d1b5 bne.n 8000918 <render_text_to_fb+0x10>
|
|
}
|
|
return col;
|
|
80009ac: 69fb ldr r3, [r7, #28]
|
|
}
|
|
80009ae: 4618 mov r0, r3
|
|
80009b0: 3720 adds r7, #32
|
|
80009b2: 46bd mov sp, r7
|
|
80009b4: bd80 pop {r7, pc}
|
|
80009b6: bf00 nop
|
|
80009b8: 0800584c .word 0x0800584c
|
|
|
|
080009bc <render_centred_text>:
|
|
|
|
/* ── Render text centred on display ── */
|
|
static void render_centred_text(const char *txt)
|
|
{
|
|
80009bc: b580 push {r7, lr}
|
|
80009be: b086 sub sp, #24
|
|
80009c0: af00 add r7, sp, #0
|
|
80009c2: 6078 str r0, [r7, #4]
|
|
int len = 0;
|
|
80009c4: 2300 movs r3, #0
|
|
80009c6: 617b str r3, [r7, #20]
|
|
const char *p = txt;
|
|
80009c8: 687b ldr r3, [r7, #4]
|
|
80009ca: 613b str r3, [r7, #16]
|
|
while (*p++) len++;
|
|
80009cc: e002 b.n 80009d4 <render_centred_text+0x18>
|
|
80009ce: 697b ldr r3, [r7, #20]
|
|
80009d0: 3301 adds r3, #1
|
|
80009d2: 617b str r3, [r7, #20]
|
|
80009d4: 693b ldr r3, [r7, #16]
|
|
80009d6: 1c5a adds r2, r3, #1
|
|
80009d8: 613a str r2, [r7, #16]
|
|
80009da: 781b ldrb r3, [r3, #0]
|
|
80009dc: 2b00 cmp r3, #0
|
|
80009de: d1f6 bne.n 80009ce <render_centred_text+0x12>
|
|
int text_width = len * 6 - 1;
|
|
80009e0: 697a ldr r2, [r7, #20]
|
|
80009e2: 4613 mov r3, r2
|
|
80009e4: 005b lsls r3, r3, #1
|
|
80009e6: 4413 add r3, r2
|
|
80009e8: 005b lsls r3, r3, #1
|
|
80009ea: 3b01 subs r3, #1
|
|
80009ec: 60fb str r3, [r7, #12]
|
|
int x = (COLS - text_width) / 2;
|
|
80009ee: 68fb ldr r3, [r7, #12]
|
|
80009f0: f1c3 0360 rsb r3, r3, #96 @ 0x60
|
|
80009f4: 0fda lsrs r2, r3, #31
|
|
80009f6: 4413 add r3, r2
|
|
80009f8: 105b asrs r3, r3, #1
|
|
80009fa: 60bb str r3, [r7, #8]
|
|
memset(fb, 0, sizeof(fb));
|
|
80009fc: 2254 movs r2, #84 @ 0x54
|
|
80009fe: 2100 movs r1, #0
|
|
8000a00: 4805 ldr r0, [pc, #20] @ (8000a18 <render_centred_text+0x5c>)
|
|
8000a02: f004 fea5 bl 8005750 <memset>
|
|
render_text_to_fb(txt, x);
|
|
8000a06: 68b9 ldr r1, [r7, #8]
|
|
8000a08: 6878 ldr r0, [r7, #4]
|
|
8000a0a: f7ff ff7d bl 8000908 <render_text_to_fb>
|
|
}
|
|
8000a0e: bf00 nop
|
|
8000a10: 3718 adds r7, #24
|
|
8000a12: 46bd mov sp, r7
|
|
8000a14: bd80 pop {r7, pc}
|
|
8000a16: bf00 nop
|
|
8000a18: 2000012c .word 0x2000012c
|
|
|
|
08000a1c <render_scroll>:
|
|
|
|
/* ── Render word into wide[] for scrolling, returns total width ── */
|
|
static uint16_t render_scroll(const char *txt, int x_start)
|
|
{
|
|
8000a1c: b580 push {r7, lr}
|
|
8000a1e: b088 sub sp, #32
|
|
8000a20: af00 add r7, sp, #0
|
|
8000a22: 6078 str r0, [r7, #4]
|
|
8000a24: 6039 str r1, [r7, #0]
|
|
memset(wide, 0, sizeof(wide));
|
|
8000a26: f44f 6260 mov.w r2, #3584 @ 0xe00
|
|
8000a2a: 2100 movs r1, #0
|
|
8000a2c: 4831 ldr r0, [pc, #196] @ (8000af4 <render_scroll+0xd8>)
|
|
8000a2e: f004 fe8f bl 8005750 <memset>
|
|
int col = x_start;
|
|
8000a32: 683b ldr r3, [r7, #0]
|
|
8000a34: 61fb str r3, [r7, #28]
|
|
while (*txt && col < WIDE_COLS - 6) {
|
|
8000a36: e04c b.n 8000ad2 <render_scroll+0xb6>
|
|
uint8_t c = (uint8_t)*txt++;
|
|
8000a38: 687b ldr r3, [r7, #4]
|
|
8000a3a: 1c5a adds r2, r3, #1
|
|
8000a3c: 607a str r2, [r7, #4]
|
|
8000a3e: 781b ldrb r3, [r3, #0]
|
|
8000a40: 76fb strb r3, [r7, #27]
|
|
if (c >= 'a' && c <= 'z') c -= 32;
|
|
8000a42: 7efb ldrb r3, [r7, #27]
|
|
8000a44: 2b60 cmp r3, #96 @ 0x60
|
|
8000a46: d905 bls.n 8000a54 <render_scroll+0x38>
|
|
8000a48: 7efb ldrb r3, [r7, #27]
|
|
8000a4a: 2b7a cmp r3, #122 @ 0x7a
|
|
8000a4c: d802 bhi.n 8000a54 <render_scroll+0x38>
|
|
8000a4e: 7efb ldrb r3, [r7, #27]
|
|
8000a50: 3b20 subs r3, #32
|
|
8000a52: 76fb strb r3, [r7, #27]
|
|
if (c >= 32 && c <= 90) {
|
|
8000a54: 7efb ldrb r3, [r7, #27]
|
|
8000a56: 2b1f cmp r3, #31
|
|
8000a58: d938 bls.n 8000acc <render_scroll+0xb0>
|
|
8000a5a: 7efb ldrb r3, [r7, #27]
|
|
8000a5c: 2b5a cmp r3, #90 @ 0x5a
|
|
8000a5e: d835 bhi.n 8000acc <render_scroll+0xb0>
|
|
const uint8_t *g = FONT[c - 32];
|
|
8000a60: 7efb ldrb r3, [r7, #27]
|
|
8000a62: f1a3 0220 sub.w r2, r3, #32
|
|
8000a66: 4613 mov r3, r2
|
|
8000a68: 009b lsls r3, r3, #2
|
|
8000a6a: 4413 add r3, r2
|
|
8000a6c: 4a22 ldr r2, [pc, #136] @ (8000af8 <render_scroll+0xdc>)
|
|
8000a6e: 4413 add r3, r2
|
|
8000a70: 60fb str r3, [r7, #12]
|
|
for (int i = 0; i < 5 && col < WIDE_COLS; i++, col++) {
|
|
8000a72: 2300 movs r3, #0
|
|
8000a74: 617b str r3, [r7, #20]
|
|
8000a76: e022 b.n 8000abe <render_scroll+0xa2>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000a78: 2300 movs r3, #0
|
|
8000a7a: 613b str r3, [r7, #16]
|
|
8000a7c: e016 b.n 8000aac <render_scroll+0x90>
|
|
if (g[i] & (1 << row)) wide[row][col] = 1;
|
|
8000a7e: 697b ldr r3, [r7, #20]
|
|
8000a80: 68fa ldr r2, [r7, #12]
|
|
8000a82: 4413 add r3, r2
|
|
8000a84: 781b ldrb r3, [r3, #0]
|
|
8000a86: 461a mov r2, r3
|
|
8000a88: 693b ldr r3, [r7, #16]
|
|
8000a8a: fa42 f303 asr.w r3, r2, r3
|
|
8000a8e: f003 0301 and.w r3, r3, #1
|
|
8000a92: 2b00 cmp r3, #0
|
|
8000a94: d007 beq.n 8000aa6 <render_scroll+0x8a>
|
|
8000a96: 4a17 ldr r2, [pc, #92] @ (8000af4 <render_scroll+0xd8>)
|
|
8000a98: 693b ldr r3, [r7, #16]
|
|
8000a9a: 025b lsls r3, r3, #9
|
|
8000a9c: 441a add r2, r3
|
|
8000a9e: 69fb ldr r3, [r7, #28]
|
|
8000aa0: 4413 add r3, r2
|
|
8000aa2: 2201 movs r2, #1
|
|
8000aa4: 701a strb r2, [r3, #0]
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000aa6: 693b ldr r3, [r7, #16]
|
|
8000aa8: 3301 adds r3, #1
|
|
8000aaa: 613b str r3, [r7, #16]
|
|
8000aac: 693b ldr r3, [r7, #16]
|
|
8000aae: 2b06 cmp r3, #6
|
|
8000ab0: dde5 ble.n 8000a7e <render_scroll+0x62>
|
|
for (int i = 0; i < 5 && col < WIDE_COLS; i++, col++) {
|
|
8000ab2: 697b ldr r3, [r7, #20]
|
|
8000ab4: 3301 adds r3, #1
|
|
8000ab6: 617b str r3, [r7, #20]
|
|
8000ab8: 69fb ldr r3, [r7, #28]
|
|
8000aba: 3301 adds r3, #1
|
|
8000abc: 61fb str r3, [r7, #28]
|
|
8000abe: 697b ldr r3, [r7, #20]
|
|
8000ac0: 2b04 cmp r3, #4
|
|
8000ac2: dc03 bgt.n 8000acc <render_scroll+0xb0>
|
|
8000ac4: 69fb ldr r3, [r7, #28]
|
|
8000ac6: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8000aca: dbd5 blt.n 8000a78 <render_scroll+0x5c>
|
|
}
|
|
}
|
|
}
|
|
col++;
|
|
8000acc: 69fb ldr r3, [r7, #28]
|
|
8000ace: 3301 adds r3, #1
|
|
8000ad0: 61fb str r3, [r7, #28]
|
|
while (*txt && col < WIDE_COLS - 6) {
|
|
8000ad2: 687b ldr r3, [r7, #4]
|
|
8000ad4: 781b ldrb r3, [r3, #0]
|
|
8000ad6: 2b00 cmp r3, #0
|
|
8000ad8: d003 beq.n 8000ae2 <render_scroll+0xc6>
|
|
8000ada: 69fb ldr r3, [r7, #28]
|
|
8000adc: f5b3 7ffd cmp.w r3, #506 @ 0x1fa
|
|
8000ae0: dbaa blt.n 8000a38 <render_scroll+0x1c>
|
|
}
|
|
return (uint16_t)(col + COLS);
|
|
8000ae2: 69fb ldr r3, [r7, #28]
|
|
8000ae4: b29b uxth r3, r3
|
|
8000ae6: 3360 adds r3, #96 @ 0x60
|
|
8000ae8: b29b uxth r3, r3
|
|
}
|
|
8000aea: 4618 mov r0, r3
|
|
8000aec: 3720 adds r7, #32
|
|
8000aee: 46bd mov sp, r7
|
|
8000af0: bd80 pop {r7, pc}
|
|
8000af2: bf00 nop
|
|
8000af4: 20000180 .word 0x20000180
|
|
8000af8: 0800584c .word 0x0800584c
|
|
|
|
08000afc <update_fb_from_scroll>:
|
|
|
|
static void update_fb_from_scroll(void)
|
|
{
|
|
8000afc: b580 push {r7, lr}
|
|
8000afe: b084 sub sp, #16
|
|
8000b00: af00 add r7, sp, #0
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000b02: 2300 movs r3, #0
|
|
8000b04: 60fb str r3, [r7, #12]
|
|
8000b06: e030 b.n 8000b6a <update_fb_from_scroll+0x6e>
|
|
memset(fb[row], 0, NUM_CHIPS);
|
|
8000b08: 68fa ldr r2, [r7, #12]
|
|
8000b0a: 4613 mov r3, r2
|
|
8000b0c: 005b lsls r3, r3, #1
|
|
8000b0e: 4413 add r3, r2
|
|
8000b10: 009b lsls r3, r3, #2
|
|
8000b12: 4a1a ldr r2, [pc, #104] @ (8000b7c <update_fb_from_scroll+0x80>)
|
|
8000b14: 4413 add r3, r2
|
|
8000b16: 220c movs r2, #12
|
|
8000b18: 2100 movs r1, #0
|
|
8000b1a: 4618 mov r0, r3
|
|
8000b1c: f004 fe18 bl 8005750 <memset>
|
|
for (int col = 0; col < COLS; col++) {
|
|
8000b20: 2300 movs r3, #0
|
|
8000b22: 60bb str r3, [r7, #8]
|
|
8000b24: e01b b.n 8000b5e <update_fb_from_scroll+0x62>
|
|
uint16_t src = (uint16_t)(scroll_x + col);
|
|
8000b26: 4b16 ldr r3, [pc, #88] @ (8000b80 <update_fb_from_scroll+0x84>)
|
|
8000b28: 681b ldr r3, [r3, #0]
|
|
8000b2a: b29a uxth r2, r3
|
|
8000b2c: 68bb ldr r3, [r7, #8]
|
|
8000b2e: b29b uxth r3, r3
|
|
8000b30: 4413 add r3, r2
|
|
8000b32: 80fb strh r3, [r7, #6]
|
|
if (src < WIDE_COLS && wide[row][src])
|
|
8000b34: 88fb ldrh r3, [r7, #6]
|
|
8000b36: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8000b3a: d20d bcs.n 8000b58 <update_fb_from_scroll+0x5c>
|
|
8000b3c: 88fb ldrh r3, [r7, #6]
|
|
8000b3e: 4911 ldr r1, [pc, #68] @ (8000b84 <update_fb_from_scroll+0x88>)
|
|
8000b40: 68fa ldr r2, [r7, #12]
|
|
8000b42: 0252 lsls r2, r2, #9
|
|
8000b44: 440a add r2, r1
|
|
8000b46: 4413 add r3, r2
|
|
8000b48: 781b ldrb r3, [r3, #0]
|
|
8000b4a: 2b00 cmp r3, #0
|
|
8000b4c: d004 beq.n 8000b58 <update_fb_from_scroll+0x5c>
|
|
fb_set_pixel(col, row, 1);
|
|
8000b4e: 2201 movs r2, #1
|
|
8000b50: 68f9 ldr r1, [r7, #12]
|
|
8000b52: 68b8 ldr r0, [r7, #8]
|
|
8000b54: f7ff fd98 bl 8000688 <fb_set_pixel>
|
|
for (int col = 0; col < COLS; col++) {
|
|
8000b58: 68bb ldr r3, [r7, #8]
|
|
8000b5a: 3301 adds r3, #1
|
|
8000b5c: 60bb str r3, [r7, #8]
|
|
8000b5e: 68bb ldr r3, [r7, #8]
|
|
8000b60: 2b5f cmp r3, #95 @ 0x5f
|
|
8000b62: dde0 ble.n 8000b26 <update_fb_from_scroll+0x2a>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000b64: 68fb ldr r3, [r7, #12]
|
|
8000b66: 3301 adds r3, #1
|
|
8000b68: 60fb str r3, [r7, #12]
|
|
8000b6a: 68fb ldr r3, [r7, #12]
|
|
8000b6c: 2b06 cmp r3, #6
|
|
8000b6e: ddcb ble.n 8000b08 <update_fb_from_scroll+0xc>
|
|
}
|
|
}
|
|
}
|
|
8000b70: bf00 nop
|
|
8000b72: bf00 nop
|
|
8000b74: 3710 adds r7, #16
|
|
8000b76: 46bd mov sp, r7
|
|
8000b78: bd80 pop {r7, pc}
|
|
8000b7a: bf00 nop
|
|
8000b7c: 2000012c .word 0x2000012c
|
|
8000b80: 20000f84 .word 0x20000f84
|
|
8000b84: 20000180 .word 0x20000180
|
|
|
|
08000b88 <update_fb_from_scroll_clipped>:
|
|
|
|
/* ── Update fb from scroll but only write to cols >= clip_left ── */
|
|
static void update_fb_from_scroll_clipped(int clip_left)
|
|
{
|
|
8000b88: b580 push {r7, lr}
|
|
8000b8a: b086 sub sp, #24
|
|
8000b8c: af00 add r7, sp, #0
|
|
8000b8e: 6078 str r0, [r7, #4]
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000b90: 2300 movs r3, #0
|
|
8000b92: 617b str r3, [r7, #20]
|
|
8000b94: e026 b.n 8000be4 <update_fb_from_scroll_clipped+0x5c>
|
|
for (int col = clip_left; col < COLS; col++) {
|
|
8000b96: 687b ldr r3, [r7, #4]
|
|
8000b98: 613b str r3, [r7, #16]
|
|
8000b9a: e01d b.n 8000bd8 <update_fb_from_scroll_clipped+0x50>
|
|
uint16_t src = (uint16_t)(scroll_x + (col - clip_left));
|
|
8000b9c: 4b15 ldr r3, [pc, #84] @ (8000bf4 <update_fb_from_scroll_clipped+0x6c>)
|
|
8000b9e: 681b ldr r3, [r3, #0]
|
|
8000ba0: b29a uxth r2, r3
|
|
8000ba2: 693b ldr r3, [r7, #16]
|
|
8000ba4: b299 uxth r1, r3
|
|
8000ba6: 687b ldr r3, [r7, #4]
|
|
8000ba8: b29b uxth r3, r3
|
|
8000baa: 1acb subs r3, r1, r3
|
|
8000bac: b29b uxth r3, r3
|
|
8000bae: 4413 add r3, r2
|
|
8000bb0: 81fb strh r3, [r7, #14]
|
|
if (src < WIDE_COLS)
|
|
8000bb2: 89fb ldrh r3, [r7, #14]
|
|
8000bb4: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8000bb8: d20b bcs.n 8000bd2 <update_fb_from_scroll_clipped+0x4a>
|
|
fb_set_pixel(col, row, wide[row][src]);
|
|
8000bba: 89fb ldrh r3, [r7, #14]
|
|
8000bbc: 490e ldr r1, [pc, #56] @ (8000bf8 <update_fb_from_scroll_clipped+0x70>)
|
|
8000bbe: 697a ldr r2, [r7, #20]
|
|
8000bc0: 0252 lsls r2, r2, #9
|
|
8000bc2: 440a add r2, r1
|
|
8000bc4: 4413 add r3, r2
|
|
8000bc6: 781b ldrb r3, [r3, #0]
|
|
8000bc8: 461a mov r2, r3
|
|
8000bca: 6979 ldr r1, [r7, #20]
|
|
8000bcc: 6938 ldr r0, [r7, #16]
|
|
8000bce: f7ff fd5b bl 8000688 <fb_set_pixel>
|
|
for (int col = clip_left; col < COLS; col++) {
|
|
8000bd2: 693b ldr r3, [r7, #16]
|
|
8000bd4: 3301 adds r3, #1
|
|
8000bd6: 613b str r3, [r7, #16]
|
|
8000bd8: 693b ldr r3, [r7, #16]
|
|
8000bda: 2b5f cmp r3, #95 @ 0x5f
|
|
8000bdc: ddde ble.n 8000b9c <update_fb_from_scroll_clipped+0x14>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000bde: 697b ldr r3, [r7, #20]
|
|
8000be0: 3301 adds r3, #1
|
|
8000be2: 617b str r3, [r7, #20]
|
|
8000be4: 697b ldr r3, [r7, #20]
|
|
8000be6: 2b06 cmp r3, #6
|
|
8000be8: ddd5 ble.n 8000b96 <update_fb_from_scroll_clipped+0xe>
|
|
}
|
|
}
|
|
}
|
|
8000bea: bf00 nop
|
|
8000bec: bf00 nop
|
|
8000bee: 3718 adds r7, #24
|
|
8000bf0: 46bd mov sp, r7
|
|
8000bf2: bd80 pop {r7, pc}
|
|
8000bf4: 20000f84 .word 0x20000f84
|
|
8000bf8: 20000180 .word 0x20000180
|
|
|
|
08000bfc <fade_out_rows>:
|
|
|
|
/* ── Fade rows out (centre outward to top+bottom) ── */
|
|
static void fade_out_rows(int star_col, int text_col, uint8_t is_logo)
|
|
{
|
|
8000bfc: b580 push {r7, lr}
|
|
8000bfe: b09e sub sp, #120 @ 0x78
|
|
8000c00: af00 add r7, sp, #0
|
|
8000c02: 60f8 str r0, [r7, #12]
|
|
8000c04: 60b9 str r1, [r7, #8]
|
|
8000c06: 4613 mov r3, r2
|
|
8000c08: 71fb strb r3, [r7, #7]
|
|
uint8_t masks[] = {0x7E, 0x7C, 0x3C, 0x1C, 0x0C, 0x08, 0x00};
|
|
8000c0a: 4a32 ldr r2, [pc, #200] @ (8000cd4 <fade_out_rows+0xd8>)
|
|
8000c0c: f107 0368 add.w r3, r7, #104 @ 0x68
|
|
8000c10: e892 0003 ldmia.w r2, {r0, r1}
|
|
8000c14: 6018 str r0, [r3, #0]
|
|
8000c16: 3304 adds r3, #4
|
|
8000c18: 8019 strh r1, [r3, #0]
|
|
8000c1a: 3302 adds r3, #2
|
|
8000c1c: 0c0a lsrs r2, r1, #16
|
|
8000c1e: 701a strb r2, [r3, #0]
|
|
uint8_t snap[ROWS][NUM_CHIPS];
|
|
memcpy(snap, fb, sizeof(fb));
|
|
8000c20: 4a2d ldr r2, [pc, #180] @ (8000cd8 <fade_out_rows+0xdc>)
|
|
8000c22: f107 0314 add.w r3, r7, #20
|
|
8000c26: 4611 mov r1, r2
|
|
8000c28: 2254 movs r2, #84 @ 0x54
|
|
8000c2a: 4618 mov r0, r3
|
|
8000c2c: f004 fdbc bl 80057a8 <memcpy>
|
|
for (int i = 0; i < 7; i++) {
|
|
8000c30: 2300 movs r3, #0
|
|
8000c32: 677b str r3, [r7, #116] @ 0x74
|
|
8000c34: e041 b.n 8000cba <fade_out_rows+0xbe>
|
|
if (is_logo) {
|
|
8000c36: 79fb ldrb r3, [r7, #7]
|
|
8000c38: 2b00 cmp r3, #0
|
|
8000c3a: d00a beq.n 8000c52 <fade_out_rows+0x56>
|
|
render_logo_rows(star_col, text_col, masks[i]);
|
|
8000c3c: f107 0268 add.w r2, r7, #104 @ 0x68
|
|
8000c40: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8000c42: 4413 add r3, r2
|
|
8000c44: 781b ldrb r3, [r3, #0]
|
|
8000c46: 461a mov r2, r3
|
|
8000c48: 68b9 ldr r1, [r7, #8]
|
|
8000c4a: 68f8 ldr r0, [r7, #12]
|
|
8000c4c: f7ff fdf4 bl 8000838 <render_logo_rows>
|
|
8000c50: e02d b.n 8000cae <fade_out_rows+0xb2>
|
|
} else {
|
|
memset(fb, 0, sizeof(fb));
|
|
8000c52: 2254 movs r2, #84 @ 0x54
|
|
8000c54: 2100 movs r1, #0
|
|
8000c56: 4820 ldr r0, [pc, #128] @ (8000cd8 <fade_out_rows+0xdc>)
|
|
8000c58: f004 fd7a bl 8005750 <memset>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000c5c: 2300 movs r3, #0
|
|
8000c5e: 673b str r3, [r7, #112] @ 0x70
|
|
8000c60: e022 b.n 8000ca8 <fade_out_rows+0xac>
|
|
if (masks[i] & (1 << row))
|
|
8000c62: f107 0268 add.w r2, r7, #104 @ 0x68
|
|
8000c66: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8000c68: 4413 add r3, r2
|
|
8000c6a: 781b ldrb r3, [r3, #0]
|
|
8000c6c: 461a mov r2, r3
|
|
8000c6e: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8000c70: fa42 f303 asr.w r3, r2, r3
|
|
8000c74: f003 0301 and.w r3, r3, #1
|
|
8000c78: 2b00 cmp r3, #0
|
|
8000c7a: d012 beq.n 8000ca2 <fade_out_rows+0xa6>
|
|
memcpy(fb[row], snap[row], NUM_CHIPS);
|
|
8000c7c: 6f3a ldr r2, [r7, #112] @ 0x70
|
|
8000c7e: 4613 mov r3, r2
|
|
8000c80: 005b lsls r3, r3, #1
|
|
8000c82: 4413 add r3, r2
|
|
8000c84: 009b lsls r3, r3, #2
|
|
8000c86: 4a14 ldr r2, [pc, #80] @ (8000cd8 <fade_out_rows+0xdc>)
|
|
8000c88: 1898 adds r0, r3, r2
|
|
8000c8a: f107 0114 add.w r1, r7, #20
|
|
8000c8e: 6f3a ldr r2, [r7, #112] @ 0x70
|
|
8000c90: 4613 mov r3, r2
|
|
8000c92: 005b lsls r3, r3, #1
|
|
8000c94: 4413 add r3, r2
|
|
8000c96: 009b lsls r3, r3, #2
|
|
8000c98: 440b add r3, r1
|
|
8000c9a: 220c movs r2, #12
|
|
8000c9c: 4619 mov r1, r3
|
|
8000c9e: f004 fd83 bl 80057a8 <memcpy>
|
|
for (int row = 0; row < ROWS; row++) {
|
|
8000ca2: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8000ca4: 3301 adds r3, #1
|
|
8000ca6: 673b str r3, [r7, #112] @ 0x70
|
|
8000ca8: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8000caa: 2b06 cmp r3, #6
|
|
8000cac: ddd9 ble.n 8000c62 <fade_out_rows+0x66>
|
|
}
|
|
}
|
|
refresh_for(60);
|
|
8000cae: 203c movs r0, #60 @ 0x3c
|
|
8000cb0: f7ff fcc6 bl 8000640 <refresh_for>
|
|
for (int i = 0; i < 7; i++) {
|
|
8000cb4: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8000cb6: 3301 adds r3, #1
|
|
8000cb8: 677b str r3, [r7, #116] @ 0x74
|
|
8000cba: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8000cbc: 2b06 cmp r3, #6
|
|
8000cbe: ddba ble.n 8000c36 <fade_out_rows+0x3a>
|
|
}
|
|
memset(fb, 0, sizeof(fb));
|
|
8000cc0: 2254 movs r2, #84 @ 0x54
|
|
8000cc2: 2100 movs r1, #0
|
|
8000cc4: 4804 ldr r0, [pc, #16] @ (8000cd8 <fade_out_rows+0xdc>)
|
|
8000cc6: f004 fd43 bl 8005750 <memset>
|
|
}
|
|
8000cca: bf00 nop
|
|
8000ccc: 3778 adds r7, #120 @ 0x78
|
|
8000cce: 46bd mov sp, r7
|
|
8000cd0: bd80 pop {r7, pc}
|
|
8000cd2: bf00 nop
|
|
8000cd4: 080057dc .word 0x080057dc
|
|
8000cd8: 2000012c .word 0x2000012c
|
|
|
|
08000cdc <arrive_animation>:
|
|
/* ════════════════════════════════════════════════
|
|
Arrive boot / splash animation
|
|
════════════════════════════════════════════════ */
|
|
|
|
static void arrive_animation(void)
|
|
{
|
|
8000cdc: b580 push {r7, lr}
|
|
8000cde: b088 sub sp, #32
|
|
8000ce0: af00 add r7, sp, #0
|
|
const int text_col = 23;
|
|
8000ce2: 2317 movs r3, #23
|
|
8000ce4: 60bb str r3, [r7, #8]
|
|
const int star_col = 61;
|
|
8000ce6: 233d movs r3, #61 @ 0x3d
|
|
8000ce8: 607b str r3, [r7, #4]
|
|
|
|
/* Phase 1 — star builds */
|
|
memset(fb, 0, sizeof(fb));
|
|
8000cea: 2254 movs r2, #84 @ 0x54
|
|
8000cec: 2100 movs r1, #0
|
|
8000cee: 4853 ldr r0, [pc, #332] @ (8000e3c <arrive_animation+0x160>)
|
|
8000cf0: f004 fd2e bl 8005750 <memset>
|
|
for (int row = 0; row < 7; row++) fb_set_pixel(star_col + 4, row, 1);
|
|
8000cf4: 2300 movs r3, #0
|
|
8000cf6: 61fb str r3, [r7, #28]
|
|
8000cf8: e009 b.n 8000d0e <arrive_animation+0x32>
|
|
8000cfa: 687b ldr r3, [r7, #4]
|
|
8000cfc: 3304 adds r3, #4
|
|
8000cfe: 2201 movs r2, #1
|
|
8000d00: 69f9 ldr r1, [r7, #28]
|
|
8000d02: 4618 mov r0, r3
|
|
8000d04: f7ff fcc0 bl 8000688 <fb_set_pixel>
|
|
8000d08: 69fb ldr r3, [r7, #28]
|
|
8000d0a: 3301 adds r3, #1
|
|
8000d0c: 61fb str r3, [r7, #28]
|
|
8000d0e: 69fb ldr r3, [r7, #28]
|
|
8000d10: 2b06 cmp r3, #6
|
|
8000d12: ddf2 ble.n 8000cfa <arrive_animation+0x1e>
|
|
for (int sc = 3; sc <= 5; sc++) fb_set_pixel(star_col + sc, 3, 1);
|
|
8000d14: 2303 movs r3, #3
|
|
8000d16: 61bb str r3, [r7, #24]
|
|
8000d18: e00a b.n 8000d30 <arrive_animation+0x54>
|
|
8000d1a: 687a ldr r2, [r7, #4]
|
|
8000d1c: 69bb ldr r3, [r7, #24]
|
|
8000d1e: 4413 add r3, r2
|
|
8000d20: 2201 movs r2, #1
|
|
8000d22: 2103 movs r1, #3
|
|
8000d24: 4618 mov r0, r3
|
|
8000d26: f7ff fcaf bl 8000688 <fb_set_pixel>
|
|
8000d2a: 69bb ldr r3, [r7, #24]
|
|
8000d2c: 3301 adds r3, #1
|
|
8000d2e: 61bb str r3, [r7, #24]
|
|
8000d30: 69bb ldr r3, [r7, #24]
|
|
8000d32: 2b05 cmp r3, #5
|
|
8000d34: ddf1 ble.n 8000d1a <arrive_animation+0x3e>
|
|
refresh_for(120);
|
|
8000d36: 2078 movs r0, #120 @ 0x78
|
|
8000d38: f7ff fc82 bl 8000640 <refresh_for>
|
|
|
|
memset(fb, 0, sizeof(fb));
|
|
8000d3c: 2254 movs r2, #84 @ 0x54
|
|
8000d3e: 2100 movs r1, #0
|
|
8000d40: 483e ldr r0, [pc, #248] @ (8000e3c <arrive_animation+0x160>)
|
|
8000d42: f004 fd05 bl 8005750 <memset>
|
|
for (int row = 0; row < 7; row++)
|
|
8000d46: 2300 movs r3, #0
|
|
8000d48: 617b str r3, [r7, #20]
|
|
8000d4a: e020 b.n 8000d8e <arrive_animation+0xb2>
|
|
for (int sc = 3; sc <= 7; sc++)
|
|
8000d4c: 2303 movs r3, #3
|
|
8000d4e: 613b str r3, [r7, #16]
|
|
8000d50: e017 b.n 8000d82 <arrive_animation+0xa6>
|
|
if (STAR[row][sc]) fb_set_pixel(star_col + sc, row, 1);
|
|
8000d52: 493b ldr r1, [pc, #236] @ (8000e40 <arrive_animation+0x164>)
|
|
8000d54: 697a ldr r2, [r7, #20]
|
|
8000d56: 4613 mov r3, r2
|
|
8000d58: 009b lsls r3, r3, #2
|
|
8000d5a: 4413 add r3, r2
|
|
8000d5c: 005b lsls r3, r3, #1
|
|
8000d5e: 4413 add r3, r2
|
|
8000d60: 18ca adds r2, r1, r3
|
|
8000d62: 693b ldr r3, [r7, #16]
|
|
8000d64: 4413 add r3, r2
|
|
8000d66: 781b ldrb r3, [r3, #0]
|
|
8000d68: 2b00 cmp r3, #0
|
|
8000d6a: d007 beq.n 8000d7c <arrive_animation+0xa0>
|
|
8000d6c: 687a ldr r2, [r7, #4]
|
|
8000d6e: 693b ldr r3, [r7, #16]
|
|
8000d70: 4413 add r3, r2
|
|
8000d72: 2201 movs r2, #1
|
|
8000d74: 6979 ldr r1, [r7, #20]
|
|
8000d76: 4618 mov r0, r3
|
|
8000d78: f7ff fc86 bl 8000688 <fb_set_pixel>
|
|
for (int sc = 3; sc <= 7; sc++)
|
|
8000d7c: 693b ldr r3, [r7, #16]
|
|
8000d7e: 3301 adds r3, #1
|
|
8000d80: 613b str r3, [r7, #16]
|
|
8000d82: 693b ldr r3, [r7, #16]
|
|
8000d84: 2b07 cmp r3, #7
|
|
8000d86: dde4 ble.n 8000d52 <arrive_animation+0x76>
|
|
for (int row = 0; row < 7; row++)
|
|
8000d88: 697b ldr r3, [r7, #20]
|
|
8000d8a: 3301 adds r3, #1
|
|
8000d8c: 617b str r3, [r7, #20]
|
|
8000d8e: 697b ldr r3, [r7, #20]
|
|
8000d90: 2b06 cmp r3, #6
|
|
8000d92: dddb ble.n 8000d4c <arrive_animation+0x70>
|
|
refresh_for(120);
|
|
8000d94: 2078 movs r0, #120 @ 0x78
|
|
8000d96: f7ff fc53 bl 8000640 <refresh_for>
|
|
|
|
render_logo(star_col, text_col, star_col);
|
|
8000d9a: 687a ldr r2, [r7, #4]
|
|
8000d9c: 68b9 ldr r1, [r7, #8]
|
|
8000d9e: 6878 ldr r0, [r7, #4]
|
|
8000da0: f7ff fce0 bl 8000764 <render_logo>
|
|
refresh_for(150);
|
|
8000da4: 2096 movs r0, #150 @ 0x96
|
|
8000da6: f7ff fc4b bl 8000640 <refresh_for>
|
|
|
|
/* Phase 2 — glint pulse */
|
|
memset(fb, 0, sizeof(fb)); refresh_for(80);
|
|
8000daa: 2254 movs r2, #84 @ 0x54
|
|
8000dac: 2100 movs r1, #0
|
|
8000dae: 4823 ldr r0, [pc, #140] @ (8000e3c <arrive_animation+0x160>)
|
|
8000db0: f004 fcce bl 8005750 <memset>
|
|
8000db4: 2050 movs r0, #80 @ 0x50
|
|
8000db6: f7ff fc43 bl 8000640 <refresh_for>
|
|
render_logo(star_col, text_col, star_col); refresh_for(80);
|
|
8000dba: 687a ldr r2, [r7, #4]
|
|
8000dbc: 68b9 ldr r1, [r7, #8]
|
|
8000dbe: 6878 ldr r0, [r7, #4]
|
|
8000dc0: f7ff fcd0 bl 8000764 <render_logo>
|
|
8000dc4: 2050 movs r0, #80 @ 0x50
|
|
8000dc6: f7ff fc3b bl 8000640 <refresh_for>
|
|
memset(fb, 0, sizeof(fb)); refresh_for(60);
|
|
8000dca: 2254 movs r2, #84 @ 0x54
|
|
8000dcc: 2100 movs r1, #0
|
|
8000dce: 481b ldr r0, [pc, #108] @ (8000e3c <arrive_animation+0x160>)
|
|
8000dd0: f004 fcbe bl 8005750 <memset>
|
|
8000dd4: 203c movs r0, #60 @ 0x3c
|
|
8000dd6: f7ff fc33 bl 8000640 <refresh_for>
|
|
render_logo(star_col, text_col, star_col); refresh_for(100);
|
|
8000dda: 687a ldr r2, [r7, #4]
|
|
8000ddc: 68b9 ldr r1, [r7, #8]
|
|
8000dde: 6878 ldr r0, [r7, #4]
|
|
8000de0: f7ff fcc0 bl 8000764 <render_logo>
|
|
8000de4: 2064 movs r0, #100 @ 0x64
|
|
8000de6: f7ff fc2b bl 8000640 <refresh_for>
|
|
|
|
/* Phase 3 — wipe reveal */
|
|
for (int mask = star_col; mask >= text_col - 1; mask -= 2) {
|
|
8000dea: 687b ldr r3, [r7, #4]
|
|
8000dec: 60fb str r3, [r7, #12]
|
|
8000dee: e00a b.n 8000e06 <arrive_animation+0x12a>
|
|
render_logo(star_col, text_col, mask);
|
|
8000df0: 68fa ldr r2, [r7, #12]
|
|
8000df2: 68b9 ldr r1, [r7, #8]
|
|
8000df4: 6878 ldr r0, [r7, #4]
|
|
8000df6: f7ff fcb5 bl 8000764 <render_logo>
|
|
refresh_for(18);
|
|
8000dfa: 2012 movs r0, #18
|
|
8000dfc: f7ff fc20 bl 8000640 <refresh_for>
|
|
for (int mask = star_col; mask >= text_col - 1; mask -= 2) {
|
|
8000e00: 68fb ldr r3, [r7, #12]
|
|
8000e02: 3b02 subs r3, #2
|
|
8000e04: 60fb str r3, [r7, #12]
|
|
8000e06: 68bb ldr r3, [r7, #8]
|
|
8000e08: 3b01 subs r3, #1
|
|
8000e0a: 68fa ldr r2, [r7, #12]
|
|
8000e0c: 429a cmp r2, r3
|
|
8000e0e: daef bge.n 8000df0 <arrive_animation+0x114>
|
|
}
|
|
render_logo(star_col, text_col, -1);
|
|
8000e10: f04f 32ff mov.w r2, #4294967295
|
|
8000e14: 68b9 ldr r1, [r7, #8]
|
|
8000e16: 6878 ldr r0, [r7, #4]
|
|
8000e18: f7ff fca4 bl 8000764 <render_logo>
|
|
|
|
/* Phase 4 — hold */
|
|
refresh_for(2000);
|
|
8000e1c: f44f 60fa mov.w r0, #2000 @ 0x7d0
|
|
8000e20: f7ff fc0e bl 8000640 <refresh_for>
|
|
|
|
/* Phase 5 — fade out */
|
|
fade_out_rows(star_col, text_col, 1);
|
|
8000e24: 2201 movs r2, #1
|
|
8000e26: 68b9 ldr r1, [r7, #8]
|
|
8000e28: 6878 ldr r0, [r7, #4]
|
|
8000e2a: f7ff fee7 bl 8000bfc <fade_out_rows>
|
|
refresh_for(200);
|
|
8000e2e: 20c8 movs r0, #200 @ 0xc8
|
|
8000e30: f7ff fc06 bl 8000640 <refresh_for>
|
|
}
|
|
8000e34: bf00 nop
|
|
8000e36: 3720 adds r7, #32
|
|
8000e38: 46bd mov sp, r7
|
|
8000e3a: bd80 pop {r7, pc}
|
|
8000e3c: 2000012c .word 0x2000012c
|
|
8000e40: 08005974 .word 0x08005974
|
|
|
|
08000e44 <run_values>:
|
|
|
|
static const char *VALUES_WORDS[] = { "CURIOUS", "FOCUSED", "TOGETHER" };
|
|
#define VALUES_COUNT 3
|
|
|
|
static void run_values(void)
|
|
{
|
|
8000e44: b580 push {r7, lr}
|
|
8000e46: b082 sub sp, #8
|
|
8000e48: af00 add r7, sp, #0
|
|
uint8_t idx = 0;
|
|
8000e4a: 2300 movs r3, #0
|
|
8000e4c: 71fb strb r3, [r7, #7]
|
|
|
|
while (!check_new_cmd()) {
|
|
8000e4e: e03b b.n 8000ec8 <run_values+0x84>
|
|
/* Arrive splash with fade out */
|
|
arrive_animation();
|
|
8000e50: f7ff ff44 bl 8000cdc <arrive_animation>
|
|
if (check_new_cmd()) break;
|
|
8000e54: f7ff fc0c bl 8000670 <check_new_cmd>
|
|
8000e58: 4603 mov r3, r0
|
|
8000e5a: 2b00 cmp r3, #0
|
|
8000e5c: d13a bne.n 8000ed4 <run_values+0x90>
|
|
|
|
/* Display word centred — no fade in, just show it */
|
|
render_centred_text(VALUES_WORDS[idx]);
|
|
8000e5e: 79fb ldrb r3, [r7, #7]
|
|
8000e60: 4a22 ldr r2, [pc, #136] @ (8000eec <run_values+0xa8>)
|
|
8000e62: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8000e66: 4618 mov r0, r3
|
|
8000e68: f7ff fda8 bl 80009bc <render_centred_text>
|
|
refresh_for(2500);
|
|
8000e6c: f640 10c4 movw r0, #2500 @ 0x9c4
|
|
8000e70: f7ff fbe6 bl 8000640 <refresh_for>
|
|
if (check_new_cmd()) break;
|
|
8000e74: f7ff fbfc bl 8000670 <check_new_cmd>
|
|
8000e78: 4603 mov r3, r0
|
|
8000e7a: 2b00 cmp r3, #0
|
|
8000e7c: d12c bne.n 8000ed8 <run_values+0x94>
|
|
|
|
/* Fade out same as arrive splash — rows collapse inward */
|
|
fade_out_rows(0, 0, 0);
|
|
8000e7e: 2200 movs r2, #0
|
|
8000e80: 2100 movs r1, #0
|
|
8000e82: 2000 movs r0, #0
|
|
8000e84: f7ff feba bl 8000bfc <fade_out_rows>
|
|
if (check_new_cmd()) break;
|
|
8000e88: f7ff fbf2 bl 8000670 <check_new_cmd>
|
|
8000e8c: 4603 mov r3, r0
|
|
8000e8e: 2b00 cmp r3, #0
|
|
8000e90: d124 bne.n 8000edc <run_values+0x98>
|
|
|
|
/* Wait before next cycle */
|
|
memset(fb, 0, sizeof(fb));
|
|
8000e92: 2254 movs r2, #84 @ 0x54
|
|
8000e94: 2100 movs r1, #0
|
|
8000e96: 4816 ldr r0, [pc, #88] @ (8000ef0 <run_values+0xac>)
|
|
8000e98: f004 fc5a bl 8005750 <memset>
|
|
refresh_for(600);
|
|
8000e9c: f44f 7016 mov.w r0, #600 @ 0x258
|
|
8000ea0: f7ff fbce bl 8000640 <refresh_for>
|
|
if (check_new_cmd()) break;
|
|
8000ea4: f7ff fbe4 bl 8000670 <check_new_cmd>
|
|
8000ea8: 4603 mov r3, r0
|
|
8000eaa: 2b00 cmp r3, #0
|
|
8000eac: d118 bne.n 8000ee0 <run_values+0x9c>
|
|
|
|
idx = (idx + 1) % VALUES_COUNT;
|
|
8000eae: 79fb ldrb r3, [r7, #7]
|
|
8000eb0: 1c5a adds r2, r3, #1
|
|
8000eb2: 4b10 ldr r3, [pc, #64] @ (8000ef4 <run_values+0xb0>)
|
|
8000eb4: fb83 3102 smull r3, r1, r3, r2
|
|
8000eb8: 17d3 asrs r3, r2, #31
|
|
8000eba: 1ac9 subs r1, r1, r3
|
|
8000ebc: 460b mov r3, r1
|
|
8000ebe: 005b lsls r3, r3, #1
|
|
8000ec0: 440b add r3, r1
|
|
8000ec2: 1ad1 subs r1, r2, r3
|
|
8000ec4: 460b mov r3, r1
|
|
8000ec6: 71fb strb r3, [r7, #7]
|
|
while (!check_new_cmd()) {
|
|
8000ec8: f7ff fbd2 bl 8000670 <check_new_cmd>
|
|
8000ecc: 4603 mov r3, r0
|
|
8000ece: 2b00 cmp r3, #0
|
|
8000ed0: d0be beq.n 8000e50 <run_values+0xc>
|
|
}
|
|
}
|
|
8000ed2: e006 b.n 8000ee2 <run_values+0x9e>
|
|
if (check_new_cmd()) break;
|
|
8000ed4: bf00 nop
|
|
8000ed6: e004 b.n 8000ee2 <run_values+0x9e>
|
|
if (check_new_cmd()) break;
|
|
8000ed8: bf00 nop
|
|
8000eda: e002 b.n 8000ee2 <run_values+0x9e>
|
|
if (check_new_cmd()) break;
|
|
8000edc: bf00 nop
|
|
8000ede: e000 b.n 8000ee2 <run_values+0x9e>
|
|
if (check_new_cmd()) break;
|
|
8000ee0: bf00 nop
|
|
}
|
|
8000ee2: bf00 nop
|
|
8000ee4: 3708 adds r7, #8
|
|
8000ee6: 46bd mov sp, r7
|
|
8000ee8: bd80 pop {r7, pc}
|
|
8000eea: bf00 nop
|
|
8000eec: 20000000 .word 0x20000000
|
|
8000ef0: 2000012c .word 0x2000012c
|
|
8000ef4: 55555556 .word 0x55555556
|
|
|
|
08000ef8 <run_hw_dept>:
|
|
#define HW_TEXT_COL 2
|
|
#define HW_STAR_COL 40
|
|
#define HW_SCROLL_START 54
|
|
|
|
static void run_hw_dept(void)
|
|
{
|
|
8000ef8: b580 push {r7, lr}
|
|
8000efa: b086 sub sp, #24
|
|
8000efc: af00 add r7, sp, #0
|
|
const char *hw_txt = "HARDWARE DEPT ";
|
|
8000efe: 4b1f ldr r3, [pc, #124] @ (8000f7c <run_hw_dept+0x84>)
|
|
8000f00: 60fb str r3, [r7, #12]
|
|
/* Start text one scroll-zone width to the right so it scrolls in from edge */
|
|
const int scroll_zone = COLS - HW_SCROLL_START; /* ~42 cols */
|
|
8000f02: 232a movs r3, #42 @ 0x2a
|
|
8000f04: 60bb str r3, [r7, #8]
|
|
uint16_t hw_wide_cols = render_scroll(hw_txt, scroll_zone);
|
|
8000f06: 68b9 ldr r1, [r7, #8]
|
|
8000f08: 68f8 ldr r0, [r7, #12]
|
|
8000f0a: f7ff fd87 bl 8000a1c <render_scroll>
|
|
8000f0e: 4603 mov r3, r0
|
|
8000f10: 80fb strh r3, [r7, #6]
|
|
int32_t hw_scroll_x = 0;
|
|
8000f12: 2300 movs r3, #0
|
|
8000f14: 617b str r3, [r7, #20]
|
|
uint32_t last_scroll = HAL_GetTick();
|
|
8000f16: f000 fcb7 bl 8001888 <HAL_GetTick>
|
|
8000f1a: 6138 str r0, [r7, #16]
|
|
const uint32_t scroll_ms = 40;
|
|
8000f1c: 2328 movs r3, #40 @ 0x28
|
|
8000f1e: 603b str r3, [r7, #0]
|
|
|
|
while (!check_new_cmd()) {
|
|
8000f20: e021 b.n 8000f66 <run_hw_dept+0x6e>
|
|
/* Draw logo into fb */
|
|
render_logo(HW_STAR_COL, HW_TEXT_COL, -1);
|
|
8000f22: f04f 32ff mov.w r2, #4294967295
|
|
8000f26: 2102 movs r1, #2
|
|
8000f28: 2028 movs r0, #40 @ 0x28
|
|
8000f2a: f7ff fc1b bl 8000764 <render_logo>
|
|
|
|
/* Overlay scrolling text on right side */
|
|
update_fb_from_scroll_clipped(HW_SCROLL_START);
|
|
8000f2e: 2036 movs r0, #54 @ 0x36
|
|
8000f30: f7ff fe2a bl 8000b88 <update_fb_from_scroll_clipped>
|
|
|
|
/* Advance scroll */
|
|
if ((HAL_GetTick() - last_scroll) >= scroll_ms) {
|
|
8000f34: f000 fca8 bl 8001888 <HAL_GetTick>
|
|
8000f38: 4602 mov r2, r0
|
|
8000f3a: 693b ldr r3, [r7, #16]
|
|
8000f3c: 1ad3 subs r3, r2, r3
|
|
8000f3e: 683a ldr r2, [r7, #0]
|
|
8000f40: 429a cmp r2, r3
|
|
8000f42: d80e bhi.n 8000f62 <run_hw_dept+0x6a>
|
|
last_scroll = HAL_GetTick();
|
|
8000f44: f000 fca0 bl 8001888 <HAL_GetTick>
|
|
8000f48: 6138 str r0, [r7, #16]
|
|
hw_scroll_x++;
|
|
8000f4a: 697b ldr r3, [r7, #20]
|
|
8000f4c: 3301 adds r3, #1
|
|
8000f4e: 617b str r3, [r7, #20]
|
|
if (hw_scroll_x >= hw_wide_cols) hw_scroll_x = 0;
|
|
8000f50: 88fb ldrh r3, [r7, #6]
|
|
8000f52: 697a ldr r2, [r7, #20]
|
|
8000f54: 429a cmp r2, r3
|
|
8000f56: db01 blt.n 8000f5c <run_hw_dept+0x64>
|
|
8000f58: 2300 movs r3, #0
|
|
8000f5a: 617b str r3, [r7, #20]
|
|
scroll_x = hw_scroll_x;
|
|
8000f5c: 4a08 ldr r2, [pc, #32] @ (8000f80 <run_hw_dept+0x88>)
|
|
8000f5e: 697b ldr r3, [r7, #20]
|
|
8000f60: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
display_refresh();
|
|
8000f62: f7ff fb35 bl 80005d0 <display_refresh>
|
|
while (!check_new_cmd()) {
|
|
8000f66: f7ff fb83 bl 8000670 <check_new_cmd>
|
|
8000f6a: 4603 mov r3, r0
|
|
8000f6c: 2b00 cmp r3, #0
|
|
8000f6e: d0d8 beq.n 8000f22 <run_hw_dept+0x2a>
|
|
}
|
|
}
|
|
8000f70: bf00 nop
|
|
8000f72: bf00 nop
|
|
8000f74: 3718 adds r7, #24
|
|
8000f76: 46bd mov sp, r7
|
|
8000f78: bd80 pop {r7, pc}
|
|
8000f7a: bf00 nop
|
|
8000f7c: 08005800 .word 0x08005800
|
|
8000f80: 20000f84 .word 0x20000f84
|
|
|
|
08000f84 <run_scroll>:
|
|
/* ════════════════════════════════════════════════
|
|
CMD_SCROLL — scroll arbitrary text
|
|
════════════════════════════════════════════════ */
|
|
|
|
static void run_scroll(void)
|
|
{
|
|
8000f84: b580 push {r7, lr}
|
|
8000f86: b082 sub sp, #8
|
|
8000f88: af00 add r7, sp, #0
|
|
wide_cols = render_scroll(message, COLS);
|
|
8000f8a: 2160 movs r1, #96 @ 0x60
|
|
8000f8c: 481c ldr r0, [pc, #112] @ (8001000 <run_scroll+0x7c>)
|
|
8000f8e: f7ff fd45 bl 8000a1c <render_scroll>
|
|
8000f92: 4603 mov r3, r0
|
|
8000f94: 461a mov r2, r3
|
|
8000f96: 4b1b ldr r3, [pc, #108] @ (8001004 <run_scroll+0x80>)
|
|
8000f98: 801a strh r2, [r3, #0]
|
|
scroll_x = 0;
|
|
8000f9a: 4b1b ldr r3, [pc, #108] @ (8001008 <run_scroll+0x84>)
|
|
8000f9c: 2200 movs r2, #0
|
|
8000f9e: 601a str r2, [r3, #0]
|
|
update_fb_from_scroll();
|
|
8000fa0: f7ff fdac bl 8000afc <update_fb_from_scroll>
|
|
|
|
uint32_t last_scroll = HAL_GetTick();
|
|
8000fa4: f000 fc70 bl 8001888 <HAL_GetTick>
|
|
8000fa8: 6078 str r0, [r7, #4]
|
|
const uint32_t scroll_ms = 40;
|
|
8000faa: 2328 movs r3, #40 @ 0x28
|
|
8000fac: 603b str r3, [r7, #0]
|
|
|
|
while (!check_new_cmd()) {
|
|
8000fae: e01d b.n 8000fec <run_scroll+0x68>
|
|
if ((HAL_GetTick() - last_scroll) >= scroll_ms) {
|
|
8000fb0: f000 fc6a bl 8001888 <HAL_GetTick>
|
|
8000fb4: 4602 mov r2, r0
|
|
8000fb6: 687b ldr r3, [r7, #4]
|
|
8000fb8: 1ad3 subs r3, r2, r3
|
|
8000fba: 683a ldr r2, [r7, #0]
|
|
8000fbc: 429a cmp r2, r3
|
|
8000fbe: d813 bhi.n 8000fe8 <run_scroll+0x64>
|
|
last_scroll = HAL_GetTick();
|
|
8000fc0: f000 fc62 bl 8001888 <HAL_GetTick>
|
|
8000fc4: 6078 str r0, [r7, #4]
|
|
scroll_x++;
|
|
8000fc6: 4b10 ldr r3, [pc, #64] @ (8001008 <run_scroll+0x84>)
|
|
8000fc8: 681b ldr r3, [r3, #0]
|
|
8000fca: 3301 adds r3, #1
|
|
8000fcc: 4a0e ldr r2, [pc, #56] @ (8001008 <run_scroll+0x84>)
|
|
8000fce: 6013 str r3, [r2, #0]
|
|
if (scroll_x >= wide_cols) scroll_x = 0;
|
|
8000fd0: 4b0c ldr r3, [pc, #48] @ (8001004 <run_scroll+0x80>)
|
|
8000fd2: 881b ldrh r3, [r3, #0]
|
|
8000fd4: 461a mov r2, r3
|
|
8000fd6: 4b0c ldr r3, [pc, #48] @ (8001008 <run_scroll+0x84>)
|
|
8000fd8: 681b ldr r3, [r3, #0]
|
|
8000fda: 429a cmp r2, r3
|
|
8000fdc: dc02 bgt.n 8000fe4 <run_scroll+0x60>
|
|
8000fde: 4b0a ldr r3, [pc, #40] @ (8001008 <run_scroll+0x84>)
|
|
8000fe0: 2200 movs r2, #0
|
|
8000fe2: 601a str r2, [r3, #0]
|
|
update_fb_from_scroll();
|
|
8000fe4: f7ff fd8a bl 8000afc <update_fb_from_scroll>
|
|
}
|
|
display_refresh();
|
|
8000fe8: f7ff faf2 bl 80005d0 <display_refresh>
|
|
while (!check_new_cmd()) {
|
|
8000fec: f7ff fb40 bl 8000670 <check_new_cmd>
|
|
8000ff0: 4603 mov r3, r0
|
|
8000ff2: 2b00 cmp r3, #0
|
|
8000ff4: d0dc beq.n 8000fb0 <run_scroll+0x2c>
|
|
}
|
|
}
|
|
8000ff6: bf00 nop
|
|
8000ff8: bf00 nop
|
|
8000ffa: 3708 adds r7, #8
|
|
8000ffc: 46bd mov sp, r7
|
|
8000ffe: bd80 pop {r7, pc}
|
|
8001000: 20001098 .word 0x20001098
|
|
8001004: 20000f80 .word 0x20000f80
|
|
8001008: 20000f84 .word 0x20000f84
|
|
|
|
0800100c <HAL_UART_RxCpltCallback>:
|
|
} UartState;
|
|
|
|
static UartState uart_state = UART_WAIT_A;
|
|
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800100c: b580 push {r7, lr}
|
|
800100e: b084 sub sp, #16
|
|
8001010: af00 add r7, sp, #0
|
|
8001012: 6078 str r0, [r7, #4]
|
|
if (huart->Instance != USART2) return;
|
|
8001014: 687b ldr r3, [r7, #4]
|
|
8001016: 681b ldr r3, [r3, #0]
|
|
8001018: 4a5b ldr r2, [pc, #364] @ (8001188 <HAL_UART_RxCpltCallback+0x17c>)
|
|
800101a: 4293 cmp r3, r2
|
|
800101c: f040 80b0 bne.w 8001180 <HAL_UART_RxCpltCallback+0x174>
|
|
uint8_t b = uart_rx_byte;
|
|
8001020: 4b5a ldr r3, [pc, #360] @ (800118c <HAL_UART_RxCpltCallback+0x180>)
|
|
8001022: 781b ldrb r3, [r3, #0]
|
|
8001024: 73fb strb r3, [r7, #15]
|
|
|
|
switch (uart_state) {
|
|
8001026: 4b5a ldr r3, [pc, #360] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
8001028: 781b ldrb r3, [r3, #0]
|
|
800102a: 2b06 cmp r3, #6
|
|
800102c: f200 80a2 bhi.w 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
8001030: a201 add r2, pc, #4 @ (adr r2, 8001038 <HAL_UART_RxCpltCallback+0x2c>)
|
|
8001032: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001036: bf00 nop
|
|
8001038: 08001055 .word 0x08001055
|
|
800103c: 08001065 .word 0x08001065
|
|
8001040: 08001077 .word 0x08001077
|
|
8001044: 08001085 .word 0x08001085
|
|
8001048: 0800109f .word 0x0800109f
|
|
800104c: 080010ad .word 0x080010ad
|
|
8001050: 080010e3 .word 0x080010e3
|
|
case UART_WAIT_A:
|
|
if (b == 'A') uart_state = UART_WAIT_R;
|
|
8001054: 7bfb ldrb r3, [r7, #15]
|
|
8001056: 2b41 cmp r3, #65 @ 0x41
|
|
8001058: f040 8087 bne.w 800116a <HAL_UART_RxCpltCallback+0x15e>
|
|
800105c: 4b4c ldr r3, [pc, #304] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
800105e: 2201 movs r2, #1
|
|
8001060: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001062: e082 b.n 800116a <HAL_UART_RxCpltCallback+0x15e>
|
|
case UART_WAIT_R:
|
|
uart_state = (b == 'R') ? UART_WAIT_CMD : UART_WAIT_A;
|
|
8001064: 7bfb ldrb r3, [r7, #15]
|
|
8001066: 2b52 cmp r3, #82 @ 0x52
|
|
8001068: d101 bne.n 800106e <HAL_UART_RxCpltCallback+0x62>
|
|
800106a: 2202 movs r2, #2
|
|
800106c: e000 b.n 8001070 <HAL_UART_RxCpltCallback+0x64>
|
|
800106e: 2200 movs r2, #0
|
|
8001070: 4b47 ldr r3, [pc, #284] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
8001072: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001074: e07e b.n 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
case UART_WAIT_CMD:
|
|
uart_cmd = b;
|
|
8001076: 4a47 ldr r2, [pc, #284] @ (8001194 <HAL_UART_RxCpltCallback+0x188>)
|
|
8001078: 7bfb ldrb r3, [r7, #15]
|
|
800107a: 7013 strb r3, [r2, #0]
|
|
uart_state = UART_WAIT_LEN;
|
|
800107c: 4b44 ldr r3, [pc, #272] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
800107e: 2203 movs r2, #3
|
|
8001080: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001082: e077 b.n 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
case UART_WAIT_LEN:
|
|
uart_len = b;
|
|
8001084: 4a44 ldr r2, [pc, #272] @ (8001198 <HAL_UART_RxCpltCallback+0x18c>)
|
|
8001086: 7bfb ldrb r3, [r7, #15]
|
|
8001088: 7013 strb r3, [r2, #0]
|
|
uart_idx = 0;
|
|
800108a: 4b44 ldr r3, [pc, #272] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
800108c: 2200 movs r2, #0
|
|
800108e: 701a strb r2, [r3, #0]
|
|
uart_cs_acc = 0;
|
|
8001090: 4b43 ldr r3, [pc, #268] @ (80011a0 <HAL_UART_RxCpltCallback+0x194>)
|
|
8001092: 2200 movs r2, #0
|
|
8001094: 701a strb r2, [r3, #0]
|
|
uart_state = UART_WAIT_CS1;
|
|
8001096: 4b3e ldr r3, [pc, #248] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
8001098: 2204 movs r2, #4
|
|
800109a: 701a strb r2, [r3, #0]
|
|
break;
|
|
800109c: e06a b.n 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
case UART_WAIT_CS1:
|
|
uart_cs1 = b;
|
|
800109e: 4a41 ldr r2, [pc, #260] @ (80011a4 <HAL_UART_RxCpltCallback+0x198>)
|
|
80010a0: 7bfb ldrb r3, [r7, #15]
|
|
80010a2: 7013 strb r3, [r2, #0]
|
|
uart_state = UART_WAIT_CS2;
|
|
80010a4: 4b3a ldr r3, [pc, #232] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
80010a6: 2205 movs r2, #5
|
|
80010a8: 701a strb r2, [r3, #0]
|
|
break;
|
|
80010aa: e063 b.n 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
case UART_WAIT_CS2:
|
|
uart_cs2 = b;
|
|
80010ac: 4a3e ldr r2, [pc, #248] @ (80011a8 <HAL_UART_RxCpltCallback+0x19c>)
|
|
80010ae: 7bfb ldrb r3, [r7, #15]
|
|
80010b0: 7013 strb r3, [r2, #0]
|
|
uart_state = (uart_len > 0) ? UART_WAIT_DATA : UART_WAIT_A;
|
|
80010b2: 4b39 ldr r3, [pc, #228] @ (8001198 <HAL_UART_RxCpltCallback+0x18c>)
|
|
80010b4: 781b ldrb r3, [r3, #0]
|
|
80010b6: 2b00 cmp r3, #0
|
|
80010b8: d001 beq.n 80010be <HAL_UART_RxCpltCallback+0xb2>
|
|
80010ba: 2206 movs r2, #6
|
|
80010bc: e000 b.n 80010c0 <HAL_UART_RxCpltCallback+0xb4>
|
|
80010be: 2200 movs r2, #0
|
|
80010c0: 4b33 ldr r3, [pc, #204] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
80010c2: 701a strb r2, [r3, #0]
|
|
if (uart_len == 0) {
|
|
80010c4: 4b34 ldr r3, [pc, #208] @ (8001198 <HAL_UART_RxCpltCallback+0x18c>)
|
|
80010c6: 781b ldrb r3, [r3, #0]
|
|
80010c8: 2b00 cmp r3, #0
|
|
80010ca: d150 bne.n 800116e <HAL_UART_RxCpltCallback+0x162>
|
|
/* No payload — validate empty checksum (cs1=cs2=0 for empty) */
|
|
pending_cmd = uart_cmd;
|
|
80010cc: 4b31 ldr r3, [pc, #196] @ (8001194 <HAL_UART_RxCpltCallback+0x188>)
|
|
80010ce: 781a ldrb r2, [r3, #0]
|
|
80010d0: 4b36 ldr r3, [pc, #216] @ (80011ac <HAL_UART_RxCpltCallback+0x1a0>)
|
|
80010d2: 701a strb r2, [r3, #0]
|
|
pending_msg[0] = '\0';
|
|
80010d4: 4b36 ldr r3, [pc, #216] @ (80011b0 <HAL_UART_RxCpltCallback+0x1a4>)
|
|
80010d6: 2200 movs r2, #0
|
|
80010d8: 701a strb r2, [r3, #0]
|
|
pending_cmd_rdy = 1;
|
|
80010da: 4b36 ldr r3, [pc, #216] @ (80011b4 <HAL_UART_RxCpltCallback+0x1a8>)
|
|
80010dc: 2201 movs r2, #1
|
|
80010de: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
80010e0: e045 b.n 800116e <HAL_UART_RxCpltCallback+0x162>
|
|
case UART_WAIT_DATA:
|
|
uart_buf[uart_idx++] = (char)b;
|
|
80010e2: 4b2e ldr r3, [pc, #184] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
80010e4: 781b ldrb r3, [r3, #0]
|
|
80010e6: 1c5a adds r2, r3, #1
|
|
80010e8: b2d1 uxtb r1, r2
|
|
80010ea: 4a2c ldr r2, [pc, #176] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
80010ec: 7011 strb r1, [r2, #0]
|
|
80010ee: 4619 mov r1, r3
|
|
80010f0: 4a31 ldr r2, [pc, #196] @ (80011b8 <HAL_UART_RxCpltCallback+0x1ac>)
|
|
80010f2: 7bfb ldrb r3, [r7, #15]
|
|
80010f4: 5453 strb r3, [r2, r1]
|
|
uart_cs_acc += b;
|
|
80010f6: 4b2a ldr r3, [pc, #168] @ (80011a0 <HAL_UART_RxCpltCallback+0x194>)
|
|
80010f8: 781a ldrb r2, [r3, #0]
|
|
80010fa: 7bfb ldrb r3, [r7, #15]
|
|
80010fc: 4413 add r3, r2
|
|
80010fe: b2da uxtb r2, r3
|
|
8001100: 4b27 ldr r3, [pc, #156] @ (80011a0 <HAL_UART_RxCpltCallback+0x194>)
|
|
8001102: 701a strb r2, [r3, #0]
|
|
if (uart_idx >= uart_len) {
|
|
8001104: 4b25 ldr r3, [pc, #148] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
8001106: 781a ldrb r2, [r3, #0]
|
|
8001108: 4b23 ldr r3, [pc, #140] @ (8001198 <HAL_UART_RxCpltCallback+0x18c>)
|
|
800110a: 781b ldrb r3, [r3, #0]
|
|
800110c: 429a cmp r2, r3
|
|
800110e: d330 bcc.n 8001172 <HAL_UART_RxCpltCallback+0x166>
|
|
uart_buf[uart_idx] = '\0';
|
|
8001110: 4b22 ldr r3, [pc, #136] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
8001112: 781b ldrb r3, [r3, #0]
|
|
8001114: 461a mov r2, r3
|
|
8001116: 4b28 ldr r3, [pc, #160] @ (80011b8 <HAL_UART_RxCpltCallback+0x1ac>)
|
|
8001118: 2100 movs r1, #0
|
|
800111a: 5499 strb r1, [r3, r2]
|
|
uint8_t cs1c = uart_cs_acc & 0xFF;
|
|
800111c: 4b20 ldr r3, [pc, #128] @ (80011a0 <HAL_UART_RxCpltCallback+0x194>)
|
|
800111e: 781b ldrb r3, [r3, #0]
|
|
8001120: 73bb strb r3, [r7, #14]
|
|
uint8_t cs2c = (~uart_cs_acc) & 0xFF;
|
|
8001122: 4b1f ldr r3, [pc, #124] @ (80011a0 <HAL_UART_RxCpltCallback+0x194>)
|
|
8001124: 781b ldrb r3, [r3, #0]
|
|
8001126: 43db mvns r3, r3
|
|
8001128: 737b strb r3, [r7, #13]
|
|
if (cs1c == uart_cs1 && cs2c == uart_cs2) {
|
|
800112a: 4b1e ldr r3, [pc, #120] @ (80011a4 <HAL_UART_RxCpltCallback+0x198>)
|
|
800112c: 781b ldrb r3, [r3, #0]
|
|
800112e: 7bba ldrb r2, [r7, #14]
|
|
8001130: 429a cmp r2, r3
|
|
8001132: d113 bne.n 800115c <HAL_UART_RxCpltCallback+0x150>
|
|
8001134: 4b1c ldr r3, [pc, #112] @ (80011a8 <HAL_UART_RxCpltCallback+0x19c>)
|
|
8001136: 781b ldrb r3, [r3, #0]
|
|
8001138: 7b7a ldrb r2, [r7, #13]
|
|
800113a: 429a cmp r2, r3
|
|
800113c: d10e bne.n 800115c <HAL_UART_RxCpltCallback+0x150>
|
|
memcpy(pending_msg, uart_buf, uart_idx + 1);
|
|
800113e: 4b17 ldr r3, [pc, #92] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
8001140: 781b ldrb r3, [r3, #0]
|
|
8001142: 3301 adds r3, #1
|
|
8001144: 461a mov r2, r3
|
|
8001146: 491c ldr r1, [pc, #112] @ (80011b8 <HAL_UART_RxCpltCallback+0x1ac>)
|
|
8001148: 4819 ldr r0, [pc, #100] @ (80011b0 <HAL_UART_RxCpltCallback+0x1a4>)
|
|
800114a: f004 fb2d bl 80057a8 <memcpy>
|
|
pending_cmd = uart_cmd;
|
|
800114e: 4b11 ldr r3, [pc, #68] @ (8001194 <HAL_UART_RxCpltCallback+0x188>)
|
|
8001150: 781a ldrb r2, [r3, #0]
|
|
8001152: 4b16 ldr r3, [pc, #88] @ (80011ac <HAL_UART_RxCpltCallback+0x1a0>)
|
|
8001154: 701a strb r2, [r3, #0]
|
|
pending_cmd_rdy = 1;
|
|
8001156: 4b17 ldr r3, [pc, #92] @ (80011b4 <HAL_UART_RxCpltCallback+0x1a8>)
|
|
8001158: 2201 movs r2, #1
|
|
800115a: 701a strb r2, [r3, #0]
|
|
}
|
|
uart_state = UART_WAIT_A;
|
|
800115c: 4b0c ldr r3, [pc, #48] @ (8001190 <HAL_UART_RxCpltCallback+0x184>)
|
|
800115e: 2200 movs r2, #0
|
|
8001160: 701a strb r2, [r3, #0]
|
|
uart_idx = 0;
|
|
8001162: 4b0e ldr r3, [pc, #56] @ (800119c <HAL_UART_RxCpltCallback+0x190>)
|
|
8001164: 2200 movs r2, #0
|
|
8001166: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
8001168: e003 b.n 8001172 <HAL_UART_RxCpltCallback+0x166>
|
|
break;
|
|
800116a: bf00 nop
|
|
800116c: e002 b.n 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
break;
|
|
800116e: bf00 nop
|
|
8001170: e000 b.n 8001174 <HAL_UART_RxCpltCallback+0x168>
|
|
break;
|
|
8001172: bf00 nop
|
|
}
|
|
HAL_UART_Receive_IT(&huart2, &uart_rx_byte, 1);
|
|
8001174: 2201 movs r2, #1
|
|
8001176: 4905 ldr r1, [pc, #20] @ (800118c <HAL_UART_RxCpltCallback+0x180>)
|
|
8001178: 4810 ldr r0, [pc, #64] @ (80011bc <HAL_UART_RxCpltCallback+0x1b0>)
|
|
800117a: f002 fab1 bl 80036e0 <HAL_UART_Receive_IT>
|
|
800117e: e000 b.n 8001182 <HAL_UART_RxCpltCallback+0x176>
|
|
if (huart->Instance != USART2) return;
|
|
8001180: bf00 nop
|
|
}
|
|
8001182: 3710 adds r7, #16
|
|
8001184: 46bd mov sp, r7
|
|
8001186: bd80 pop {r7, pc}
|
|
8001188: 40004400 .word 0x40004400
|
|
800118c: 20000f88 .word 0x20000f88
|
|
8001190: 20001118 .word 0x20001118
|
|
8001194: 20001011 .word 0x20001011
|
|
8001198: 20001010 .word 0x20001010
|
|
800119c: 2000100c .word 0x2000100c
|
|
80011a0: 2000100d .word 0x2000100d
|
|
80011a4: 2000100e .word 0x2000100e
|
|
80011a8: 2000100f .word 0x2000100f
|
|
80011ac: 20001012 .word 0x20001012
|
|
80011b0: 20001014 .word 0x20001014
|
|
80011b4: 20001013 .word 0x20001013
|
|
80011b8: 20000f8c .word 0x20000f8c
|
|
80011bc: 20000098 .word 0x20000098
|
|
|
|
080011c0 <main>:
|
|
|
|
/* USER CODE END 0 */
|
|
|
|
int main(void)
|
|
{
|
|
80011c0: b580 push {r7, lr}
|
|
80011c2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 1 */
|
|
/* USER CODE END 1 */
|
|
|
|
HAL_Init();
|
|
80011c4: f000 fafb bl 80017be <HAL_Init>
|
|
|
|
/* USER CODE BEGIN Init */
|
|
/* USER CODE END Init */
|
|
|
|
SystemClock_Config();
|
|
80011c8: f000 f87c bl 80012c4 <SystemClock_Config>
|
|
|
|
/* USER CODE BEGIN SysInit */
|
|
/* USER CODE END SysInit */
|
|
|
|
MX_GPIO_Init();
|
|
80011cc: f000 f950 bl 8001470 <MX_GPIO_Init>
|
|
MX_SPI1_Init();
|
|
80011d0: f000 f8c4 bl 800135c <MX_SPI1_Init>
|
|
MX_USART2_UART_Init();
|
|
80011d4: f000 f900 bl 80013d8 <MX_USART2_UART_Init>
|
|
|
|
/* USER CODE BEGIN 2 */
|
|
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
|
80011d8: 4b30 ldr r3, [pc, #192] @ (800129c <main+0xdc>)
|
|
80011da: 68db ldr r3, [r3, #12]
|
|
80011dc: 4a2f ldr r2, [pc, #188] @ (800129c <main+0xdc>)
|
|
80011de: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
80011e2: 60d3 str r3, [r2, #12]
|
|
DWT->CYCCNT = 0;
|
|
80011e4: 4b2e ldr r3, [pc, #184] @ (80012a0 <main+0xe0>)
|
|
80011e6: 2200 movs r2, #0
|
|
80011e8: 605a str r2, [r3, #4]
|
|
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
|
|
80011ea: 4b2d ldr r3, [pc, #180] @ (80012a0 <main+0xe0>)
|
|
80011ec: 681b ldr r3, [r3, #0]
|
|
80011ee: 4a2c ldr r2, [pc, #176] @ (80012a0 <main+0xe0>)
|
|
80011f0: f043 0301 orr.w r3, r3, #1
|
|
80011f4: 6013 str r3, [r2, #0]
|
|
|
|
all_rows_off();
|
|
80011f6: f7ff f9cb bl 8000590 <all_rows_off>
|
|
memset(fb, 0, sizeof(fb));
|
|
80011fa: 2254 movs r2, #84 @ 0x54
|
|
80011fc: 2100 movs r1, #0
|
|
80011fe: 4829 ldr r0, [pc, #164] @ (80012a4 <main+0xe4>)
|
|
8001200: f004 faa6 bl 8005750 <memset>
|
|
|
|
HAL_UART_Receive_IT(&huart2, &uart_rx_byte, 1);
|
|
8001204: 2201 movs r2, #1
|
|
8001206: 4928 ldr r1, [pc, #160] @ (80012a8 <main+0xe8>)
|
|
8001208: 4828 ldr r0, [pc, #160] @ (80012ac <main+0xec>)
|
|
800120a: f002 fa69 bl 80036e0 <HAL_UART_Receive_IT>
|
|
|
|
arrive_animation();
|
|
800120e: f7ff fd65 bl 8000cdc <arrive_animation>
|
|
memset(fb, 0, sizeof(fb));
|
|
8001212: 2254 movs r2, #84 @ 0x54
|
|
8001214: 2100 movs r1, #0
|
|
8001216: 4823 ldr r0, [pc, #140] @ (80012a4 <main+0xe4>)
|
|
8001218: f004 fa9a bl 8005750 <memset>
|
|
current_cmd = 0;
|
|
800121c: 4b24 ldr r3, [pc, #144] @ (80012b0 <main+0xf0>)
|
|
800121e: 2200 movs r2, #0
|
|
8001220: 701a strb r2, [r3, #0]
|
|
/* USER CODE END 2 */
|
|
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
if (pending_cmd_rdy) {
|
|
8001222: 4b24 ldr r3, [pc, #144] @ (80012b4 <main+0xf4>)
|
|
8001224: 781b ldrb r3, [r3, #0]
|
|
8001226: b2db uxtb r3, r3
|
|
8001228: 2b00 cmp r3, #0
|
|
800122a: d00f beq.n 800124c <main+0x8c>
|
|
pending_cmd_rdy = 0;
|
|
800122c: 4b21 ldr r3, [pc, #132] @ (80012b4 <main+0xf4>)
|
|
800122e: 2200 movs r2, #0
|
|
8001230: 701a strb r2, [r3, #0]
|
|
current_cmd = pending_cmd;
|
|
8001232: 4b21 ldr r3, [pc, #132] @ (80012b8 <main+0xf8>)
|
|
8001234: 781b ldrb r3, [r3, #0]
|
|
8001236: b2da uxtb r2, r3
|
|
8001238: 4b1d ldr r3, [pc, #116] @ (80012b0 <main+0xf0>)
|
|
800123a: 701a strb r2, [r3, #0]
|
|
memcpy(message, pending_msg, sizeof(pending_msg));
|
|
800123c: 4a1f ldr r2, [pc, #124] @ (80012bc <main+0xfc>)
|
|
800123e: 4b20 ldr r3, [pc, #128] @ (80012c0 <main+0x100>)
|
|
8001240: 4610 mov r0, r2
|
|
8001242: 4619 mov r1, r3
|
|
8001244: 2380 movs r3, #128 @ 0x80
|
|
8001246: 461a mov r2, r3
|
|
8001248: f004 faae bl 80057a8 <memcpy>
|
|
}
|
|
|
|
switch (current_cmd) {
|
|
800124c: 4b18 ldr r3, [pc, #96] @ (80012b0 <main+0xf0>)
|
|
800124e: 781b ldrb r3, [r3, #0]
|
|
8001250: 3b01 subs r3, #1
|
|
8001252: 2b03 cmp r3, #3
|
|
8001254: d81e bhi.n 8001294 <main+0xd4>
|
|
8001256: a201 add r2, pc, #4 @ (adr r2, 800125c <main+0x9c>)
|
|
8001258: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800125c: 0800126d .word 0x0800126d
|
|
8001260: 08001283 .word 0x08001283
|
|
8001264: 08001289 .word 0x08001289
|
|
8001268: 0800128f .word 0x0800128f
|
|
case CMD_CLEAR:
|
|
memset(fb, 0, sizeof(fb));
|
|
800126c: 2254 movs r2, #84 @ 0x54
|
|
800126e: 2100 movs r1, #0
|
|
8001270: 480c ldr r0, [pc, #48] @ (80012a4 <main+0xe4>)
|
|
8001272: f004 fa6d bl 8005750 <memset>
|
|
display_refresh();
|
|
8001276: f7ff f9ab bl 80005d0 <display_refresh>
|
|
current_cmd = 0;
|
|
800127a: 4b0d ldr r3, [pc, #52] @ (80012b0 <main+0xf0>)
|
|
800127c: 2200 movs r2, #0
|
|
800127e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001280: e00b b.n 800129a <main+0xda>
|
|
|
|
case CMD_VALUES:
|
|
run_values();
|
|
8001282: f7ff fddf bl 8000e44 <run_values>
|
|
break;
|
|
8001286: e008 b.n 800129a <main+0xda>
|
|
|
|
case CMD_HW_DEPT:
|
|
run_hw_dept();
|
|
8001288: f7ff fe36 bl 8000ef8 <run_hw_dept>
|
|
break;
|
|
800128c: e005 b.n 800129a <main+0xda>
|
|
|
|
case CMD_SCROLL:
|
|
run_scroll();
|
|
800128e: f7ff fe79 bl 8000f84 <run_scroll>
|
|
break;
|
|
8001292: e002 b.n 800129a <main+0xda>
|
|
|
|
default:
|
|
display_refresh();
|
|
8001294: f7ff f99c bl 80005d0 <display_refresh>
|
|
break;
|
|
8001298: bf00 nop
|
|
if (pending_cmd_rdy) {
|
|
800129a: e7c2 b.n 8001222 <main+0x62>
|
|
800129c: e000edf0 .word 0xe000edf0
|
|
80012a0: e0001000 .word 0xe0001000
|
|
80012a4: 2000012c .word 0x2000012c
|
|
80012a8: 20000f88 .word 0x20000f88
|
|
80012ac: 20000098 .word 0x20000098
|
|
80012b0: 20001094 .word 0x20001094
|
|
80012b4: 20001013 .word 0x20001013
|
|
80012b8: 20001012 .word 0x20001012
|
|
80012bc: 20001098 .word 0x20001098
|
|
80012c0: 20001014 .word 0x20001014
|
|
|
|
080012c4 <SystemClock_Config>:
|
|
}
|
|
/* USER CODE END 3 */
|
|
}
|
|
|
|
void SystemClock_Config(void)
|
|
{
|
|
80012c4: b580 push {r7, lr}
|
|
80012c6: b094 sub sp, #80 @ 0x50
|
|
80012c8: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
80012ca: f107 0318 add.w r3, r7, #24
|
|
80012ce: 2238 movs r2, #56 @ 0x38
|
|
80012d0: 2100 movs r1, #0
|
|
80012d2: 4618 mov r0, r3
|
|
80012d4: f004 fa3c bl 8005750 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80012d8: 1d3b adds r3, r7, #4
|
|
80012da: 2200 movs r2, #0
|
|
80012dc: 601a str r2, [r3, #0]
|
|
80012de: 605a str r2, [r3, #4]
|
|
80012e0: 609a str r2, [r3, #8]
|
|
80012e2: 60da str r2, [r3, #12]
|
|
80012e4: 611a str r2, [r3, #16]
|
|
|
|
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
|
|
80012e6: 2000 movs r0, #0
|
|
80012e8: f000 fe52 bl 8001f90 <HAL_PWREx_ControlVoltageScaling>
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
80012ec: 2302 movs r3, #2
|
|
80012ee: 61bb str r3, [r7, #24]
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80012f0: f44f 7380 mov.w r3, #256 @ 0x100
|
|
80012f4: 627b str r3, [r7, #36] @ 0x24
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
80012f6: 2340 movs r3, #64 @ 0x40
|
|
80012f8: 62bb str r3, [r7, #40] @ 0x28
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80012fa: 2302 movs r3, #2
|
|
80012fc: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
|
80012fe: 2302 movs r3, #2
|
|
8001300: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
|
|
8001302: 2304 movs r3, #4
|
|
8001304: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 85;
|
|
8001306: 2355 movs r3, #85 @ 0x55
|
|
8001308: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
800130a: 2302 movs r3, #2
|
|
800130c: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
800130e: 2302 movs r3, #2
|
|
8001310: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
8001312: 2302 movs r3, #2
|
|
8001314: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) Error_Handler();
|
|
8001316: f107 0318 add.w r3, r7, #24
|
|
800131a: 4618 mov r0, r3
|
|
800131c: f000 feec bl 80020f8 <HAL_RCC_OscConfig>
|
|
8001320: 4603 mov r3, r0
|
|
8001322: 2b00 cmp r3, #0
|
|
8001324: d001 beq.n 800132a <SystemClock_Config+0x66>
|
|
8001326: f000 f909 bl 800153c <Error_Handler>
|
|
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
800132a: 230f movs r3, #15
|
|
800132c: 607b str r3, [r7, #4]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
800132e: 2303 movs r3, #3
|
|
8001330: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8001332: 2300 movs r3, #0
|
|
8001334: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8001336: 2300 movs r3, #0
|
|
8001338: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
800133a: 2300 movs r3, #0
|
|
800133c: 617b str r3, [r7, #20]
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) Error_Handler();
|
|
800133e: 1d3b adds r3, r7, #4
|
|
8001340: 2104 movs r1, #4
|
|
8001342: 4618 mov r0, r3
|
|
8001344: f001 f9ea bl 800271c <HAL_RCC_ClockConfig>
|
|
8001348: 4603 mov r3, r0
|
|
800134a: 2b00 cmp r3, #0
|
|
800134c: d001 beq.n 8001352 <SystemClock_Config+0x8e>
|
|
800134e: f000 f8f5 bl 800153c <Error_Handler>
|
|
}
|
|
8001352: bf00 nop
|
|
8001354: 3750 adds r7, #80 @ 0x50
|
|
8001356: 46bd mov sp, r7
|
|
8001358: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800135c <MX_SPI1_Init>:
|
|
|
|
static void MX_SPI1_Init(void)
|
|
{
|
|
800135c: b580 push {r7, lr}
|
|
800135e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SPI1_Init 0 */
|
|
/* USER CODE END SPI1_Init 0 */
|
|
/* USER CODE BEGIN SPI1_Init 1 */
|
|
/* USER CODE END SPI1_Init 1 */
|
|
hspi1.Instance = SPI1;
|
|
8001360: 4b1b ldr r3, [pc, #108] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001362: 4a1c ldr r2, [pc, #112] @ (80013d4 <MX_SPI1_Init+0x78>)
|
|
8001364: 601a str r2, [r3, #0]
|
|
hspi1.Init.Mode = SPI_MODE_MASTER;
|
|
8001366: 4b1a ldr r3, [pc, #104] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001368: f44f 7282 mov.w r2, #260 @ 0x104
|
|
800136c: 605a str r2, [r3, #4]
|
|
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
|
|
800136e: 4b18 ldr r3, [pc, #96] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001370: 2200 movs r2, #0
|
|
8001372: 609a str r2, [r3, #8]
|
|
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
|
|
8001374: 4b16 ldr r3, [pc, #88] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001376: f44f 62e0 mov.w r2, #1792 @ 0x700
|
|
800137a: 60da str r2, [r3, #12]
|
|
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
800137c: 4b14 ldr r3, [pc, #80] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
800137e: 2200 movs r2, #0
|
|
8001380: 611a str r2, [r3, #16]
|
|
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8001382: 4b13 ldr r3, [pc, #76] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001384: 2200 movs r2, #0
|
|
8001386: 615a str r2, [r3, #20]
|
|
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
|
|
8001388: 4b11 ldr r3, [pc, #68] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
800138a: f44f 2280 mov.w r2, #262144 @ 0x40000
|
|
800138e: 619a str r2, [r3, #24]
|
|
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
|
|
8001390: 4b0f ldr r3, [pc, #60] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001392: 2220 movs r2, #32
|
|
8001394: 61da str r2, [r3, #28]
|
|
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
8001396: 4b0e ldr r3, [pc, #56] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
8001398: 2200 movs r2, #0
|
|
800139a: 621a str r2, [r3, #32]
|
|
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
800139c: 4b0c ldr r3, [pc, #48] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
800139e: 2200 movs r2, #0
|
|
80013a0: 625a str r2, [r3, #36] @ 0x24
|
|
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
80013a2: 4b0b ldr r3, [pc, #44] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
80013a4: 2200 movs r2, #0
|
|
80013a6: 629a str r2, [r3, #40] @ 0x28
|
|
hspi1.Init.CRCPolynomial = 7;
|
|
80013a8: 4b09 ldr r3, [pc, #36] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
80013aa: 2207 movs r2, #7
|
|
80013ac: 62da str r2, [r3, #44] @ 0x2c
|
|
hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
|
80013ae: 4b08 ldr r3, [pc, #32] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
80013b0: 2200 movs r2, #0
|
|
80013b2: 631a str r2, [r3, #48] @ 0x30
|
|
hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
|
80013b4: 4b06 ldr r3, [pc, #24] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
80013b6: 2208 movs r2, #8
|
|
80013b8: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_SPI_Init(&hspi1) != HAL_OK) Error_Handler();
|
|
80013ba: 4805 ldr r0, [pc, #20] @ (80013d0 <MX_SPI1_Init+0x74>)
|
|
80013bc: f001 fdba bl 8002f34 <HAL_SPI_Init>
|
|
80013c0: 4603 mov r3, r0
|
|
80013c2: 2b00 cmp r3, #0
|
|
80013c4: d001 beq.n 80013ca <MX_SPI1_Init+0x6e>
|
|
80013c6: f000 f8b9 bl 800153c <Error_Handler>
|
|
/* USER CODE BEGIN SPI1_Init 2 */
|
|
/* USER CODE END SPI1_Init 2 */
|
|
}
|
|
80013ca: bf00 nop
|
|
80013cc: bd80 pop {r7, pc}
|
|
80013ce: bf00 nop
|
|
80013d0: 20000034 .word 0x20000034
|
|
80013d4: 40013000 .word 0x40013000
|
|
|
|
080013d8 <MX_USART2_UART_Init>:
|
|
|
|
static void MX_USART2_UART_Init(void)
|
|
{
|
|
80013d8: b580 push {r7, lr}
|
|
80013da: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART2_Init 0 */
|
|
/* USER CODE END USART2_Init 0 */
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
80013dc: 4b22 ldr r3, [pc, #136] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
80013de: 4a23 ldr r2, [pc, #140] @ (800146c <MX_USART2_UART_Init+0x94>)
|
|
80013e0: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
80013e2: 4b21 ldr r3, [pc, #132] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
80013e4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
80013e8: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80013ea: 4b1f ldr r3, [pc, #124] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
80013ec: 2200 movs r2, #0
|
|
80013ee: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
80013f0: 4b1d ldr r3, [pc, #116] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
80013f2: 2200 movs r2, #0
|
|
80013f4: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
80013f6: 4b1c ldr r3, [pc, #112] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
80013f8: 2200 movs r2, #0
|
|
80013fa: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
80013fc: 4b1a ldr r3, [pc, #104] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
80013fe: 220c movs r2, #12
|
|
8001400: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001402: 4b19 ldr r3, [pc, #100] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001404: 2200 movs r2, #0
|
|
8001406: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001408: 4b17 ldr r3, [pc, #92] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
800140a: 2200 movs r2, #0
|
|
800140c: 61da str r2, [r3, #28]
|
|
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
800140e: 4b16 ldr r3, [pc, #88] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001410: 2200 movs r2, #0
|
|
8001412: 621a str r2, [r3, #32]
|
|
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
|
8001414: 4b14 ldr r3, [pc, #80] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001416: 2200 movs r2, #0
|
|
8001418: 625a str r2, [r3, #36] @ 0x24
|
|
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
800141a: 4b13 ldr r3, [pc, #76] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
800141c: 2200 movs r2, #0
|
|
800141e: 629a str r2, [r3, #40] @ 0x28
|
|
if (HAL_UART_Init(&huart2) != HAL_OK) Error_Handler();
|
|
8001420: 4811 ldr r0, [pc, #68] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001422: f002 f90d bl 8003640 <HAL_UART_Init>
|
|
8001426: 4603 mov r3, r0
|
|
8001428: 2b00 cmp r3, #0
|
|
800142a: d001 beq.n 8001430 <MX_USART2_UART_Init+0x58>
|
|
800142c: f000 f886 bl 800153c <Error_Handler>
|
|
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) Error_Handler();
|
|
8001430: 2100 movs r1, #0
|
|
8001432: 480d ldr r0, [pc, #52] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001434: f004 f8c1 bl 80055ba <HAL_UARTEx_SetTxFifoThreshold>
|
|
8001438: 4603 mov r3, r0
|
|
800143a: 2b00 cmp r3, #0
|
|
800143c: d001 beq.n 8001442 <MX_USART2_UART_Init+0x6a>
|
|
800143e: f000 f87d bl 800153c <Error_Handler>
|
|
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) Error_Handler();
|
|
8001442: 2100 movs r1, #0
|
|
8001444: 4808 ldr r0, [pc, #32] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001446: f004 f8f6 bl 8005636 <HAL_UARTEx_SetRxFifoThreshold>
|
|
800144a: 4603 mov r3, r0
|
|
800144c: 2b00 cmp r3, #0
|
|
800144e: d001 beq.n 8001454 <MX_USART2_UART_Init+0x7c>
|
|
8001450: f000 f874 bl 800153c <Error_Handler>
|
|
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) Error_Handler();
|
|
8001454: 4804 ldr r0, [pc, #16] @ (8001468 <MX_USART2_UART_Init+0x90>)
|
|
8001456: f004 f877 bl 8005548 <HAL_UARTEx_DisableFifoMode>
|
|
800145a: 4603 mov r3, r0
|
|
800145c: 2b00 cmp r3, #0
|
|
800145e: d001 beq.n 8001464 <MX_USART2_UART_Init+0x8c>
|
|
8001460: f000 f86c bl 800153c <Error_Handler>
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
/* USER CODE END USART2_Init 2 */
|
|
}
|
|
8001464: bf00 nop
|
|
8001466: bd80 pop {r7, pc}
|
|
8001468: 20000098 .word 0x20000098
|
|
800146c: 40004400 .word 0x40004400
|
|
|
|
08001470 <MX_GPIO_Init>:
|
|
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8001470: b580 push {r7, lr}
|
|
8001472: b088 sub sp, #32
|
|
8001474: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001476: f107 030c add.w r3, r7, #12
|
|
800147a: 2200 movs r2, #0
|
|
800147c: 601a str r2, [r3, #0]
|
|
800147e: 605a str r2, [r3, #4]
|
|
8001480: 609a str r2, [r3, #8]
|
|
8001482: 60da str r2, [r3, #12]
|
|
8001484: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001486: 4b2b ldr r3, [pc, #172] @ (8001534 <MX_GPIO_Init+0xc4>)
|
|
8001488: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800148a: 4a2a ldr r2, [pc, #168] @ (8001534 <MX_GPIO_Init+0xc4>)
|
|
800148c: f043 0301 orr.w r3, r3, #1
|
|
8001490: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001492: 4b28 ldr r3, [pc, #160] @ (8001534 <MX_GPIO_Init+0xc4>)
|
|
8001494: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001496: f003 0301 and.w r3, r3, #1
|
|
800149a: 60bb str r3, [r7, #8]
|
|
800149c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800149e: 4b25 ldr r3, [pc, #148] @ (8001534 <MX_GPIO_Init+0xc4>)
|
|
80014a0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80014a2: 4a24 ldr r2, [pc, #144] @ (8001534 <MX_GPIO_Init+0xc4>)
|
|
80014a4: f043 0302 orr.w r3, r3, #2
|
|
80014a8: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80014aa: 4b22 ldr r3, [pc, #136] @ (8001534 <MX_GPIO_Init+0xc4>)
|
|
80014ac: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80014ae: f003 0302 and.w r3, r3, #2
|
|
80014b2: 607b str r3, [r7, #4]
|
|
80014b4: 687b ldr r3, [r7, #4]
|
|
|
|
HAL_GPIO_WritePin(GPIOA, ROW_1_Pin|ROW_2_Pin|ROW_6_Pin|ROW_5_Pin, GPIO_PIN_SET);
|
|
80014b6: 2201 movs r2, #1
|
|
80014b8: f640 1103 movw r1, #2307 @ 0x903
|
|
80014bc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80014c0: f000 fd4e bl 8001f60 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(GPIOB, ROW_0_Pin|ROW_3_Pin|ROW_4_Pin|LED_Pin, GPIO_PIN_SET);
|
|
80014c4: 2201 movs r2, #1
|
|
80014c6: f240 1131 movw r1, #305 @ 0x131
|
|
80014ca: 481b ldr r0, [pc, #108] @ (8001538 <MX_GPIO_Init+0xc8>)
|
|
80014cc: f000 fd48 bl 8001f60 <HAL_GPIO_WritePin>
|
|
|
|
GPIO_InitStruct.Pin = ROW_1_Pin|ROW_2_Pin|ROW_6_Pin|ROW_5_Pin;
|
|
80014d0: f640 1303 movw r3, #2307 @ 0x903
|
|
80014d4: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80014d6: 2301 movs r3, #1
|
|
80014d8: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80014da: 2300 movs r3, #0
|
|
80014dc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
80014de: 2302 movs r3, #2
|
|
80014e0: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80014e2: f107 030c add.w r3, r7, #12
|
|
80014e6: 4619 mov r1, r3
|
|
80014e8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80014ec: f000 fbac bl 8001c48 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = ROW_0_Pin|ROW_3_Pin|ROW_4_Pin;
|
|
80014f0: 2331 movs r3, #49 @ 0x31
|
|
80014f2: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80014f4: 2301 movs r3, #1
|
|
80014f6: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80014f8: 2300 movs r3, #0
|
|
80014fa: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
80014fc: 2302 movs r3, #2
|
|
80014fe: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001500: f107 030c add.w r3, r7, #12
|
|
8001504: 4619 mov r1, r3
|
|
8001506: 480c ldr r0, [pc, #48] @ (8001538 <MX_GPIO_Init+0xc8>)
|
|
8001508: f000 fb9e bl 8001c48 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = LED_Pin;
|
|
800150c: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8001510: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001512: 2301 movs r3, #1
|
|
8001514: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001516: 2300 movs r3, #0
|
|
8001518: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800151a: 2300 movs r3, #0
|
|
800151c: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
|
|
800151e: f107 030c add.w r3, r7, #12
|
|
8001522: 4619 mov r1, r3
|
|
8001524: 4804 ldr r0, [pc, #16] @ (8001538 <MX_GPIO_Init+0xc8>)
|
|
8001526: f000 fb8f bl 8001c48 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
800152a: bf00 nop
|
|
800152c: 3720 adds r7, #32
|
|
800152e: 46bd mov sp, r7
|
|
8001530: bd80 pop {r7, pc}
|
|
8001532: bf00 nop
|
|
8001534: 40021000 .word 0x40021000
|
|
8001538: 48000400 .word 0x48000400
|
|
|
|
0800153c <Error_Handler>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
/* USER CODE END 4 */
|
|
|
|
void Error_Handler(void)
|
|
{
|
|
800153c: b480 push {r7}
|
|
800153e: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001540: b672 cpsid i
|
|
}
|
|
8001542: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
__disable_irq();
|
|
while (1) {}
|
|
8001544: bf00 nop
|
|
8001546: e7fd b.n 8001544 <Error_Handler+0x8>
|
|
|
|
08001548 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8001548: b580 push {r7, lr}
|
|
800154a: b082 sub sp, #8
|
|
800154c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800154e: 4b0f ldr r3, [pc, #60] @ (800158c <HAL_MspInit+0x44>)
|
|
8001550: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001552: 4a0e ldr r2, [pc, #56] @ (800158c <HAL_MspInit+0x44>)
|
|
8001554: f043 0301 orr.w r3, r3, #1
|
|
8001558: 6613 str r3, [r2, #96] @ 0x60
|
|
800155a: 4b0c ldr r3, [pc, #48] @ (800158c <HAL_MspInit+0x44>)
|
|
800155c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800155e: f003 0301 and.w r3, r3, #1
|
|
8001562: 607b str r3, [r7, #4]
|
|
8001564: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001566: 4b09 ldr r3, [pc, #36] @ (800158c <HAL_MspInit+0x44>)
|
|
8001568: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800156a: 4a08 ldr r2, [pc, #32] @ (800158c <HAL_MspInit+0x44>)
|
|
800156c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001570: 6593 str r3, [r2, #88] @ 0x58
|
|
8001572: 4b06 ldr r3, [pc, #24] @ (800158c <HAL_MspInit+0x44>)
|
|
8001574: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001576: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800157a: 603b str r3, [r7, #0]
|
|
800157c: 683b ldr r3, [r7, #0]
|
|
|
|
/* System interrupt init*/
|
|
|
|
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
|
|
*/
|
|
HAL_PWREx_DisableUCPDDeadBattery();
|
|
800157e: f000 fdab bl 80020d8 <HAL_PWREx_DisableUCPDDeadBattery>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8001582: bf00 nop
|
|
8001584: 3708 adds r7, #8
|
|
8001586: 46bd mov sp, r7
|
|
8001588: bd80 pop {r7, pc}
|
|
800158a: bf00 nop
|
|
800158c: 40021000 .word 0x40021000
|
|
|
|
08001590 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
8001590: b580 push {r7, lr}
|
|
8001592: b08a sub sp, #40 @ 0x28
|
|
8001594: af00 add r7, sp, #0
|
|
8001596: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001598: f107 0314 add.w r3, r7, #20
|
|
800159c: 2200 movs r2, #0
|
|
800159e: 601a str r2, [r3, #0]
|
|
80015a0: 605a str r2, [r3, #4]
|
|
80015a2: 609a str r2, [r3, #8]
|
|
80015a4: 60da str r2, [r3, #12]
|
|
80015a6: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI1)
|
|
80015a8: 687b ldr r3, [r7, #4]
|
|
80015aa: 681b ldr r3, [r3, #0]
|
|
80015ac: 4a17 ldr r2, [pc, #92] @ (800160c <HAL_SPI_MspInit+0x7c>)
|
|
80015ae: 4293 cmp r3, r2
|
|
80015b0: d128 bne.n 8001604 <HAL_SPI_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN SPI1_MspInit 0 */
|
|
|
|
/* USER CODE END SPI1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI1_CLK_ENABLE();
|
|
80015b2: 4b17 ldr r3, [pc, #92] @ (8001610 <HAL_SPI_MspInit+0x80>)
|
|
80015b4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80015b6: 4a16 ldr r2, [pc, #88] @ (8001610 <HAL_SPI_MspInit+0x80>)
|
|
80015b8: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
80015bc: 6613 str r3, [r2, #96] @ 0x60
|
|
80015be: 4b14 ldr r3, [pc, #80] @ (8001610 <HAL_SPI_MspInit+0x80>)
|
|
80015c0: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80015c2: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
80015c6: 613b str r3, [r7, #16]
|
|
80015c8: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80015ca: 4b11 ldr r3, [pc, #68] @ (8001610 <HAL_SPI_MspInit+0x80>)
|
|
80015cc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80015ce: 4a10 ldr r2, [pc, #64] @ (8001610 <HAL_SPI_MspInit+0x80>)
|
|
80015d0: f043 0301 orr.w r3, r3, #1
|
|
80015d4: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80015d6: 4b0e ldr r3, [pc, #56] @ (8001610 <HAL_SPI_MspInit+0x80>)
|
|
80015d8: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80015da: f003 0301 and.w r3, r3, #1
|
|
80015de: 60fb str r3, [r7, #12]
|
|
80015e0: 68fb ldr r3, [r7, #12]
|
|
/**SPI1 GPIO Configuration
|
|
PA4 ------> SPI1_NSS
|
|
PA5 ------> SPI1_SCK
|
|
PA7 ------> SPI1_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7;
|
|
80015e2: 23b0 movs r3, #176 @ 0xb0
|
|
80015e4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80015e6: 2302 movs r3, #2
|
|
80015e8: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80015ea: 2300 movs r3, #0
|
|
80015ec: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80015ee: 2300 movs r3, #0
|
|
80015f0: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
|
|
80015f2: 2305 movs r3, #5
|
|
80015f4: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80015f6: f107 0314 add.w r3, r7, #20
|
|
80015fa: 4619 mov r1, r3
|
|
80015fc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001600: f000 fb22 bl 8001c48 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END SPI1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001604: bf00 nop
|
|
8001606: 3728 adds r7, #40 @ 0x28
|
|
8001608: 46bd mov sp, r7
|
|
800160a: bd80 pop {r7, pc}
|
|
800160c: 40013000 .word 0x40013000
|
|
8001610: 40021000 .word 0x40021000
|
|
|
|
08001614 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8001614: b580 push {r7, lr}
|
|
8001616: b09a sub sp, #104 @ 0x68
|
|
8001618: af00 add r7, sp, #0
|
|
800161a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800161c: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001620: 2200 movs r2, #0
|
|
8001622: 601a str r2, [r3, #0]
|
|
8001624: 605a str r2, [r3, #4]
|
|
8001626: 609a str r2, [r3, #8]
|
|
8001628: 60da str r2, [r3, #12]
|
|
800162a: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
800162c: f107 0310 add.w r3, r7, #16
|
|
8001630: 2244 movs r2, #68 @ 0x44
|
|
8001632: 2100 movs r1, #0
|
|
8001634: 4618 mov r0, r3
|
|
8001636: f004 f88b bl 8005750 <memset>
|
|
if(huart->Instance==USART2)
|
|
800163a: 687b ldr r3, [r7, #4]
|
|
800163c: 681b ldr r3, [r3, #0]
|
|
800163e: 4a23 ldr r2, [pc, #140] @ (80016cc <HAL_UART_MspInit+0xb8>)
|
|
8001640: 4293 cmp r3, r2
|
|
8001642: d13e bne.n 80016c2 <HAL_UART_MspInit+0xae>
|
|
|
|
/* USER CODE END USART2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
|
|
8001644: 2302 movs r3, #2
|
|
8001646: 613b str r3, [r7, #16]
|
|
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
|
|
8001648: 2300 movs r3, #0
|
|
800164a: 61bb str r3, [r7, #24]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
800164c: f107 0310 add.w r3, r7, #16
|
|
8001650: 4618 mov r0, r3
|
|
8001652: f001 fa7f bl 8002b54 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001656: 4603 mov r3, r0
|
|
8001658: 2b00 cmp r3, #0
|
|
800165a: d001 beq.n 8001660 <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
800165c: f7ff ff6e bl 800153c <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
8001660: 4b1b ldr r3, [pc, #108] @ (80016d0 <HAL_UART_MspInit+0xbc>)
|
|
8001662: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001664: 4a1a ldr r2, [pc, #104] @ (80016d0 <HAL_UART_MspInit+0xbc>)
|
|
8001666: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
800166a: 6593 str r3, [r2, #88] @ 0x58
|
|
800166c: 4b18 ldr r3, [pc, #96] @ (80016d0 <HAL_UART_MspInit+0xbc>)
|
|
800166e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001670: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001674: 60fb str r3, [r7, #12]
|
|
8001676: 68fb ldr r3, [r7, #12]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001678: 4b15 ldr r3, [pc, #84] @ (80016d0 <HAL_UART_MspInit+0xbc>)
|
|
800167a: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800167c: 4a14 ldr r2, [pc, #80] @ (80016d0 <HAL_UART_MspInit+0xbc>)
|
|
800167e: f043 0301 orr.w r3, r3, #1
|
|
8001682: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001684: 4b12 ldr r3, [pc, #72] @ (80016d0 <HAL_UART_MspInit+0xbc>)
|
|
8001686: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001688: f003 0301 and.w r3, r3, #1
|
|
800168c: 60bb str r3, [r7, #8]
|
|
800168e: 68bb ldr r3, [r7, #8]
|
|
/**USART2 GPIO Configuration
|
|
PA2 ------> USART2_TX
|
|
PA3 ------> USART2_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin;
|
|
8001690: 230c movs r3, #12
|
|
8001692: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001694: 2302 movs r3, #2
|
|
8001696: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001698: 2300 movs r3, #0
|
|
800169a: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800169c: 2300 movs r3, #0
|
|
800169e: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
80016a0: 2307 movs r3, #7
|
|
80016a2: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80016a4: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
80016a8: 4619 mov r1, r3
|
|
80016aa: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80016ae: f000 facb bl 8001c48 <HAL_GPIO_Init>
|
|
|
|
/* USART2 interrupt Init */
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
|
|
80016b2: 2200 movs r2, #0
|
|
80016b4: 2100 movs r1, #0
|
|
80016b6: 2026 movs r0, #38 @ 0x26
|
|
80016b8: f000 f9cd bl 8001a56 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
80016bc: 2026 movs r0, #38 @ 0x26
|
|
80016be: f000 f9e4 bl 8001a8a <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80016c2: bf00 nop
|
|
80016c4: 3768 adds r7, #104 @ 0x68
|
|
80016c6: 46bd mov sp, r7
|
|
80016c8: bd80 pop {r7, pc}
|
|
80016ca: bf00 nop
|
|
80016cc: 40004400 .word 0x40004400
|
|
80016d0: 40021000 .word 0x40021000
|
|
|
|
080016d4 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80016d4: b480 push {r7}
|
|
80016d6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80016d8: bf00 nop
|
|
80016da: e7fd b.n 80016d8 <NMI_Handler+0x4>
|
|
|
|
080016dc <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80016dc: b480 push {r7}
|
|
80016de: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80016e0: bf00 nop
|
|
80016e2: e7fd b.n 80016e0 <HardFault_Handler+0x4>
|
|
|
|
080016e4 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80016e4: b480 push {r7}
|
|
80016e6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80016e8: bf00 nop
|
|
80016ea: e7fd b.n 80016e8 <MemManage_Handler+0x4>
|
|
|
|
080016ec <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
80016ec: b480 push {r7}
|
|
80016ee: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
80016f0: bf00 nop
|
|
80016f2: e7fd b.n 80016f0 <BusFault_Handler+0x4>
|
|
|
|
080016f4 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
80016f4: b480 push {r7}
|
|
80016f6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
80016f8: bf00 nop
|
|
80016fa: e7fd b.n 80016f8 <UsageFault_Handler+0x4>
|
|
|
|
080016fc <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
80016fc: b480 push {r7}
|
|
80016fe: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8001700: bf00 nop
|
|
8001702: 46bd mov sp, r7
|
|
8001704: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001708: 4770 bx lr
|
|
|
|
0800170a <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800170a: b480 push {r7}
|
|
800170c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800170e: bf00 nop
|
|
8001710: 46bd mov sp, r7
|
|
8001712: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001716: 4770 bx lr
|
|
|
|
08001718 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8001718: b480 push {r7}
|
|
800171a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
800171c: bf00 nop
|
|
800171e: 46bd mov sp, r7
|
|
8001720: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001724: 4770 bx lr
|
|
|
|
08001726 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8001726: b580 push {r7, lr}
|
|
8001728: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
800172a: f000 f89b bl 8001864 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
800172e: bf00 nop
|
|
8001730: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001734 <USART2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
|
|
*/
|
|
void USART2_IRQHandler(void)
|
|
{
|
|
8001734: b580 push {r7, lr}
|
|
8001736: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
|
|
|
/* USER CODE END USART2_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart2);
|
|
8001738: 4802 ldr r0, [pc, #8] @ (8001744 <USART2_IRQHandler+0x10>)
|
|
800173a: f002 f81d bl 8003778 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
|
|
|
/* USER CODE END USART2_IRQn 1 */
|
|
}
|
|
800173e: bf00 nop
|
|
8001740: bd80 pop {r7, pc}
|
|
8001742: bf00 nop
|
|
8001744: 20000098 .word 0x20000098
|
|
|
|
08001748 <SystemInit>:
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8001748: b480 push {r7}
|
|
800174a: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
|
|
800174c: 4b06 ldr r3, [pc, #24] @ (8001768 <SystemInit+0x20>)
|
|
800174e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8001752: 4a05 ldr r2, [pc, #20] @ (8001768 <SystemInit+0x20>)
|
|
8001754: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8001758: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
800175c: bf00 nop
|
|
800175e: 46bd mov sp, r7
|
|
8001760: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001764: 4770 bx lr
|
|
8001766: bf00 nop
|
|
8001768: e000ed00 .word 0xe000ed00
|
|
|
|
0800176c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
800176c: 480d ldr r0, [pc, #52] @ (80017a4 <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
800176e: 4685 mov sp, r0
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001770: f7ff ffea bl 8001748 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001774: 480c ldr r0, [pc, #48] @ (80017a8 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8001776: 490d ldr r1, [pc, #52] @ (80017ac <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8001778: 4a0d ldr r2, [pc, #52] @ (80017b0 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
800177a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800177c: e002 b.n 8001784 <LoopCopyDataInit>
|
|
|
|
0800177e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800177e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001780: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001782: 3304 adds r3, #4
|
|
|
|
08001784 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001784: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001786: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001788: d3f9 bcc.n 800177e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800178a: 4a0a ldr r2, [pc, #40] @ (80017b4 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
800178c: 4c0a ldr r4, [pc, #40] @ (80017b8 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
800178e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001790: e001 b.n 8001796 <LoopFillZerobss>
|
|
|
|
08001792 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001792: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001794: 3204 adds r2, #4
|
|
|
|
08001796 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001796: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001798: d3fb bcc.n 8001792 <FillZerobss>
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800179a: f003 ffe1 bl 8005760 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800179e: f7ff fd0f bl 80011c0 <main>
|
|
|
|
080017a2 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
80017a2: e7fe b.n 80017a2 <LoopForever>
|
|
ldr r0, =_estack
|
|
80017a4: 20008000 .word 0x20008000
|
|
ldr r0, =_sdata
|
|
80017a8: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
80017ac: 20000018 .word 0x20000018
|
|
ldr r2, =_sidata
|
|
80017b0: 08005b10 .word 0x08005b10
|
|
ldr r2, =_sbss
|
|
80017b4: 20000018 .word 0x20000018
|
|
ldr r4, =_ebss
|
|
80017b8: 20001120 .word 0x20001120
|
|
|
|
080017bc <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80017bc: e7fe b.n 80017bc <ADC1_2_IRQHandler>
|
|
|
|
080017be <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80017be: b580 push {r7, lr}
|
|
80017c0: b082 sub sp, #8
|
|
80017c2: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80017c4: 2300 movs r3, #0
|
|
80017c6: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80017c8: 2003 movs r0, #3
|
|
80017ca: f000 f939 bl 8001a40 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
80017ce: 2000 movs r0, #0
|
|
80017d0: f000 f80e bl 80017f0 <HAL_InitTick>
|
|
80017d4: 4603 mov r3, r0
|
|
80017d6: 2b00 cmp r3, #0
|
|
80017d8: d002 beq.n 80017e0 <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
80017da: 2301 movs r3, #1
|
|
80017dc: 71fb strb r3, [r7, #7]
|
|
80017de: e001 b.n 80017e4 <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80017e0: f7ff feb2 bl 8001548 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80017e4: 79fb ldrb r3, [r7, #7]
|
|
|
|
}
|
|
80017e6: 4618 mov r0, r3
|
|
80017e8: 3708 adds r7, #8
|
|
80017ea: 46bd mov sp, r7
|
|
80017ec: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080017f0 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80017f0: b580 push {r7, lr}
|
|
80017f2: b084 sub sp, #16
|
|
80017f4: af00 add r7, sp, #0
|
|
80017f6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80017f8: 2300 movs r3, #0
|
|
80017fa: 73fb strb r3, [r7, #15]
|
|
|
|
if (uwTickFreq != 0U)
|
|
80017fc: 4b16 ldr r3, [pc, #88] @ (8001858 <HAL_InitTick+0x68>)
|
|
80017fe: 681b ldr r3, [r3, #0]
|
|
8001800: 2b00 cmp r3, #0
|
|
8001802: d022 beq.n 800184a <HAL_InitTick+0x5a>
|
|
{
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
|
|
8001804: 4b15 ldr r3, [pc, #84] @ (800185c <HAL_InitTick+0x6c>)
|
|
8001806: 681a ldr r2, [r3, #0]
|
|
8001808: 4b13 ldr r3, [pc, #76] @ (8001858 <HAL_InitTick+0x68>)
|
|
800180a: 681b ldr r3, [r3, #0]
|
|
800180c: f44f 717a mov.w r1, #1000 @ 0x3e8
|
|
8001810: fbb1 f3f3 udiv r3, r1, r3
|
|
8001814: fbb2 f3f3 udiv r3, r2, r3
|
|
8001818: 4618 mov r0, r3
|
|
800181a: f000 f944 bl 8001aa6 <HAL_SYSTICK_Config>
|
|
800181e: 4603 mov r3, r0
|
|
8001820: 2b00 cmp r3, #0
|
|
8001822: d10f bne.n 8001844 <HAL_InitTick+0x54>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001824: 687b ldr r3, [r7, #4]
|
|
8001826: 2b0f cmp r3, #15
|
|
8001828: d809 bhi.n 800183e <HAL_InitTick+0x4e>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
800182a: 2200 movs r2, #0
|
|
800182c: 6879 ldr r1, [r7, #4]
|
|
800182e: f04f 30ff mov.w r0, #4294967295
|
|
8001832: f000 f910 bl 8001a56 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001836: 4a0a ldr r2, [pc, #40] @ (8001860 <HAL_InitTick+0x70>)
|
|
8001838: 687b ldr r3, [r7, #4]
|
|
800183a: 6013 str r3, [r2, #0]
|
|
800183c: e007 b.n 800184e <HAL_InitTick+0x5e>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800183e: 2301 movs r3, #1
|
|
8001840: 73fb strb r3, [r7, #15]
|
|
8001842: e004 b.n 800184e <HAL_InitTick+0x5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001844: 2301 movs r3, #1
|
|
8001846: 73fb strb r3, [r7, #15]
|
|
8001848: e001 b.n 800184e <HAL_InitTick+0x5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800184a: 2301 movs r3, #1
|
|
800184c: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
800184e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001850: 4618 mov r0, r3
|
|
8001852: 3710 adds r7, #16
|
|
8001854: 46bd mov sp, r7
|
|
8001856: bd80 pop {r7, pc}
|
|
8001858: 20000014 .word 0x20000014
|
|
800185c: 2000000c .word 0x2000000c
|
|
8001860: 20000010 .word 0x20000010
|
|
|
|
08001864 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8001864: b480 push {r7}
|
|
8001866: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8001868: 4b05 ldr r3, [pc, #20] @ (8001880 <HAL_IncTick+0x1c>)
|
|
800186a: 681a ldr r2, [r3, #0]
|
|
800186c: 4b05 ldr r3, [pc, #20] @ (8001884 <HAL_IncTick+0x20>)
|
|
800186e: 681b ldr r3, [r3, #0]
|
|
8001870: 4413 add r3, r2
|
|
8001872: 4a03 ldr r2, [pc, #12] @ (8001880 <HAL_IncTick+0x1c>)
|
|
8001874: 6013 str r3, [r2, #0]
|
|
}
|
|
8001876: bf00 nop
|
|
8001878: 46bd mov sp, r7
|
|
800187a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800187e: 4770 bx lr
|
|
8001880: 2000111c .word 0x2000111c
|
|
8001884: 20000014 .word 0x20000014
|
|
|
|
08001888 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001888: b480 push {r7}
|
|
800188a: af00 add r7, sp, #0
|
|
return uwTick;
|
|
800188c: 4b03 ldr r3, [pc, #12] @ (800189c <HAL_GetTick+0x14>)
|
|
800188e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001890: 4618 mov r0, r3
|
|
8001892: 46bd mov sp, r7
|
|
8001894: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001898: 4770 bx lr
|
|
800189a: bf00 nop
|
|
800189c: 2000111c .word 0x2000111c
|
|
|
|
080018a0 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80018a0: b480 push {r7}
|
|
80018a2: b085 sub sp, #20
|
|
80018a4: af00 add r7, sp, #0
|
|
80018a6: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80018a8: 687b ldr r3, [r7, #4]
|
|
80018aa: f003 0307 and.w r3, r3, #7
|
|
80018ae: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80018b0: 4b0c ldr r3, [pc, #48] @ (80018e4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80018b2: 68db ldr r3, [r3, #12]
|
|
80018b4: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80018b6: 68ba ldr r2, [r7, #8]
|
|
80018b8: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80018bc: 4013 ands r3, r2
|
|
80018be: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80018c0: 68fb ldr r3, [r7, #12]
|
|
80018c2: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80018c4: 68bb ldr r3, [r7, #8]
|
|
80018c6: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80018c8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80018cc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80018d0: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80018d2: 4a04 ldr r2, [pc, #16] @ (80018e4 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80018d4: 68bb ldr r3, [r7, #8]
|
|
80018d6: 60d3 str r3, [r2, #12]
|
|
}
|
|
80018d8: bf00 nop
|
|
80018da: 3714 adds r7, #20
|
|
80018dc: 46bd mov sp, r7
|
|
80018de: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018e2: 4770 bx lr
|
|
80018e4: e000ed00 .word 0xe000ed00
|
|
|
|
080018e8 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
80018e8: b480 push {r7}
|
|
80018ea: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80018ec: 4b04 ldr r3, [pc, #16] @ (8001900 <__NVIC_GetPriorityGrouping+0x18>)
|
|
80018ee: 68db ldr r3, [r3, #12]
|
|
80018f0: 0a1b lsrs r3, r3, #8
|
|
80018f2: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80018f6: 4618 mov r0, r3
|
|
80018f8: 46bd mov sp, r7
|
|
80018fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018fe: 4770 bx lr
|
|
8001900: e000ed00 .word 0xe000ed00
|
|
|
|
08001904 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001904: b480 push {r7}
|
|
8001906: b083 sub sp, #12
|
|
8001908: af00 add r7, sp, #0
|
|
800190a: 4603 mov r3, r0
|
|
800190c: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800190e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001912: 2b00 cmp r3, #0
|
|
8001914: db0b blt.n 800192e <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8001916: 79fb ldrb r3, [r7, #7]
|
|
8001918: f003 021f and.w r2, r3, #31
|
|
800191c: 4907 ldr r1, [pc, #28] @ (800193c <__NVIC_EnableIRQ+0x38>)
|
|
800191e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001922: 095b lsrs r3, r3, #5
|
|
8001924: 2001 movs r0, #1
|
|
8001926: fa00 f202 lsl.w r2, r0, r2
|
|
800192a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
800192e: bf00 nop
|
|
8001930: 370c adds r7, #12
|
|
8001932: 46bd mov sp, r7
|
|
8001934: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001938: 4770 bx lr
|
|
800193a: bf00 nop
|
|
800193c: e000e100 .word 0xe000e100
|
|
|
|
08001940 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8001940: b480 push {r7}
|
|
8001942: b083 sub sp, #12
|
|
8001944: af00 add r7, sp, #0
|
|
8001946: 4603 mov r3, r0
|
|
8001948: 6039 str r1, [r7, #0]
|
|
800194a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800194c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001950: 2b00 cmp r3, #0
|
|
8001952: db0a blt.n 800196a <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001954: 683b ldr r3, [r7, #0]
|
|
8001956: b2da uxtb r2, r3
|
|
8001958: 490c ldr r1, [pc, #48] @ (800198c <__NVIC_SetPriority+0x4c>)
|
|
800195a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800195e: 0112 lsls r2, r2, #4
|
|
8001960: b2d2 uxtb r2, r2
|
|
8001962: 440b add r3, r1
|
|
8001964: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001968: e00a b.n 8001980 <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
800196a: 683b ldr r3, [r7, #0]
|
|
800196c: b2da uxtb r2, r3
|
|
800196e: 4908 ldr r1, [pc, #32] @ (8001990 <__NVIC_SetPriority+0x50>)
|
|
8001970: 79fb ldrb r3, [r7, #7]
|
|
8001972: f003 030f and.w r3, r3, #15
|
|
8001976: 3b04 subs r3, #4
|
|
8001978: 0112 lsls r2, r2, #4
|
|
800197a: b2d2 uxtb r2, r2
|
|
800197c: 440b add r3, r1
|
|
800197e: 761a strb r2, [r3, #24]
|
|
}
|
|
8001980: bf00 nop
|
|
8001982: 370c adds r7, #12
|
|
8001984: 46bd mov sp, r7
|
|
8001986: f85d 7b04 ldr.w r7, [sp], #4
|
|
800198a: 4770 bx lr
|
|
800198c: e000e100 .word 0xe000e100
|
|
8001990: e000ed00 .word 0xe000ed00
|
|
|
|
08001994 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001994: b480 push {r7}
|
|
8001996: b089 sub sp, #36 @ 0x24
|
|
8001998: af00 add r7, sp, #0
|
|
800199a: 60f8 str r0, [r7, #12]
|
|
800199c: 60b9 str r1, [r7, #8]
|
|
800199e: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80019a0: 68fb ldr r3, [r7, #12]
|
|
80019a2: f003 0307 and.w r3, r3, #7
|
|
80019a6: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80019a8: 69fb ldr r3, [r7, #28]
|
|
80019aa: f1c3 0307 rsb r3, r3, #7
|
|
80019ae: 2b04 cmp r3, #4
|
|
80019b0: bf28 it cs
|
|
80019b2: 2304 movcs r3, #4
|
|
80019b4: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80019b6: 69fb ldr r3, [r7, #28]
|
|
80019b8: 3304 adds r3, #4
|
|
80019ba: 2b06 cmp r3, #6
|
|
80019bc: d902 bls.n 80019c4 <NVIC_EncodePriority+0x30>
|
|
80019be: 69fb ldr r3, [r7, #28]
|
|
80019c0: 3b03 subs r3, #3
|
|
80019c2: e000 b.n 80019c6 <NVIC_EncodePriority+0x32>
|
|
80019c4: 2300 movs r3, #0
|
|
80019c6: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80019c8: f04f 32ff mov.w r2, #4294967295
|
|
80019cc: 69bb ldr r3, [r7, #24]
|
|
80019ce: fa02 f303 lsl.w r3, r2, r3
|
|
80019d2: 43da mvns r2, r3
|
|
80019d4: 68bb ldr r3, [r7, #8]
|
|
80019d6: 401a ands r2, r3
|
|
80019d8: 697b ldr r3, [r7, #20]
|
|
80019da: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80019dc: f04f 31ff mov.w r1, #4294967295
|
|
80019e0: 697b ldr r3, [r7, #20]
|
|
80019e2: fa01 f303 lsl.w r3, r1, r3
|
|
80019e6: 43d9 mvns r1, r3
|
|
80019e8: 687b ldr r3, [r7, #4]
|
|
80019ea: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80019ec: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
80019ee: 4618 mov r0, r3
|
|
80019f0: 3724 adds r7, #36 @ 0x24
|
|
80019f2: 46bd mov sp, r7
|
|
80019f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80019f8: 4770 bx lr
|
|
...
|
|
|
|
080019fc <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
80019fc: b580 push {r7, lr}
|
|
80019fe: b082 sub sp, #8
|
|
8001a00: af00 add r7, sp, #0
|
|
8001a02: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8001a04: 687b ldr r3, [r7, #4]
|
|
8001a06: 3b01 subs r3, #1
|
|
8001a08: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8001a0c: d301 bcc.n 8001a12 <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8001a0e: 2301 movs r3, #1
|
|
8001a10: e00f b.n 8001a32 <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8001a12: 4a0a ldr r2, [pc, #40] @ (8001a3c <SysTick_Config+0x40>)
|
|
8001a14: 687b ldr r3, [r7, #4]
|
|
8001a16: 3b01 subs r3, #1
|
|
8001a18: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8001a1a: 210f movs r1, #15
|
|
8001a1c: f04f 30ff mov.w r0, #4294967295
|
|
8001a20: f7ff ff8e bl 8001940 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8001a24: 4b05 ldr r3, [pc, #20] @ (8001a3c <SysTick_Config+0x40>)
|
|
8001a26: 2200 movs r2, #0
|
|
8001a28: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8001a2a: 4b04 ldr r3, [pc, #16] @ (8001a3c <SysTick_Config+0x40>)
|
|
8001a2c: 2207 movs r2, #7
|
|
8001a2e: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
8001a30: 2300 movs r3, #0
|
|
}
|
|
8001a32: 4618 mov r0, r3
|
|
8001a34: 3708 adds r7, #8
|
|
8001a36: 46bd mov sp, r7
|
|
8001a38: bd80 pop {r7, pc}
|
|
8001a3a: bf00 nop
|
|
8001a3c: e000e010 .word 0xe000e010
|
|
|
|
08001a40 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001a40: b580 push {r7, lr}
|
|
8001a42: b082 sub sp, #8
|
|
8001a44: af00 add r7, sp, #0
|
|
8001a46: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8001a48: 6878 ldr r0, [r7, #4]
|
|
8001a4a: f7ff ff29 bl 80018a0 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8001a4e: bf00 nop
|
|
8001a50: 3708 adds r7, #8
|
|
8001a52: 46bd mov sp, r7
|
|
8001a54: bd80 pop {r7, pc}
|
|
|
|
08001a56 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001a56: b580 push {r7, lr}
|
|
8001a58: b086 sub sp, #24
|
|
8001a5a: af00 add r7, sp, #0
|
|
8001a5c: 4603 mov r3, r0
|
|
8001a5e: 60b9 str r1, [r7, #8]
|
|
8001a60: 607a str r2, [r7, #4]
|
|
8001a62: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8001a64: f7ff ff40 bl 80018e8 <__NVIC_GetPriorityGrouping>
|
|
8001a68: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8001a6a: 687a ldr r2, [r7, #4]
|
|
8001a6c: 68b9 ldr r1, [r7, #8]
|
|
8001a6e: 6978 ldr r0, [r7, #20]
|
|
8001a70: f7ff ff90 bl 8001994 <NVIC_EncodePriority>
|
|
8001a74: 4602 mov r2, r0
|
|
8001a76: f997 300f ldrsb.w r3, [r7, #15]
|
|
8001a7a: 4611 mov r1, r2
|
|
8001a7c: 4618 mov r0, r3
|
|
8001a7e: f7ff ff5f bl 8001940 <__NVIC_SetPriority>
|
|
}
|
|
8001a82: bf00 nop
|
|
8001a84: 3718 adds r7, #24
|
|
8001a86: 46bd mov sp, r7
|
|
8001a88: bd80 pop {r7, pc}
|
|
|
|
08001a8a <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8001a8a: b580 push {r7, lr}
|
|
8001a8c: b082 sub sp, #8
|
|
8001a8e: af00 add r7, sp, #0
|
|
8001a90: 4603 mov r3, r0
|
|
8001a92: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8001a94: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8001a98: 4618 mov r0, r3
|
|
8001a9a: f7ff ff33 bl 8001904 <__NVIC_EnableIRQ>
|
|
}
|
|
8001a9e: bf00 nop
|
|
8001aa0: 3708 adds r7, #8
|
|
8001aa2: 46bd mov sp, r7
|
|
8001aa4: bd80 pop {r7, pc}
|
|
|
|
08001aa6 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8001aa6: b580 push {r7, lr}
|
|
8001aa8: b082 sub sp, #8
|
|
8001aaa: af00 add r7, sp, #0
|
|
8001aac: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
8001aae: 6878 ldr r0, [r7, #4]
|
|
8001ab0: f7ff ffa4 bl 80019fc <SysTick_Config>
|
|
8001ab4: 4603 mov r3, r0
|
|
}
|
|
8001ab6: 4618 mov r0, r3
|
|
8001ab8: 3708 adds r7, #8
|
|
8001aba: 46bd mov sp, r7
|
|
8001abc: bd80 pop {r7, pc}
|
|
|
|
08001abe <HAL_DMA_Abort>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001abe: b480 push {r7}
|
|
8001ac0: b085 sub sp, #20
|
|
8001ac2: af00 add r7, sp, #0
|
|
8001ac4: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001ac6: 2300 movs r3, #0
|
|
8001ac8: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the DMA peripheral handle parameter */
|
|
if (hdma == NULL)
|
|
8001aca: 687b ldr r3, [r7, #4]
|
|
8001acc: 2b00 cmp r3, #0
|
|
8001ace: d101 bne.n 8001ad4 <HAL_DMA_Abort+0x16>
|
|
{
|
|
return HAL_ERROR;
|
|
8001ad0: 2301 movs r3, #1
|
|
8001ad2: e04c b.n 8001b6e <HAL_DMA_Abort+0xb0>
|
|
}
|
|
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
8001ad4: 687b ldr r3, [r7, #4]
|
|
8001ad6: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8001ada: b2db uxtb r3, r3
|
|
8001adc: 2b02 cmp r3, #2
|
|
8001ade: d005 beq.n 8001aec <HAL_DMA_Abort+0x2e>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8001ae0: 687b ldr r3, [r7, #4]
|
|
8001ae2: 2204 movs r2, #4
|
|
8001ae4: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
8001ae6: 2301 movs r3, #1
|
|
8001ae8: 73fb strb r3, [r7, #15]
|
|
8001aea: e037 b.n 8001b5c <HAL_DMA_Abort+0x9e>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001aec: 687b ldr r3, [r7, #4]
|
|
8001aee: 681b ldr r3, [r3, #0]
|
|
8001af0: 681a ldr r2, [r3, #0]
|
|
8001af2: 687b ldr r3, [r7, #4]
|
|
8001af4: 681b ldr r3, [r3, #0]
|
|
8001af6: f022 0201 bic.w r2, r2, #1
|
|
8001afa: 601a str r2, [r3, #0]
|
|
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8001afc: 687b ldr r3, [r7, #4]
|
|
8001afe: 681b ldr r3, [r3, #0]
|
|
8001b00: 681a ldr r2, [r3, #0]
|
|
8001b02: 687b ldr r3, [r7, #4]
|
|
8001b04: 681b ldr r3, [r3, #0]
|
|
8001b06: f022 020e bic.w r2, r2, #14
|
|
8001b0a: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8001b0c: 687b ldr r3, [r7, #4]
|
|
8001b0e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001b10: 681a ldr r2, [r3, #0]
|
|
8001b12: 687b ldr r3, [r7, #4]
|
|
8001b14: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001b16: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001b1a: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
|
|
8001b1c: 687b ldr r3, [r7, #4]
|
|
8001b1e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001b20: f003 021f and.w r2, r3, #31
|
|
8001b24: 687b ldr r3, [r7, #4]
|
|
8001b26: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001b28: 2101 movs r1, #1
|
|
8001b2a: fa01 f202 lsl.w r2, r1, r2
|
|
8001b2e: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8001b30: 687b ldr r3, [r7, #4]
|
|
8001b32: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001b34: 687a ldr r2, [r7, #4]
|
|
8001b36: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001b38: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8001b3a: 687b ldr r3, [r7, #4]
|
|
8001b3c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001b3e: 2b00 cmp r3, #0
|
|
8001b40: d00c beq.n 8001b5c <HAL_DMA_Abort+0x9e>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8001b42: 687b ldr r3, [r7, #4]
|
|
8001b44: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001b46: 681a ldr r2, [r3, #0]
|
|
8001b48: 687b ldr r3, [r7, #4]
|
|
8001b4a: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001b4c: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001b50: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8001b52: 687b ldr r3, [r7, #4]
|
|
8001b54: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001b56: 687a ldr r2, [r7, #4]
|
|
8001b58: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8001b5a: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001b5c: 687b ldr r3, [r7, #4]
|
|
8001b5e: 2201 movs r2, #1
|
|
8001b60: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001b64: 687b ldr r3, [r7, #4]
|
|
8001b66: 2200 movs r2, #0
|
|
8001b68: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return status;
|
|
8001b6c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001b6e: 4618 mov r0, r3
|
|
8001b70: 3714 adds r7, #20
|
|
8001b72: 46bd mov sp, r7
|
|
8001b74: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b78: 4770 bx lr
|
|
|
|
08001b7a <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8001b7a: b580 push {r7, lr}
|
|
8001b7c: b084 sub sp, #16
|
|
8001b7e: af00 add r7, sp, #0
|
|
8001b80: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8001b82: 2300 movs r3, #0
|
|
8001b84: 73fb strb r3, [r7, #15]
|
|
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
8001b86: 687b ldr r3, [r7, #4]
|
|
8001b88: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
8001b8c: b2db uxtb r3, r3
|
|
8001b8e: 2b02 cmp r3, #2
|
|
8001b90: d00d beq.n 8001bae <HAL_DMA_Abort_IT+0x34>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8001b92: 687b ldr r3, [r7, #4]
|
|
8001b94: 2204 movs r2, #4
|
|
8001b96: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001b98: 687b ldr r3, [r7, #4]
|
|
8001b9a: 2201 movs r2, #1
|
|
8001b9c: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001ba0: 687b ldr r3, [r7, #4]
|
|
8001ba2: 2200 movs r2, #0
|
|
8001ba4: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
status = HAL_ERROR;
|
|
8001ba8: 2301 movs r3, #1
|
|
8001baa: 73fb strb r3, [r7, #15]
|
|
8001bac: e047 b.n 8001c3e <HAL_DMA_Abort_IT+0xc4>
|
|
}
|
|
else
|
|
{
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8001bae: 687b ldr r3, [r7, #4]
|
|
8001bb0: 681b ldr r3, [r3, #0]
|
|
8001bb2: 681a ldr r2, [r3, #0]
|
|
8001bb4: 687b ldr r3, [r7, #4]
|
|
8001bb6: 681b ldr r3, [r3, #0]
|
|
8001bb8: f022 0201 bic.w r2, r2, #1
|
|
8001bbc: 601a str r2, [r3, #0]
|
|
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8001bbe: 687b ldr r3, [r7, #4]
|
|
8001bc0: 681b ldr r3, [r3, #0]
|
|
8001bc2: 681a ldr r2, [r3, #0]
|
|
8001bc4: 687b ldr r3, [r7, #4]
|
|
8001bc6: 681b ldr r3, [r3, #0]
|
|
8001bc8: f022 020e bic.w r2, r2, #14
|
|
8001bcc: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8001bce: 687b ldr r3, [r7, #4]
|
|
8001bd0: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001bd2: 681a ldr r2, [r3, #0]
|
|
8001bd4: 687b ldr r3, [r7, #4]
|
|
8001bd6: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8001bd8: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001bdc: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
|
|
8001bde: 687b ldr r3, [r7, #4]
|
|
8001be0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001be2: f003 021f and.w r2, r3, #31
|
|
8001be6: 687b ldr r3, [r7, #4]
|
|
8001be8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001bea: 2101 movs r1, #1
|
|
8001bec: fa01 f202 lsl.w r2, r1, r2
|
|
8001bf0: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8001bf2: 687b ldr r3, [r7, #4]
|
|
8001bf4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001bf6: 687a ldr r2, [r7, #4]
|
|
8001bf8: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001bfa: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8001bfc: 687b ldr r3, [r7, #4]
|
|
8001bfe: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001c00: 2b00 cmp r3, #0
|
|
8001c02: d00c beq.n 8001c1e <HAL_DMA_Abort_IT+0xa4>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8001c04: 687b ldr r3, [r7, #4]
|
|
8001c06: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001c08: 681a ldr r2, [r3, #0]
|
|
8001c0a: 687b ldr r3, [r7, #4]
|
|
8001c0c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8001c0e: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001c12: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8001c14: 687b ldr r3, [r7, #4]
|
|
8001c16: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001c18: 687a ldr r2, [r7, #4]
|
|
8001c1a: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
8001c1c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8001c1e: 687b ldr r3, [r7, #4]
|
|
8001c20: 2201 movs r2, #1
|
|
8001c22: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8001c26: 687b ldr r3, [r7, #4]
|
|
8001c28: 2200 movs r2, #0
|
|
8001c2a: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if (hdma->XferAbortCallback != NULL)
|
|
8001c2e: 687b ldr r3, [r7, #4]
|
|
8001c30: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001c32: 2b00 cmp r3, #0
|
|
8001c34: d003 beq.n 8001c3e <HAL_DMA_Abort_IT+0xc4>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
8001c36: 687b ldr r3, [r7, #4]
|
|
8001c38: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001c3a: 6878 ldr r0, [r7, #4]
|
|
8001c3c: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
8001c3e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001c40: 4618 mov r0, r3
|
|
8001c42: 3710 adds r7, #16
|
|
8001c44: 46bd mov sp, r7
|
|
8001c46: bd80 pop {r7, pc}
|
|
|
|
08001c48 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init)
|
|
{
|
|
8001c48: b480 push {r7}
|
|
8001c4a: b087 sub sp, #28
|
|
8001c4c: af00 add r7, sp, #0
|
|
8001c4e: 6078 str r0, [r7, #4]
|
|
8001c50: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00U;
|
|
8001c52: 2300 movs r3, #0
|
|
8001c54: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0U)
|
|
8001c56: e164 b.n 8001f22 <HAL_GPIO_Init+0x2da>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1UL << position);
|
|
8001c58: 683b ldr r3, [r7, #0]
|
|
8001c5a: 681a ldr r2, [r3, #0]
|
|
8001c5c: 2101 movs r1, #1
|
|
8001c5e: 697b ldr r3, [r7, #20]
|
|
8001c60: fa01 f303 lsl.w r3, r1, r3
|
|
8001c64: 4013 ands r3, r2
|
|
8001c66: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8001c68: 68fb ldr r3, [r7, #12]
|
|
8001c6a: 2b00 cmp r3, #0
|
|
8001c6c: f000 8156 beq.w 8001f1c <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
|
8001c70: 683b ldr r3, [r7, #0]
|
|
8001c72: 685b ldr r3, [r3, #4]
|
|
8001c74: f003 0303 and.w r3, r3, #3
|
|
8001c78: 2b01 cmp r3, #1
|
|
8001c7a: d005 beq.n 8001c88 <HAL_GPIO_Init+0x40>
|
|
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8001c7c: 683b ldr r3, [r7, #0]
|
|
8001c7e: 685b ldr r3, [r3, #4]
|
|
8001c80: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
|
8001c84: 2b02 cmp r3, #2
|
|
8001c86: d130 bne.n 8001cea <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8001c88: 687b ldr r3, [r7, #4]
|
|
8001c8a: 689b ldr r3, [r3, #8]
|
|
8001c8c: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
|
8001c8e: 697b ldr r3, [r7, #20]
|
|
8001c90: 005b lsls r3, r3, #1
|
|
8001c92: 2203 movs r2, #3
|
|
8001c94: fa02 f303 lsl.w r3, r2, r3
|
|
8001c98: 43db mvns r3, r3
|
|
8001c9a: 693a ldr r2, [r7, #16]
|
|
8001c9c: 4013 ands r3, r2
|
|
8001c9e: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8001ca0: 683b ldr r3, [r7, #0]
|
|
8001ca2: 68da ldr r2, [r3, #12]
|
|
8001ca4: 697b ldr r3, [r7, #20]
|
|
8001ca6: 005b lsls r3, r3, #1
|
|
8001ca8: fa02 f303 lsl.w r3, r2, r3
|
|
8001cac: 693a ldr r2, [r7, #16]
|
|
8001cae: 4313 orrs r3, r2
|
|
8001cb0: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8001cb2: 687b ldr r3, [r7, #4]
|
|
8001cb4: 693a ldr r2, [r7, #16]
|
|
8001cb6: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8001cb8: 687b ldr r3, [r7, #4]
|
|
8001cba: 685b ldr r3, [r3, #4]
|
|
8001cbc: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8001cbe: 2201 movs r2, #1
|
|
8001cc0: 697b ldr r3, [r7, #20]
|
|
8001cc2: fa02 f303 lsl.w r3, r2, r3
|
|
8001cc6: 43db mvns r3, r3
|
|
8001cc8: 693a ldr r2, [r7, #16]
|
|
8001cca: 4013 ands r3, r2
|
|
8001ccc: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001cce: 683b ldr r3, [r7, #0]
|
|
8001cd0: 685b ldr r3, [r3, #4]
|
|
8001cd2: 091b lsrs r3, r3, #4
|
|
8001cd4: f003 0201 and.w r2, r3, #1
|
|
8001cd8: 697b ldr r3, [r7, #20]
|
|
8001cda: fa02 f303 lsl.w r3, r2, r3
|
|
8001cde: 693a ldr r2, [r7, #16]
|
|
8001ce0: 4313 orrs r3, r2
|
|
8001ce2: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8001ce4: 687b ldr r3, [r7, #4]
|
|
8001ce6: 693a ldr r2, [r7, #16]
|
|
8001ce8: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
|
|
8001cea: 683b ldr r3, [r7, #0]
|
|
8001cec: 685b ldr r3, [r3, #4]
|
|
8001cee: f003 0303 and.w r3, r3, #3
|
|
8001cf2: 2b03 cmp r3, #3
|
|
8001cf4: d109 bne.n 8001d0a <HAL_GPIO_Init+0xc2>
|
|
(((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
|
|
8001cf6: 683b ldr r3, [r7, #0]
|
|
8001cf8: 685b ldr r3, [r3, #4]
|
|
8001cfa: f003 0303 and.w r3, r3, #3
|
|
if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) ||
|
|
8001cfe: 2b03 cmp r3, #3
|
|
8001d00: d11b bne.n 8001d3a <HAL_GPIO_Init+0xf2>
|
|
(((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP)))
|
|
8001d02: 683b ldr r3, [r7, #0]
|
|
8001d04: 689b ldr r3, [r3, #8]
|
|
8001d06: 2b01 cmp r3, #1
|
|
8001d08: d017 beq.n 8001d3a <HAL_GPIO_Init+0xf2>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8001d0a: 687b ldr r3, [r7, #4]
|
|
8001d0c: 68db ldr r3, [r3, #12]
|
|
8001d0e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
8001d10: 697b ldr r3, [r7, #20]
|
|
8001d12: 005b lsls r3, r3, #1
|
|
8001d14: 2203 movs r2, #3
|
|
8001d16: fa02 f303 lsl.w r3, r2, r3
|
|
8001d1a: 43db mvns r3, r3
|
|
8001d1c: 693a ldr r2, [r7, #16]
|
|
8001d1e: 4013 ands r3, r2
|
|
8001d20: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001d22: 683b ldr r3, [r7, #0]
|
|
8001d24: 689a ldr r2, [r3, #8]
|
|
8001d26: 697b ldr r3, [r7, #20]
|
|
8001d28: 005b lsls r3, r3, #1
|
|
8001d2a: fa02 f303 lsl.w r3, r2, r3
|
|
8001d2e: 693a ldr r2, [r7, #16]
|
|
8001d30: 4313 orrs r3, r2
|
|
8001d32: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8001d34: 687b ldr r3, [r7, #4]
|
|
8001d36: 693a ldr r2, [r7, #16]
|
|
8001d38: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001d3a: 683b ldr r3, [r7, #0]
|
|
8001d3c: 685b ldr r3, [r3, #4]
|
|
8001d3e: f003 0303 and.w r3, r3, #3
|
|
8001d42: 2b02 cmp r3, #2
|
|
8001d44: d123 bne.n 8001d8e <HAL_GPIO_Init+0x146>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
8001d46: 697b ldr r3, [r7, #20]
|
|
8001d48: 08da lsrs r2, r3, #3
|
|
8001d4a: 687b ldr r3, [r7, #4]
|
|
8001d4c: 3208 adds r2, #8
|
|
8001d4e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8001d52: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFU << ((position & 0x07U) * 4U));
|
|
8001d54: 697b ldr r3, [r7, #20]
|
|
8001d56: f003 0307 and.w r3, r3, #7
|
|
8001d5a: 009b lsls r3, r3, #2
|
|
8001d5c: 220f movs r2, #15
|
|
8001d5e: fa02 f303 lsl.w r3, r2, r3
|
|
8001d62: 43db mvns r3, r3
|
|
8001d64: 693a ldr r2, [r7, #16]
|
|
8001d66: 4013 ands r3, r2
|
|
8001d68: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
|
|
8001d6a: 683b ldr r3, [r7, #0]
|
|
8001d6c: 691a ldr r2, [r3, #16]
|
|
8001d6e: 697b ldr r3, [r7, #20]
|
|
8001d70: f003 0307 and.w r3, r3, #7
|
|
8001d74: 009b lsls r3, r3, #2
|
|
8001d76: fa02 f303 lsl.w r3, r2, r3
|
|
8001d7a: 693a ldr r2, [r7, #16]
|
|
8001d7c: 4313 orrs r3, r2
|
|
8001d7e: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
8001d80: 697b ldr r3, [r7, #20]
|
|
8001d82: 08da lsrs r2, r3, #3
|
|
8001d84: 687b ldr r3, [r7, #4]
|
|
8001d86: 3208 adds r2, #8
|
|
8001d88: 6939 ldr r1, [r7, #16]
|
|
8001d8a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8001d8e: 687b ldr r3, [r7, #4]
|
|
8001d90: 681b ldr r3, [r3, #0]
|
|
8001d92: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
|
8001d94: 697b ldr r3, [r7, #20]
|
|
8001d96: 005b lsls r3, r3, #1
|
|
8001d98: 2203 movs r2, #3
|
|
8001d9a: fa02 f303 lsl.w r3, r2, r3
|
|
8001d9e: 43db mvns r3, r3
|
|
8001da0: 693a ldr r2, [r7, #16]
|
|
8001da2: 4013 ands r3, r2
|
|
8001da4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8001da6: 683b ldr r3, [r7, #0]
|
|
8001da8: 685b ldr r3, [r3, #4]
|
|
8001daa: f003 0203 and.w r2, r3, #3
|
|
8001dae: 697b ldr r3, [r7, #20]
|
|
8001db0: 005b lsls r3, r3, #1
|
|
8001db2: fa02 f303 lsl.w r3, r2, r3
|
|
8001db6: 693a ldr r2, [r7, #16]
|
|
8001db8: 4313 orrs r3, r2
|
|
8001dba: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8001dbc: 687b ldr r3, [r7, #4]
|
|
8001dbe: 693a ldr r2, [r7, #16]
|
|
8001dc0: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
8001dc2: 683b ldr r3, [r7, #0]
|
|
8001dc4: 685b ldr r3, [r3, #4]
|
|
8001dc6: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001dca: 2b00 cmp r3, #0
|
|
8001dcc: f000 80a6 beq.w 8001f1c <HAL_GPIO_Init+0x2d4>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001dd0: 4b5b ldr r3, [pc, #364] @ (8001f40 <HAL_GPIO_Init+0x2f8>)
|
|
8001dd2: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001dd4: 4a5a ldr r2, [pc, #360] @ (8001f40 <HAL_GPIO_Init+0x2f8>)
|
|
8001dd6: f043 0301 orr.w r3, r3, #1
|
|
8001dda: 6613 str r3, [r2, #96] @ 0x60
|
|
8001ddc: 4b58 ldr r3, [pc, #352] @ (8001f40 <HAL_GPIO_Init+0x2f8>)
|
|
8001dde: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001de0: f003 0301 and.w r3, r3, #1
|
|
8001de4: 60bb str r3, [r7, #8]
|
|
8001de6: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8001de8: 4a56 ldr r2, [pc, #344] @ (8001f44 <HAL_GPIO_Init+0x2fc>)
|
|
8001dea: 697b ldr r3, [r7, #20]
|
|
8001dec: 089b lsrs r3, r3, #2
|
|
8001dee: 3302 adds r3, #2
|
|
8001df0: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001df4: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
|
|
8001df6: 697b ldr r3, [r7, #20]
|
|
8001df8: f003 0303 and.w r3, r3, #3
|
|
8001dfc: 009b lsls r3, r3, #2
|
|
8001dfe: 220f movs r2, #15
|
|
8001e00: fa02 f303 lsl.w r3, r2, r3
|
|
8001e04: 43db mvns r3, r3
|
|
8001e06: 693a ldr r2, [r7, #16]
|
|
8001e08: 4013 ands r3, r2
|
|
8001e0a: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
|
|
8001e0c: 687b ldr r3, [r7, #4]
|
|
8001e0e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
8001e12: d01f beq.n 8001e54 <HAL_GPIO_Init+0x20c>
|
|
8001e14: 687b ldr r3, [r7, #4]
|
|
8001e16: 4a4c ldr r2, [pc, #304] @ (8001f48 <HAL_GPIO_Init+0x300>)
|
|
8001e18: 4293 cmp r3, r2
|
|
8001e1a: d019 beq.n 8001e50 <HAL_GPIO_Init+0x208>
|
|
8001e1c: 687b ldr r3, [r7, #4]
|
|
8001e1e: 4a4b ldr r2, [pc, #300] @ (8001f4c <HAL_GPIO_Init+0x304>)
|
|
8001e20: 4293 cmp r3, r2
|
|
8001e22: d013 beq.n 8001e4c <HAL_GPIO_Init+0x204>
|
|
8001e24: 687b ldr r3, [r7, #4]
|
|
8001e26: 4a4a ldr r2, [pc, #296] @ (8001f50 <HAL_GPIO_Init+0x308>)
|
|
8001e28: 4293 cmp r3, r2
|
|
8001e2a: d00d beq.n 8001e48 <HAL_GPIO_Init+0x200>
|
|
8001e2c: 687b ldr r3, [r7, #4]
|
|
8001e2e: 4a49 ldr r2, [pc, #292] @ (8001f54 <HAL_GPIO_Init+0x30c>)
|
|
8001e30: 4293 cmp r3, r2
|
|
8001e32: d007 beq.n 8001e44 <HAL_GPIO_Init+0x1fc>
|
|
8001e34: 687b ldr r3, [r7, #4]
|
|
8001e36: 4a48 ldr r2, [pc, #288] @ (8001f58 <HAL_GPIO_Init+0x310>)
|
|
8001e38: 4293 cmp r3, r2
|
|
8001e3a: d101 bne.n 8001e40 <HAL_GPIO_Init+0x1f8>
|
|
8001e3c: 2305 movs r3, #5
|
|
8001e3e: e00a b.n 8001e56 <HAL_GPIO_Init+0x20e>
|
|
8001e40: 2306 movs r3, #6
|
|
8001e42: e008 b.n 8001e56 <HAL_GPIO_Init+0x20e>
|
|
8001e44: 2304 movs r3, #4
|
|
8001e46: e006 b.n 8001e56 <HAL_GPIO_Init+0x20e>
|
|
8001e48: 2303 movs r3, #3
|
|
8001e4a: e004 b.n 8001e56 <HAL_GPIO_Init+0x20e>
|
|
8001e4c: 2302 movs r3, #2
|
|
8001e4e: e002 b.n 8001e56 <HAL_GPIO_Init+0x20e>
|
|
8001e50: 2301 movs r3, #1
|
|
8001e52: e000 b.n 8001e56 <HAL_GPIO_Init+0x20e>
|
|
8001e54: 2300 movs r3, #0
|
|
8001e56: 697a ldr r2, [r7, #20]
|
|
8001e58: f002 0203 and.w r2, r2, #3
|
|
8001e5c: 0092 lsls r2, r2, #2
|
|
8001e5e: 4093 lsls r3, r2
|
|
8001e60: 693a ldr r2, [r7, #16]
|
|
8001e62: 4313 orrs r3, r2
|
|
8001e64: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
8001e66: 4937 ldr r1, [pc, #220] @ (8001f44 <HAL_GPIO_Init+0x2fc>)
|
|
8001e68: 697b ldr r3, [r7, #20]
|
|
8001e6a: 089b lsrs r3, r3, #2
|
|
8001e6c: 3302 adds r3, #2
|
|
8001e6e: 693a ldr r2, [r7, #16]
|
|
8001e70: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
8001e74: 4b39 ldr r3, [pc, #228] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001e76: 689b ldr r3, [r3, #8]
|
|
8001e78: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001e7a: 68fb ldr r3, [r7, #12]
|
|
8001e7c: 43db mvns r3, r3
|
|
8001e7e: 693a ldr r2, [r7, #16]
|
|
8001e80: 4013 ands r3, r2
|
|
8001e82: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8001e84: 683b ldr r3, [r7, #0]
|
|
8001e86: 685b ldr r3, [r3, #4]
|
|
8001e88: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001e8c: 2b00 cmp r3, #0
|
|
8001e8e: d003 beq.n 8001e98 <HAL_GPIO_Init+0x250>
|
|
{
|
|
temp |= iocurrent;
|
|
8001e90: 693a ldr r2, [r7, #16]
|
|
8001e92: 68fb ldr r3, [r7, #12]
|
|
8001e94: 4313 orrs r3, r2
|
|
8001e96: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
8001e98: 4a30 ldr r2, [pc, #192] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001e9a: 693b ldr r3, [r7, #16]
|
|
8001e9c: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
8001e9e: 4b2f ldr r3, [pc, #188] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001ea0: 68db ldr r3, [r3, #12]
|
|
8001ea2: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001ea4: 68fb ldr r3, [r7, #12]
|
|
8001ea6: 43db mvns r3, r3
|
|
8001ea8: 693a ldr r2, [r7, #16]
|
|
8001eaa: 4013 ands r3, r2
|
|
8001eac: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8001eae: 683b ldr r3, [r7, #0]
|
|
8001eb0: 685b ldr r3, [r3, #4]
|
|
8001eb2: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001eb6: 2b00 cmp r3, #0
|
|
8001eb8: d003 beq.n 8001ec2 <HAL_GPIO_Init+0x27a>
|
|
{
|
|
temp |= iocurrent;
|
|
8001eba: 693a ldr r2, [r7, #16]
|
|
8001ebc: 68fb ldr r3, [r7, #12]
|
|
8001ebe: 4313 orrs r3, r2
|
|
8001ec0: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8001ec2: 4a26 ldr r2, [pc, #152] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001ec4: 693b ldr r3, [r7, #16]
|
|
8001ec6: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR1;
|
|
8001ec8: 4b24 ldr r3, [pc, #144] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001eca: 685b ldr r3, [r3, #4]
|
|
8001ecc: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001ece: 68fb ldr r3, [r7, #12]
|
|
8001ed0: 43db mvns r3, r3
|
|
8001ed2: 693a ldr r2, [r7, #16]
|
|
8001ed4: 4013 ands r3, r2
|
|
8001ed6: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001ed8: 683b ldr r3, [r7, #0]
|
|
8001eda: 685b ldr r3, [r3, #4]
|
|
8001edc: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001ee0: 2b00 cmp r3, #0
|
|
8001ee2: d003 beq.n 8001eec <HAL_GPIO_Init+0x2a4>
|
|
{
|
|
temp |= iocurrent;
|
|
8001ee4: 693a ldr r2, [r7, #16]
|
|
8001ee6: 68fb ldr r3, [r7, #12]
|
|
8001ee8: 4313 orrs r3, r2
|
|
8001eea: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
8001eec: 4a1b ldr r2, [pc, #108] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001eee: 693b ldr r3, [r7, #16]
|
|
8001ef0: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR1;
|
|
8001ef2: 4b1a ldr r3, [pc, #104] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001ef4: 681b ldr r3, [r3, #0]
|
|
8001ef6: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8001ef8: 68fb ldr r3, [r7, #12]
|
|
8001efa: 43db mvns r3, r3
|
|
8001efc: 693a ldr r2, [r7, #16]
|
|
8001efe: 4013 ands r3, r2
|
|
8001f00: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8001f02: 683b ldr r3, [r7, #0]
|
|
8001f04: 685b ldr r3, [r3, #4]
|
|
8001f06: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001f0a: 2b00 cmp r3, #0
|
|
8001f0c: d003 beq.n 8001f16 <HAL_GPIO_Init+0x2ce>
|
|
{
|
|
temp |= iocurrent;
|
|
8001f0e: 693a ldr r2, [r7, #16]
|
|
8001f10: 68fb ldr r3, [r7, #12]
|
|
8001f12: 4313 orrs r3, r2
|
|
8001f14: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8001f16: 4a11 ldr r2, [pc, #68] @ (8001f5c <HAL_GPIO_Init+0x314>)
|
|
8001f18: 693b ldr r3, [r7, #16]
|
|
8001f1a: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8001f1c: 697b ldr r3, [r7, #20]
|
|
8001f1e: 3301 adds r3, #1
|
|
8001f20: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0U)
|
|
8001f22: 683b ldr r3, [r7, #0]
|
|
8001f24: 681a ldr r2, [r3, #0]
|
|
8001f26: 697b ldr r3, [r7, #20]
|
|
8001f28: fa22 f303 lsr.w r3, r2, r3
|
|
8001f2c: 2b00 cmp r3, #0
|
|
8001f2e: f47f ae93 bne.w 8001c58 <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8001f32: bf00 nop
|
|
8001f34: bf00 nop
|
|
8001f36: 371c adds r7, #28
|
|
8001f38: 46bd mov sp, r7
|
|
8001f3a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f3e: 4770 bx lr
|
|
8001f40: 40021000 .word 0x40021000
|
|
8001f44: 40010000 .word 0x40010000
|
|
8001f48: 48000400 .word 0x48000400
|
|
8001f4c: 48000800 .word 0x48000800
|
|
8001f50: 48000c00 .word 0x48000c00
|
|
8001f54: 48001000 .word 0x48001000
|
|
8001f58: 48001400 .word 0x48001400
|
|
8001f5c: 40010400 .word 0x40010400
|
|
|
|
08001f60 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8001f60: b480 push {r7}
|
|
8001f62: b083 sub sp, #12
|
|
8001f64: af00 add r7, sp, #0
|
|
8001f66: 6078 str r0, [r7, #4]
|
|
8001f68: 460b mov r3, r1
|
|
8001f6a: 807b strh r3, [r7, #2]
|
|
8001f6c: 4613 mov r3, r2
|
|
8001f6e: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8001f70: 787b ldrb r3, [r7, #1]
|
|
8001f72: 2b00 cmp r3, #0
|
|
8001f74: d003 beq.n 8001f7e <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8001f76: 887a ldrh r2, [r7, #2]
|
|
8001f78: 687b ldr r3, [r7, #4]
|
|
8001f7a: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8001f7c: e002 b.n 8001f84 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8001f7e: 887a ldrh r2, [r7, #2]
|
|
8001f80: 687b ldr r3, [r7, #4]
|
|
8001f82: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
8001f84: bf00 nop
|
|
8001f86: 370c adds r7, #12
|
|
8001f88: 46bd mov sp, r7
|
|
8001f8a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f8e: 4770 bx lr
|
|
|
|
08001f90 <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
8001f90: b480 push {r7}
|
|
8001f92: b085 sub sp, #20
|
|
8001f94: af00 add r7, sp, #0
|
|
8001f96: 6078 str r0, [r7, #4]
|
|
uint32_t wait_loop_index;
|
|
|
|
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
|
|
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
|
|
8001f98: 687b ldr r3, [r7, #4]
|
|
8001f9a: 2b00 cmp r3, #0
|
|
8001f9c: d141 bne.n 8002022 <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
{
|
|
/* If current range is range 2 */
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
8001f9e: 4b4b ldr r3, [pc, #300] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8001fa0: 681b ldr r3, [r3, #0]
|
|
8001fa2: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8001fa6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8001faa: d131 bne.n 8002010 <HAL_PWREx_ControlVoltageScaling+0x80>
|
|
{
|
|
/* Make sure Range 1 Boost is enabled */
|
|
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
8001fac: 4b47 ldr r3, [pc, #284] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8001fae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8001fb2: 4a46 ldr r2, [pc, #280] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8001fb4: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8001fb8: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8001fbc: 4b43 ldr r3, [pc, #268] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8001fbe: 681b ldr r3, [r3, #0]
|
|
8001fc0: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8001fc4: 4a41 ldr r2, [pc, #260] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8001fc6: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8001fca: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
8001fcc: 4b40 ldr r3, [pc, #256] @ (80020d0 <HAL_PWREx_ControlVoltageScaling+0x140>)
|
|
8001fce: 681b ldr r3, [r3, #0]
|
|
8001fd0: 2232 movs r2, #50 @ 0x32
|
|
8001fd2: fb02 f303 mul.w r3, r2, r3
|
|
8001fd6: 4a3f ldr r2, [pc, #252] @ (80020d4 <HAL_PWREx_ControlVoltageScaling+0x144>)
|
|
8001fd8: fba2 2303 umull r2, r3, r2, r3
|
|
8001fdc: 0c9b lsrs r3, r3, #18
|
|
8001fde: 3301 adds r3, #1
|
|
8001fe0: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8001fe2: e002 b.n 8001fea <HAL_PWREx_ControlVoltageScaling+0x5a>
|
|
{
|
|
wait_loop_index--;
|
|
8001fe4: 68fb ldr r3, [r7, #12]
|
|
8001fe6: 3b01 subs r3, #1
|
|
8001fe8: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8001fea: 4b38 ldr r3, [pc, #224] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8001fec: 695b ldr r3, [r3, #20]
|
|
8001fee: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8001ff2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8001ff6: d102 bne.n 8001ffe <HAL_PWREx_ControlVoltageScaling+0x6e>
|
|
8001ff8: 68fb ldr r3, [r7, #12]
|
|
8001ffa: 2b00 cmp r3, #0
|
|
8001ffc: d1f2 bne.n 8001fe4 <HAL_PWREx_ControlVoltageScaling+0x54>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8001ffe: 4b33 ldr r3, [pc, #204] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8002000: 695b ldr r3, [r3, #20]
|
|
8002002: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002006: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800200a: d158 bne.n 80020be <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800200c: 2303 movs r3, #3
|
|
800200e: e057 b.n 80020c0 <HAL_PWREx_ControlVoltageScaling+0x130>
|
|
}
|
|
/* If current range is range 1 normal or boost mode */
|
|
else
|
|
{
|
|
/* Enable Range 1 Boost (no issue if bit already reset) */
|
|
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
8002010: 4b2e ldr r3, [pc, #184] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8002012: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8002016: 4a2d ldr r2, [pc, #180] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8002018: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800201c: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
8002020: e04d b.n 80020be <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
}
|
|
}
|
|
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8002022: 687b ldr r3, [r7, #4]
|
|
8002024: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8002028: d141 bne.n 80020ae <HAL_PWREx_ControlVoltageScaling+0x11e>
|
|
{
|
|
/* If current range is range 2 */
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
800202a: 4b28 ldr r3, [pc, #160] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800202c: 681b ldr r3, [r3, #0]
|
|
800202e: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8002032: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002036: d131 bne.n 800209c <HAL_PWREx_ControlVoltageScaling+0x10c>
|
|
{
|
|
/* Make sure Range 1 Boost is disabled */
|
|
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
8002038: 4b24 ldr r3, [pc, #144] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800203a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800203e: 4a23 ldr r2, [pc, #140] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8002040: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002044: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8002048: 4b20 ldr r3, [pc, #128] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800204a: 681b ldr r3, [r3, #0]
|
|
800204c: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8002050: 4a1e ldr r2, [pc, #120] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8002052: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
8002056: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
8002058: 4b1d ldr r3, [pc, #116] @ (80020d0 <HAL_PWREx_ControlVoltageScaling+0x140>)
|
|
800205a: 681b ldr r3, [r3, #0]
|
|
800205c: 2232 movs r2, #50 @ 0x32
|
|
800205e: fb02 f303 mul.w r3, r2, r3
|
|
8002062: 4a1c ldr r2, [pc, #112] @ (80020d4 <HAL_PWREx_ControlVoltageScaling+0x144>)
|
|
8002064: fba2 2303 umull r2, r3, r2, r3
|
|
8002068: 0c9b lsrs r3, r3, #18
|
|
800206a: 3301 adds r3, #1
|
|
800206c: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
800206e: e002 b.n 8002076 <HAL_PWREx_ControlVoltageScaling+0xe6>
|
|
{
|
|
wait_loop_index--;
|
|
8002070: 68fb ldr r3, [r7, #12]
|
|
8002072: 3b01 subs r3, #1
|
|
8002074: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8002076: 4b15 ldr r3, [pc, #84] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8002078: 695b ldr r3, [r3, #20]
|
|
800207a: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800207e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002082: d102 bne.n 800208a <HAL_PWREx_ControlVoltageScaling+0xfa>
|
|
8002084: 68fb ldr r3, [r7, #12]
|
|
8002086: 2b00 cmp r3, #0
|
|
8002088: d1f2 bne.n 8002070 <HAL_PWREx_ControlVoltageScaling+0xe0>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
800208a: 4b10 ldr r3, [pc, #64] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800208c: 695b ldr r3, [r3, #20]
|
|
800208e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002092: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002096: d112 bne.n 80020be <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002098: 2303 movs r3, #3
|
|
800209a: e011 b.n 80020c0 <HAL_PWREx_ControlVoltageScaling+0x130>
|
|
}
|
|
/* If current range is range 1 normal or boost mode */
|
|
else
|
|
{
|
|
/* Disable Range 1 Boost (no issue if bit already set) */
|
|
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
800209c: 4b0b ldr r3, [pc, #44] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800209e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80020a2: 4a0a ldr r2, [pc, #40] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80020a4: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80020a8: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
80020ac: e007 b.n 80020be <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
80020ae: 4b07 ldr r3, [pc, #28] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80020b0: 681b ldr r3, [r3, #0]
|
|
80020b2: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
80020b6: 4a05 ldr r2, [pc, #20] @ (80020cc <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80020b8: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
80020bc: 6013 str r3, [r2, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
|
|
}
|
|
|
|
return HAL_OK;
|
|
80020be: 2300 movs r3, #0
|
|
}
|
|
80020c0: 4618 mov r0, r3
|
|
80020c2: 3714 adds r7, #20
|
|
80020c4: 46bd mov sp, r7
|
|
80020c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80020ca: 4770 bx lr
|
|
80020cc: 40007000 .word 0x40007000
|
|
80020d0: 2000000c .word 0x2000000c
|
|
80020d4: 431bde83 .word 0x431bde83
|
|
|
|
080020d8 <HAL_PWREx_DisableUCPDDeadBattery>:
|
|
* or to hand over control to the UCPD (which should therefore be
|
|
* initialized before doing the disable).
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_DisableUCPDDeadBattery(void)
|
|
{
|
|
80020d8: b480 push {r7}
|
|
80020da: af00 add r7, sp, #0
|
|
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
|
|
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
|
|
80020dc: 4b05 ldr r3, [pc, #20] @ (80020f4 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
|
|
80020de: 689b ldr r3, [r3, #8]
|
|
80020e0: 4a04 ldr r2, [pc, #16] @ (80020f4 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
|
|
80020e2: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80020e6: 6093 str r3, [r2, #8]
|
|
}
|
|
80020e8: bf00 nop
|
|
80020ea: 46bd mov sp, r7
|
|
80020ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80020f0: 4770 bx lr
|
|
80020f2: bf00 nop
|
|
80020f4: 40007000 .word 0x40007000
|
|
|
|
080020f8 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
80020f8: b580 push {r7, lr}
|
|
80020fa: b088 sub sp, #32
|
|
80020fc: af00 add r7, sp, #0
|
|
80020fe: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t temp_sysclksrc;
|
|
uint32_t temp_pllckcfg;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8002100: 687b ldr r3, [r7, #4]
|
|
8002102: 2b00 cmp r3, #0
|
|
8002104: d101 bne.n 800210a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002106: 2301 movs r3, #1
|
|
8002108: e2fe b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800210a: 687b ldr r3, [r7, #4]
|
|
800210c: 681b ldr r3, [r3, #0]
|
|
800210e: f003 0301 and.w r3, r3, #1
|
|
8002112: 2b00 cmp r3, #0
|
|
8002114: d075 beq.n 8002202 <HAL_RCC_OscConfig+0x10a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8002116: 4b97 ldr r3, [pc, #604] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002118: 689b ldr r3, [r3, #8]
|
|
800211a: f003 030c and.w r3, r3, #12
|
|
800211e: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8002120: 4b94 ldr r3, [pc, #592] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002122: 68db ldr r3, [r3, #12]
|
|
8002124: f003 0303 and.w r3, r3, #3
|
|
8002128: 617b str r3, [r7, #20]
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
|
|
800212a: 69bb ldr r3, [r7, #24]
|
|
800212c: 2b0c cmp r3, #12
|
|
800212e: d102 bne.n 8002136 <HAL_RCC_OscConfig+0x3e>
|
|
8002130: 697b ldr r3, [r7, #20]
|
|
8002132: 2b03 cmp r3, #3
|
|
8002134: d002 beq.n 800213c <HAL_RCC_OscConfig+0x44>
|
|
8002136: 69bb ldr r3, [r7, #24]
|
|
8002138: 2b08 cmp r3, #8
|
|
800213a: d10b bne.n 8002154 <HAL_RCC_OscConfig+0x5c>
|
|
{
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
800213c: 4b8d ldr r3, [pc, #564] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800213e: 681b ldr r3, [r3, #0]
|
|
8002140: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002144: 2b00 cmp r3, #0
|
|
8002146: d05b beq.n 8002200 <HAL_RCC_OscConfig+0x108>
|
|
8002148: 687b ldr r3, [r7, #4]
|
|
800214a: 685b ldr r3, [r3, #4]
|
|
800214c: 2b00 cmp r3, #0
|
|
800214e: d157 bne.n 8002200 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
return HAL_ERROR;
|
|
8002150: 2301 movs r3, #1
|
|
8002152: e2d9 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8002154: 687b ldr r3, [r7, #4]
|
|
8002156: 685b ldr r3, [r3, #4]
|
|
8002158: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800215c: d106 bne.n 800216c <HAL_RCC_OscConfig+0x74>
|
|
800215e: 4b85 ldr r3, [pc, #532] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002160: 681b ldr r3, [r3, #0]
|
|
8002162: 4a84 ldr r2, [pc, #528] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002164: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8002168: 6013 str r3, [r2, #0]
|
|
800216a: e01d b.n 80021a8 <HAL_RCC_OscConfig+0xb0>
|
|
800216c: 687b ldr r3, [r7, #4]
|
|
800216e: 685b ldr r3, [r3, #4]
|
|
8002170: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8002174: d10c bne.n 8002190 <HAL_RCC_OscConfig+0x98>
|
|
8002176: 4b7f ldr r3, [pc, #508] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002178: 681b ldr r3, [r3, #0]
|
|
800217a: 4a7e ldr r2, [pc, #504] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800217c: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8002180: 6013 str r3, [r2, #0]
|
|
8002182: 4b7c ldr r3, [pc, #496] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002184: 681b ldr r3, [r3, #0]
|
|
8002186: 4a7b ldr r2, [pc, #492] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002188: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800218c: 6013 str r3, [r2, #0]
|
|
800218e: e00b b.n 80021a8 <HAL_RCC_OscConfig+0xb0>
|
|
8002190: 4b78 ldr r3, [pc, #480] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002192: 681b ldr r3, [r3, #0]
|
|
8002194: 4a77 ldr r2, [pc, #476] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002196: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800219a: 6013 str r3, [r2, #0]
|
|
800219c: 4b75 ldr r3, [pc, #468] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800219e: 681b ldr r3, [r3, #0]
|
|
80021a0: 4a74 ldr r2, [pc, #464] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80021a2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80021a6: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
80021a8: 687b ldr r3, [r7, #4]
|
|
80021aa: 685b ldr r3, [r3, #4]
|
|
80021ac: 2b00 cmp r3, #0
|
|
80021ae: d013 beq.n 80021d8 <HAL_RCC_OscConfig+0xe0>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80021b0: f7ff fb6a bl 8001888 <HAL_GetTick>
|
|
80021b4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80021b6: e008 b.n 80021ca <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80021b8: f7ff fb66 bl 8001888 <HAL_GetTick>
|
|
80021bc: 4602 mov r2, r0
|
|
80021be: 693b ldr r3, [r7, #16]
|
|
80021c0: 1ad3 subs r3, r2, r3
|
|
80021c2: 2b64 cmp r3, #100 @ 0x64
|
|
80021c4: d901 bls.n 80021ca <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80021c6: 2303 movs r3, #3
|
|
80021c8: e29e b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80021ca: 4b6a ldr r3, [pc, #424] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80021cc: 681b ldr r3, [r3, #0]
|
|
80021ce: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80021d2: 2b00 cmp r3, #0
|
|
80021d4: d0f0 beq.n 80021b8 <HAL_RCC_OscConfig+0xc0>
|
|
80021d6: e014 b.n 8002202 <HAL_RCC_OscConfig+0x10a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80021d8: f7ff fb56 bl 8001888 <HAL_GetTick>
|
|
80021dc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
80021de: e008 b.n 80021f2 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80021e0: f7ff fb52 bl 8001888 <HAL_GetTick>
|
|
80021e4: 4602 mov r2, r0
|
|
80021e6: 693b ldr r3, [r7, #16]
|
|
80021e8: 1ad3 subs r3, r2, r3
|
|
80021ea: 2b64 cmp r3, #100 @ 0x64
|
|
80021ec: d901 bls.n 80021f2 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80021ee: 2303 movs r3, #3
|
|
80021f0: e28a b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
80021f2: 4b60 ldr r3, [pc, #384] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80021f4: 681b ldr r3, [r3, #0]
|
|
80021f6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80021fa: 2b00 cmp r3, #0
|
|
80021fc: d1f0 bne.n 80021e0 <HAL_RCC_OscConfig+0xe8>
|
|
80021fe: e000 b.n 8002202 <HAL_RCC_OscConfig+0x10a>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8002200: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8002202: 687b ldr r3, [r7, #4]
|
|
8002204: 681b ldr r3, [r3, #0]
|
|
8002206: f003 0302 and.w r3, r3, #2
|
|
800220a: 2b00 cmp r3, #0
|
|
800220c: d075 beq.n 80022fa <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800220e: 4b59 ldr r3, [pc, #356] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002210: 689b ldr r3, [r3, #8]
|
|
8002212: f003 030c and.w r3, r3, #12
|
|
8002216: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8002218: 4b56 ldr r3, [pc, #344] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800221a: 68db ldr r3, [r3, #12]
|
|
800221c: f003 0303 and.w r3, r3, #3
|
|
8002220: 617b str r3, [r7, #20]
|
|
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
|
|
8002222: 69bb ldr r3, [r7, #24]
|
|
8002224: 2b0c cmp r3, #12
|
|
8002226: d102 bne.n 800222e <HAL_RCC_OscConfig+0x136>
|
|
8002228: 697b ldr r3, [r7, #20]
|
|
800222a: 2b02 cmp r3, #2
|
|
800222c: d002 beq.n 8002234 <HAL_RCC_OscConfig+0x13c>
|
|
800222e: 69bb ldr r3, [r7, #24]
|
|
8002230: 2b04 cmp r3, #4
|
|
8002232: d11f bne.n 8002274 <HAL_RCC_OscConfig+0x17c>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8002234: 4b4f ldr r3, [pc, #316] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002236: 681b ldr r3, [r3, #0]
|
|
8002238: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800223c: 2b00 cmp r3, #0
|
|
800223e: d005 beq.n 800224c <HAL_RCC_OscConfig+0x154>
|
|
8002240: 687b ldr r3, [r7, #4]
|
|
8002242: 68db ldr r3, [r3, #12]
|
|
8002244: 2b00 cmp r3, #0
|
|
8002246: d101 bne.n 800224c <HAL_RCC_OscConfig+0x154>
|
|
{
|
|
return HAL_ERROR;
|
|
8002248: 2301 movs r3, #1
|
|
800224a: e25d b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800224c: 4b49 ldr r3, [pc, #292] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800224e: 685b ldr r3, [r3, #4]
|
|
8002250: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
|
|
8002254: 687b ldr r3, [r7, #4]
|
|
8002256: 691b ldr r3, [r3, #16]
|
|
8002258: 061b lsls r3, r3, #24
|
|
800225a: 4946 ldr r1, [pc, #280] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800225c: 4313 orrs r3, r2
|
|
800225e: 604b str r3, [r1, #4]
|
|
|
|
/* Adapt Systick interrupt period */
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
8002260: 4b45 ldr r3, [pc, #276] @ (8002378 <HAL_RCC_OscConfig+0x280>)
|
|
8002262: 681b ldr r3, [r3, #0]
|
|
8002264: 4618 mov r0, r3
|
|
8002266: f7ff fac3 bl 80017f0 <HAL_InitTick>
|
|
800226a: 4603 mov r3, r0
|
|
800226c: 2b00 cmp r3, #0
|
|
800226e: d043 beq.n 80022f8 <HAL_RCC_OscConfig+0x200>
|
|
{
|
|
return HAL_ERROR;
|
|
8002270: 2301 movs r3, #1
|
|
8002272: e249 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8002274: 687b ldr r3, [r7, #4]
|
|
8002276: 68db ldr r3, [r3, #12]
|
|
8002278: 2b00 cmp r3, #0
|
|
800227a: d023 beq.n 80022c4 <HAL_RCC_OscConfig+0x1cc>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800227c: 4b3d ldr r3, [pc, #244] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800227e: 681b ldr r3, [r3, #0]
|
|
8002280: 4a3c ldr r2, [pc, #240] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002282: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002286: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002288: f7ff fafe bl 8001888 <HAL_GetTick>
|
|
800228c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
800228e: e008 b.n 80022a2 <HAL_RCC_OscConfig+0x1aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8002290: f7ff fafa bl 8001888 <HAL_GetTick>
|
|
8002294: 4602 mov r2, r0
|
|
8002296: 693b ldr r3, [r7, #16]
|
|
8002298: 1ad3 subs r3, r2, r3
|
|
800229a: 2b02 cmp r3, #2
|
|
800229c: d901 bls.n 80022a2 <HAL_RCC_OscConfig+0x1aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800229e: 2303 movs r3, #3
|
|
80022a0: e232 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
80022a2: 4b34 ldr r3, [pc, #208] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80022a4: 681b ldr r3, [r3, #0]
|
|
80022a6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80022aa: 2b00 cmp r3, #0
|
|
80022ac: d0f0 beq.n 8002290 <HAL_RCC_OscConfig+0x198>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80022ae: 4b31 ldr r3, [pc, #196] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80022b0: 685b ldr r3, [r3, #4]
|
|
80022b2: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
|
|
80022b6: 687b ldr r3, [r7, #4]
|
|
80022b8: 691b ldr r3, [r3, #16]
|
|
80022ba: 061b lsls r3, r3, #24
|
|
80022bc: 492d ldr r1, [pc, #180] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80022be: 4313 orrs r3, r2
|
|
80022c0: 604b str r3, [r1, #4]
|
|
80022c2: e01a b.n 80022fa <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
80022c4: 4b2b ldr r3, [pc, #172] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80022c6: 681b ldr r3, [r3, #0]
|
|
80022c8: 4a2a ldr r2, [pc, #168] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80022ca: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80022ce: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80022d0: f7ff fada bl 8001888 <HAL_GetTick>
|
|
80022d4: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
80022d6: e008 b.n 80022ea <HAL_RCC_OscConfig+0x1f2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
80022d8: f7ff fad6 bl 8001888 <HAL_GetTick>
|
|
80022dc: 4602 mov r2, r0
|
|
80022de: 693b ldr r3, [r7, #16]
|
|
80022e0: 1ad3 subs r3, r2, r3
|
|
80022e2: 2b02 cmp r3, #2
|
|
80022e4: d901 bls.n 80022ea <HAL_RCC_OscConfig+0x1f2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80022e6: 2303 movs r3, #3
|
|
80022e8: e20e b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
80022ea: 4b22 ldr r3, [pc, #136] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
80022ec: 681b ldr r3, [r3, #0]
|
|
80022ee: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80022f2: 2b00 cmp r3, #0
|
|
80022f4: d1f0 bne.n 80022d8 <HAL_RCC_OscConfig+0x1e0>
|
|
80022f6: e000 b.n 80022fa <HAL_RCC_OscConfig+0x202>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
80022f8: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80022fa: 687b ldr r3, [r7, #4]
|
|
80022fc: 681b ldr r3, [r3, #0]
|
|
80022fe: f003 0308 and.w r3, r3, #8
|
|
8002302: 2b00 cmp r3, #0
|
|
8002304: d041 beq.n 800238a <HAL_RCC_OscConfig+0x292>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8002306: 687b ldr r3, [r7, #4]
|
|
8002308: 695b ldr r3, [r3, #20]
|
|
800230a: 2b00 cmp r3, #0
|
|
800230c: d01c beq.n 8002348 <HAL_RCC_OscConfig+0x250>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
800230e: 4b19 ldr r3, [pc, #100] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002310: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002314: 4a17 ldr r2, [pc, #92] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002316: f043 0301 orr.w r3, r3, #1
|
|
800231a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800231e: f7ff fab3 bl 8001888 <HAL_GetTick>
|
|
8002322: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8002324: e008 b.n 8002338 <HAL_RCC_OscConfig+0x240>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8002326: f7ff faaf bl 8001888 <HAL_GetTick>
|
|
800232a: 4602 mov r2, r0
|
|
800232c: 693b ldr r3, [r7, #16]
|
|
800232e: 1ad3 subs r3, r2, r3
|
|
8002330: 2b02 cmp r3, #2
|
|
8002332: d901 bls.n 8002338 <HAL_RCC_OscConfig+0x240>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002334: 2303 movs r3, #3
|
|
8002336: e1e7 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8002338: 4b0e ldr r3, [pc, #56] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800233a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800233e: f003 0302 and.w r3, r3, #2
|
|
8002342: 2b00 cmp r3, #0
|
|
8002344: d0ef beq.n 8002326 <HAL_RCC_OscConfig+0x22e>
|
|
8002346: e020 b.n 800238a <HAL_RCC_OscConfig+0x292>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8002348: 4b0a ldr r3, [pc, #40] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
800234a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800234e: 4a09 ldr r2, [pc, #36] @ (8002374 <HAL_RCC_OscConfig+0x27c>)
|
|
8002350: f023 0301 bic.w r3, r3, #1
|
|
8002354: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002358: f7ff fa96 bl 8001888 <HAL_GetTick>
|
|
800235c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
800235e: e00d b.n 800237c <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8002360: f7ff fa92 bl 8001888 <HAL_GetTick>
|
|
8002364: 4602 mov r2, r0
|
|
8002366: 693b ldr r3, [r7, #16]
|
|
8002368: 1ad3 subs r3, r2, r3
|
|
800236a: 2b02 cmp r3, #2
|
|
800236c: d906 bls.n 800237c <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800236e: 2303 movs r3, #3
|
|
8002370: e1ca b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
8002372: bf00 nop
|
|
8002374: 40021000 .word 0x40021000
|
|
8002378: 20000010 .word 0x20000010
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
800237c: 4b8c ldr r3, [pc, #560] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
800237e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8002382: f003 0302 and.w r3, r3, #2
|
|
8002386: 2b00 cmp r3, #0
|
|
8002388: d1ea bne.n 8002360 <HAL_RCC_OscConfig+0x268>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
800238a: 687b ldr r3, [r7, #4]
|
|
800238c: 681b ldr r3, [r3, #0]
|
|
800238e: f003 0304 and.w r3, r3, #4
|
|
8002392: 2b00 cmp r3, #0
|
|
8002394: f000 80a6 beq.w 80024e4 <HAL_RCC_OscConfig+0x3ec>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8002398: 2300 movs r3, #0
|
|
800239a: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain if necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
800239c: 4b84 ldr r3, [pc, #528] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
800239e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80023a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80023a4: 2b00 cmp r3, #0
|
|
80023a6: d101 bne.n 80023ac <HAL_RCC_OscConfig+0x2b4>
|
|
80023a8: 2301 movs r3, #1
|
|
80023aa: e000 b.n 80023ae <HAL_RCC_OscConfig+0x2b6>
|
|
80023ac: 2300 movs r3, #0
|
|
80023ae: 2b00 cmp r3, #0
|
|
80023b0: d00d beq.n 80023ce <HAL_RCC_OscConfig+0x2d6>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80023b2: 4b7f ldr r3, [pc, #508] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80023b4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80023b6: 4a7e ldr r2, [pc, #504] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80023b8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80023bc: 6593 str r3, [r2, #88] @ 0x58
|
|
80023be: 4b7c ldr r3, [pc, #496] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80023c0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80023c2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80023c6: 60fb str r3, [r7, #12]
|
|
80023c8: 68fb ldr r3, [r7, #12]
|
|
pwrclkchanged = SET;
|
|
80023ca: 2301 movs r3, #1
|
|
80023cc: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
80023ce: 4b79 ldr r3, [pc, #484] @ (80025b4 <HAL_RCC_OscConfig+0x4bc>)
|
|
80023d0: 681b ldr r3, [r3, #0]
|
|
80023d2: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80023d6: 2b00 cmp r3, #0
|
|
80023d8: d118 bne.n 800240c <HAL_RCC_OscConfig+0x314>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80023da: 4b76 ldr r3, [pc, #472] @ (80025b4 <HAL_RCC_OscConfig+0x4bc>)
|
|
80023dc: 681b ldr r3, [r3, #0]
|
|
80023de: 4a75 ldr r2, [pc, #468] @ (80025b4 <HAL_RCC_OscConfig+0x4bc>)
|
|
80023e0: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80023e4: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80023e6: f7ff fa4f bl 8001888 <HAL_GetTick>
|
|
80023ea: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
80023ec: e008 b.n 8002400 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80023ee: f7ff fa4b bl 8001888 <HAL_GetTick>
|
|
80023f2: 4602 mov r2, r0
|
|
80023f4: 693b ldr r3, [r7, #16]
|
|
80023f6: 1ad3 subs r3, r2, r3
|
|
80023f8: 2b02 cmp r3, #2
|
|
80023fa: d901 bls.n 8002400 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80023fc: 2303 movs r3, #3
|
|
80023fe: e183 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8002400: 4b6c ldr r3, [pc, #432] @ (80025b4 <HAL_RCC_OscConfig+0x4bc>)
|
|
8002402: 681b ldr r3, [r3, #0]
|
|
8002404: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002408: 2b00 cmp r3, #0
|
|
800240a: d0f0 beq.n 80023ee <HAL_RCC_OscConfig+0x2f6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
800240c: 687b ldr r3, [r7, #4]
|
|
800240e: 689b ldr r3, [r3, #8]
|
|
8002410: 2b01 cmp r3, #1
|
|
8002412: d108 bne.n 8002426 <HAL_RCC_OscConfig+0x32e>
|
|
8002414: 4b66 ldr r3, [pc, #408] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002416: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800241a: 4a65 ldr r2, [pc, #404] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
800241c: f043 0301 orr.w r3, r3, #1
|
|
8002420: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8002424: e024 b.n 8002470 <HAL_RCC_OscConfig+0x378>
|
|
8002426: 687b ldr r3, [r7, #4]
|
|
8002428: 689b ldr r3, [r3, #8]
|
|
800242a: 2b05 cmp r3, #5
|
|
800242c: d110 bne.n 8002450 <HAL_RCC_OscConfig+0x358>
|
|
800242e: 4b60 ldr r3, [pc, #384] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002430: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002434: 4a5e ldr r2, [pc, #376] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002436: f043 0304 orr.w r3, r3, #4
|
|
800243a: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
800243e: 4b5c ldr r3, [pc, #368] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002440: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002444: 4a5a ldr r2, [pc, #360] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002446: f043 0301 orr.w r3, r3, #1
|
|
800244a: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
800244e: e00f b.n 8002470 <HAL_RCC_OscConfig+0x378>
|
|
8002450: 4b57 ldr r3, [pc, #348] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002452: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002456: 4a56 ldr r2, [pc, #344] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002458: f023 0301 bic.w r3, r3, #1
|
|
800245c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8002460: 4b53 ldr r3, [pc, #332] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002462: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002466: 4a52 ldr r2, [pc, #328] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002468: f023 0304 bic.w r3, r3, #4
|
|
800246c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8002470: 687b ldr r3, [r7, #4]
|
|
8002472: 689b ldr r3, [r3, #8]
|
|
8002474: 2b00 cmp r3, #0
|
|
8002476: d016 beq.n 80024a6 <HAL_RCC_OscConfig+0x3ae>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002478: f7ff fa06 bl 8001888 <HAL_GetTick>
|
|
800247c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
800247e: e00a b.n 8002496 <HAL_RCC_OscConfig+0x39e>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8002480: f7ff fa02 bl 8001888 <HAL_GetTick>
|
|
8002484: 4602 mov r2, r0
|
|
8002486: 693b ldr r3, [r7, #16]
|
|
8002488: 1ad3 subs r3, r2, r3
|
|
800248a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800248e: 4293 cmp r3, r2
|
|
8002490: d901 bls.n 8002496 <HAL_RCC_OscConfig+0x39e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002492: 2303 movs r3, #3
|
|
8002494: e138 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8002496: 4b46 ldr r3, [pc, #280] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002498: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800249c: f003 0302 and.w r3, r3, #2
|
|
80024a0: 2b00 cmp r3, #0
|
|
80024a2: d0ed beq.n 8002480 <HAL_RCC_OscConfig+0x388>
|
|
80024a4: e015 b.n 80024d2 <HAL_RCC_OscConfig+0x3da>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80024a6: f7ff f9ef bl 8001888 <HAL_GetTick>
|
|
80024aa: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
80024ac: e00a b.n 80024c4 <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80024ae: f7ff f9eb bl 8001888 <HAL_GetTick>
|
|
80024b2: 4602 mov r2, r0
|
|
80024b4: 693b ldr r3, [r7, #16]
|
|
80024b6: 1ad3 subs r3, r2, r3
|
|
80024b8: f241 3288 movw r2, #5000 @ 0x1388
|
|
80024bc: 4293 cmp r3, r2
|
|
80024be: d901 bls.n 80024c4 <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80024c0: 2303 movs r3, #3
|
|
80024c2: e121 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
80024c4: 4b3a ldr r3, [pc, #232] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80024c6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80024ca: f003 0302 and.w r3, r3, #2
|
|
80024ce: 2b00 cmp r3, #0
|
|
80024d0: d1ed bne.n 80024ae <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
80024d2: 7ffb ldrb r3, [r7, #31]
|
|
80024d4: 2b01 cmp r3, #1
|
|
80024d6: d105 bne.n 80024e4 <HAL_RCC_OscConfig+0x3ec>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80024d8: 4b35 ldr r3, [pc, #212] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80024da: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80024dc: 4a34 ldr r2, [pc, #208] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80024de: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80024e2: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*------------------------------ HSI48 Configuration -----------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|
80024e4: 687b ldr r3, [r7, #4]
|
|
80024e6: 681b ldr r3, [r3, #0]
|
|
80024e8: f003 0320 and.w r3, r3, #32
|
|
80024ec: 2b00 cmp r3, #0
|
|
80024ee: d03c beq.n 800256a <HAL_RCC_OscConfig+0x472>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|
|
|
/* Check the HSI48 State */
|
|
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|
80024f0: 687b ldr r3, [r7, #4]
|
|
80024f2: 699b ldr r3, [r3, #24]
|
|
80024f4: 2b00 cmp r3, #0
|
|
80024f6: d01c beq.n 8002532 <HAL_RCC_OscConfig+0x43a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_ENABLE();
|
|
80024f8: 4b2d ldr r3, [pc, #180] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
80024fa: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
80024fe: 4a2c ldr r2, [pc, #176] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002500: f043 0301 orr.w r3, r3, #1
|
|
8002504: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002508: f7ff f9be bl 8001888 <HAL_GetTick>
|
|
800250c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI48 is ready */
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
800250e: e008 b.n 8002522 <HAL_RCC_OscConfig+0x42a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
8002510: f7ff f9ba bl 8001888 <HAL_GetTick>
|
|
8002514: 4602 mov r2, r0
|
|
8002516: 693b ldr r3, [r7, #16]
|
|
8002518: 1ad3 subs r3, r2, r3
|
|
800251a: 2b02 cmp r3, #2
|
|
800251c: d901 bls.n 8002522 <HAL_RCC_OscConfig+0x42a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800251e: 2303 movs r3, #3
|
|
8002520: e0f2 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
8002522: 4b23 ldr r3, [pc, #140] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002524: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8002528: f003 0302 and.w r3, r3, #2
|
|
800252c: 2b00 cmp r3, #0
|
|
800252e: d0ef beq.n 8002510 <HAL_RCC_OscConfig+0x418>
|
|
8002530: e01b b.n 800256a <HAL_RCC_OscConfig+0x472>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_DISABLE();
|
|
8002532: 4b1f ldr r3, [pc, #124] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002534: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8002538: 4a1d ldr r2, [pc, #116] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
800253a: f023 0301 bic.w r3, r3, #1
|
|
800253e: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002542: f7ff f9a1 bl 8001888 <HAL_GetTick>
|
|
8002546: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI48 is disabled */
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
8002548: e008 b.n 800255c <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
800254a: f7ff f99d bl 8001888 <HAL_GetTick>
|
|
800254e: 4602 mov r2, r0
|
|
8002550: 693b ldr r3, [r7, #16]
|
|
8002552: 1ad3 subs r3, r2, r3
|
|
8002554: 2b02 cmp r3, #2
|
|
8002556: d901 bls.n 800255c <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002558: 2303 movs r3, #3
|
|
800255a: e0d5 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
800255c: 4b14 ldr r3, [pc, #80] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
800255e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8002562: f003 0302 and.w r3, r3, #2
|
|
8002566: 2b00 cmp r3, #0
|
|
8002568: d1ef bne.n 800254a <HAL_RCC_OscConfig+0x452>
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
800256a: 687b ldr r3, [r7, #4]
|
|
800256c: 69db ldr r3, [r3, #28]
|
|
800256e: 2b00 cmp r3, #0
|
|
8002570: f000 80c9 beq.w 8002706 <HAL_RCC_OscConfig+0x60e>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
8002574: 4b0e ldr r3, [pc, #56] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002576: 689b ldr r3, [r3, #8]
|
|
8002578: f003 030c and.w r3, r3, #12
|
|
800257c: 2b0c cmp r3, #12
|
|
800257e: f000 8083 beq.w 8002688 <HAL_RCC_OscConfig+0x590>
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8002582: 687b ldr r3, [r7, #4]
|
|
8002584: 69db ldr r3, [r3, #28]
|
|
8002586: 2b02 cmp r3, #2
|
|
8002588: d15e bne.n 8002648 <HAL_RCC_OscConfig+0x550>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800258a: 4b09 ldr r3, [pc, #36] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
800258c: 681b ldr r3, [r3, #0]
|
|
800258e: 4a08 ldr r2, [pc, #32] @ (80025b0 <HAL_RCC_OscConfig+0x4b8>)
|
|
8002590: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8002594: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002596: f7ff f977 bl 8001888 <HAL_GetTick>
|
|
800259a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800259c: e00c b.n 80025b8 <HAL_RCC_OscConfig+0x4c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800259e: f7ff f973 bl 8001888 <HAL_GetTick>
|
|
80025a2: 4602 mov r2, r0
|
|
80025a4: 693b ldr r3, [r7, #16]
|
|
80025a6: 1ad3 subs r3, r2, r3
|
|
80025a8: 2b02 cmp r3, #2
|
|
80025aa: d905 bls.n 80025b8 <HAL_RCC_OscConfig+0x4c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80025ac: 2303 movs r3, #3
|
|
80025ae: e0ab b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
80025b0: 40021000 .word 0x40021000
|
|
80025b4: 40007000 .word 0x40007000
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80025b8: 4b55 ldr r3, [pc, #340] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
80025ba: 681b ldr r3, [r3, #0]
|
|
80025bc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80025c0: 2b00 cmp r3, #0
|
|
80025c2: d1ec bne.n 800259e <HAL_RCC_OscConfig+0x4a6>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
80025c4: 4b52 ldr r3, [pc, #328] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
80025c6: 68da ldr r2, [r3, #12]
|
|
80025c8: 4b52 ldr r3, [pc, #328] @ (8002714 <HAL_RCC_OscConfig+0x61c>)
|
|
80025ca: 4013 ands r3, r2
|
|
80025cc: 687a ldr r2, [r7, #4]
|
|
80025ce: 6a11 ldr r1, [r2, #32]
|
|
80025d0: 687a ldr r2, [r7, #4]
|
|
80025d2: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
80025d4: 3a01 subs r2, #1
|
|
80025d6: 0112 lsls r2, r2, #4
|
|
80025d8: 4311 orrs r1, r2
|
|
80025da: 687a ldr r2, [r7, #4]
|
|
80025dc: 6a92 ldr r2, [r2, #40] @ 0x28
|
|
80025de: 0212 lsls r2, r2, #8
|
|
80025e0: 4311 orrs r1, r2
|
|
80025e2: 687a ldr r2, [r7, #4]
|
|
80025e4: 6b12 ldr r2, [r2, #48] @ 0x30
|
|
80025e6: 0852 lsrs r2, r2, #1
|
|
80025e8: 3a01 subs r2, #1
|
|
80025ea: 0552 lsls r2, r2, #21
|
|
80025ec: 4311 orrs r1, r2
|
|
80025ee: 687a ldr r2, [r7, #4]
|
|
80025f0: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
80025f2: 0852 lsrs r2, r2, #1
|
|
80025f4: 3a01 subs r2, #1
|
|
80025f6: 0652 lsls r2, r2, #25
|
|
80025f8: 4311 orrs r1, r2
|
|
80025fa: 687a ldr r2, [r7, #4]
|
|
80025fc: 6ad2 ldr r2, [r2, #44] @ 0x2c
|
|
80025fe: 06d2 lsls r2, r2, #27
|
|
8002600: 430a orrs r2, r1
|
|
8002602: 4943 ldr r1, [pc, #268] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
8002604: 4313 orrs r3, r2
|
|
8002606: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8002608: 4b41 ldr r3, [pc, #260] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800260a: 681b ldr r3, [r3, #0]
|
|
800260c: 4a40 ldr r2, [pc, #256] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800260e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8002612: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8002614: 4b3e ldr r3, [pc, #248] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
8002616: 68db ldr r3, [r3, #12]
|
|
8002618: 4a3d ldr r2, [pc, #244] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800261a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
800261e: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002620: f7ff f932 bl 8001888 <HAL_GetTick>
|
|
8002624: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8002626: e008 b.n 800263a <HAL_RCC_OscConfig+0x542>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8002628: f7ff f92e bl 8001888 <HAL_GetTick>
|
|
800262c: 4602 mov r2, r0
|
|
800262e: 693b ldr r3, [r7, #16]
|
|
8002630: 1ad3 subs r3, r2, r3
|
|
8002632: 2b02 cmp r3, #2
|
|
8002634: d901 bls.n 800263a <HAL_RCC_OscConfig+0x542>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002636: 2303 movs r3, #3
|
|
8002638: e066 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
800263a: 4b35 ldr r3, [pc, #212] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800263c: 681b ldr r3, [r3, #0]
|
|
800263e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002642: 2b00 cmp r3, #0
|
|
8002644: d0f0 beq.n 8002628 <HAL_RCC_OscConfig+0x530>
|
|
8002646: e05e b.n 8002706 <HAL_RCC_OscConfig+0x60e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8002648: 4b31 ldr r3, [pc, #196] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800264a: 681b ldr r3, [r3, #0]
|
|
800264c: 4a30 ldr r2, [pc, #192] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800264e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8002652: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002654: f7ff f918 bl 8001888 <HAL_GetTick>
|
|
8002658: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800265a: e008 b.n 800266e <HAL_RCC_OscConfig+0x576>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800265c: f7ff f914 bl 8001888 <HAL_GetTick>
|
|
8002660: 4602 mov r2, r0
|
|
8002662: 693b ldr r3, [r7, #16]
|
|
8002664: 1ad3 subs r3, r2, r3
|
|
8002666: 2b02 cmp r3, #2
|
|
8002668: d901 bls.n 800266e <HAL_RCC_OscConfig+0x576>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800266a: 2303 movs r3, #3
|
|
800266c: e04c b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800266e: 4b28 ldr r3, [pc, #160] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
8002670: 681b ldr r3, [r3, #0]
|
|
8002672: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002676: 2b00 cmp r3, #0
|
|
8002678: d1f0 bne.n 800265c <HAL_RCC_OscConfig+0x564>
|
|
}
|
|
}
|
|
|
|
/* Unselect PLL clock source and disable outputs to save power */
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
|
|
800267a: 4b25 ldr r3, [pc, #148] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
800267c: 68da ldr r2, [r3, #12]
|
|
800267e: 4924 ldr r1, [pc, #144] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
8002680: 4b25 ldr r3, [pc, #148] @ (8002718 <HAL_RCC_OscConfig+0x620>)
|
|
8002682: 4013 ands r3, r2
|
|
8002684: 60cb str r3, [r1, #12]
|
|
8002686: e03e b.n 8002706 <HAL_RCC_OscConfig+0x60e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8002688: 687b ldr r3, [r7, #4]
|
|
800268a: 69db ldr r3, [r3, #28]
|
|
800268c: 2b01 cmp r3, #1
|
|
800268e: d101 bne.n 8002694 <HAL_RCC_OscConfig+0x59c>
|
|
{
|
|
return HAL_ERROR;
|
|
8002690: 2301 movs r3, #1
|
|
8002692: e039 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
temp_pllckcfg = RCC->PLLCFGR;
|
|
8002694: 4b1e ldr r3, [pc, #120] @ (8002710 <HAL_RCC_OscConfig+0x618>)
|
|
8002696: 68db ldr r3, [r3, #12]
|
|
8002698: 617b str r3, [r7, #20]
|
|
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800269a: 697b ldr r3, [r7, #20]
|
|
800269c: f003 0203 and.w r2, r3, #3
|
|
80026a0: 687b ldr r3, [r7, #4]
|
|
80026a2: 6a1b ldr r3, [r3, #32]
|
|
80026a4: 429a cmp r2, r3
|
|
80026a6: d12c bne.n 8002702 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
80026a8: 697b ldr r3, [r7, #20]
|
|
80026aa: f003 02f0 and.w r2, r3, #240 @ 0xf0
|
|
80026ae: 687b ldr r3, [r7, #4]
|
|
80026b0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80026b2: 3b01 subs r3, #1
|
|
80026b4: 011b lsls r3, r3, #4
|
|
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
80026b6: 429a cmp r2, r3
|
|
80026b8: d123 bne.n 8002702 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
80026ba: 697b ldr r3, [r7, #20]
|
|
80026bc: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
80026c0: 687b ldr r3, [r7, #4]
|
|
80026c2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80026c4: 021b lsls r3, r3, #8
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
80026c6: 429a cmp r2, r3
|
|
80026c8: d11b bne.n 8002702 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
80026ca: 697b ldr r3, [r7, #20]
|
|
80026cc: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
|
|
80026d0: 687b ldr r3, [r7, #4]
|
|
80026d2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80026d4: 06db lsls r3, r3, #27
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
80026d6: 429a cmp r2, r3
|
|
80026d8: d113 bne.n 8002702 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80026da: 697b ldr r3, [r7, #20]
|
|
80026dc: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
|
|
80026e0: 687b ldr r3, [r7, #4]
|
|
80026e2: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80026e4: 085b lsrs r3, r3, #1
|
|
80026e6: 3b01 subs r3, #1
|
|
80026e8: 055b lsls r3, r3, #21
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
80026ea: 429a cmp r2, r3
|
|
80026ec: d109 bne.n 8002702 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
80026ee: 697b ldr r3, [r7, #20]
|
|
80026f0: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
|
|
80026f4: 687b ldr r3, [r7, #4]
|
|
80026f6: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80026f8: 085b lsrs r3, r3, #1
|
|
80026fa: 3b01 subs r3, #1
|
|
80026fc: 065b lsls r3, r3, #25
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80026fe: 429a cmp r2, r3
|
|
8002700: d001 beq.n 8002706 <HAL_RCC_OscConfig+0x60e>
|
|
{
|
|
return HAL_ERROR;
|
|
8002702: 2301 movs r3, #1
|
|
8002704: e000 b.n 8002708 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8002706: 2300 movs r3, #0
|
|
}
|
|
8002708: 4618 mov r0, r3
|
|
800270a: 3720 adds r7, #32
|
|
800270c: 46bd mov sp, r7
|
|
800270e: bd80 pop {r7, pc}
|
|
8002710: 40021000 .word 0x40021000
|
|
8002714: 019f800c .word 0x019f800c
|
|
8002718: feeefffc .word 0xfeeefffc
|
|
|
|
0800271c <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
800271c: b580 push {r7, lr}
|
|
800271e: b086 sub sp, #24
|
|
8002720: af00 add r7, sp, #0
|
|
8002722: 6078 str r0, [r7, #4]
|
|
8002724: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t pllfreq;
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
8002726: 2300 movs r3, #0
|
|
8002728: 617b str r3, [r7, #20]
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800272a: 687b ldr r3, [r7, #4]
|
|
800272c: 2b00 cmp r3, #0
|
|
800272e: d101 bne.n 8002734 <HAL_RCC_ClockConfig+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8002730: 2301 movs r3, #1
|
|
8002732: e11e b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8002734: 4b91 ldr r3, [pc, #580] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
8002736: 681b ldr r3, [r3, #0]
|
|
8002738: f003 030f and.w r3, r3, #15
|
|
800273c: 683a ldr r2, [r7, #0]
|
|
800273e: 429a cmp r2, r3
|
|
8002740: d910 bls.n 8002764 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8002742: 4b8e ldr r3, [pc, #568] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
8002744: 681b ldr r3, [r3, #0]
|
|
8002746: f023 020f bic.w r2, r3, #15
|
|
800274a: 498c ldr r1, [pc, #560] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
800274c: 683b ldr r3, [r7, #0]
|
|
800274e: 4313 orrs r3, r2
|
|
8002750: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8002752: 4b8a ldr r3, [pc, #552] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
8002754: 681b ldr r3, [r3, #0]
|
|
8002756: f003 030f and.w r3, r3, #15
|
|
800275a: 683a ldr r2, [r7, #0]
|
|
800275c: 429a cmp r2, r3
|
|
800275e: d001 beq.n 8002764 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
return HAL_ERROR;
|
|
8002760: 2301 movs r3, #1
|
|
8002762: e106 b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8002764: 687b ldr r3, [r7, #4]
|
|
8002766: 681b ldr r3, [r3, #0]
|
|
8002768: f003 0301 and.w r3, r3, #1
|
|
800276c: 2b00 cmp r3, #0
|
|
800276e: d073 beq.n 8002858 <HAL_RCC_ClockConfig+0x13c>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8002770: 687b ldr r3, [r7, #4]
|
|
8002772: 685b ldr r3, [r3, #4]
|
|
8002774: 2b03 cmp r3, #3
|
|
8002776: d129 bne.n 80027cc <HAL_RCC_ClockConfig+0xb0>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8002778: 4b81 ldr r3, [pc, #516] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
800277a: 681b ldr r3, [r3, #0]
|
|
800277c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002780: 2b00 cmp r3, #0
|
|
8002782: d101 bne.n 8002788 <HAL_RCC_ClockConfig+0x6c>
|
|
{
|
|
return HAL_ERROR;
|
|
8002784: 2301 movs r3, #1
|
|
8002786: e0f4 b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
|
|
/* Compute target PLL output frequency */
|
|
pllfreq = RCC_GetSysClockFreqFromPLLSource();
|
|
8002788: f000 f99e bl 8002ac8 <RCC_GetSysClockFreqFromPLLSource>
|
|
800278c: 6138 str r0, [r7, #16]
|
|
|
|
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
|
|
if(pllfreq > 80000000U)
|
|
800278e: 693b ldr r3, [r7, #16]
|
|
8002790: 4a7c ldr r2, [pc, #496] @ (8002984 <HAL_RCC_ClockConfig+0x268>)
|
|
8002792: 4293 cmp r3, r2
|
|
8002794: d93f bls.n 8002816 <HAL_RCC_ClockConfig+0xfa>
|
|
{
|
|
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
|
|
8002796: 4b7a ldr r3, [pc, #488] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002798: 689b ldr r3, [r3, #8]
|
|
800279a: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
800279e: 2b00 cmp r3, #0
|
|
80027a0: d009 beq.n 80027b6 <HAL_RCC_ClockConfig+0x9a>
|
|
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
|
|
80027a2: 687b ldr r3, [r7, #4]
|
|
80027a4: 681b ldr r3, [r3, #0]
|
|
80027a6: f003 0302 and.w r3, r3, #2
|
|
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
|
|
80027aa: 2b00 cmp r3, #0
|
|
80027ac: d033 beq.n 8002816 <HAL_RCC_ClockConfig+0xfa>
|
|
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
|
|
80027ae: 687b ldr r3, [r7, #4]
|
|
80027b0: 689b ldr r3, [r3, #8]
|
|
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
|
|
80027b2: 2b00 cmp r3, #0
|
|
80027b4: d12f bne.n 8002816 <HAL_RCC_ClockConfig+0xfa>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
|
|
80027b6: 4b72 ldr r3, [pc, #456] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80027b8: 689b ldr r3, [r3, #8]
|
|
80027ba: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
80027be: 4a70 ldr r2, [pc, #448] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80027c0: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80027c4: 6093 str r3, [r2, #8]
|
|
hpre = RCC_SYSCLK_DIV2;
|
|
80027c6: 2380 movs r3, #128 @ 0x80
|
|
80027c8: 617b str r3, [r7, #20]
|
|
80027ca: e024 b.n 8002816 <HAL_RCC_ClockConfig+0xfa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
80027cc: 687b ldr r3, [r7, #4]
|
|
80027ce: 685b ldr r3, [r3, #4]
|
|
80027d0: 2b02 cmp r3, #2
|
|
80027d2: d107 bne.n 80027e4 <HAL_RCC_ClockConfig+0xc8>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80027d4: 4b6a ldr r3, [pc, #424] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80027d6: 681b ldr r3, [r3, #0]
|
|
80027d8: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80027dc: 2b00 cmp r3, #0
|
|
80027de: d109 bne.n 80027f4 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
80027e0: 2301 movs r3, #1
|
|
80027e2: e0c6 b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
80027e4: 4b66 ldr r3, [pc, #408] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80027e6: 681b ldr r3, [r3, #0]
|
|
80027e8: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80027ec: 2b00 cmp r3, #0
|
|
80027ee: d101 bne.n 80027f4 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
80027f0: 2301 movs r3, #1
|
|
80027f2: e0be b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
}
|
|
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
|
|
pllfreq = HAL_RCC_GetSysClockFreq();
|
|
80027f4: f000 f8ce bl 8002994 <HAL_RCC_GetSysClockFreq>
|
|
80027f8: 6138 str r0, [r7, #16]
|
|
|
|
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
|
|
if(pllfreq > 80000000U)
|
|
80027fa: 693b ldr r3, [r7, #16]
|
|
80027fc: 4a61 ldr r2, [pc, #388] @ (8002984 <HAL_RCC_ClockConfig+0x268>)
|
|
80027fe: 4293 cmp r3, r2
|
|
8002800: d909 bls.n 8002816 <HAL_RCC_ClockConfig+0xfa>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
|
|
8002802: 4b5f ldr r3, [pc, #380] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002804: 689b ldr r3, [r3, #8]
|
|
8002806: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800280a: 4a5d ldr r2, [pc, #372] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
800280c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8002810: 6093 str r3, [r2, #8]
|
|
hpre = RCC_SYSCLK_DIV2;
|
|
8002812: 2380 movs r3, #128 @ 0x80
|
|
8002814: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
8002816: 4b5a ldr r3, [pc, #360] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002818: 689b ldr r3, [r3, #8]
|
|
800281a: f023 0203 bic.w r2, r3, #3
|
|
800281e: 687b ldr r3, [r7, #4]
|
|
8002820: 685b ldr r3, [r3, #4]
|
|
8002822: 4957 ldr r1, [pc, #348] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002824: 4313 orrs r3, r2
|
|
8002826: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002828: f7ff f82e bl 8001888 <HAL_GetTick>
|
|
800282c: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800282e: e00a b.n 8002846 <HAL_RCC_ClockConfig+0x12a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8002830: f7ff f82a bl 8001888 <HAL_GetTick>
|
|
8002834: 4602 mov r2, r0
|
|
8002836: 68fb ldr r3, [r7, #12]
|
|
8002838: 1ad3 subs r3, r2, r3
|
|
800283a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800283e: 4293 cmp r3, r2
|
|
8002840: d901 bls.n 8002846 <HAL_RCC_ClockConfig+0x12a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8002842: 2303 movs r3, #3
|
|
8002844: e095 b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8002846: 4b4e ldr r3, [pc, #312] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002848: 689b ldr r3, [r3, #8]
|
|
800284a: f003 020c and.w r2, r3, #12
|
|
800284e: 687b ldr r3, [r7, #4]
|
|
8002850: 685b ldr r3, [r3, #4]
|
|
8002852: 009b lsls r3, r3, #2
|
|
8002854: 429a cmp r2, r3
|
|
8002856: d1eb bne.n 8002830 <HAL_RCC_ClockConfig+0x114>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8002858: 687b ldr r3, [r7, #4]
|
|
800285a: 681b ldr r3, [r3, #0]
|
|
800285c: f003 0302 and.w r3, r3, #2
|
|
8002860: 2b00 cmp r3, #0
|
|
8002862: d023 beq.n 80028ac <HAL_RCC_ClockConfig+0x190>
|
|
{
|
|
/* Set the highest APB divider in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8002864: 687b ldr r3, [r7, #4]
|
|
8002866: 681b ldr r3, [r3, #0]
|
|
8002868: f003 0304 and.w r3, r3, #4
|
|
800286c: 2b00 cmp r3, #0
|
|
800286e: d005 beq.n 800287c <HAL_RCC_ClockConfig+0x160>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8002870: 4b43 ldr r3, [pc, #268] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002872: 689b ldr r3, [r3, #8]
|
|
8002874: 4a42 ldr r2, [pc, #264] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002876: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
800287a: 6093 str r3, [r2, #8]
|
|
}
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
800287c: 687b ldr r3, [r7, #4]
|
|
800287e: 681b ldr r3, [r3, #0]
|
|
8002880: f003 0308 and.w r3, r3, #8
|
|
8002884: 2b00 cmp r3, #0
|
|
8002886: d007 beq.n 8002898 <HAL_RCC_ClockConfig+0x17c>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
|
|
8002888: 4b3d ldr r3, [pc, #244] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
800288a: 689b ldr r3, [r3, #8]
|
|
800288c: f423 537c bic.w r3, r3, #16128 @ 0x3f00
|
|
8002890: 4a3b ldr r2, [pc, #236] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002892: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
8002896: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8002898: 4b39 ldr r3, [pc, #228] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
800289a: 689b ldr r3, [r3, #8]
|
|
800289c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
80028a0: 687b ldr r3, [r7, #4]
|
|
80028a2: 689b ldr r3, [r3, #8]
|
|
80028a4: 4936 ldr r1, [pc, #216] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80028a6: 4313 orrs r3, r2
|
|
80028a8: 608b str r3, [r1, #8]
|
|
80028aa: e008 b.n 80028be <HAL_RCC_ClockConfig+0x1a2>
|
|
}
|
|
else
|
|
{
|
|
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
|
|
if(hpre == RCC_SYSCLK_DIV2)
|
|
80028ac: 697b ldr r3, [r7, #20]
|
|
80028ae: 2b80 cmp r3, #128 @ 0x80
|
|
80028b0: d105 bne.n 80028be <HAL_RCC_ClockConfig+0x1a2>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
|
|
80028b2: 4b33 ldr r3, [pc, #204] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80028b4: 689b ldr r3, [r3, #8]
|
|
80028b6: 4a32 ldr r2, [pc, #200] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
80028b8: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
80028bc: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80028be: 4b2f ldr r3, [pc, #188] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
80028c0: 681b ldr r3, [r3, #0]
|
|
80028c2: f003 030f and.w r3, r3, #15
|
|
80028c6: 683a ldr r2, [r7, #0]
|
|
80028c8: 429a cmp r2, r3
|
|
80028ca: d21d bcs.n 8002908 <HAL_RCC_ClockConfig+0x1ec>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80028cc: 4b2b ldr r3, [pc, #172] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
80028ce: 681b ldr r3, [r3, #0]
|
|
80028d0: f023 020f bic.w r2, r3, #15
|
|
80028d4: 4929 ldr r1, [pc, #164] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
80028d6: 683b ldr r3, [r7, #0]
|
|
80028d8: 4313 orrs r3, r2
|
|
80028da: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by polling the FLASH_ACR register */
|
|
tickstart = HAL_GetTick();
|
|
80028dc: f7fe ffd4 bl 8001888 <HAL_GetTick>
|
|
80028e0: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80028e2: e00a b.n 80028fa <HAL_RCC_ClockConfig+0x1de>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80028e4: f7fe ffd0 bl 8001888 <HAL_GetTick>
|
|
80028e8: 4602 mov r2, r0
|
|
80028ea: 68fb ldr r3, [r7, #12]
|
|
80028ec: 1ad3 subs r3, r2, r3
|
|
80028ee: f241 3288 movw r2, #5000 @ 0x1388
|
|
80028f2: 4293 cmp r3, r2
|
|
80028f4: d901 bls.n 80028fa <HAL_RCC_ClockConfig+0x1de>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80028f6: 2303 movs r3, #3
|
|
80028f8: e03b b.n 8002972 <HAL_RCC_ClockConfig+0x256>
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80028fa: 4b20 ldr r3, [pc, #128] @ (800297c <HAL_RCC_ClockConfig+0x260>)
|
|
80028fc: 681b ldr r3, [r3, #0]
|
|
80028fe: f003 030f and.w r3, r3, #15
|
|
8002902: 683a ldr r2, [r7, #0]
|
|
8002904: 429a cmp r2, r3
|
|
8002906: d1ed bne.n 80028e4 <HAL_RCC_ClockConfig+0x1c8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8002908: 687b ldr r3, [r7, #4]
|
|
800290a: 681b ldr r3, [r3, #0]
|
|
800290c: f003 0304 and.w r3, r3, #4
|
|
8002910: 2b00 cmp r3, #0
|
|
8002912: d008 beq.n 8002926 <HAL_RCC_ClockConfig+0x20a>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8002914: 4b1a ldr r3, [pc, #104] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002916: 689b ldr r3, [r3, #8]
|
|
8002918: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
800291c: 687b ldr r3, [r7, #4]
|
|
800291e: 68db ldr r3, [r3, #12]
|
|
8002920: 4917 ldr r1, [pc, #92] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002922: 4313 orrs r3, r2
|
|
8002924: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8002926: 687b ldr r3, [r7, #4]
|
|
8002928: 681b ldr r3, [r3, #0]
|
|
800292a: f003 0308 and.w r3, r3, #8
|
|
800292e: 2b00 cmp r3, #0
|
|
8002930: d009 beq.n 8002946 <HAL_RCC_ClockConfig+0x22a>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8002932: 4b13 ldr r3, [pc, #76] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002934: 689b ldr r3, [r3, #8]
|
|
8002936: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
800293a: 687b ldr r3, [r7, #4]
|
|
800293c: 691b ldr r3, [r3, #16]
|
|
800293e: 00db lsls r3, r3, #3
|
|
8002940: 490f ldr r1, [pc, #60] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
8002942: 4313 orrs r3, r2
|
|
8002944: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8002946: f000 f825 bl 8002994 <HAL_RCC_GetSysClockFreq>
|
|
800294a: 4602 mov r2, r0
|
|
800294c: 4b0c ldr r3, [pc, #48] @ (8002980 <HAL_RCC_ClockConfig+0x264>)
|
|
800294e: 689b ldr r3, [r3, #8]
|
|
8002950: 091b lsrs r3, r3, #4
|
|
8002952: f003 030f and.w r3, r3, #15
|
|
8002956: 490c ldr r1, [pc, #48] @ (8002988 <HAL_RCC_ClockConfig+0x26c>)
|
|
8002958: 5ccb ldrb r3, [r1, r3]
|
|
800295a: f003 031f and.w r3, r3, #31
|
|
800295e: fa22 f303 lsr.w r3, r2, r3
|
|
8002962: 4a0a ldr r2, [pc, #40] @ (800298c <HAL_RCC_ClockConfig+0x270>)
|
|
8002964: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
return HAL_InitTick(uwTickPrio);
|
|
8002966: 4b0a ldr r3, [pc, #40] @ (8002990 <HAL_RCC_ClockConfig+0x274>)
|
|
8002968: 681b ldr r3, [r3, #0]
|
|
800296a: 4618 mov r0, r3
|
|
800296c: f7fe ff40 bl 80017f0 <HAL_InitTick>
|
|
8002970: 4603 mov r3, r0
|
|
}
|
|
8002972: 4618 mov r0, r3
|
|
8002974: 3718 adds r7, #24
|
|
8002976: 46bd mov sp, r7
|
|
8002978: bd80 pop {r7, pc}
|
|
800297a: bf00 nop
|
|
800297c: 40022000 .word 0x40022000
|
|
8002980: 40021000 .word 0x40021000
|
|
8002984: 04c4b400 .word 0x04c4b400
|
|
8002988: 08005ac0 .word 0x08005ac0
|
|
800298c: 2000000c .word 0x2000000c
|
|
8002990: 20000010 .word 0x20000010
|
|
|
|
08002994 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8002994: b480 push {r7}
|
|
8002996: b087 sub sp, #28
|
|
8002998: af00 add r7, sp, #0
|
|
uint32_t pllvco, pllsource, pllr, pllm;
|
|
uint32_t sysclockfreq;
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
800299a: 4b2c ldr r3, [pc, #176] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
800299c: 689b ldr r3, [r3, #8]
|
|
800299e: f003 030c and.w r3, r3, #12
|
|
80029a2: 2b04 cmp r3, #4
|
|
80029a4: d102 bne.n 80029ac <HAL_RCC_GetSysClockFreq+0x18>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
80029a6: 4b2a ldr r3, [pc, #168] @ (8002a50 <HAL_RCC_GetSysClockFreq+0xbc>)
|
|
80029a8: 613b str r3, [r7, #16]
|
|
80029aa: e047 b.n 8002a3c <HAL_RCC_GetSysClockFreq+0xa8>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
80029ac: 4b27 ldr r3, [pc, #156] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80029ae: 689b ldr r3, [r3, #8]
|
|
80029b0: f003 030c and.w r3, r3, #12
|
|
80029b4: 2b08 cmp r3, #8
|
|
80029b6: d102 bne.n 80029be <HAL_RCC_GetSysClockFreq+0x2a>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
80029b8: 4b26 ldr r3, [pc, #152] @ (8002a54 <HAL_RCC_GetSysClockFreq+0xc0>)
|
|
80029ba: 613b str r3, [r7, #16]
|
|
80029bc: e03e b.n 8002a3c <HAL_RCC_GetSysClockFreq+0xa8>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
|
|
80029be: 4b23 ldr r3, [pc, #140] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80029c0: 689b ldr r3, [r3, #8]
|
|
80029c2: f003 030c and.w r3, r3, #12
|
|
80029c6: 2b0c cmp r3, #12
|
|
80029c8: d136 bne.n 8002a38 <HAL_RCC_GetSysClockFreq+0xa4>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
80029ca: 4b20 ldr r3, [pc, #128] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80029cc: 68db ldr r3, [r3, #12]
|
|
80029ce: f003 0303 and.w r3, r3, #3
|
|
80029d2: 60fb str r3, [r7, #12]
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
80029d4: 4b1d ldr r3, [pc, #116] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80029d6: 68db ldr r3, [r3, #12]
|
|
80029d8: 091b lsrs r3, r3, #4
|
|
80029da: f003 030f and.w r3, r3, #15
|
|
80029de: 3301 adds r3, #1
|
|
80029e0: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
80029e2: 68fb ldr r3, [r7, #12]
|
|
80029e4: 2b03 cmp r3, #3
|
|
80029e6: d10c bne.n 8002a02 <HAL_RCC_GetSysClockFreq+0x6e>
|
|
{
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
80029e8: 4a1a ldr r2, [pc, #104] @ (8002a54 <HAL_RCC_GetSysClockFreq+0xc0>)
|
|
80029ea: 68bb ldr r3, [r7, #8]
|
|
80029ec: fbb2 f3f3 udiv r3, r2, r3
|
|
80029f0: 4a16 ldr r2, [pc, #88] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80029f2: 68d2 ldr r2, [r2, #12]
|
|
80029f4: 0a12 lsrs r2, r2, #8
|
|
80029f6: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
80029fa: fb02 f303 mul.w r3, r2, r3
|
|
80029fe: 617b str r3, [r7, #20]
|
|
break;
|
|
8002a00: e00c b.n 8002a1c <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
default:
|
|
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8002a02: 4a13 ldr r2, [pc, #76] @ (8002a50 <HAL_RCC_GetSysClockFreq+0xbc>)
|
|
8002a04: 68bb ldr r3, [r7, #8]
|
|
8002a06: fbb2 f3f3 udiv r3, r2, r3
|
|
8002a0a: 4a10 ldr r2, [pc, #64] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8002a0c: 68d2 ldr r2, [r2, #12]
|
|
8002a0e: 0a12 lsrs r2, r2, #8
|
|
8002a10: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
8002a14: fb02 f303 mul.w r3, r2, r3
|
|
8002a18: 617b str r3, [r7, #20]
|
|
break;
|
|
8002a1a: bf00 nop
|
|
}
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
8002a1c: 4b0b ldr r3, [pc, #44] @ (8002a4c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8002a1e: 68db ldr r3, [r3, #12]
|
|
8002a20: 0e5b lsrs r3, r3, #25
|
|
8002a22: f003 0303 and.w r3, r3, #3
|
|
8002a26: 3301 adds r3, #1
|
|
8002a28: 005b lsls r3, r3, #1
|
|
8002a2a: 607b str r3, [r7, #4]
|
|
sysclockfreq = pllvco/pllr;
|
|
8002a2c: 697a ldr r2, [r7, #20]
|
|
8002a2e: 687b ldr r3, [r7, #4]
|
|
8002a30: fbb2 f3f3 udiv r3, r2, r3
|
|
8002a34: 613b str r3, [r7, #16]
|
|
8002a36: e001 b.n 8002a3c <HAL_RCC_GetSysClockFreq+0xa8>
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = 0U;
|
|
8002a38: 2300 movs r3, #0
|
|
8002a3a: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
8002a3c: 693b ldr r3, [r7, #16]
|
|
}
|
|
8002a3e: 4618 mov r0, r3
|
|
8002a40: 371c adds r7, #28
|
|
8002a42: 46bd mov sp, r7
|
|
8002a44: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002a48: 4770 bx lr
|
|
8002a4a: bf00 nop
|
|
8002a4c: 40021000 .word 0x40021000
|
|
8002a50: 00f42400 .word 0x00f42400
|
|
8002a54: 007a1200 .word 0x007a1200
|
|
|
|
08002a58 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8002a58: b480 push {r7}
|
|
8002a5a: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8002a5c: 4b03 ldr r3, [pc, #12] @ (8002a6c <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8002a5e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002a60: 4618 mov r0, r3
|
|
8002a62: 46bd mov sp, r7
|
|
8002a64: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002a68: 4770 bx lr
|
|
8002a6a: bf00 nop
|
|
8002a6c: 2000000c .word 0x2000000c
|
|
|
|
08002a70 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8002a70: b580 push {r7, lr}
|
|
8002a72: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
8002a74: f7ff fff0 bl 8002a58 <HAL_RCC_GetHCLKFreq>
|
|
8002a78: 4602 mov r2, r0
|
|
8002a7a: 4b06 ldr r3, [pc, #24] @ (8002a94 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8002a7c: 689b ldr r3, [r3, #8]
|
|
8002a7e: 0a1b lsrs r3, r3, #8
|
|
8002a80: f003 0307 and.w r3, r3, #7
|
|
8002a84: 4904 ldr r1, [pc, #16] @ (8002a98 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
8002a86: 5ccb ldrb r3, [r1, r3]
|
|
8002a88: f003 031f and.w r3, r3, #31
|
|
8002a8c: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8002a90: 4618 mov r0, r3
|
|
8002a92: bd80 pop {r7, pc}
|
|
8002a94: 40021000 .word 0x40021000
|
|
8002a98: 08005ad0 .word 0x08005ad0
|
|
|
|
08002a9c <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8002a9c: b580 push {r7, lr}
|
|
8002a9e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
8002aa0: f7ff ffda bl 8002a58 <HAL_RCC_GetHCLKFreq>
|
|
8002aa4: 4602 mov r2, r0
|
|
8002aa6: 4b06 ldr r3, [pc, #24] @ (8002ac0 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8002aa8: 689b ldr r3, [r3, #8]
|
|
8002aaa: 0adb lsrs r3, r3, #11
|
|
8002aac: f003 0307 and.w r3, r3, #7
|
|
8002ab0: 4904 ldr r1, [pc, #16] @ (8002ac4 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
8002ab2: 5ccb ldrb r3, [r1, r3]
|
|
8002ab4: f003 031f and.w r3, r3, #31
|
|
8002ab8: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8002abc: 4618 mov r0, r3
|
|
8002abe: bd80 pop {r7, pc}
|
|
8002ac0: 40021000 .word 0x40021000
|
|
8002ac4: 08005ad0 .word 0x08005ad0
|
|
|
|
08002ac8 <RCC_GetSysClockFreqFromPLLSource>:
|
|
/**
|
|
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
|
|
{
|
|
8002ac8: b480 push {r7}
|
|
8002aca: b087 sub sp, #28
|
|
8002acc: af00 add r7, sp, #0
|
|
uint32_t sysclockfreq;
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
8002ace: 4b1e ldr r3, [pc, #120] @ (8002b48 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8002ad0: 68db ldr r3, [r3, #12]
|
|
8002ad2: f003 0303 and.w r3, r3, #3
|
|
8002ad6: 613b str r3, [r7, #16]
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8002ad8: 4b1b ldr r3, [pc, #108] @ (8002b48 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8002ada: 68db ldr r3, [r3, #12]
|
|
8002adc: 091b lsrs r3, r3, #4
|
|
8002ade: f003 030f and.w r3, r3, #15
|
|
8002ae2: 3301 adds r3, #1
|
|
8002ae4: 60fb str r3, [r7, #12]
|
|
|
|
switch (pllsource)
|
|
8002ae6: 693b ldr r3, [r7, #16]
|
|
8002ae8: 2b03 cmp r3, #3
|
|
8002aea: d10c bne.n 8002b06 <RCC_GetSysClockFreqFromPLLSource+0x3e>
|
|
{
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8002aec: 4a17 ldr r2, [pc, #92] @ (8002b4c <RCC_GetSysClockFreqFromPLLSource+0x84>)
|
|
8002aee: 68fb ldr r3, [r7, #12]
|
|
8002af0: fbb2 f3f3 udiv r3, r2, r3
|
|
8002af4: 4a14 ldr r2, [pc, #80] @ (8002b48 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8002af6: 68d2 ldr r2, [r2, #12]
|
|
8002af8: 0a12 lsrs r2, r2, #8
|
|
8002afa: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
8002afe: fb02 f303 mul.w r3, r2, r3
|
|
8002b02: 617b str r3, [r7, #20]
|
|
break;
|
|
8002b04: e00c b.n 8002b20 <RCC_GetSysClockFreqFromPLLSource+0x58>
|
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
default:
|
|
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8002b06: 4a12 ldr r2, [pc, #72] @ (8002b50 <RCC_GetSysClockFreqFromPLLSource+0x88>)
|
|
8002b08: 68fb ldr r3, [r7, #12]
|
|
8002b0a: fbb2 f3f3 udiv r3, r2, r3
|
|
8002b0e: 4a0e ldr r2, [pc, #56] @ (8002b48 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8002b10: 68d2 ldr r2, [r2, #12]
|
|
8002b12: 0a12 lsrs r2, r2, #8
|
|
8002b14: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
8002b18: fb02 f303 mul.w r3, r2, r3
|
|
8002b1c: 617b str r3, [r7, #20]
|
|
break;
|
|
8002b1e: bf00 nop
|
|
}
|
|
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
8002b20: 4b09 ldr r3, [pc, #36] @ (8002b48 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8002b22: 68db ldr r3, [r3, #12]
|
|
8002b24: 0e5b lsrs r3, r3, #25
|
|
8002b26: f003 0303 and.w r3, r3, #3
|
|
8002b2a: 3301 adds r3, #1
|
|
8002b2c: 005b lsls r3, r3, #1
|
|
8002b2e: 60bb str r3, [r7, #8]
|
|
sysclockfreq = pllvco/pllr;
|
|
8002b30: 697a ldr r2, [r7, #20]
|
|
8002b32: 68bb ldr r3, [r7, #8]
|
|
8002b34: fbb2 f3f3 udiv r3, r2, r3
|
|
8002b38: 607b str r3, [r7, #4]
|
|
|
|
return sysclockfreq;
|
|
8002b3a: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002b3c: 4618 mov r0, r3
|
|
8002b3e: 371c adds r7, #28
|
|
8002b40: 46bd mov sp, r7
|
|
8002b42: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002b46: 4770 bx lr
|
|
8002b48: 40021000 .word 0x40021000
|
|
8002b4c: 007a1200 .word 0x007a1200
|
|
8002b50: 00f42400 .word 0x00f42400
|
|
|
|
08002b54 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit)
|
|
{
|
|
8002b54: b580 push {r7, lr}
|
|
8002b56: b086 sub sp, #24
|
|
8002b58: af00 add r7, sp, #0
|
|
8002b5a: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister;
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8002b5c: 2300 movs r3, #0
|
|
8002b5e: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8002b60: 2300 movs r3, #0
|
|
8002b62: 74bb strb r3, [r7, #18]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8002b64: 687b ldr r3, [r7, #4]
|
|
8002b66: 681b ldr r3, [r3, #0]
|
|
8002b68: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
8002b6c: 2b00 cmp r3, #0
|
|
8002b6e: f000 8098 beq.w 8002ca2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8002b72: 2300 movs r3, #0
|
|
8002b74: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8002b76: 4b43 ldr r3, [pc, #268] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002b78: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002b7a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002b7e: 2b00 cmp r3, #0
|
|
8002b80: d10d bne.n 8002b9e <HAL_RCCEx_PeriphCLKConfig+0x4a>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002b82: 4b40 ldr r3, [pc, #256] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002b84: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002b86: 4a3f ldr r2, [pc, #252] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002b88: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8002b8c: 6593 str r3, [r2, #88] @ 0x58
|
|
8002b8e: 4b3d ldr r3, [pc, #244] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002b90: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002b92: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8002b96: 60bb str r3, [r7, #8]
|
|
8002b98: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8002b9a: 2301 movs r3, #1
|
|
8002b9c: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8002b9e: 4b3a ldr r3, [pc, #232] @ (8002c88 <HAL_RCCEx_PeriphCLKConfig+0x134>)
|
|
8002ba0: 681b ldr r3, [r3, #0]
|
|
8002ba2: 4a39 ldr r2, [pc, #228] @ (8002c88 <HAL_RCCEx_PeriphCLKConfig+0x134>)
|
|
8002ba4: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8002ba8: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8002baa: f7fe fe6d bl 8001888 <HAL_GetTick>
|
|
8002bae: 60f8 str r0, [r7, #12]
|
|
|
|
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
|
|
8002bb0: e009 b.n 8002bc6 <HAL_RCCEx_PeriphCLKConfig+0x72>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8002bb2: f7fe fe69 bl 8001888 <HAL_GetTick>
|
|
8002bb6: 4602 mov r2, r0
|
|
8002bb8: 68fb ldr r3, [r7, #12]
|
|
8002bba: 1ad3 subs r3, r2, r3
|
|
8002bbc: 2b02 cmp r3, #2
|
|
8002bbe: d902 bls.n 8002bc6 <HAL_RCCEx_PeriphCLKConfig+0x72>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8002bc0: 2303 movs r3, #3
|
|
8002bc2: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8002bc4: e005 b.n 8002bd2 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
|
|
8002bc6: 4b30 ldr r3, [pc, #192] @ (8002c88 <HAL_RCCEx_PeriphCLKConfig+0x134>)
|
|
8002bc8: 681b ldr r3, [r3, #0]
|
|
8002bca: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002bce: 2b00 cmp r3, #0
|
|
8002bd0: d0ef beq.n 8002bb2 <HAL_RCCEx_PeriphCLKConfig+0x5e>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8002bd2: 7cfb ldrb r3, [r7, #19]
|
|
8002bd4: 2b00 cmp r3, #0
|
|
8002bd6: d159 bne.n 8002c8c <HAL_RCCEx_PeriphCLKConfig+0x138>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
8002bd8: 4b2a ldr r3, [pc, #168] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002bda: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002bde: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8002be2: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
8002be4: 697b ldr r3, [r7, #20]
|
|
8002be6: 2b00 cmp r3, #0
|
|
8002be8: d01e beq.n 8002c28 <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
8002bea: 687b ldr r3, [r7, #4]
|
|
8002bec: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002bee: 697a ldr r2, [r7, #20]
|
|
8002bf0: 429a cmp r2, r3
|
|
8002bf2: d019 beq.n 8002c28 <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
8002bf4: 4b23 ldr r3, [pc, #140] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002bf6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002bfa: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8002bfe: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8002c00: 4b20 ldr r3, [pc, #128] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c02: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002c06: 4a1f ldr r2, [pc, #124] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c08: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8002c0c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8002c10: 4b1c ldr r3, [pc, #112] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002c16: 4a1b ldr r2, [pc, #108] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c18: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8002c1c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8002c20: 4a18 ldr r2, [pc, #96] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c22: 697b ldr r3, [r7, #20]
|
|
8002c24: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8002c28: 697b ldr r3, [r7, #20]
|
|
8002c2a: f003 0301 and.w r3, r3, #1
|
|
8002c2e: 2b00 cmp r3, #0
|
|
8002c30: d016 beq.n 8002c60 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8002c32: f7fe fe29 bl 8001888 <HAL_GetTick>
|
|
8002c36: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8002c38: e00b b.n 8002c52 <HAL_RCCEx_PeriphCLKConfig+0xfe>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8002c3a: f7fe fe25 bl 8001888 <HAL_GetTick>
|
|
8002c3e: 4602 mov r2, r0
|
|
8002c40: 68fb ldr r3, [r7, #12]
|
|
8002c42: 1ad3 subs r3, r2, r3
|
|
8002c44: f241 3288 movw r2, #5000 @ 0x1388
|
|
8002c48: 4293 cmp r3, r2
|
|
8002c4a: d902 bls.n 8002c52 <HAL_RCCEx_PeriphCLKConfig+0xfe>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8002c4c: 2303 movs r3, #3
|
|
8002c4e: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8002c50: e006 b.n 8002c60 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8002c52: 4b0c ldr r3, [pc, #48] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c54: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002c58: f003 0302 and.w r3, r3, #2
|
|
8002c5c: 2b00 cmp r3, #0
|
|
8002c5e: d0ec beq.n 8002c3a <HAL_RCCEx_PeriphCLKConfig+0xe6>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8002c60: 7cfb ldrb r3, [r7, #19]
|
|
8002c62: 2b00 cmp r3, #0
|
|
8002c64: d10b bne.n 8002c7e <HAL_RCCEx_PeriphCLKConfig+0x12a>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8002c66: 4b07 ldr r3, [pc, #28] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c68: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8002c6c: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8002c70: 687b ldr r3, [r7, #4]
|
|
8002c72: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002c74: 4903 ldr r1, [pc, #12] @ (8002c84 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8002c76: 4313 orrs r3, r2
|
|
8002c78: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
8002c7c: e008 b.n 8002c90 <HAL_RCCEx_PeriphCLKConfig+0x13c>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8002c7e: 7cfb ldrb r3, [r7, #19]
|
|
8002c80: 74bb strb r3, [r7, #18]
|
|
8002c82: e005 b.n 8002c90 <HAL_RCCEx_PeriphCLKConfig+0x13c>
|
|
8002c84: 40021000 .word 0x40021000
|
|
8002c88: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8002c8c: 7cfb ldrb r3, [r7, #19]
|
|
8002c8e: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8002c90: 7c7b ldrb r3, [r7, #17]
|
|
8002c92: 2b01 cmp r3, #1
|
|
8002c94: d105 bne.n 8002ca2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8002c96: 4ba6 ldr r3, [pc, #664] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002c98: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002c9a: 4aa5 ldr r2, [pc, #660] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002c9c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8002ca0: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
8002ca2: 687b ldr r3, [r7, #4]
|
|
8002ca4: 681b ldr r3, [r3, #0]
|
|
8002ca6: f003 0301 and.w r3, r3, #1
|
|
8002caa: 2b00 cmp r3, #0
|
|
8002cac: d00a beq.n 8002cc4 <HAL_RCCEx_PeriphCLKConfig+0x170>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
8002cae: 4ba0 ldr r3, [pc, #640] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002cb0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002cb4: f023 0203 bic.w r2, r3, #3
|
|
8002cb8: 687b ldr r3, [r7, #4]
|
|
8002cba: 685b ldr r3, [r3, #4]
|
|
8002cbc: 499c ldr r1, [pc, #624] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002cbe: 4313 orrs r3, r2
|
|
8002cc0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8002cc4: 687b ldr r3, [r7, #4]
|
|
8002cc6: 681b ldr r3, [r3, #0]
|
|
8002cc8: f003 0302 and.w r3, r3, #2
|
|
8002ccc: 2b00 cmp r3, #0
|
|
8002cce: d00a beq.n 8002ce6 <HAL_RCCEx_PeriphCLKConfig+0x192>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
8002cd0: 4b97 ldr r3, [pc, #604] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002cd2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002cd6: f023 020c bic.w r2, r3, #12
|
|
8002cda: 687b ldr r3, [r7, #4]
|
|
8002cdc: 689b ldr r3, [r3, #8]
|
|
8002cde: 4994 ldr r1, [pc, #592] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002ce0: 4313 orrs r3, r2
|
|
8002ce2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
8002ce6: 687b ldr r3, [r7, #4]
|
|
8002ce8: 681b ldr r3, [r3, #0]
|
|
8002cea: f003 0304 and.w r3, r3, #4
|
|
8002cee: 2b00 cmp r3, #0
|
|
8002cf0: d00a beq.n 8002d08 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
8002cf2: 4b8f ldr r3, [pc, #572] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002cf4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002cf8: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
8002cfc: 687b ldr r3, [r7, #4]
|
|
8002cfe: 68db ldr r3, [r3, #12]
|
|
8002d00: 498b ldr r1, [pc, #556] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d02: 4313 orrs r3, r2
|
|
8002d04: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
8002d08: 687b ldr r3, [r7, #4]
|
|
8002d0a: 681b ldr r3, [r3, #0]
|
|
8002d0c: f003 0308 and.w r3, r3, #8
|
|
8002d10: 2b00 cmp r3, #0
|
|
8002d12: d00a beq.n 8002d2a <HAL_RCCEx_PeriphCLKConfig+0x1d6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
8002d14: 4b86 ldr r3, [pc, #536] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d16: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002d1a: f023 02c0 bic.w r2, r3, #192 @ 0xc0
|
|
8002d1e: 687b ldr r3, [r7, #4]
|
|
8002d20: 691b ldr r3, [r3, #16]
|
|
8002d22: 4983 ldr r1, [pc, #524] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d24: 4313 orrs r3, r2
|
|
8002d26: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
8002d2a: 687b ldr r3, [r7, #4]
|
|
8002d2c: 681b ldr r3, [r3, #0]
|
|
8002d2e: f003 0320 and.w r3, r3, #32
|
|
8002d32: 2b00 cmp r3, #0
|
|
8002d34: d00a beq.n 8002d4c <HAL_RCCEx_PeriphCLKConfig+0x1f8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUAR1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
8002d36: 4b7e ldr r3, [pc, #504] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d38: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002d3c: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
8002d40: 687b ldr r3, [r7, #4]
|
|
8002d42: 695b ldr r3, [r3, #20]
|
|
8002d44: 497a ldr r1, [pc, #488] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d46: 4313 orrs r3, r2
|
|
8002d48: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8002d4c: 687b ldr r3, [r7, #4]
|
|
8002d4e: 681b ldr r3, [r3, #0]
|
|
8002d50: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002d54: 2b00 cmp r3, #0
|
|
8002d56: d00a beq.n 8002d6e <HAL_RCCEx_PeriphCLKConfig+0x21a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
8002d58: 4b75 ldr r3, [pc, #468] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d5a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002d5e: f423 5240 bic.w r2, r3, #12288 @ 0x3000
|
|
8002d62: 687b ldr r3, [r7, #4]
|
|
8002d64: 699b ldr r3, [r3, #24]
|
|
8002d66: 4972 ldr r1, [pc, #456] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d68: 4313 orrs r3, r2
|
|
8002d6a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
8002d6e: 687b ldr r3, [r7, #4]
|
|
8002d70: 681b ldr r3, [r3, #0]
|
|
8002d72: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002d76: 2b00 cmp r3, #0
|
|
8002d78: d00a beq.n 8002d90 <HAL_RCCEx_PeriphCLKConfig+0x23c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
8002d7a: 4b6d ldr r3, [pc, #436] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d7c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002d80: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
8002d84: 687b ldr r3, [r7, #4]
|
|
8002d86: 69db ldr r3, [r3, #28]
|
|
8002d88: 4969 ldr r1, [pc, #420] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d8a: 4313 orrs r3, r2
|
|
8002d8c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
#if defined(I2C3)
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
8002d90: 687b ldr r3, [r7, #4]
|
|
8002d92: 681b ldr r3, [r3, #0]
|
|
8002d94: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002d98: 2b00 cmp r3, #0
|
|
8002d9a: d00a beq.n 8002db2 <HAL_RCCEx_PeriphCLKConfig+0x25e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
8002d9c: 4b64 ldr r3, [pc, #400] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002d9e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002da2: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8002da6: 687b ldr r3, [r7, #4]
|
|
8002da8: 6a1b ldr r3, [r3, #32]
|
|
8002daa: 4961 ldr r1, [pc, #388] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002dac: 4313 orrs r3, r2
|
|
8002dae: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* I2C4 */
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
|
|
8002db2: 687b ldr r3, [r7, #4]
|
|
8002db4: 681b ldr r3, [r3, #0]
|
|
8002db6: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8002dba: 2b00 cmp r3, #0
|
|
8002dbc: d00a beq.n 8002dd4 <HAL_RCCEx_PeriphCLKConfig+0x280>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
|
|
|
|
/* Configure the LPTIM1 clock source */
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
8002dbe: 4b5c ldr r3, [pc, #368] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002dc0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002dc4: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
8002dc8: 687b ldr r3, [r7, #4]
|
|
8002dca: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002dcc: 4958 ldr r1, [pc, #352] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002dce: 4313 orrs r3, r2
|
|
8002dd0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(SAI1)
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8002dd4: 687b ldr r3, [r7, #4]
|
|
8002dd6: 681b ldr r3, [r3, #0]
|
|
8002dd8: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002ddc: 2b00 cmp r3, #0
|
|
8002dde: d015 beq.n 8002e0c <HAL_RCCEx_PeriphCLKConfig+0x2b8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure the SAI1 interface clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8002de0: 4b53 ldr r3, [pc, #332] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002de2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002de6: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8002dea: 687b ldr r3, [r7, #4]
|
|
8002dec: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002dee: 4950 ldr r1, [pc, #320] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002df0: 4313 orrs r3, r2
|
|
8002df2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
|
|
8002df6: 687b ldr r3, [r7, #4]
|
|
8002df8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8002dfa: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8002dfe: d105 bne.n 8002e0c <HAL_RCCEx_PeriphCLKConfig+0x2b8>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8002e00: 4b4b ldr r3, [pc, #300] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e02: 68db ldr r3, [r3, #12]
|
|
8002e04: 4a4a ldr r2, [pc, #296] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e06: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8002e0a: 60d3 str r3, [r2, #12]
|
|
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SPI_I2S_SUPPORT)
|
|
/*-------------------------- I2S clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
|
|
8002e0c: 687b ldr r3, [r7, #4]
|
|
8002e0e: 681b ldr r3, [r3, #0]
|
|
8002e10: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8002e14: 2b00 cmp r3, #0
|
|
8002e16: d015 beq.n 8002e44 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
|
|
|
|
/* Configure the I2S interface clock source */
|
|
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
|
|
8002e18: 4b45 ldr r3, [pc, #276] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e1a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002e1e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8002e22: 687b ldr r3, [r7, #4]
|
|
8002e24: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002e26: 4942 ldr r1, [pc, #264] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e28: 4313 orrs r3, r2
|
|
8002e2a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
|
|
8002e2e: 687b ldr r3, [r7, #4]
|
|
8002e30: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8002e32: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8002e36: d105 bne.n 8002e44 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8002e38: 4b3d ldr r3, [pc, #244] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e3a: 68db ldr r3, [r3, #12]
|
|
8002e3c: 4a3c ldr r2, [pc, #240] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e3e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8002e42: 60d3 str r3, [r2, #12]
|
|
|
|
#endif /* SPI_I2S_SUPPORT */
|
|
|
|
#if defined(FDCAN1)
|
|
/*-------------------------- FDCAN clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
|
|
8002e44: 687b ldr r3, [r7, #4]
|
|
8002e46: 681b ldr r3, [r3, #0]
|
|
8002e48: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8002e4c: 2b00 cmp r3, #0
|
|
8002e4e: d015 beq.n 8002e7c <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
|
|
|
|
/* Configure the FDCAN interface clock source */
|
|
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
|
|
8002e50: 4b37 ldr r3, [pc, #220] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e52: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002e56: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
|
|
8002e5a: 687b ldr r3, [r7, #4]
|
|
8002e5c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002e5e: 4934 ldr r1, [pc, #208] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e60: 4313 orrs r3, r2
|
|
8002e62: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
|
|
8002e66: 687b ldr r3, [r7, #4]
|
|
8002e68: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8002e6a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8002e6e: d105 bne.n 8002e7c <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8002e70: 4b2f ldr r3, [pc, #188] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e72: 68db ldr r3, [r3, #12]
|
|
8002e74: 4a2e ldr r2, [pc, #184] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e76: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8002e7a: 60d3 str r3, [r2, #12]
|
|
#endif /* FDCAN1 */
|
|
|
|
#if defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
8002e7c: 687b ldr r3, [r7, #4]
|
|
8002e7e: 681b ldr r3, [r3, #0]
|
|
8002e80: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8002e84: 2b00 cmp r3, #0
|
|
8002e86: d015 beq.n 8002eb4 <HAL_RCCEx_PeriphCLKConfig+0x360>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
8002e88: 4b29 ldr r3, [pc, #164] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e8a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002e8e: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8002e92: 687b ldr r3, [r7, #4]
|
|
8002e94: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8002e96: 4926 ldr r1, [pc, #152] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002e98: 4313 orrs r3, r2
|
|
8002e9a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
8002e9e: 687b ldr r3, [r7, #4]
|
|
8002ea0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8002ea2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8002ea6: d105 bne.n 8002eb4 <HAL_RCCEx_PeriphCLKConfig+0x360>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8002ea8: 4b21 ldr r3, [pc, #132] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002eaa: 68db ldr r3, [r3, #12]
|
|
8002eac: 4a20 ldr r2, [pc, #128] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002eae: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8002eb2: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
#endif /* USB */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8002eb4: 687b ldr r3, [r7, #4]
|
|
8002eb6: 681b ldr r3, [r3, #0]
|
|
8002eb8: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8002ebc: 2b00 cmp r3, #0
|
|
8002ebe: d015 beq.n 8002eec <HAL_RCCEx_PeriphCLKConfig+0x398>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
8002ec0: 4b1b ldr r3, [pc, #108] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002ec2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002ec6: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8002eca: 687b ldr r3, [r7, #4]
|
|
8002ecc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8002ece: 4918 ldr r1, [pc, #96] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002ed0: 4313 orrs r3, r2
|
|
8002ed2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8002ed6: 687b ldr r3, [r7, #4]
|
|
8002ed8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8002eda: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
8002ede: d105 bne.n 8002eec <HAL_RCCEx_PeriphCLKConfig+0x398>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8002ee0: 4b13 ldr r3, [pc, #76] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002ee2: 68db ldr r3, [r3, #12]
|
|
8002ee4: 4a12 ldr r2, [pc, #72] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002ee6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8002eea: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC12 clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
|
|
8002eec: 687b ldr r3, [r7, #4]
|
|
8002eee: 681b ldr r3, [r3, #0]
|
|
8002ef0: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8002ef4: 2b00 cmp r3, #0
|
|
8002ef6: d015 beq.n 8002f24 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
|
|
|
|
/* Configure the ADC12 interface clock source */
|
|
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
|
|
8002ef8: 4b0d ldr r3, [pc, #52] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002efa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8002efe: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
8002f02: 687b ldr r3, [r7, #4]
|
|
8002f04: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002f06: 490a ldr r1, [pc, #40] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002f08: 4313 orrs r3, r2
|
|
8002f0a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
|
|
8002f0e: 687b ldr r3, [r7, #4]
|
|
8002f10: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002f12: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8002f16: d105 bne.n 8002f24 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
{
|
|
/* Enable PLLADCCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
|
|
8002f18: 4b05 ldr r3, [pc, #20] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002f1a: 68db ldr r3, [r3, #12]
|
|
8002f1c: 4a04 ldr r2, [pc, #16] @ (8002f30 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8002f1e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8002f22: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
#endif /* QUADSPI */
|
|
|
|
return status;
|
|
8002f24: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8002f26: 4618 mov r0, r3
|
|
8002f28: 3718 adds r7, #24
|
|
8002f2a: 46bd mov sp, r7
|
|
8002f2c: bd80 pop {r7, pc}
|
|
8002f2e: bf00 nop
|
|
8002f30: 40021000 .word 0x40021000
|
|
|
|
08002f34 <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8002f34: b580 push {r7, lr}
|
|
8002f36: b084 sub sp, #16
|
|
8002f38: af00 add r7, sp, #0
|
|
8002f3a: 6078 str r0, [r7, #4]
|
|
uint32_t frxth;
|
|
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
8002f3c: 687b ldr r3, [r7, #4]
|
|
8002f3e: 2b00 cmp r3, #0
|
|
8002f40: d101 bne.n 8002f46 <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f42: 2301 movs r3, #1
|
|
8002f44: e09d b.n 8003082 <HAL_SPI_Init+0x14e>
|
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
|
assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
8002f46: 687b ldr r3, [r7, #4]
|
|
8002f48: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002f4a: 2b00 cmp r3, #0
|
|
8002f4c: d108 bne.n 8002f60 <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
8002f4e: 687b ldr r3, [r7, #4]
|
|
8002f50: 685b ldr r3, [r3, #4]
|
|
8002f52: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8002f56: d009 beq.n 8002f6c <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
8002f58: 687b ldr r3, [r7, #4]
|
|
8002f5a: 2200 movs r2, #0
|
|
8002f5c: 61da str r2, [r3, #28]
|
|
8002f5e: e005 b.n 8002f6c <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8002f60: 687b ldr r3, [r7, #4]
|
|
8002f62: 2200 movs r2, #0
|
|
8002f64: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8002f66: 687b ldr r3, [r7, #4]
|
|
8002f68: 2200 movs r2, #0
|
|
8002f6a: 615a str r2, [r3, #20]
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8002f6c: 687b ldr r3, [r7, #4]
|
|
8002f6e: 2200 movs r2, #0
|
|
8002f70: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
8002f72: 687b ldr r3, [r7, #4]
|
|
8002f74: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
8002f78: b2db uxtb r3, r3
|
|
8002f7a: 2b00 cmp r3, #0
|
|
8002f7c: d106 bne.n 8002f8c <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
8002f7e: 687b ldr r3, [r7, #4]
|
|
8002f80: 2200 movs r2, #0
|
|
8002f82: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
8002f86: 6878 ldr r0, [r7, #4]
|
|
8002f88: f7fe fb02 bl 8001590 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
8002f8c: 687b ldr r3, [r7, #4]
|
|
8002f8e: 2202 movs r2, #2
|
|
8002f90: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8002f94: 687b ldr r3, [r7, #4]
|
|
8002f96: 681b ldr r3, [r3, #0]
|
|
8002f98: 681a ldr r2, [r3, #0]
|
|
8002f9a: 687b ldr r3, [r7, #4]
|
|
8002f9c: 681b ldr r3, [r3, #0]
|
|
8002f9e: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8002fa2: 601a str r2, [r3, #0]
|
|
|
|
/* Align by default the rs fifo threshold on the data size */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
8002fa4: 687b ldr r3, [r7, #4]
|
|
8002fa6: 68db ldr r3, [r3, #12]
|
|
8002fa8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8002fac: d902 bls.n 8002fb4 <HAL_SPI_Init+0x80>
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_HF;
|
|
8002fae: 2300 movs r3, #0
|
|
8002fb0: 60fb str r3, [r7, #12]
|
|
8002fb2: e002 b.n 8002fba <HAL_SPI_Init+0x86>
|
|
}
|
|
else
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_QF;
|
|
8002fb4: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8002fb8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* CRC calculation is valid only for 16Bit and 8 Bit */
|
|
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
|
|
8002fba: 687b ldr r3, [r7, #4]
|
|
8002fbc: 68db ldr r3, [r3, #12]
|
|
8002fbe: f5b3 6f70 cmp.w r3, #3840 @ 0xf00
|
|
8002fc2: d007 beq.n 8002fd4 <HAL_SPI_Init+0xa0>
|
|
8002fc4: 687b ldr r3, [r7, #4]
|
|
8002fc6: 68db ldr r3, [r3, #12]
|
|
8002fc8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
8002fcc: d002 beq.n 8002fd4 <HAL_SPI_Init+0xa0>
|
|
{
|
|
/* CRC must be disabled */
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8002fce: 687b ldr r3, [r7, #4]
|
|
8002fd0: 2200 movs r2, #0
|
|
8002fd2: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
8002fd4: 687b ldr r3, [r7, #4]
|
|
8002fd6: 685b ldr r3, [r3, #4]
|
|
8002fd8: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
8002fdc: 687b ldr r3, [r7, #4]
|
|
8002fde: 689b ldr r3, [r3, #8]
|
|
8002fe0: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
8002fe4: 431a orrs r2, r3
|
|
8002fe6: 687b ldr r3, [r7, #4]
|
|
8002fe8: 691b ldr r3, [r3, #16]
|
|
8002fea: f003 0302 and.w r3, r3, #2
|
|
8002fee: 431a orrs r2, r3
|
|
8002ff0: 687b ldr r3, [r7, #4]
|
|
8002ff2: 695b ldr r3, [r3, #20]
|
|
8002ff4: f003 0301 and.w r3, r3, #1
|
|
8002ff8: 431a orrs r2, r3
|
|
8002ffa: 687b ldr r3, [r7, #4]
|
|
8002ffc: 699b ldr r3, [r3, #24]
|
|
8002ffe: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8003002: 431a orrs r2, r3
|
|
8003004: 687b ldr r3, [r7, #4]
|
|
8003006: 69db ldr r3, [r3, #28]
|
|
8003008: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
800300c: 431a orrs r2, r3
|
|
800300e: 687b ldr r3, [r7, #4]
|
|
8003010: 6a1b ldr r3, [r3, #32]
|
|
8003012: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003016: ea42 0103 orr.w r1, r2, r3
|
|
800301a: 687b ldr r3, [r7, #4]
|
|
800301c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800301e: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
8003022: 687b ldr r3, [r7, #4]
|
|
8003024: 681b ldr r3, [r3, #0]
|
|
8003026: 430a orrs r2, r1
|
|
8003028: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
|
|
800302a: 687b ldr r3, [r7, #4]
|
|
800302c: 699b ldr r3, [r3, #24]
|
|
800302e: 0c1b lsrs r3, r3, #16
|
|
8003030: f003 0204 and.w r2, r3, #4
|
|
8003034: 687b ldr r3, [r7, #4]
|
|
8003036: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003038: f003 0310 and.w r3, r3, #16
|
|
800303c: 431a orrs r2, r3
|
|
800303e: 687b ldr r3, [r7, #4]
|
|
8003040: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003042: f003 0308 and.w r3, r3, #8
|
|
8003046: 431a orrs r2, r3
|
|
8003048: 687b ldr r3, [r7, #4]
|
|
800304a: 68db ldr r3, [r3, #12]
|
|
800304c: f403 6370 and.w r3, r3, #3840 @ 0xf00
|
|
8003050: ea42 0103 orr.w r1, r2, r3
|
|
8003054: 68fb ldr r3, [r7, #12]
|
|
8003056: f403 5280 and.w r2, r3, #4096 @ 0x1000
|
|
800305a: 687b ldr r3, [r7, #4]
|
|
800305c: 681b ldr r3, [r3, #0]
|
|
800305e: 430a orrs r2, r1
|
|
8003060: 605a str r2, [r3, #4]
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
8003062: 687b ldr r3, [r7, #4]
|
|
8003064: 681b ldr r3, [r3, #0]
|
|
8003066: 69da ldr r2, [r3, #28]
|
|
8003068: 687b ldr r3, [r7, #4]
|
|
800306a: 681b ldr r3, [r3, #0]
|
|
800306c: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8003070: 61da str r2, [r3, #28]
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8003072: 687b ldr r3, [r7, #4]
|
|
8003074: 2200 movs r2, #0
|
|
8003076: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8003078: 687b ldr r3, [r7, #4]
|
|
800307a: 2201 movs r2, #1
|
|
800307c: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
return HAL_OK;
|
|
8003080: 2300 movs r3, #0
|
|
}
|
|
8003082: 4618 mov r0, r3
|
|
8003084: 3710 adds r7, #16
|
|
8003086: 46bd mov sp, r7
|
|
8003088: bd80 pop {r7, pc}
|
|
|
|
0800308a <HAL_SPI_Transmit>:
|
|
* @param Size amount of data elements (u8 or u16) to be sent
|
|
* @param Timeout Timeout duration in ms
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800308a: b580 push {r7, lr}
|
|
800308c: b088 sub sp, #32
|
|
800308e: af00 add r7, sp, #0
|
|
8003090: 60f8 str r0, [r7, #12]
|
|
8003092: 60b9 str r1, [r7, #8]
|
|
8003094: 603b str r3, [r7, #0]
|
|
8003096: 4613 mov r3, r2
|
|
8003098: 80fb strh r3, [r7, #6]
|
|
|
|
/* Check Direction parameter */
|
|
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800309a: f7fe fbf5 bl 8001888 <HAL_GetTick>
|
|
800309e: 61f8 str r0, [r7, #28]
|
|
initial_TxXferCount = Size;
|
|
80030a0: 88fb ldrh r3, [r7, #6]
|
|
80030a2: 837b strh r3, [r7, #26]
|
|
|
|
if (hspi->State != HAL_SPI_STATE_READY)
|
|
80030a4: 68fb ldr r3, [r7, #12]
|
|
80030a6: f893 305d ldrb.w r3, [r3, #93] @ 0x5d
|
|
80030aa: b2db uxtb r3, r3
|
|
80030ac: 2b01 cmp r3, #1
|
|
80030ae: d001 beq.n 80030b4 <HAL_SPI_Transmit+0x2a>
|
|
{
|
|
return HAL_BUSY;
|
|
80030b0: 2302 movs r3, #2
|
|
80030b2: e15c b.n 800336e <HAL_SPI_Transmit+0x2e4>
|
|
}
|
|
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80030b4: 68bb ldr r3, [r7, #8]
|
|
80030b6: 2b00 cmp r3, #0
|
|
80030b8: d002 beq.n 80030c0 <HAL_SPI_Transmit+0x36>
|
|
80030ba: 88fb ldrh r3, [r7, #6]
|
|
80030bc: 2b00 cmp r3, #0
|
|
80030be: d101 bne.n 80030c4 <HAL_SPI_Transmit+0x3a>
|
|
{
|
|
return HAL_ERROR;
|
|
80030c0: 2301 movs r3, #1
|
|
80030c2: e154 b.n 800336e <HAL_SPI_Transmit+0x2e4>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hspi);
|
|
80030c4: 68fb ldr r3, [r7, #12]
|
|
80030c6: f893 305c ldrb.w r3, [r3, #92] @ 0x5c
|
|
80030ca: 2b01 cmp r3, #1
|
|
80030cc: d101 bne.n 80030d2 <HAL_SPI_Transmit+0x48>
|
|
80030ce: 2302 movs r3, #2
|
|
80030d0: e14d b.n 800336e <HAL_SPI_Transmit+0x2e4>
|
|
80030d2: 68fb ldr r3, [r7, #12]
|
|
80030d4: 2201 movs r2, #1
|
|
80030d6: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set the transaction information */
|
|
hspi->State = HAL_SPI_STATE_BUSY_TX;
|
|
80030da: 68fb ldr r3, [r7, #12]
|
|
80030dc: 2203 movs r2, #3
|
|
80030de: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
80030e2: 68fb ldr r3, [r7, #12]
|
|
80030e4: 2200 movs r2, #0
|
|
80030e6: 661a str r2, [r3, #96] @ 0x60
|
|
hspi->pTxBuffPtr = (const uint8_t *)pData;
|
|
80030e8: 68fb ldr r3, [r7, #12]
|
|
80030ea: 68ba ldr r2, [r7, #8]
|
|
80030ec: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferSize = Size;
|
|
80030ee: 68fb ldr r3, [r7, #12]
|
|
80030f0: 88fa ldrh r2, [r7, #6]
|
|
80030f2: 879a strh r2, [r3, #60] @ 0x3c
|
|
hspi->TxXferCount = Size;
|
|
80030f4: 68fb ldr r3, [r7, #12]
|
|
80030f6: 88fa ldrh r2, [r7, #6]
|
|
80030f8: 87da strh r2, [r3, #62] @ 0x3e
|
|
|
|
/*Init field not used in handle to zero */
|
|
hspi->pRxBuffPtr = (uint8_t *)NULL;
|
|
80030fa: 68fb ldr r3, [r7, #12]
|
|
80030fc: 2200 movs r2, #0
|
|
80030fe: 641a str r2, [r3, #64] @ 0x40
|
|
hspi->RxXferSize = 0U;
|
|
8003100: 68fb ldr r3, [r7, #12]
|
|
8003102: 2200 movs r2, #0
|
|
8003104: f8a3 2044 strh.w r2, [r3, #68] @ 0x44
|
|
hspi->RxXferCount = 0U;
|
|
8003108: 68fb ldr r3, [r7, #12]
|
|
800310a: 2200 movs r2, #0
|
|
800310c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46
|
|
hspi->TxISR = NULL;
|
|
8003110: 68fb ldr r3, [r7, #12]
|
|
8003112: 2200 movs r2, #0
|
|
8003114: 651a str r2, [r3, #80] @ 0x50
|
|
hspi->RxISR = NULL;
|
|
8003116: 68fb ldr r3, [r7, #12]
|
|
8003118: 2200 movs r2, #0
|
|
800311a: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Configure communication direction : 1Line */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
800311c: 68fb ldr r3, [r7, #12]
|
|
800311e: 689b ldr r3, [r3, #8]
|
|
8003120: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8003124: d10f bne.n 8003146 <HAL_SPI_Transmit+0xbc>
|
|
{
|
|
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8003126: 68fb ldr r3, [r7, #12]
|
|
8003128: 681b ldr r3, [r3, #0]
|
|
800312a: 681a ldr r2, [r3, #0]
|
|
800312c: 68fb ldr r3, [r7, #12]
|
|
800312e: 681b ldr r3, [r3, #0]
|
|
8003130: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8003134: 601a str r2, [r3, #0]
|
|
SPI_1LINE_TX(hspi);
|
|
8003136: 68fb ldr r3, [r7, #12]
|
|
8003138: 681b ldr r3, [r3, #0]
|
|
800313a: 681a ldr r2, [r3, #0]
|
|
800313c: 68fb ldr r3, [r7, #12]
|
|
800313e: 681b ldr r3, [r3, #0]
|
|
8003140: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8003144: 601a str r2, [r3, #0]
|
|
SPI_RESET_CRC(hspi);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check if the SPI is already enabled */
|
|
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
|
|
8003146: 68fb ldr r3, [r7, #12]
|
|
8003148: 681b ldr r3, [r3, #0]
|
|
800314a: 681b ldr r3, [r3, #0]
|
|
800314c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003150: 2b40 cmp r3, #64 @ 0x40
|
|
8003152: d007 beq.n 8003164 <HAL_SPI_Transmit+0xda>
|
|
{
|
|
/* Enable SPI peripheral */
|
|
__HAL_SPI_ENABLE(hspi);
|
|
8003154: 68fb ldr r3, [r7, #12]
|
|
8003156: 681b ldr r3, [r3, #0]
|
|
8003158: 681a ldr r2, [r3, #0]
|
|
800315a: 68fb ldr r3, [r7, #12]
|
|
800315c: 681b ldr r3, [r3, #0]
|
|
800315e: f042 0240 orr.w r2, r2, #64 @ 0x40
|
|
8003162: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Transmit data in 16 Bit mode */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
8003164: 68fb ldr r3, [r7, #12]
|
|
8003166: 68db ldr r3, [r3, #12]
|
|
8003168: f5b3 6fe0 cmp.w r3, #1792 @ 0x700
|
|
800316c: d952 bls.n 8003214 <HAL_SPI_Transmit+0x18a>
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
800316e: 68fb ldr r3, [r7, #12]
|
|
8003170: 685b ldr r3, [r3, #4]
|
|
8003172: 2b00 cmp r3, #0
|
|
8003174: d002 beq.n 800317c <HAL_SPI_Transmit+0xf2>
|
|
8003176: 8b7b ldrh r3, [r7, #26]
|
|
8003178: 2b01 cmp r3, #1
|
|
800317a: d145 bne.n 8003208 <HAL_SPI_Transmit+0x17e>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800317c: 68fb ldr r3, [r7, #12]
|
|
800317e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003180: 881a ldrh r2, [r3, #0]
|
|
8003182: 68fb ldr r3, [r7, #12]
|
|
8003184: 681b ldr r3, [r3, #0]
|
|
8003186: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8003188: 68fb ldr r3, [r7, #12]
|
|
800318a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800318c: 1c9a adds r2, r3, #2
|
|
800318e: 68fb ldr r3, [r7, #12]
|
|
8003190: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
8003192: 68fb ldr r3, [r7, #12]
|
|
8003194: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8003196: b29b uxth r3, r3
|
|
8003198: 3b01 subs r3, #1
|
|
800319a: b29a uxth r2, r3
|
|
800319c: 68fb ldr r3, [r7, #12]
|
|
800319e: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
/* Transmit data in 16 Bit mode */
|
|
while (hspi->TxXferCount > 0U)
|
|
80031a0: e032 b.n 8003208 <HAL_SPI_Transmit+0x17e>
|
|
{
|
|
/* Wait until TXE flag is set to send data */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
|
|
80031a2: 68fb ldr r3, [r7, #12]
|
|
80031a4: 681b ldr r3, [r3, #0]
|
|
80031a6: 689b ldr r3, [r3, #8]
|
|
80031a8: f003 0302 and.w r3, r3, #2
|
|
80031ac: 2b02 cmp r3, #2
|
|
80031ae: d112 bne.n 80031d6 <HAL_SPI_Transmit+0x14c>
|
|
{
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
80031b0: 68fb ldr r3, [r7, #12]
|
|
80031b2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80031b4: 881a ldrh r2, [r3, #0]
|
|
80031b6: 68fb ldr r3, [r7, #12]
|
|
80031b8: 681b ldr r3, [r3, #0]
|
|
80031ba: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
80031bc: 68fb ldr r3, [r7, #12]
|
|
80031be: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80031c0: 1c9a adds r2, r3, #2
|
|
80031c2: 68fb ldr r3, [r7, #12]
|
|
80031c4: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
80031c6: 68fb ldr r3, [r7, #12]
|
|
80031c8: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80031ca: b29b uxth r3, r3
|
|
80031cc: 3b01 subs r3, #1
|
|
80031ce: b29a uxth r2, r3
|
|
80031d0: 68fb ldr r3, [r7, #12]
|
|
80031d2: 87da strh r2, [r3, #62] @ 0x3e
|
|
80031d4: e018 b.n 8003208 <HAL_SPI_Transmit+0x17e>
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
80031d6: f7fe fb57 bl 8001888 <HAL_GetTick>
|
|
80031da: 4602 mov r2, r0
|
|
80031dc: 69fb ldr r3, [r7, #28]
|
|
80031de: 1ad3 subs r3, r2, r3
|
|
80031e0: 683a ldr r2, [r7, #0]
|
|
80031e2: 429a cmp r2, r3
|
|
80031e4: d803 bhi.n 80031ee <HAL_SPI_Transmit+0x164>
|
|
80031e6: 683b ldr r3, [r7, #0]
|
|
80031e8: f1b3 3fff cmp.w r3, #4294967295
|
|
80031ec: d102 bne.n 80031f4 <HAL_SPI_Transmit+0x16a>
|
|
80031ee: 683b ldr r3, [r7, #0]
|
|
80031f0: 2b00 cmp r3, #0
|
|
80031f2: d109 bne.n 8003208 <HAL_SPI_Transmit+0x17e>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80031f4: 68fb ldr r3, [r7, #12]
|
|
80031f6: 2201 movs r2, #1
|
|
80031f8: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
80031fc: 68fb ldr r3, [r7, #12]
|
|
80031fe: 2200 movs r2, #0
|
|
8003200: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
8003204: 2303 movs r3, #3
|
|
8003206: e0b2 b.n 800336e <HAL_SPI_Transmit+0x2e4>
|
|
while (hspi->TxXferCount > 0U)
|
|
8003208: 68fb ldr r3, [r7, #12]
|
|
800320a: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800320c: b29b uxth r3, r3
|
|
800320e: 2b00 cmp r3, #0
|
|
8003210: d1c7 bne.n 80031a2 <HAL_SPI_Transmit+0x118>
|
|
8003212: e083 b.n 800331c <HAL_SPI_Transmit+0x292>
|
|
}
|
|
}
|
|
/* Transmit data in 8 Bit mode */
|
|
else
|
|
{
|
|
if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
|
|
8003214: 68fb ldr r3, [r7, #12]
|
|
8003216: 685b ldr r3, [r3, #4]
|
|
8003218: 2b00 cmp r3, #0
|
|
800321a: d002 beq.n 8003222 <HAL_SPI_Transmit+0x198>
|
|
800321c: 8b7b ldrh r3, [r7, #26]
|
|
800321e: 2b01 cmp r3, #1
|
|
8003220: d177 bne.n 8003312 <HAL_SPI_Transmit+0x288>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
8003222: 68fb ldr r3, [r7, #12]
|
|
8003224: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8003226: b29b uxth r3, r3
|
|
8003228: 2b01 cmp r3, #1
|
|
800322a: d912 bls.n 8003252 <HAL_SPI_Transmit+0x1c8>
|
|
{
|
|
/* write on the data register in packing mode */
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
800322c: 68fb ldr r3, [r7, #12]
|
|
800322e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003230: 881a ldrh r2, [r3, #0]
|
|
8003232: 68fb ldr r3, [r7, #12]
|
|
8003234: 681b ldr r3, [r3, #0]
|
|
8003236: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
8003238: 68fb ldr r3, [r7, #12]
|
|
800323a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800323c: 1c9a adds r2, r3, #2
|
|
800323e: 68fb ldr r3, [r7, #12]
|
|
8003240: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
8003242: 68fb ldr r3, [r7, #12]
|
|
8003244: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8003246: b29b uxth r3, r3
|
|
8003248: 3b02 subs r3, #2
|
|
800324a: b29a uxth r2, r3
|
|
800324c: 68fb ldr r3, [r7, #12]
|
|
800324e: 87da strh r2, [r3, #62] @ 0x3e
|
|
8003250: e05f b.n 8003312 <HAL_SPI_Transmit+0x288>
|
|
}
|
|
else
|
|
{
|
|
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
8003252: 68fb ldr r3, [r7, #12]
|
|
8003254: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8003256: 68fb ldr r3, [r7, #12]
|
|
8003258: 681b ldr r3, [r3, #0]
|
|
800325a: 330c adds r3, #12
|
|
800325c: 7812 ldrb r2, [r2, #0]
|
|
800325e: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr ++;
|
|
8003260: 68fb ldr r3, [r7, #12]
|
|
8003262: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003264: 1c5a adds r2, r3, #1
|
|
8003266: 68fb ldr r3, [r7, #12]
|
|
8003268: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
800326a: 68fb ldr r3, [r7, #12]
|
|
800326c: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800326e: b29b uxth r3, r3
|
|
8003270: 3b01 subs r3, #1
|
|
8003272: b29a uxth r2, r3
|
|
8003274: 68fb ldr r3, [r7, #12]
|
|
8003276: 87da strh r2, [r3, #62] @ 0x3e
|
|
}
|
|
}
|
|
while (hspi->TxXferCount > 0U)
|
|
8003278: e04b b.n 8003312 <HAL_SPI_Transmit+0x288>
|
|
{
|
|
/* Wait until TXE flag is set to send data */
|
|
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
|
|
800327a: 68fb ldr r3, [r7, #12]
|
|
800327c: 681b ldr r3, [r3, #0]
|
|
800327e: 689b ldr r3, [r3, #8]
|
|
8003280: f003 0302 and.w r3, r3, #2
|
|
8003284: 2b02 cmp r3, #2
|
|
8003286: d12b bne.n 80032e0 <HAL_SPI_Transmit+0x256>
|
|
{
|
|
if (hspi->TxXferCount > 1U)
|
|
8003288: 68fb ldr r3, [r7, #12]
|
|
800328a: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
800328c: b29b uxth r3, r3
|
|
800328e: 2b01 cmp r3, #1
|
|
8003290: d912 bls.n 80032b8 <HAL_SPI_Transmit+0x22e>
|
|
{
|
|
/* write on the data register in packing mode */
|
|
hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr);
|
|
8003292: 68fb ldr r3, [r7, #12]
|
|
8003294: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003296: 881a ldrh r2, [r3, #0]
|
|
8003298: 68fb ldr r3, [r7, #12]
|
|
800329a: 681b ldr r3, [r3, #0]
|
|
800329c: 60da str r2, [r3, #12]
|
|
hspi->pTxBuffPtr += sizeof(uint16_t);
|
|
800329e: 68fb ldr r3, [r7, #12]
|
|
80032a0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80032a2: 1c9a adds r2, r3, #2
|
|
80032a4: 68fb ldr r3, [r7, #12]
|
|
80032a6: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount -= 2U;
|
|
80032a8: 68fb ldr r3, [r7, #12]
|
|
80032aa: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80032ac: b29b uxth r3, r3
|
|
80032ae: 3b02 subs r3, #2
|
|
80032b0: b29a uxth r2, r3
|
|
80032b2: 68fb ldr r3, [r7, #12]
|
|
80032b4: 87da strh r2, [r3, #62] @ 0x3e
|
|
80032b6: e02c b.n 8003312 <HAL_SPI_Transmit+0x288>
|
|
}
|
|
else
|
|
{
|
|
*((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr);
|
|
80032b8: 68fb ldr r3, [r7, #12]
|
|
80032ba: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
80032bc: 68fb ldr r3, [r7, #12]
|
|
80032be: 681b ldr r3, [r3, #0]
|
|
80032c0: 330c adds r3, #12
|
|
80032c2: 7812 ldrb r2, [r2, #0]
|
|
80032c4: 701a strb r2, [r3, #0]
|
|
hspi->pTxBuffPtr++;
|
|
80032c6: 68fb ldr r3, [r7, #12]
|
|
80032c8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80032ca: 1c5a adds r2, r3, #1
|
|
80032cc: 68fb ldr r3, [r7, #12]
|
|
80032ce: 639a str r2, [r3, #56] @ 0x38
|
|
hspi->TxXferCount--;
|
|
80032d0: 68fb ldr r3, [r7, #12]
|
|
80032d2: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
80032d4: b29b uxth r3, r3
|
|
80032d6: 3b01 subs r3, #1
|
|
80032d8: b29a uxth r2, r3
|
|
80032da: 68fb ldr r3, [r7, #12]
|
|
80032dc: 87da strh r2, [r3, #62] @ 0x3e
|
|
80032de: e018 b.n 8003312 <HAL_SPI_Transmit+0x288>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Timeout management */
|
|
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
|
|
80032e0: f7fe fad2 bl 8001888 <HAL_GetTick>
|
|
80032e4: 4602 mov r2, r0
|
|
80032e6: 69fb ldr r3, [r7, #28]
|
|
80032e8: 1ad3 subs r3, r2, r3
|
|
80032ea: 683a ldr r2, [r7, #0]
|
|
80032ec: 429a cmp r2, r3
|
|
80032ee: d803 bhi.n 80032f8 <HAL_SPI_Transmit+0x26e>
|
|
80032f0: 683b ldr r3, [r7, #0]
|
|
80032f2: f1b3 3fff cmp.w r3, #4294967295
|
|
80032f6: d102 bne.n 80032fe <HAL_SPI_Transmit+0x274>
|
|
80032f8: 683b ldr r3, [r7, #0]
|
|
80032fa: 2b00 cmp r3, #0
|
|
80032fc: d109 bne.n 8003312 <HAL_SPI_Transmit+0x288>
|
|
{
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
80032fe: 68fb ldr r3, [r7, #12]
|
|
8003300: 2201 movs r2, #1
|
|
8003302: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
__HAL_UNLOCK(hspi);
|
|
8003306: 68fb ldr r3, [r7, #12]
|
|
8003308: 2200 movs r2, #0
|
|
800330a: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
return HAL_TIMEOUT;
|
|
800330e: 2303 movs r3, #3
|
|
8003310: e02d b.n 800336e <HAL_SPI_Transmit+0x2e4>
|
|
while (hspi->TxXferCount > 0U)
|
|
8003312: 68fb ldr r3, [r7, #12]
|
|
8003314: 8fdb ldrh r3, [r3, #62] @ 0x3e
|
|
8003316: b29b uxth r3, r3
|
|
8003318: 2b00 cmp r3, #0
|
|
800331a: d1ae bne.n 800327a <HAL_SPI_Transmit+0x1f0>
|
|
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Check the end of the transaction */
|
|
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
|
|
800331c: 69fa ldr r2, [r7, #28]
|
|
800331e: 6839 ldr r1, [r7, #0]
|
|
8003320: 68f8 ldr r0, [r7, #12]
|
|
8003322: f000 f947 bl 80035b4 <SPI_EndRxTxTransaction>
|
|
8003326: 4603 mov r3, r0
|
|
8003328: 2b00 cmp r3, #0
|
|
800332a: d002 beq.n 8003332 <HAL_SPI_Transmit+0x2a8>
|
|
{
|
|
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
|
|
800332c: 68fb ldr r3, [r7, #12]
|
|
800332e: 2220 movs r2, #32
|
|
8003330: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Clear overrun flag in 2 Lines communication mode because received is not read */
|
|
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
|
|
8003332: 68fb ldr r3, [r7, #12]
|
|
8003334: 689b ldr r3, [r3, #8]
|
|
8003336: 2b00 cmp r3, #0
|
|
8003338: d10a bne.n 8003350 <HAL_SPI_Transmit+0x2c6>
|
|
{
|
|
__HAL_SPI_CLEAR_OVRFLAG(hspi);
|
|
800333a: 2300 movs r3, #0
|
|
800333c: 617b str r3, [r7, #20]
|
|
800333e: 68fb ldr r3, [r7, #12]
|
|
8003340: 681b ldr r3, [r3, #0]
|
|
8003342: 68db ldr r3, [r3, #12]
|
|
8003344: 617b str r3, [r7, #20]
|
|
8003346: 68fb ldr r3, [r7, #12]
|
|
8003348: 681b ldr r3, [r3, #0]
|
|
800334a: 689b ldr r3, [r3, #8]
|
|
800334c: 617b str r3, [r7, #20]
|
|
800334e: 697b ldr r3, [r7, #20]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8003350: 68fb ldr r3, [r7, #12]
|
|
8003352: 2201 movs r2, #1
|
|
8003354: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8003358: 68fb ldr r3, [r7, #12]
|
|
800335a: 2200 movs r2, #0
|
|
800335c: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
|
|
8003360: 68fb ldr r3, [r7, #12]
|
|
8003362: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003364: 2b00 cmp r3, #0
|
|
8003366: d001 beq.n 800336c <HAL_SPI_Transmit+0x2e2>
|
|
{
|
|
return HAL_ERROR;
|
|
8003368: 2301 movs r3, #1
|
|
800336a: e000 b.n 800336e <HAL_SPI_Transmit+0x2e4>
|
|
}
|
|
else
|
|
{
|
|
return HAL_OK;
|
|
800336c: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800336e: 4618 mov r0, r3
|
|
8003370: 3720 adds r7, #32
|
|
8003372: 46bd mov sp, r7
|
|
8003374: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08003378 <SPI_WaitFlagStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8003378: b580 push {r7, lr}
|
|
800337a: b088 sub sp, #32
|
|
800337c: af00 add r7, sp, #0
|
|
800337e: 60f8 str r0, [r7, #12]
|
|
8003380: 60b9 str r1, [r7, #8]
|
|
8003382: 603b str r3, [r7, #0]
|
|
8003384: 4613 mov r3, r2
|
|
8003386: 71fb strb r3, [r7, #7]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
8003388: f7fe fa7e bl 8001888 <HAL_GetTick>
|
|
800338c: 4602 mov r2, r0
|
|
800338e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003390: 1a9b subs r3, r3, r2
|
|
8003392: 683a ldr r2, [r7, #0]
|
|
8003394: 4413 add r3, r2
|
|
8003396: 61fb str r3, [r7, #28]
|
|
tmp_tickstart = HAL_GetTick();
|
|
8003398: f7fe fa76 bl 8001888 <HAL_GetTick>
|
|
800339c: 61b8 str r0, [r7, #24]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
|
|
800339e: 4b39 ldr r3, [pc, #228] @ (8003484 <SPI_WaitFlagStateUntilTimeout+0x10c>)
|
|
80033a0: 681b ldr r3, [r3, #0]
|
|
80033a2: 015b lsls r3, r3, #5
|
|
80033a4: 0d1b lsrs r3, r3, #20
|
|
80033a6: 69fa ldr r2, [r7, #28]
|
|
80033a8: fb02 f303 mul.w r3, r2, r3
|
|
80033ac: 617b str r3, [r7, #20]
|
|
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
80033ae: e055 b.n 800345c <SPI_WaitFlagStateUntilTimeout+0xe4>
|
|
{
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80033b0: 683b ldr r3, [r7, #0]
|
|
80033b2: f1b3 3fff cmp.w r3, #4294967295
|
|
80033b6: d051 beq.n 800345c <SPI_WaitFlagStateUntilTimeout+0xe4>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
80033b8: f7fe fa66 bl 8001888 <HAL_GetTick>
|
|
80033bc: 4602 mov r2, r0
|
|
80033be: 69bb ldr r3, [r7, #24]
|
|
80033c0: 1ad3 subs r3, r2, r3
|
|
80033c2: 69fa ldr r2, [r7, #28]
|
|
80033c4: 429a cmp r2, r3
|
|
80033c6: d902 bls.n 80033ce <SPI_WaitFlagStateUntilTimeout+0x56>
|
|
80033c8: 69fb ldr r3, [r7, #28]
|
|
80033ca: 2b00 cmp r3, #0
|
|
80033cc: d13d bne.n 800344a <SPI_WaitFlagStateUntilTimeout+0xd2>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
80033ce: 68fb ldr r3, [r7, #12]
|
|
80033d0: 681b ldr r3, [r3, #0]
|
|
80033d2: 685a ldr r2, [r3, #4]
|
|
80033d4: 68fb ldr r3, [r7, #12]
|
|
80033d6: 681b ldr r3, [r3, #0]
|
|
80033d8: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
80033dc: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
80033de: 68fb ldr r3, [r7, #12]
|
|
80033e0: 685b ldr r3, [r3, #4]
|
|
80033e2: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
80033e6: d111 bne.n 800340c <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
80033e8: 68fb ldr r3, [r7, #12]
|
|
80033ea: 689b ldr r3, [r3, #8]
|
|
80033ec: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80033f0: d004 beq.n 80033fc <SPI_WaitFlagStateUntilTimeout+0x84>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
80033f2: 68fb ldr r3, [r7, #12]
|
|
80033f4: 689b ldr r3, [r3, #8]
|
|
80033f6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80033fa: d107 bne.n 800340c <SPI_WaitFlagStateUntilTimeout+0x94>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
80033fc: 68fb ldr r3, [r7, #12]
|
|
80033fe: 681b ldr r3, [r3, #0]
|
|
8003400: 681a ldr r2, [r3, #0]
|
|
8003402: 68fb ldr r3, [r7, #12]
|
|
8003404: 681b ldr r3, [r3, #0]
|
|
8003406: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
800340a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
800340c: 68fb ldr r3, [r7, #12]
|
|
800340e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003410: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8003414: d10f bne.n 8003436 <SPI_WaitFlagStateUntilTimeout+0xbe>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
8003416: 68fb ldr r3, [r7, #12]
|
|
8003418: 681b ldr r3, [r3, #0]
|
|
800341a: 681a ldr r2, [r3, #0]
|
|
800341c: 68fb ldr r3, [r7, #12]
|
|
800341e: 681b ldr r3, [r3, #0]
|
|
8003420: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8003424: 601a str r2, [r3, #0]
|
|
8003426: 68fb ldr r3, [r7, #12]
|
|
8003428: 681b ldr r3, [r3, #0]
|
|
800342a: 681a ldr r2, [r3, #0]
|
|
800342c: 68fb ldr r3, [r7, #12]
|
|
800342e: 681b ldr r3, [r3, #0]
|
|
8003430: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8003434: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8003436: 68fb ldr r3, [r7, #12]
|
|
8003438: 2201 movs r2, #1
|
|
800343a: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
800343e: 68fb ldr r3, [r7, #12]
|
|
8003440: 2200 movs r2, #0
|
|
8003442: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_TIMEOUT;
|
|
8003446: 2303 movs r3, #3
|
|
8003448: e018 b.n 800347c <SPI_WaitFlagStateUntilTimeout+0x104>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
800344a: 697b ldr r3, [r7, #20]
|
|
800344c: 2b00 cmp r3, #0
|
|
800344e: d102 bne.n 8003456 <SPI_WaitFlagStateUntilTimeout+0xde>
|
|
{
|
|
tmp_timeout = 0U;
|
|
8003450: 2300 movs r3, #0
|
|
8003452: 61fb str r3, [r7, #28]
|
|
8003454: e002 b.n 800345c <SPI_WaitFlagStateUntilTimeout+0xe4>
|
|
}
|
|
else
|
|
{
|
|
count--;
|
|
8003456: 697b ldr r3, [r7, #20]
|
|
8003458: 3b01 subs r3, #1
|
|
800345a: 617b str r3, [r7, #20]
|
|
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
|
|
800345c: 68fb ldr r3, [r7, #12]
|
|
800345e: 681b ldr r3, [r3, #0]
|
|
8003460: 689a ldr r2, [r3, #8]
|
|
8003462: 68bb ldr r3, [r7, #8]
|
|
8003464: 4013 ands r3, r2
|
|
8003466: 68ba ldr r2, [r7, #8]
|
|
8003468: 429a cmp r2, r3
|
|
800346a: bf0c ite eq
|
|
800346c: 2301 moveq r3, #1
|
|
800346e: 2300 movne r3, #0
|
|
8003470: b2db uxtb r3, r3
|
|
8003472: 461a mov r2, r3
|
|
8003474: 79fb ldrb r3, [r7, #7]
|
|
8003476: 429a cmp r2, r3
|
|
8003478: d19a bne.n 80033b0 <SPI_WaitFlagStateUntilTimeout+0x38>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800347a: 2300 movs r3, #0
|
|
}
|
|
800347c: 4618 mov r0, r3
|
|
800347e: 3720 adds r7, #32
|
|
8003480: 46bd mov sp, r7
|
|
8003482: bd80 pop {r7, pc}
|
|
8003484: 2000000c .word 0x2000000c
|
|
|
|
08003488 <SPI_WaitFifoStateUntilTimeout>:
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8003488: b580 push {r7, lr}
|
|
800348a: b08a sub sp, #40 @ 0x28
|
|
800348c: af00 add r7, sp, #0
|
|
800348e: 60f8 str r0, [r7, #12]
|
|
8003490: 60b9 str r1, [r7, #8]
|
|
8003492: 607a str r2, [r7, #4]
|
|
8003494: 603b str r3, [r7, #0]
|
|
__IO uint32_t count;
|
|
uint32_t tmp_timeout;
|
|
uint32_t tmp_tickstart;
|
|
__IO const uint8_t *ptmpreg8;
|
|
__IO uint8_t tmpreg8 = 0;
|
|
8003496: 2300 movs r3, #0
|
|
8003498: 75fb strb r3, [r7, #23]
|
|
|
|
/* Adjust Timeout value in case of end of transfer */
|
|
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
|
|
800349a: f7fe f9f5 bl 8001888 <HAL_GetTick>
|
|
800349e: 4602 mov r2, r0
|
|
80034a0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80034a2: 1a9b subs r3, r3, r2
|
|
80034a4: 683a ldr r2, [r7, #0]
|
|
80034a6: 4413 add r3, r2
|
|
80034a8: 627b str r3, [r7, #36] @ 0x24
|
|
tmp_tickstart = HAL_GetTick();
|
|
80034aa: f7fe f9ed bl 8001888 <HAL_GetTick>
|
|
80034ae: 6238 str r0, [r7, #32]
|
|
|
|
/* Initialize the 8bit temporary pointer */
|
|
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
|
|
80034b0: 68fb ldr r3, [r7, #12]
|
|
80034b2: 681b ldr r3, [r3, #0]
|
|
80034b4: 330c adds r3, #12
|
|
80034b6: 61fb str r3, [r7, #28]
|
|
|
|
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
|
|
count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
|
|
80034b8: 4b3d ldr r3, [pc, #244] @ (80035b0 <SPI_WaitFifoStateUntilTimeout+0x128>)
|
|
80034ba: 681a ldr r2, [r3, #0]
|
|
80034bc: 4613 mov r3, r2
|
|
80034be: 009b lsls r3, r3, #2
|
|
80034c0: 4413 add r3, r2
|
|
80034c2: 00da lsls r2, r3, #3
|
|
80034c4: 1ad3 subs r3, r2, r3
|
|
80034c6: 0d1b lsrs r3, r3, #20
|
|
80034c8: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80034ca: fb02 f303 mul.w r3, r2, r3
|
|
80034ce: 61bb str r3, [r7, #24]
|
|
|
|
while ((hspi->Instance->SR & Fifo) != State)
|
|
80034d0: e061 b.n 8003596 <SPI_WaitFifoStateUntilTimeout+0x10e>
|
|
{
|
|
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
|
|
80034d2: 68bb ldr r3, [r7, #8]
|
|
80034d4: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
|
|
80034d8: d107 bne.n 80034ea <SPI_WaitFifoStateUntilTimeout+0x62>
|
|
80034da: 687b ldr r3, [r7, #4]
|
|
80034dc: 2b00 cmp r3, #0
|
|
80034de: d104 bne.n 80034ea <SPI_WaitFifoStateUntilTimeout+0x62>
|
|
{
|
|
/* Flush Data Register by a blank read */
|
|
tmpreg8 = *ptmpreg8;
|
|
80034e0: 69fb ldr r3, [r7, #28]
|
|
80034e2: 781b ldrb r3, [r3, #0]
|
|
80034e4: b2db uxtb r3, r3
|
|
80034e6: 75fb strb r3, [r7, #23]
|
|
/* To avoid GCC warning */
|
|
UNUSED(tmpreg8);
|
|
80034e8: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80034ea: 683b ldr r3, [r7, #0]
|
|
80034ec: f1b3 3fff cmp.w r3, #4294967295
|
|
80034f0: d051 beq.n 8003596 <SPI_WaitFifoStateUntilTimeout+0x10e>
|
|
{
|
|
if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
|
|
80034f2: f7fe f9c9 bl 8001888 <HAL_GetTick>
|
|
80034f6: 4602 mov r2, r0
|
|
80034f8: 6a3b ldr r3, [r7, #32]
|
|
80034fa: 1ad3 subs r3, r2, r3
|
|
80034fc: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80034fe: 429a cmp r2, r3
|
|
8003500: d902 bls.n 8003508 <SPI_WaitFifoStateUntilTimeout+0x80>
|
|
8003502: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003504: 2b00 cmp r3, #0
|
|
8003506: d13d bne.n 8003584 <SPI_WaitFifoStateUntilTimeout+0xfc>
|
|
/* Disable the SPI and reset the CRC: the CRC value should be cleared
|
|
on both master and slave sides in order to resynchronize the master
|
|
and slave for their respective CRC calculation */
|
|
|
|
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
|
|
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
|
|
8003508: 68fb ldr r3, [r7, #12]
|
|
800350a: 681b ldr r3, [r3, #0]
|
|
800350c: 685a ldr r2, [r3, #4]
|
|
800350e: 68fb ldr r3, [r7, #12]
|
|
8003510: 681b ldr r3, [r3, #0]
|
|
8003512: f022 02e0 bic.w r2, r2, #224 @ 0xe0
|
|
8003516: 605a str r2, [r3, #4]
|
|
|
|
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
|
|
8003518: 68fb ldr r3, [r7, #12]
|
|
800351a: 685b ldr r3, [r3, #4]
|
|
800351c: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8003520: d111 bne.n 8003546 <SPI_WaitFifoStateUntilTimeout+0xbe>
|
|
8003522: 68fb ldr r3, [r7, #12]
|
|
8003524: 689b ldr r3, [r3, #8]
|
|
8003526: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800352a: d004 beq.n 8003536 <SPI_WaitFifoStateUntilTimeout+0xae>
|
|
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
|
|
800352c: 68fb ldr r3, [r7, #12]
|
|
800352e: 689b ldr r3, [r3, #8]
|
|
8003530: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8003534: d107 bne.n 8003546 <SPI_WaitFifoStateUntilTimeout+0xbe>
|
|
{
|
|
/* Disable SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8003536: 68fb ldr r3, [r7, #12]
|
|
8003538: 681b ldr r3, [r3, #0]
|
|
800353a: 681a ldr r2, [r3, #0]
|
|
800353c: 68fb ldr r3, [r7, #12]
|
|
800353e: 681b ldr r3, [r3, #0]
|
|
8003540: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8003544: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset CRC Calculation */
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
8003546: 68fb ldr r3, [r7, #12]
|
|
8003548: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800354a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800354e: d10f bne.n 8003570 <SPI_WaitFifoStateUntilTimeout+0xe8>
|
|
{
|
|
SPI_RESET_CRC(hspi);
|
|
8003550: 68fb ldr r3, [r7, #12]
|
|
8003552: 681b ldr r3, [r3, #0]
|
|
8003554: 681a ldr r2, [r3, #0]
|
|
8003556: 68fb ldr r3, [r7, #12]
|
|
8003558: 681b ldr r3, [r3, #0]
|
|
800355a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800355e: 601a str r2, [r3, #0]
|
|
8003560: 68fb ldr r3, [r7, #12]
|
|
8003562: 681b ldr r3, [r3, #0]
|
|
8003564: 681a ldr r2, [r3, #0]
|
|
8003566: 68fb ldr r3, [r7, #12]
|
|
8003568: 681b ldr r3, [r3, #0]
|
|
800356a: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
800356e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8003570: 68fb ldr r3, [r7, #12]
|
|
8003572: 2201 movs r2, #1
|
|
8003574: f883 205d strb.w r2, [r3, #93] @ 0x5d
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hspi);
|
|
8003578: 68fb ldr r3, [r7, #12]
|
|
800357a: 2200 movs r2, #0
|
|
800357c: f883 205c strb.w r2, [r3, #92] @ 0x5c
|
|
|
|
return HAL_TIMEOUT;
|
|
8003580: 2303 movs r3, #3
|
|
8003582: e011 b.n 80035a8 <SPI_WaitFifoStateUntilTimeout+0x120>
|
|
}
|
|
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
|
|
if (count == 0U)
|
|
8003584: 69bb ldr r3, [r7, #24]
|
|
8003586: 2b00 cmp r3, #0
|
|
8003588: d102 bne.n 8003590 <SPI_WaitFifoStateUntilTimeout+0x108>
|
|
{
|
|
tmp_timeout = 0U;
|
|
800358a: 2300 movs r3, #0
|
|
800358c: 627b str r3, [r7, #36] @ 0x24
|
|
800358e: e002 b.n 8003596 <SPI_WaitFifoStateUntilTimeout+0x10e>
|
|
}
|
|
else
|
|
{
|
|
count--;
|
|
8003590: 69bb ldr r3, [r7, #24]
|
|
8003592: 3b01 subs r3, #1
|
|
8003594: 61bb str r3, [r7, #24]
|
|
while ((hspi->Instance->SR & Fifo) != State)
|
|
8003596: 68fb ldr r3, [r7, #12]
|
|
8003598: 681b ldr r3, [r3, #0]
|
|
800359a: 689a ldr r2, [r3, #8]
|
|
800359c: 68bb ldr r3, [r7, #8]
|
|
800359e: 4013 ands r3, r2
|
|
80035a0: 687a ldr r2, [r7, #4]
|
|
80035a2: 429a cmp r2, r3
|
|
80035a4: d195 bne.n 80034d2 <SPI_WaitFifoStateUntilTimeout+0x4a>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
80035a6: 2300 movs r3, #0
|
|
}
|
|
80035a8: 4618 mov r0, r3
|
|
80035aa: 3728 adds r7, #40 @ 0x28
|
|
80035ac: 46bd mov sp, r7
|
|
80035ae: bd80 pop {r7, pc}
|
|
80035b0: 2000000c .word 0x2000000c
|
|
|
|
080035b4 <SPI_EndRxTxTransaction>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80035b4: b580 push {r7, lr}
|
|
80035b6: b086 sub sp, #24
|
|
80035b8: af02 add r7, sp, #8
|
|
80035ba: 60f8 str r0, [r7, #12]
|
|
80035bc: 60b9 str r1, [r7, #8]
|
|
80035be: 607a str r2, [r7, #4]
|
|
/* Control if the TX fifo is empty */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
80035c0: 687b ldr r3, [r7, #4]
|
|
80035c2: 9300 str r3, [sp, #0]
|
|
80035c4: 68bb ldr r3, [r7, #8]
|
|
80035c6: 2200 movs r2, #0
|
|
80035c8: f44f 51c0 mov.w r1, #6144 @ 0x1800
|
|
80035cc: 68f8 ldr r0, [r7, #12]
|
|
80035ce: f7ff ff5b bl 8003488 <SPI_WaitFifoStateUntilTimeout>
|
|
80035d2: 4603 mov r3, r0
|
|
80035d4: 2b00 cmp r3, #0
|
|
80035d6: d007 beq.n 80035e8 <SPI_EndRxTxTransaction+0x34>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80035d8: 68fb ldr r3, [r7, #12]
|
|
80035da: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80035dc: f043 0220 orr.w r2, r3, #32
|
|
80035e0: 68fb ldr r3, [r7, #12]
|
|
80035e2: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
80035e4: 2303 movs r3, #3
|
|
80035e6: e027 b.n 8003638 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
/* Control the BSY flag */
|
|
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
|
|
80035e8: 687b ldr r3, [r7, #4]
|
|
80035ea: 9300 str r3, [sp, #0]
|
|
80035ec: 68bb ldr r3, [r7, #8]
|
|
80035ee: 2200 movs r2, #0
|
|
80035f0: 2180 movs r1, #128 @ 0x80
|
|
80035f2: 68f8 ldr r0, [r7, #12]
|
|
80035f4: f7ff fec0 bl 8003378 <SPI_WaitFlagStateUntilTimeout>
|
|
80035f8: 4603 mov r3, r0
|
|
80035fa: 2b00 cmp r3, #0
|
|
80035fc: d007 beq.n 800360e <SPI_EndRxTxTransaction+0x5a>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
80035fe: 68fb ldr r3, [r7, #12]
|
|
8003600: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003602: f043 0220 orr.w r2, r3, #32
|
|
8003606: 68fb ldr r3, [r7, #12]
|
|
8003608: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
800360a: 2303 movs r3, #3
|
|
800360c: e014 b.n 8003638 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
/* Control if the RX fifo is empty */
|
|
if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
|
|
800360e: 687b ldr r3, [r7, #4]
|
|
8003610: 9300 str r3, [sp, #0]
|
|
8003612: 68bb ldr r3, [r7, #8]
|
|
8003614: 2200 movs r2, #0
|
|
8003616: f44f 61c0 mov.w r1, #1536 @ 0x600
|
|
800361a: 68f8 ldr r0, [r7, #12]
|
|
800361c: f7ff ff34 bl 8003488 <SPI_WaitFifoStateUntilTimeout>
|
|
8003620: 4603 mov r3, r0
|
|
8003622: 2b00 cmp r3, #0
|
|
8003624: d007 beq.n 8003636 <SPI_EndRxTxTransaction+0x82>
|
|
{
|
|
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
|
|
8003626: 68fb ldr r3, [r7, #12]
|
|
8003628: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800362a: f043 0220 orr.w r2, r3, #32
|
|
800362e: 68fb ldr r3, [r7, #12]
|
|
8003630: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_TIMEOUT;
|
|
8003632: 2303 movs r3, #3
|
|
8003634: e000 b.n 8003638 <SPI_EndRxTxTransaction+0x84>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003636: 2300 movs r3, #0
|
|
}
|
|
8003638: 4618 mov r0, r3
|
|
800363a: 3710 adds r7, #16
|
|
800363c: 46bd mov sp, r7
|
|
800363e: bd80 pop {r7, pc}
|
|
|
|
08003640 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8003640: b580 push {r7, lr}
|
|
8003642: b082 sub sp, #8
|
|
8003644: af00 add r7, sp, #0
|
|
8003646: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8003648: 687b ldr r3, [r7, #4]
|
|
800364a: 2b00 cmp r3, #0
|
|
800364c: d101 bne.n 8003652 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800364e: 2301 movs r3, #1
|
|
8003650: e042 b.n 80036d8 <HAL_UART_Init+0x98>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8003652: 687b ldr r3, [r7, #4]
|
|
8003654: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003658: 2b00 cmp r3, #0
|
|
800365a: d106 bne.n 800366a <HAL_UART_Init+0x2a>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
800365c: 687b ldr r3, [r7, #4]
|
|
800365e: 2200 movs r2, #0
|
|
8003660: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8003664: 6878 ldr r0, [r7, #4]
|
|
8003666: f7fd ffd5 bl 8001614 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
800366a: 687b ldr r3, [r7, #4]
|
|
800366c: 2224 movs r2, #36 @ 0x24
|
|
800366e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8003672: 687b ldr r3, [r7, #4]
|
|
8003674: 681b ldr r3, [r3, #0]
|
|
8003676: 681a ldr r2, [r3, #0]
|
|
8003678: 687b ldr r3, [r7, #4]
|
|
800367a: 681b ldr r3, [r3, #0]
|
|
800367c: f022 0201 bic.w r2, r2, #1
|
|
8003680: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8003682: 687b ldr r3, [r7, #4]
|
|
8003684: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003686: 2b00 cmp r3, #0
|
|
8003688: d002 beq.n 8003690 <HAL_UART_Init+0x50>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
800368a: 6878 ldr r0, [r7, #4]
|
|
800368c: f000 fea2 bl 80043d4 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8003690: 6878 ldr r0, [r7, #4]
|
|
8003692: f000 fbd3 bl 8003e3c <UART_SetConfig>
|
|
8003696: 4603 mov r3, r0
|
|
8003698: 2b01 cmp r3, #1
|
|
800369a: d101 bne.n 80036a0 <HAL_UART_Init+0x60>
|
|
{
|
|
return HAL_ERROR;
|
|
800369c: 2301 movs r3, #1
|
|
800369e: e01b b.n 80036d8 <HAL_UART_Init+0x98>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
80036a0: 687b ldr r3, [r7, #4]
|
|
80036a2: 681b ldr r3, [r3, #0]
|
|
80036a4: 685a ldr r2, [r3, #4]
|
|
80036a6: 687b ldr r3, [r7, #4]
|
|
80036a8: 681b ldr r3, [r3, #0]
|
|
80036aa: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
80036ae: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
80036b0: 687b ldr r3, [r7, #4]
|
|
80036b2: 681b ldr r3, [r3, #0]
|
|
80036b4: 689a ldr r2, [r3, #8]
|
|
80036b6: 687b ldr r3, [r7, #4]
|
|
80036b8: 681b ldr r3, [r3, #0]
|
|
80036ba: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
80036be: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
80036c0: 687b ldr r3, [r7, #4]
|
|
80036c2: 681b ldr r3, [r3, #0]
|
|
80036c4: 681a ldr r2, [r3, #0]
|
|
80036c6: 687b ldr r3, [r7, #4]
|
|
80036c8: 681b ldr r3, [r3, #0]
|
|
80036ca: f042 0201 orr.w r2, r2, #1
|
|
80036ce: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
80036d0: 6878 ldr r0, [r7, #4]
|
|
80036d2: f000 ff21 bl 8004518 <UART_CheckIdleState>
|
|
80036d6: 4603 mov r3, r0
|
|
}
|
|
80036d8: 4618 mov r0, r3
|
|
80036da: 3708 adds r7, #8
|
|
80036dc: 46bd mov sp, r7
|
|
80036de: bd80 pop {r7, pc}
|
|
|
|
080036e0 <HAL_UART_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
80036e0: b580 push {r7, lr}
|
|
80036e2: b08a sub sp, #40 @ 0x28
|
|
80036e4: af00 add r7, sp, #0
|
|
80036e6: 60f8 str r0, [r7, #12]
|
|
80036e8: 60b9 str r1, [r7, #8]
|
|
80036ea: 4613 mov r3, r2
|
|
80036ec: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
80036ee: 68fb ldr r3, [r7, #12]
|
|
80036f0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80036f4: 2b20 cmp r3, #32
|
|
80036f6: d137 bne.n 8003768 <HAL_UART_Receive_IT+0x88>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80036f8: 68bb ldr r3, [r7, #8]
|
|
80036fa: 2b00 cmp r3, #0
|
|
80036fc: d002 beq.n 8003704 <HAL_UART_Receive_IT+0x24>
|
|
80036fe: 88fb ldrh r3, [r7, #6]
|
|
8003700: 2b00 cmp r3, #0
|
|
8003702: d101 bne.n 8003708 <HAL_UART_Receive_IT+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
8003704: 2301 movs r3, #1
|
|
8003706: e030 b.n 800376a <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8003708: 68fb ldr r3, [r7, #12]
|
|
800370a: 2200 movs r2, #0
|
|
800370c: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
800370e: 68fb ldr r3, [r7, #12]
|
|
8003710: 681b ldr r3, [r3, #0]
|
|
8003712: 4a18 ldr r2, [pc, #96] @ (8003774 <HAL_UART_Receive_IT+0x94>)
|
|
8003714: 4293 cmp r3, r2
|
|
8003716: d01f beq.n 8003758 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8003718: 68fb ldr r3, [r7, #12]
|
|
800371a: 681b ldr r3, [r3, #0]
|
|
800371c: 685b ldr r3, [r3, #4]
|
|
800371e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8003722: 2b00 cmp r3, #0
|
|
8003724: d018 beq.n 8003758 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8003726: 68fb ldr r3, [r7, #12]
|
|
8003728: 681b ldr r3, [r3, #0]
|
|
800372a: 617b str r3, [r7, #20]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800372c: 697b ldr r3, [r7, #20]
|
|
800372e: e853 3f00 ldrex r3, [r3]
|
|
8003732: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8003734: 693b ldr r3, [r7, #16]
|
|
8003736: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
800373a: 627b str r3, [r7, #36] @ 0x24
|
|
800373c: 68fb ldr r3, [r7, #12]
|
|
800373e: 681b ldr r3, [r3, #0]
|
|
8003740: 461a mov r2, r3
|
|
8003742: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003744: 623b str r3, [r7, #32]
|
|
8003746: 61fa str r2, [r7, #28]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003748: 69f9 ldr r1, [r7, #28]
|
|
800374a: 6a3a ldr r2, [r7, #32]
|
|
800374c: e841 2300 strex r3, r2, [r1]
|
|
8003750: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8003752: 69bb ldr r3, [r7, #24]
|
|
8003754: 2b00 cmp r3, #0
|
|
8003756: d1e6 bne.n 8003726 <HAL_UART_Receive_IT+0x46>
|
|
}
|
|
}
|
|
|
|
return (UART_Start_Receive_IT(huart, pData, Size));
|
|
8003758: 88fb ldrh r3, [r7, #6]
|
|
800375a: 461a mov r2, r3
|
|
800375c: 68b9 ldr r1, [r7, #8]
|
|
800375e: 68f8 ldr r0, [r7, #12]
|
|
8003760: f000 fff2 bl 8004748 <UART_Start_Receive_IT>
|
|
8003764: 4603 mov r3, r0
|
|
8003766: e000 b.n 800376a <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003768: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800376a: 4618 mov r0, r3
|
|
800376c: 3728 adds r7, #40 @ 0x28
|
|
800376e: 46bd mov sp, r7
|
|
8003770: bd80 pop {r7, pc}
|
|
8003772: bf00 nop
|
|
8003774: 40008000 .word 0x40008000
|
|
|
|
08003778 <HAL_UART_IRQHandler>:
|
|
* @brief Handle UART interrupt request.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8003778: b580 push {r7, lr}
|
|
800377a: b0ba sub sp, #232 @ 0xe8
|
|
800377c: af00 add r7, sp, #0
|
|
800377e: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8003780: 687b ldr r3, [r7, #4]
|
|
8003782: 681b ldr r3, [r3, #0]
|
|
8003784: 69db ldr r3, [r3, #28]
|
|
8003786: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
800378a: 687b ldr r3, [r7, #4]
|
|
800378c: 681b ldr r3, [r3, #0]
|
|
800378e: 681b ldr r3, [r3, #0]
|
|
8003790: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8003794: 687b ldr r3, [r7, #4]
|
|
8003796: 681b ldr r3, [r3, #0]
|
|
8003798: 689b ldr r3, [r3, #8]
|
|
800379a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
|
|
uint32_t errorflags;
|
|
uint32_t errorcode;
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
800379e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
|
|
80037a2: f640 030f movw r3, #2063 @ 0x80f
|
|
80037a6: 4013 ands r3, r2
|
|
80037a8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == 0U)
|
|
80037ac: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80037b0: 2b00 cmp r3, #0
|
|
80037b2: d11b bne.n 80037ec <HAL_UART_IRQHandler+0x74>
|
|
{
|
|
/* UART in mode Receiver ---------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
80037b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80037b8: f003 0320 and.w r3, r3, #32
|
|
80037bc: 2b00 cmp r3, #0
|
|
80037be: d015 beq.n 80037ec <HAL_UART_IRQHandler+0x74>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
80037c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80037c4: f003 0320 and.w r3, r3, #32
|
|
80037c8: 2b00 cmp r3, #0
|
|
80037ca: d105 bne.n 80037d8 <HAL_UART_IRQHandler+0x60>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
80037cc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80037d0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80037d4: 2b00 cmp r3, #0
|
|
80037d6: d009 beq.n 80037ec <HAL_UART_IRQHandler+0x74>
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
80037d8: 687b ldr r3, [r7, #4]
|
|
80037da: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80037dc: 2b00 cmp r3, #0
|
|
80037de: f000 8300 beq.w 8003de2 <HAL_UART_IRQHandler+0x66a>
|
|
{
|
|
huart->RxISR(huart);
|
|
80037e2: 687b ldr r3, [r7, #4]
|
|
80037e4: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80037e6: 6878 ldr r0, [r7, #4]
|
|
80037e8: 4798 blx r3
|
|
}
|
|
return;
|
|
80037ea: e2fa b.n 8003de2 <HAL_UART_IRQHandler+0x66a>
|
|
}
|
|
}
|
|
|
|
/* If some errors occur */
|
|
if ((errorflags != 0U)
|
|
80037ec: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
80037f0: 2b00 cmp r3, #0
|
|
80037f2: f000 8123 beq.w 8003a3c <HAL_UART_IRQHandler+0x2c4>
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
80037f6: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
|
|
80037fa: 4b8d ldr r3, [pc, #564] @ (8003a30 <HAL_UART_IRQHandler+0x2b8>)
|
|
80037fc: 4013 ands r3, r2
|
|
80037fe: 2b00 cmp r3, #0
|
|
8003800: d106 bne.n 8003810 <HAL_UART_IRQHandler+0x98>
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
8003802: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
|
|
8003806: 4b8b ldr r3, [pc, #556] @ (8003a34 <HAL_UART_IRQHandler+0x2bc>)
|
|
8003808: 4013 ands r3, r2
|
|
800380a: 2b00 cmp r3, #0
|
|
800380c: f000 8116 beq.w 8003a3c <HAL_UART_IRQHandler+0x2c4>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8003810: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003814: f003 0301 and.w r3, r3, #1
|
|
8003818: 2b00 cmp r3, #0
|
|
800381a: d011 beq.n 8003840 <HAL_UART_IRQHandler+0xc8>
|
|
800381c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8003820: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003824: 2b00 cmp r3, #0
|
|
8003826: d00b beq.n 8003840 <HAL_UART_IRQHandler+0xc8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8003828: 687b ldr r3, [r7, #4]
|
|
800382a: 681b ldr r3, [r3, #0]
|
|
800382c: 2201 movs r2, #1
|
|
800382e: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8003830: 687b ldr r3, [r7, #4]
|
|
8003832: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003836: f043 0201 orr.w r2, r3, #1
|
|
800383a: 687b ldr r3, [r7, #4]
|
|
800383c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8003840: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003844: f003 0302 and.w r3, r3, #2
|
|
8003848: 2b00 cmp r3, #0
|
|
800384a: d011 beq.n 8003870 <HAL_UART_IRQHandler+0xf8>
|
|
800384c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8003850: f003 0301 and.w r3, r3, #1
|
|
8003854: 2b00 cmp r3, #0
|
|
8003856: d00b beq.n 8003870 <HAL_UART_IRQHandler+0xf8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8003858: 687b ldr r3, [r7, #4]
|
|
800385a: 681b ldr r3, [r3, #0]
|
|
800385c: 2202 movs r2, #2
|
|
800385e: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8003860: 687b ldr r3, [r7, #4]
|
|
8003862: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003866: f043 0204 orr.w r2, r3, #4
|
|
800386a: 687b ldr r3, [r7, #4]
|
|
800386c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8003870: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003874: f003 0304 and.w r3, r3, #4
|
|
8003878: 2b00 cmp r3, #0
|
|
800387a: d011 beq.n 80038a0 <HAL_UART_IRQHandler+0x128>
|
|
800387c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8003880: f003 0301 and.w r3, r3, #1
|
|
8003884: 2b00 cmp r3, #0
|
|
8003886: d00b beq.n 80038a0 <HAL_UART_IRQHandler+0x128>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8003888: 687b ldr r3, [r7, #4]
|
|
800388a: 681b ldr r3, [r3, #0]
|
|
800388c: 2204 movs r2, #4
|
|
800388e: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8003890: 687b ldr r3, [r7, #4]
|
|
8003892: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003896: f043 0202 orr.w r2, r3, #2
|
|
800389a: 687b ldr r3, [r7, #4]
|
|
800389c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART Over-Run interrupt occurred -----------------------------------------*/
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
80038a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80038a4: f003 0308 and.w r3, r3, #8
|
|
80038a8: 2b00 cmp r3, #0
|
|
80038aa: d017 beq.n 80038dc <HAL_UART_IRQHandler+0x164>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
80038ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80038b0: f003 0320 and.w r3, r3, #32
|
|
80038b4: 2b00 cmp r3, #0
|
|
80038b6: d105 bne.n 80038c4 <HAL_UART_IRQHandler+0x14c>
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
80038b8: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
|
|
80038bc: 4b5c ldr r3, [pc, #368] @ (8003a30 <HAL_UART_IRQHandler+0x2b8>)
|
|
80038be: 4013 ands r3, r2
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
80038c0: 2b00 cmp r3, #0
|
|
80038c2: d00b beq.n 80038dc <HAL_UART_IRQHandler+0x164>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
80038c4: 687b ldr r3, [r7, #4]
|
|
80038c6: 681b ldr r3, [r3, #0]
|
|
80038c8: 2208 movs r2, #8
|
|
80038ca: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
80038cc: 687b ldr r3, [r7, #4]
|
|
80038ce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80038d2: f043 0208 orr.w r2, r3, #8
|
|
80038d6: 687b ldr r3, [r7, #4]
|
|
80038d8: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
80038dc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80038e0: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80038e4: 2b00 cmp r3, #0
|
|
80038e6: d012 beq.n 800390e <HAL_UART_IRQHandler+0x196>
|
|
80038e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80038ec: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
80038f0: 2b00 cmp r3, #0
|
|
80038f2: d00c beq.n 800390e <HAL_UART_IRQHandler+0x196>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
80038f4: 687b ldr r3, [r7, #4]
|
|
80038f6: 681b ldr r3, [r3, #0]
|
|
80038f8: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
80038fc: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
80038fe: 687b ldr r3, [r7, #4]
|
|
8003900: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003904: f043 0220 orr.w r2, r3, #32
|
|
8003908: 687b ldr r3, [r7, #4]
|
|
800390a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
800390e: 687b ldr r3, [r7, #4]
|
|
8003910: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003914: 2b00 cmp r3, #0
|
|
8003916: f000 8266 beq.w 8003de6 <HAL_UART_IRQHandler+0x66e>
|
|
{
|
|
/* UART in mode Receiver --------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
800391a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800391e: f003 0320 and.w r3, r3, #32
|
|
8003922: 2b00 cmp r3, #0
|
|
8003924: d013 beq.n 800394e <HAL_UART_IRQHandler+0x1d6>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
8003926: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800392a: f003 0320 and.w r3, r3, #32
|
|
800392e: 2b00 cmp r3, #0
|
|
8003930: d105 bne.n 800393e <HAL_UART_IRQHandler+0x1c6>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
8003932: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8003936: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800393a: 2b00 cmp r3, #0
|
|
800393c: d007 beq.n 800394e <HAL_UART_IRQHandler+0x1d6>
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
800393e: 687b ldr r3, [r7, #4]
|
|
8003940: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8003942: 2b00 cmp r3, #0
|
|
8003944: d003 beq.n 800394e <HAL_UART_IRQHandler+0x1d6>
|
|
{
|
|
huart->RxISR(huart);
|
|
8003946: 687b ldr r3, [r7, #4]
|
|
8003948: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800394a: 6878 ldr r0, [r7, #4]
|
|
800394c: 4798 blx r3
|
|
/* If Error is to be considered as blocking :
|
|
- Receiver Timeout error in Reception
|
|
- Overrun error in Reception
|
|
- any error occurs in DMA mode reception
|
|
*/
|
|
errorcode = huart->ErrorCode;
|
|
800394e: 687b ldr r3, [r7, #4]
|
|
8003950: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003954: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8003958: 687b ldr r3, [r7, #4]
|
|
800395a: 681b ldr r3, [r3, #0]
|
|
800395c: 689b ldr r3, [r3, #8]
|
|
800395e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003962: 2b40 cmp r3, #64 @ 0x40
|
|
8003964: d005 beq.n 8003972 <HAL_UART_IRQHandler+0x1fa>
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
8003966: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
800396a: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800396e: 2b00 cmp r3, #0
|
|
8003970: d054 beq.n 8003a1c <HAL_UART_IRQHandler+0x2a4>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8003972: 6878 ldr r0, [r7, #4]
|
|
8003974: f001 f80a bl 800498c <UART_EndRxTransfer>
|
|
|
|
/* Abort the UART DMA Rx channel if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8003978: 687b ldr r3, [r7, #4]
|
|
800397a: 681b ldr r3, [r3, #0]
|
|
800397c: 689b ldr r3, [r3, #8]
|
|
800397e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003982: 2b40 cmp r3, #64 @ 0x40
|
|
8003984: d146 bne.n 8003a14 <HAL_UART_IRQHandler+0x29c>
|
|
{
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8003986: 687b ldr r3, [r7, #4]
|
|
8003988: 681b ldr r3, [r3, #0]
|
|
800398a: 3308 adds r3, #8
|
|
800398c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003990: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8003994: e853 3f00 ldrex r3, [r3]
|
|
8003998: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
800399c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80039a0: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80039a4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80039a8: 687b ldr r3, [r7, #4]
|
|
80039aa: 681b ldr r3, [r3, #0]
|
|
80039ac: 3308 adds r3, #8
|
|
80039ae: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
80039b2: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
80039b6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80039ba: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
80039be: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
80039c2: e841 2300 strex r3, r2, [r1]
|
|
80039c6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
80039ca: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
80039ce: 2b00 cmp r3, #0
|
|
80039d0: d1d9 bne.n 8003986 <HAL_UART_IRQHandler+0x20e>
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
80039d2: 687b ldr r3, [r7, #4]
|
|
80039d4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80039d8: 2b00 cmp r3, #0
|
|
80039da: d017 beq.n 8003a0c <HAL_UART_IRQHandler+0x294>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
80039dc: 687b ldr r3, [r7, #4]
|
|
80039de: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80039e2: 4a15 ldr r2, [pc, #84] @ (8003a38 <HAL_UART_IRQHandler+0x2c0>)
|
|
80039e4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
80039e6: 687b ldr r3, [r7, #4]
|
|
80039e8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80039ec: 4618 mov r0, r3
|
|
80039ee: f7fe f8c4 bl 8001b7a <HAL_DMA_Abort_IT>
|
|
80039f2: 4603 mov r3, r0
|
|
80039f4: 2b00 cmp r3, #0
|
|
80039f6: d019 beq.n 8003a2c <HAL_UART_IRQHandler+0x2b4>
|
|
{
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
80039f8: 687b ldr r3, [r7, #4]
|
|
80039fa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80039fe: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003a00: 687a ldr r2, [r7, #4]
|
|
8003a02: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80
|
|
8003a06: 4610 mov r0, r2
|
|
8003a08: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8003a0a: e00f b.n 8003a2c <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8003a0c: 6878 ldr r0, [r7, #4]
|
|
8003a0e: f000 f9ff bl 8003e10 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8003a12: e00b b.n 8003a2c <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8003a14: 6878 ldr r0, [r7, #4]
|
|
8003a16: f000 f9fb bl 8003e10 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8003a1a: e007 b.n 8003a2c <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8003a1c: 6878 ldr r0, [r7, #4]
|
|
8003a1e: f000 f9f7 bl 8003e10 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8003a22: 687b ldr r3, [r7, #4]
|
|
8003a24: 2200 movs r2, #0
|
|
8003a26: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
return;
|
|
8003a2a: e1dc b.n 8003de6 <HAL_UART_IRQHandler+0x66e>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8003a2c: bf00 nop
|
|
return;
|
|
8003a2e: e1da b.n 8003de6 <HAL_UART_IRQHandler+0x66e>
|
|
8003a30: 10000001 .word 0x10000001
|
|
8003a34: 04000120 .word 0x04000120
|
|
8003a38: 08004a59 .word 0x08004a59
|
|
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8003a3c: 687b ldr r3, [r7, #4]
|
|
8003a3e: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8003a40: 2b01 cmp r3, #1
|
|
8003a42: f040 8170 bne.w 8003d26 <HAL_UART_IRQHandler+0x5ae>
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
8003a46: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003a4a: f003 0310 and.w r3, r3, #16
|
|
8003a4e: 2b00 cmp r3, #0
|
|
8003a50: f000 8169 beq.w 8003d26 <HAL_UART_IRQHandler+0x5ae>
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
8003a54: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8003a58: f003 0310 and.w r3, r3, #16
|
|
8003a5c: 2b00 cmp r3, #0
|
|
8003a5e: f000 8162 beq.w 8003d26 <HAL_UART_IRQHandler+0x5ae>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8003a62: 687b ldr r3, [r7, #4]
|
|
8003a64: 681b ldr r3, [r3, #0]
|
|
8003a66: 2210 movs r2, #16
|
|
8003a68: 621a str r2, [r3, #32]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8003a6a: 687b ldr r3, [r7, #4]
|
|
8003a6c: 681b ldr r3, [r3, #0]
|
|
8003a6e: 689b ldr r3, [r3, #8]
|
|
8003a70: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003a74: 2b40 cmp r3, #64 @ 0x40
|
|
8003a76: f040 80d8 bne.w 8003c2a <HAL_UART_IRQHandler+0x4b2>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
8003a7a: 687b ldr r3, [r7, #4]
|
|
8003a7c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003a80: 681b ldr r3, [r3, #0]
|
|
8003a82: 685b ldr r3, [r3, #4]
|
|
8003a84: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
8003a88: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
8003a8c: 2b00 cmp r3, #0
|
|
8003a8e: f000 80af beq.w 8003bf0 <HAL_UART_IRQHandler+0x478>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
8003a92: 687b ldr r3, [r7, #4]
|
|
8003a94: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8003a98: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8003a9c: 429a cmp r2, r3
|
|
8003a9e: f080 80a7 bcs.w 8003bf0 <HAL_UART_IRQHandler+0x478>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
8003aa2: 687b ldr r3, [r7, #4]
|
|
8003aa4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8003aa8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
8003aac: 687b ldr r3, [r7, #4]
|
|
8003aae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003ab2: 681b ldr r3, [r3, #0]
|
|
8003ab4: 681b ldr r3, [r3, #0]
|
|
8003ab6: f003 0320 and.w r3, r3, #32
|
|
8003aba: 2b00 cmp r3, #0
|
|
8003abc: f040 8087 bne.w 8003bce <HAL_UART_IRQHandler+0x456>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8003ac0: 687b ldr r3, [r7, #4]
|
|
8003ac2: 681b ldr r3, [r3, #0]
|
|
8003ac4: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003ac8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
8003acc: e853 3f00 ldrex r3, [r3]
|
|
8003ad0: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
8003ad4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8003ad8: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8003adc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8003ae0: 687b ldr r3, [r7, #4]
|
|
8003ae2: 681b ldr r3, [r3, #0]
|
|
8003ae4: 461a mov r2, r3
|
|
8003ae6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
8003aea: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8003aee: f8c7 2090 str.w r2, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003af2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
8003af6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
8003afa: e841 2300 strex r3, r2, [r1]
|
|
8003afe: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
8003b02: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8003b06: 2b00 cmp r3, #0
|
|
8003b08: d1da bne.n 8003ac0 <HAL_UART_IRQHandler+0x348>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8003b0a: 687b ldr r3, [r7, #4]
|
|
8003b0c: 681b ldr r3, [r3, #0]
|
|
8003b0e: 3308 adds r3, #8
|
|
8003b10: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003b12: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8003b14: e853 3f00 ldrex r3, [r3]
|
|
8003b18: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8003b1a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8003b1c: f023 0301 bic.w r3, r3, #1
|
|
8003b20: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8003b24: 687b ldr r3, [r7, #4]
|
|
8003b26: 681b ldr r3, [r3, #0]
|
|
8003b28: 3308 adds r3, #8
|
|
8003b2a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
8003b2e: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
8003b32: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003b34: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8003b36: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8003b3a: e841 2300 strex r3, r2, [r1]
|
|
8003b3e: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8003b40: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8003b42: 2b00 cmp r3, #0
|
|
8003b44: d1e1 bne.n 8003b0a <HAL_UART_IRQHandler+0x392>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8003b46: 687b ldr r3, [r7, #4]
|
|
8003b48: 681b ldr r3, [r3, #0]
|
|
8003b4a: 3308 adds r3, #8
|
|
8003b4c: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003b4e: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8003b50: e853 3f00 ldrex r3, [r3]
|
|
8003b54: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8003b56: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8003b58: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8003b5c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8003b60: 687b ldr r3, [r7, #4]
|
|
8003b62: 681b ldr r3, [r3, #0]
|
|
8003b64: 3308 adds r3, #8
|
|
8003b66: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
8003b6a: 66fa str r2, [r7, #108] @ 0x6c
|
|
8003b6c: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003b6e: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8003b70: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
8003b72: e841 2300 strex r3, r2, [r1]
|
|
8003b76: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8003b78: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8003b7a: 2b00 cmp r3, #0
|
|
8003b7c: d1e3 bne.n 8003b46 <HAL_UART_IRQHandler+0x3ce>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8003b7e: 687b ldr r3, [r7, #4]
|
|
8003b80: 2220 movs r2, #32
|
|
8003b82: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8003b86: 687b ldr r3, [r7, #4]
|
|
8003b88: 2200 movs r2, #0
|
|
8003b8a: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8003b8c: 687b ldr r3, [r7, #4]
|
|
8003b8e: 681b ldr r3, [r3, #0]
|
|
8003b90: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003b92: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8003b94: e853 3f00 ldrex r3, [r3]
|
|
8003b98: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8003b9a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8003b9c: f023 0310 bic.w r3, r3, #16
|
|
8003ba0: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
8003ba4: 687b ldr r3, [r7, #4]
|
|
8003ba6: 681b ldr r3, [r3, #0]
|
|
8003ba8: 461a mov r2, r3
|
|
8003baa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8003bae: 65bb str r3, [r7, #88] @ 0x58
|
|
8003bb0: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003bb2: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8003bb4: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8003bb6: e841 2300 strex r3, r2, [r1]
|
|
8003bba: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8003bbc: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8003bbe: 2b00 cmp r3, #0
|
|
8003bc0: d1e4 bne.n 8003b8c <HAL_UART_IRQHandler+0x414>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
8003bc2: 687b ldr r3, [r7, #4]
|
|
8003bc4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003bc8: 4618 mov r0, r3
|
|
8003bca: f7fd ff78 bl 8001abe <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8003bce: 687b ldr r3, [r7, #4]
|
|
8003bd0: 2202 movs r2, #2
|
|
8003bd2: 671a str r2, [r3, #112] @ 0x70
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8003bd4: 687b ldr r3, [r7, #4]
|
|
8003bd6: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
|
|
8003bda: 687b ldr r3, [r7, #4]
|
|
8003bdc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8003be0: b29b uxth r3, r3
|
|
8003be2: 1ad3 subs r3, r2, r3
|
|
8003be4: b29b uxth r3, r3
|
|
8003be6: 4619 mov r1, r3
|
|
8003be8: 6878 ldr r0, [r7, #4]
|
|
8003bea: f000 f91b bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
8003bee: e0fc b.n 8003dea <HAL_UART_IRQHandler+0x672>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
8003bf0: 687b ldr r3, [r7, #4]
|
|
8003bf2: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8003bf6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8003bfa: 429a cmp r2, r3
|
|
8003bfc: f040 80f5 bne.w 8003dea <HAL_UART_IRQHandler+0x672>
|
|
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
8003c00: 687b ldr r3, [r7, #4]
|
|
8003c02: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003c06: 681b ldr r3, [r3, #0]
|
|
8003c08: 681b ldr r3, [r3, #0]
|
|
8003c0a: f003 0320 and.w r3, r3, #32
|
|
8003c0e: 2b20 cmp r3, #32
|
|
8003c10: f040 80eb bne.w 8003dea <HAL_UART_IRQHandler+0x672>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8003c14: 687b ldr r3, [r7, #4]
|
|
8003c16: 2202 movs r2, #2
|
|
8003c18: 671a str r2, [r3, #112] @ 0x70
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8003c1a: 687b ldr r3, [r7, #4]
|
|
8003c1c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8003c20: 4619 mov r1, r3
|
|
8003c22: 6878 ldr r0, [r7, #4]
|
|
8003c24: f000 f8fe bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
8003c28: e0df b.n 8003dea <HAL_UART_IRQHandler+0x672>
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
8003c2a: 687b ldr r3, [r7, #4]
|
|
8003c2c: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
|
|
8003c30: 687b ldr r3, [r7, #4]
|
|
8003c32: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8003c36: b29b uxth r3, r3
|
|
8003c38: 1ad3 subs r3, r2, r3
|
|
8003c3a: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
8003c3e: 687b ldr r3, [r7, #4]
|
|
8003c40: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8003c44: b29b uxth r3, r3
|
|
8003c46: 2b00 cmp r3, #0
|
|
8003c48: f000 80d1 beq.w 8003dee <HAL_UART_IRQHandler+0x676>
|
|
&& (nb_rx_data > 0U))
|
|
8003c4c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8003c50: 2b00 cmp r3, #0
|
|
8003c52: f000 80cc beq.w 8003dee <HAL_UART_IRQHandler+0x676>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8003c56: 687b ldr r3, [r7, #4]
|
|
8003c58: 681b ldr r3, [r3, #0]
|
|
8003c5a: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003c5c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8003c5e: e853 3f00 ldrex r3, [r3]
|
|
8003c62: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8003c64: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8003c66: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8003c6a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8003c6e: 687b ldr r3, [r7, #4]
|
|
8003c70: 681b ldr r3, [r3, #0]
|
|
8003c72: 461a mov r2, r3
|
|
8003c74: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8003c78: 647b str r3, [r7, #68] @ 0x44
|
|
8003c7a: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003c7c: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8003c7e: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8003c80: e841 2300 strex r3, r2, [r1]
|
|
8003c84: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8003c86: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8003c88: 2b00 cmp r3, #0
|
|
8003c8a: d1e4 bne.n 8003c56 <HAL_UART_IRQHandler+0x4de>
|
|
|
|
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8003c8c: 687b ldr r3, [r7, #4]
|
|
8003c8e: 681b ldr r3, [r3, #0]
|
|
8003c90: 3308 adds r3, #8
|
|
8003c92: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003c94: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003c96: e853 3f00 ldrex r3, [r3]
|
|
8003c9a: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8003c9c: 6a3b ldr r3, [r7, #32]
|
|
8003c9e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003ca2: f023 0301 bic.w r3, r3, #1
|
|
8003ca6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
8003caa: 687b ldr r3, [r7, #4]
|
|
8003cac: 681b ldr r3, [r3, #0]
|
|
8003cae: 3308 adds r3, #8
|
|
8003cb0: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
8003cb4: 633a str r2, [r7, #48] @ 0x30
|
|
8003cb6: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003cb8: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8003cba: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8003cbc: e841 2300 strex r3, r2, [r1]
|
|
8003cc0: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8003cc2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003cc4: 2b00 cmp r3, #0
|
|
8003cc6: d1e1 bne.n 8003c8c <HAL_UART_IRQHandler+0x514>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8003cc8: 687b ldr r3, [r7, #4]
|
|
8003cca: 2220 movs r2, #32
|
|
8003ccc: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8003cd0: 687b ldr r3, [r7, #4]
|
|
8003cd2: 2200 movs r2, #0
|
|
8003cd4: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8003cd6: 687b ldr r3, [r7, #4]
|
|
8003cd8: 2200 movs r2, #0
|
|
8003cda: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8003cdc: 687b ldr r3, [r7, #4]
|
|
8003cde: 681b ldr r3, [r3, #0]
|
|
8003ce0: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8003ce2: 693b ldr r3, [r7, #16]
|
|
8003ce4: e853 3f00 ldrex r3, [r3]
|
|
8003ce8: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8003cea: 68fb ldr r3, [r7, #12]
|
|
8003cec: f023 0310 bic.w r3, r3, #16
|
|
8003cf0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8003cf4: 687b ldr r3, [r7, #4]
|
|
8003cf6: 681b ldr r3, [r3, #0]
|
|
8003cf8: 461a mov r2, r3
|
|
8003cfa: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
8003cfe: 61fb str r3, [r7, #28]
|
|
8003d00: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8003d02: 69b9 ldr r1, [r7, #24]
|
|
8003d04: 69fa ldr r2, [r7, #28]
|
|
8003d06: e841 2300 strex r3, r2, [r1]
|
|
8003d0a: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8003d0c: 697b ldr r3, [r7, #20]
|
|
8003d0e: 2b00 cmp r3, #0
|
|
8003d10: d1e4 bne.n 8003cdc <HAL_UART_IRQHandler+0x564>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8003d12: 687b ldr r3, [r7, #4]
|
|
8003d14: 2202 movs r2, #2
|
|
8003d16: 671a str r2, [r3, #112] @ 0x70
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
8003d18: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8003d1c: 4619 mov r1, r3
|
|
8003d1e: 6878 ldr r0, [r7, #4]
|
|
8003d20: f000 f880 bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
return;
|
|
8003d24: e063 b.n 8003dee <HAL_UART_IRQHandler+0x676>
|
|
}
|
|
}
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
8003d26: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003d2a: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8003d2e: 2b00 cmp r3, #0
|
|
8003d30: d00e beq.n 8003d50 <HAL_UART_IRQHandler+0x5d8>
|
|
8003d32: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8003d36: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8003d3a: 2b00 cmp r3, #0
|
|
8003d3c: d008 beq.n 8003d50 <HAL_UART_IRQHandler+0x5d8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
8003d3e: 687b ldr r3, [r7, #4]
|
|
8003d40: 681b ldr r3, [r3, #0]
|
|
8003d42: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
8003d46: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Wakeup Callback */
|
|
huart->WakeupCallback(huart);
|
|
#else
|
|
/* Call legacy weak Wakeup Callback */
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
8003d48: 6878 ldr r0, [r7, #4]
|
|
8003d4a: f001 fbdf bl 800550c <HAL_UARTEx_WakeupCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
8003d4e: e051 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
8003d50: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003d54: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003d58: 2b00 cmp r3, #0
|
|
8003d5a: d014 beq.n 8003d86 <HAL_UART_IRQHandler+0x60e>
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
8003d5c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8003d60: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003d64: 2b00 cmp r3, #0
|
|
8003d66: d105 bne.n 8003d74 <HAL_UART_IRQHandler+0x5fc>
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
8003d68: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8003d6c: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8003d70: 2b00 cmp r3, #0
|
|
8003d72: d008 beq.n 8003d86 <HAL_UART_IRQHandler+0x60e>
|
|
{
|
|
if (huart->TxISR != NULL)
|
|
8003d74: 687b ldr r3, [r7, #4]
|
|
8003d76: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8003d78: 2b00 cmp r3, #0
|
|
8003d7a: d03a beq.n 8003df2 <HAL_UART_IRQHandler+0x67a>
|
|
{
|
|
huart->TxISR(huart);
|
|
8003d7c: 687b ldr r3, [r7, #4]
|
|
8003d7e: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
8003d80: 6878 ldr r0, [r7, #4]
|
|
8003d82: 4798 blx r3
|
|
}
|
|
return;
|
|
8003d84: e035 b.n 8003df2 <HAL_UART_IRQHandler+0x67a>
|
|
}
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
8003d86: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003d8a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003d8e: 2b00 cmp r3, #0
|
|
8003d90: d009 beq.n 8003da6 <HAL_UART_IRQHandler+0x62e>
|
|
8003d92: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8003d96: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8003d9a: 2b00 cmp r3, #0
|
|
8003d9c: d003 beq.n 8003da6 <HAL_UART_IRQHandler+0x62e>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
8003d9e: 6878 ldr r0, [r7, #4]
|
|
8003da0: f000 fe68 bl 8004a74 <UART_EndTransmit_IT>
|
|
return;
|
|
8003da4: e026 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART TX Fifo Empty occurred ----------------------------------------------*/
|
|
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
|
|
8003da6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003daa: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8003dae: 2b00 cmp r3, #0
|
|
8003db0: d009 beq.n 8003dc6 <HAL_UART_IRQHandler+0x64e>
|
|
8003db2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8003db6: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
8003dba: 2b00 cmp r3, #0
|
|
8003dbc: d003 beq.n 8003dc6 <HAL_UART_IRQHandler+0x64e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Tx Fifo Empty Callback */
|
|
huart->TxFifoEmptyCallback(huart);
|
|
#else
|
|
/* Call legacy weak Tx Fifo Empty Callback */
|
|
HAL_UARTEx_TxFifoEmptyCallback(huart);
|
|
8003dbe: 6878 ldr r0, [r7, #4]
|
|
8003dc0: f001 fbb8 bl 8005534 <HAL_UARTEx_TxFifoEmptyCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
8003dc4: e016 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART RX Fifo Full occurred ----------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
|
|
8003dc6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8003dca: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
8003dce: 2b00 cmp r3, #0
|
|
8003dd0: d010 beq.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
8003dd2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8003dd6: 2b00 cmp r3, #0
|
|
8003dd8: da0c bge.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Rx Fifo Full Callback */
|
|
huart->RxFifoFullCallback(huart);
|
|
#else
|
|
/* Call legacy weak Rx Fifo Full Callback */
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
8003dda: 6878 ldr r0, [r7, #4]
|
|
8003ddc: f001 fba0 bl 8005520 <HAL_UARTEx_RxFifoFullCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
8003de0: e008 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8003de2: bf00 nop
|
|
8003de4: e006 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8003de6: bf00 nop
|
|
8003de8: e004 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8003dea: bf00 nop
|
|
8003dec: e002 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8003dee: bf00 nop
|
|
8003df0: e000 b.n 8003df4 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8003df2: bf00 nop
|
|
}
|
|
}
|
|
8003df4: 37e8 adds r7, #232 @ 0xe8
|
|
8003df6: 46bd mov sp, r7
|
|
8003df8: bd80 pop {r7, pc}
|
|
8003dfa: bf00 nop
|
|
|
|
08003dfc <HAL_UART_TxCpltCallback>:
|
|
* @brief Tx Transfer completed callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8003dfc: b480 push {r7}
|
|
8003dfe: b083 sub sp, #12
|
|
8003e00: af00 add r7, sp, #0
|
|
8003e02: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8003e04: bf00 nop
|
|
8003e06: 370c adds r7, #12
|
|
8003e08: 46bd mov sp, r7
|
|
8003e0a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e0e: 4770 bx lr
|
|
|
|
08003e10 <HAL_UART_ErrorCallback>:
|
|
* @brief UART error callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8003e10: b480 push {r7}
|
|
8003e12: b083 sub sp, #12
|
|
8003e14: af00 add r7, sp, #0
|
|
8003e16: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8003e18: bf00 nop
|
|
8003e1a: 370c adds r7, #12
|
|
8003e1c: 46bd mov sp, r7
|
|
8003e1e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e22: 4770 bx lr
|
|
|
|
08003e24 <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
8003e24: b480 push {r7}
|
|
8003e26: b083 sub sp, #12
|
|
8003e28: af00 add r7, sp, #0
|
|
8003e2a: 6078 str r0, [r7, #4]
|
|
8003e2c: 460b mov r3, r1
|
|
8003e2e: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8003e30: bf00 nop
|
|
8003e32: 370c adds r7, #12
|
|
8003e34: 46bd mov sp, r7
|
|
8003e36: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e3a: 4770 bx lr
|
|
|
|
08003e3c <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8003e3c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8003e40: b08c sub sp, #48 @ 0x30
|
|
8003e42: af00 add r7, sp, #0
|
|
8003e44: 6178 str r0, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8003e46: 2300 movs r3, #0
|
|
8003e48: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8003e4c: 697b ldr r3, [r7, #20]
|
|
8003e4e: 689a ldr r2, [r3, #8]
|
|
8003e50: 697b ldr r3, [r7, #20]
|
|
8003e52: 691b ldr r3, [r3, #16]
|
|
8003e54: 431a orrs r2, r3
|
|
8003e56: 697b ldr r3, [r7, #20]
|
|
8003e58: 695b ldr r3, [r3, #20]
|
|
8003e5a: 431a orrs r2, r3
|
|
8003e5c: 697b ldr r3, [r7, #20]
|
|
8003e5e: 69db ldr r3, [r3, #28]
|
|
8003e60: 4313 orrs r3, r2
|
|
8003e62: 62fb str r3, [r7, #44] @ 0x2c
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8003e64: 697b ldr r3, [r7, #20]
|
|
8003e66: 681b ldr r3, [r3, #0]
|
|
8003e68: 681a ldr r2, [r3, #0]
|
|
8003e6a: 4bab ldr r3, [pc, #684] @ (8004118 <UART_SetConfig+0x2dc>)
|
|
8003e6c: 4013 ands r3, r2
|
|
8003e6e: 697a ldr r2, [r7, #20]
|
|
8003e70: 6812 ldr r2, [r2, #0]
|
|
8003e72: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8003e74: 430b orrs r3, r1
|
|
8003e76: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8003e78: 697b ldr r3, [r7, #20]
|
|
8003e7a: 681b ldr r3, [r3, #0]
|
|
8003e7c: 685b ldr r3, [r3, #4]
|
|
8003e7e: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
8003e82: 697b ldr r3, [r7, #20]
|
|
8003e84: 68da ldr r2, [r3, #12]
|
|
8003e86: 697b ldr r3, [r7, #20]
|
|
8003e88: 681b ldr r3, [r3, #0]
|
|
8003e8a: 430a orrs r2, r1
|
|
8003e8c: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
8003e8e: 697b ldr r3, [r7, #20]
|
|
8003e90: 699b ldr r3, [r3, #24]
|
|
8003e92: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
8003e94: 697b ldr r3, [r7, #20]
|
|
8003e96: 681b ldr r3, [r3, #0]
|
|
8003e98: 4aa0 ldr r2, [pc, #640] @ (800411c <UART_SetConfig+0x2e0>)
|
|
8003e9a: 4293 cmp r3, r2
|
|
8003e9c: d004 beq.n 8003ea8 <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8003e9e: 697b ldr r3, [r7, #20]
|
|
8003ea0: 6a1b ldr r3, [r3, #32]
|
|
8003ea2: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8003ea4: 4313 orrs r3, r2
|
|
8003ea6: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8003ea8: 697b ldr r3, [r7, #20]
|
|
8003eaa: 681b ldr r3, [r3, #0]
|
|
8003eac: 689b ldr r3, [r3, #8]
|
|
8003eae: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
|
|
8003eb2: f423 6330 bic.w r3, r3, #2816 @ 0xb00
|
|
8003eb6: 697a ldr r2, [r7, #20]
|
|
8003eb8: 6812 ldr r2, [r2, #0]
|
|
8003eba: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8003ebc: 430b orrs r3, r1
|
|
8003ebe: 6093 str r3, [r2, #8]
|
|
|
|
/*-------------------------- USART PRESC Configuration -----------------------*/
|
|
/* Configure
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
8003ec0: 697b ldr r3, [r7, #20]
|
|
8003ec2: 681b ldr r3, [r3, #0]
|
|
8003ec4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003ec6: f023 010f bic.w r1, r3, #15
|
|
8003eca: 697b ldr r3, [r7, #20]
|
|
8003ecc: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8003ece: 697b ldr r3, [r7, #20]
|
|
8003ed0: 681b ldr r3, [r3, #0]
|
|
8003ed2: 430a orrs r2, r1
|
|
8003ed4: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8003ed6: 697b ldr r3, [r7, #20]
|
|
8003ed8: 681b ldr r3, [r3, #0]
|
|
8003eda: 4a91 ldr r2, [pc, #580] @ (8004120 <UART_SetConfig+0x2e4>)
|
|
8003edc: 4293 cmp r3, r2
|
|
8003ede: d125 bne.n 8003f2c <UART_SetConfig+0xf0>
|
|
8003ee0: 4b90 ldr r3, [pc, #576] @ (8004124 <UART_SetConfig+0x2e8>)
|
|
8003ee2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003ee6: f003 0303 and.w r3, r3, #3
|
|
8003eea: 2b03 cmp r3, #3
|
|
8003eec: d81a bhi.n 8003f24 <UART_SetConfig+0xe8>
|
|
8003eee: a201 add r2, pc, #4 @ (adr r2, 8003ef4 <UART_SetConfig+0xb8>)
|
|
8003ef0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8003ef4: 08003f05 .word 0x08003f05
|
|
8003ef8: 08003f15 .word 0x08003f15
|
|
8003efc: 08003f0d .word 0x08003f0d
|
|
8003f00: 08003f1d .word 0x08003f1d
|
|
8003f04: 2301 movs r3, #1
|
|
8003f06: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f0a: e0d6 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f0c: 2302 movs r3, #2
|
|
8003f0e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f12: e0d2 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f14: 2304 movs r3, #4
|
|
8003f16: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f1a: e0ce b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f1c: 2308 movs r3, #8
|
|
8003f1e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f22: e0ca b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f24: 2310 movs r3, #16
|
|
8003f26: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f2a: e0c6 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f2c: 697b ldr r3, [r7, #20]
|
|
8003f2e: 681b ldr r3, [r3, #0]
|
|
8003f30: 4a7d ldr r2, [pc, #500] @ (8004128 <UART_SetConfig+0x2ec>)
|
|
8003f32: 4293 cmp r3, r2
|
|
8003f34: d138 bne.n 8003fa8 <UART_SetConfig+0x16c>
|
|
8003f36: 4b7b ldr r3, [pc, #492] @ (8004124 <UART_SetConfig+0x2e8>)
|
|
8003f38: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003f3c: f003 030c and.w r3, r3, #12
|
|
8003f40: 2b0c cmp r3, #12
|
|
8003f42: d82d bhi.n 8003fa0 <UART_SetConfig+0x164>
|
|
8003f44: a201 add r2, pc, #4 @ (adr r2, 8003f4c <UART_SetConfig+0x110>)
|
|
8003f46: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8003f4a: bf00 nop
|
|
8003f4c: 08003f81 .word 0x08003f81
|
|
8003f50: 08003fa1 .word 0x08003fa1
|
|
8003f54: 08003fa1 .word 0x08003fa1
|
|
8003f58: 08003fa1 .word 0x08003fa1
|
|
8003f5c: 08003f91 .word 0x08003f91
|
|
8003f60: 08003fa1 .word 0x08003fa1
|
|
8003f64: 08003fa1 .word 0x08003fa1
|
|
8003f68: 08003fa1 .word 0x08003fa1
|
|
8003f6c: 08003f89 .word 0x08003f89
|
|
8003f70: 08003fa1 .word 0x08003fa1
|
|
8003f74: 08003fa1 .word 0x08003fa1
|
|
8003f78: 08003fa1 .word 0x08003fa1
|
|
8003f7c: 08003f99 .word 0x08003f99
|
|
8003f80: 2300 movs r3, #0
|
|
8003f82: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f86: e098 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f88: 2302 movs r3, #2
|
|
8003f8a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f8e: e094 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f90: 2304 movs r3, #4
|
|
8003f92: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f96: e090 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003f98: 2308 movs r3, #8
|
|
8003f9a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003f9e: e08c b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003fa0: 2310 movs r3, #16
|
|
8003fa2: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003fa6: e088 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003fa8: 697b ldr r3, [r7, #20]
|
|
8003faa: 681b ldr r3, [r3, #0]
|
|
8003fac: 4a5f ldr r2, [pc, #380] @ (800412c <UART_SetConfig+0x2f0>)
|
|
8003fae: 4293 cmp r3, r2
|
|
8003fb0: d125 bne.n 8003ffe <UART_SetConfig+0x1c2>
|
|
8003fb2: 4b5c ldr r3, [pc, #368] @ (8004124 <UART_SetConfig+0x2e8>)
|
|
8003fb4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8003fb8: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
8003fbc: 2b30 cmp r3, #48 @ 0x30
|
|
8003fbe: d016 beq.n 8003fee <UART_SetConfig+0x1b2>
|
|
8003fc0: 2b30 cmp r3, #48 @ 0x30
|
|
8003fc2: d818 bhi.n 8003ff6 <UART_SetConfig+0x1ba>
|
|
8003fc4: 2b20 cmp r3, #32
|
|
8003fc6: d00a beq.n 8003fde <UART_SetConfig+0x1a2>
|
|
8003fc8: 2b20 cmp r3, #32
|
|
8003fca: d814 bhi.n 8003ff6 <UART_SetConfig+0x1ba>
|
|
8003fcc: 2b00 cmp r3, #0
|
|
8003fce: d002 beq.n 8003fd6 <UART_SetConfig+0x19a>
|
|
8003fd0: 2b10 cmp r3, #16
|
|
8003fd2: d008 beq.n 8003fe6 <UART_SetConfig+0x1aa>
|
|
8003fd4: e00f b.n 8003ff6 <UART_SetConfig+0x1ba>
|
|
8003fd6: 2300 movs r3, #0
|
|
8003fd8: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003fdc: e06d b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003fde: 2302 movs r3, #2
|
|
8003fe0: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003fe4: e069 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003fe6: 2304 movs r3, #4
|
|
8003fe8: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003fec: e065 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003fee: 2308 movs r3, #8
|
|
8003ff0: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003ff4: e061 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003ff6: 2310 movs r3, #16
|
|
8003ff8: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8003ffc: e05d b.n 80040ba <UART_SetConfig+0x27e>
|
|
8003ffe: 697b ldr r3, [r7, #20]
|
|
8004000: 681b ldr r3, [r3, #0]
|
|
8004002: 4a4b ldr r2, [pc, #300] @ (8004130 <UART_SetConfig+0x2f4>)
|
|
8004004: 4293 cmp r3, r2
|
|
8004006: d125 bne.n 8004054 <UART_SetConfig+0x218>
|
|
8004008: 4b46 ldr r3, [pc, #280] @ (8004124 <UART_SetConfig+0x2e8>)
|
|
800400a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800400e: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
8004012: 2bc0 cmp r3, #192 @ 0xc0
|
|
8004014: d016 beq.n 8004044 <UART_SetConfig+0x208>
|
|
8004016: 2bc0 cmp r3, #192 @ 0xc0
|
|
8004018: d818 bhi.n 800404c <UART_SetConfig+0x210>
|
|
800401a: 2b80 cmp r3, #128 @ 0x80
|
|
800401c: d00a beq.n 8004034 <UART_SetConfig+0x1f8>
|
|
800401e: 2b80 cmp r3, #128 @ 0x80
|
|
8004020: d814 bhi.n 800404c <UART_SetConfig+0x210>
|
|
8004022: 2b00 cmp r3, #0
|
|
8004024: d002 beq.n 800402c <UART_SetConfig+0x1f0>
|
|
8004026: 2b40 cmp r3, #64 @ 0x40
|
|
8004028: d008 beq.n 800403c <UART_SetConfig+0x200>
|
|
800402a: e00f b.n 800404c <UART_SetConfig+0x210>
|
|
800402c: 2300 movs r3, #0
|
|
800402e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8004032: e042 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8004034: 2302 movs r3, #2
|
|
8004036: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800403a: e03e b.n 80040ba <UART_SetConfig+0x27e>
|
|
800403c: 2304 movs r3, #4
|
|
800403e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8004042: e03a b.n 80040ba <UART_SetConfig+0x27e>
|
|
8004044: 2308 movs r3, #8
|
|
8004046: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800404a: e036 b.n 80040ba <UART_SetConfig+0x27e>
|
|
800404c: 2310 movs r3, #16
|
|
800404e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8004052: e032 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8004054: 697b ldr r3, [r7, #20]
|
|
8004056: 681b ldr r3, [r3, #0]
|
|
8004058: 4a30 ldr r2, [pc, #192] @ (800411c <UART_SetConfig+0x2e0>)
|
|
800405a: 4293 cmp r3, r2
|
|
800405c: d12a bne.n 80040b4 <UART_SetConfig+0x278>
|
|
800405e: 4b31 ldr r3, [pc, #196] @ (8004124 <UART_SetConfig+0x2e8>)
|
|
8004060: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004064: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
8004068: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
800406c: d01a beq.n 80040a4 <UART_SetConfig+0x268>
|
|
800406e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
8004072: d81b bhi.n 80040ac <UART_SetConfig+0x270>
|
|
8004074: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8004078: d00c beq.n 8004094 <UART_SetConfig+0x258>
|
|
800407a: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
800407e: d815 bhi.n 80040ac <UART_SetConfig+0x270>
|
|
8004080: 2b00 cmp r3, #0
|
|
8004082: d003 beq.n 800408c <UART_SetConfig+0x250>
|
|
8004084: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8004088: d008 beq.n 800409c <UART_SetConfig+0x260>
|
|
800408a: e00f b.n 80040ac <UART_SetConfig+0x270>
|
|
800408c: 2300 movs r3, #0
|
|
800408e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8004092: e012 b.n 80040ba <UART_SetConfig+0x27e>
|
|
8004094: 2302 movs r3, #2
|
|
8004096: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800409a: e00e b.n 80040ba <UART_SetConfig+0x27e>
|
|
800409c: 2304 movs r3, #4
|
|
800409e: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80040a2: e00a b.n 80040ba <UART_SetConfig+0x27e>
|
|
80040a4: 2308 movs r3, #8
|
|
80040a6: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80040aa: e006 b.n 80040ba <UART_SetConfig+0x27e>
|
|
80040ac: 2310 movs r3, #16
|
|
80040ae: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80040b2: e002 b.n 80040ba <UART_SetConfig+0x27e>
|
|
80040b4: 2310 movs r3, #16
|
|
80040b6: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
80040ba: 697b ldr r3, [r7, #20]
|
|
80040bc: 681b ldr r3, [r3, #0]
|
|
80040be: 4a17 ldr r2, [pc, #92] @ (800411c <UART_SetConfig+0x2e0>)
|
|
80040c0: 4293 cmp r3, r2
|
|
80040c2: f040 80a8 bne.w 8004216 <UART_SetConfig+0x3da>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
80040c6: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
80040ca: 2b08 cmp r3, #8
|
|
80040cc: d834 bhi.n 8004138 <UART_SetConfig+0x2fc>
|
|
80040ce: a201 add r2, pc, #4 @ (adr r2, 80040d4 <UART_SetConfig+0x298>)
|
|
80040d0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80040d4: 080040f9 .word 0x080040f9
|
|
80040d8: 08004139 .word 0x08004139
|
|
80040dc: 08004101 .word 0x08004101
|
|
80040e0: 08004139 .word 0x08004139
|
|
80040e4: 08004107 .word 0x08004107
|
|
80040e8: 08004139 .word 0x08004139
|
|
80040ec: 08004139 .word 0x08004139
|
|
80040f0: 08004139 .word 0x08004139
|
|
80040f4: 0800410f .word 0x0800410f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80040f8: f7fe fcba bl 8002a70 <HAL_RCC_GetPCLK1Freq>
|
|
80040fc: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
80040fe: e021 b.n 8004144 <UART_SetConfig+0x308>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8004100: 4b0c ldr r3, [pc, #48] @ (8004134 <UART_SetConfig+0x2f8>)
|
|
8004102: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004104: e01e b.n 8004144 <UART_SetConfig+0x308>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8004106: f7fe fc45 bl 8002994 <HAL_RCC_GetSysClockFreq>
|
|
800410a: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
800410c: e01a b.n 8004144 <UART_SetConfig+0x308>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800410e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004112: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004114: e016 b.n 8004144 <UART_SetConfig+0x308>
|
|
8004116: bf00 nop
|
|
8004118: cfff69f3 .word 0xcfff69f3
|
|
800411c: 40008000 .word 0x40008000
|
|
8004120: 40013800 .word 0x40013800
|
|
8004124: 40021000 .word 0x40021000
|
|
8004128: 40004400 .word 0x40004400
|
|
800412c: 40004800 .word 0x40004800
|
|
8004130: 40004c00 .word 0x40004c00
|
|
8004134: 00f42400 .word 0x00f42400
|
|
default:
|
|
pclk = 0U;
|
|
8004138: 2300 movs r3, #0
|
|
800413a: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
800413c: 2301 movs r3, #1
|
|
800413e: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8004142: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
8004144: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004146: 2b00 cmp r3, #0
|
|
8004148: f000 812a beq.w 80043a0 <UART_SetConfig+0x564>
|
|
{
|
|
/* Compute clock after Prescaler */
|
|
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
|
|
800414c: 697b ldr r3, [r7, #20]
|
|
800414e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004150: 4a9e ldr r2, [pc, #632] @ (80043cc <UART_SetConfig+0x590>)
|
|
8004152: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8004156: 461a mov r2, r3
|
|
8004158: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800415a: fbb3 f3f2 udiv r3, r3, r2
|
|
800415e: 61bb str r3, [r7, #24]
|
|
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
|
|
8004160: 697b ldr r3, [r7, #20]
|
|
8004162: 685a ldr r2, [r3, #4]
|
|
8004164: 4613 mov r3, r2
|
|
8004166: 005b lsls r3, r3, #1
|
|
8004168: 4413 add r3, r2
|
|
800416a: 69ba ldr r2, [r7, #24]
|
|
800416c: 429a cmp r2, r3
|
|
800416e: d305 bcc.n 800417c <UART_SetConfig+0x340>
|
|
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
|
|
8004170: 697b ldr r3, [r7, #20]
|
|
8004172: 685b ldr r3, [r3, #4]
|
|
8004174: 031b lsls r3, r3, #12
|
|
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
|
|
8004176: 69ba ldr r2, [r7, #24]
|
|
8004178: 429a cmp r2, r3
|
|
800417a: d903 bls.n 8004184 <UART_SetConfig+0x348>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800417c: 2301 movs r3, #1
|
|
800417e: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8004182: e10d b.n 80043a0 <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
/* Check computed UsartDiv value is in allocated range
|
|
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8004184: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004186: 2200 movs r2, #0
|
|
8004188: 60bb str r3, [r7, #8]
|
|
800418a: 60fa str r2, [r7, #12]
|
|
800418c: 697b ldr r3, [r7, #20]
|
|
800418e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004190: 4a8e ldr r2, [pc, #568] @ (80043cc <UART_SetConfig+0x590>)
|
|
8004192: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8004196: b29b uxth r3, r3
|
|
8004198: 2200 movs r2, #0
|
|
800419a: 603b str r3, [r7, #0]
|
|
800419c: 607a str r2, [r7, #4]
|
|
800419e: e9d7 2300 ldrd r2, r3, [r7]
|
|
80041a2: e9d7 0102 ldrd r0, r1, [r7, #8]
|
|
80041a6: f7fc f837 bl 8000218 <__aeabi_uldivmod>
|
|
80041aa: 4602 mov r2, r0
|
|
80041ac: 460b mov r3, r1
|
|
80041ae: 4610 mov r0, r2
|
|
80041b0: 4619 mov r1, r3
|
|
80041b2: f04f 0200 mov.w r2, #0
|
|
80041b6: f04f 0300 mov.w r3, #0
|
|
80041ba: 020b lsls r3, r1, #8
|
|
80041bc: ea43 6310 orr.w r3, r3, r0, lsr #24
|
|
80041c0: 0202 lsls r2, r0, #8
|
|
80041c2: 6979 ldr r1, [r7, #20]
|
|
80041c4: 6849 ldr r1, [r1, #4]
|
|
80041c6: 0849 lsrs r1, r1, #1
|
|
80041c8: 2000 movs r0, #0
|
|
80041ca: 460c mov r4, r1
|
|
80041cc: 4605 mov r5, r0
|
|
80041ce: eb12 0804 adds.w r8, r2, r4
|
|
80041d2: eb43 0905 adc.w r9, r3, r5
|
|
80041d6: 697b ldr r3, [r7, #20]
|
|
80041d8: 685b ldr r3, [r3, #4]
|
|
80041da: 2200 movs r2, #0
|
|
80041dc: 469a mov sl, r3
|
|
80041de: 4693 mov fp, r2
|
|
80041e0: 4652 mov r2, sl
|
|
80041e2: 465b mov r3, fp
|
|
80041e4: 4640 mov r0, r8
|
|
80041e6: 4649 mov r1, r9
|
|
80041e8: f7fc f816 bl 8000218 <__aeabi_uldivmod>
|
|
80041ec: 4602 mov r2, r0
|
|
80041ee: 460b mov r3, r1
|
|
80041f0: 4613 mov r3, r2
|
|
80041f2: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
80041f4: 6a3b ldr r3, [r7, #32]
|
|
80041f6: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
80041fa: d308 bcc.n 800420e <UART_SetConfig+0x3d2>
|
|
80041fc: 6a3b ldr r3, [r7, #32]
|
|
80041fe: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8004202: d204 bcs.n 800420e <UART_SetConfig+0x3d2>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8004204: 697b ldr r3, [r7, #20]
|
|
8004206: 681b ldr r3, [r3, #0]
|
|
8004208: 6a3a ldr r2, [r7, #32]
|
|
800420a: 60da str r2, [r3, #12]
|
|
800420c: e0c8 b.n 80043a0 <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800420e: 2301 movs r3, #1
|
|
8004210: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8004214: e0c4 b.n 80043a0 <UART_SetConfig+0x564>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8004216: 697b ldr r3, [r7, #20]
|
|
8004218: 69db ldr r3, [r3, #28]
|
|
800421a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
800421e: d167 bne.n 80042f0 <UART_SetConfig+0x4b4>
|
|
{
|
|
switch (clocksource)
|
|
8004220: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
8004224: 2b08 cmp r3, #8
|
|
8004226: d828 bhi.n 800427a <UART_SetConfig+0x43e>
|
|
8004228: a201 add r2, pc, #4 @ (adr r2, 8004230 <UART_SetConfig+0x3f4>)
|
|
800422a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800422e: bf00 nop
|
|
8004230: 08004255 .word 0x08004255
|
|
8004234: 0800425d .word 0x0800425d
|
|
8004238: 08004265 .word 0x08004265
|
|
800423c: 0800427b .word 0x0800427b
|
|
8004240: 0800426b .word 0x0800426b
|
|
8004244: 0800427b .word 0x0800427b
|
|
8004248: 0800427b .word 0x0800427b
|
|
800424c: 0800427b .word 0x0800427b
|
|
8004250: 08004273 .word 0x08004273
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004254: f7fe fc0c bl 8002a70 <HAL_RCC_GetPCLK1Freq>
|
|
8004258: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
800425a: e014 b.n 8004286 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800425c: f7fe fc1e bl 8002a9c <HAL_RCC_GetPCLK2Freq>
|
|
8004260: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8004262: e010 b.n 8004286 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8004264: 4b5a ldr r3, [pc, #360] @ (80043d0 <UART_SetConfig+0x594>)
|
|
8004266: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004268: e00d b.n 8004286 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800426a: f7fe fb93 bl 8002994 <HAL_RCC_GetSysClockFreq>
|
|
800426e: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8004270: e009 b.n 8004286 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8004272: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004276: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004278: e005 b.n 8004286 <UART_SetConfig+0x44a>
|
|
default:
|
|
pclk = 0U;
|
|
800427a: 2300 movs r3, #0
|
|
800427c: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
800427e: 2301 movs r3, #1
|
|
8004280: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8004284: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
8004286: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004288: 2b00 cmp r3, #0
|
|
800428a: f000 8089 beq.w 80043a0 <UART_SetConfig+0x564>
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
800428e: 697b ldr r3, [r7, #20]
|
|
8004290: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004292: 4a4e ldr r2, [pc, #312] @ (80043cc <UART_SetConfig+0x590>)
|
|
8004294: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8004298: 461a mov r2, r3
|
|
800429a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800429c: fbb3 f3f2 udiv r3, r3, r2
|
|
80042a0: 005a lsls r2, r3, #1
|
|
80042a2: 697b ldr r3, [r7, #20]
|
|
80042a4: 685b ldr r3, [r3, #4]
|
|
80042a6: 085b lsrs r3, r3, #1
|
|
80042a8: 441a add r2, r3
|
|
80042aa: 697b ldr r3, [r7, #20]
|
|
80042ac: 685b ldr r3, [r3, #4]
|
|
80042ae: fbb2 f3f3 udiv r3, r2, r3
|
|
80042b2: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
80042b4: 6a3b ldr r3, [r7, #32]
|
|
80042b6: 2b0f cmp r3, #15
|
|
80042b8: d916 bls.n 80042e8 <UART_SetConfig+0x4ac>
|
|
80042ba: 6a3b ldr r3, [r7, #32]
|
|
80042bc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
80042c0: d212 bcs.n 80042e8 <UART_SetConfig+0x4ac>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
80042c2: 6a3b ldr r3, [r7, #32]
|
|
80042c4: b29b uxth r3, r3
|
|
80042c6: f023 030f bic.w r3, r3, #15
|
|
80042ca: 83fb strh r3, [r7, #30]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
80042cc: 6a3b ldr r3, [r7, #32]
|
|
80042ce: 085b lsrs r3, r3, #1
|
|
80042d0: b29b uxth r3, r3
|
|
80042d2: f003 0307 and.w r3, r3, #7
|
|
80042d6: b29a uxth r2, r3
|
|
80042d8: 8bfb ldrh r3, [r7, #30]
|
|
80042da: 4313 orrs r3, r2
|
|
80042dc: 83fb strh r3, [r7, #30]
|
|
huart->Instance->BRR = brrtemp;
|
|
80042de: 697b ldr r3, [r7, #20]
|
|
80042e0: 681b ldr r3, [r3, #0]
|
|
80042e2: 8bfa ldrh r2, [r7, #30]
|
|
80042e4: 60da str r2, [r3, #12]
|
|
80042e6: e05b b.n 80043a0 <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
80042e8: 2301 movs r3, #1
|
|
80042ea: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
80042ee: e057 b.n 80043a0 <UART_SetConfig+0x564>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
80042f0: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
80042f4: 2b08 cmp r3, #8
|
|
80042f6: d828 bhi.n 800434a <UART_SetConfig+0x50e>
|
|
80042f8: a201 add r2, pc, #4 @ (adr r2, 8004300 <UART_SetConfig+0x4c4>)
|
|
80042fa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80042fe: bf00 nop
|
|
8004300: 08004325 .word 0x08004325
|
|
8004304: 0800432d .word 0x0800432d
|
|
8004308: 08004335 .word 0x08004335
|
|
800430c: 0800434b .word 0x0800434b
|
|
8004310: 0800433b .word 0x0800433b
|
|
8004314: 0800434b .word 0x0800434b
|
|
8004318: 0800434b .word 0x0800434b
|
|
800431c: 0800434b .word 0x0800434b
|
|
8004320: 08004343 .word 0x08004343
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004324: f7fe fba4 bl 8002a70 <HAL_RCC_GetPCLK1Freq>
|
|
8004328: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
800432a: e014 b.n 8004356 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800432c: f7fe fbb6 bl 8002a9c <HAL_RCC_GetPCLK2Freq>
|
|
8004330: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8004332: e010 b.n 8004356 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8004334: 4b26 ldr r3, [pc, #152] @ (80043d0 <UART_SetConfig+0x594>)
|
|
8004336: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004338: e00d b.n 8004356 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800433a: f7fe fb2b bl 8002994 <HAL_RCC_GetSysClockFreq>
|
|
800433e: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8004340: e009 b.n 8004356 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8004342: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8004346: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8004348: e005 b.n 8004356 <UART_SetConfig+0x51a>
|
|
default:
|
|
pclk = 0U;
|
|
800434a: 2300 movs r3, #0
|
|
800434c: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
800434e: 2301 movs r3, #1
|
|
8004350: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8004354: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8004356: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004358: 2b00 cmp r3, #0
|
|
800435a: d021 beq.n 80043a0 <UART_SetConfig+0x564>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
800435c: 697b ldr r3, [r7, #20]
|
|
800435e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004360: 4a1a ldr r2, [pc, #104] @ (80043cc <UART_SetConfig+0x590>)
|
|
8004362: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8004366: 461a mov r2, r3
|
|
8004368: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800436a: fbb3 f2f2 udiv r2, r3, r2
|
|
800436e: 697b ldr r3, [r7, #20]
|
|
8004370: 685b ldr r3, [r3, #4]
|
|
8004372: 085b lsrs r3, r3, #1
|
|
8004374: 441a add r2, r3
|
|
8004376: 697b ldr r3, [r7, #20]
|
|
8004378: 685b ldr r3, [r3, #4]
|
|
800437a: fbb2 f3f3 udiv r3, r2, r3
|
|
800437e: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8004380: 6a3b ldr r3, [r7, #32]
|
|
8004382: 2b0f cmp r3, #15
|
|
8004384: d909 bls.n 800439a <UART_SetConfig+0x55e>
|
|
8004386: 6a3b ldr r3, [r7, #32]
|
|
8004388: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
800438c: d205 bcs.n 800439a <UART_SetConfig+0x55e>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
800438e: 6a3b ldr r3, [r7, #32]
|
|
8004390: b29a uxth r2, r3
|
|
8004392: 697b ldr r3, [r7, #20]
|
|
8004394: 681b ldr r3, [r3, #0]
|
|
8004396: 60da str r2, [r3, #12]
|
|
8004398: e002 b.n 80043a0 <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800439a: 2301 movs r3, #1
|
|
800439c: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Initialize the number of data to process during RX/TX ISR execution */
|
|
huart->NbTxDataToProcess = 1;
|
|
80043a0: 697b ldr r3, [r7, #20]
|
|
80043a2: 2201 movs r2, #1
|
|
80043a4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = 1;
|
|
80043a8: 697b ldr r3, [r7, #20]
|
|
80043aa: 2201 movs r2, #1
|
|
80043ac: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
80043b0: 697b ldr r3, [r7, #20]
|
|
80043b2: 2200 movs r2, #0
|
|
80043b4: 675a str r2, [r3, #116] @ 0x74
|
|
huart->TxISR = NULL;
|
|
80043b6: 697b ldr r3, [r7, #20]
|
|
80043b8: 2200 movs r2, #0
|
|
80043ba: 679a str r2, [r3, #120] @ 0x78
|
|
|
|
return ret;
|
|
80043bc: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
80043c0: 4618 mov r0, r3
|
|
80043c2: 3730 adds r7, #48 @ 0x30
|
|
80043c4: 46bd mov sp, r7
|
|
80043c6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
80043ca: bf00 nop
|
|
80043cc: 08005ad8 .word 0x08005ad8
|
|
80043d0: 00f42400 .word 0x00f42400
|
|
|
|
080043d4 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
80043d4: b480 push {r7}
|
|
80043d6: b083 sub sp, #12
|
|
80043d8: af00 add r7, sp, #0
|
|
80043da: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
80043dc: 687b ldr r3, [r7, #4]
|
|
80043de: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80043e0: f003 0308 and.w r3, r3, #8
|
|
80043e4: 2b00 cmp r3, #0
|
|
80043e6: d00a beq.n 80043fe <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
80043e8: 687b ldr r3, [r7, #4]
|
|
80043ea: 681b ldr r3, [r3, #0]
|
|
80043ec: 685b ldr r3, [r3, #4]
|
|
80043ee: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
80043f2: 687b ldr r3, [r7, #4]
|
|
80043f4: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
80043f6: 687b ldr r3, [r7, #4]
|
|
80043f8: 681b ldr r3, [r3, #0]
|
|
80043fa: 430a orrs r2, r1
|
|
80043fc: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
80043fe: 687b ldr r3, [r7, #4]
|
|
8004400: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004402: f003 0301 and.w r3, r3, #1
|
|
8004406: 2b00 cmp r3, #0
|
|
8004408: d00a beq.n 8004420 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
800440a: 687b ldr r3, [r7, #4]
|
|
800440c: 681b ldr r3, [r3, #0]
|
|
800440e: 685b ldr r3, [r3, #4]
|
|
8004410: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8004414: 687b ldr r3, [r7, #4]
|
|
8004416: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8004418: 687b ldr r3, [r7, #4]
|
|
800441a: 681b ldr r3, [r3, #0]
|
|
800441c: 430a orrs r2, r1
|
|
800441e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8004420: 687b ldr r3, [r7, #4]
|
|
8004422: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004424: f003 0302 and.w r3, r3, #2
|
|
8004428: 2b00 cmp r3, #0
|
|
800442a: d00a beq.n 8004442 <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
800442c: 687b ldr r3, [r7, #4]
|
|
800442e: 681b ldr r3, [r3, #0]
|
|
8004430: 685b ldr r3, [r3, #4]
|
|
8004432: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8004436: 687b ldr r3, [r7, #4]
|
|
8004438: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
800443a: 687b ldr r3, [r7, #4]
|
|
800443c: 681b ldr r3, [r3, #0]
|
|
800443e: 430a orrs r2, r1
|
|
8004440: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8004442: 687b ldr r3, [r7, #4]
|
|
8004444: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004446: f003 0304 and.w r3, r3, #4
|
|
800444a: 2b00 cmp r3, #0
|
|
800444c: d00a beq.n 8004464 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
800444e: 687b ldr r3, [r7, #4]
|
|
8004450: 681b ldr r3, [r3, #0]
|
|
8004452: 685b ldr r3, [r3, #4]
|
|
8004454: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8004458: 687b ldr r3, [r7, #4]
|
|
800445a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800445c: 687b ldr r3, [r7, #4]
|
|
800445e: 681b ldr r3, [r3, #0]
|
|
8004460: 430a orrs r2, r1
|
|
8004462: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8004464: 687b ldr r3, [r7, #4]
|
|
8004466: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004468: f003 0310 and.w r3, r3, #16
|
|
800446c: 2b00 cmp r3, #0
|
|
800446e: d00a beq.n 8004486 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8004470: 687b ldr r3, [r7, #4]
|
|
8004472: 681b ldr r3, [r3, #0]
|
|
8004474: 689b ldr r3, [r3, #8]
|
|
8004476: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
800447a: 687b ldr r3, [r7, #4]
|
|
800447c: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
800447e: 687b ldr r3, [r7, #4]
|
|
8004480: 681b ldr r3, [r3, #0]
|
|
8004482: 430a orrs r2, r1
|
|
8004484: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8004486: 687b ldr r3, [r7, #4]
|
|
8004488: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800448a: f003 0320 and.w r3, r3, #32
|
|
800448e: 2b00 cmp r3, #0
|
|
8004490: d00a beq.n 80044a8 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8004492: 687b ldr r3, [r7, #4]
|
|
8004494: 681b ldr r3, [r3, #0]
|
|
8004496: 689b ldr r3, [r3, #8]
|
|
8004498: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
800449c: 687b ldr r3, [r7, #4]
|
|
800449e: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80044a0: 687b ldr r3, [r7, #4]
|
|
80044a2: 681b ldr r3, [r3, #0]
|
|
80044a4: 430a orrs r2, r1
|
|
80044a6: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
80044a8: 687b ldr r3, [r7, #4]
|
|
80044aa: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80044ac: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80044b0: 2b00 cmp r3, #0
|
|
80044b2: d01a beq.n 80044ea <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
80044b4: 687b ldr r3, [r7, #4]
|
|
80044b6: 681b ldr r3, [r3, #0]
|
|
80044b8: 685b ldr r3, [r3, #4]
|
|
80044ba: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
80044be: 687b ldr r3, [r7, #4]
|
|
80044c0: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
80044c2: 687b ldr r3, [r7, #4]
|
|
80044c4: 681b ldr r3, [r3, #0]
|
|
80044c6: 430a orrs r2, r1
|
|
80044c8: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
80044ca: 687b ldr r3, [r7, #4]
|
|
80044cc: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80044ce: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80044d2: d10a bne.n 80044ea <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
80044d4: 687b ldr r3, [r7, #4]
|
|
80044d6: 681b ldr r3, [r3, #0]
|
|
80044d8: 685b ldr r3, [r3, #4]
|
|
80044da: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
80044de: 687b ldr r3, [r7, #4]
|
|
80044e0: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
80044e2: 687b ldr r3, [r7, #4]
|
|
80044e4: 681b ldr r3, [r3, #0]
|
|
80044e6: 430a orrs r2, r1
|
|
80044e8: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
80044ea: 687b ldr r3, [r7, #4]
|
|
80044ec: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80044ee: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80044f2: 2b00 cmp r3, #0
|
|
80044f4: d00a beq.n 800450c <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
80044f6: 687b ldr r3, [r7, #4]
|
|
80044f8: 681b ldr r3, [r3, #0]
|
|
80044fa: 685b ldr r3, [r3, #4]
|
|
80044fc: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8004500: 687b ldr r3, [r7, #4]
|
|
8004502: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8004504: 687b ldr r3, [r7, #4]
|
|
8004506: 681b ldr r3, [r3, #0]
|
|
8004508: 430a orrs r2, r1
|
|
800450a: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
800450c: bf00 nop
|
|
800450e: 370c adds r7, #12
|
|
8004510: 46bd mov sp, r7
|
|
8004512: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004516: 4770 bx lr
|
|
|
|
08004518 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8004518: b580 push {r7, lr}
|
|
800451a: b098 sub sp, #96 @ 0x60
|
|
800451c: af02 add r7, sp, #8
|
|
800451e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004520: 687b ldr r3, [r7, #4]
|
|
8004522: 2200 movs r2, #0
|
|
8004524: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8004528: f7fd f9ae bl 8001888 <HAL_GetTick>
|
|
800452c: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
800452e: 687b ldr r3, [r7, #4]
|
|
8004530: 681b ldr r3, [r3, #0]
|
|
8004532: 681b ldr r3, [r3, #0]
|
|
8004534: f003 0308 and.w r3, r3, #8
|
|
8004538: 2b08 cmp r3, #8
|
|
800453a: d12f bne.n 800459c <UART_CheckIdleState+0x84>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
800453c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8004540: 9300 str r3, [sp, #0]
|
|
8004542: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8004544: 2200 movs r2, #0
|
|
8004546: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
800454a: 6878 ldr r0, [r7, #4]
|
|
800454c: f000 f88e bl 800466c <UART_WaitOnFlagUntilTimeout>
|
|
8004550: 4603 mov r3, r0
|
|
8004552: 2b00 cmp r3, #0
|
|
8004554: d022 beq.n 800459c <UART_CheckIdleState+0x84>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
8004556: 687b ldr r3, [r7, #4]
|
|
8004558: 681b ldr r3, [r3, #0]
|
|
800455a: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800455c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800455e: e853 3f00 ldrex r3, [r3]
|
|
8004562: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8004564: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8004566: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
800456a: 653b str r3, [r7, #80] @ 0x50
|
|
800456c: 687b ldr r3, [r7, #4]
|
|
800456e: 681b ldr r3, [r3, #0]
|
|
8004570: 461a mov r2, r3
|
|
8004572: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8004574: 647b str r3, [r7, #68] @ 0x44
|
|
8004576: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004578: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
800457a: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800457c: e841 2300 strex r3, r2, [r1]
|
|
8004580: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8004582: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8004584: 2b00 cmp r3, #0
|
|
8004586: d1e6 bne.n 8004556 <UART_CheckIdleState+0x3e>
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004588: 687b ldr r3, [r7, #4]
|
|
800458a: 2220 movs r2, #32
|
|
800458c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8004590: 687b ldr r3, [r7, #4]
|
|
8004592: 2200 movs r2, #0
|
|
8004594: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8004598: 2303 movs r3, #3
|
|
800459a: e063 b.n 8004664 <UART_CheckIdleState+0x14c>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
800459c: 687b ldr r3, [r7, #4]
|
|
800459e: 681b ldr r3, [r3, #0]
|
|
80045a0: 681b ldr r3, [r3, #0]
|
|
80045a2: f003 0304 and.w r3, r3, #4
|
|
80045a6: 2b04 cmp r3, #4
|
|
80045a8: d149 bne.n 800463e <UART_CheckIdleState+0x126>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
80045aa: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
80045ae: 9300 str r3, [sp, #0]
|
|
80045b0: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80045b2: 2200 movs r2, #0
|
|
80045b4: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
80045b8: 6878 ldr r0, [r7, #4]
|
|
80045ba: f000 f857 bl 800466c <UART_WaitOnFlagUntilTimeout>
|
|
80045be: 4603 mov r3, r0
|
|
80045c0: 2b00 cmp r3, #0
|
|
80045c2: d03c beq.n 800463e <UART_CheckIdleState+0x126>
|
|
{
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
80045c4: 687b ldr r3, [r7, #4]
|
|
80045c6: 681b ldr r3, [r3, #0]
|
|
80045c8: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80045ca: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80045cc: e853 3f00 ldrex r3, [r3]
|
|
80045d0: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80045d2: 6a3b ldr r3, [r7, #32]
|
|
80045d4: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80045d8: 64fb str r3, [r7, #76] @ 0x4c
|
|
80045da: 687b ldr r3, [r7, #4]
|
|
80045dc: 681b ldr r3, [r3, #0]
|
|
80045de: 461a mov r2, r3
|
|
80045e0: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80045e2: 633b str r3, [r7, #48] @ 0x30
|
|
80045e4: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80045e6: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80045e8: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80045ea: e841 2300 strex r3, r2, [r1]
|
|
80045ee: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80045f0: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80045f2: 2b00 cmp r3, #0
|
|
80045f4: d1e6 bne.n 80045c4 <UART_CheckIdleState+0xac>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80045f6: 687b ldr r3, [r7, #4]
|
|
80045f8: 681b ldr r3, [r3, #0]
|
|
80045fa: 3308 adds r3, #8
|
|
80045fc: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80045fe: 693b ldr r3, [r7, #16]
|
|
8004600: e853 3f00 ldrex r3, [r3]
|
|
8004604: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8004606: 68fb ldr r3, [r7, #12]
|
|
8004608: f023 0301 bic.w r3, r3, #1
|
|
800460c: 64bb str r3, [r7, #72] @ 0x48
|
|
800460e: 687b ldr r3, [r7, #4]
|
|
8004610: 681b ldr r3, [r3, #0]
|
|
8004612: 3308 adds r3, #8
|
|
8004614: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8004616: 61fa str r2, [r7, #28]
|
|
8004618: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800461a: 69b9 ldr r1, [r7, #24]
|
|
800461c: 69fa ldr r2, [r7, #28]
|
|
800461e: e841 2300 strex r3, r2, [r1]
|
|
8004622: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8004624: 697b ldr r3, [r7, #20]
|
|
8004626: 2b00 cmp r3, #0
|
|
8004628: d1e5 bne.n 80045f6 <UART_CheckIdleState+0xde>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800462a: 687b ldr r3, [r7, #4]
|
|
800462c: 2220 movs r2, #32
|
|
800462e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8004632: 687b ldr r3, [r7, #4]
|
|
8004634: 2200 movs r2, #0
|
|
8004636: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
800463a: 2303 movs r3, #3
|
|
800463c: e012 b.n 8004664 <UART_CheckIdleState+0x14c>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800463e: 687b ldr r3, [r7, #4]
|
|
8004640: 2220 movs r2, #32
|
|
8004642: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004646: 687b ldr r3, [r7, #4]
|
|
8004648: 2220 movs r2, #32
|
|
800464a: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800464e: 687b ldr r3, [r7, #4]
|
|
8004650: 2200 movs r2, #0
|
|
8004652: 66da str r2, [r3, #108] @ 0x6c
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004654: 687b ldr r3, [r7, #4]
|
|
8004656: 2200 movs r2, #0
|
|
8004658: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800465a: 687b ldr r3, [r7, #4]
|
|
800465c: 2200 movs r2, #0
|
|
800465e: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
8004662: 2300 movs r3, #0
|
|
}
|
|
8004664: 4618 mov r0, r3
|
|
8004666: 3758 adds r7, #88 @ 0x58
|
|
8004668: 46bd mov sp, r7
|
|
800466a: bd80 pop {r7, pc}
|
|
|
|
0800466c <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
800466c: b580 push {r7, lr}
|
|
800466e: b084 sub sp, #16
|
|
8004670: af00 add r7, sp, #0
|
|
8004672: 60f8 str r0, [r7, #12]
|
|
8004674: 60b9 str r1, [r7, #8]
|
|
8004676: 603b str r3, [r7, #0]
|
|
8004678: 4613 mov r3, r2
|
|
800467a: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800467c: e04f b.n 800471e <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800467e: 69bb ldr r3, [r7, #24]
|
|
8004680: f1b3 3fff cmp.w r3, #4294967295
|
|
8004684: d04b beq.n 800471e <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004686: f7fd f8ff bl 8001888 <HAL_GetTick>
|
|
800468a: 4602 mov r2, r0
|
|
800468c: 683b ldr r3, [r7, #0]
|
|
800468e: 1ad3 subs r3, r2, r3
|
|
8004690: 69ba ldr r2, [r7, #24]
|
|
8004692: 429a cmp r2, r3
|
|
8004694: d302 bcc.n 800469c <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8004696: 69bb ldr r3, [r7, #24]
|
|
8004698: 2b00 cmp r3, #0
|
|
800469a: d101 bne.n 80046a0 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
800469c: 2303 movs r3, #3
|
|
800469e: e04e b.n 800473e <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
80046a0: 68fb ldr r3, [r7, #12]
|
|
80046a2: 681b ldr r3, [r3, #0]
|
|
80046a4: 681b ldr r3, [r3, #0]
|
|
80046a6: f003 0304 and.w r3, r3, #4
|
|
80046aa: 2b00 cmp r3, #0
|
|
80046ac: d037 beq.n 800471e <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
80046ae: 68bb ldr r3, [r7, #8]
|
|
80046b0: 2b80 cmp r3, #128 @ 0x80
|
|
80046b2: d034 beq.n 800471e <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
80046b4: 68bb ldr r3, [r7, #8]
|
|
80046b6: 2b40 cmp r3, #64 @ 0x40
|
|
80046b8: d031 beq.n 800471e <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
80046ba: 68fb ldr r3, [r7, #12]
|
|
80046bc: 681b ldr r3, [r3, #0]
|
|
80046be: 69db ldr r3, [r3, #28]
|
|
80046c0: f003 0308 and.w r3, r3, #8
|
|
80046c4: 2b08 cmp r3, #8
|
|
80046c6: d110 bne.n 80046ea <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
80046c8: 68fb ldr r3, [r7, #12]
|
|
80046ca: 681b ldr r3, [r3, #0]
|
|
80046cc: 2208 movs r2, #8
|
|
80046ce: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
80046d0: 68f8 ldr r0, [r7, #12]
|
|
80046d2: f000 f95b bl 800498c <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
80046d6: 68fb ldr r3, [r7, #12]
|
|
80046d8: 2208 movs r2, #8
|
|
80046da: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80046de: 68fb ldr r3, [r7, #12]
|
|
80046e0: 2200 movs r2, #0
|
|
80046e2: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_ERROR;
|
|
80046e6: 2301 movs r3, #1
|
|
80046e8: e029 b.n 800473e <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
80046ea: 68fb ldr r3, [r7, #12]
|
|
80046ec: 681b ldr r3, [r3, #0]
|
|
80046ee: 69db ldr r3, [r3, #28]
|
|
80046f0: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80046f4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80046f8: d111 bne.n 800471e <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
80046fa: 68fb ldr r3, [r7, #12]
|
|
80046fc: 681b ldr r3, [r3, #0]
|
|
80046fe: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8004702: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8004704: 68f8 ldr r0, [r7, #12]
|
|
8004706: f000 f941 bl 800498c <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
800470a: 68fb ldr r3, [r7, #12]
|
|
800470c: 2220 movs r2, #32
|
|
800470e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8004712: 68fb ldr r3, [r7, #12]
|
|
8004714: 2200 movs r2, #0
|
|
8004716: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_TIMEOUT;
|
|
800471a: 2303 movs r3, #3
|
|
800471c: e00f b.n 800473e <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800471e: 68fb ldr r3, [r7, #12]
|
|
8004720: 681b ldr r3, [r3, #0]
|
|
8004722: 69da ldr r2, [r3, #28]
|
|
8004724: 68bb ldr r3, [r7, #8]
|
|
8004726: 4013 ands r3, r2
|
|
8004728: 68ba ldr r2, [r7, #8]
|
|
800472a: 429a cmp r2, r3
|
|
800472c: bf0c ite eq
|
|
800472e: 2301 moveq r3, #1
|
|
8004730: 2300 movne r3, #0
|
|
8004732: b2db uxtb r3, r3
|
|
8004734: 461a mov r2, r3
|
|
8004736: 79fb ldrb r3, [r7, #7]
|
|
8004738: 429a cmp r2, r3
|
|
800473a: d0a0 beq.n 800467e <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800473c: 2300 movs r3, #0
|
|
}
|
|
800473e: 4618 mov r0, r3
|
|
8004740: 3710 adds r7, #16
|
|
8004742: 46bd mov sp, r7
|
|
8004744: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004748 <UART_Start_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8004748: b480 push {r7}
|
|
800474a: b0a3 sub sp, #140 @ 0x8c
|
|
800474c: af00 add r7, sp, #0
|
|
800474e: 60f8 str r0, [r7, #12]
|
|
8004750: 60b9 str r1, [r7, #8]
|
|
8004752: 4613 mov r3, r2
|
|
8004754: 80fb strh r3, [r7, #6]
|
|
huart->pRxBuffPtr = pData;
|
|
8004756: 68fb ldr r3, [r7, #12]
|
|
8004758: 68ba ldr r2, [r7, #8]
|
|
800475a: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferSize = Size;
|
|
800475c: 68fb ldr r3, [r7, #12]
|
|
800475e: 88fa ldrh r2, [r7, #6]
|
|
8004760: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
huart->RxXferCount = Size;
|
|
8004764: 68fb ldr r3, [r7, #12]
|
|
8004766: 88fa ldrh r2, [r7, #6]
|
|
8004768: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
huart->RxISR = NULL;
|
|
800476c: 68fb ldr r3, [r7, #12]
|
|
800476e: 2200 movs r2, #0
|
|
8004770: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
UART_MASK_COMPUTATION(huart);
|
|
8004772: 68fb ldr r3, [r7, #12]
|
|
8004774: 689b ldr r3, [r3, #8]
|
|
8004776: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800477a: d10e bne.n 800479a <UART_Start_Receive_IT+0x52>
|
|
800477c: 68fb ldr r3, [r7, #12]
|
|
800477e: 691b ldr r3, [r3, #16]
|
|
8004780: 2b00 cmp r3, #0
|
|
8004782: d105 bne.n 8004790 <UART_Start_Receive_IT+0x48>
|
|
8004784: 68fb ldr r3, [r7, #12]
|
|
8004786: f240 12ff movw r2, #511 @ 0x1ff
|
|
800478a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
800478e: e02d b.n 80047ec <UART_Start_Receive_IT+0xa4>
|
|
8004790: 68fb ldr r3, [r7, #12]
|
|
8004792: 22ff movs r2, #255 @ 0xff
|
|
8004794: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8004798: e028 b.n 80047ec <UART_Start_Receive_IT+0xa4>
|
|
800479a: 68fb ldr r3, [r7, #12]
|
|
800479c: 689b ldr r3, [r3, #8]
|
|
800479e: 2b00 cmp r3, #0
|
|
80047a0: d10d bne.n 80047be <UART_Start_Receive_IT+0x76>
|
|
80047a2: 68fb ldr r3, [r7, #12]
|
|
80047a4: 691b ldr r3, [r3, #16]
|
|
80047a6: 2b00 cmp r3, #0
|
|
80047a8: d104 bne.n 80047b4 <UART_Start_Receive_IT+0x6c>
|
|
80047aa: 68fb ldr r3, [r7, #12]
|
|
80047ac: 22ff movs r2, #255 @ 0xff
|
|
80047ae: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
80047b2: e01b b.n 80047ec <UART_Start_Receive_IT+0xa4>
|
|
80047b4: 68fb ldr r3, [r7, #12]
|
|
80047b6: 227f movs r2, #127 @ 0x7f
|
|
80047b8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
80047bc: e016 b.n 80047ec <UART_Start_Receive_IT+0xa4>
|
|
80047be: 68fb ldr r3, [r7, #12]
|
|
80047c0: 689b ldr r3, [r3, #8]
|
|
80047c2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
80047c6: d10d bne.n 80047e4 <UART_Start_Receive_IT+0x9c>
|
|
80047c8: 68fb ldr r3, [r7, #12]
|
|
80047ca: 691b ldr r3, [r3, #16]
|
|
80047cc: 2b00 cmp r3, #0
|
|
80047ce: d104 bne.n 80047da <UART_Start_Receive_IT+0x92>
|
|
80047d0: 68fb ldr r3, [r7, #12]
|
|
80047d2: 227f movs r2, #127 @ 0x7f
|
|
80047d4: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
80047d8: e008 b.n 80047ec <UART_Start_Receive_IT+0xa4>
|
|
80047da: 68fb ldr r3, [r7, #12]
|
|
80047dc: 223f movs r2, #63 @ 0x3f
|
|
80047de: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
80047e2: e003 b.n 80047ec <UART_Start_Receive_IT+0xa4>
|
|
80047e4: 68fb ldr r3, [r7, #12]
|
|
80047e6: 2200 movs r2, #0
|
|
80047e8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80047ec: 68fb ldr r3, [r7, #12]
|
|
80047ee: 2200 movs r2, #0
|
|
80047f0: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
80047f4: 68fb ldr r3, [r7, #12]
|
|
80047f6: 2222 movs r2, #34 @ 0x22
|
|
80047f8: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80047fc: 68fb ldr r3, [r7, #12]
|
|
80047fe: 681b ldr r3, [r3, #0]
|
|
8004800: 3308 adds r3, #8
|
|
8004802: 667b str r3, [r7, #100] @ 0x64
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004804: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8004806: e853 3f00 ldrex r3, [r3]
|
|
800480a: 663b str r3, [r7, #96] @ 0x60
|
|
return(result);
|
|
800480c: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800480e: f043 0301 orr.w r3, r3, #1
|
|
8004812: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8004816: 68fb ldr r3, [r7, #12]
|
|
8004818: 681b ldr r3, [r3, #0]
|
|
800481a: 3308 adds r3, #8
|
|
800481c: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
|
|
8004820: 673a str r2, [r7, #112] @ 0x70
|
|
8004822: 66fb str r3, [r7, #108] @ 0x6c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004824: 6ef9 ldr r1, [r7, #108] @ 0x6c
|
|
8004826: 6f3a ldr r2, [r7, #112] @ 0x70
|
|
8004828: e841 2300 strex r3, r2, [r1]
|
|
800482c: 66bb str r3, [r7, #104] @ 0x68
|
|
return(result);
|
|
800482e: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8004830: 2b00 cmp r3, #0
|
|
8004832: d1e3 bne.n 80047fc <UART_Start_Receive_IT+0xb4>
|
|
|
|
/* Configure Rx interrupt processing */
|
|
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
|
|
8004834: 68fb ldr r3, [r7, #12]
|
|
8004836: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8004838: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800483c: d14f bne.n 80048de <UART_Start_Receive_IT+0x196>
|
|
800483e: 68fb ldr r3, [r7, #12]
|
|
8004840: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8004844: 88fa ldrh r2, [r7, #6]
|
|
8004846: 429a cmp r2, r3
|
|
8004848: d349 bcc.n 80048de <UART_Start_Receive_IT+0x196>
|
|
{
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
800484a: 68fb ldr r3, [r7, #12]
|
|
800484c: 689b ldr r3, [r3, #8]
|
|
800484e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8004852: d107 bne.n 8004864 <UART_Start_Receive_IT+0x11c>
|
|
8004854: 68fb ldr r3, [r7, #12]
|
|
8004856: 691b ldr r3, [r3, #16]
|
|
8004858: 2b00 cmp r3, #0
|
|
800485a: d103 bne.n 8004864 <UART_Start_Receive_IT+0x11c>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
|
|
800485c: 68fb ldr r3, [r7, #12]
|
|
800485e: 4a47 ldr r2, [pc, #284] @ (800497c <UART_Start_Receive_IT+0x234>)
|
|
8004860: 675a str r2, [r3, #116] @ 0x74
|
|
8004862: e002 b.n 800486a <UART_Start_Receive_IT+0x122>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
|
|
8004864: 68fb ldr r3, [r7, #12]
|
|
8004866: 4a46 ldr r2, [pc, #280] @ (8004980 <UART_Start_Receive_IT+0x238>)
|
|
8004868: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
800486a: 68fb ldr r3, [r7, #12]
|
|
800486c: 691b ldr r3, [r3, #16]
|
|
800486e: 2b00 cmp r3, #0
|
|
8004870: d01a beq.n 80048a8 <UART_Start_Receive_IT+0x160>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8004872: 68fb ldr r3, [r7, #12]
|
|
8004874: 681b ldr r3, [r3, #0]
|
|
8004876: 653b str r3, [r7, #80] @ 0x50
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004878: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800487a: e853 3f00 ldrex r3, [r3]
|
|
800487e: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
8004880: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8004882: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004886: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
800488a: 68fb ldr r3, [r7, #12]
|
|
800488c: 681b ldr r3, [r3, #0]
|
|
800488e: 461a mov r2, r3
|
|
8004890: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8004894: 65fb str r3, [r7, #92] @ 0x5c
|
|
8004896: 65ba str r2, [r7, #88] @ 0x58
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004898: 6db9 ldr r1, [r7, #88] @ 0x58
|
|
800489a: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
800489c: e841 2300 strex r3, r2, [r1]
|
|
80048a0: 657b str r3, [r7, #84] @ 0x54
|
|
return(result);
|
|
80048a2: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80048a4: 2b00 cmp r3, #0
|
|
80048a6: d1e4 bne.n 8004872 <UART_Start_Receive_IT+0x12a>
|
|
}
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
80048a8: 68fb ldr r3, [r7, #12]
|
|
80048aa: 681b ldr r3, [r3, #0]
|
|
80048ac: 3308 adds r3, #8
|
|
80048ae: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80048b0: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80048b2: e853 3f00 ldrex r3, [r3]
|
|
80048b6: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
80048b8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80048ba: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80048be: 67fb str r3, [r7, #124] @ 0x7c
|
|
80048c0: 68fb ldr r3, [r7, #12]
|
|
80048c2: 681b ldr r3, [r3, #0]
|
|
80048c4: 3308 adds r3, #8
|
|
80048c6: 6ffa ldr r2, [r7, #124] @ 0x7c
|
|
80048c8: 64ba str r2, [r7, #72] @ 0x48
|
|
80048ca: 647b str r3, [r7, #68] @ 0x44
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80048cc: 6c79 ldr r1, [r7, #68] @ 0x44
|
|
80048ce: 6cba ldr r2, [r7, #72] @ 0x48
|
|
80048d0: e841 2300 strex r3, r2, [r1]
|
|
80048d4: 643b str r3, [r7, #64] @ 0x40
|
|
return(result);
|
|
80048d6: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
80048d8: 2b00 cmp r3, #0
|
|
80048da: d1e5 bne.n 80048a8 <UART_Start_Receive_IT+0x160>
|
|
80048dc: e046 b.n 800496c <UART_Start_Receive_IT+0x224>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
80048de: 68fb ldr r3, [r7, #12]
|
|
80048e0: 689b ldr r3, [r3, #8]
|
|
80048e2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
80048e6: d107 bne.n 80048f8 <UART_Start_Receive_IT+0x1b0>
|
|
80048e8: 68fb ldr r3, [r7, #12]
|
|
80048ea: 691b ldr r3, [r3, #16]
|
|
80048ec: 2b00 cmp r3, #0
|
|
80048ee: d103 bne.n 80048f8 <UART_Start_Receive_IT+0x1b0>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
80048f0: 68fb ldr r3, [r7, #12]
|
|
80048f2: 4a24 ldr r2, [pc, #144] @ (8004984 <UART_Start_Receive_IT+0x23c>)
|
|
80048f4: 675a str r2, [r3, #116] @ 0x74
|
|
80048f6: e002 b.n 80048fe <UART_Start_Receive_IT+0x1b6>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
80048f8: 68fb ldr r3, [r7, #12]
|
|
80048fa: 4a23 ldr r2, [pc, #140] @ (8004988 <UART_Start_Receive_IT+0x240>)
|
|
80048fc: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
80048fe: 68fb ldr r3, [r7, #12]
|
|
8004900: 691b ldr r3, [r3, #16]
|
|
8004902: 2b00 cmp r3, #0
|
|
8004904: d019 beq.n 800493a <UART_Start_Receive_IT+0x1f2>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
|
|
8004906: 68fb ldr r3, [r7, #12]
|
|
8004908: 681b ldr r3, [r3, #0]
|
|
800490a: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800490c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800490e: e853 3f00 ldrex r3, [r3]
|
|
8004912: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8004914: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004916: f443 7390 orr.w r3, r3, #288 @ 0x120
|
|
800491a: 677b str r3, [r7, #116] @ 0x74
|
|
800491c: 68fb ldr r3, [r7, #12]
|
|
800491e: 681b ldr r3, [r3, #0]
|
|
8004920: 461a mov r2, r3
|
|
8004922: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8004924: 637b str r3, [r7, #52] @ 0x34
|
|
8004926: 633a str r2, [r7, #48] @ 0x30
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004928: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
800492a: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
800492c: e841 2300 strex r3, r2, [r1]
|
|
8004930: 62fb str r3, [r7, #44] @ 0x2c
|
|
return(result);
|
|
8004932: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8004934: 2b00 cmp r3, #0
|
|
8004936: d1e6 bne.n 8004906 <UART_Start_Receive_IT+0x1be>
|
|
8004938: e018 b.n 800496c <UART_Start_Receive_IT+0x224>
|
|
}
|
|
else
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
800493a: 68fb ldr r3, [r7, #12]
|
|
800493c: 681b ldr r3, [r3, #0]
|
|
800493e: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004940: 697b ldr r3, [r7, #20]
|
|
8004942: e853 3f00 ldrex r3, [r3]
|
|
8004946: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8004948: 693b ldr r3, [r7, #16]
|
|
800494a: f043 0320 orr.w r3, r3, #32
|
|
800494e: 67bb str r3, [r7, #120] @ 0x78
|
|
8004950: 68fb ldr r3, [r7, #12]
|
|
8004952: 681b ldr r3, [r3, #0]
|
|
8004954: 461a mov r2, r3
|
|
8004956: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8004958: 623b str r3, [r7, #32]
|
|
800495a: 61fa str r2, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800495c: 69f9 ldr r1, [r7, #28]
|
|
800495e: 6a3a ldr r2, [r7, #32]
|
|
8004960: e841 2300 strex r3, r2, [r1]
|
|
8004964: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8004966: 69bb ldr r3, [r7, #24]
|
|
8004968: 2b00 cmp r3, #0
|
|
800496a: d1e6 bne.n 800493a <UART_Start_Receive_IT+0x1f2>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800496c: 2300 movs r3, #0
|
|
}
|
|
800496e: 4618 mov r0, r3
|
|
8004970: 378c adds r7, #140 @ 0x8c
|
|
8004972: 46bd mov sp, r7
|
|
8004974: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004978: 4770 bx lr
|
|
800497a: bf00 nop
|
|
800497c: 080051a1 .word 0x080051a1
|
|
8004980: 08004e3d .word 0x08004e3d
|
|
8004984: 08004c85 .word 0x08004c85
|
|
8004988: 08004acd .word 0x08004acd
|
|
|
|
0800498c <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
800498c: b480 push {r7}
|
|
800498e: b095 sub sp, #84 @ 0x54
|
|
8004990: af00 add r7, sp, #0
|
|
8004992: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8004994: 687b ldr r3, [r7, #4]
|
|
8004996: 681b ldr r3, [r3, #0]
|
|
8004998: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800499a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800499c: e853 3f00 ldrex r3, [r3]
|
|
80049a0: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
80049a2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80049a4: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80049a8: 64fb str r3, [r7, #76] @ 0x4c
|
|
80049aa: 687b ldr r3, [r7, #4]
|
|
80049ac: 681b ldr r3, [r3, #0]
|
|
80049ae: 461a mov r2, r3
|
|
80049b0: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80049b2: 643b str r3, [r7, #64] @ 0x40
|
|
80049b4: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80049b6: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80049b8: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80049ba: e841 2300 strex r3, r2, [r1]
|
|
80049be: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
80049c0: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80049c2: 2b00 cmp r3, #0
|
|
80049c4: d1e6 bne.n 8004994 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
80049c6: 687b ldr r3, [r7, #4]
|
|
80049c8: 681b ldr r3, [r3, #0]
|
|
80049ca: 3308 adds r3, #8
|
|
80049cc: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80049ce: 6a3b ldr r3, [r7, #32]
|
|
80049d0: e853 3f00 ldrex r3, [r3]
|
|
80049d4: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80049d6: 69fb ldr r3, [r7, #28]
|
|
80049d8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80049dc: f023 0301 bic.w r3, r3, #1
|
|
80049e0: 64bb str r3, [r7, #72] @ 0x48
|
|
80049e2: 687b ldr r3, [r7, #4]
|
|
80049e4: 681b ldr r3, [r3, #0]
|
|
80049e6: 3308 adds r3, #8
|
|
80049e8: 6cba ldr r2, [r7, #72] @ 0x48
|
|
80049ea: 62fa str r2, [r7, #44] @ 0x2c
|
|
80049ec: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80049ee: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
80049f0: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80049f2: e841 2300 strex r3, r2, [r1]
|
|
80049f6: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
80049f8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80049fa: 2b00 cmp r3, #0
|
|
80049fc: d1e3 bne.n 80049c6 <UART_EndRxTransfer+0x3a>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80049fe: 687b ldr r3, [r7, #4]
|
|
8004a00: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8004a02: 2b01 cmp r3, #1
|
|
8004a04: d118 bne.n 8004a38 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004a06: 687b ldr r3, [r7, #4]
|
|
8004a08: 681b ldr r3, [r3, #0]
|
|
8004a0a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004a0c: 68fb ldr r3, [r7, #12]
|
|
8004a0e: e853 3f00 ldrex r3, [r3]
|
|
8004a12: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8004a14: 68bb ldr r3, [r7, #8]
|
|
8004a16: f023 0310 bic.w r3, r3, #16
|
|
8004a1a: 647b str r3, [r7, #68] @ 0x44
|
|
8004a1c: 687b ldr r3, [r7, #4]
|
|
8004a1e: 681b ldr r3, [r3, #0]
|
|
8004a20: 461a mov r2, r3
|
|
8004a22: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8004a24: 61bb str r3, [r7, #24]
|
|
8004a26: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004a28: 6979 ldr r1, [r7, #20]
|
|
8004a2a: 69ba ldr r2, [r7, #24]
|
|
8004a2c: e841 2300 strex r3, r2, [r1]
|
|
8004a30: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8004a32: 693b ldr r3, [r7, #16]
|
|
8004a34: 2b00 cmp r3, #0
|
|
8004a36: d1e6 bne.n 8004a06 <UART_EndRxTransfer+0x7a>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004a38: 687b ldr r3, [r7, #4]
|
|
8004a3a: 2220 movs r2, #32
|
|
8004a3c: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004a40: 687b ldr r3, [r7, #4]
|
|
8004a42: 2200 movs r2, #0
|
|
8004a44: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8004a46: 687b ldr r3, [r7, #4]
|
|
8004a48: 2200 movs r2, #0
|
|
8004a4a: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
8004a4c: bf00 nop
|
|
8004a4e: 3754 adds r7, #84 @ 0x54
|
|
8004a50: 46bd mov sp, r7
|
|
8004a52: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004a56: 4770 bx lr
|
|
|
|
08004a58 <UART_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8004a58: b580 push {r7, lr}
|
|
8004a5a: b084 sub sp, #16
|
|
8004a5c: af00 add r7, sp, #0
|
|
8004a5e: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
8004a60: 687b ldr r3, [r7, #4]
|
|
8004a62: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004a64: 60fb str r3, [r7, #12]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8004a66: 68f8 ldr r0, [r7, #12]
|
|
8004a68: f7ff f9d2 bl 8003e10 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8004a6c: bf00 nop
|
|
8004a6e: 3710 adds r7, #16
|
|
8004a70: 46bd mov sp, r7
|
|
8004a72: bd80 pop {r7, pc}
|
|
|
|
08004a74 <UART_EndTransmit_IT>:
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
8004a74: b580 push {r7, lr}
|
|
8004a76: b088 sub sp, #32
|
|
8004a78: af00 add r7, sp, #0
|
|
8004a7a: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8004a7c: 687b ldr r3, [r7, #4]
|
|
8004a7e: 681b ldr r3, [r3, #0]
|
|
8004a80: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004a82: 68fb ldr r3, [r7, #12]
|
|
8004a84: e853 3f00 ldrex r3, [r3]
|
|
8004a88: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8004a8a: 68bb ldr r3, [r7, #8]
|
|
8004a8c: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8004a90: 61fb str r3, [r7, #28]
|
|
8004a92: 687b ldr r3, [r7, #4]
|
|
8004a94: 681b ldr r3, [r3, #0]
|
|
8004a96: 461a mov r2, r3
|
|
8004a98: 69fb ldr r3, [r7, #28]
|
|
8004a9a: 61bb str r3, [r7, #24]
|
|
8004a9c: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004a9e: 6979 ldr r1, [r7, #20]
|
|
8004aa0: 69ba ldr r2, [r7, #24]
|
|
8004aa2: e841 2300 strex r3, r2, [r1]
|
|
8004aa6: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8004aa8: 693b ldr r3, [r7, #16]
|
|
8004aaa: 2b00 cmp r3, #0
|
|
8004aac: d1e6 bne.n 8004a7c <UART_EndTransmit_IT+0x8>
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004aae: 687b ldr r3, [r7, #4]
|
|
8004ab0: 2220 movs r2, #32
|
|
8004ab2: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
8004ab6: 687b ldr r3, [r7, #4]
|
|
8004ab8: 2200 movs r2, #0
|
|
8004aba: 679a str r2, [r3, #120] @ 0x78
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8004abc: 6878 ldr r0, [r7, #4]
|
|
8004abe: f7ff f99d bl 8003dfc <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8004ac2: bf00 nop
|
|
8004ac4: 3720 adds r7, #32
|
|
8004ac6: 46bd mov sp, r7
|
|
8004ac8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004acc <UART_RxISR_8BIT>:
|
|
* @brief RX interrupt handler for 7 or 8 bits data word length .
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8004acc: b580 push {r7, lr}
|
|
8004ace: b09c sub sp, #112 @ 0x70
|
|
8004ad0: af00 add r7, sp, #0
|
|
8004ad2: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
8004ad4: 687b ldr r3, [r7, #4]
|
|
8004ad6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
8004ada: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8004ade: 687b ldr r3, [r7, #4]
|
|
8004ae0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004ae4: 2b22 cmp r3, #34 @ 0x22
|
|
8004ae6: f040 80be bne.w 8004c66 <UART_RxISR_8BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
8004aea: 687b ldr r3, [r7, #4]
|
|
8004aec: 681b ldr r3, [r3, #0]
|
|
8004aee: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004af0: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
8004af4: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
8004af8: b2d9 uxtb r1, r3
|
|
8004afa: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
8004afe: b2da uxtb r2, r3
|
|
8004b00: 687b ldr r3, [r7, #4]
|
|
8004b02: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8004b04: 400a ands r2, r1
|
|
8004b06: b2d2 uxtb r2, r2
|
|
8004b08: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
8004b0a: 687b ldr r3, [r7, #4]
|
|
8004b0c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8004b0e: 1c5a adds r2, r3, #1
|
|
8004b10: 687b ldr r3, [r7, #4]
|
|
8004b12: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8004b14: 687b ldr r3, [r7, #4]
|
|
8004b16: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8004b1a: b29b uxth r3, r3
|
|
8004b1c: 3b01 subs r3, #1
|
|
8004b1e: b29a uxth r2, r3
|
|
8004b20: 687b ldr r3, [r7, #4]
|
|
8004b22: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8004b26: 687b ldr r3, [r7, #4]
|
|
8004b28: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8004b2c: b29b uxth r3, r3
|
|
8004b2e: 2b00 cmp r3, #0
|
|
8004b30: f040 80a1 bne.w 8004c76 <UART_RxISR_8BIT+0x1aa>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8004b34: 687b ldr r3, [r7, #4]
|
|
8004b36: 681b ldr r3, [r3, #0]
|
|
8004b38: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004b3a: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8004b3c: e853 3f00 ldrex r3, [r3]
|
|
8004b40: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8004b42: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8004b44: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8004b48: 66bb str r3, [r7, #104] @ 0x68
|
|
8004b4a: 687b ldr r3, [r7, #4]
|
|
8004b4c: 681b ldr r3, [r3, #0]
|
|
8004b4e: 461a mov r2, r3
|
|
8004b50: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8004b52: 65bb str r3, [r7, #88] @ 0x58
|
|
8004b54: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004b56: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8004b58: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8004b5a: e841 2300 strex r3, r2, [r1]
|
|
8004b5e: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8004b60: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8004b62: 2b00 cmp r3, #0
|
|
8004b64: d1e6 bne.n 8004b34 <UART_RxISR_8BIT+0x68>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8004b66: 687b ldr r3, [r7, #4]
|
|
8004b68: 681b ldr r3, [r3, #0]
|
|
8004b6a: 3308 adds r3, #8
|
|
8004b6c: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004b6e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8004b70: e853 3f00 ldrex r3, [r3]
|
|
8004b74: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8004b76: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8004b78: f023 0301 bic.w r3, r3, #1
|
|
8004b7c: 667b str r3, [r7, #100] @ 0x64
|
|
8004b7e: 687b ldr r3, [r7, #4]
|
|
8004b80: 681b ldr r3, [r3, #0]
|
|
8004b82: 3308 adds r3, #8
|
|
8004b84: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
8004b86: 647a str r2, [r7, #68] @ 0x44
|
|
8004b88: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004b8a: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8004b8c: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8004b8e: e841 2300 strex r3, r2, [r1]
|
|
8004b92: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8004b94: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8004b96: 2b00 cmp r3, #0
|
|
8004b98: d1e5 bne.n 8004b66 <UART_RxISR_8BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004b9a: 687b ldr r3, [r7, #4]
|
|
8004b9c: 2220 movs r2, #32
|
|
8004b9e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8004ba2: 687b ldr r3, [r7, #4]
|
|
8004ba4: 2200 movs r2, #0
|
|
8004ba6: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004ba8: 687b ldr r3, [r7, #4]
|
|
8004baa: 2200 movs r2, #0
|
|
8004bac: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8004bae: 687b ldr r3, [r7, #4]
|
|
8004bb0: 681b ldr r3, [r3, #0]
|
|
8004bb2: 4a33 ldr r2, [pc, #204] @ (8004c80 <UART_RxISR_8BIT+0x1b4>)
|
|
8004bb4: 4293 cmp r3, r2
|
|
8004bb6: d01f beq.n 8004bf8 <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8004bb8: 687b ldr r3, [r7, #4]
|
|
8004bba: 681b ldr r3, [r3, #0]
|
|
8004bbc: 685b ldr r3, [r3, #4]
|
|
8004bbe: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8004bc2: 2b00 cmp r3, #0
|
|
8004bc4: d018 beq.n 8004bf8 <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8004bc6: 687b ldr r3, [r7, #4]
|
|
8004bc8: 681b ldr r3, [r3, #0]
|
|
8004bca: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004bcc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004bce: e853 3f00 ldrex r3, [r3]
|
|
8004bd2: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8004bd4: 6a3b ldr r3, [r7, #32]
|
|
8004bd6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8004bda: 663b str r3, [r7, #96] @ 0x60
|
|
8004bdc: 687b ldr r3, [r7, #4]
|
|
8004bde: 681b ldr r3, [r3, #0]
|
|
8004be0: 461a mov r2, r3
|
|
8004be2: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8004be4: 633b str r3, [r7, #48] @ 0x30
|
|
8004be6: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004be8: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8004bea: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8004bec: e841 2300 strex r3, r2, [r1]
|
|
8004bf0: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8004bf2: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8004bf4: 2b00 cmp r3, #0
|
|
8004bf6: d1e6 bne.n 8004bc6 <UART_RxISR_8BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8004bf8: 687b ldr r3, [r7, #4]
|
|
8004bfa: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8004bfc: 2b01 cmp r3, #1
|
|
8004bfe: d12e bne.n 8004c5e <UART_RxISR_8BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004c00: 687b ldr r3, [r7, #4]
|
|
8004c02: 2200 movs r2, #0
|
|
8004c04: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004c06: 687b ldr r3, [r7, #4]
|
|
8004c08: 681b ldr r3, [r3, #0]
|
|
8004c0a: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004c0c: 693b ldr r3, [r7, #16]
|
|
8004c0e: e853 3f00 ldrex r3, [r3]
|
|
8004c12: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8004c14: 68fb ldr r3, [r7, #12]
|
|
8004c16: f023 0310 bic.w r3, r3, #16
|
|
8004c1a: 65fb str r3, [r7, #92] @ 0x5c
|
|
8004c1c: 687b ldr r3, [r7, #4]
|
|
8004c1e: 681b ldr r3, [r3, #0]
|
|
8004c20: 461a mov r2, r3
|
|
8004c22: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8004c24: 61fb str r3, [r7, #28]
|
|
8004c26: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004c28: 69b9 ldr r1, [r7, #24]
|
|
8004c2a: 69fa ldr r2, [r7, #28]
|
|
8004c2c: e841 2300 strex r3, r2, [r1]
|
|
8004c30: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8004c32: 697b ldr r3, [r7, #20]
|
|
8004c34: 2b00 cmp r3, #0
|
|
8004c36: d1e6 bne.n 8004c06 <UART_RxISR_8BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8004c38: 687b ldr r3, [r7, #4]
|
|
8004c3a: 681b ldr r3, [r3, #0]
|
|
8004c3c: 69db ldr r3, [r3, #28]
|
|
8004c3e: f003 0310 and.w r3, r3, #16
|
|
8004c42: 2b10 cmp r3, #16
|
|
8004c44: d103 bne.n 8004c4e <UART_RxISR_8BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8004c46: 687b ldr r3, [r7, #4]
|
|
8004c48: 681b ldr r3, [r3, #0]
|
|
8004c4a: 2210 movs r2, #16
|
|
8004c4c: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8004c4e: 687b ldr r3, [r7, #4]
|
|
8004c50: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8004c54: 4619 mov r1, r3
|
|
8004c56: 6878 ldr r0, [r7, #4]
|
|
8004c58: f7ff f8e4 bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8004c5c: e00b b.n 8004c76 <UART_RxISR_8BIT+0x1aa>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8004c5e: 6878 ldr r0, [r7, #4]
|
|
8004c60: f7fc f9d4 bl 800100c <HAL_UART_RxCpltCallback>
|
|
}
|
|
8004c64: e007 b.n 8004c76 <UART_RxISR_8BIT+0x1aa>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8004c66: 687b ldr r3, [r7, #4]
|
|
8004c68: 681b ldr r3, [r3, #0]
|
|
8004c6a: 699a ldr r2, [r3, #24]
|
|
8004c6c: 687b ldr r3, [r7, #4]
|
|
8004c6e: 681b ldr r3, [r3, #0]
|
|
8004c70: f042 0208 orr.w r2, r2, #8
|
|
8004c74: 619a str r2, [r3, #24]
|
|
}
|
|
8004c76: bf00 nop
|
|
8004c78: 3770 adds r7, #112 @ 0x70
|
|
8004c7a: 46bd mov sp, r7
|
|
8004c7c: bd80 pop {r7, pc}
|
|
8004c7e: bf00 nop
|
|
8004c80: 40008000 .word 0x40008000
|
|
|
|
08004c84 <UART_RxISR_16BIT>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8004c84: b580 push {r7, lr}
|
|
8004c86: b09c sub sp, #112 @ 0x70
|
|
8004c88: af00 add r7, sp, #0
|
|
8004c8a: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
8004c8c: 687b ldr r3, [r7, #4]
|
|
8004c8e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
8004c92: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8004c96: 687b ldr r3, [r7, #4]
|
|
8004c98: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004c9c: 2b22 cmp r3, #34 @ 0x22
|
|
8004c9e: f040 80be bne.w 8004e1e <UART_RxISR_16BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
8004ca2: 687b ldr r3, [r7, #4]
|
|
8004ca4: 681b ldr r3, [r3, #0]
|
|
8004ca6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004ca8: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
8004cac: 687b ldr r3, [r7, #4]
|
|
8004cae: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8004cb0: 66bb str r3, [r7, #104] @ 0x68
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
8004cb2: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
|
|
8004cb6: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
8004cba: 4013 ands r3, r2
|
|
8004cbc: b29a uxth r2, r3
|
|
8004cbe: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8004cc0: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
8004cc2: 687b ldr r3, [r7, #4]
|
|
8004cc4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8004cc6: 1c9a adds r2, r3, #2
|
|
8004cc8: 687b ldr r3, [r7, #4]
|
|
8004cca: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8004ccc: 687b ldr r3, [r7, #4]
|
|
8004cce: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8004cd2: b29b uxth r3, r3
|
|
8004cd4: 3b01 subs r3, #1
|
|
8004cd6: b29a uxth r2, r3
|
|
8004cd8: 687b ldr r3, [r7, #4]
|
|
8004cda: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8004cde: 687b ldr r3, [r7, #4]
|
|
8004ce0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8004ce4: b29b uxth r3, r3
|
|
8004ce6: 2b00 cmp r3, #0
|
|
8004ce8: f040 80a1 bne.w 8004e2e <UART_RxISR_16BIT+0x1aa>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8004cec: 687b ldr r3, [r7, #4]
|
|
8004cee: 681b ldr r3, [r3, #0]
|
|
8004cf0: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004cf2: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8004cf4: e853 3f00 ldrex r3, [r3]
|
|
8004cf8: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
8004cfa: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8004cfc: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8004d00: 667b str r3, [r7, #100] @ 0x64
|
|
8004d02: 687b ldr r3, [r7, #4]
|
|
8004d04: 681b ldr r3, [r3, #0]
|
|
8004d06: 461a mov r2, r3
|
|
8004d08: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8004d0a: 657b str r3, [r7, #84] @ 0x54
|
|
8004d0c: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004d0e: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
8004d10: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8004d12: e841 2300 strex r3, r2, [r1]
|
|
8004d16: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
8004d18: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8004d1a: 2b00 cmp r3, #0
|
|
8004d1c: d1e6 bne.n 8004cec <UART_RxISR_16BIT+0x68>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8004d1e: 687b ldr r3, [r7, #4]
|
|
8004d20: 681b ldr r3, [r3, #0]
|
|
8004d22: 3308 adds r3, #8
|
|
8004d24: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004d26: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8004d28: e853 3f00 ldrex r3, [r3]
|
|
8004d2c: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8004d2e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8004d30: f023 0301 bic.w r3, r3, #1
|
|
8004d34: 663b str r3, [r7, #96] @ 0x60
|
|
8004d36: 687b ldr r3, [r7, #4]
|
|
8004d38: 681b ldr r3, [r3, #0]
|
|
8004d3a: 3308 adds r3, #8
|
|
8004d3c: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8004d3e: 643a str r2, [r7, #64] @ 0x40
|
|
8004d40: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004d42: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8004d44: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8004d46: e841 2300 strex r3, r2, [r1]
|
|
8004d4a: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8004d4c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8004d4e: 2b00 cmp r3, #0
|
|
8004d50: d1e5 bne.n 8004d1e <UART_RxISR_16BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004d52: 687b ldr r3, [r7, #4]
|
|
8004d54: 2220 movs r2, #32
|
|
8004d56: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8004d5a: 687b ldr r3, [r7, #4]
|
|
8004d5c: 2200 movs r2, #0
|
|
8004d5e: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004d60: 687b ldr r3, [r7, #4]
|
|
8004d62: 2200 movs r2, #0
|
|
8004d64: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8004d66: 687b ldr r3, [r7, #4]
|
|
8004d68: 681b ldr r3, [r3, #0]
|
|
8004d6a: 4a33 ldr r2, [pc, #204] @ (8004e38 <UART_RxISR_16BIT+0x1b4>)
|
|
8004d6c: 4293 cmp r3, r2
|
|
8004d6e: d01f beq.n 8004db0 <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8004d70: 687b ldr r3, [r7, #4]
|
|
8004d72: 681b ldr r3, [r3, #0]
|
|
8004d74: 685b ldr r3, [r3, #4]
|
|
8004d76: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8004d7a: 2b00 cmp r3, #0
|
|
8004d7c: d018 beq.n 8004db0 <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8004d7e: 687b ldr r3, [r7, #4]
|
|
8004d80: 681b ldr r3, [r3, #0]
|
|
8004d82: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004d84: 6a3b ldr r3, [r7, #32]
|
|
8004d86: e853 3f00 ldrex r3, [r3]
|
|
8004d8a: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8004d8c: 69fb ldr r3, [r7, #28]
|
|
8004d8e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8004d92: 65fb str r3, [r7, #92] @ 0x5c
|
|
8004d94: 687b ldr r3, [r7, #4]
|
|
8004d96: 681b ldr r3, [r3, #0]
|
|
8004d98: 461a mov r2, r3
|
|
8004d9a: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8004d9c: 62fb str r3, [r7, #44] @ 0x2c
|
|
8004d9e: 62ba str r2, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004da0: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8004da2: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8004da4: e841 2300 strex r3, r2, [r1]
|
|
8004da8: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8004daa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004dac: 2b00 cmp r3, #0
|
|
8004dae: d1e6 bne.n 8004d7e <UART_RxISR_16BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8004db0: 687b ldr r3, [r7, #4]
|
|
8004db2: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8004db4: 2b01 cmp r3, #1
|
|
8004db6: d12e bne.n 8004e16 <UART_RxISR_16BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004db8: 687b ldr r3, [r7, #4]
|
|
8004dba: 2200 movs r2, #0
|
|
8004dbc: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004dbe: 687b ldr r3, [r7, #4]
|
|
8004dc0: 681b ldr r3, [r3, #0]
|
|
8004dc2: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004dc4: 68fb ldr r3, [r7, #12]
|
|
8004dc6: e853 3f00 ldrex r3, [r3]
|
|
8004dca: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8004dcc: 68bb ldr r3, [r7, #8]
|
|
8004dce: f023 0310 bic.w r3, r3, #16
|
|
8004dd2: 65bb str r3, [r7, #88] @ 0x58
|
|
8004dd4: 687b ldr r3, [r7, #4]
|
|
8004dd6: 681b ldr r3, [r3, #0]
|
|
8004dd8: 461a mov r2, r3
|
|
8004dda: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8004ddc: 61bb str r3, [r7, #24]
|
|
8004dde: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004de0: 6979 ldr r1, [r7, #20]
|
|
8004de2: 69ba ldr r2, [r7, #24]
|
|
8004de4: e841 2300 strex r3, r2, [r1]
|
|
8004de8: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8004dea: 693b ldr r3, [r7, #16]
|
|
8004dec: 2b00 cmp r3, #0
|
|
8004dee: d1e6 bne.n 8004dbe <UART_RxISR_16BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8004df0: 687b ldr r3, [r7, #4]
|
|
8004df2: 681b ldr r3, [r3, #0]
|
|
8004df4: 69db ldr r3, [r3, #28]
|
|
8004df6: f003 0310 and.w r3, r3, #16
|
|
8004dfa: 2b10 cmp r3, #16
|
|
8004dfc: d103 bne.n 8004e06 <UART_RxISR_16BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8004dfe: 687b ldr r3, [r7, #4]
|
|
8004e00: 681b ldr r3, [r3, #0]
|
|
8004e02: 2210 movs r2, #16
|
|
8004e04: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8004e06: 687b ldr r3, [r7, #4]
|
|
8004e08: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8004e0c: 4619 mov r1, r3
|
|
8004e0e: 6878 ldr r0, [r7, #4]
|
|
8004e10: f7ff f808 bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8004e14: e00b b.n 8004e2e <UART_RxISR_16BIT+0x1aa>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8004e16: 6878 ldr r0, [r7, #4]
|
|
8004e18: f7fc f8f8 bl 800100c <HAL_UART_RxCpltCallback>
|
|
}
|
|
8004e1c: e007 b.n 8004e2e <UART_RxISR_16BIT+0x1aa>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8004e1e: 687b ldr r3, [r7, #4]
|
|
8004e20: 681b ldr r3, [r3, #0]
|
|
8004e22: 699a ldr r2, [r3, #24]
|
|
8004e24: 687b ldr r3, [r7, #4]
|
|
8004e26: 681b ldr r3, [r3, #0]
|
|
8004e28: f042 0208 orr.w r2, r2, #8
|
|
8004e2c: 619a str r2, [r3, #24]
|
|
}
|
|
8004e2e: bf00 nop
|
|
8004e30: 3770 adds r7, #112 @ 0x70
|
|
8004e32: 46bd mov sp, r7
|
|
8004e34: bd80 pop {r7, pc}
|
|
8004e36: bf00 nop
|
|
8004e38: 40008000 .word 0x40008000
|
|
|
|
08004e3c <UART_RxISR_8BIT_FIFOEN>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|
{
|
|
8004e3c: b580 push {r7, lr}
|
|
8004e3e: b0ac sub sp, #176 @ 0xb0
|
|
8004e40: af00 add r7, sp, #0
|
|
8004e42: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
8004e44: 687b ldr r3, [r7, #4]
|
|
8004e46: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
8004e4a: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa
|
|
uint16_t uhdata;
|
|
uint16_t nb_rx_data;
|
|
uint16_t rxdatacount;
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8004e4e: 687b ldr r3, [r7, #4]
|
|
8004e50: 681b ldr r3, [r3, #0]
|
|
8004e52: 69db ldr r3, [r3, #28]
|
|
8004e54: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8004e58: 687b ldr r3, [r7, #4]
|
|
8004e5a: 681b ldr r3, [r3, #0]
|
|
8004e5c: 681b ldr r3, [r3, #0]
|
|
8004e5e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8004e62: 687b ldr r3, [r7, #4]
|
|
8004e64: 681b ldr r3, [r3, #0]
|
|
8004e66: 689b ldr r3, [r3, #8]
|
|
8004e68: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8004e6c: 687b ldr r3, [r7, #4]
|
|
8004e6e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004e72: 2b22 cmp r3, #34 @ 0x22
|
|
8004e74: f040 8183 bne.w 800517e <UART_RxISR_8BIT_FIFOEN+0x342>
|
|
{
|
|
nb_rx_data = huart->NbRxDataToProcess;
|
|
8004e78: 687b ldr r3, [r7, #4]
|
|
8004e7a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8004e7e: f8a7 309e strh.w r3, [r7, #158] @ 0x9e
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8004e82: e126 b.n 80050d2 <UART_RxISR_8BIT_FIFOEN+0x296>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
8004e84: 687b ldr r3, [r7, #4]
|
|
8004e86: 681b ldr r3, [r3, #0]
|
|
8004e88: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004e8a: f8a7 309c strh.w r3, [r7, #156] @ 0x9c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
8004e8e: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c
|
|
8004e92: b2d9 uxtb r1, r3
|
|
8004e94: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa
|
|
8004e98: b2da uxtb r2, r3
|
|
8004e9a: 687b ldr r3, [r7, #4]
|
|
8004e9c: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8004e9e: 400a ands r2, r1
|
|
8004ea0: b2d2 uxtb r2, r2
|
|
8004ea2: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
8004ea4: 687b ldr r3, [r7, #4]
|
|
8004ea6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8004ea8: 1c5a adds r2, r3, #1
|
|
8004eaa: 687b ldr r3, [r7, #4]
|
|
8004eac: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8004eae: 687b ldr r3, [r7, #4]
|
|
8004eb0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8004eb4: b29b uxth r3, r3
|
|
8004eb6: 3b01 subs r3, #1
|
|
8004eb8: b29a uxth r2, r3
|
|
8004eba: 687b ldr r3, [r7, #4]
|
|
8004ebc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
isrflags = READ_REG(huart->Instance->ISR);
|
|
8004ec0: 687b ldr r3, [r7, #4]
|
|
8004ec2: 681b ldr r3, [r3, #0]
|
|
8004ec4: 69db ldr r3, [r3, #28]
|
|
8004ec6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
|
|
/* If some non blocking errors occurred */
|
|
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
|
|
8004eca: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004ece: f003 0307 and.w r3, r3, #7
|
|
8004ed2: 2b00 cmp r3, #0
|
|
8004ed4: d053 beq.n 8004f7e <UART_RxISR_8BIT_FIFOEN+0x142>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8004ed6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004eda: f003 0301 and.w r3, r3, #1
|
|
8004ede: 2b00 cmp r3, #0
|
|
8004ee0: d011 beq.n 8004f06 <UART_RxISR_8BIT_FIFOEN+0xca>
|
|
8004ee2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
8004ee6: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004eea: 2b00 cmp r3, #0
|
|
8004eec: d00b beq.n 8004f06 <UART_RxISR_8BIT_FIFOEN+0xca>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8004eee: 687b ldr r3, [r7, #4]
|
|
8004ef0: 681b ldr r3, [r3, #0]
|
|
8004ef2: 2201 movs r2, #1
|
|
8004ef4: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8004ef6: 687b ldr r3, [r7, #4]
|
|
8004ef8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004efc: f043 0201 orr.w r2, r3, #1
|
|
8004f00: 687b ldr r3, [r7, #4]
|
|
8004f02: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8004f06: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004f0a: f003 0302 and.w r3, r3, #2
|
|
8004f0e: 2b00 cmp r3, #0
|
|
8004f10: d011 beq.n 8004f36 <UART_RxISR_8BIT_FIFOEN+0xfa>
|
|
8004f12: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8004f16: f003 0301 and.w r3, r3, #1
|
|
8004f1a: 2b00 cmp r3, #0
|
|
8004f1c: d00b beq.n 8004f36 <UART_RxISR_8BIT_FIFOEN+0xfa>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8004f1e: 687b ldr r3, [r7, #4]
|
|
8004f20: 681b ldr r3, [r3, #0]
|
|
8004f22: 2202 movs r2, #2
|
|
8004f24: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8004f26: 687b ldr r3, [r7, #4]
|
|
8004f28: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004f2c: f043 0204 orr.w r2, r3, #4
|
|
8004f30: 687b ldr r3, [r7, #4]
|
|
8004f32: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8004f36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8004f3a: f003 0304 and.w r3, r3, #4
|
|
8004f3e: 2b00 cmp r3, #0
|
|
8004f40: d011 beq.n 8004f66 <UART_RxISR_8BIT_FIFOEN+0x12a>
|
|
8004f42: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8004f46: f003 0301 and.w r3, r3, #1
|
|
8004f4a: 2b00 cmp r3, #0
|
|
8004f4c: d00b beq.n 8004f66 <UART_RxISR_8BIT_FIFOEN+0x12a>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8004f4e: 687b ldr r3, [r7, #4]
|
|
8004f50: 681b ldr r3, [r3, #0]
|
|
8004f52: 2204 movs r2, #4
|
|
8004f54: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8004f56: 687b ldr r3, [r7, #4]
|
|
8004f58: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004f5c: f043 0202 orr.w r2, r3, #2
|
|
8004f60: 687b ldr r3, [r7, #4]
|
|
8004f62: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8004f66: 687b ldr r3, [r7, #4]
|
|
8004f68: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004f6c: 2b00 cmp r3, #0
|
|
8004f6e: d006 beq.n 8004f7e <UART_RxISR_8BIT_FIFOEN+0x142>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8004f70: 6878 ldr r0, [r7, #4]
|
|
8004f72: f7fe ff4d bl 8003e10 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004f76: 687b ldr r3, [r7, #4]
|
|
8004f78: 2200 movs r2, #0
|
|
8004f7a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8004f7e: 687b ldr r3, [r7, #4]
|
|
8004f80: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8004f84: b29b uxth r3, r3
|
|
8004f86: 2b00 cmp r3, #0
|
|
8004f88: f040 80a3 bne.w 80050d2 <UART_RxISR_8BIT_FIFOEN+0x296>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8004f8c: 687b ldr r3, [r7, #4]
|
|
8004f8e: 681b ldr r3, [r3, #0]
|
|
8004f90: 673b str r3, [r7, #112] @ 0x70
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004f92: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8004f94: e853 3f00 ldrex r3, [r3]
|
|
8004f98: 66fb str r3, [r7, #108] @ 0x6c
|
|
return(result);
|
|
8004f9a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8004f9c: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8004fa0: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8004fa4: 687b ldr r3, [r7, #4]
|
|
8004fa6: 681b ldr r3, [r3, #0]
|
|
8004fa8: 461a mov r2, r3
|
|
8004faa: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8004fae: 67fb str r3, [r7, #124] @ 0x7c
|
|
8004fb0: 67ba str r2, [r7, #120] @ 0x78
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004fb2: 6fb9 ldr r1, [r7, #120] @ 0x78
|
|
8004fb4: 6ffa ldr r2, [r7, #124] @ 0x7c
|
|
8004fb6: e841 2300 strex r3, r2, [r1]
|
|
8004fba: 677b str r3, [r7, #116] @ 0x74
|
|
return(result);
|
|
8004fbc: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8004fbe: 2b00 cmp r3, #0
|
|
8004fc0: d1e4 bne.n 8004f8c <UART_RxISR_8BIT_FIFOEN+0x150>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
|
and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8004fc2: 687b ldr r3, [r7, #4]
|
|
8004fc4: 681b ldr r3, [r3, #0]
|
|
8004fc6: 3308 adds r3, #8
|
|
8004fc8: 65fb str r3, [r7, #92] @ 0x5c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004fca: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8004fcc: e853 3f00 ldrex r3, [r3]
|
|
8004fd0: 65bb str r3, [r7, #88] @ 0x58
|
|
return(result);
|
|
8004fd2: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8004fd4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8004fd8: f023 0301 bic.w r3, r3, #1
|
|
8004fdc: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8004fe0: 687b ldr r3, [r7, #4]
|
|
8004fe2: 681b ldr r3, [r3, #0]
|
|
8004fe4: 3308 adds r3, #8
|
|
8004fe6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
8004fea: 66ba str r2, [r7, #104] @ 0x68
|
|
8004fec: 667b str r3, [r7, #100] @ 0x64
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8004fee: 6e79 ldr r1, [r7, #100] @ 0x64
|
|
8004ff0: 6eba ldr r2, [r7, #104] @ 0x68
|
|
8004ff2: e841 2300 strex r3, r2, [r1]
|
|
8004ff6: 663b str r3, [r7, #96] @ 0x60
|
|
return(result);
|
|
8004ff8: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8004ffa: 2b00 cmp r3, #0
|
|
8004ffc: d1e1 bne.n 8004fc2 <UART_RxISR_8BIT_FIFOEN+0x186>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004ffe: 687b ldr r3, [r7, #4]
|
|
8005000: 2220 movs r2, #32
|
|
8005002: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8005006: 687b ldr r3, [r7, #4]
|
|
8005008: 2200 movs r2, #0
|
|
800500a: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800500c: 687b ldr r3, [r7, #4]
|
|
800500e: 2200 movs r2, #0
|
|
8005010: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8005012: 687b ldr r3, [r7, #4]
|
|
8005014: 681b ldr r3, [r3, #0]
|
|
8005016: 4a60 ldr r2, [pc, #384] @ (8005198 <UART_RxISR_8BIT_FIFOEN+0x35c>)
|
|
8005018: 4293 cmp r3, r2
|
|
800501a: d021 beq.n 8005060 <UART_RxISR_8BIT_FIFOEN+0x224>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
800501c: 687b ldr r3, [r7, #4]
|
|
800501e: 681b ldr r3, [r3, #0]
|
|
8005020: 685b ldr r3, [r3, #4]
|
|
8005022: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8005026: 2b00 cmp r3, #0
|
|
8005028: d01a beq.n 8005060 <UART_RxISR_8BIT_FIFOEN+0x224>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
800502a: 687b ldr r3, [r7, #4]
|
|
800502c: 681b ldr r3, [r3, #0]
|
|
800502e: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005030: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8005032: e853 3f00 ldrex r3, [r3]
|
|
8005036: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
8005038: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800503a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
800503e: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8005042: 687b ldr r3, [r7, #4]
|
|
8005044: 681b ldr r3, [r3, #0]
|
|
8005046: 461a mov r2, r3
|
|
8005048: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
800504c: 657b str r3, [r7, #84] @ 0x54
|
|
800504e: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005050: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
8005052: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8005054: e841 2300 strex r3, r2, [r1]
|
|
8005058: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
800505a: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800505c: 2b00 cmp r3, #0
|
|
800505e: d1e4 bne.n 800502a <UART_RxISR_8BIT_FIFOEN+0x1ee>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005060: 687b ldr r3, [r7, #4]
|
|
8005062: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8005064: 2b01 cmp r3, #1
|
|
8005066: d130 bne.n 80050ca <UART_RxISR_8BIT_FIFOEN+0x28e>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005068: 687b ldr r3, [r7, #4]
|
|
800506a: 2200 movs r2, #0
|
|
800506c: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800506e: 687b ldr r3, [r7, #4]
|
|
8005070: 681b ldr r3, [r3, #0]
|
|
8005072: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005074: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8005076: e853 3f00 ldrex r3, [r3]
|
|
800507a: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
800507c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800507e: f023 0310 bic.w r3, r3, #16
|
|
8005082: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
8005086: 687b ldr r3, [r7, #4]
|
|
8005088: 681b ldr r3, [r3, #0]
|
|
800508a: 461a mov r2, r3
|
|
800508c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8005090: 643b str r3, [r7, #64] @ 0x40
|
|
8005092: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005094: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8005096: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8005098: e841 2300 strex r3, r2, [r1]
|
|
800509c: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
800509e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80050a0: 2b00 cmp r3, #0
|
|
80050a2: d1e4 bne.n 800506e <UART_RxISR_8BIT_FIFOEN+0x232>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
80050a4: 687b ldr r3, [r7, #4]
|
|
80050a6: 681b ldr r3, [r3, #0]
|
|
80050a8: 69db ldr r3, [r3, #28]
|
|
80050aa: f003 0310 and.w r3, r3, #16
|
|
80050ae: 2b10 cmp r3, #16
|
|
80050b0: d103 bne.n 80050ba <UART_RxISR_8BIT_FIFOEN+0x27e>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80050b2: 687b ldr r3, [r7, #4]
|
|
80050b4: 681b ldr r3, [r3, #0]
|
|
80050b6: 2210 movs r2, #16
|
|
80050b8: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80050ba: 687b ldr r3, [r7, #4]
|
|
80050bc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
80050c0: 4619 mov r1, r3
|
|
80050c2: 6878 ldr r0, [r7, #4]
|
|
80050c4: f7fe feae bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
break;
|
|
80050c8: e00e b.n 80050e8 <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
80050ca: 6878 ldr r0, [r7, #4]
|
|
80050cc: f7fb ff9e bl 800100c <HAL_UART_RxCpltCallback>
|
|
break;
|
|
80050d0: e00a b.n 80050e8 <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
80050d2: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e
|
|
80050d6: 2b00 cmp r3, #0
|
|
80050d8: d006 beq.n 80050e8 <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
80050da: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80050de: f003 0320 and.w r3, r3, #32
|
|
80050e2: 2b00 cmp r3, #0
|
|
80050e4: f47f aece bne.w 8004e84 <UART_RxISR_8BIT_FIFOEN+0x48>
|
|
|
|
/* When remaining number of bytes to receive is less than the RX FIFO
|
|
threshold, next incoming frames are processed as if FIFO mode was
|
|
disabled (i.e. one interrupt per received frame).
|
|
*/
|
|
rxdatacount = huart->RxXferCount;
|
|
80050e8: 687b ldr r3, [r7, #4]
|
|
80050ea: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80050ee: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
|
80050f2: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
80050f6: 2b00 cmp r3, #0
|
|
80050f8: d049 beq.n 800518e <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
80050fa: 687b ldr r3, [r7, #4]
|
|
80050fc: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8005100: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a
|
|
8005104: 429a cmp r2, r3
|
|
8005106: d242 bcs.n 800518e <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
{
|
|
/* Disable the UART RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
8005108: 687b ldr r3, [r7, #4]
|
|
800510a: 681b ldr r3, [r3, #0]
|
|
800510c: 3308 adds r3, #8
|
|
800510e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005110: 6a3b ldr r3, [r7, #32]
|
|
8005112: e853 3f00 ldrex r3, [r3]
|
|
8005116: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8005118: 69fb ldr r3, [r7, #28]
|
|
800511a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800511e: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8005122: 687b ldr r3, [r7, #4]
|
|
8005124: 681b ldr r3, [r3, #0]
|
|
8005126: 3308 adds r3, #8
|
|
8005128: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
|
|
800512c: 62fa str r2, [r7, #44] @ 0x2c
|
|
800512e: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005130: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8005132: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8005134: e841 2300 strex r3, r2, [r1]
|
|
8005138: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
800513a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800513c: 2b00 cmp r3, #0
|
|
800513e: d1e3 bne.n 8005108 <UART_RxISR_8BIT_FIFOEN+0x2cc>
|
|
|
|
/* Update the RxISR function pointer */
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
8005140: 687b ldr r3, [r7, #4]
|
|
8005142: 4a16 ldr r2, [pc, #88] @ (800519c <UART_RxISR_8BIT_FIFOEN+0x360>)
|
|
8005144: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Enable the UART Data Register Not Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
8005146: 687b ldr r3, [r7, #4]
|
|
8005148: 681b ldr r3, [r3, #0]
|
|
800514a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800514c: 68fb ldr r3, [r7, #12]
|
|
800514e: e853 3f00 ldrex r3, [r3]
|
|
8005152: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8005154: 68bb ldr r3, [r7, #8]
|
|
8005156: f043 0320 orr.w r3, r3, #32
|
|
800515a: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
800515e: 687b ldr r3, [r7, #4]
|
|
8005160: 681b ldr r3, [r3, #0]
|
|
8005162: 461a mov r2, r3
|
|
8005164: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8005168: 61bb str r3, [r7, #24]
|
|
800516a: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800516c: 6979 ldr r1, [r7, #20]
|
|
800516e: 69ba ldr r2, [r7, #24]
|
|
8005170: e841 2300 strex r3, r2, [r1]
|
|
8005174: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8005176: 693b ldr r3, [r7, #16]
|
|
8005178: 2b00 cmp r3, #0
|
|
800517a: d1e4 bne.n 8005146 <UART_RxISR_8BIT_FIFOEN+0x30a>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
800517c: e007 b.n 800518e <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
800517e: 687b ldr r3, [r7, #4]
|
|
8005180: 681b ldr r3, [r3, #0]
|
|
8005182: 699a ldr r2, [r3, #24]
|
|
8005184: 687b ldr r3, [r7, #4]
|
|
8005186: 681b ldr r3, [r3, #0]
|
|
8005188: f042 0208 orr.w r2, r2, #8
|
|
800518c: 619a str r2, [r3, #24]
|
|
}
|
|
800518e: bf00 nop
|
|
8005190: 37b0 adds r7, #176 @ 0xb0
|
|
8005192: 46bd mov sp, r7
|
|
8005194: bd80 pop {r7, pc}
|
|
8005196: bf00 nop
|
|
8005198: 40008000 .word 0x40008000
|
|
800519c: 08004acd .word 0x08004acd
|
|
|
|
080051a0 <UART_RxISR_16BIT_FIFOEN>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|
{
|
|
80051a0: b580 push {r7, lr}
|
|
80051a2: b0ae sub sp, #184 @ 0xb8
|
|
80051a4: af00 add r7, sp, #0
|
|
80051a6: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
80051a8: 687b ldr r3, [r7, #4]
|
|
80051aa: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
80051ae: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2
|
|
uint16_t uhdata;
|
|
uint16_t nb_rx_data;
|
|
uint16_t rxdatacount;
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
80051b2: 687b ldr r3, [r7, #4]
|
|
80051b4: 681b ldr r3, [r3, #0]
|
|
80051b6: 69db ldr r3, [r3, #28]
|
|
80051b8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
80051bc: 687b ldr r3, [r7, #4]
|
|
80051be: 681b ldr r3, [r3, #0]
|
|
80051c0: 681b ldr r3, [r3, #0]
|
|
80051c2: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
80051c6: 687b ldr r3, [r7, #4]
|
|
80051c8: 681b ldr r3, [r3, #0]
|
|
80051ca: 689b ldr r3, [r3, #8]
|
|
80051cc: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
80051d0: 687b ldr r3, [r7, #4]
|
|
80051d2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80051d6: 2b22 cmp r3, #34 @ 0x22
|
|
80051d8: f040 8187 bne.w 80054ea <UART_RxISR_16BIT_FIFOEN+0x34a>
|
|
{
|
|
nb_rx_data = huart->NbRxDataToProcess;
|
|
80051dc: 687b ldr r3, [r7, #4]
|
|
80051de: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
80051e2: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
80051e6: e12a b.n 800543e <UART_RxISR_16BIT_FIFOEN+0x29e>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
80051e8: 687b ldr r3, [r7, #4]
|
|
80051ea: 681b ldr r3, [r3, #0]
|
|
80051ec: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80051ee: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
80051f2: 687b ldr r3, [r7, #4]
|
|
80051f4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80051f6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
80051fa: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4
|
|
80051fe: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2
|
|
8005202: 4013 ands r3, r2
|
|
8005204: b29a uxth r2, r3
|
|
8005206: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
800520a: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
800520c: 687b ldr r3, [r7, #4]
|
|
800520e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8005210: 1c9a adds r2, r3, #2
|
|
8005212: 687b ldr r3, [r7, #4]
|
|
8005214: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8005216: 687b ldr r3, [r7, #4]
|
|
8005218: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
800521c: b29b uxth r3, r3
|
|
800521e: 3b01 subs r3, #1
|
|
8005220: b29a uxth r2, r3
|
|
8005222: 687b ldr r3, [r7, #4]
|
|
8005224: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
isrflags = READ_REG(huart->Instance->ISR);
|
|
8005228: 687b ldr r3, [r7, #4]
|
|
800522a: 681b ldr r3, [r3, #0]
|
|
800522c: 69db ldr r3, [r3, #28]
|
|
800522e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
|
|
/* If some non blocking errors occurred */
|
|
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
|
|
8005232: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8005236: f003 0307 and.w r3, r3, #7
|
|
800523a: 2b00 cmp r3, #0
|
|
800523c: d053 beq.n 80052e6 <UART_RxISR_16BIT_FIFOEN+0x146>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
800523e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8005242: f003 0301 and.w r3, r3, #1
|
|
8005246: 2b00 cmp r3, #0
|
|
8005248: d011 beq.n 800526e <UART_RxISR_16BIT_FIFOEN+0xce>
|
|
800524a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800524e: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8005252: 2b00 cmp r3, #0
|
|
8005254: d00b beq.n 800526e <UART_RxISR_16BIT_FIFOEN+0xce>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8005256: 687b ldr r3, [r7, #4]
|
|
8005258: 681b ldr r3, [r3, #0]
|
|
800525a: 2201 movs r2, #1
|
|
800525c: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
800525e: 687b ldr r3, [r7, #4]
|
|
8005260: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005264: f043 0201 orr.w r2, r3, #1
|
|
8005268: 687b ldr r3, [r7, #4]
|
|
800526a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800526e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8005272: f003 0302 and.w r3, r3, #2
|
|
8005276: 2b00 cmp r3, #0
|
|
8005278: d011 beq.n 800529e <UART_RxISR_16BIT_FIFOEN+0xfe>
|
|
800527a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
800527e: f003 0301 and.w r3, r3, #1
|
|
8005282: 2b00 cmp r3, #0
|
|
8005284: d00b beq.n 800529e <UART_RxISR_16BIT_FIFOEN+0xfe>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8005286: 687b ldr r3, [r7, #4]
|
|
8005288: 681b ldr r3, [r3, #0]
|
|
800528a: 2202 movs r2, #2
|
|
800528c: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
800528e: 687b ldr r3, [r7, #4]
|
|
8005290: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8005294: f043 0204 orr.w r2, r3, #4
|
|
8005298: 687b ldr r3, [r7, #4]
|
|
800529a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800529e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
80052a2: f003 0304 and.w r3, r3, #4
|
|
80052a6: 2b00 cmp r3, #0
|
|
80052a8: d011 beq.n 80052ce <UART_RxISR_16BIT_FIFOEN+0x12e>
|
|
80052aa: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
80052ae: f003 0301 and.w r3, r3, #1
|
|
80052b2: 2b00 cmp r3, #0
|
|
80052b4: d00b beq.n 80052ce <UART_RxISR_16BIT_FIFOEN+0x12e>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
80052b6: 687b ldr r3, [r7, #4]
|
|
80052b8: 681b ldr r3, [r3, #0]
|
|
80052ba: 2204 movs r2, #4
|
|
80052bc: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
80052be: 687b ldr r3, [r7, #4]
|
|
80052c0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80052c4: f043 0202 orr.w r2, r3, #2
|
|
80052c8: 687b ldr r3, [r7, #4]
|
|
80052ca: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
80052ce: 687b ldr r3, [r7, #4]
|
|
80052d0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80052d4: 2b00 cmp r3, #0
|
|
80052d6: d006 beq.n 80052e6 <UART_RxISR_16BIT_FIFOEN+0x146>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80052d8: 6878 ldr r0, [r7, #4]
|
|
80052da: f7fe fd99 bl 8003e10 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80052de: 687b ldr r3, [r7, #4]
|
|
80052e0: 2200 movs r2, #0
|
|
80052e2: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
80052e6: 687b ldr r3, [r7, #4]
|
|
80052e8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80052ec: b29b uxth r3, r3
|
|
80052ee: 2b00 cmp r3, #0
|
|
80052f0: f040 80a5 bne.w 800543e <UART_RxISR_16BIT_FIFOEN+0x29e>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80052f4: 687b ldr r3, [r7, #4]
|
|
80052f6: 681b ldr r3, [r3, #0]
|
|
80052f8: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80052fa: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80052fc: e853 3f00 ldrex r3, [r3]
|
|
8005300: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8005302: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8005304: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005308: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
800530c: 687b ldr r3, [r7, #4]
|
|
800530e: 681b ldr r3, [r3, #0]
|
|
8005310: 461a mov r2, r3
|
|
8005312: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8005316: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
800531a: 67fa str r2, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800531c: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
800531e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8005322: e841 2300 strex r3, r2, [r1]
|
|
8005326: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8005328: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
800532a: 2b00 cmp r3, #0
|
|
800532c: d1e2 bne.n 80052f4 <UART_RxISR_16BIT_FIFOEN+0x154>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
|
and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
800532e: 687b ldr r3, [r7, #4]
|
|
8005330: 681b ldr r3, [r3, #0]
|
|
8005332: 3308 adds r3, #8
|
|
8005334: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005336: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8005338: e853 3f00 ldrex r3, [r3]
|
|
800533c: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
800533e: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8005340: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005344: f023 0301 bic.w r3, r3, #1
|
|
8005348: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
800534c: 687b ldr r3, [r7, #4]
|
|
800534e: 681b ldr r3, [r3, #0]
|
|
8005350: 3308 adds r3, #8
|
|
8005352: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98
|
|
8005356: 66fa str r2, [r7, #108] @ 0x6c
|
|
8005358: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800535a: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
800535c: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
800535e: e841 2300 strex r3, r2, [r1]
|
|
8005362: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8005364: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8005366: 2b00 cmp r3, #0
|
|
8005368: d1e1 bne.n 800532e <UART_RxISR_16BIT_FIFOEN+0x18e>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800536a: 687b ldr r3, [r7, #4]
|
|
800536c: 2220 movs r2, #32
|
|
800536e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8005372: 687b ldr r3, [r7, #4]
|
|
8005374: 2200 movs r2, #0
|
|
8005376: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005378: 687b ldr r3, [r7, #4]
|
|
800537a: 2200 movs r2, #0
|
|
800537c: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
800537e: 687b ldr r3, [r7, #4]
|
|
8005380: 681b ldr r3, [r3, #0]
|
|
8005382: 4a60 ldr r2, [pc, #384] @ (8005504 <UART_RxISR_16BIT_FIFOEN+0x364>)
|
|
8005384: 4293 cmp r3, r2
|
|
8005386: d021 beq.n 80053cc <UART_RxISR_16BIT_FIFOEN+0x22c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8005388: 687b ldr r3, [r7, #4]
|
|
800538a: 681b ldr r3, [r3, #0]
|
|
800538c: 685b ldr r3, [r3, #4]
|
|
800538e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8005392: 2b00 cmp r3, #0
|
|
8005394: d01a beq.n 80053cc <UART_RxISR_16BIT_FIFOEN+0x22c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8005396: 687b ldr r3, [r7, #4]
|
|
8005398: 681b ldr r3, [r3, #0]
|
|
800539a: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800539c: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800539e: e853 3f00 ldrex r3, [r3]
|
|
80053a2: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80053a4: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80053a6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
80053aa: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
80053ae: 687b ldr r3, [r7, #4]
|
|
80053b0: 681b ldr r3, [r3, #0]
|
|
80053b2: 461a mov r2, r3
|
|
80053b4: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
80053b8: 65bb str r3, [r7, #88] @ 0x58
|
|
80053ba: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80053bc: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80053be: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80053c0: e841 2300 strex r3, r2, [r1]
|
|
80053c4: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80053c6: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80053c8: 2b00 cmp r3, #0
|
|
80053ca: d1e4 bne.n 8005396 <UART_RxISR_16BIT_FIFOEN+0x1f6>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80053cc: 687b ldr r3, [r7, #4]
|
|
80053ce: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80053d0: 2b01 cmp r3, #1
|
|
80053d2: d130 bne.n 8005436 <UART_RxISR_16BIT_FIFOEN+0x296>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80053d4: 687b ldr r3, [r7, #4]
|
|
80053d6: 2200 movs r2, #0
|
|
80053d8: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80053da: 687b ldr r3, [r7, #4]
|
|
80053dc: 681b ldr r3, [r3, #0]
|
|
80053de: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80053e0: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80053e2: e853 3f00 ldrex r3, [r3]
|
|
80053e6: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
80053e8: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80053ea: f023 0310 bic.w r3, r3, #16
|
|
80053ee: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
80053f2: 687b ldr r3, [r7, #4]
|
|
80053f4: 681b ldr r3, [r3, #0]
|
|
80053f6: 461a mov r2, r3
|
|
80053f8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
80053fc: 647b str r3, [r7, #68] @ 0x44
|
|
80053fe: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005400: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8005402: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8005404: e841 2300 strex r3, r2, [r1]
|
|
8005408: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
800540a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800540c: 2b00 cmp r3, #0
|
|
800540e: d1e4 bne.n 80053da <UART_RxISR_16BIT_FIFOEN+0x23a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8005410: 687b ldr r3, [r7, #4]
|
|
8005412: 681b ldr r3, [r3, #0]
|
|
8005414: 69db ldr r3, [r3, #28]
|
|
8005416: f003 0310 and.w r3, r3, #16
|
|
800541a: 2b10 cmp r3, #16
|
|
800541c: d103 bne.n 8005426 <UART_RxISR_16BIT_FIFOEN+0x286>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
800541e: 687b ldr r3, [r7, #4]
|
|
8005420: 681b ldr r3, [r3, #0]
|
|
8005422: 2210 movs r2, #16
|
|
8005424: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8005426: 687b ldr r3, [r7, #4]
|
|
8005428: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
800542c: 4619 mov r1, r3
|
|
800542e: 6878 ldr r0, [r7, #4]
|
|
8005430: f7fe fcf8 bl 8003e24 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
break;
|
|
8005434: e00e b.n 8005454 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8005436: 6878 ldr r0, [r7, #4]
|
|
8005438: f7fb fde8 bl 800100c <HAL_UART_RxCpltCallback>
|
|
break;
|
|
800543c: e00a b.n 8005454 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
800543e: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6
|
|
8005442: 2b00 cmp r3, #0
|
|
8005444: d006 beq.n 8005454 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
8005446: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
800544a: f003 0320 and.w r3, r3, #32
|
|
800544e: 2b00 cmp r3, #0
|
|
8005450: f47f aeca bne.w 80051e8 <UART_RxISR_16BIT_FIFOEN+0x48>
|
|
|
|
/* When remaining number of bytes to receive is less than the RX FIFO
|
|
threshold, next incoming frames are processed as if FIFO mode was
|
|
disabled (i.e. one interrupt per received frame).
|
|
*/
|
|
rxdatacount = huart->RxXferCount;
|
|
8005454: 687b ldr r3, [r7, #4]
|
|
8005456: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
800545a: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
|
|
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
|
800545e: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
|
|
8005462: 2b00 cmp r3, #0
|
|
8005464: d049 beq.n 80054fa <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
8005466: 687b ldr r3, [r7, #4]
|
|
8005468: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
800546c: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e
|
|
8005470: 429a cmp r2, r3
|
|
8005472: d242 bcs.n 80054fa <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
{
|
|
/* Disable the UART RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
8005474: 687b ldr r3, [r7, #4]
|
|
8005476: 681b ldr r3, [r3, #0]
|
|
8005478: 3308 adds r3, #8
|
|
800547a: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800547c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800547e: e853 3f00 ldrex r3, [r3]
|
|
8005482: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8005484: 6a3b ldr r3, [r7, #32]
|
|
8005486: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800548a: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800548e: 687b ldr r3, [r7, #4]
|
|
8005490: 681b ldr r3, [r3, #0]
|
|
8005492: 3308 adds r3, #8
|
|
8005494: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88
|
|
8005498: 633a str r2, [r7, #48] @ 0x30
|
|
800549a: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800549c: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800549e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80054a0: e841 2300 strex r3, r2, [r1]
|
|
80054a4: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
80054a6: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80054a8: 2b00 cmp r3, #0
|
|
80054aa: d1e3 bne.n 8005474 <UART_RxISR_16BIT_FIFOEN+0x2d4>
|
|
|
|
/* Update the RxISR function pointer */
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
80054ac: 687b ldr r3, [r7, #4]
|
|
80054ae: 4a16 ldr r2, [pc, #88] @ (8005508 <UART_RxISR_16BIT_FIFOEN+0x368>)
|
|
80054b0: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Enable the UART Data Register Not Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
80054b2: 687b ldr r3, [r7, #4]
|
|
80054b4: 681b ldr r3, [r3, #0]
|
|
80054b6: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80054b8: 693b ldr r3, [r7, #16]
|
|
80054ba: e853 3f00 ldrex r3, [r3]
|
|
80054be: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80054c0: 68fb ldr r3, [r7, #12]
|
|
80054c2: f043 0320 orr.w r3, r3, #32
|
|
80054c6: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
80054ca: 687b ldr r3, [r7, #4]
|
|
80054cc: 681b ldr r3, [r3, #0]
|
|
80054ce: 461a mov r2, r3
|
|
80054d0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
80054d4: 61fb str r3, [r7, #28]
|
|
80054d6: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80054d8: 69b9 ldr r1, [r7, #24]
|
|
80054da: 69fa ldr r2, [r7, #28]
|
|
80054dc: e841 2300 strex r3, r2, [r1]
|
|
80054e0: 617b str r3, [r7, #20]
|
|
return(result);
|
|
80054e2: 697b ldr r3, [r7, #20]
|
|
80054e4: 2b00 cmp r3, #0
|
|
80054e6: d1e4 bne.n 80054b2 <UART_RxISR_16BIT_FIFOEN+0x312>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
80054e8: e007 b.n 80054fa <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
80054ea: 687b ldr r3, [r7, #4]
|
|
80054ec: 681b ldr r3, [r3, #0]
|
|
80054ee: 699a ldr r2, [r3, #24]
|
|
80054f0: 687b ldr r3, [r7, #4]
|
|
80054f2: 681b ldr r3, [r3, #0]
|
|
80054f4: f042 0208 orr.w r2, r2, #8
|
|
80054f8: 619a str r2, [r3, #24]
|
|
}
|
|
80054fa: bf00 nop
|
|
80054fc: 37b8 adds r7, #184 @ 0xb8
|
|
80054fe: 46bd mov sp, r7
|
|
8005500: bd80 pop {r7, pc}
|
|
8005502: bf00 nop
|
|
8005504: 40008000 .word 0x40008000
|
|
8005508: 08004c85 .word 0x08004c85
|
|
|
|
0800550c <HAL_UARTEx_WakeupCallback>:
|
|
* @brief UART wakeup from Stop mode callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800550c: b480 push {r7}
|
|
800550e: b083 sub sp, #12
|
|
8005510: af00 add r7, sp, #0
|
|
8005512: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005514: bf00 nop
|
|
8005516: 370c adds r7, #12
|
|
8005518: 46bd mov sp, r7
|
|
800551a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800551e: 4770 bx lr
|
|
|
|
08005520 <HAL_UARTEx_RxFifoFullCallback>:
|
|
* @brief UART RX Fifo full callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005520: b480 push {r7}
|
|
8005522: b083 sub sp, #12
|
|
8005524: af00 add r7, sp, #0
|
|
8005526: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005528: bf00 nop
|
|
800552a: 370c adds r7, #12
|
|
800552c: 46bd mov sp, r7
|
|
800552e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005532: 4770 bx lr
|
|
|
|
08005534 <HAL_UARTEx_TxFifoEmptyCallback>:
|
|
* @brief UART TX Fifo empty callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005534: b480 push {r7}
|
|
8005536: b083 sub sp, #12
|
|
8005538: af00 add r7, sp, #0
|
|
800553a: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800553c: bf00 nop
|
|
800553e: 370c adds r7, #12
|
|
8005540: 46bd mov sp, r7
|
|
8005542: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005546: 4770 bx lr
|
|
|
|
08005548 <HAL_UARTEx_DisableFifoMode>:
|
|
* @brief Disable the FIFO mode.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
|
|
{
|
|
8005548: b480 push {r7}
|
|
800554a: b085 sub sp, #20
|
|
800554c: af00 add r7, sp, #0
|
|
800554e: 6078 str r0, [r7, #4]
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8005550: 687b ldr r3, [r7, #4]
|
|
8005552: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8005556: 2b01 cmp r3, #1
|
|
8005558: d101 bne.n 800555e <HAL_UARTEx_DisableFifoMode+0x16>
|
|
800555a: 2302 movs r3, #2
|
|
800555c: e027 b.n 80055ae <HAL_UARTEx_DisableFifoMode+0x66>
|
|
800555e: 687b ldr r3, [r7, #4]
|
|
8005560: 2201 movs r2, #1
|
|
8005562: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005566: 687b ldr r3, [r7, #4]
|
|
8005568: 2224 movs r2, #36 @ 0x24
|
|
800556a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
800556e: 687b ldr r3, [r7, #4]
|
|
8005570: 681b ldr r3, [r3, #0]
|
|
8005572: 681b ldr r3, [r3, #0]
|
|
8005574: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
8005576: 687b ldr r3, [r7, #4]
|
|
8005578: 681b ldr r3, [r3, #0]
|
|
800557a: 681a ldr r2, [r3, #0]
|
|
800557c: 687b ldr r3, [r7, #4]
|
|
800557e: 681b ldr r3, [r3, #0]
|
|
8005580: f022 0201 bic.w r2, r2, #1
|
|
8005584: 601a str r2, [r3, #0]
|
|
|
|
/* Disable FIFO mode */
|
|
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
|
|
8005586: 68fb ldr r3, [r7, #12]
|
|
8005588: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
|
|
800558c: 60fb str r3, [r7, #12]
|
|
huart->FifoMode = UART_FIFOMODE_DISABLE;
|
|
800558e: 687b ldr r3, [r7, #4]
|
|
8005590: 2200 movs r2, #0
|
|
8005592: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8005594: 687b ldr r3, [r7, #4]
|
|
8005596: 681b ldr r3, [r3, #0]
|
|
8005598: 68fa ldr r2, [r7, #12]
|
|
800559a: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800559c: 687b ldr r3, [r7, #4]
|
|
800559e: 2220 movs r2, #32
|
|
80055a0: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80055a4: 687b ldr r3, [r7, #4]
|
|
80055a6: 2200 movs r2, #0
|
|
80055a8: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
80055ac: 2300 movs r3, #0
|
|
}
|
|
80055ae: 4618 mov r0, r3
|
|
80055b0: 3714 adds r7, #20
|
|
80055b2: 46bd mov sp, r7
|
|
80055b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80055b8: 4770 bx lr
|
|
|
|
080055ba <HAL_UARTEx_SetTxFifoThreshold>:
|
|
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
|
|
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
|
{
|
|
80055ba: b580 push {r7, lr}
|
|
80055bc: b084 sub sp, #16
|
|
80055be: af00 add r7, sp, #0
|
|
80055c0: 6078 str r0, [r7, #4]
|
|
80055c2: 6039 str r1, [r7, #0]
|
|
/* Check parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
80055c4: 687b ldr r3, [r7, #4]
|
|
80055c6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
80055ca: 2b01 cmp r3, #1
|
|
80055cc: d101 bne.n 80055d2 <HAL_UARTEx_SetTxFifoThreshold+0x18>
|
|
80055ce: 2302 movs r3, #2
|
|
80055d0: e02d b.n 800562e <HAL_UARTEx_SetTxFifoThreshold+0x74>
|
|
80055d2: 687b ldr r3, [r7, #4]
|
|
80055d4: 2201 movs r2, #1
|
|
80055d6: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80055da: 687b ldr r3, [r7, #4]
|
|
80055dc: 2224 movs r2, #36 @ 0x24
|
|
80055de: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
80055e2: 687b ldr r3, [r7, #4]
|
|
80055e4: 681b ldr r3, [r3, #0]
|
|
80055e6: 681b ldr r3, [r3, #0]
|
|
80055e8: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
80055ea: 687b ldr r3, [r7, #4]
|
|
80055ec: 681b ldr r3, [r3, #0]
|
|
80055ee: 681a ldr r2, [r3, #0]
|
|
80055f0: 687b ldr r3, [r7, #4]
|
|
80055f2: 681b ldr r3, [r3, #0]
|
|
80055f4: f022 0201 bic.w r2, r2, #1
|
|
80055f8: 601a str r2, [r3, #0]
|
|
|
|
/* Update TX threshold configuration */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
|
|
80055fa: 687b ldr r3, [r7, #4]
|
|
80055fc: 681b ldr r3, [r3, #0]
|
|
80055fe: 689b ldr r3, [r3, #8]
|
|
8005600: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
|
|
8005604: 687b ldr r3, [r7, #4]
|
|
8005606: 681b ldr r3, [r3, #0]
|
|
8005608: 683a ldr r2, [r7, #0]
|
|
800560a: 430a orrs r2, r1
|
|
800560c: 609a str r2, [r3, #8]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
800560e: 6878 ldr r0, [r7, #4]
|
|
8005610: f000 f850 bl 80056b4 <UARTEx_SetNbDataToProcess>
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8005614: 687b ldr r3, [r7, #4]
|
|
8005616: 681b ldr r3, [r3, #0]
|
|
8005618: 68fa ldr r2, [r7, #12]
|
|
800561a: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800561c: 687b ldr r3, [r7, #4]
|
|
800561e: 2220 movs r2, #32
|
|
8005620: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8005624: 687b ldr r3, [r7, #4]
|
|
8005626: 2200 movs r2, #0
|
|
8005628: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
800562c: 2300 movs r3, #0
|
|
}
|
|
800562e: 4618 mov r0, r3
|
|
8005630: 3710 adds r7, #16
|
|
8005632: 46bd mov sp, r7
|
|
8005634: bd80 pop {r7, pc}
|
|
|
|
08005636 <HAL_UARTEx_SetRxFifoThreshold>:
|
|
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
|
|
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
|
{
|
|
8005636: b580 push {r7, lr}
|
|
8005638: b084 sub sp, #16
|
|
800563a: af00 add r7, sp, #0
|
|
800563c: 6078 str r0, [r7, #4]
|
|
800563e: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8005640: 687b ldr r3, [r7, #4]
|
|
8005642: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8005646: 2b01 cmp r3, #1
|
|
8005648: d101 bne.n 800564e <HAL_UARTEx_SetRxFifoThreshold+0x18>
|
|
800564a: 2302 movs r3, #2
|
|
800564c: e02d b.n 80056aa <HAL_UARTEx_SetRxFifoThreshold+0x74>
|
|
800564e: 687b ldr r3, [r7, #4]
|
|
8005650: 2201 movs r2, #1
|
|
8005652: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005656: 687b ldr r3, [r7, #4]
|
|
8005658: 2224 movs r2, #36 @ 0x24
|
|
800565a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
800565e: 687b ldr r3, [r7, #4]
|
|
8005660: 681b ldr r3, [r3, #0]
|
|
8005662: 681b ldr r3, [r3, #0]
|
|
8005664: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
8005666: 687b ldr r3, [r7, #4]
|
|
8005668: 681b ldr r3, [r3, #0]
|
|
800566a: 681a ldr r2, [r3, #0]
|
|
800566c: 687b ldr r3, [r7, #4]
|
|
800566e: 681b ldr r3, [r3, #0]
|
|
8005670: f022 0201 bic.w r2, r2, #1
|
|
8005674: 601a str r2, [r3, #0]
|
|
|
|
/* Update RX threshold configuration */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
|
|
8005676: 687b ldr r3, [r7, #4]
|
|
8005678: 681b ldr r3, [r3, #0]
|
|
800567a: 689b ldr r3, [r3, #8]
|
|
800567c: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
|
|
8005680: 687b ldr r3, [r7, #4]
|
|
8005682: 681b ldr r3, [r3, #0]
|
|
8005684: 683a ldr r2, [r7, #0]
|
|
8005686: 430a orrs r2, r1
|
|
8005688: 609a str r2, [r3, #8]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
800568a: 6878 ldr r0, [r7, #4]
|
|
800568c: f000 f812 bl 80056b4 <UARTEx_SetNbDataToProcess>
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8005690: 687b ldr r3, [r7, #4]
|
|
8005692: 681b ldr r3, [r3, #0]
|
|
8005694: 68fa ldr r2, [r7, #12]
|
|
8005696: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005698: 687b ldr r3, [r7, #4]
|
|
800569a: 2220 movs r2, #32
|
|
800569c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
80056a0: 687b ldr r3, [r7, #4]
|
|
80056a2: 2200 movs r2, #0
|
|
80056a4: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
80056a8: 2300 movs r3, #0
|
|
}
|
|
80056aa: 4618 mov r0, r3
|
|
80056ac: 3710 adds r7, #16
|
|
80056ae: 46bd mov sp, r7
|
|
80056b0: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080056b4 <UARTEx_SetNbDataToProcess>:
|
|
* the UART configuration registers.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
|
|
{
|
|
80056b4: b480 push {r7}
|
|
80056b6: b085 sub sp, #20
|
|
80056b8: af00 add r7, sp, #0
|
|
80056ba: 6078 str r0, [r7, #4]
|
|
uint8_t rx_fifo_threshold;
|
|
uint8_t tx_fifo_threshold;
|
|
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
|
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
|
|
|
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
|
80056bc: 687b ldr r3, [r7, #4]
|
|
80056be: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
80056c0: 2b00 cmp r3, #0
|
|
80056c2: d108 bne.n 80056d6 <UARTEx_SetNbDataToProcess+0x22>
|
|
{
|
|
huart->NbTxDataToProcess = 1U;
|
|
80056c4: 687b ldr r3, [r7, #4]
|
|
80056c6: 2201 movs r2, #1
|
|
80056c8: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = 1U;
|
|
80056cc: 687b ldr r3, [r7, #4]
|
|
80056ce: 2201 movs r2, #1
|
|
80056d0: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
}
|
|
}
|
|
80056d4: e031 b.n 800573a <UARTEx_SetNbDataToProcess+0x86>
|
|
rx_fifo_depth = RX_FIFO_DEPTH;
|
|
80056d6: 2308 movs r3, #8
|
|
80056d8: 73fb strb r3, [r7, #15]
|
|
tx_fifo_depth = TX_FIFO_DEPTH;
|
|
80056da: 2308 movs r3, #8
|
|
80056dc: 73bb strb r3, [r7, #14]
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
80056de: 687b ldr r3, [r7, #4]
|
|
80056e0: 681b ldr r3, [r3, #0]
|
|
80056e2: 689b ldr r3, [r3, #8]
|
|
80056e4: 0e5b lsrs r3, r3, #25
|
|
80056e6: b2db uxtb r3, r3
|
|
80056e8: f003 0307 and.w r3, r3, #7
|
|
80056ec: 737b strb r3, [r7, #13]
|
|
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
|
80056ee: 687b ldr r3, [r7, #4]
|
|
80056f0: 681b ldr r3, [r3, #0]
|
|
80056f2: 689b ldr r3, [r3, #8]
|
|
80056f4: 0f5b lsrs r3, r3, #29
|
|
80056f6: b2db uxtb r3, r3
|
|
80056f8: f003 0307 and.w r3, r3, #7
|
|
80056fc: 733b strb r3, [r7, #12]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
80056fe: 7bbb ldrb r3, [r7, #14]
|
|
8005700: 7b3a ldrb r2, [r7, #12]
|
|
8005702: 4911 ldr r1, [pc, #68] @ (8005748 <UARTEx_SetNbDataToProcess+0x94>)
|
|
8005704: 5c8a ldrb r2, [r1, r2]
|
|
8005706: fb02 f303 mul.w r3, r2, r3
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
800570a: 7b3a ldrb r2, [r7, #12]
|
|
800570c: 490f ldr r1, [pc, #60] @ (800574c <UARTEx_SetNbDataToProcess+0x98>)
|
|
800570e: 5c8a ldrb r2, [r1, r2]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8005710: fb93 f3f2 sdiv r3, r3, r2
|
|
8005714: b29a uxth r2, r3
|
|
8005716: 687b ldr r3, [r7, #4]
|
|
8005718: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
800571c: 7bfb ldrb r3, [r7, #15]
|
|
800571e: 7b7a ldrb r2, [r7, #13]
|
|
8005720: 4909 ldr r1, [pc, #36] @ (8005748 <UARTEx_SetNbDataToProcess+0x94>)
|
|
8005722: 5c8a ldrb r2, [r1, r2]
|
|
8005724: fb02 f303 mul.w r3, r2, r3
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
8005728: 7b7a ldrb r2, [r7, #13]
|
|
800572a: 4908 ldr r1, [pc, #32] @ (800574c <UARTEx_SetNbDataToProcess+0x98>)
|
|
800572c: 5c8a ldrb r2, [r1, r2]
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
800572e: fb93 f3f2 sdiv r3, r3, r2
|
|
8005732: b29a uxth r2, r3
|
|
8005734: 687b ldr r3, [r7, #4]
|
|
8005736: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
}
|
|
800573a: bf00 nop
|
|
800573c: 3714 adds r7, #20
|
|
800573e: 46bd mov sp, r7
|
|
8005740: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005744: 4770 bx lr
|
|
8005746: bf00 nop
|
|
8005748: 08005af0 .word 0x08005af0
|
|
800574c: 08005af8 .word 0x08005af8
|
|
|
|
08005750 <memset>:
|
|
8005750: 4402 add r2, r0
|
|
8005752: 4603 mov r3, r0
|
|
8005754: 4293 cmp r3, r2
|
|
8005756: d100 bne.n 800575a <memset+0xa>
|
|
8005758: 4770 bx lr
|
|
800575a: f803 1b01 strb.w r1, [r3], #1
|
|
800575e: e7f9 b.n 8005754 <memset+0x4>
|
|
|
|
08005760 <__libc_init_array>:
|
|
8005760: b570 push {r4, r5, r6, lr}
|
|
8005762: 4b0d ldr r3, [pc, #52] @ (8005798 <__libc_init_array+0x38>)
|
|
8005764: 4d0d ldr r5, [pc, #52] @ (800579c <__libc_init_array+0x3c>)
|
|
8005766: 1b5b subs r3, r3, r5
|
|
8005768: 109c asrs r4, r3, #2
|
|
800576a: 2600 movs r6, #0
|
|
800576c: 42a6 cmp r6, r4
|
|
800576e: d109 bne.n 8005784 <__libc_init_array+0x24>
|
|
8005770: f000 f828 bl 80057c4 <_init>
|
|
8005774: 4d0a ldr r5, [pc, #40] @ (80057a0 <__libc_init_array+0x40>)
|
|
8005776: 4b0b ldr r3, [pc, #44] @ (80057a4 <__libc_init_array+0x44>)
|
|
8005778: 1b5b subs r3, r3, r5
|
|
800577a: 109c asrs r4, r3, #2
|
|
800577c: 2600 movs r6, #0
|
|
800577e: 42a6 cmp r6, r4
|
|
8005780: d105 bne.n 800578e <__libc_init_array+0x2e>
|
|
8005782: bd70 pop {r4, r5, r6, pc}
|
|
8005784: f855 3b04 ldr.w r3, [r5], #4
|
|
8005788: 4798 blx r3
|
|
800578a: 3601 adds r6, #1
|
|
800578c: e7ee b.n 800576c <__libc_init_array+0xc>
|
|
800578e: f855 3b04 ldr.w r3, [r5], #4
|
|
8005792: 4798 blx r3
|
|
8005794: 3601 adds r6, #1
|
|
8005796: e7f2 b.n 800577e <__libc_init_array+0x1e>
|
|
8005798: 08005b08 .word 0x08005b08
|
|
800579c: 08005b08 .word 0x08005b08
|
|
80057a0: 08005b08 .word 0x08005b08
|
|
80057a4: 08005b0c .word 0x08005b0c
|
|
|
|
080057a8 <memcpy>:
|
|
80057a8: 440a add r2, r1
|
|
80057aa: 4291 cmp r1, r2
|
|
80057ac: f100 33ff add.w r3, r0, #4294967295
|
|
80057b0: d100 bne.n 80057b4 <memcpy+0xc>
|
|
80057b2: 4770 bx lr
|
|
80057b4: b510 push {r4, lr}
|
|
80057b6: f811 4b01 ldrb.w r4, [r1], #1
|
|
80057ba: f803 4f01 strb.w r4, [r3, #1]!
|
|
80057be: 4291 cmp r1, r2
|
|
80057c0: d1f9 bne.n 80057b6 <memcpy+0xe>
|
|
80057c2: bd10 pop {r4, pc}
|
|
|
|
080057c4 <_init>:
|
|
80057c4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80057c6: bf00 nop
|
|
80057c8: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80057ca: bc08 pop {r3}
|
|
80057cc: 469e mov lr, r3
|
|
80057ce: 4770 bx lr
|
|
|
|
080057d0 <_fini>:
|
|
80057d0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80057d2: bf00 nop
|
|
80057d4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80057d6: bc08 pop {r3}
|
|
80057d8: 469e mov lr, r3
|
|
80057da: 4770 bx lr
|