HW_DEPT_NEXIO_SIGN.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00005314 080001d8 080001d8 000011d8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000002ec 080054ec 080054ec 000064ec 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080057d8 080057d8 0000700c 2**0 CONTENTS, READONLY 4 .ARM 00000008 080057d8 080057d8 000067d8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080057e0 080057e0 0000700c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080057e0 080057e0 000067e0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 080057e4 080057e4 000067e4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 080057e8 00007000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000107c 2000000c 080057f4 0000700c 2**2 ALLOC 10 ._user_heap_stack 00000600 20001088 080057f4 00007088 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000700c 2**0 CONTENTS, READONLY 12 .debug_info 0000f3cc 00000000 00000000 0000703c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002085 00000000 00000000 00016408 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000c38 00000000 00000000 00018490 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000976 00000000 00000000 000190c8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001d1bb 00000000 00000000 00019a3e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0000ec7a 00000000 00000000 00036bf9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000b86c2 00000000 00000000 00045873 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000fdf35 2**0 CONTENTS, READONLY 20 .debug_frame 00002f7c 00000000 00000000 000fdf78 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000071 00000000 00000000 00100ef4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001d8 <__do_global_dtors_aux>: 80001d8: b510 push {r4, lr} 80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>) 80001dc: 7823 ldrb r3, [r4, #0] 80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16> 80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>) 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12> 80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>) 80001e6: f3af 8000 nop.w 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} 80001f0: 2000000c .word 0x2000000c 80001f4: 00000000 .word 0x00000000 80001f8: 080054d4 .word 0x080054d4 080001fc : 80001fc: b508 push {r3, lr} 80001fe: 4b03 ldr r3, [pc, #12] @ (800020c ) 8000200: b11b cbz r3, 800020a 8000202: 4903 ldr r1, [pc, #12] @ (8000210 ) 8000204: 4803 ldr r0, [pc, #12] @ (8000214 ) 8000206: f3af 8000 nop.w 800020a: bd08 pop {r3, pc} 800020c: 00000000 .word 0x00000000 8000210: 20000010 .word 0x20000010 8000214: 080054d4 .word 0x080054d4 08000218 <__aeabi_uldivmod>: 8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18> 800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18> 800021c: 2900 cmp r1, #0 800021e: bf08 it eq 8000220: 2800 cmpeq r0, #0 8000222: bf1c itt ne 8000224: f04f 31ff movne.w r1, #4294967295 8000228: f04f 30ff movne.w r0, #4294967295 800022c: f000 b988 b.w 8000540 <__aeabi_idiv0> 8000230: f1ad 0c08 sub.w ip, sp, #8 8000234: e96d ce04 strd ip, lr, [sp, #-16]! 8000238: f000 f806 bl 8000248 <__udivmoddi4> 800023c: f8dd e004 ldr.w lr, [sp, #4] 8000240: e9dd 2302 ldrd r2, r3, [sp, #8] 8000244: b004 add sp, #16 8000246: 4770 bx lr 08000248 <__udivmoddi4>: 8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800024c: 9d08 ldr r5, [sp, #32] 800024e: 460f mov r7, r1 8000250: 4604 mov r4, r0 8000252: 468c mov ip, r1 8000254: 2b00 cmp r3, #0 8000256: d148 bne.n 80002ea <__udivmoddi4+0xa2> 8000258: 428a cmp r2, r1 800025a: 4616 mov r6, r2 800025c: d961 bls.n 8000322 <__udivmoddi4+0xda> 800025e: fab2 f382 clz r3, r2 8000262: b14b cbz r3, 8000278 <__udivmoddi4+0x30> 8000264: f1c3 0220 rsb r2, r3, #32 8000268: fa01 fc03 lsl.w ip, r1, r3 800026c: fa20 f202 lsr.w r2, r0, r2 8000270: 409e lsls r6, r3 8000272: ea42 0c0c orr.w ip, r2, ip 8000276: 409c lsls r4, r3 8000278: ea4f 4e16 mov.w lr, r6, lsr #16 800027c: b2b7 uxth r7, r6 800027e: fbbc f1fe udiv r1, ip, lr 8000282: 0c22 lsrs r2, r4, #16 8000284: fb0e cc11 mls ip, lr, r1, ip 8000288: ea42 420c orr.w r2, r2, ip, lsl #16 800028c: fb01 f007 mul.w r0, r1, r7 8000290: 4290 cmp r0, r2 8000292: d909 bls.n 80002a8 <__udivmoddi4+0x60> 8000294: 18b2 adds r2, r6, r2 8000296: f101 3cff add.w ip, r1, #4294967295 800029a: f080 80ee bcs.w 800047a <__udivmoddi4+0x232> 800029e: 4290 cmp r0, r2 80002a0: f240 80eb bls.w 800047a <__udivmoddi4+0x232> 80002a4: 3902 subs r1, #2 80002a6: 4432 add r2, r6 80002a8: 1a12 subs r2, r2, r0 80002aa: b2a4 uxth r4, r4 80002ac: fbb2 f0fe udiv r0, r2, lr 80002b0: fb0e 2210 mls r2, lr, r0, r2 80002b4: ea44 4402 orr.w r4, r4, r2, lsl #16 80002b8: fb00 f707 mul.w r7, r0, r7 80002bc: 42a7 cmp r7, r4 80002be: d909 bls.n 80002d4 <__udivmoddi4+0x8c> 80002c0: 1934 adds r4, r6, r4 80002c2: f100 32ff add.w r2, r0, #4294967295 80002c6: f080 80da bcs.w 800047e <__udivmoddi4+0x236> 80002ca: 42a7 cmp r7, r4 80002cc: f240 80d7 bls.w 800047e <__udivmoddi4+0x236> 80002d0: 4434 add r4, r6 80002d2: 3802 subs r0, #2 80002d4: ea40 4001 orr.w r0, r0, r1, lsl #16 80002d8: 1be4 subs r4, r4, r7 80002da: 2100 movs r1, #0 80002dc: b11d cbz r5, 80002e6 <__udivmoddi4+0x9e> 80002de: 40dc lsrs r4, r3 80002e0: 2300 movs r3, #0 80002e2: e9c5 4300 strd r4, r3, [r5] 80002e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002ea: 428b cmp r3, r1 80002ec: d906 bls.n 80002fc <__udivmoddi4+0xb4> 80002ee: b10d cbz r5, 80002f4 <__udivmoddi4+0xac> 80002f0: e9c5 0100 strd r0, r1, [r5] 80002f4: 2100 movs r1, #0 80002f6: 4608 mov r0, r1 80002f8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002fc: fab3 f183 clz r1, r3 8000300: 2900 cmp r1, #0 8000302: d148 bne.n 8000396 <__udivmoddi4+0x14e> 8000304: 42bb cmp r3, r7 8000306: d302 bcc.n 800030e <__udivmoddi4+0xc6> 8000308: 4282 cmp r2, r0 800030a: f200 8107 bhi.w 800051c <__udivmoddi4+0x2d4> 800030e: 1a84 subs r4, r0, r2 8000310: eb67 0203 sbc.w r2, r7, r3 8000314: 2001 movs r0, #1 8000316: 4694 mov ip, r2 8000318: 2d00 cmp r5, #0 800031a: d0e4 beq.n 80002e6 <__udivmoddi4+0x9e> 800031c: e9c5 4c00 strd r4, ip, [r5] 8000320: e7e1 b.n 80002e6 <__udivmoddi4+0x9e> 8000322: 2a00 cmp r2, #0 8000324: f000 8092 beq.w 800044c <__udivmoddi4+0x204> 8000328: fab2 f382 clz r3, r2 800032c: 2b00 cmp r3, #0 800032e: f040 80a8 bne.w 8000482 <__udivmoddi4+0x23a> 8000332: 1a8a subs r2, r1, r2 8000334: ea4f 4e16 mov.w lr, r6, lsr #16 8000338: fa1f fc86 uxth.w ip, r6 800033c: 2101 movs r1, #1 800033e: 0c20 lsrs r0, r4, #16 8000340: fbb2 f7fe udiv r7, r2, lr 8000344: fb0e 2217 mls r2, lr, r7, r2 8000348: ea40 4202 orr.w r2, r0, r2, lsl #16 800034c: fb0c f007 mul.w r0, ip, r7 8000350: 4290 cmp r0, r2 8000352: d907 bls.n 8000364 <__udivmoddi4+0x11c> 8000354: 18b2 adds r2, r6, r2 8000356: f107 38ff add.w r8, r7, #4294967295 800035a: d202 bcs.n 8000362 <__udivmoddi4+0x11a> 800035c: 4290 cmp r0, r2 800035e: f200 80e2 bhi.w 8000526 <__udivmoddi4+0x2de> 8000362: 4647 mov r7, r8 8000364: 1a12 subs r2, r2, r0 8000366: b2a4 uxth r4, r4 8000368: fbb2 f0fe udiv r0, r2, lr 800036c: fb0e 2210 mls r2, lr, r0, r2 8000370: ea44 4402 orr.w r4, r4, r2, lsl #16 8000374: fb0c fc00 mul.w ip, ip, r0 8000378: 45a4 cmp ip, r4 800037a: d907 bls.n 800038c <__udivmoddi4+0x144> 800037c: 1934 adds r4, r6, r4 800037e: f100 32ff add.w r2, r0, #4294967295 8000382: d202 bcs.n 800038a <__udivmoddi4+0x142> 8000384: 45a4 cmp ip, r4 8000386: f200 80cb bhi.w 8000520 <__udivmoddi4+0x2d8> 800038a: 4610 mov r0, r2 800038c: eba4 040c sub.w r4, r4, ip 8000390: ea40 4007 orr.w r0, r0, r7, lsl #16 8000394: e7a2 b.n 80002dc <__udivmoddi4+0x94> 8000396: f1c1 0620 rsb r6, r1, #32 800039a: 408b lsls r3, r1 800039c: fa22 fc06 lsr.w ip, r2, r6 80003a0: ea4c 0c03 orr.w ip, ip, r3 80003a4: fa07 f401 lsl.w r4, r7, r1 80003a8: fa20 f306 lsr.w r3, r0, r6 80003ac: 40f7 lsrs r7, r6 80003ae: ea4f 491c mov.w r9, ip, lsr #16 80003b2: 4323 orrs r3, r4 80003b4: fa00 f801 lsl.w r8, r0, r1 80003b8: fa1f fe8c uxth.w lr, ip 80003bc: fbb7 f0f9 udiv r0, r7, r9 80003c0: 0c1c lsrs r4, r3, #16 80003c2: fb09 7710 mls r7, r9, r0, r7 80003c6: ea44 4407 orr.w r4, r4, r7, lsl #16 80003ca: fb00 f70e mul.w r7, r0, lr 80003ce: 42a7 cmp r7, r4 80003d0: fa02 f201 lsl.w r2, r2, r1 80003d4: d90a bls.n 80003ec <__udivmoddi4+0x1a4> 80003d6: eb1c 0404 adds.w r4, ip, r4 80003da: f100 3aff add.w sl, r0, #4294967295 80003de: f080 809b bcs.w 8000518 <__udivmoddi4+0x2d0> 80003e2: 42a7 cmp r7, r4 80003e4: f240 8098 bls.w 8000518 <__udivmoddi4+0x2d0> 80003e8: 3802 subs r0, #2 80003ea: 4464 add r4, ip 80003ec: 1be4 subs r4, r4, r7 80003ee: b29f uxth r7, r3 80003f0: fbb4 f3f9 udiv r3, r4, r9 80003f4: fb09 4413 mls r4, r9, r3, r4 80003f8: ea47 4404 orr.w r4, r7, r4, lsl #16 80003fc: fb03 fe0e mul.w lr, r3, lr 8000400: 45a6 cmp lr, r4 8000402: d909 bls.n 8000418 <__udivmoddi4+0x1d0> 8000404: eb1c 0404 adds.w r4, ip, r4 8000408: f103 37ff add.w r7, r3, #4294967295 800040c: f080 8082 bcs.w 8000514 <__udivmoddi4+0x2cc> 8000410: 45a6 cmp lr, r4 8000412: d97f bls.n 8000514 <__udivmoddi4+0x2cc> 8000414: 3b02 subs r3, #2 8000416: 4464 add r4, ip 8000418: ea43 4000 orr.w r0, r3, r0, lsl #16 800041c: eba4 040e sub.w r4, r4, lr 8000420: fba0 e702 umull lr, r7, r0, r2 8000424: 42bc cmp r4, r7 8000426: 4673 mov r3, lr 8000428: 46b9 mov r9, r7 800042a: d363 bcc.n 80004f4 <__udivmoddi4+0x2ac> 800042c: d060 beq.n 80004f0 <__udivmoddi4+0x2a8> 800042e: b15d cbz r5, 8000448 <__udivmoddi4+0x200> 8000430: ebb8 0203 subs.w r2, r8, r3 8000434: eb64 0409 sbc.w r4, r4, r9 8000438: fa04 f606 lsl.w r6, r4, r6 800043c: fa22 f301 lsr.w r3, r2, r1 8000440: 431e orrs r6, r3 8000442: 40cc lsrs r4, r1 8000444: e9c5 6400 strd r6, r4, [r5] 8000448: 2100 movs r1, #0 800044a: e74c b.n 80002e6 <__udivmoddi4+0x9e> 800044c: 0862 lsrs r2, r4, #1 800044e: 0848 lsrs r0, r1, #1 8000450: ea42 71c1 orr.w r1, r2, r1, lsl #31 8000454: 0c0b lsrs r3, r1, #16 8000456: ea43 4300 orr.w r3, r3, r0, lsl #16 800045a: b28a uxth r2, r1 800045c: ea42 4203 orr.w r2, r2, r3, lsl #16 8000460: fbb3 f1f6 udiv r1, r3, r6 8000464: 07e4 lsls r4, r4, #31 8000466: 46b4 mov ip, r6 8000468: 4637 mov r7, r6 800046a: 46b6 mov lr, r6 800046c: 231f movs r3, #31 800046e: fbb0 f0f6 udiv r0, r0, r6 8000472: 1bd2 subs r2, r2, r7 8000474: ea41 4100 orr.w r1, r1, r0, lsl #16 8000478: e761 b.n 800033e <__udivmoddi4+0xf6> 800047a: 4661 mov r1, ip 800047c: e714 b.n 80002a8 <__udivmoddi4+0x60> 800047e: 4610 mov r0, r2 8000480: e728 b.n 80002d4 <__udivmoddi4+0x8c> 8000482: f1c3 0120 rsb r1, r3, #32 8000486: fa20 f201 lsr.w r2, r0, r1 800048a: 409e lsls r6, r3 800048c: fa27 f101 lsr.w r1, r7, r1 8000490: 409f lsls r7, r3 8000492: 433a orrs r2, r7 8000494: ea4f 4e16 mov.w lr, r6, lsr #16 8000498: fa1f fc86 uxth.w ip, r6 800049c: fbb1 f7fe udiv r7, r1, lr 80004a0: fb0e 1017 mls r0, lr, r7, r1 80004a4: 0c11 lsrs r1, r2, #16 80004a6: ea41 4100 orr.w r1, r1, r0, lsl #16 80004aa: fb07 f80c mul.w r8, r7, ip 80004ae: 4588 cmp r8, r1 80004b0: fa04 f403 lsl.w r4, r4, r3 80004b4: d93a bls.n 800052c <__udivmoddi4+0x2e4> 80004b6: 1871 adds r1, r6, r1 80004b8: f107 30ff add.w r0, r7, #4294967295 80004bc: d201 bcs.n 80004c2 <__udivmoddi4+0x27a> 80004be: 4588 cmp r8, r1 80004c0: d81f bhi.n 8000502 <__udivmoddi4+0x2ba> 80004c2: eba1 0108 sub.w r1, r1, r8 80004c6: fbb1 f8fe udiv r8, r1, lr 80004ca: fb08 f70c mul.w r7, r8, ip 80004ce: fb0e 1118 mls r1, lr, r8, r1 80004d2: b292 uxth r2, r2 80004d4: ea42 4201 orr.w r2, r2, r1, lsl #16 80004d8: 42ba cmp r2, r7 80004da: d22f bcs.n 800053c <__udivmoddi4+0x2f4> 80004dc: 18b2 adds r2, r6, r2 80004de: f108 31ff add.w r1, r8, #4294967295 80004e2: d2c6 bcs.n 8000472 <__udivmoddi4+0x22a> 80004e4: 42ba cmp r2, r7 80004e6: d2c4 bcs.n 8000472 <__udivmoddi4+0x22a> 80004e8: f1a8 0102 sub.w r1, r8, #2 80004ec: 4432 add r2, r6 80004ee: e7c0 b.n 8000472 <__udivmoddi4+0x22a> 80004f0: 45f0 cmp r8, lr 80004f2: d29c bcs.n 800042e <__udivmoddi4+0x1e6> 80004f4: ebbe 0302 subs.w r3, lr, r2 80004f8: eb67 070c sbc.w r7, r7, ip 80004fc: 3801 subs r0, #1 80004fe: 46b9 mov r9, r7 8000500: e795 b.n 800042e <__udivmoddi4+0x1e6> 8000502: eba6 0808 sub.w r8, r6, r8 8000506: 4441 add r1, r8 8000508: 1eb8 subs r0, r7, #2 800050a: fbb1 f8fe udiv r8, r1, lr 800050e: fb08 f70c mul.w r7, r8, ip 8000512: e7dc b.n 80004ce <__udivmoddi4+0x286> 8000514: 463b mov r3, r7 8000516: e77f b.n 8000418 <__udivmoddi4+0x1d0> 8000518: 4650 mov r0, sl 800051a: e767 b.n 80003ec <__udivmoddi4+0x1a4> 800051c: 4608 mov r0, r1 800051e: e6fb b.n 8000318 <__udivmoddi4+0xd0> 8000520: 4434 add r4, r6 8000522: 3802 subs r0, #2 8000524: e732 b.n 800038c <__udivmoddi4+0x144> 8000526: 3f02 subs r7, #2 8000528: 4432 add r2, r6 800052a: e71b b.n 8000364 <__udivmoddi4+0x11c> 800052c: eba1 0108 sub.w r1, r1, r8 8000530: 4638 mov r0, r7 8000532: fbb1 f8fe udiv r8, r1, lr 8000536: fb08 f70c mul.w r7, r8, ip 800053a: e7c8 b.n 80004ce <__udivmoddi4+0x286> 800053c: 4641 mov r1, r8 800053e: e798 b.n 8000472 <__udivmoddi4+0x22a> 08000540 <__aeabi_idiv0>: 8000540: 4770 bx lr 8000542: bf00 nop 08000544 : {0x61,0x51,0x49,0x45,0x43}, /* 'Z' */ }; /* ── Microsecond busy-wait using DWT cycle counter ── */ static void delay_us(uint32_t us) { 8000544: b480 push {r7} 8000546: b085 sub sp, #20 8000548: af00 add r7, sp, #0 800054a: 6078 str r0, [r7, #4] uint32_t start = DWT->CYCCNT; 800054c: 4b0d ldr r3, [pc, #52] @ (8000584 ) 800054e: 685b ldr r3, [r3, #4] 8000550: 60fb str r3, [r7, #12] uint32_t ticks = (SystemCoreClock / 1000000U) * us; 8000552: 4b0d ldr r3, [pc, #52] @ (8000588 ) 8000554: 681b ldr r3, [r3, #0] 8000556: 4a0d ldr r2, [pc, #52] @ (800058c ) 8000558: fba2 2303 umull r2, r3, r2, r3 800055c: 0c9a lsrs r2, r3, #18 800055e: 687b ldr r3, [r7, #4] 8000560: fb02 f303 mul.w r3, r2, r3 8000564: 60bb str r3, [r7, #8] while ((DWT->CYCCNT - start) < ticks); 8000566: bf00 nop 8000568: 4b06 ldr r3, [pc, #24] @ (8000584 ) 800056a: 685a ldr r2, [r3, #4] 800056c: 68fb ldr r3, [r7, #12] 800056e: 1ad3 subs r3, r2, r3 8000570: 68ba ldr r2, [r7, #8] 8000572: 429a cmp r2, r3 8000574: d8f8 bhi.n 8000568 } 8000576: bf00 nop 8000578: bf00 nop 800057a: 3714 adds r7, #20 800057c: 46bd mov sp, r7 800057e: f85d 7b04 ldr.w r7, [sp], #4 8000582: 4770 bx lr 8000584: e0001000 .word 0xe0001000 8000588: 20000000 .word 0x20000000 800058c: 431bde83 .word 0x431bde83 08000590 : /* ── Turn all row pins off (HIGH = ULN2803A pulls gate low = MOSFET off) ── */ static void all_rows_off(void) { 8000590: b580 push {r7, lr} 8000592: b082 sub sp, #8 8000594: af00 add r7, sp, #0 for (int i = 0; i < ROWS; i++) 8000596: 2300 movs r3, #0 8000598: 607b str r3, [r7, #4] 800059a: e00f b.n 80005bc HAL_GPIO_WritePin(ROW_PINS[i].port, ROW_PINS[i].pin, GPIO_PIN_SET); 800059c: 4a0b ldr r2, [pc, #44] @ (80005cc ) 800059e: 687b ldr r3, [r7, #4] 80005a0: f852 0033 ldr.w r0, [r2, r3, lsl #3] 80005a4: 4a09 ldr r2, [pc, #36] @ (80005cc ) 80005a6: 687b ldr r3, [r7, #4] 80005a8: 00db lsls r3, r3, #3 80005aa: 4413 add r3, r2 80005ac: 889b ldrh r3, [r3, #4] 80005ae: 2201 movs r2, #1 80005b0: 4619 mov r1, r3 80005b2: f001 fb5d bl 8001c70 for (int i = 0; i < ROWS; i++) 80005b6: 687b ldr r3, [r7, #4] 80005b8: 3301 adds r3, #1 80005ba: 607b str r3, [r7, #4] 80005bc: 687b ldr r3, [r7, #4] 80005be: 2b06 cmp r3, #6 80005c0: ddec ble.n 800059c } 80005c2: bf00 nop 80005c4: bf00 nop 80005c6: 3708 adds r7, #8 80005c8: 46bd mov sp, r7 80005ca: bd80 pop {r7, pc} 80005cc: 080054ec .word 0x080054ec 080005d0 : /* ── Send one row of column data via SPI then enable that row ── */ static void display_refresh(void) { 80005d0: b580 push {r7, lr} 80005d2: b082 sub sp, #8 80005d4: af00 add r7, sp, #0 for (int row = 0; row < ROWS; row++) { 80005d6: 2300 movs r3, #0 80005d8: 607b str r3, [r7, #4] 80005da: e022 b.n 8000622 all_rows_off(); 80005dc: f7ff ffd8 bl 8000590 HAL_SPI_Transmit(&hspi1, fb[row], NUM_CHIPS, HAL_MAX_DELAY); 80005e0: 687a ldr r2, [r7, #4] 80005e2: 4613 mov r3, r2 80005e4: 005b lsls r3, r3, #1 80005e6: 4413 add r3, r2 80005e8: 009b lsls r3, r3, #2 80005ea: 4a12 ldr r2, [pc, #72] @ (8000634 ) 80005ec: 1899 adds r1, r3, r2 80005ee: f04f 33ff mov.w r3, #4294967295 80005f2: 220c movs r2, #12 80005f4: 4810 ldr r0, [pc, #64] @ (8000638 ) 80005f6: f002 fbd0 bl 8002d9a /* LOW = ULN2803A releases gate = MOSFET on = row enabled */ HAL_GPIO_WritePin(ROW_PINS[row].port, ROW_PINS[row].pin, GPIO_PIN_RESET); 80005fa: 4a10 ldr r2, [pc, #64] @ (800063c ) 80005fc: 687b ldr r3, [r7, #4] 80005fe: f852 0033 ldr.w r0, [r2, r3, lsl #3] 8000602: 4a0e ldr r2, [pc, #56] @ (800063c ) 8000604: 687b ldr r3, [r7, #4] 8000606: 00db lsls r3, r3, #3 8000608: 4413 add r3, r2 800060a: 889b ldrh r3, [r3, #4] 800060c: 2200 movs r2, #0 800060e: 4619 mov r1, r3 8000610: f001 fb2e bl 8001c70 delay_us(ROW_DWELL); 8000614: f44f 70fa mov.w r0, #500 @ 0x1f4 8000618: f7ff ff94 bl 8000544 for (int row = 0; row < ROWS; row++) { 800061c: 687b ldr r3, [r7, #4] 800061e: 3301 adds r3, #1 8000620: 607b str r3, [r7, #4] 8000622: 687b ldr r3, [r7, #4] 8000624: 2b06 cmp r3, #6 8000626: ddd9 ble.n 80005dc } all_rows_off(); 8000628: f7ff ffb2 bl 8000590 } 800062c: bf00 nop 800062e: 3708 adds r7, #8 8000630: 46bd mov sp, r7 8000632: bd80 pop {r7, pc} 8000634: 20000120 .word 0x20000120 8000638: 20000028 .word 0x20000028 800063c: 080054ec .word 0x080054ec 08000640 : /* ── Render message string into wide[] pixel buffer ── */ static void render_message(const char *msg) { 8000640: b580 push {r7, lr} 8000642: b086 sub sp, #24 8000644: af00 add r7, sp, #0 8000646: 6078 str r0, [r7, #4] memset(wide, 0, sizeof(wide)); 8000648: f44f 6260 mov.w r2, #3584 @ 0xe00 800064c: 2100 movs r1, #0 800064e: 4833 ldr r0, [pc, #204] @ (800071c ) 8000650: f004 ff06 bl 8005460 uint16_t col = COLS; /* lead with one blank screen so text scrolls in */ 8000654: 2360 movs r3, #96 @ 0x60 8000656: 82fb strh r3, [r7, #22] while (*msg && col < (WIDE_COLS - 6)) { 8000658: e04c b.n 80006f4 uint8_t c = (uint8_t)*msg++; 800065a: 687b ldr r3, [r7, #4] 800065c: 1c5a adds r2, r3, #1 800065e: 607a str r2, [r7, #4] 8000660: 781b ldrb r3, [r3, #0] 8000662: 757b strb r3, [r7, #21] /* Convert lowercase to uppercase */ if (c >= 'a' && c <= 'z') c -= 32; 8000664: 7d7b ldrb r3, [r7, #21] 8000666: 2b60 cmp r3, #96 @ 0x60 8000668: d905 bls.n 8000676 800066a: 7d7b ldrb r3, [r7, #21] 800066c: 2b7a cmp r3, #122 @ 0x7a 800066e: d802 bhi.n 8000676 8000670: 7d7b ldrb r3, [r7, #21] 8000672: 3b20 subs r3, #32 8000674: 757b strb r3, [r7, #21] if (c >= 32 && c <= 90) { 8000676: 7d7b ldrb r3, [r7, #21] 8000678: 2b1f cmp r3, #31 800067a: d938 bls.n 80006ee 800067c: 7d7b ldrb r3, [r7, #21] 800067e: 2b5a cmp r3, #90 @ 0x5a 8000680: d835 bhi.n 80006ee const uint8_t *glyph = FONT[c - 32]; 8000682: 7d7b ldrb r3, [r7, #21] 8000684: f1a3 0220 sub.w r2, r3, #32 8000688: 4613 mov r3, r2 800068a: 009b lsls r3, r3, #2 800068c: 4413 add r3, r2 800068e: 4a24 ldr r2, [pc, #144] @ (8000720 ) 8000690: 4413 add r3, r2 8000692: 60bb str r3, [r7, #8] for (int g = 0; g < 5 && col < WIDE_COLS; g++, col++) { 8000694: 2300 movs r3, #0 8000696: 613b str r3, [r7, #16] 8000698: e022 b.n 80006e0 for (int row = 0; row < ROWS; row++) { 800069a: 2300 movs r3, #0 800069c: 60fb str r3, [r7, #12] 800069e: e016 b.n 80006ce wide[row][col] = (glyph[g] >> row) & 1; 80006a0: 693b ldr r3, [r7, #16] 80006a2: 68ba ldr r2, [r7, #8] 80006a4: 4413 add r3, r2 80006a6: 781b ldrb r3, [r3, #0] 80006a8: 461a mov r2, r3 80006aa: 68fb ldr r3, [r7, #12] 80006ac: fa42 f303 asr.w r3, r2, r3 80006b0: b2da uxtb r2, r3 80006b2: 8afb ldrh r3, [r7, #22] 80006b4: f002 0201 and.w r2, r2, #1 80006b8: b2d0 uxtb r0, r2 80006ba: 4918 ldr r1, [pc, #96] @ (800071c ) 80006bc: 68fa ldr r2, [r7, #12] 80006be: 0252 lsls r2, r2, #9 80006c0: 440a add r2, r1 80006c2: 4413 add r3, r2 80006c4: 4602 mov r2, r0 80006c6: 701a strb r2, [r3, #0] for (int row = 0; row < ROWS; row++) { 80006c8: 68fb ldr r3, [r7, #12] 80006ca: 3301 adds r3, #1 80006cc: 60fb str r3, [r7, #12] 80006ce: 68fb ldr r3, [r7, #12] 80006d0: 2b06 cmp r3, #6 80006d2: dde5 ble.n 80006a0 for (int g = 0; g < 5 && col < WIDE_COLS; g++, col++) { 80006d4: 693b ldr r3, [r7, #16] 80006d6: 3301 adds r3, #1 80006d8: 613b str r3, [r7, #16] 80006da: 8afb ldrh r3, [r7, #22] 80006dc: 3301 adds r3, #1 80006de: 82fb strh r3, [r7, #22] 80006e0: 693b ldr r3, [r7, #16] 80006e2: 2b04 cmp r3, #4 80006e4: dc03 bgt.n 80006ee 80006e6: 8afb ldrh r3, [r7, #22] 80006e8: f5b3 7f00 cmp.w r3, #512 @ 0x200 80006ec: d3d5 bcc.n 800069a } } } col++; /* one gap column between characters */ 80006ee: 8afb ldrh r3, [r7, #22] 80006f0: 3301 adds r3, #1 80006f2: 82fb strh r3, [r7, #22] while (*msg && col < (WIDE_COLS - 6)) { 80006f4: 687b ldr r3, [r7, #4] 80006f6: 781b ldrb r3, [r3, #0] 80006f8: 2b00 cmp r3, #0 80006fa: d003 beq.n 8000704 80006fc: 8afb ldrh r3, [r7, #22] 80006fe: f5b3 7ffd cmp.w r3, #506 @ 0x1fa 8000702: d3aa bcc.n 800065a } wide_cols = col + COLS; /* scroll until text fully exits left edge */ 8000704: 8afb ldrh r3, [r7, #22] 8000706: 3360 adds r3, #96 @ 0x60 8000708: b29a uxth r2, r3 800070a: 4b06 ldr r3, [pc, #24] @ (8000724 ) 800070c: 801a strh r2, [r3, #0] scroll_x = 0; 800070e: 4b06 ldr r3, [pc, #24] @ (8000728 ) 8000710: 2200 movs r2, #0 8000712: 601a str r2, [r3, #0] } 8000714: bf00 nop 8000716: 3718 adds r7, #24 8000718: 46bd mov sp, r7 800071a: bd80 pop {r7, pc} 800071c: 20000174 .word 0x20000174 8000720: 08005524 .word 0x08005524 8000724: 20000f74 .word 0x20000f74 8000728: 20000f78 .word 0x20000f78 0800072c : /* ── Copy current scroll window from wide[] into fb[][] ── */ static void update_fb_from_scroll(void) { 800072c: b580 push {r7, lr} 800072e: b086 sub sp, #24 8000730: af00 add r7, sp, #0 for (int row = 0; row < ROWS; row++) { 8000732: 2300 movs r3, #0 8000734: 617b str r3, [r7, #20] 8000736: e058 b.n 80007ea memset(fb[row], 0, NUM_CHIPS); 8000738: 697a ldr r2, [r7, #20] 800073a: 4613 mov r3, r2 800073c: 005b lsls r3, r3, #1 800073e: 4413 add r3, r2 8000740: 009b lsls r3, r3, #2 8000742: 4a2e ldr r2, [pc, #184] @ (80007fc ) 8000744: 4413 add r3, r2 8000746: 220c movs r2, #12 8000748: 2100 movs r1, #0 800074a: 4618 mov r0, r3 800074c: f004 fe88 bl 8005460 for (int col = 0; col < COLS; col++) { 8000750: 2300 movs r3, #0 8000752: 613b str r3, [r7, #16] 8000754: e043 b.n 80007de uint16_t src = (uint16_t)(scroll_x + col); 8000756: 4b2a ldr r3, [pc, #168] @ (8000800 ) 8000758: 681b ldr r3, [r3, #0] 800075a: b29a uxth r2, r3 800075c: 693b ldr r3, [r7, #16] 800075e: b29b uxth r3, r3 8000760: 4413 add r3, r2 8000762: 81fb strh r3, [r7, #14] if (src < WIDE_COLS && wide[row][src]) { 8000764: 89fb ldrh r3, [r7, #14] 8000766: f5b3 7f00 cmp.w r3, #512 @ 0x200 800076a: d235 bcs.n 80007d8 800076c: 89fb ldrh r3, [r7, #14] 800076e: 4925 ldr r1, [pc, #148] @ (8000804 ) 8000770: 697a ldr r2, [r7, #20] 8000772: 0252 lsls r2, r2, #9 8000774: 440a add r2, r1 8000776: 4413 add r3, r2 8000778: 781b ldrb r3, [r3, #0] 800077a: 2b00 cmp r3, #0 800077c: d02c beq.n 80007d8 int chip = col / 8; 800077e: 693b ldr r3, [r7, #16] 8000780: 2b00 cmp r3, #0 8000782: da00 bge.n 8000786 8000784: 3307 adds r3, #7 8000786: 10db asrs r3, r3, #3 8000788: 60bb str r3, [r7, #8] int bit = 7 - (col % 8); 800078a: 693b ldr r3, [r7, #16] 800078c: 425a negs r2, r3 800078e: f003 0307 and.w r3, r3, #7 8000792: f002 0207 and.w r2, r2, #7 8000796: bf58 it pl 8000798: 4253 negpl r3, r2 800079a: f1c3 0307 rsb r3, r3, #7 800079e: 607b str r3, [r7, #4] fb[row][chip] |= (uint8_t)(1 << bit); 80007a0: 4916 ldr r1, [pc, #88] @ (80007fc ) 80007a2: 697a ldr r2, [r7, #20] 80007a4: 4613 mov r3, r2 80007a6: 005b lsls r3, r3, #1 80007a8: 4413 add r3, r2 80007aa: 009b lsls r3, r3, #2 80007ac: 18ca adds r2, r1, r3 80007ae: 68bb ldr r3, [r7, #8] 80007b0: 4413 add r3, r2 80007b2: 781a ldrb r2, [r3, #0] 80007b4: 2101 movs r1, #1 80007b6: 687b ldr r3, [r7, #4] 80007b8: fa01 f303 lsl.w r3, r1, r3 80007bc: b2db uxtb r3, r3 80007be: 4313 orrs r3, r2 80007c0: b2d8 uxtb r0, r3 80007c2: 490e ldr r1, [pc, #56] @ (80007fc ) 80007c4: 697a ldr r2, [r7, #20] 80007c6: 4613 mov r3, r2 80007c8: 005b lsls r3, r3, #1 80007ca: 4413 add r3, r2 80007cc: 009b lsls r3, r3, #2 80007ce: 18ca adds r2, r1, r3 80007d0: 68bb ldr r3, [r7, #8] 80007d2: 4413 add r3, r2 80007d4: 4602 mov r2, r0 80007d6: 701a strb r2, [r3, #0] for (int col = 0; col < COLS; col++) { 80007d8: 693b ldr r3, [r7, #16] 80007da: 3301 adds r3, #1 80007dc: 613b str r3, [r7, #16] 80007de: 693b ldr r3, [r7, #16] 80007e0: 2b5f cmp r3, #95 @ 0x5f 80007e2: ddb8 ble.n 8000756 for (int row = 0; row < ROWS; row++) { 80007e4: 697b ldr r3, [r7, #20] 80007e6: 3301 adds r3, #1 80007e8: 617b str r3, [r7, #20] 80007ea: 697b ldr r3, [r7, #20] 80007ec: 2b06 cmp r3, #6 80007ee: dda3 ble.n 8000738 } } } } 80007f0: bf00 nop 80007f2: bf00 nop 80007f4: 3718 adds r7, #24 80007f6: 46bd mov sp, r7 80007f8: bd80 pop {r7, pc} 80007fa: bf00 nop 80007fc: 20000120 .word 0x20000120 8000800: 20000f78 .word 0x20000f78 8000804: 20000174 .word 0x20000174 08000808 : }; /* ── Render logo into fb mask_col: columns < mask_col are hidden (wipe reveals right-to-left), -1 = show all ── */ static void render_logo(int star_col, int text_col, int mask_col) { 8000808: b580 push {r7, lr} 800080a: b08e sub sp, #56 @ 0x38 800080c: af00 add r7, sp, #0 800080e: 60f8 str r0, [r7, #12] 8000810: 60b9 str r1, [r7, #8] 8000812: 607a str r2, [r7, #4] memset(fb, 0, sizeof(fb)); 8000814: 2254 movs r2, #84 @ 0x54 8000816: 2100 movs r1, #0 8000818: 4860 ldr r0, [pc, #384] @ (800099c ) 800081a: f004 fe21 bl 8005460 /* Draw star */ for (int row = 0; row < 7; row++) { 800081e: 2300 movs r3, #0 8000820: 637b str r3, [r7, #52] @ 0x34 8000822: e056 b.n 80008d2 for (int sc = 0; sc < 11; sc++) { 8000824: 2300 movs r3, #0 8000826: 633b str r3, [r7, #48] @ 0x30 8000828: e04d b.n 80008c6 int col = star_col + sc; 800082a: 68fa ldr r2, [r7, #12] 800082c: 6b3b ldr r3, [r7, #48] @ 0x30 800082e: 4413 add r3, r2 8000830: 61bb str r3, [r7, #24] if (col >= 0 && col < COLS && STAR[row][sc]) { 8000832: 69bb ldr r3, [r7, #24] 8000834: 2b00 cmp r3, #0 8000836: db43 blt.n 80008c0 8000838: 69bb ldr r3, [r7, #24] 800083a: 2b5f cmp r3, #95 @ 0x5f 800083c: dc40 bgt.n 80008c0 800083e: 4958 ldr r1, [pc, #352] @ (80009a0 ) 8000840: 6b7a ldr r2, [r7, #52] @ 0x34 8000842: 4613 mov r3, r2 8000844: 009b lsls r3, r3, #2 8000846: 4413 add r3, r2 8000848: 005b lsls r3, r3, #1 800084a: 4413 add r3, r2 800084c: 18ca adds r2, r1, r3 800084e: 6b3b ldr r3, [r7, #48] @ 0x30 8000850: 4413 add r3, r2 8000852: 781b ldrb r3, [r3, #0] 8000854: 2b00 cmp r3, #0 8000856: d033 beq.n 80008c0 if (mask_col < 0 || col >= mask_col) { 8000858: 687b ldr r3, [r7, #4] 800085a: 2b00 cmp r3, #0 800085c: db03 blt.n 8000866 800085e: 69ba ldr r2, [r7, #24] 8000860: 687b ldr r3, [r7, #4] 8000862: 429a cmp r2, r3 8000864: db2c blt.n 80008c0 int chip = col / 8; 8000866: 69bb ldr r3, [r7, #24] 8000868: 2b00 cmp r3, #0 800086a: da00 bge.n 800086e 800086c: 3307 adds r3, #7 800086e: 10db asrs r3, r3, #3 8000870: 617b str r3, [r7, #20] int bit = 7 - (col % 8); 8000872: 69bb ldr r3, [r7, #24] 8000874: 425a negs r2, r3 8000876: f003 0307 and.w r3, r3, #7 800087a: f002 0207 and.w r2, r2, #7 800087e: bf58 it pl 8000880: 4253 negpl r3, r2 8000882: f1c3 0307 rsb r3, r3, #7 8000886: 613b str r3, [r7, #16] fb[row][chip] |= (uint8_t)(1 << bit); 8000888: 4944 ldr r1, [pc, #272] @ (800099c ) 800088a: 6b7a ldr r2, [r7, #52] @ 0x34 800088c: 4613 mov r3, r2 800088e: 005b lsls r3, r3, #1 8000890: 4413 add r3, r2 8000892: 009b lsls r3, r3, #2 8000894: 18ca adds r2, r1, r3 8000896: 697b ldr r3, [r7, #20] 8000898: 4413 add r3, r2 800089a: 781a ldrb r2, [r3, #0] 800089c: 2101 movs r1, #1 800089e: 693b ldr r3, [r7, #16] 80008a0: fa01 f303 lsl.w r3, r1, r3 80008a4: b2db uxtb r3, r3 80008a6: 4313 orrs r3, r2 80008a8: b2d8 uxtb r0, r3 80008aa: 493c ldr r1, [pc, #240] @ (800099c ) 80008ac: 6b7a ldr r2, [r7, #52] @ 0x34 80008ae: 4613 mov r3, r2 80008b0: 005b lsls r3, r3, #1 80008b2: 4413 add r3, r2 80008b4: 009b lsls r3, r3, #2 80008b6: 18ca adds r2, r1, r3 80008b8: 697b ldr r3, [r7, #20] 80008ba: 4413 add r3, r2 80008bc: 4602 mov r2, r0 80008be: 701a strb r2, [r3, #0] for (int sc = 0; sc < 11; sc++) { 80008c0: 6b3b ldr r3, [r7, #48] @ 0x30 80008c2: 3301 adds r3, #1 80008c4: 633b str r3, [r7, #48] @ 0x30 80008c6: 6b3b ldr r3, [r7, #48] @ 0x30 80008c8: 2b0a cmp r3, #10 80008ca: ddae ble.n 800082a for (int row = 0; row < 7; row++) { 80008cc: 6b7b ldr r3, [r7, #52] @ 0x34 80008ce: 3301 adds r3, #1 80008d0: 637b str r3, [r7, #52] @ 0x34 80008d2: 6b7b ldr r3, [r7, #52] @ 0x34 80008d4: 2b06 cmp r3, #6 80008d6: dda5 ble.n 8000824 } } } /* Draw ARRIVE text */ for (int row = 0; row < 7; row++) { 80008d8: 2300 movs r3, #0 80008da: 62fb str r3, [r7, #44] @ 0x2c 80008dc: e055 b.n 800098a for (int tc = 0; tc < 36; tc++) { 80008de: 2300 movs r3, #0 80008e0: 62bb str r3, [r7, #40] @ 0x28 80008e2: e04c b.n 800097e int col = text_col + tc; 80008e4: 68ba ldr r2, [r7, #8] 80008e6: 6abb ldr r3, [r7, #40] @ 0x28 80008e8: 4413 add r3, r2 80008ea: 627b str r3, [r7, #36] @ 0x24 if (col >= 0 && col < COLS && ARRIVE_GLYPH[row][tc]) { 80008ec: 6a7b ldr r3, [r7, #36] @ 0x24 80008ee: 2b00 cmp r3, #0 80008f0: db42 blt.n 8000978 80008f2: 6a7b ldr r3, [r7, #36] @ 0x24 80008f4: 2b5f cmp r3, #95 @ 0x5f 80008f6: dc3f bgt.n 8000978 80008f8: 492a ldr r1, [pc, #168] @ (80009a4 ) 80008fa: 6afa ldr r2, [r7, #44] @ 0x2c 80008fc: 4613 mov r3, r2 80008fe: 00db lsls r3, r3, #3 8000900: 4413 add r3, r2 8000902: 009b lsls r3, r3, #2 8000904: 18ca adds r2, r1, r3 8000906: 6abb ldr r3, [r7, #40] @ 0x28 8000908: 4413 add r3, r2 800090a: 781b ldrb r3, [r3, #0] 800090c: 2b00 cmp r3, #0 800090e: d033 beq.n 8000978 if (mask_col < 0 || col >= mask_col) { 8000910: 687b ldr r3, [r7, #4] 8000912: 2b00 cmp r3, #0 8000914: db03 blt.n 800091e 8000916: 6a7a ldr r2, [r7, #36] @ 0x24 8000918: 687b ldr r3, [r7, #4] 800091a: 429a cmp r2, r3 800091c: db2c blt.n 8000978 int chip = col / 8; 800091e: 6a7b ldr r3, [r7, #36] @ 0x24 8000920: 2b00 cmp r3, #0 8000922: da00 bge.n 8000926 8000924: 3307 adds r3, #7 8000926: 10db asrs r3, r3, #3 8000928: 623b str r3, [r7, #32] int bit = 7 - (col % 8); 800092a: 6a7b ldr r3, [r7, #36] @ 0x24 800092c: 425a negs r2, r3 800092e: f003 0307 and.w r3, r3, #7 8000932: f002 0207 and.w r2, r2, #7 8000936: bf58 it pl 8000938: 4253 negpl r3, r2 800093a: f1c3 0307 rsb r3, r3, #7 800093e: 61fb str r3, [r7, #28] fb[row][chip] |= (uint8_t)(1 << bit); 8000940: 4916 ldr r1, [pc, #88] @ (800099c ) 8000942: 6afa ldr r2, [r7, #44] @ 0x2c 8000944: 4613 mov r3, r2 8000946: 005b lsls r3, r3, #1 8000948: 4413 add r3, r2 800094a: 009b lsls r3, r3, #2 800094c: 18ca adds r2, r1, r3 800094e: 6a3b ldr r3, [r7, #32] 8000950: 4413 add r3, r2 8000952: 781a ldrb r2, [r3, #0] 8000954: 2101 movs r1, #1 8000956: 69fb ldr r3, [r7, #28] 8000958: fa01 f303 lsl.w r3, r1, r3 800095c: b2db uxtb r3, r3 800095e: 4313 orrs r3, r2 8000960: b2d8 uxtb r0, r3 8000962: 490e ldr r1, [pc, #56] @ (800099c ) 8000964: 6afa ldr r2, [r7, #44] @ 0x2c 8000966: 4613 mov r3, r2 8000968: 005b lsls r3, r3, #1 800096a: 4413 add r3, r2 800096c: 009b lsls r3, r3, #2 800096e: 18ca adds r2, r1, r3 8000970: 6a3b ldr r3, [r7, #32] 8000972: 4413 add r3, r2 8000974: 4602 mov r2, r0 8000976: 701a strb r2, [r3, #0] for (int tc = 0; tc < 36; tc++) { 8000978: 6abb ldr r3, [r7, #40] @ 0x28 800097a: 3301 adds r3, #1 800097c: 62bb str r3, [r7, #40] @ 0x28 800097e: 6abb ldr r3, [r7, #40] @ 0x28 8000980: 2b23 cmp r3, #35 @ 0x23 8000982: ddaf ble.n 80008e4 for (int row = 0; row < 7; row++) { 8000984: 6afb ldr r3, [r7, #44] @ 0x2c 8000986: 3301 adds r3, #1 8000988: 62fb str r3, [r7, #44] @ 0x2c 800098a: 6afb ldr r3, [r7, #44] @ 0x2c 800098c: 2b06 cmp r3, #6 800098e: dda6 ble.n 80008de } } } } } 8000990: bf00 nop 8000992: bf00 nop 8000994: 3738 adds r7, #56 @ 0x38 8000996: 46bd mov sp, r7 8000998: bd80 pop {r7, pc} 800099a: bf00 nop 800099c: 20000120 .word 0x20000120 80009a0: 0800564c .word 0x0800564c 80009a4: 0800569c .word 0x0800569c 080009a8 : /* ── Blank fb but keep specific rows lit (bitmask) ── */ static void render_logo_rows(int star_col, int text_col, uint8_t row_mask) { 80009a8: b580 push {r7, lr} 80009aa: b08e sub sp, #56 @ 0x38 80009ac: af00 add r7, sp, #0 80009ae: 60f8 str r0, [r7, #12] 80009b0: 60b9 str r1, [r7, #8] 80009b2: 4613 mov r3, r2 80009b4: 71fb strb r3, [r7, #7] memset(fb, 0, sizeof(fb)); 80009b6: 2254 movs r2, #84 @ 0x54 80009b8: 2100 movs r1, #0 80009ba: 485b ldr r0, [pc, #364] @ (8000b28 ) 80009bc: f004 fd50 bl 8005460 for (int row = 0; row < 7; row++) { 80009c0: 2300 movs r3, #0 80009c2: 637b str r3, [r7, #52] @ 0x34 80009c4: e0a6 b.n 8000b14 if (!(row_mask & (1 << row))) continue; 80009c6: 79fa ldrb r2, [r7, #7] 80009c8: 6b7b ldr r3, [r7, #52] @ 0x34 80009ca: fa42 f303 asr.w r3, r2, r3 80009ce: f003 0301 and.w r3, r3, #1 80009d2: 2b00 cmp r3, #0 80009d4: f000 809a beq.w 8000b0c for (int sc = 0; sc < 11; sc++) { 80009d8: 2300 movs r3, #0 80009da: 633b str r3, [r7, #48] @ 0x30 80009dc: e046 b.n 8000a6c int col = star_col + sc; 80009de: 68fa ldr r2, [r7, #12] 80009e0: 6b3b ldr r3, [r7, #48] @ 0x30 80009e2: 4413 add r3, r2 80009e4: 61fb str r3, [r7, #28] if (col >= 0 && col < COLS && STAR[row][sc]) { 80009e6: 69fb ldr r3, [r7, #28] 80009e8: 2b00 cmp r3, #0 80009ea: db3c blt.n 8000a66 80009ec: 69fb ldr r3, [r7, #28] 80009ee: 2b5f cmp r3, #95 @ 0x5f 80009f0: dc39 bgt.n 8000a66 80009f2: 494e ldr r1, [pc, #312] @ (8000b2c ) 80009f4: 6b7a ldr r2, [r7, #52] @ 0x34 80009f6: 4613 mov r3, r2 80009f8: 009b lsls r3, r3, #2 80009fa: 4413 add r3, r2 80009fc: 005b lsls r3, r3, #1 80009fe: 4413 add r3, r2 8000a00: 18ca adds r2, r1, r3 8000a02: 6b3b ldr r3, [r7, #48] @ 0x30 8000a04: 4413 add r3, r2 8000a06: 781b ldrb r3, [r3, #0] 8000a08: 2b00 cmp r3, #0 8000a0a: d02c beq.n 8000a66 int chip = col / 8; int bit = 7 - (col % 8); 8000a0c: 69fb ldr r3, [r7, #28] 8000a0e: 2b00 cmp r3, #0 8000a10: da00 bge.n 8000a14 8000a12: 3307 adds r3, #7 8000a14: 10db asrs r3, r3, #3 8000a16: 61bb str r3, [r7, #24] 8000a18: 69fb ldr r3, [r7, #28] 8000a1a: 425a negs r2, r3 8000a1c: f003 0307 and.w r3, r3, #7 8000a20: f002 0207 and.w r2, r2, #7 8000a24: bf58 it pl 8000a26: 4253 negpl r3, r2 8000a28: f1c3 0307 rsb r3, r3, #7 8000a2c: 617b str r3, [r7, #20] fb[row][chip] |= (uint8_t)(1 << bit); 8000a2e: 493e ldr r1, [pc, #248] @ (8000b28 ) 8000a30: 6b7a ldr r2, [r7, #52] @ 0x34 8000a32: 4613 mov r3, r2 8000a34: 005b lsls r3, r3, #1 8000a36: 4413 add r3, r2 8000a38: 009b lsls r3, r3, #2 8000a3a: 18ca adds r2, r1, r3 8000a3c: 69bb ldr r3, [r7, #24] 8000a3e: 4413 add r3, r2 8000a40: 781a ldrb r2, [r3, #0] 8000a42: 2101 movs r1, #1 8000a44: 697b ldr r3, [r7, #20] 8000a46: fa01 f303 lsl.w r3, r1, r3 8000a4a: b2db uxtb r3, r3 8000a4c: 4313 orrs r3, r2 8000a4e: b2d8 uxtb r0, r3 8000a50: 4935 ldr r1, [pc, #212] @ (8000b28 ) 8000a52: 6b7a ldr r2, [r7, #52] @ 0x34 8000a54: 4613 mov r3, r2 8000a56: 005b lsls r3, r3, #1 8000a58: 4413 add r3, r2 8000a5a: 009b lsls r3, r3, #2 8000a5c: 18ca adds r2, r1, r3 8000a5e: 69bb ldr r3, [r7, #24] 8000a60: 4413 add r3, r2 8000a62: 4602 mov r2, r0 8000a64: 701a strb r2, [r3, #0] for (int sc = 0; sc < 11; sc++) { 8000a66: 6b3b ldr r3, [r7, #48] @ 0x30 8000a68: 3301 adds r3, #1 8000a6a: 633b str r3, [r7, #48] @ 0x30 8000a6c: 6b3b ldr r3, [r7, #48] @ 0x30 8000a6e: 2b0a cmp r3, #10 8000a70: ddb5 ble.n 80009de } } for (int tc = 0; tc < 30; tc++) { 8000a72: 2300 movs r3, #0 8000a74: 62fb str r3, [r7, #44] @ 0x2c 8000a76: e045 b.n 8000b04 int col = text_col + tc; 8000a78: 68ba ldr r2, [r7, #8] 8000a7a: 6afb ldr r3, [r7, #44] @ 0x2c 8000a7c: 4413 add r3, r2 8000a7e: 62bb str r3, [r7, #40] @ 0x28 if (col >= 0 && col < COLS && ARRIVE_GLYPH[row][tc]) { 8000a80: 6abb ldr r3, [r7, #40] @ 0x28 8000a82: 2b00 cmp r3, #0 8000a84: db3b blt.n 8000afe 8000a86: 6abb ldr r3, [r7, #40] @ 0x28 8000a88: 2b5f cmp r3, #95 @ 0x5f 8000a8a: dc38 bgt.n 8000afe 8000a8c: 4928 ldr r1, [pc, #160] @ (8000b30 ) 8000a8e: 6b7a ldr r2, [r7, #52] @ 0x34 8000a90: 4613 mov r3, r2 8000a92: 00db lsls r3, r3, #3 8000a94: 4413 add r3, r2 8000a96: 009b lsls r3, r3, #2 8000a98: 18ca adds r2, r1, r3 8000a9a: 6afb ldr r3, [r7, #44] @ 0x2c 8000a9c: 4413 add r3, r2 8000a9e: 781b ldrb r3, [r3, #0] 8000aa0: 2b00 cmp r3, #0 8000aa2: d02c beq.n 8000afe int chip = col / 8; int bit = 7 - (col % 8); 8000aa4: 6abb ldr r3, [r7, #40] @ 0x28 8000aa6: 2b00 cmp r3, #0 8000aa8: da00 bge.n 8000aac 8000aaa: 3307 adds r3, #7 8000aac: 10db asrs r3, r3, #3 8000aae: 627b str r3, [r7, #36] @ 0x24 8000ab0: 6abb ldr r3, [r7, #40] @ 0x28 8000ab2: 425a negs r2, r3 8000ab4: f003 0307 and.w r3, r3, #7 8000ab8: f002 0207 and.w r2, r2, #7 8000abc: bf58 it pl 8000abe: 4253 negpl r3, r2 8000ac0: f1c3 0307 rsb r3, r3, #7 8000ac4: 623b str r3, [r7, #32] fb[row][chip] |= (uint8_t)(1 << bit); 8000ac6: 4918 ldr r1, [pc, #96] @ (8000b28 ) 8000ac8: 6b7a ldr r2, [r7, #52] @ 0x34 8000aca: 4613 mov r3, r2 8000acc: 005b lsls r3, r3, #1 8000ace: 4413 add r3, r2 8000ad0: 009b lsls r3, r3, #2 8000ad2: 18ca adds r2, r1, r3 8000ad4: 6a7b ldr r3, [r7, #36] @ 0x24 8000ad6: 4413 add r3, r2 8000ad8: 781a ldrb r2, [r3, #0] 8000ada: 2101 movs r1, #1 8000adc: 6a3b ldr r3, [r7, #32] 8000ade: fa01 f303 lsl.w r3, r1, r3 8000ae2: b2db uxtb r3, r3 8000ae4: 4313 orrs r3, r2 8000ae6: b2d8 uxtb r0, r3 8000ae8: 490f ldr r1, [pc, #60] @ (8000b28 ) 8000aea: 6b7a ldr r2, [r7, #52] @ 0x34 8000aec: 4613 mov r3, r2 8000aee: 005b lsls r3, r3, #1 8000af0: 4413 add r3, r2 8000af2: 009b lsls r3, r3, #2 8000af4: 18ca adds r2, r1, r3 8000af6: 6a7b ldr r3, [r7, #36] @ 0x24 8000af8: 4413 add r3, r2 8000afa: 4602 mov r2, r0 8000afc: 701a strb r2, [r3, #0] for (int tc = 0; tc < 30; tc++) { 8000afe: 6afb ldr r3, [r7, #44] @ 0x2c 8000b00: 3301 adds r3, #1 8000b02: 62fb str r3, [r7, #44] @ 0x2c 8000b04: 6afb ldr r3, [r7, #44] @ 0x2c 8000b06: 2b1d cmp r3, #29 8000b08: ddb6 ble.n 8000a78 8000b0a: e000 b.n 8000b0e if (!(row_mask & (1 << row))) continue; 8000b0c: bf00 nop for (int row = 0; row < 7; row++) { 8000b0e: 6b7b ldr r3, [r7, #52] @ 0x34 8000b10: 3301 adds r3, #1 8000b12: 637b str r3, [r7, #52] @ 0x34 8000b14: 6b7b ldr r3, [r7, #52] @ 0x34 8000b16: 2b06 cmp r3, #6 8000b18: f77f af55 ble.w 80009c6 } } } } 8000b1c: bf00 nop 8000b1e: bf00 nop 8000b20: 3738 adds r7, #56 @ 0x38 8000b22: 46bd mov sp, r7 8000b24: bd80 pop {r7, pc} 8000b26: bf00 nop 8000b28: 20000120 .word 0x20000120 8000b2c: 0800564c .word 0x0800564c 8000b30: 0800569c .word 0x0800569c 08000b34 : /* ── Refresh for a given number of milliseconds ── */ static void refresh_for(uint32_t ms) { 8000b34: b580 push {r7, lr} 8000b36: b084 sub sp, #16 8000b38: af00 add r7, sp, #0 8000b3a: 6078 str r0, [r7, #4] uint32_t t = HAL_GetTick(); 8000b3c: f000 fd2c bl 8001598 8000b40: 60f8 str r0, [r7, #12] while ((HAL_GetTick() - t) < ms) { display_refresh(); } 8000b42: e001 b.n 8000b48 8000b44: f7ff fd44 bl 80005d0 8000b48: f000 fd26 bl 8001598 8000b4c: 4602 mov r2, r0 8000b4e: 68fb ldr r3, [r7, #12] 8000b50: 1ad3 subs r3, r2, r3 8000b52: 687a ldr r2, [r7, #4] 8000b54: 429a cmp r2, r3 8000b56: d8f5 bhi.n 8000b44 } 8000b58: bf00 nop 8000b5a: bf00 nop 8000b5c: 3710 adds r7, #16 8000b5e: 46bd mov sp, r7 8000b60: bd80 pop {r7, pc} ... 08000b64 : /* ── Arrive boot animation ── */ static void arrive_animation(void) { 8000b64: b580 push {r7, lr} 8000b66: b092 sub sp, #72 @ 0x48 8000b68: af00 add r7, sp, #0 /* Logo layout — text LEFT, star RIGHT: ARRIVE = 36 cols, gap = 2, star = 11 cols → total = 49 cols centred on 96: start = (96 - 49) / 2 = 23 text_col = 23, star_col = 23 + 36 + 2 = 61 */ const int text_col = 23; 8000b6a: 2317 movs r3, #23 8000b6c: 633b str r3, [r7, #48] @ 0x30 const int star_col = 61; 8000b6e: 233d movs r3, #61 @ 0x3d 8000b70: 62fb str r3, [r7, #44] @ 0x2c /* ── Phase 1: Star builds from centre outward ── */ /* Frame 1 — just centre cross */ memset(fb, 0, sizeof(fb)); 8000b72: 2254 movs r2, #84 @ 0x54 8000b74: 2100 movs r1, #0 8000b76: 48b4 ldr r0, [pc, #720] @ (8000e48 ) 8000b78: f004 fc72 bl 8005460 for (int row = 0; row < 7; row++) { 8000b7c: 2300 movs r3, #0 8000b7e: 647b str r3, [r7, #68] @ 0x44 8000b80: e032 b.n 8000be8 int col = star_col + 4; /* centre column of star */ 8000b82: 6afb ldr r3, [r7, #44] @ 0x2c 8000b84: 3304 adds r3, #4 8000b86: 60fb str r3, [r7, #12] int chip = col / 8; int bit = 7 - (col % 8); 8000b88: 68fb ldr r3, [r7, #12] 8000b8a: 2b00 cmp r3, #0 8000b8c: da00 bge.n 8000b90 8000b8e: 3307 adds r3, #7 8000b90: 10db asrs r3, r3, #3 8000b92: 60bb str r3, [r7, #8] 8000b94: 68fb ldr r3, [r7, #12] 8000b96: 425a negs r2, r3 8000b98: f003 0307 and.w r3, r3, #7 8000b9c: f002 0207 and.w r2, r2, #7 8000ba0: bf58 it pl 8000ba2: 4253 negpl r3, r2 8000ba4: f1c3 0307 rsb r3, r3, #7 8000ba8: 607b str r3, [r7, #4] fb[row][chip] |= (uint8_t)(1 << bit); 8000baa: 49a7 ldr r1, [pc, #668] @ (8000e48 ) 8000bac: 6c7a ldr r2, [r7, #68] @ 0x44 8000bae: 4613 mov r3, r2 8000bb0: 005b lsls r3, r3, #1 8000bb2: 4413 add r3, r2 8000bb4: 009b lsls r3, r3, #2 8000bb6: 18ca adds r2, r1, r3 8000bb8: 68bb ldr r3, [r7, #8] 8000bba: 4413 add r3, r2 8000bbc: 781a ldrb r2, [r3, #0] 8000bbe: 2101 movs r1, #1 8000bc0: 687b ldr r3, [r7, #4] 8000bc2: fa01 f303 lsl.w r3, r1, r3 8000bc6: b2db uxtb r3, r3 8000bc8: 4313 orrs r3, r2 8000bca: b2d8 uxtb r0, r3 8000bcc: 499e ldr r1, [pc, #632] @ (8000e48 ) 8000bce: 6c7a ldr r2, [r7, #68] @ 0x44 8000bd0: 4613 mov r3, r2 8000bd2: 005b lsls r3, r3, #1 8000bd4: 4413 add r3, r2 8000bd6: 009b lsls r3, r3, #2 8000bd8: 18ca adds r2, r1, r3 8000bda: 68bb ldr r3, [r7, #8] 8000bdc: 4413 add r3, r2 8000bde: 4602 mov r2, r0 8000be0: 701a strb r2, [r3, #0] for (int row = 0; row < 7; row++) { 8000be2: 6c7b ldr r3, [r7, #68] @ 0x44 8000be4: 3301 adds r3, #1 8000be6: 647b str r3, [r7, #68] @ 0x44 8000be8: 6c7b ldr r3, [r7, #68] @ 0x44 8000bea: 2b06 cmp r3, #6 8000bec: ddc9 ble.n 8000b82 } /* horizontal bar centre */ for (int sc = 3; sc <= 5; sc++) { 8000bee: 2303 movs r3, #3 8000bf0: 643b str r3, [r7, #64] @ 0x40 8000bf2: e029 b.n 8000c48 int col = star_col + sc; 8000bf4: 6afa ldr r2, [r7, #44] @ 0x2c 8000bf6: 6c3b ldr r3, [r7, #64] @ 0x40 8000bf8: 4413 add r3, r2 8000bfa: 61bb str r3, [r7, #24] int chip = col / 8; int bit = 7 - (col % 8); 8000bfc: 69bb ldr r3, [r7, #24] 8000bfe: 2b00 cmp r3, #0 8000c00: da00 bge.n 8000c04 8000c02: 3307 adds r3, #7 8000c04: 10db asrs r3, r3, #3 8000c06: 617b str r3, [r7, #20] 8000c08: 69bb ldr r3, [r7, #24] 8000c0a: 425a negs r2, r3 8000c0c: f003 0307 and.w r3, r3, #7 8000c10: f002 0207 and.w r2, r2, #7 8000c14: bf58 it pl 8000c16: 4253 negpl r3, r2 8000c18: f1c3 0307 rsb r3, r3, #7 8000c1c: 613b str r3, [r7, #16] fb[3][chip] |= (uint8_t)(1 << bit); 8000c1e: 4a8a ldr r2, [pc, #552] @ (8000e48 ) 8000c20: 697b ldr r3, [r7, #20] 8000c22: 4413 add r3, r2 8000c24: 3324 adds r3, #36 @ 0x24 8000c26: 781a ldrb r2, [r3, #0] 8000c28: 2101 movs r1, #1 8000c2a: 693b ldr r3, [r7, #16] 8000c2c: fa01 f303 lsl.w r3, r1, r3 8000c30: b2db uxtb r3, r3 8000c32: 4313 orrs r3, r2 8000c34: b2d9 uxtb r1, r3 8000c36: 4a84 ldr r2, [pc, #528] @ (8000e48 ) 8000c38: 697b ldr r3, [r7, #20] 8000c3a: 4413 add r3, r2 8000c3c: 3324 adds r3, #36 @ 0x24 8000c3e: 460a mov r2, r1 8000c40: 701a strb r2, [r3, #0] for (int sc = 3; sc <= 5; sc++) { 8000c42: 6c3b ldr r3, [r7, #64] @ 0x40 8000c44: 3301 adds r3, #1 8000c46: 643b str r3, [r7, #64] @ 0x40 8000c48: 6c3b ldr r3, [r7, #64] @ 0x40 8000c4a: 2b05 cmp r3, #5 8000c4c: ddd2 ble.n 8000bf4 } refresh_for(120); 8000c4e: 2078 movs r0, #120 @ 0x78 8000c50: f7ff ff70 bl 8000b34 /* Frame 2 — inner star shape */ memset(fb, 0, sizeof(fb)); 8000c54: 2254 movs r2, #84 @ 0x54 8000c56: 2100 movs r1, #0 8000c58: 487b ldr r0, [pc, #492] @ (8000e48 ) 8000c5a: f004 fc01 bl 8005460 for (int row = 0; row < 7; row++) { 8000c5e: 2300 movs r3, #0 8000c60: 63fb str r3, [r7, #60] @ 0x3c 8000c62: e049 b.n 8000cf8 for (int sc = 3; sc <= 7; sc++) { 8000c64: 2303 movs r3, #3 8000c66: 63bb str r3, [r7, #56] @ 0x38 8000c68: e040 b.n 8000cec if (STAR[row][sc]) { 8000c6a: 4978 ldr r1, [pc, #480] @ (8000e4c ) 8000c6c: 6bfa ldr r2, [r7, #60] @ 0x3c 8000c6e: 4613 mov r3, r2 8000c70: 009b lsls r3, r3, #2 8000c72: 4413 add r3, r2 8000c74: 005b lsls r3, r3, #1 8000c76: 4413 add r3, r2 8000c78: 18ca adds r2, r1, r3 8000c7a: 6bbb ldr r3, [r7, #56] @ 0x38 8000c7c: 4413 add r3, r2 8000c7e: 781b ldrb r3, [r3, #0] 8000c80: 2b00 cmp r3, #0 8000c82: d030 beq.n 8000ce6 int col = star_col + sc; 8000c84: 6afa ldr r2, [r7, #44] @ 0x2c 8000c86: 6bbb ldr r3, [r7, #56] @ 0x38 8000c88: 4413 add r3, r2 8000c8a: 627b str r3, [r7, #36] @ 0x24 int chip = col / 8; int bit = 7 - (col % 8); 8000c8c: 6a7b ldr r3, [r7, #36] @ 0x24 8000c8e: 2b00 cmp r3, #0 8000c90: da00 bge.n 8000c94 8000c92: 3307 adds r3, #7 8000c94: 10db asrs r3, r3, #3 8000c96: 623b str r3, [r7, #32] 8000c98: 6a7b ldr r3, [r7, #36] @ 0x24 8000c9a: 425a negs r2, r3 8000c9c: f003 0307 and.w r3, r3, #7 8000ca0: f002 0207 and.w r2, r2, #7 8000ca4: bf58 it pl 8000ca6: 4253 negpl r3, r2 8000ca8: f1c3 0307 rsb r3, r3, #7 8000cac: 61fb str r3, [r7, #28] fb[row][chip] |= (uint8_t)(1 << bit); 8000cae: 4966 ldr r1, [pc, #408] @ (8000e48 ) 8000cb0: 6bfa ldr r2, [r7, #60] @ 0x3c 8000cb2: 4613 mov r3, r2 8000cb4: 005b lsls r3, r3, #1 8000cb6: 4413 add r3, r2 8000cb8: 009b lsls r3, r3, #2 8000cba: 18ca adds r2, r1, r3 8000cbc: 6a3b ldr r3, [r7, #32] 8000cbe: 4413 add r3, r2 8000cc0: 781a ldrb r2, [r3, #0] 8000cc2: 2101 movs r1, #1 8000cc4: 69fb ldr r3, [r7, #28] 8000cc6: fa01 f303 lsl.w r3, r1, r3 8000cca: b2db uxtb r3, r3 8000ccc: 4313 orrs r3, r2 8000cce: b2d8 uxtb r0, r3 8000cd0: 495d ldr r1, [pc, #372] @ (8000e48 ) 8000cd2: 6bfa ldr r2, [r7, #60] @ 0x3c 8000cd4: 4613 mov r3, r2 8000cd6: 005b lsls r3, r3, #1 8000cd8: 4413 add r3, r2 8000cda: 009b lsls r3, r3, #2 8000cdc: 18ca adds r2, r1, r3 8000cde: 6a3b ldr r3, [r7, #32] 8000ce0: 4413 add r3, r2 8000ce2: 4602 mov r2, r0 8000ce4: 701a strb r2, [r3, #0] for (int sc = 3; sc <= 7; sc++) { 8000ce6: 6bbb ldr r3, [r7, #56] @ 0x38 8000ce8: 3301 adds r3, #1 8000cea: 63bb str r3, [r7, #56] @ 0x38 8000cec: 6bbb ldr r3, [r7, #56] @ 0x38 8000cee: 2b07 cmp r3, #7 8000cf0: ddbb ble.n 8000c6a for (int row = 0; row < 7; row++) { 8000cf2: 6bfb ldr r3, [r7, #60] @ 0x3c 8000cf4: 3301 adds r3, #1 8000cf6: 63fb str r3, [r7, #60] @ 0x3c 8000cf8: 6bfb ldr r3, [r7, #60] @ 0x3c 8000cfa: 2b06 cmp r3, #6 8000cfc: ddb2 ble.n 8000c64 } } } refresh_for(120); 8000cfe: 2078 movs r0, #120 @ 0x78 8000d00: f7ff ff18 bl 8000b34 /* Frame 3 — full star, text still hidden */ render_logo(star_col, text_col, star_col); /* mask hides everything left of star */ 8000d04: 6afa ldr r2, [r7, #44] @ 0x2c 8000d06: 6b39 ldr r1, [r7, #48] @ 0x30 8000d08: 6af8 ldr r0, [r7, #44] @ 0x2c 8000d0a: f7ff fd7d bl 8000808 refresh_for(150); 8000d0e: 2096 movs r0, #150 @ 0x96 8000d10: f7ff ff10 bl 8000b34 /* ── Phase 2: Glint pulse ── */ memset(fb, 0, sizeof(fb)); 8000d14: 2254 movs r2, #84 @ 0x54 8000d16: 2100 movs r1, #0 8000d18: 484b ldr r0, [pc, #300] @ (8000e48 ) 8000d1a: f004 fba1 bl 8005460 refresh_for(80); 8000d1e: 2050 movs r0, #80 @ 0x50 8000d20: f7ff ff08 bl 8000b34 render_logo(star_col, text_col, star_col); 8000d24: 6afa ldr r2, [r7, #44] @ 0x2c 8000d26: 6b39 ldr r1, [r7, #48] @ 0x30 8000d28: 6af8 ldr r0, [r7, #44] @ 0x2c 8000d2a: f7ff fd6d bl 8000808 refresh_for(80); 8000d2e: 2050 movs r0, #80 @ 0x50 8000d30: f7ff ff00 bl 8000b34 memset(fb, 0, sizeof(fb)); 8000d34: 2254 movs r2, #84 @ 0x54 8000d36: 2100 movs r1, #0 8000d38: 4843 ldr r0, [pc, #268] @ (8000e48 ) 8000d3a: f004 fb91 bl 8005460 refresh_for(60); 8000d3e: 203c movs r0, #60 @ 0x3c 8000d40: f7ff fef8 bl 8000b34 render_logo(star_col, text_col, star_col); 8000d44: 6afa ldr r2, [r7, #44] @ 0x2c 8000d46: 6b39 ldr r1, [r7, #48] @ 0x30 8000d48: 6af8 ldr r0, [r7, #44] @ 0x2c 8000d4a: f7ff fd5d bl 8000808 refresh_for(100); 8000d4e: 2064 movs r0, #100 @ 0x64 8000d50: f7ff fef0 bl 8000b34 /* ── Phase 3: Wipe right-to-left — reveal ARRIVE sweeping from star leftward ── */ for (int mask = star_col; mask >= text_col - 1; mask -= 2) { 8000d54: 6afb ldr r3, [r7, #44] @ 0x2c 8000d56: 637b str r3, [r7, #52] @ 0x34 8000d58: e00a b.n 8000d70 render_logo(star_col, text_col, mask); 8000d5a: 6b7a ldr r2, [r7, #52] @ 0x34 8000d5c: 6b39 ldr r1, [r7, #48] @ 0x30 8000d5e: 6af8 ldr r0, [r7, #44] @ 0x2c 8000d60: f7ff fd52 bl 8000808 refresh_for(18); 8000d64: 2012 movs r0, #18 8000d66: f7ff fee5 bl 8000b34 for (int mask = star_col; mask >= text_col - 1; mask -= 2) { 8000d6a: 6b7b ldr r3, [r7, #52] @ 0x34 8000d6c: 3b02 subs r3, #2 8000d6e: 637b str r3, [r7, #52] @ 0x34 8000d70: 6b3b ldr r3, [r7, #48] @ 0x30 8000d72: 3b01 subs r3, #1 8000d74: 6b7a ldr r2, [r7, #52] @ 0x34 8000d76: 429a cmp r2, r3 8000d78: daef bge.n 8000d5a } render_logo(star_col, text_col, -1); 8000d7a: f04f 32ff mov.w r2, #4294967295 8000d7e: 6b39 ldr r1, [r7, #48] @ 0x30 8000d80: 6af8 ldr r0, [r7, #44] @ 0x2c 8000d82: f7ff fd41 bl 8000808 refresh_for(18); 8000d86: 2012 movs r0, #18 8000d88: f7ff fed4 bl 8000b34 /* ── Phase 4: Hold ── */ refresh_for(2000); 8000d8c: f44f 60fa mov.w r0, #2000 @ 0x7d0 8000d90: f7ff fed0 bl 8000b34 /* ── Phase 5: Fade out — rows extinguish top+bottom inward ── */ /* Order: 0,6 then 1,5 then 2,4 then 3 */ uint8_t row_mask = 0x7F; /* all 7 rows on */ 8000d94: 237f movs r3, #127 @ 0x7f 8000d96: f887 302b strb.w r3, [r7, #43] @ 0x2b row_mask &= ~(1 << 0); row_mask &= ~(1 << 6); 8000d9a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000d9e: f023 0301 bic.w r3, r3, #1 8000da2: f887 302b strb.w r3, [r7, #43] @ 0x2b 8000da6: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000daa: f023 0340 bic.w r3, r3, #64 @ 0x40 8000dae: f887 302b strb.w r3, [r7, #43] @ 0x2b render_logo_rows(star_col, text_col, row_mask); refresh_for(80); 8000db2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000db6: 461a mov r2, r3 8000db8: 6b39 ldr r1, [r7, #48] @ 0x30 8000dba: 6af8 ldr r0, [r7, #44] @ 0x2c 8000dbc: f7ff fdf4 bl 80009a8 8000dc0: 2050 movs r0, #80 @ 0x50 8000dc2: f7ff feb7 bl 8000b34 row_mask &= ~(1 << 1); row_mask &= ~(1 << 5); 8000dc6: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000dca: f023 0302 bic.w r3, r3, #2 8000dce: f887 302b strb.w r3, [r7, #43] @ 0x2b 8000dd2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000dd6: f023 0320 bic.w r3, r3, #32 8000dda: f887 302b strb.w r3, [r7, #43] @ 0x2b render_logo_rows(star_col, text_col, row_mask); refresh_for(80); 8000dde: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000de2: 461a mov r2, r3 8000de4: 6b39 ldr r1, [r7, #48] @ 0x30 8000de6: 6af8 ldr r0, [r7, #44] @ 0x2c 8000de8: f7ff fdde bl 80009a8 8000dec: 2050 movs r0, #80 @ 0x50 8000dee: f7ff fea1 bl 8000b34 row_mask &= ~(1 << 2); row_mask &= ~(1 << 4); 8000df2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000df6: f023 0304 bic.w r3, r3, #4 8000dfa: f887 302b strb.w r3, [r7, #43] @ 0x2b 8000dfe: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000e02: f023 0310 bic.w r3, r3, #16 8000e06: f887 302b strb.w r3, [r7, #43] @ 0x2b render_logo_rows(star_col, text_col, row_mask); refresh_for(80); 8000e0a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000e0e: 461a mov r2, r3 8000e10: 6b39 ldr r1, [r7, #48] @ 0x30 8000e12: 6af8 ldr r0, [r7, #44] @ 0x2c 8000e14: f7ff fdc8 bl 80009a8 8000e18: 2050 movs r0, #80 @ 0x50 8000e1a: f7ff fe8b bl 8000b34 row_mask &= ~(1 << 3); 8000e1e: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8000e22: f023 0308 bic.w r3, r3, #8 8000e26: f887 302b strb.w r3, [r7, #43] @ 0x2b memset(fb, 0, sizeof(fb)); refresh_for(80); 8000e2a: 2254 movs r2, #84 @ 0x54 8000e2c: 2100 movs r1, #0 8000e2e: 4806 ldr r0, [pc, #24] @ (8000e48 ) 8000e30: f004 fb16 bl 8005460 8000e34: 2050 movs r0, #80 @ 0x50 8000e36: f7ff fe7d bl 8000b34 /* Brief blank before scroll */ refresh_for(200); 8000e3a: 20c8 movs r0, #200 @ 0xc8 8000e3c: f7ff fe7a bl 8000b34 } 8000e40: bf00 nop 8000e42: 3748 adds r7, #72 @ 0x48 8000e44: 46bd mov sp, r7 8000e46: bd80 pop {r7, pc} 8000e48: 20000120 .word 0x20000120 8000e4c: 0800564c .word 0x0800564c 08000e50 : void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000e50: b580 push {r7, lr} 8000e52: b084 sub sp, #16 8000e54: af00 add r7, sp, #0 8000e56: 6078 str r0, [r7, #4] if (huart->Instance == USART2) { 8000e58: 687b ldr r3, [r7, #4] 8000e5a: 681b ldr r3, [r3, #0] 8000e5c: 4a1d ldr r2, [pc, #116] @ (8000ed4 ) 8000e5e: 4293 cmp r3, r2 8000e60: d134 bne.n 8000ecc char b = (char)uart_rx_byte; 8000e62: 4b1d ldr r3, [pc, #116] @ (8000ed8 ) 8000e64: 781b ldrb r3, [r3, #0] 8000e66: 73fb strb r3, [r7, #15] if (b == '\n' || b == '\r') { 8000e68: 7bfb ldrb r3, [r7, #15] 8000e6a: 2b0a cmp r3, #10 8000e6c: d002 beq.n 8000e74 8000e6e: 7bfb ldrb r3, [r7, #15] 8000e70: 2b0d cmp r3, #13 8000e72: d118 bne.n 8000ea6 if (uart_idx > 0) { 8000e74: 4b19 ldr r3, [pc, #100] @ (8000edc ) 8000e76: 781b ldrb r3, [r3, #0] 8000e78: 2b00 cmp r3, #0 8000e7a: d022 beq.n 8000ec2 uart_buf[uart_idx] = '\0'; 8000e7c: 4b17 ldr r3, [pc, #92] @ (8000edc ) 8000e7e: 781b ldrb r3, [r3, #0] 8000e80: 461a mov r2, r3 8000e82: 4b17 ldr r3, [pc, #92] @ (8000ee0 ) 8000e84: 2100 movs r1, #0 8000e86: 5499 strb r1, [r3, r2] memcpy(message, uart_buf, uart_idx + 1); 8000e88: 4b14 ldr r3, [pc, #80] @ (8000edc ) 8000e8a: 781b ldrb r3, [r3, #0] 8000e8c: 3301 adds r3, #1 8000e8e: 461a mov r2, r3 8000e90: 4913 ldr r1, [pc, #76] @ (8000ee0 ) 8000e92: 4814 ldr r0, [pc, #80] @ (8000ee4 ) 8000e94: f004 fb10 bl 80054b8 uart_idx = 0; 8000e98: 4b10 ldr r3, [pc, #64] @ (8000edc ) 8000e9a: 2200 movs r2, #0 8000e9c: 701a strb r2, [r3, #0] new_message = 1; 8000e9e: 4b12 ldr r3, [pc, #72] @ (8000ee8 ) 8000ea0: 2201 movs r2, #1 8000ea2: 701a strb r2, [r3, #0] if (uart_idx > 0) { 8000ea4: e00d b.n 8000ec2 } } else if (uart_idx < UART_BUF - 1) { 8000ea6: 4b0d ldr r3, [pc, #52] @ (8000edc ) 8000ea8: 781b ldrb r3, [r3, #0] 8000eaa: 2b7e cmp r3, #126 @ 0x7e 8000eac: d809 bhi.n 8000ec2 uart_buf[uart_idx++] = b; 8000eae: 4b0b ldr r3, [pc, #44] @ (8000edc ) 8000eb0: 781b ldrb r3, [r3, #0] 8000eb2: 1c5a adds r2, r3, #1 8000eb4: b2d1 uxtb r1, r2 8000eb6: 4a09 ldr r2, [pc, #36] @ (8000edc ) 8000eb8: 7011 strb r1, [r2, #0] 8000eba: 4619 mov r1, r3 8000ebc: 4a08 ldr r2, [pc, #32] @ (8000ee0 ) 8000ebe: 7bfb ldrb r3, [r7, #15] 8000ec0: 5453 strb r3, [r2, r1] } /* Re-arm for next byte */ HAL_UART_Receive_IT(&huart2, &uart_rx_byte, 1); 8000ec2: 2201 movs r2, #1 8000ec4: 4904 ldr r1, [pc, #16] @ (8000ed8 ) 8000ec6: 4809 ldr r0, [pc, #36] @ (8000eec ) 8000ec8: f002 fa92 bl 80033f0 } } 8000ecc: bf00 nop 8000ece: 3710 adds r7, #16 8000ed0: 46bd mov sp, r7 8000ed2: bd80 pop {r7, pc} 8000ed4: 40004400 .word 0x40004400 8000ed8: 20000f7c .word 0x20000f7c 8000edc: 20001000 .word 0x20001000 8000ee0: 20000f80 .word 0x20000f80 8000ee4: 20001004 .word 0x20001004 8000ee8: 20001001 .word 0x20001001 8000eec: 2000008c .word 0x2000008c 08000ef0
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000ef0: b580 push {r7, lr} 8000ef2: b082 sub sp, #8 8000ef4: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ HAL_Init(); 8000ef6: f000 faea bl 80014ce /* USER CODE BEGIN Init */ /* USER CODE END Init */ SystemClock_Config(); 8000efa: f000 f86b bl 8000fd4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ MX_GPIO_Init(); 8000efe: f000 f93f bl 8001180 MX_SPI1_Init(); 8000f02: f000 f8b3 bl 800106c MX_USART2_UART_Init(); 8000f06: f000 f8ef bl 80010e8 /* USER CODE BEGIN 2 */ /* Enable DWT cycle counter for microsecond delays */ CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; 8000f0a: 4b29 ldr r3, [pc, #164] @ (8000fb0 ) 8000f0c: 68db ldr r3, [r3, #12] 8000f0e: 4a28 ldr r2, [pc, #160] @ (8000fb0 ) 8000f10: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8000f14: 60d3 str r3, [r2, #12] DWT->CYCCNT = 0; 8000f16: 4b27 ldr r3, [pc, #156] @ (8000fb4 ) 8000f18: 2200 movs r2, #0 8000f1a: 605a str r2, [r3, #4] DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; 8000f1c: 4b25 ldr r3, [pc, #148] @ (8000fb4 ) 8000f1e: 681b ldr r3, [r3, #0] 8000f20: 4a24 ldr r2, [pc, #144] @ (8000fb4 ) 8000f22: f043 0301 orr.w r3, r3, #1 8000f26: 6013 str r3, [r2, #0] /* All rows off, blank display */ all_rows_off(); 8000f28: f7ff fb32 bl 8000590 memset(fb, 0, sizeof(fb)); 8000f2c: 2254 movs r2, #84 @ 0x54 8000f2e: 2100 movs r1, #0 8000f30: 4821 ldr r0, [pc, #132] @ (8000fb8 ) 8000f32: f004 fa95 bl 8005460 /* Start UART receive interrupt */ HAL_UART_Receive_IT(&huart2, &uart_rx_byte, 1); 8000f36: 2201 movs r2, #1 8000f38: 4920 ldr r1, [pc, #128] @ (8000fbc ) 8000f3a: 4821 ldr r0, [pc, #132] @ (8000fc0 ) 8000f3c: f002 fa58 bl 80033f0 /* Render default message */ render_message(message); 8000f40: 4820 ldr r0, [pc, #128] @ (8000fc4 ) 8000f42: f7ff fb7d bl 8000640 update_fb_from_scroll(); 8000f46: f7ff fbf1 bl 800072c /* USER CODE END 2 */ /* USER CODE BEGIN WHILE */ /* Run boot animation */ arrive_animation(); 8000f4a: f7ff fe0b bl 8000b64 update_fb_from_scroll(); 8000f4e: f7ff fbed bl 800072c uint32_t last_scroll = HAL_GetTick(); 8000f52: f000 fb21 bl 8001598 8000f56: 6078 str r0, [r7, #4] const uint32_t scroll_ms = 40; 8000f58: 2328 movs r3, #40 @ 0x28 8000f5a: 603b str r3, [r7, #0] while (1) { if (new_message) { 8000f5c: 4b1a ldr r3, [pc, #104] @ (8000fc8 ) 8000f5e: 781b ldrb r3, [r3, #0] 8000f60: 2b00 cmp r3, #0 8000f62: d005 beq.n 8000f70 new_message = 0; 8000f64: 4b18 ldr r3, [pc, #96] @ (8000fc8 ) 8000f66: 2200 movs r2, #0 8000f68: 701a strb r2, [r3, #0] render_message(message); 8000f6a: 4816 ldr r0, [pc, #88] @ (8000fc4 ) 8000f6c: f7ff fb68 bl 8000640 } if ((HAL_GetTick() - last_scroll) >= scroll_ms) { 8000f70: f000 fb12 bl 8001598 8000f74: 4602 mov r2, r0 8000f76: 687b ldr r3, [r7, #4] 8000f78: 1ad3 subs r3, r2, r3 8000f7a: 683a ldr r2, [r7, #0] 8000f7c: 429a cmp r2, r3 8000f7e: d813 bhi.n 8000fa8 last_scroll = HAL_GetTick(); 8000f80: f000 fb0a bl 8001598 8000f84: 6078 str r0, [r7, #4] scroll_x++; 8000f86: 4b11 ldr r3, [pc, #68] @ (8000fcc ) 8000f88: 681b ldr r3, [r3, #0] 8000f8a: 3301 adds r3, #1 8000f8c: 4a0f ldr r2, [pc, #60] @ (8000fcc ) 8000f8e: 6013 str r3, [r2, #0] if (scroll_x >= wide_cols) { 8000f90: 4b0f ldr r3, [pc, #60] @ (8000fd0 ) 8000f92: 881b ldrh r3, [r3, #0] 8000f94: 461a mov r2, r3 8000f96: 4b0d ldr r3, [pc, #52] @ (8000fcc ) 8000f98: 681b ldr r3, [r3, #0] 8000f9a: 429a cmp r2, r3 8000f9c: dc02 bgt.n 8000fa4 /* End of message — switch to next */ scroll_x = 0; 8000f9e: 4b0b ldr r3, [pc, #44] @ (8000fcc ) 8000fa0: 2200 movs r2, #0 8000fa2: 601a str r2, [r3, #0] } update_fb_from_scroll(); 8000fa4: f7ff fbc2 bl 800072c } display_refresh(); 8000fa8: f7ff fb12 bl 80005d0 if (new_message) { 8000fac: e7d6 b.n 8000f5c 8000fae: bf00 nop 8000fb0: e000edf0 .word 0xe000edf0 8000fb4: e0001000 .word 0xe0001000 8000fb8: 20000120 .word 0x20000120 8000fbc: 20000f7c .word 0x20000f7c 8000fc0: 2000008c .word 0x2000008c 8000fc4: 20001004 .word 0x20001004 8000fc8: 20001001 .word 0x20001001 8000fcc: 20000f78 .word 0x20000f78 8000fd0: 20000f74 .word 0x20000f74 08000fd4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000fd4: b580 push {r7, lr} 8000fd6: b094 sub sp, #80 @ 0x50 8000fd8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000fda: f107 0318 add.w r3, r7, #24 8000fde: 2238 movs r2, #56 @ 0x38 8000fe0: 2100 movs r1, #0 8000fe2: 4618 mov r0, r3 8000fe4: f004 fa3c bl 8005460 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000fe8: 1d3b adds r3, r7, #4 8000fea: 2200 movs r2, #0 8000fec: 601a str r2, [r3, #0] 8000fee: 605a str r2, [r3, #4] 8000ff0: 609a str r2, [r3, #8] 8000ff2: 60da str r2, [r3, #12] 8000ff4: 611a str r2, [r3, #16] HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); 8000ff6: 2000 movs r0, #0 8000ff8: f000 fe52 bl 8001ca0 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8000ffc: 2302 movs r3, #2 8000ffe: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001000: f44f 7380 mov.w r3, #256 @ 0x100 8001004: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8001006: 2340 movs r3, #64 @ 0x40 8001008: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800100a: 2302 movs r3, #2 800100c: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 800100e: 2302 movs r3, #2 8001010: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; 8001012: 2304 movs r3, #4 8001014: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 85; 8001016: 2355 movs r3, #85 @ 0x55 8001018: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 800101a: 2302 movs r3, #2 800101c: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 800101e: 2302 movs r3, #2 8001020: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 8001022: 2302 movs r3, #2 8001024: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001026: f107 0318 add.w r3, r7, #24 800102a: 4618 mov r0, r3 800102c: f000 feec bl 8001e08 8001030: 4603 mov r3, r0 8001032: 2b00 cmp r3, #0 8001034: d001 beq.n 800103a { Error_Handler(); 8001036: f000 f909 bl 800124c } RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800103a: 230f movs r3, #15 800103c: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 800103e: 2303 movs r3, #3 8001040: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001042: 2300 movs r3, #0 8001044: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001046: 2300 movs r3, #0 8001048: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800104a: 2300 movs r3, #0 800104c: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 800104e: 1d3b adds r3, r7, #4 8001050: 2104 movs r1, #4 8001052: 4618 mov r0, r3 8001054: f001 f9ea bl 800242c 8001058: 4603 mov r3, r0 800105a: 2b00 cmp r3, #0 800105c: d001 beq.n 8001062 { Error_Handler(); 800105e: f000 f8f5 bl 800124c } } 8001062: bf00 nop 8001064: 3750 adds r7, #80 @ 0x50 8001066: 46bd mov sp, r7 8001068: bd80 pop {r7, pc} ... 0800106c : /** * @brief SPI1 Initialization Function */ static void MX_SPI1_Init(void) { 800106c: b580 push {r7, lr} 800106e: af00 add r7, sp, #0 /* USER CODE END SPI1_Init 0 */ /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ hspi1.Instance = SPI1; 8001070: 4b1b ldr r3, [pc, #108] @ (80010e0 ) 8001072: 4a1c ldr r2, [pc, #112] @ (80010e4 ) 8001074: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 8001076: 4b1a ldr r3, [pc, #104] @ (80010e0 ) 8001078: f44f 7282 mov.w r2, #260 @ 0x104 800107c: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 800107e: 4b18 ldr r3, [pc, #96] @ (80010e0 ) 8001080: 2200 movs r2, #0 8001082: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 8001084: 4b16 ldr r3, [pc, #88] @ (80010e0 ) 8001086: f44f 62e0 mov.w r2, #1792 @ 0x700 800108a: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 800108c: 4b14 ldr r3, [pc, #80] @ (80010e0 ) 800108e: 2200 movs r2, #0 8001090: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 8001092: 4b13 ldr r3, [pc, #76] @ (80010e0 ) 8001094: 2200 movs r2, #0 8001096: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; 8001098: 4b11 ldr r3, [pc, #68] @ (80010e0 ) 800109a: f44f 2280 mov.w r2, #262144 @ 0x40000 800109e: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; 80010a0: 4b0f ldr r3, [pc, #60] @ (80010e0 ) 80010a2: 2220 movs r2, #32 80010a4: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 80010a6: 4b0e ldr r3, [pc, #56] @ (80010e0 ) 80010a8: 2200 movs r2, #0 80010aa: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 80010ac: 4b0c ldr r3, [pc, #48] @ (80010e0 ) 80010ae: 2200 movs r2, #0 80010b0: 625a str r2, [r3, #36] @ 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 80010b2: 4b0b ldr r3, [pc, #44] @ (80010e0 ) 80010b4: 2200 movs r2, #0 80010b6: 629a str r2, [r3, #40] @ 0x28 hspi1.Init.CRCPolynomial = 7; 80010b8: 4b09 ldr r3, [pc, #36] @ (80010e0 ) 80010ba: 2207 movs r2, #7 80010bc: 62da str r2, [r3, #44] @ 0x2c hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 80010be: 4b08 ldr r3, [pc, #32] @ (80010e0 ) 80010c0: 2200 movs r2, #0 80010c2: 631a str r2, [r3, #48] @ 0x30 hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 80010c4: 4b06 ldr r3, [pc, #24] @ (80010e0 ) 80010c6: 2208 movs r2, #8 80010c8: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi1) != HAL_OK) 80010ca: 4805 ldr r0, [pc, #20] @ (80010e0 ) 80010cc: f001 fdba bl 8002c44 80010d0: 4603 mov r3, r0 80010d2: 2b00 cmp r3, #0 80010d4: d001 beq.n 80010da { Error_Handler(); 80010d6: f000 f8b9 bl 800124c } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 80010da: bf00 nop 80010dc: bd80 pop {r7, pc} 80010de: bf00 nop 80010e0: 20000028 .word 0x20000028 80010e4: 40013000 .word 0x40013000 080010e8 : /** * @brief USART2 Initialization Function */ static void MX_USART2_UART_Init(void) { 80010e8: b580 push {r7, lr} 80010ea: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 80010ec: 4b22 ldr r3, [pc, #136] @ (8001178 ) 80010ee: 4a23 ldr r2, [pc, #140] @ (800117c ) 80010f0: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 80010f2: 4b21 ldr r3, [pc, #132] @ (8001178 ) 80010f4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80010f8: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 80010fa: 4b1f ldr r3, [pc, #124] @ (8001178 ) 80010fc: 2200 movs r2, #0 80010fe: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8001100: 4b1d ldr r3, [pc, #116] @ (8001178 ) 8001102: 2200 movs r2, #0 8001104: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8001106: 4b1c ldr r3, [pc, #112] @ (8001178 ) 8001108: 2200 movs r2, #0 800110a: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 800110c: 4b1a ldr r3, [pc, #104] @ (8001178 ) 800110e: 220c movs r2, #12 8001110: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001112: 4b19 ldr r3, [pc, #100] @ (8001178 ) 8001114: 2200 movs r2, #0 8001116: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001118: 4b17 ldr r3, [pc, #92] @ (8001178 ) 800111a: 2200 movs r2, #0 800111c: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800111e: 4b16 ldr r3, [pc, #88] @ (8001178 ) 8001120: 2200 movs r2, #0 8001122: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001124: 4b14 ldr r3, [pc, #80] @ (8001178 ) 8001126: 2200 movs r2, #0 8001128: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 800112a: 4b13 ldr r3, [pc, #76] @ (8001178 ) 800112c: 2200 movs r2, #0 800112e: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8001130: 4811 ldr r0, [pc, #68] @ (8001178 ) 8001132: f002 f90d bl 8003350 8001136: 4603 mov r3, r0 8001138: 2b00 cmp r3, #0 800113a: d001 beq.n 8001140 { Error_Handler(); 800113c: f000 f886 bl 800124c } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001140: 2100 movs r1, #0 8001142: 480d ldr r0, [pc, #52] @ (8001178 ) 8001144: f004 f8c1 bl 80052ca 8001148: 4603 mov r3, r0 800114a: 2b00 cmp r3, #0 800114c: d001 beq.n 8001152 { Error_Handler(); 800114e: f000 f87d bl 800124c } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001152: 2100 movs r1, #0 8001154: 4808 ldr r0, [pc, #32] @ (8001178 ) 8001156: f004 f8f6 bl 8005346 800115a: 4603 mov r3, r0 800115c: 2b00 cmp r3, #0 800115e: d001 beq.n 8001164 { Error_Handler(); 8001160: f000 f874 bl 800124c } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 8001164: 4804 ldr r0, [pc, #16] @ (8001178 ) 8001166: f004 f877 bl 8005258 800116a: 4603 mov r3, r0 800116c: 2b00 cmp r3, #0 800116e: d001 beq.n 8001174 { Error_Handler(); 8001170: f000 f86c bl 800124c } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8001174: bf00 nop 8001176: bd80 pop {r7, pc} 8001178: 2000008c .word 0x2000008c 800117c: 40004400 .word 0x40004400 08001180 : /** * @brief GPIO Initialization Function */ static void MX_GPIO_Init(void) { 8001180: b580 push {r7, lr} 8001182: b088 sub sp, #32 8001184: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001186: f107 030c add.w r3, r7, #12 800118a: 2200 movs r2, #0 800118c: 601a str r2, [r3, #0] 800118e: 605a str r2, [r3, #4] 8001190: 609a str r2, [r3, #8] 8001192: 60da str r2, [r3, #12] 8001194: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001196: 4b2b ldr r3, [pc, #172] @ (8001244 ) 8001198: 6cdb ldr r3, [r3, #76] @ 0x4c 800119a: 4a2a ldr r2, [pc, #168] @ (8001244 ) 800119c: f043 0301 orr.w r3, r3, #1 80011a0: 64d3 str r3, [r2, #76] @ 0x4c 80011a2: 4b28 ldr r3, [pc, #160] @ (8001244 ) 80011a4: 6cdb ldr r3, [r3, #76] @ 0x4c 80011a6: f003 0301 and.w r3, r3, #1 80011aa: 60bb str r3, [r7, #8] 80011ac: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 80011ae: 4b25 ldr r3, [pc, #148] @ (8001244 ) 80011b0: 6cdb ldr r3, [r3, #76] @ 0x4c 80011b2: 4a24 ldr r2, [pc, #144] @ (8001244 ) 80011b4: f043 0302 orr.w r3, r3, #2 80011b8: 64d3 str r3, [r2, #76] @ 0x4c 80011ba: 4b22 ldr r3, [pc, #136] @ (8001244 ) 80011bc: 6cdb ldr r3, [r3, #76] @ 0x4c 80011be: f003 0302 and.w r3, r3, #2 80011c2: 607b str r3, [r7, #4] 80011c4: 687b ldr r3, [r7, #4] HAL_GPIO_WritePin(GPIOA, ROW_1_Pin|ROW_2_Pin|ROW_6_Pin|ROW_5_Pin, GPIO_PIN_SET); 80011c6: 2201 movs r2, #1 80011c8: f640 1103 movw r1, #2307 @ 0x903 80011cc: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80011d0: f000 fd4e bl 8001c70 HAL_GPIO_WritePin(GPIOB, ROW_0_Pin|ROW_3_Pin|ROW_4_Pin|LED_Pin, GPIO_PIN_SET); 80011d4: 2201 movs r2, #1 80011d6: f240 1131 movw r1, #305 @ 0x131 80011da: 481b ldr r0, [pc, #108] @ (8001248 ) 80011dc: f000 fd48 bl 8001c70 GPIO_InitStruct.Pin = ROW_1_Pin|ROW_2_Pin|ROW_6_Pin|ROW_5_Pin; 80011e0: f640 1303 movw r3, #2307 @ 0x903 80011e4: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80011e6: 2301 movs r3, #1 80011e8: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011ea: 2300 movs r3, #0 80011ec: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80011ee: 2302 movs r3, #2 80011f0: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80011f2: f107 030c add.w r3, r7, #12 80011f6: 4619 mov r1, r3 80011f8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80011fc: f000 fbac bl 8001958 GPIO_InitStruct.Pin = ROW_0_Pin|ROW_3_Pin|ROW_4_Pin; 8001200: 2331 movs r3, #49 @ 0x31 8001202: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001204: 2301 movs r3, #1 8001206: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001208: 2300 movs r3, #0 800120a: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 800120c: 2302 movs r3, #2 800120e: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001210: f107 030c add.w r3, r7, #12 8001214: 4619 mov r1, r3 8001216: 480c ldr r0, [pc, #48] @ (8001248 ) 8001218: f000 fb9e bl 8001958 GPIO_InitStruct.Pin = LED_Pin; 800121c: f44f 7380 mov.w r3, #256 @ 0x100 8001220: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001222: 2301 movs r3, #1 8001224: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001226: 2300 movs r3, #0 8001228: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800122a: 2300 movs r3, #0 800122c: 61bb str r3, [r7, #24] HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); 800122e: f107 030c add.w r3, r7, #12 8001232: 4619 mov r1, r3 8001234: 4804 ldr r0, [pc, #16] @ (8001248 ) 8001236: f000 fb8f bl 8001958 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 800123a: bf00 nop 800123c: 3720 adds r7, #32 800123e: 46bd mov sp, r7 8001240: bd80 pop {r7, pc} 8001242: bf00 nop 8001244: 40021000 .word 0x40021000 8001248: 48000400 .word 0x48000400 0800124c : /** * @brief This function is executed in case of error occurrence. */ void Error_Handler(void) { 800124c: b480 push {r7} 800124e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8001250: b672 cpsid i } 8001252: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ __disable_irq(); while (1) 8001254: bf00 nop 8001256: e7fd b.n 8001254 08001258 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001258: b580 push {r7, lr} 800125a: b082 sub sp, #8 800125c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800125e: 4b0f ldr r3, [pc, #60] @ (800129c ) 8001260: 6e1b ldr r3, [r3, #96] @ 0x60 8001262: 4a0e ldr r2, [pc, #56] @ (800129c ) 8001264: f043 0301 orr.w r3, r3, #1 8001268: 6613 str r3, [r2, #96] @ 0x60 800126a: 4b0c ldr r3, [pc, #48] @ (800129c ) 800126c: 6e1b ldr r3, [r3, #96] @ 0x60 800126e: f003 0301 and.w r3, r3, #1 8001272: 607b str r3, [r7, #4] 8001274: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8001276: 4b09 ldr r3, [pc, #36] @ (800129c ) 8001278: 6d9b ldr r3, [r3, #88] @ 0x58 800127a: 4a08 ldr r2, [pc, #32] @ (800129c ) 800127c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8001280: 6593 str r3, [r2, #88] @ 0x58 8001282: 4b06 ldr r3, [pc, #24] @ (800129c ) 8001284: 6d9b ldr r3, [r3, #88] @ 0x58 8001286: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800128a: 603b str r3, [r7, #0] 800128c: 683b ldr r3, [r7, #0] /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); 800128e: f000 fdab bl 8001de8 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001292: bf00 nop 8001294: 3708 adds r7, #8 8001296: 46bd mov sp, r7 8001298: bd80 pop {r7, pc} 800129a: bf00 nop 800129c: 40021000 .word 0x40021000 080012a0 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 80012a0: b580 push {r7, lr} 80012a2: b08a sub sp, #40 @ 0x28 80012a4: af00 add r7, sp, #0 80012a6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80012a8: f107 0314 add.w r3, r7, #20 80012ac: 2200 movs r2, #0 80012ae: 601a str r2, [r3, #0] 80012b0: 605a str r2, [r3, #4] 80012b2: 609a str r2, [r3, #8] 80012b4: 60da str r2, [r3, #12] 80012b6: 611a str r2, [r3, #16] if(hspi->Instance==SPI1) 80012b8: 687b ldr r3, [r7, #4] 80012ba: 681b ldr r3, [r3, #0] 80012bc: 4a17 ldr r2, [pc, #92] @ (800131c ) 80012be: 4293 cmp r3, r2 80012c0: d128 bne.n 8001314 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 80012c2: 4b17 ldr r3, [pc, #92] @ (8001320 ) 80012c4: 6e1b ldr r3, [r3, #96] @ 0x60 80012c6: 4a16 ldr r2, [pc, #88] @ (8001320 ) 80012c8: f443 5380 orr.w r3, r3, #4096 @ 0x1000 80012cc: 6613 str r3, [r2, #96] @ 0x60 80012ce: 4b14 ldr r3, [pc, #80] @ (8001320 ) 80012d0: 6e1b ldr r3, [r3, #96] @ 0x60 80012d2: f403 5380 and.w r3, r3, #4096 @ 0x1000 80012d6: 613b str r3, [r7, #16] 80012d8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80012da: 4b11 ldr r3, [pc, #68] @ (8001320 ) 80012dc: 6cdb ldr r3, [r3, #76] @ 0x4c 80012de: 4a10 ldr r2, [pc, #64] @ (8001320 ) 80012e0: f043 0301 orr.w r3, r3, #1 80012e4: 64d3 str r3, [r2, #76] @ 0x4c 80012e6: 4b0e ldr r3, [pc, #56] @ (8001320 ) 80012e8: 6cdb ldr r3, [r3, #76] @ 0x4c 80012ea: f003 0301 and.w r3, r3, #1 80012ee: 60fb str r3, [r7, #12] 80012f0: 68fb ldr r3, [r7, #12] /**SPI1 GPIO Configuration PA4 ------> SPI1_NSS PA5 ------> SPI1_SCK PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7; 80012f2: 23b0 movs r3, #176 @ 0xb0 80012f4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80012f6: 2302 movs r3, #2 80012f8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80012fa: 2300 movs r3, #0 80012fc: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80012fe: 2300 movs r3, #0 8001300: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; 8001302: 2305 movs r3, #5 8001304: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001306: f107 0314 add.w r3, r7, #20 800130a: 4619 mov r1, r3 800130c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001310: f000 fb22 bl 8001958 /* USER CODE END SPI1_MspInit 1 */ } } 8001314: bf00 nop 8001316: 3728 adds r7, #40 @ 0x28 8001318: 46bd mov sp, r7 800131a: bd80 pop {r7, pc} 800131c: 40013000 .word 0x40013000 8001320: 40021000 .word 0x40021000 08001324 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001324: b580 push {r7, lr} 8001326: b09a sub sp, #104 @ 0x68 8001328: af00 add r7, sp, #0 800132a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800132c: f107 0354 add.w r3, r7, #84 @ 0x54 8001330: 2200 movs r2, #0 8001332: 601a str r2, [r3, #0] 8001334: 605a str r2, [r3, #4] 8001336: 609a str r2, [r3, #8] 8001338: 60da str r2, [r3, #12] 800133a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 800133c: f107 0310 add.w r3, r7, #16 8001340: 2244 movs r2, #68 @ 0x44 8001342: 2100 movs r1, #0 8001344: 4618 mov r0, r3 8001346: f004 f88b bl 8005460 if(huart->Instance==USART2) 800134a: 687b ldr r3, [r7, #4] 800134c: 681b ldr r3, [r3, #0] 800134e: 4a23 ldr r2, [pc, #140] @ (80013dc ) 8001350: 4293 cmp r3, r2 8001352: d13e bne.n 80013d2 /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; 8001354: 2302 movs r3, #2 8001356: 613b str r3, [r7, #16] PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; 8001358: 2300 movs r3, #0 800135a: 61bb str r3, [r7, #24] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800135c: f107 0310 add.w r3, r7, #16 8001360: 4618 mov r0, r3 8001362: f001 fa7f bl 8002864 8001366: 4603 mov r3, r0 8001368: 2b00 cmp r3, #0 800136a: d001 beq.n 8001370 { Error_Handler(); 800136c: f7ff ff6e bl 800124c } /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8001370: 4b1b ldr r3, [pc, #108] @ (80013e0 ) 8001372: 6d9b ldr r3, [r3, #88] @ 0x58 8001374: 4a1a ldr r2, [pc, #104] @ (80013e0 ) 8001376: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800137a: 6593 str r3, [r2, #88] @ 0x58 800137c: 4b18 ldr r3, [pc, #96] @ (80013e0 ) 800137e: 6d9b ldr r3, [r3, #88] @ 0x58 8001380: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001384: 60fb str r3, [r7, #12] 8001386: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001388: 4b15 ldr r3, [pc, #84] @ (80013e0 ) 800138a: 6cdb ldr r3, [r3, #76] @ 0x4c 800138c: 4a14 ldr r2, [pc, #80] @ (80013e0 ) 800138e: f043 0301 orr.w r3, r3, #1 8001392: 64d3 str r3, [r2, #76] @ 0x4c 8001394: 4b12 ldr r3, [pc, #72] @ (80013e0 ) 8001396: 6cdb ldr r3, [r3, #76] @ 0x4c 8001398: f003 0301 and.w r3, r3, #1 800139c: 60bb str r3, [r7, #8] 800139e: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin; 80013a0: 230c movs r3, #12 80013a2: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80013a4: 2302 movs r3, #2 80013a6: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80013a8: 2300 movs r3, #0 80013aa: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80013ac: 2300 movs r3, #0 80013ae: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 80013b0: 2307 movs r3, #7 80013b2: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80013b4: f107 0354 add.w r3, r7, #84 @ 0x54 80013b8: 4619 mov r1, r3 80013ba: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 80013be: f000 facb bl 8001958 /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 80013c2: 2200 movs r2, #0 80013c4: 2100 movs r1, #0 80013c6: 2026 movs r0, #38 @ 0x26 80013c8: f000 f9cd bl 8001766 HAL_NVIC_EnableIRQ(USART2_IRQn); 80013cc: 2026 movs r0, #38 @ 0x26 80013ce: f000 f9e4 bl 800179a /* USER CODE END USART2_MspInit 1 */ } } 80013d2: bf00 nop 80013d4: 3768 adds r7, #104 @ 0x68 80013d6: 46bd mov sp, r7 80013d8: bd80 pop {r7, pc} 80013da: bf00 nop 80013dc: 40004400 .word 0x40004400 80013e0: 40021000 .word 0x40021000 080013e4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80013e4: b480 push {r7} 80013e6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80013e8: bf00 nop 80013ea: e7fd b.n 80013e8 080013ec : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80013ec: b480 push {r7} 80013ee: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80013f0: bf00 nop 80013f2: e7fd b.n 80013f0 080013f4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80013f4: b480 push {r7} 80013f6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 80013f8: bf00 nop 80013fa: e7fd b.n 80013f8 080013fc : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 80013fc: b480 push {r7} 80013fe: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001400: bf00 nop 8001402: e7fd b.n 8001400 08001404 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001404: b480 push {r7} 8001406: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001408: bf00 nop 800140a: e7fd b.n 8001408 0800140c : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 800140c: b480 push {r7} 800140e: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001410: bf00 nop 8001412: 46bd mov sp, r7 8001414: f85d 7b04 ldr.w r7, [sp], #4 8001418: 4770 bx lr 0800141a : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800141a: b480 push {r7} 800141c: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800141e: bf00 nop 8001420: 46bd mov sp, r7 8001422: f85d 7b04 ldr.w r7, [sp], #4 8001426: 4770 bx lr 08001428 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001428: b480 push {r7} 800142a: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 800142c: bf00 nop 800142e: 46bd mov sp, r7 8001430: f85d 7b04 ldr.w r7, [sp], #4 8001434: 4770 bx lr 08001436 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001436: b580 push {r7, lr} 8001438: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800143a: f000 f89b bl 8001574 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 800143e: bf00 nop 8001440: bd80 pop {r7, pc} ... 08001444 : /** * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26. */ void USART2_IRQHandler(void) { 8001444: b580 push {r7, lr} 8001446: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 8001448: 4802 ldr r0, [pc, #8] @ (8001454 ) 800144a: f002 f81d bl 8003488 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 800144e: bf00 nop 8001450: bd80 pop {r7, pc} 8001452: bf00 nop 8001454: 2000008c .word 0x2000008c 08001458 : * @param None * @retval None */ void SystemInit(void) { 8001458: b480 push {r7} 800145a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 800145c: 4b06 ldr r3, [pc, #24] @ (8001478 ) 800145e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8001462: 4a05 ldr r2, [pc, #20] @ (8001478 ) 8001464: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001468: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 800146c: bf00 nop 800146e: 46bd mov sp, r7 8001470: f85d 7b04 ldr.w r7, [sp], #4 8001474: 4770 bx lr 8001476: bf00 nop 8001478: e000ed00 .word 0xe000ed00 0800147c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 800147c: 480d ldr r0, [pc, #52] @ (80014b4 ) mov sp, r0 /* set stack pointer */ 800147e: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8001480: f7ff ffea bl 8001458 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001484: 480c ldr r0, [pc, #48] @ (80014b8 ) ldr r1, =_edata 8001486: 490d ldr r1, [pc, #52] @ (80014bc ) ldr r2, =_sidata 8001488: 4a0d ldr r2, [pc, #52] @ (80014c0 ) movs r3, #0 800148a: 2300 movs r3, #0 b LoopCopyDataInit 800148c: e002 b.n 8001494 0800148e : CopyDataInit: ldr r4, [r2, r3] 800148e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001490: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001492: 3304 adds r3, #4 08001494 : LoopCopyDataInit: adds r4, r0, r3 8001494: 18c4 adds r4, r0, r3 cmp r4, r1 8001496: 428c cmp r4, r1 bcc CopyDataInit 8001498: d3f9 bcc.n 800148e /* Zero fill the bss segment. */ ldr r2, =_sbss 800149a: 4a0a ldr r2, [pc, #40] @ (80014c4 ) ldr r4, =_ebss 800149c: 4c0a ldr r4, [pc, #40] @ (80014c8 ) movs r3, #0 800149e: 2300 movs r3, #0 b LoopFillZerobss 80014a0: e001 b.n 80014a6 080014a2 : FillZerobss: str r3, [r2] 80014a2: 6013 str r3, [r2, #0] adds r2, r2, #4 80014a4: 3204 adds r2, #4 080014a6 : LoopFillZerobss: cmp r2, r4 80014a6: 42a2 cmp r2, r4 bcc FillZerobss 80014a8: d3fb bcc.n 80014a2 /* Call static constructors */ bl __libc_init_array 80014aa: f003 ffe1 bl 8005470 <__libc_init_array> /* Call the application's entry point.*/ bl main 80014ae: f7ff fd1f bl 8000ef0
080014b2 : LoopForever: b LoopForever 80014b2: e7fe b.n 80014b2 ldr r0, =_estack 80014b4: 20008000 .word 0x20008000 ldr r0, =_sdata 80014b8: 20000000 .word 0x20000000 ldr r1, =_edata 80014bc: 2000000c .word 0x2000000c ldr r2, =_sidata 80014c0: 080057e8 .word 0x080057e8 ldr r2, =_sbss 80014c4: 2000000c .word 0x2000000c ldr r4, =_ebss 80014c8: 20001088 .word 0x20001088 080014cc : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80014cc: e7fe b.n 80014cc 080014ce : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80014ce: b580 push {r7, lr} 80014d0: b082 sub sp, #8 80014d2: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 80014d4: 2300 movs r3, #0 80014d6: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80014d8: 2003 movs r0, #3 80014da: f000 f939 bl 8001750 /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80014de: 2000 movs r0, #0 80014e0: f000 f80e bl 8001500 80014e4: 4603 mov r3, r0 80014e6: 2b00 cmp r3, #0 80014e8: d002 beq.n 80014f0 { status = HAL_ERROR; 80014ea: 2301 movs r3, #1 80014ec: 71fb strb r3, [r7, #7] 80014ee: e001 b.n 80014f4 } else { /* Init the low level hardware */ HAL_MspInit(); 80014f0: f7ff feb2 bl 8001258 } /* Return function status */ return status; 80014f4: 79fb ldrb r3, [r7, #7] } 80014f6: 4618 mov r0, r3 80014f8: 3708 adds r7, #8 80014fa: 46bd mov sp, r7 80014fc: bd80 pop {r7, pc} ... 08001500 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001500: b580 push {r7, lr} 8001502: b084 sub sp, #16 8001504: af00 add r7, sp, #0 8001506: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8001508: 2300 movs r3, #0 800150a: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) 800150c: 4b16 ldr r3, [pc, #88] @ (8001568 ) 800150e: 681b ldr r3, [r3, #0] 8001510: 2b00 cmp r3, #0 8001512: d022 beq.n 800155a { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 8001514: 4b15 ldr r3, [pc, #84] @ (800156c ) 8001516: 681a ldr r2, [r3, #0] 8001518: 4b13 ldr r3, [pc, #76] @ (8001568 ) 800151a: 681b ldr r3, [r3, #0] 800151c: f44f 717a mov.w r1, #1000 @ 0x3e8 8001520: fbb1 f3f3 udiv r3, r1, r3 8001524: fbb2 f3f3 udiv r3, r2, r3 8001528: 4618 mov r0, r3 800152a: f000 f944 bl 80017b6 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d10f bne.n 8001554 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001534: 687b ldr r3, [r7, #4] 8001536: 2b0f cmp r3, #15 8001538: d809 bhi.n 800154e { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800153a: 2200 movs r2, #0 800153c: 6879 ldr r1, [r7, #4] 800153e: f04f 30ff mov.w r0, #4294967295 8001542: f000 f910 bl 8001766 uwTickPrio = TickPriority; 8001546: 4a0a ldr r2, [pc, #40] @ (8001570 ) 8001548: 687b ldr r3, [r7, #4] 800154a: 6013 str r3, [r2, #0] 800154c: e007 b.n 800155e } else { status = HAL_ERROR; 800154e: 2301 movs r3, #1 8001550: 73fb strb r3, [r7, #15] 8001552: e004 b.n 800155e } } else { status = HAL_ERROR; 8001554: 2301 movs r3, #1 8001556: 73fb strb r3, [r7, #15] 8001558: e001 b.n 800155e } } else { status = HAL_ERROR; 800155a: 2301 movs r3, #1 800155c: 73fb strb r3, [r7, #15] } /* Return function status */ return status; 800155e: 7bfb ldrb r3, [r7, #15] } 8001560: 4618 mov r0, r3 8001562: 3710 adds r7, #16 8001564: 46bd mov sp, r7 8001566: bd80 pop {r7, pc} 8001568: 20000008 .word 0x20000008 800156c: 20000000 .word 0x20000000 8001570: 20000004 .word 0x20000004 08001574 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001574: b480 push {r7} 8001576: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001578: 4b05 ldr r3, [pc, #20] @ (8001590 ) 800157a: 681a ldr r2, [r3, #0] 800157c: 4b05 ldr r3, [pc, #20] @ (8001594 ) 800157e: 681b ldr r3, [r3, #0] 8001580: 4413 add r3, r2 8001582: 4a03 ldr r2, [pc, #12] @ (8001590 ) 8001584: 6013 str r3, [r2, #0] } 8001586: bf00 nop 8001588: 46bd mov sp, r7 800158a: f85d 7b04 ldr.w r7, [sp], #4 800158e: 4770 bx lr 8001590: 20001084 .word 0x20001084 8001594: 20000008 .word 0x20000008 08001598 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001598: b480 push {r7} 800159a: af00 add r7, sp, #0 return uwTick; 800159c: 4b03 ldr r3, [pc, #12] @ (80015ac ) 800159e: 681b ldr r3, [r3, #0] } 80015a0: 4618 mov r0, r3 80015a2: 46bd mov sp, r7 80015a4: f85d 7b04 ldr.w r7, [sp], #4 80015a8: 4770 bx lr 80015aa: bf00 nop 80015ac: 20001084 .word 0x20001084 080015b0 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80015b0: b480 push {r7} 80015b2: b085 sub sp, #20 80015b4: af00 add r7, sp, #0 80015b6: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80015b8: 687b ldr r3, [r7, #4] 80015ba: f003 0307 and.w r3, r3, #7 80015be: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80015c0: 4b0c ldr r3, [pc, #48] @ (80015f4 <__NVIC_SetPriorityGrouping+0x44>) 80015c2: 68db ldr r3, [r3, #12] 80015c4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80015c6: 68ba ldr r2, [r7, #8] 80015c8: f64f 03ff movw r3, #63743 @ 0xf8ff 80015cc: 4013 ands r3, r2 80015ce: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80015d0: 68fb ldr r3, [r7, #12] 80015d2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80015d4: 68bb ldr r3, [r7, #8] 80015d6: 4313 orrs r3, r2 reg_value = (reg_value | 80015d8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80015dc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80015e0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80015e2: 4a04 ldr r2, [pc, #16] @ (80015f4 <__NVIC_SetPriorityGrouping+0x44>) 80015e4: 68bb ldr r3, [r7, #8] 80015e6: 60d3 str r3, [r2, #12] } 80015e8: bf00 nop 80015ea: 3714 adds r7, #20 80015ec: 46bd mov sp, r7 80015ee: f85d 7b04 ldr.w r7, [sp], #4 80015f2: 4770 bx lr 80015f4: e000ed00 .word 0xe000ed00 080015f8 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 80015f8: b480 push {r7} 80015fa: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80015fc: 4b04 ldr r3, [pc, #16] @ (8001610 <__NVIC_GetPriorityGrouping+0x18>) 80015fe: 68db ldr r3, [r3, #12] 8001600: 0a1b lsrs r3, r3, #8 8001602: f003 0307 and.w r3, r3, #7 } 8001606: 4618 mov r0, r3 8001608: 46bd mov sp, r7 800160a: f85d 7b04 ldr.w r7, [sp], #4 800160e: 4770 bx lr 8001610: e000ed00 .word 0xe000ed00 08001614 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001614: b480 push {r7} 8001616: b083 sub sp, #12 8001618: af00 add r7, sp, #0 800161a: 4603 mov r3, r0 800161c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800161e: f997 3007 ldrsb.w r3, [r7, #7] 8001622: 2b00 cmp r3, #0 8001624: db0b blt.n 800163e <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001626: 79fb ldrb r3, [r7, #7] 8001628: f003 021f and.w r2, r3, #31 800162c: 4907 ldr r1, [pc, #28] @ (800164c <__NVIC_EnableIRQ+0x38>) 800162e: f997 3007 ldrsb.w r3, [r7, #7] 8001632: 095b lsrs r3, r3, #5 8001634: 2001 movs r0, #1 8001636: fa00 f202 lsl.w r2, r0, r2 800163a: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 800163e: bf00 nop 8001640: 370c adds r7, #12 8001642: 46bd mov sp, r7 8001644: f85d 7b04 ldr.w r7, [sp], #4 8001648: 4770 bx lr 800164a: bf00 nop 800164c: e000e100 .word 0xe000e100 08001650 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001650: b480 push {r7} 8001652: b083 sub sp, #12 8001654: af00 add r7, sp, #0 8001656: 4603 mov r3, r0 8001658: 6039 str r1, [r7, #0] 800165a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800165c: f997 3007 ldrsb.w r3, [r7, #7] 8001660: 2b00 cmp r3, #0 8001662: db0a blt.n 800167a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001664: 683b ldr r3, [r7, #0] 8001666: b2da uxtb r2, r3 8001668: 490c ldr r1, [pc, #48] @ (800169c <__NVIC_SetPriority+0x4c>) 800166a: f997 3007 ldrsb.w r3, [r7, #7] 800166e: 0112 lsls r2, r2, #4 8001670: b2d2 uxtb r2, r2 8001672: 440b add r3, r1 8001674: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001678: e00a b.n 8001690 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800167a: 683b ldr r3, [r7, #0] 800167c: b2da uxtb r2, r3 800167e: 4908 ldr r1, [pc, #32] @ (80016a0 <__NVIC_SetPriority+0x50>) 8001680: 79fb ldrb r3, [r7, #7] 8001682: f003 030f and.w r3, r3, #15 8001686: 3b04 subs r3, #4 8001688: 0112 lsls r2, r2, #4 800168a: b2d2 uxtb r2, r2 800168c: 440b add r3, r1 800168e: 761a strb r2, [r3, #24] } 8001690: bf00 nop 8001692: 370c adds r7, #12 8001694: 46bd mov sp, r7 8001696: f85d 7b04 ldr.w r7, [sp], #4 800169a: 4770 bx lr 800169c: e000e100 .word 0xe000e100 80016a0: e000ed00 .word 0xe000ed00 080016a4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80016a4: b480 push {r7} 80016a6: b089 sub sp, #36 @ 0x24 80016a8: af00 add r7, sp, #0 80016aa: 60f8 str r0, [r7, #12] 80016ac: 60b9 str r1, [r7, #8] 80016ae: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80016b0: 68fb ldr r3, [r7, #12] 80016b2: f003 0307 and.w r3, r3, #7 80016b6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80016b8: 69fb ldr r3, [r7, #28] 80016ba: f1c3 0307 rsb r3, r3, #7 80016be: 2b04 cmp r3, #4 80016c0: bf28 it cs 80016c2: 2304 movcs r3, #4 80016c4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80016c6: 69fb ldr r3, [r7, #28] 80016c8: 3304 adds r3, #4 80016ca: 2b06 cmp r3, #6 80016cc: d902 bls.n 80016d4 80016ce: 69fb ldr r3, [r7, #28] 80016d0: 3b03 subs r3, #3 80016d2: e000 b.n 80016d6 80016d4: 2300 movs r3, #0 80016d6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80016d8: f04f 32ff mov.w r2, #4294967295 80016dc: 69bb ldr r3, [r7, #24] 80016de: fa02 f303 lsl.w r3, r2, r3 80016e2: 43da mvns r2, r3 80016e4: 68bb ldr r3, [r7, #8] 80016e6: 401a ands r2, r3 80016e8: 697b ldr r3, [r7, #20] 80016ea: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80016ec: f04f 31ff mov.w r1, #4294967295 80016f0: 697b ldr r3, [r7, #20] 80016f2: fa01 f303 lsl.w r3, r1, r3 80016f6: 43d9 mvns r1, r3 80016f8: 687b ldr r3, [r7, #4] 80016fa: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80016fc: 4313 orrs r3, r2 ); } 80016fe: 4618 mov r0, r3 8001700: 3724 adds r7, #36 @ 0x24 8001702: 46bd mov sp, r7 8001704: f85d 7b04 ldr.w r7, [sp], #4 8001708: 4770 bx lr ... 0800170c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800170c: b580 push {r7, lr} 800170e: b082 sub sp, #8 8001710: af00 add r7, sp, #0 8001712: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001714: 687b ldr r3, [r7, #4] 8001716: 3b01 subs r3, #1 8001718: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800171c: d301 bcc.n 8001722 { return (1UL); /* Reload value impossible */ 800171e: 2301 movs r3, #1 8001720: e00f b.n 8001742 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8001722: 4a0a ldr r2, [pc, #40] @ (800174c ) 8001724: 687b ldr r3, [r7, #4] 8001726: 3b01 subs r3, #1 8001728: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800172a: 210f movs r1, #15 800172c: f04f 30ff mov.w r0, #4294967295 8001730: f7ff ff8e bl 8001650 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001734: 4b05 ldr r3, [pc, #20] @ (800174c ) 8001736: 2200 movs r2, #0 8001738: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800173a: 4b04 ldr r3, [pc, #16] @ (800174c ) 800173c: 2207 movs r2, #7 800173e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001740: 2300 movs r3, #0 } 8001742: 4618 mov r0, r3 8001744: 3708 adds r7, #8 8001746: 46bd mov sp, r7 8001748: bd80 pop {r7, pc} 800174a: bf00 nop 800174c: e000e010 .word 0xe000e010 08001750 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001750: b580 push {r7, lr} 8001752: b082 sub sp, #8 8001754: af00 add r7, sp, #0 8001756: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8001758: 6878 ldr r0, [r7, #4] 800175a: f7ff ff29 bl 80015b0 <__NVIC_SetPriorityGrouping> } 800175e: bf00 nop 8001760: 3708 adds r7, #8 8001762: 46bd mov sp, r7 8001764: bd80 pop {r7, pc} 08001766 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001766: b580 push {r7, lr} 8001768: b086 sub sp, #24 800176a: af00 add r7, sp, #0 800176c: 4603 mov r3, r0 800176e: 60b9 str r1, [r7, #8] 8001770: 607a str r2, [r7, #4] 8001772: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8001774: f7ff ff40 bl 80015f8 <__NVIC_GetPriorityGrouping> 8001778: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800177a: 687a ldr r2, [r7, #4] 800177c: 68b9 ldr r1, [r7, #8] 800177e: 6978 ldr r0, [r7, #20] 8001780: f7ff ff90 bl 80016a4 8001784: 4602 mov r2, r0 8001786: f997 300f ldrsb.w r3, [r7, #15] 800178a: 4611 mov r1, r2 800178c: 4618 mov r0, r3 800178e: f7ff ff5f bl 8001650 <__NVIC_SetPriority> } 8001792: bf00 nop 8001794: 3718 adds r7, #24 8001796: 46bd mov sp, r7 8001798: bd80 pop {r7, pc} 0800179a : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800179a: b580 push {r7, lr} 800179c: b082 sub sp, #8 800179e: af00 add r7, sp, #0 80017a0: 4603 mov r3, r0 80017a2: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80017a4: f997 3007 ldrsb.w r3, [r7, #7] 80017a8: 4618 mov r0, r3 80017aa: f7ff ff33 bl 8001614 <__NVIC_EnableIRQ> } 80017ae: bf00 nop 80017b0: 3708 adds r7, #8 80017b2: 46bd mov sp, r7 80017b4: bd80 pop {r7, pc} 080017b6 : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80017b6: b580 push {r7, lr} 80017b8: b082 sub sp, #8 80017ba: af00 add r7, sp, #0 80017bc: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80017be: 6878 ldr r0, [r7, #4] 80017c0: f7ff ffa4 bl 800170c 80017c4: 4603 mov r3, r0 } 80017c6: 4618 mov r0, r3 80017c8: 3708 adds r7, #8 80017ca: 46bd mov sp, r7 80017cc: bd80 pop {r7, pc} 080017ce : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80017ce: b480 push {r7} 80017d0: b085 sub sp, #20 80017d2: af00 add r7, sp, #0 80017d4: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80017d6: 2300 movs r3, #0 80017d8: 73fb strb r3, [r7, #15] /* Check the DMA peripheral handle parameter */ if (hdma == NULL) 80017da: 687b ldr r3, [r7, #4] 80017dc: 2b00 cmp r3, #0 80017de: d101 bne.n 80017e4 { return HAL_ERROR; 80017e0: 2301 movs r3, #1 80017e2: e04c b.n 800187e } if (hdma->State != HAL_DMA_STATE_BUSY) 80017e4: 687b ldr r3, [r7, #4] 80017e6: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 80017ea: b2db uxtb r3, r3 80017ec: 2b02 cmp r3, #2 80017ee: d005 beq.n 80017fc { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80017f0: 687b ldr r3, [r7, #4] 80017f2: 2204 movs r2, #4 80017f4: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 80017f6: 2301 movs r3, #1 80017f8: 73fb strb r3, [r7, #15] 80017fa: e037 b.n 800186c } else { /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80017fc: 687b ldr r3, [r7, #4] 80017fe: 681b ldr r3, [r3, #0] 8001800: 681a ldr r2, [r3, #0] 8001802: 687b ldr r3, [r7, #4] 8001804: 681b ldr r3, [r3, #0] 8001806: f022 0201 bic.w r2, r2, #1 800180a: 601a str r2, [r3, #0] /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800180c: 687b ldr r3, [r7, #4] 800180e: 681b ldr r3, [r3, #0] 8001810: 681a ldr r2, [r3, #0] 8001812: 687b ldr r3, [r7, #4] 8001814: 681b ldr r3, [r3, #0] 8001816: f022 020e bic.w r2, r2, #14 800181a: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800181c: 687b ldr r3, [r7, #4] 800181e: 6c9b ldr r3, [r3, #72] @ 0x48 8001820: 681a ldr r2, [r3, #0] 8001822: 687b ldr r3, [r7, #4] 8001824: 6c9b ldr r3, [r3, #72] @ 0x48 8001826: f422 7280 bic.w r2, r2, #256 @ 0x100 800182a: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 800182c: 687b ldr r3, [r7, #4] 800182e: 6c5b ldr r3, [r3, #68] @ 0x44 8001830: f003 021f and.w r2, r3, #31 8001834: 687b ldr r3, [r7, #4] 8001836: 6c1b ldr r3, [r3, #64] @ 0x40 8001838: 2101 movs r1, #1 800183a: fa01 f202 lsl.w r2, r1, r2 800183e: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001840: 687b ldr r3, [r7, #4] 8001842: 6cdb ldr r3, [r3, #76] @ 0x4c 8001844: 687a ldr r2, [r7, #4] 8001846: 6d12 ldr r2, [r2, #80] @ 0x50 8001848: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 800184a: 687b ldr r3, [r7, #4] 800184c: 6d5b ldr r3, [r3, #84] @ 0x54 800184e: 2b00 cmp r3, #0 8001850: d00c beq.n 800186c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001852: 687b ldr r3, [r7, #4] 8001854: 6d5b ldr r3, [r3, #84] @ 0x54 8001856: 681a ldr r2, [r3, #0] 8001858: 687b ldr r3, [r7, #4] 800185a: 6d5b ldr r3, [r3, #84] @ 0x54 800185c: f422 7280 bic.w r2, r2, #256 @ 0x100 8001860: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001862: 687b ldr r3, [r7, #4] 8001864: 6d9b ldr r3, [r3, #88] @ 0x58 8001866: 687a ldr r2, [r7, #4] 8001868: 6dd2 ldr r2, [r2, #92] @ 0x5c 800186a: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800186c: 687b ldr r3, [r7, #4] 800186e: 2201 movs r2, #1 8001870: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001874: 687b ldr r3, [r7, #4] 8001876: 2200 movs r2, #0 8001878: f883 2024 strb.w r2, [r3, #36] @ 0x24 return status; 800187c: 7bfb ldrb r3, [r7, #15] } 800187e: 4618 mov r0, r3 8001880: 3714 adds r7, #20 8001882: 46bd mov sp, r7 8001884: f85d 7b04 ldr.w r7, [sp], #4 8001888: 4770 bx lr 0800188a : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800188a: b580 push {r7, lr} 800188c: b084 sub sp, #16 800188e: af00 add r7, sp, #0 8001890: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8001892: 2300 movs r3, #0 8001894: 73fb strb r3, [r7, #15] if (HAL_DMA_STATE_BUSY != hdma->State) 8001896: 687b ldr r3, [r7, #4] 8001898: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 800189c: b2db uxtb r3, r3 800189e: 2b02 cmp r3, #2 80018a0: d00d beq.n 80018be { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80018a2: 687b ldr r3, [r7, #4] 80018a4: 2204 movs r2, #4 80018a6: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80018a8: 687b ldr r3, [r7, #4] 80018aa: 2201 movs r2, #1 80018ac: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80018b0: 687b ldr r3, [r7, #4] 80018b2: 2200 movs r2, #0 80018b4: f883 2024 strb.w r2, [r3, #36] @ 0x24 status = HAL_ERROR; 80018b8: 2301 movs r3, #1 80018ba: 73fb strb r3, [r7, #15] 80018bc: e047 b.n 800194e } else { /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80018be: 687b ldr r3, [r7, #4] 80018c0: 681b ldr r3, [r3, #0] 80018c2: 681a ldr r2, [r3, #0] 80018c4: 687b ldr r3, [r7, #4] 80018c6: 681b ldr r3, [r3, #0] 80018c8: f022 0201 bic.w r2, r2, #1 80018cc: 601a str r2, [r3, #0] /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80018ce: 687b ldr r3, [r7, #4] 80018d0: 681b ldr r3, [r3, #0] 80018d2: 681a ldr r2, [r3, #0] 80018d4: 687b ldr r3, [r7, #4] 80018d6: 681b ldr r3, [r3, #0] 80018d8: f022 020e bic.w r2, r2, #14 80018dc: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80018de: 687b ldr r3, [r7, #4] 80018e0: 6c9b ldr r3, [r3, #72] @ 0x48 80018e2: 681a ldr r2, [r3, #0] 80018e4: 687b ldr r3, [r7, #4] 80018e6: 6c9b ldr r3, [r3, #72] @ 0x48 80018e8: f422 7280 bic.w r2, r2, #256 @ 0x100 80018ec: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 80018ee: 687b ldr r3, [r7, #4] 80018f0: 6c5b ldr r3, [r3, #68] @ 0x44 80018f2: f003 021f and.w r2, r3, #31 80018f6: 687b ldr r3, [r7, #4] 80018f8: 6c1b ldr r3, [r3, #64] @ 0x40 80018fa: 2101 movs r1, #1 80018fc: fa01 f202 lsl.w r2, r1, r2 8001900: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001902: 687b ldr r3, [r7, #4] 8001904: 6cdb ldr r3, [r3, #76] @ 0x4c 8001906: 687a ldr r2, [r7, #4] 8001908: 6d12 ldr r2, [r2, #80] @ 0x50 800190a: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 800190c: 687b ldr r3, [r7, #4] 800190e: 6d5b ldr r3, [r3, #84] @ 0x54 8001910: 2b00 cmp r3, #0 8001912: d00c beq.n 800192e { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001914: 687b ldr r3, [r7, #4] 8001916: 6d5b ldr r3, [r3, #84] @ 0x54 8001918: 681a ldr r2, [r3, #0] 800191a: 687b ldr r3, [r7, #4] 800191c: 6d5b ldr r3, [r3, #84] @ 0x54 800191e: f422 7280 bic.w r2, r2, #256 @ 0x100 8001922: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001924: 687b ldr r3, [r7, #4] 8001926: 6d9b ldr r3, [r3, #88] @ 0x58 8001928: 687a ldr r2, [r7, #4] 800192a: 6dd2 ldr r2, [r2, #92] @ 0x5c 800192c: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800192e: 687b ldr r3, [r7, #4] 8001930: 2201 movs r2, #1 8001932: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001936: 687b ldr r3, [r7, #4] 8001938: 2200 movs r2, #0 800193a: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 800193e: 687b ldr r3, [r7, #4] 8001940: 6b9b ldr r3, [r3, #56] @ 0x38 8001942: 2b00 cmp r3, #0 8001944: d003 beq.n 800194e { hdma->XferAbortCallback(hdma); 8001946: 687b ldr r3, [r7, #4] 8001948: 6b9b ldr r3, [r3, #56] @ 0x38 800194a: 6878 ldr r0, [r7, #4] 800194c: 4798 blx r3 } } return status; 800194e: 7bfb ldrb r3, [r7, #15] } 8001950: 4618 mov r0, r3 8001952: 3710 adds r7, #16 8001954: 46bd mov sp, r7 8001956: bd80 pop {r7, pc} 08001958 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef const *GPIO_Init) { 8001958: b480 push {r7} 800195a: b087 sub sp, #28 800195c: af00 add r7, sp, #0 800195e: 6078 str r0, [r7, #4] 8001960: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8001962: 2300 movs r3, #0 8001964: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) 8001966: e164 b.n 8001c32 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8001968: 683b ldr r3, [r7, #0] 800196a: 681a ldr r2, [r3, #0] 800196c: 2101 movs r1, #1 800196e: 697b ldr r3, [r7, #20] 8001970: fa01 f303 lsl.w r3, r1, r3 8001974: 4013 ands r3, r2 8001976: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8001978: 68fb ldr r3, [r7, #12] 800197a: 2b00 cmp r3, #0 800197c: f000 8156 beq.w 8001c2c { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001980: 683b ldr r3, [r7, #0] 8001982: 685b ldr r3, [r3, #4] 8001984: f003 0303 and.w r3, r3, #3 8001988: 2b01 cmp r3, #1 800198a: d005 beq.n 8001998 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800198c: 683b ldr r3, [r7, #0] 800198e: 685b ldr r3, [r3, #4] 8001990: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8001994: 2b02 cmp r3, #2 8001996: d130 bne.n 80019fa { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001998: 687b ldr r3, [r7, #4] 800199a: 689b ldr r3, [r3, #8] 800199c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800199e: 697b ldr r3, [r7, #20] 80019a0: 005b lsls r3, r3, #1 80019a2: 2203 movs r2, #3 80019a4: fa02 f303 lsl.w r3, r2, r3 80019a8: 43db mvns r3, r3 80019aa: 693a ldr r2, [r7, #16] 80019ac: 4013 ands r3, r2 80019ae: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2U)); 80019b0: 683b ldr r3, [r7, #0] 80019b2: 68da ldr r2, [r3, #12] 80019b4: 697b ldr r3, [r7, #20] 80019b6: 005b lsls r3, r3, #1 80019b8: fa02 f303 lsl.w r3, r2, r3 80019bc: 693a ldr r2, [r7, #16] 80019be: 4313 orrs r3, r2 80019c0: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80019c2: 687b ldr r3, [r7, #4] 80019c4: 693a ldr r2, [r7, #16] 80019c6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80019c8: 687b ldr r3, [r7, #4] 80019ca: 685b ldr r3, [r3, #4] 80019cc: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 80019ce: 2201 movs r2, #1 80019d0: 697b ldr r3, [r7, #20] 80019d2: fa02 f303 lsl.w r3, r2, r3 80019d6: 43db mvns r3, r3 80019d8: 693a ldr r2, [r7, #16] 80019da: 4013 ands r3, r2 80019dc: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80019de: 683b ldr r3, [r7, #0] 80019e0: 685b ldr r3, [r3, #4] 80019e2: 091b lsrs r3, r3, #4 80019e4: f003 0201 and.w r2, r3, #1 80019e8: 697b ldr r3, [r7, #20] 80019ea: fa02 f303 lsl.w r3, r2, r3 80019ee: 693a ldr r2, [r7, #16] 80019f0: 4313 orrs r3, r2 80019f2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 80019f4: 687b ldr r3, [r7, #4] 80019f6: 693a ldr r2, [r7, #16] 80019f8: 605a str r2, [r3, #4] } if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || 80019fa: 683b ldr r3, [r7, #0] 80019fc: 685b ldr r3, [r3, #4] 80019fe: f003 0303 and.w r3, r3, #3 8001a02: 2b03 cmp r3, #3 8001a04: d109 bne.n 8001a1a (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) 8001a06: 683b ldr r3, [r7, #0] 8001a08: 685b ldr r3, [r3, #4] 8001a0a: f003 0303 and.w r3, r3, #3 if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || 8001a0e: 2b03 cmp r3, #3 8001a10: d11b bne.n 8001a4a (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) 8001a12: 683b ldr r3, [r7, #0] 8001a14: 689b ldr r3, [r3, #8] 8001a16: 2b01 cmp r3, #1 8001a18: d017 beq.n 8001a4a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001a1a: 687b ldr r3, [r7, #4] 8001a1c: 68db ldr r3, [r3, #12] 8001a1e: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8001a20: 697b ldr r3, [r7, #20] 8001a22: 005b lsls r3, r3, #1 8001a24: 2203 movs r2, #3 8001a26: fa02 f303 lsl.w r3, r2, r3 8001a2a: 43db mvns r3, r3 8001a2c: 693a ldr r2, [r7, #16] 8001a2e: 4013 ands r3, r2 8001a30: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001a32: 683b ldr r3, [r7, #0] 8001a34: 689a ldr r2, [r3, #8] 8001a36: 697b ldr r3, [r7, #20] 8001a38: 005b lsls r3, r3, #1 8001a3a: fa02 f303 lsl.w r3, r2, r3 8001a3e: 693a ldr r2, [r7, #16] 8001a40: 4313 orrs r3, r2 8001a42: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001a44: 687b ldr r3, [r7, #4] 8001a46: 693a ldr r2, [r7, #16] 8001a48: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001a4a: 683b ldr r3, [r7, #0] 8001a4c: 685b ldr r3, [r3, #4] 8001a4e: f003 0303 and.w r3, r3, #3 8001a52: 2b02 cmp r3, #2 8001a54: d123 bne.n 8001a9e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001a56: 697b ldr r3, [r7, #20] 8001a58: 08da lsrs r2, r3, #3 8001a5a: 687b ldr r3, [r7, #4] 8001a5c: 3208 adds r2, #8 8001a5e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001a62: 613b str r3, [r7, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8001a64: 697b ldr r3, [r7, #20] 8001a66: f003 0307 and.w r3, r3, #7 8001a6a: 009b lsls r3, r3, #2 8001a6c: 220f movs r2, #15 8001a6e: fa02 f303 lsl.w r3, r2, r3 8001a72: 43db mvns r3, r3 8001a74: 693a ldr r2, [r7, #16] 8001a76: 4013 ands r3, r2 8001a78: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8001a7a: 683b ldr r3, [r7, #0] 8001a7c: 691a ldr r2, [r3, #16] 8001a7e: 697b ldr r3, [r7, #20] 8001a80: f003 0307 and.w r3, r3, #7 8001a84: 009b lsls r3, r3, #2 8001a86: fa02 f303 lsl.w r3, r2, r3 8001a8a: 693a ldr r2, [r7, #16] 8001a8c: 4313 orrs r3, r2 8001a8e: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3U] = temp; 8001a90: 697b ldr r3, [r7, #20] 8001a92: 08da lsrs r2, r3, #3 8001a94: 687b ldr r3, [r7, #4] 8001a96: 3208 adds r2, #8 8001a98: 6939 ldr r1, [r7, #16] 8001a9a: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001a9e: 687b ldr r3, [r7, #4] 8001aa0: 681b ldr r3, [r3, #0] 8001aa2: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8001aa4: 697b ldr r3, [r7, #20] 8001aa6: 005b lsls r3, r3, #1 8001aa8: 2203 movs r2, #3 8001aaa: fa02 f303 lsl.w r3, r2, r3 8001aae: 43db mvns r3, r3 8001ab0: 693a ldr r2, [r7, #16] 8001ab2: 4013 ands r3, r2 8001ab4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001ab6: 683b ldr r3, [r7, #0] 8001ab8: 685b ldr r3, [r3, #4] 8001aba: f003 0203 and.w r2, r3, #3 8001abe: 697b ldr r3, [r7, #20] 8001ac0: 005b lsls r3, r3, #1 8001ac2: fa02 f303 lsl.w r3, r2, r3 8001ac6: 693a ldr r2, [r7, #16] 8001ac8: 4313 orrs r3, r2 8001aca: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001acc: 687b ldr r3, [r7, #4] 8001ace: 693a ldr r2, [r7, #16] 8001ad0: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8001ad2: 683b ldr r3, [r7, #0] 8001ad4: 685b ldr r3, [r3, #4] 8001ad6: f403 3340 and.w r3, r3, #196608 @ 0x30000 8001ada: 2b00 cmp r3, #0 8001adc: f000 80a6 beq.w 8001c2c { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001ae0: 4b5b ldr r3, [pc, #364] @ (8001c50 ) 8001ae2: 6e1b ldr r3, [r3, #96] @ 0x60 8001ae4: 4a5a ldr r2, [pc, #360] @ (8001c50 ) 8001ae6: f043 0301 orr.w r3, r3, #1 8001aea: 6613 str r3, [r2, #96] @ 0x60 8001aec: 4b58 ldr r3, [pc, #352] @ (8001c50 ) 8001aee: 6e1b ldr r3, [r3, #96] @ 0x60 8001af0: f003 0301 and.w r3, r3, #1 8001af4: 60bb str r3, [r7, #8] 8001af6: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2U]; 8001af8: 4a56 ldr r2, [pc, #344] @ (8001c54 ) 8001afa: 697b ldr r3, [r7, #20] 8001afc: 089b lsrs r3, r3, #2 8001afe: 3302 adds r3, #2 8001b00: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001b04: 613b str r3, [r7, #16] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8001b06: 697b ldr r3, [r7, #20] 8001b08: f003 0303 and.w r3, r3, #3 8001b0c: 009b lsls r3, r3, #2 8001b0e: 220f movs r2, #15 8001b10: fa02 f303 lsl.w r3, r2, r3 8001b14: 43db mvns r3, r3 8001b16: 693a ldr r2, [r7, #16] 8001b18: 4013 ands r3, r2 8001b1a: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8001b1c: 687b ldr r3, [r7, #4] 8001b1e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8001b22: d01f beq.n 8001b64 8001b24: 687b ldr r3, [r7, #4] 8001b26: 4a4c ldr r2, [pc, #304] @ (8001c58 ) 8001b28: 4293 cmp r3, r2 8001b2a: d019 beq.n 8001b60 8001b2c: 687b ldr r3, [r7, #4] 8001b2e: 4a4b ldr r2, [pc, #300] @ (8001c5c ) 8001b30: 4293 cmp r3, r2 8001b32: d013 beq.n 8001b5c 8001b34: 687b ldr r3, [r7, #4] 8001b36: 4a4a ldr r2, [pc, #296] @ (8001c60 ) 8001b38: 4293 cmp r3, r2 8001b3a: d00d beq.n 8001b58 8001b3c: 687b ldr r3, [r7, #4] 8001b3e: 4a49 ldr r2, [pc, #292] @ (8001c64 ) 8001b40: 4293 cmp r3, r2 8001b42: d007 beq.n 8001b54 8001b44: 687b ldr r3, [r7, #4] 8001b46: 4a48 ldr r2, [pc, #288] @ (8001c68 ) 8001b48: 4293 cmp r3, r2 8001b4a: d101 bne.n 8001b50 8001b4c: 2305 movs r3, #5 8001b4e: e00a b.n 8001b66 8001b50: 2306 movs r3, #6 8001b52: e008 b.n 8001b66 8001b54: 2304 movs r3, #4 8001b56: e006 b.n 8001b66 8001b58: 2303 movs r3, #3 8001b5a: e004 b.n 8001b66 8001b5c: 2302 movs r3, #2 8001b5e: e002 b.n 8001b66 8001b60: 2301 movs r3, #1 8001b62: e000 b.n 8001b66 8001b64: 2300 movs r3, #0 8001b66: 697a ldr r2, [r7, #20] 8001b68: f002 0203 and.w r2, r2, #3 8001b6c: 0092 lsls r2, r2, #2 8001b6e: 4093 lsls r3, r2 8001b70: 693a ldr r2, [r7, #16] 8001b72: 4313 orrs r3, r2 8001b74: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2U] = temp; 8001b76: 4937 ldr r1, [pc, #220] @ (8001c54 ) 8001b78: 697b ldr r3, [r7, #20] 8001b7a: 089b lsrs r3, r3, #2 8001b7c: 3302 adds r3, #2 8001b7e: 693a ldr r2, [r7, #16] 8001b80: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001b84: 4b39 ldr r3, [pc, #228] @ (8001c6c ) 8001b86: 689b ldr r3, [r3, #8] 8001b88: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001b8a: 68fb ldr r3, [r7, #12] 8001b8c: 43db mvns r3, r3 8001b8e: 693a ldr r2, [r7, #16] 8001b90: 4013 ands r3, r2 8001b92: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001b94: 683b ldr r3, [r7, #0] 8001b96: 685b ldr r3, [r3, #4] 8001b98: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001b9c: 2b00 cmp r3, #0 8001b9e: d003 beq.n 8001ba8 { temp |= iocurrent; 8001ba0: 693a ldr r2, [r7, #16] 8001ba2: 68fb ldr r3, [r7, #12] 8001ba4: 4313 orrs r3, r2 8001ba6: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8001ba8: 4a30 ldr r2, [pc, #192] @ (8001c6c ) 8001baa: 693b ldr r3, [r7, #16] 8001bac: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; 8001bae: 4b2f ldr r3, [pc, #188] @ (8001c6c ) 8001bb0: 68db ldr r3, [r3, #12] 8001bb2: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001bb4: 68fb ldr r3, [r7, #12] 8001bb6: 43db mvns r3, r3 8001bb8: 693a ldr r2, [r7, #16] 8001bba: 4013 ands r3, r2 8001bbc: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001bbe: 683b ldr r3, [r7, #0] 8001bc0: 685b ldr r3, [r3, #4] 8001bc2: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001bc6: 2b00 cmp r3, #0 8001bc8: d003 beq.n 8001bd2 { temp |= iocurrent; 8001bca: 693a ldr r2, [r7, #16] 8001bcc: 68fb ldr r3, [r7, #12] 8001bce: 4313 orrs r3, r2 8001bd0: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8001bd2: 4a26 ldr r2, [pc, #152] @ (8001c6c ) 8001bd4: 693b ldr r3, [r7, #16] 8001bd6: 60d3 str r3, [r2, #12] temp = EXTI->EMR1; 8001bd8: 4b24 ldr r3, [pc, #144] @ (8001c6c ) 8001bda: 685b ldr r3, [r3, #4] 8001bdc: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001bde: 68fb ldr r3, [r7, #12] 8001be0: 43db mvns r3, r3 8001be2: 693a ldr r2, [r7, #16] 8001be4: 4013 ands r3, r2 8001be6: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001be8: 683b ldr r3, [r7, #0] 8001bea: 685b ldr r3, [r3, #4] 8001bec: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001bf0: 2b00 cmp r3, #0 8001bf2: d003 beq.n 8001bfc { temp |= iocurrent; 8001bf4: 693a ldr r2, [r7, #16] 8001bf6: 68fb ldr r3, [r7, #12] 8001bf8: 4313 orrs r3, r2 8001bfa: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8001bfc: 4a1b ldr r2, [pc, #108] @ (8001c6c ) 8001bfe: 693b ldr r3, [r7, #16] 8001c00: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 8001c02: 4b1a ldr r3, [pc, #104] @ (8001c6c ) 8001c04: 681b ldr r3, [r3, #0] 8001c06: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001c08: 68fb ldr r3, [r7, #12] 8001c0a: 43db mvns r3, r3 8001c0c: 693a ldr r2, [r7, #16] 8001c0e: 4013 ands r3, r2 8001c10: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001c12: 683b ldr r3, [r7, #0] 8001c14: 685b ldr r3, [r3, #4] 8001c16: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001c1a: 2b00 cmp r3, #0 8001c1c: d003 beq.n 8001c26 { temp |= iocurrent; 8001c1e: 693a ldr r2, [r7, #16] 8001c20: 68fb ldr r3, [r7, #12] 8001c22: 4313 orrs r3, r2 8001c24: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8001c26: 4a11 ldr r2, [pc, #68] @ (8001c6c ) 8001c28: 693b ldr r3, [r7, #16] 8001c2a: 6013 str r3, [r2, #0] } } position++; 8001c2c: 697b ldr r3, [r7, #20] 8001c2e: 3301 adds r3, #1 8001c30: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0U) 8001c32: 683b ldr r3, [r7, #0] 8001c34: 681a ldr r2, [r3, #0] 8001c36: 697b ldr r3, [r7, #20] 8001c38: fa22 f303 lsr.w r3, r2, r3 8001c3c: 2b00 cmp r3, #0 8001c3e: f47f ae93 bne.w 8001968 } } 8001c42: bf00 nop 8001c44: bf00 nop 8001c46: 371c adds r7, #28 8001c48: 46bd mov sp, r7 8001c4a: f85d 7b04 ldr.w r7, [sp], #4 8001c4e: 4770 bx lr 8001c50: 40021000 .word 0x40021000 8001c54: 40010000 .word 0x40010000 8001c58: 48000400 .word 0x48000400 8001c5c: 48000800 .word 0x48000800 8001c60: 48000c00 .word 0x48000c00 8001c64: 48001000 .word 0x48001000 8001c68: 48001400 .word 0x48001400 8001c6c: 40010400 .word 0x40010400 08001c70 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001c70: b480 push {r7} 8001c72: b083 sub sp, #12 8001c74: af00 add r7, sp, #0 8001c76: 6078 str r0, [r7, #4] 8001c78: 460b mov r3, r1 8001c7a: 807b strh r3, [r7, #2] 8001c7c: 4613 mov r3, r2 8001c7e: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001c80: 787b ldrb r3, [r7, #1] 8001c82: 2b00 cmp r3, #0 8001c84: d003 beq.n 8001c8e { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001c86: 887a ldrh r2, [r7, #2] 8001c88: 687b ldr r3, [r7, #4] 8001c8a: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8001c8c: e002 b.n 8001c94 GPIOx->BRR = (uint32_t)GPIO_Pin; 8001c8e: 887a ldrh r2, [r7, #2] 8001c90: 687b ldr r3, [r7, #4] 8001c92: 629a str r2, [r3, #40] @ 0x28 } 8001c94: bf00 nop 8001c96: 370c adds r7, #12 8001c98: 46bd mov sp, r7 8001c9a: f85d 7b04 ldr.w r7, [sp], #4 8001c9e: 4770 bx lr 08001ca0 : * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 8001ca0: b480 push {r7} 8001ca2: b085 sub sp, #20 8001ca4: af00 add r7, sp, #0 8001ca6: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) 8001ca8: 687b ldr r3, [r7, #4] 8001caa: 2b00 cmp r3, #0 8001cac: d141 bne.n 8001d32 { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8001cae: 4b4b ldr r3, [pc, #300] @ (8001ddc ) 8001cb0: 681b ldr r3, [r3, #0] 8001cb2: f403 63c0 and.w r3, r3, #1536 @ 0x600 8001cb6: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8001cba: d131 bne.n 8001d20 { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8001cbc: 4b47 ldr r3, [pc, #284] @ (8001ddc ) 8001cbe: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8001cc2: 4a46 ldr r2, [pc, #280] @ (8001ddc ) 8001cc4: f423 7380 bic.w r3, r3, #256 @ 0x100 8001cc8: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8001ccc: 4b43 ldr r3, [pc, #268] @ (8001ddc ) 8001cce: 681b ldr r3, [r3, #0] 8001cd0: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8001cd4: 4a41 ldr r2, [pc, #260] @ (8001ddc ) 8001cd6: f443 7300 orr.w r3, r3, #512 @ 0x200 8001cda: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8001cdc: 4b40 ldr r3, [pc, #256] @ (8001de0 ) 8001cde: 681b ldr r3, [r3, #0] 8001ce0: 2232 movs r2, #50 @ 0x32 8001ce2: fb02 f303 mul.w r3, r2, r3 8001ce6: 4a3f ldr r2, [pc, #252] @ (8001de4 ) 8001ce8: fba2 2303 umull r2, r3, r2, r3 8001cec: 0c9b lsrs r3, r3, #18 8001cee: 3301 adds r3, #1 8001cf0: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8001cf2: e002 b.n 8001cfa { wait_loop_index--; 8001cf4: 68fb ldr r3, [r7, #12] 8001cf6: 3b01 subs r3, #1 8001cf8: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8001cfa: 4b38 ldr r3, [pc, #224] @ (8001ddc ) 8001cfc: 695b ldr r3, [r3, #20] 8001cfe: f403 6380 and.w r3, r3, #1024 @ 0x400 8001d02: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8001d06: d102 bne.n 8001d0e 8001d08: 68fb ldr r3, [r7, #12] 8001d0a: 2b00 cmp r3, #0 8001d0c: d1f2 bne.n 8001cf4 } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8001d0e: 4b33 ldr r3, [pc, #204] @ (8001ddc ) 8001d10: 695b ldr r3, [r3, #20] 8001d12: f403 6380 and.w r3, r3, #1024 @ 0x400 8001d16: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8001d1a: d158 bne.n 8001dce { return HAL_TIMEOUT; 8001d1c: 2303 movs r3, #3 8001d1e: e057 b.n 8001dd0 } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8001d20: 4b2e ldr r3, [pc, #184] @ (8001ddc ) 8001d22: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8001d26: 4a2d ldr r2, [pc, #180] @ (8001ddc ) 8001d28: f423 7380 bic.w r3, r3, #256 @ 0x100 8001d2c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 8001d30: e04d b.n 8001dce } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 8001d32: 687b ldr r3, [r7, #4] 8001d34: f5b3 7f00 cmp.w r3, #512 @ 0x200 8001d38: d141 bne.n 8001dbe { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 8001d3a: 4b28 ldr r3, [pc, #160] @ (8001ddc ) 8001d3c: 681b ldr r3, [r3, #0] 8001d3e: f403 63c0 and.w r3, r3, #1536 @ 0x600 8001d42: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8001d46: d131 bne.n 8001dac { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8001d48: 4b24 ldr r3, [pc, #144] @ (8001ddc ) 8001d4a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8001d4e: 4a23 ldr r2, [pc, #140] @ (8001ddc ) 8001d50: f443 7380 orr.w r3, r3, #256 @ 0x100 8001d54: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8001d58: 4b20 ldr r3, [pc, #128] @ (8001ddc ) 8001d5a: 681b ldr r3, [r3, #0] 8001d5c: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8001d60: 4a1e ldr r2, [pc, #120] @ (8001ddc ) 8001d62: f443 7300 orr.w r3, r3, #512 @ 0x200 8001d66: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8001d68: 4b1d ldr r3, [pc, #116] @ (8001de0 ) 8001d6a: 681b ldr r3, [r3, #0] 8001d6c: 2232 movs r2, #50 @ 0x32 8001d6e: fb02 f303 mul.w r3, r2, r3 8001d72: 4a1c ldr r2, [pc, #112] @ (8001de4 ) 8001d74: fba2 2303 umull r2, r3, r2, r3 8001d78: 0c9b lsrs r3, r3, #18 8001d7a: 3301 adds r3, #1 8001d7c: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8001d7e: e002 b.n 8001d86 { wait_loop_index--; 8001d80: 68fb ldr r3, [r7, #12] 8001d82: 3b01 subs r3, #1 8001d84: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8001d86: 4b15 ldr r3, [pc, #84] @ (8001ddc ) 8001d88: 695b ldr r3, [r3, #20] 8001d8a: f403 6380 and.w r3, r3, #1024 @ 0x400 8001d8e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8001d92: d102 bne.n 8001d9a 8001d94: 68fb ldr r3, [r7, #12] 8001d96: 2b00 cmp r3, #0 8001d98: d1f2 bne.n 8001d80 } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8001d9a: 4b10 ldr r3, [pc, #64] @ (8001ddc ) 8001d9c: 695b ldr r3, [r3, #20] 8001d9e: f403 6380 and.w r3, r3, #1024 @ 0x400 8001da2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8001da6: d112 bne.n 8001dce { return HAL_TIMEOUT; 8001da8: 2303 movs r3, #3 8001daa: e011 b.n 8001dd0 } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8001dac: 4b0b ldr r3, [pc, #44] @ (8001ddc ) 8001dae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8001db2: 4a0a ldr r2, [pc, #40] @ (8001ddc ) 8001db4: f443 7380 orr.w r3, r3, #256 @ 0x100 8001db8: f8c2 3080 str.w r3, [r2, #128] @ 0x80 8001dbc: e007 b.n 8001dce } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 8001dbe: 4b07 ldr r3, [pc, #28] @ (8001ddc ) 8001dc0: 681b ldr r3, [r3, #0] 8001dc2: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8001dc6: 4a05 ldr r2, [pc, #20] @ (8001ddc ) 8001dc8: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001dcc: 6013 str r3, [r2, #0] /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; 8001dce: 2300 movs r3, #0 } 8001dd0: 4618 mov r0, r3 8001dd2: 3714 adds r7, #20 8001dd4: 46bd mov sp, r7 8001dd6: f85d 7b04 ldr.w r7, [sp], #4 8001dda: 4770 bx lr 8001ddc: 40007000 .word 0x40007000 8001de0: 20000000 .word 0x20000000 8001de4: 431bde83 .word 0x431bde83 08001de8 : * or to hand over control to the UCPD (which should therefore be * initialized before doing the disable). * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { 8001de8: b480 push {r7} 8001dea: af00 add r7, sp, #0 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); 8001dec: 4b05 ldr r3, [pc, #20] @ (8001e04 ) 8001dee: 689b ldr r3, [r3, #8] 8001df0: 4a04 ldr r2, [pc, #16] @ (8001e04 ) 8001df2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8001df6: 6093 str r3, [r2, #8] } 8001df8: bf00 nop 8001dfa: 46bd mov sp, r7 8001dfc: f85d 7b04 ldr.w r7, [sp], #4 8001e00: 4770 bx lr 8001e02: bf00 nop 8001e04: 40007000 .word 0x40007000 08001e08 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001e08: b580 push {r7, lr} 8001e0a: b088 sub sp, #32 8001e0c: af00 add r7, sp, #0 8001e0e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001e10: 687b ldr r3, [r7, #4] 8001e12: 2b00 cmp r3, #0 8001e14: d101 bne.n 8001e1a { return HAL_ERROR; 8001e16: 2301 movs r3, #1 8001e18: e2fe b.n 8002418 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8001e1a: 687b ldr r3, [r7, #4] 8001e1c: 681b ldr r3, [r3, #0] 8001e1e: f003 0301 and.w r3, r3, #1 8001e22: 2b00 cmp r3, #0 8001e24: d075 beq.n 8001f12 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8001e26: 4b97 ldr r3, [pc, #604] @ (8002084 ) 8001e28: 689b ldr r3, [r3, #8] 8001e2a: f003 030c and.w r3, r3, #12 8001e2e: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8001e30: 4b94 ldr r3, [pc, #592] @ (8002084 ) 8001e32: 68db ldr r3, [r3, #12] 8001e34: f003 0303 and.w r3, r3, #3 8001e38: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 8001e3a: 69bb ldr r3, [r7, #24] 8001e3c: 2b0c cmp r3, #12 8001e3e: d102 bne.n 8001e46 8001e40: 697b ldr r3, [r7, #20] 8001e42: 2b03 cmp r3, #3 8001e44: d002 beq.n 8001e4c 8001e46: 69bb ldr r3, [r7, #24] 8001e48: 2b08 cmp r3, #8 8001e4a: d10b bne.n 8001e64 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001e4c: 4b8d ldr r3, [pc, #564] @ (8002084 ) 8001e4e: 681b ldr r3, [r3, #0] 8001e50: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001e54: 2b00 cmp r3, #0 8001e56: d05b beq.n 8001f10 8001e58: 687b ldr r3, [r7, #4] 8001e5a: 685b ldr r3, [r3, #4] 8001e5c: 2b00 cmp r3, #0 8001e5e: d157 bne.n 8001f10 { return HAL_ERROR; 8001e60: 2301 movs r3, #1 8001e62: e2d9 b.n 8002418 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8001e64: 687b ldr r3, [r7, #4] 8001e66: 685b ldr r3, [r3, #4] 8001e68: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8001e6c: d106 bne.n 8001e7c 8001e6e: 4b85 ldr r3, [pc, #532] @ (8002084 ) 8001e70: 681b ldr r3, [r3, #0] 8001e72: 4a84 ldr r2, [pc, #528] @ (8002084 ) 8001e74: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8001e78: 6013 str r3, [r2, #0] 8001e7a: e01d b.n 8001eb8 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 685b ldr r3, [r3, #4] 8001e80: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8001e84: d10c bne.n 8001ea0 8001e86: 4b7f ldr r3, [pc, #508] @ (8002084 ) 8001e88: 681b ldr r3, [r3, #0] 8001e8a: 4a7e ldr r2, [pc, #504] @ (8002084 ) 8001e8c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8001e90: 6013 str r3, [r2, #0] 8001e92: 4b7c ldr r3, [pc, #496] @ (8002084 ) 8001e94: 681b ldr r3, [r3, #0] 8001e96: 4a7b ldr r2, [pc, #492] @ (8002084 ) 8001e98: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8001e9c: 6013 str r3, [r2, #0] 8001e9e: e00b b.n 8001eb8 8001ea0: 4b78 ldr r3, [pc, #480] @ (8002084 ) 8001ea2: 681b ldr r3, [r3, #0] 8001ea4: 4a77 ldr r2, [pc, #476] @ (8002084 ) 8001ea6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8001eaa: 6013 str r3, [r2, #0] 8001eac: 4b75 ldr r3, [pc, #468] @ (8002084 ) 8001eae: 681b ldr r3, [r3, #0] 8001eb0: 4a74 ldr r2, [pc, #464] @ (8002084 ) 8001eb2: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8001eb6: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 685b ldr r3, [r3, #4] 8001ebc: 2b00 cmp r3, #0 8001ebe: d013 beq.n 8001ee8 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001ec0: f7ff fb6a bl 8001598 8001ec4: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8001ec6: e008 b.n 8001eda { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001ec8: f7ff fb66 bl 8001598 8001ecc: 4602 mov r2, r0 8001ece: 693b ldr r3, [r7, #16] 8001ed0: 1ad3 subs r3, r2, r3 8001ed2: 2b64 cmp r3, #100 @ 0x64 8001ed4: d901 bls.n 8001eda { return HAL_TIMEOUT; 8001ed6: 2303 movs r3, #3 8001ed8: e29e b.n 8002418 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8001eda: 4b6a ldr r3, [pc, #424] @ (8002084 ) 8001edc: 681b ldr r3, [r3, #0] 8001ede: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001ee2: 2b00 cmp r3, #0 8001ee4: d0f0 beq.n 8001ec8 8001ee6: e014 b.n 8001f12 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001ee8: f7ff fb56 bl 8001598 8001eec: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8001eee: e008 b.n 8001f02 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001ef0: f7ff fb52 bl 8001598 8001ef4: 4602 mov r2, r0 8001ef6: 693b ldr r3, [r7, #16] 8001ef8: 1ad3 subs r3, r2, r3 8001efa: 2b64 cmp r3, #100 @ 0x64 8001efc: d901 bls.n 8001f02 { return HAL_TIMEOUT; 8001efe: 2303 movs r3, #3 8001f00: e28a b.n 8002418 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8001f02: 4b60 ldr r3, [pc, #384] @ (8002084 ) 8001f04: 681b ldr r3, [r3, #0] 8001f06: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001f0a: 2b00 cmp r3, #0 8001f0c: d1f0 bne.n 8001ef0 8001f0e: e000 b.n 8001f12 if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001f10: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8001f12: 687b ldr r3, [r7, #4] 8001f14: 681b ldr r3, [r3, #0] 8001f16: f003 0302 and.w r3, r3, #2 8001f1a: 2b00 cmp r3, #0 8001f1c: d075 beq.n 800200a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8001f1e: 4b59 ldr r3, [pc, #356] @ (8002084 ) 8001f20: 689b ldr r3, [r3, #8] 8001f22: f003 030c and.w r3, r3, #12 8001f26: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8001f28: 4b56 ldr r3, [pc, #344] @ (8002084 ) 8001f2a: 68db ldr r3, [r3, #12] 8001f2c: f003 0303 and.w r3, r3, #3 8001f30: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 8001f32: 69bb ldr r3, [r7, #24] 8001f34: 2b0c cmp r3, #12 8001f36: d102 bne.n 8001f3e 8001f38: 697b ldr r3, [r7, #20] 8001f3a: 2b02 cmp r3, #2 8001f3c: d002 beq.n 8001f44 8001f3e: 69bb ldr r3, [r7, #24] 8001f40: 2b04 cmp r3, #4 8001f42: d11f bne.n 8001f84 { /* When HSI is used as system clock it will not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8001f44: 4b4f ldr r3, [pc, #316] @ (8002084 ) 8001f46: 681b ldr r3, [r3, #0] 8001f48: f403 6380 and.w r3, r3, #1024 @ 0x400 8001f4c: 2b00 cmp r3, #0 8001f4e: d005 beq.n 8001f5c 8001f50: 687b ldr r3, [r7, #4] 8001f52: 68db ldr r3, [r3, #12] 8001f54: 2b00 cmp r3, #0 8001f56: d101 bne.n 8001f5c { return HAL_ERROR; 8001f58: 2301 movs r3, #1 8001f5a: e25d b.n 8002418 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001f5c: 4b49 ldr r3, [pc, #292] @ (8002084 ) 8001f5e: 685b ldr r3, [r3, #4] 8001f60: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8001f64: 687b ldr r3, [r7, #4] 8001f66: 691b ldr r3, [r3, #16] 8001f68: 061b lsls r3, r3, #24 8001f6a: 4946 ldr r1, [pc, #280] @ (8002084 ) 8001f6c: 4313 orrs r3, r2 8001f6e: 604b str r3, [r1, #4] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8001f70: 4b45 ldr r3, [pc, #276] @ (8002088 ) 8001f72: 681b ldr r3, [r3, #0] 8001f74: 4618 mov r0, r3 8001f76: f7ff fac3 bl 8001500 8001f7a: 4603 mov r3, r0 8001f7c: 2b00 cmp r3, #0 8001f7e: d043 beq.n 8002008 { return HAL_ERROR; 8001f80: 2301 movs r3, #1 8001f82: e249 b.n 8002418 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8001f84: 687b ldr r3, [r7, #4] 8001f86: 68db ldr r3, [r3, #12] 8001f88: 2b00 cmp r3, #0 8001f8a: d023 beq.n 8001fd4 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8001f8c: 4b3d ldr r3, [pc, #244] @ (8002084 ) 8001f8e: 681b ldr r3, [r3, #0] 8001f90: 4a3c ldr r2, [pc, #240] @ (8002084 ) 8001f92: f443 7380 orr.w r3, r3, #256 @ 0x100 8001f96: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001f98: f7ff fafe bl 8001598 8001f9c: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8001f9e: e008 b.n 8001fb2 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8001fa0: f7ff fafa bl 8001598 8001fa4: 4602 mov r2, r0 8001fa6: 693b ldr r3, [r7, #16] 8001fa8: 1ad3 subs r3, r2, r3 8001faa: 2b02 cmp r3, #2 8001fac: d901 bls.n 8001fb2 { return HAL_TIMEOUT; 8001fae: 2303 movs r3, #3 8001fb0: e232 b.n 8002418 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8001fb2: 4b34 ldr r3, [pc, #208] @ (8002084 ) 8001fb4: 681b ldr r3, [r3, #0] 8001fb6: f403 6380 and.w r3, r3, #1024 @ 0x400 8001fba: 2b00 cmp r3, #0 8001fbc: d0f0 beq.n 8001fa0 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001fbe: 4b31 ldr r3, [pc, #196] @ (8002084 ) 8001fc0: 685b ldr r3, [r3, #4] 8001fc2: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8001fc6: 687b ldr r3, [r7, #4] 8001fc8: 691b ldr r3, [r3, #16] 8001fca: 061b lsls r3, r3, #24 8001fcc: 492d ldr r1, [pc, #180] @ (8002084 ) 8001fce: 4313 orrs r3, r2 8001fd0: 604b str r3, [r1, #4] 8001fd2: e01a b.n 800200a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8001fd4: 4b2b ldr r3, [pc, #172] @ (8002084 ) 8001fd6: 681b ldr r3, [r3, #0] 8001fd8: 4a2a ldr r2, [pc, #168] @ (8002084 ) 8001fda: f423 7380 bic.w r3, r3, #256 @ 0x100 8001fde: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001fe0: f7ff fada bl 8001598 8001fe4: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8001fe6: e008 b.n 8001ffa { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8001fe8: f7ff fad6 bl 8001598 8001fec: 4602 mov r2, r0 8001fee: 693b ldr r3, [r7, #16] 8001ff0: 1ad3 subs r3, r2, r3 8001ff2: 2b02 cmp r3, #2 8001ff4: d901 bls.n 8001ffa { return HAL_TIMEOUT; 8001ff6: 2303 movs r3, #3 8001ff8: e20e b.n 8002418 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8001ffa: 4b22 ldr r3, [pc, #136] @ (8002084 ) 8001ffc: 681b ldr r3, [r3, #0] 8001ffe: f403 6380 and.w r3, r3, #1024 @ 0x400 8002002: 2b00 cmp r3, #0 8002004: d1f0 bne.n 8001fe8 8002006: e000 b.n 800200a if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8002008: bf00 nop } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800200a: 687b ldr r3, [r7, #4] 800200c: 681b ldr r3, [r3, #0] 800200e: f003 0308 and.w r3, r3, #8 8002012: 2b00 cmp r3, #0 8002014: d041 beq.n 800209a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8002016: 687b ldr r3, [r7, #4] 8002018: 695b ldr r3, [r3, #20] 800201a: 2b00 cmp r3, #0 800201c: d01c beq.n 8002058 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800201e: 4b19 ldr r3, [pc, #100] @ (8002084 ) 8002020: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002024: 4a17 ldr r2, [pc, #92] @ (8002084 ) 8002026: f043 0301 orr.w r3, r3, #1 800202a: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800202e: f7ff fab3 bl 8001598 8002032: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002034: e008 b.n 8002048 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002036: f7ff faaf bl 8001598 800203a: 4602 mov r2, r0 800203c: 693b ldr r3, [r7, #16] 800203e: 1ad3 subs r3, r2, r3 8002040: 2b02 cmp r3, #2 8002042: d901 bls.n 8002048 { return HAL_TIMEOUT; 8002044: 2303 movs r3, #3 8002046: e1e7 b.n 8002418 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002048: 4b0e ldr r3, [pc, #56] @ (8002084 ) 800204a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800204e: f003 0302 and.w r3, r3, #2 8002052: 2b00 cmp r3, #0 8002054: d0ef beq.n 8002036 8002056: e020 b.n 800209a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8002058: 4b0a ldr r3, [pc, #40] @ (8002084 ) 800205a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800205e: 4a09 ldr r2, [pc, #36] @ (8002084 ) 8002060: f023 0301 bic.w r3, r3, #1 8002064: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002068: f7ff fa96 bl 8001598 800206c: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 800206e: e00d b.n 800208c { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002070: f7ff fa92 bl 8001598 8002074: 4602 mov r2, r0 8002076: 693b ldr r3, [r7, #16] 8002078: 1ad3 subs r3, r2, r3 800207a: 2b02 cmp r3, #2 800207c: d906 bls.n 800208c { return HAL_TIMEOUT; 800207e: 2303 movs r3, #3 8002080: e1ca b.n 8002418 8002082: bf00 nop 8002084: 40021000 .word 0x40021000 8002088: 20000004 .word 0x20000004 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 800208c: 4b8c ldr r3, [pc, #560] @ (80022c0 ) 800208e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8002092: f003 0302 and.w r3, r3, #2 8002096: 2b00 cmp r3, #0 8002098: d1ea bne.n 8002070 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800209a: 687b ldr r3, [r7, #4] 800209c: 681b ldr r3, [r3, #0] 800209e: f003 0304 and.w r3, r3, #4 80020a2: 2b00 cmp r3, #0 80020a4: f000 80a6 beq.w 80021f4 { FlagStatus pwrclkchanged = RESET; 80020a8: 2300 movs r3, #0 80020aa: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 80020ac: 4b84 ldr r3, [pc, #528] @ (80022c0 ) 80020ae: 6d9b ldr r3, [r3, #88] @ 0x58 80020b0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80020b4: 2b00 cmp r3, #0 80020b6: d101 bne.n 80020bc 80020b8: 2301 movs r3, #1 80020ba: e000 b.n 80020be 80020bc: 2300 movs r3, #0 80020be: 2b00 cmp r3, #0 80020c0: d00d beq.n 80020de { __HAL_RCC_PWR_CLK_ENABLE(); 80020c2: 4b7f ldr r3, [pc, #508] @ (80022c0 ) 80020c4: 6d9b ldr r3, [r3, #88] @ 0x58 80020c6: 4a7e ldr r2, [pc, #504] @ (80022c0 ) 80020c8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80020cc: 6593 str r3, [r2, #88] @ 0x58 80020ce: 4b7c ldr r3, [pc, #496] @ (80022c0 ) 80020d0: 6d9b ldr r3, [r3, #88] @ 0x58 80020d2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80020d6: 60fb str r3, [r7, #12] 80020d8: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 80020da: 2301 movs r3, #1 80020dc: 77fb strb r3, [r7, #31] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80020de: 4b79 ldr r3, [pc, #484] @ (80022c4 ) 80020e0: 681b ldr r3, [r3, #0] 80020e2: f403 7380 and.w r3, r3, #256 @ 0x100 80020e6: 2b00 cmp r3, #0 80020e8: d118 bne.n 800211c { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 80020ea: 4b76 ldr r3, [pc, #472] @ (80022c4 ) 80020ec: 681b ldr r3, [r3, #0] 80020ee: 4a75 ldr r2, [pc, #468] @ (80022c4 ) 80020f0: f443 7380 orr.w r3, r3, #256 @ 0x100 80020f4: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80020f6: f7ff fa4f bl 8001598 80020fa: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80020fc: e008 b.n 8002110 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80020fe: f7ff fa4b bl 8001598 8002102: 4602 mov r2, r0 8002104: 693b ldr r3, [r7, #16] 8002106: 1ad3 subs r3, r2, r3 8002108: 2b02 cmp r3, #2 800210a: d901 bls.n 8002110 { return HAL_TIMEOUT; 800210c: 2303 movs r3, #3 800210e: e183 b.n 8002418 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8002110: 4b6c ldr r3, [pc, #432] @ (80022c4 ) 8002112: 681b ldr r3, [r3, #0] 8002114: f403 7380 and.w r3, r3, #256 @ 0x100 8002118: 2b00 cmp r3, #0 800211a: d0f0 beq.n 80020fe } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800211c: 687b ldr r3, [r7, #4] 800211e: 689b ldr r3, [r3, #8] 8002120: 2b01 cmp r3, #1 8002122: d108 bne.n 8002136 8002124: 4b66 ldr r3, [pc, #408] @ (80022c0 ) 8002126: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800212a: 4a65 ldr r2, [pc, #404] @ (80022c0 ) 800212c: f043 0301 orr.w r3, r3, #1 8002130: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8002134: e024 b.n 8002180 8002136: 687b ldr r3, [r7, #4] 8002138: 689b ldr r3, [r3, #8] 800213a: 2b05 cmp r3, #5 800213c: d110 bne.n 8002160 800213e: 4b60 ldr r3, [pc, #384] @ (80022c0 ) 8002140: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002144: 4a5e ldr r2, [pc, #376] @ (80022c0 ) 8002146: f043 0304 orr.w r3, r3, #4 800214a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 800214e: 4b5c ldr r3, [pc, #368] @ (80022c0 ) 8002150: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002154: 4a5a ldr r2, [pc, #360] @ (80022c0 ) 8002156: f043 0301 orr.w r3, r3, #1 800215a: f8c2 3090 str.w r3, [r2, #144] @ 0x90 800215e: e00f b.n 8002180 8002160: 4b57 ldr r3, [pc, #348] @ (80022c0 ) 8002162: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002166: 4a56 ldr r2, [pc, #344] @ (80022c0 ) 8002168: f023 0301 bic.w r3, r3, #1 800216c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 8002170: 4b53 ldr r3, [pc, #332] @ (80022c0 ) 8002172: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002176: 4a52 ldr r2, [pc, #328] @ (80022c0 ) 8002178: f023 0304 bic.w r3, r3, #4 800217c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8002180: 687b ldr r3, [r7, #4] 8002182: 689b ldr r3, [r3, #8] 8002184: 2b00 cmp r3, #0 8002186: d016 beq.n 80021b6 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002188: f7ff fa06 bl 8001598 800218c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800218e: e00a b.n 80021a6 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8002190: f7ff fa02 bl 8001598 8002194: 4602 mov r2, r0 8002196: 693b ldr r3, [r7, #16] 8002198: 1ad3 subs r3, r2, r3 800219a: f241 3288 movw r2, #5000 @ 0x1388 800219e: 4293 cmp r3, r2 80021a0: d901 bls.n 80021a6 { return HAL_TIMEOUT; 80021a2: 2303 movs r3, #3 80021a4: e138 b.n 8002418 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80021a6: 4b46 ldr r3, [pc, #280] @ (80022c0 ) 80021a8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80021ac: f003 0302 and.w r3, r3, #2 80021b0: 2b00 cmp r3, #0 80021b2: d0ed beq.n 8002190 80021b4: e015 b.n 80021e2 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80021b6: f7ff f9ef bl 8001598 80021ba: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 80021bc: e00a b.n 80021d4 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80021be: f7ff f9eb bl 8001598 80021c2: 4602 mov r2, r0 80021c4: 693b ldr r3, [r7, #16] 80021c6: 1ad3 subs r3, r2, r3 80021c8: f241 3288 movw r2, #5000 @ 0x1388 80021cc: 4293 cmp r3, r2 80021ce: d901 bls.n 80021d4 { return HAL_TIMEOUT; 80021d0: 2303 movs r3, #3 80021d2: e121 b.n 8002418 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 80021d4: 4b3a ldr r3, [pc, #232] @ (80022c0 ) 80021d6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80021da: f003 0302 and.w r3, r3, #2 80021de: 2b00 cmp r3, #0 80021e0: d1ed bne.n 80021be } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80021e2: 7ffb ldrb r3, [r7, #31] 80021e4: 2b01 cmp r3, #1 80021e6: d105 bne.n 80021f4 { __HAL_RCC_PWR_CLK_DISABLE(); 80021e8: 4b35 ldr r3, [pc, #212] @ (80022c0 ) 80021ea: 6d9b ldr r3, [r3, #88] @ 0x58 80021ec: 4a34 ldr r2, [pc, #208] @ (80022c0 ) 80021ee: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80021f2: 6593 str r3, [r2, #88] @ 0x58 } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80021f4: 687b ldr r3, [r7, #4] 80021f6: 681b ldr r3, [r3, #0] 80021f8: f003 0320 and.w r3, r3, #32 80021fc: 2b00 cmp r3, #0 80021fe: d03c beq.n 800227a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8002200: 687b ldr r3, [r7, #4] 8002202: 699b ldr r3, [r3, #24] 8002204: 2b00 cmp r3, #0 8002206: d01c beq.n 8002242 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8002208: 4b2d ldr r3, [pc, #180] @ (80022c0 ) 800220a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800220e: 4a2c ldr r2, [pc, #176] @ (80022c0 ) 8002210: f043 0301 orr.w r3, r3, #1 8002214: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002218: f7ff f9be bl 8001598 800221c: 6138 str r0, [r7, #16] /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 800221e: e008 b.n 8002232 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8002220: f7ff f9ba bl 8001598 8002224: 4602 mov r2, r0 8002226: 693b ldr r3, [r7, #16] 8002228: 1ad3 subs r3, r2, r3 800222a: 2b02 cmp r3, #2 800222c: d901 bls.n 8002232 { return HAL_TIMEOUT; 800222e: 2303 movs r3, #3 8002230: e0f2 b.n 8002418 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 8002232: 4b23 ldr r3, [pc, #140] @ (80022c0 ) 8002234: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8002238: f003 0302 and.w r3, r3, #2 800223c: 2b00 cmp r3, #0 800223e: d0ef beq.n 8002220 8002240: e01b b.n 800227a } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8002242: 4b1f ldr r3, [pc, #124] @ (80022c0 ) 8002244: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8002248: 4a1d ldr r2, [pc, #116] @ (80022c0 ) 800224a: f023 0301 bic.w r3, r3, #1 800224e: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002252: f7ff f9a1 bl 8001598 8002256: 6138 str r0, [r7, #16] /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8002258: e008 b.n 800226c { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800225a: f7ff f99d bl 8001598 800225e: 4602 mov r2, r0 8002260: 693b ldr r3, [r7, #16] 8002262: 1ad3 subs r3, r2, r3 8002264: 2b02 cmp r3, #2 8002266: d901 bls.n 800226c { return HAL_TIMEOUT; 8002268: 2303 movs r3, #3 800226a: e0d5 b.n 8002418 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 800226c: 4b14 ldr r3, [pc, #80] @ (80022c0 ) 800226e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8002272: f003 0302 and.w r3, r3, #2 8002276: 2b00 cmp r3, #0 8002278: d1ef bne.n 800225a /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 800227a: 687b ldr r3, [r7, #4] 800227c: 69db ldr r3, [r3, #28] 800227e: 2b00 cmp r3, #0 8002280: f000 80c9 beq.w 8002416 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8002284: 4b0e ldr r3, [pc, #56] @ (80022c0 ) 8002286: 689b ldr r3, [r3, #8] 8002288: f003 030c and.w r3, r3, #12 800228c: 2b0c cmp r3, #12 800228e: f000 8083 beq.w 8002398 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8002292: 687b ldr r3, [r7, #4] 8002294: 69db ldr r3, [r3, #28] 8002296: 2b02 cmp r3, #2 8002298: d15e bne.n 8002358 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800229a: 4b09 ldr r3, [pc, #36] @ (80022c0 ) 800229c: 681b ldr r3, [r3, #0] 800229e: 4a08 ldr r2, [pc, #32] @ (80022c0 ) 80022a0: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 80022a4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80022a6: f7ff f977 bl 8001598 80022aa: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80022ac: e00c b.n 80022c8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80022ae: f7ff f973 bl 8001598 80022b2: 4602 mov r2, r0 80022b4: 693b ldr r3, [r7, #16] 80022b6: 1ad3 subs r3, r2, r3 80022b8: 2b02 cmp r3, #2 80022ba: d905 bls.n 80022c8 { return HAL_TIMEOUT; 80022bc: 2303 movs r3, #3 80022be: e0ab b.n 8002418 80022c0: 40021000 .word 0x40021000 80022c4: 40007000 .word 0x40007000 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80022c8: 4b55 ldr r3, [pc, #340] @ (8002420 ) 80022ca: 681b ldr r3, [r3, #0] 80022cc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80022d0: 2b00 cmp r3, #0 80022d2: d1ec bne.n 80022ae } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80022d4: 4b52 ldr r3, [pc, #328] @ (8002420 ) 80022d6: 68da ldr r2, [r3, #12] 80022d8: 4b52 ldr r3, [pc, #328] @ (8002424 ) 80022da: 4013 ands r3, r2 80022dc: 687a ldr r2, [r7, #4] 80022de: 6a11 ldr r1, [r2, #32] 80022e0: 687a ldr r2, [r7, #4] 80022e2: 6a52 ldr r2, [r2, #36] @ 0x24 80022e4: 3a01 subs r2, #1 80022e6: 0112 lsls r2, r2, #4 80022e8: 4311 orrs r1, r2 80022ea: 687a ldr r2, [r7, #4] 80022ec: 6a92 ldr r2, [r2, #40] @ 0x28 80022ee: 0212 lsls r2, r2, #8 80022f0: 4311 orrs r1, r2 80022f2: 687a ldr r2, [r7, #4] 80022f4: 6b12 ldr r2, [r2, #48] @ 0x30 80022f6: 0852 lsrs r2, r2, #1 80022f8: 3a01 subs r2, #1 80022fa: 0552 lsls r2, r2, #21 80022fc: 4311 orrs r1, r2 80022fe: 687a ldr r2, [r7, #4] 8002300: 6b52 ldr r2, [r2, #52] @ 0x34 8002302: 0852 lsrs r2, r2, #1 8002304: 3a01 subs r2, #1 8002306: 0652 lsls r2, r2, #25 8002308: 4311 orrs r1, r2 800230a: 687a ldr r2, [r7, #4] 800230c: 6ad2 ldr r2, [r2, #44] @ 0x2c 800230e: 06d2 lsls r2, r2, #27 8002310: 430a orrs r2, r1 8002312: 4943 ldr r1, [pc, #268] @ (8002420 ) 8002314: 4313 orrs r3, r2 8002316: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8002318: 4b41 ldr r3, [pc, #260] @ (8002420 ) 800231a: 681b ldr r3, [r3, #0] 800231c: 4a40 ldr r2, [pc, #256] @ (8002420 ) 800231e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8002322: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 8002324: 4b3e ldr r3, [pc, #248] @ (8002420 ) 8002326: 68db ldr r3, [r3, #12] 8002328: 4a3d ldr r2, [pc, #244] @ (8002420 ) 800232a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800232e: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002330: f7ff f932 bl 8001598 8002334: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002336: e008 b.n 800234a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8002338: f7ff f92e bl 8001598 800233c: 4602 mov r2, r0 800233e: 693b ldr r3, [r7, #16] 8002340: 1ad3 subs r3, r2, r3 8002342: 2b02 cmp r3, #2 8002344: d901 bls.n 800234a { return HAL_TIMEOUT; 8002346: 2303 movs r3, #3 8002348: e066 b.n 8002418 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800234a: 4b35 ldr r3, [pc, #212] @ (8002420 ) 800234c: 681b ldr r3, [r3, #0] 800234e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002352: 2b00 cmp r3, #0 8002354: d0f0 beq.n 8002338 8002356: e05e b.n 8002416 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8002358: 4b31 ldr r3, [pc, #196] @ (8002420 ) 800235a: 681b ldr r3, [r3, #0] 800235c: 4a30 ldr r2, [pc, #192] @ (8002420 ) 800235e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8002362: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002364: f7ff f918 bl 8001598 8002368: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800236a: e008 b.n 800237e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800236c: f7ff f914 bl 8001598 8002370: 4602 mov r2, r0 8002372: 693b ldr r3, [r7, #16] 8002374: 1ad3 subs r3, r2, r3 8002376: 2b02 cmp r3, #2 8002378: d901 bls.n 800237e { return HAL_TIMEOUT; 800237a: 2303 movs r3, #3 800237c: e04c b.n 8002418 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800237e: 4b28 ldr r3, [pc, #160] @ (8002420 ) 8002380: 681b ldr r3, [r3, #0] 8002382: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002386: 2b00 cmp r3, #0 8002388: d1f0 bne.n 800236c } } /* Unselect PLL clock source and disable outputs to save power */ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); 800238a: 4b25 ldr r3, [pc, #148] @ (8002420 ) 800238c: 68da ldr r2, [r3, #12] 800238e: 4924 ldr r1, [pc, #144] @ (8002420 ) 8002390: 4b25 ldr r3, [pc, #148] @ (8002428 ) 8002392: 4013 ands r3, r2 8002394: 60cb str r3, [r1, #12] 8002396: e03e b.n 8002416 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8002398: 687b ldr r3, [r7, #4] 800239a: 69db ldr r3, [r3, #28] 800239c: 2b01 cmp r3, #1 800239e: d101 bne.n 80023a4 { return HAL_ERROR; 80023a0: 2301 movs r3, #1 80023a2: e039 b.n 8002418 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 80023a4: 4b1e ldr r3, [pc, #120] @ (8002420 ) 80023a6: 68db ldr r3, [r3, #12] 80023a8: 617b str r3, [r7, #20] if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80023aa: 697b ldr r3, [r7, #20] 80023ac: f003 0203 and.w r2, r3, #3 80023b0: 687b ldr r3, [r7, #4] 80023b2: 6a1b ldr r3, [r3, #32] 80023b4: 429a cmp r2, r3 80023b6: d12c bne.n 8002412 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 80023b8: 697b ldr r3, [r7, #20] 80023ba: f003 02f0 and.w r2, r3, #240 @ 0xf0 80023be: 687b ldr r3, [r7, #4] 80023c0: 6a5b ldr r3, [r3, #36] @ 0x24 80023c2: 3b01 subs r3, #1 80023c4: 011b lsls r3, r3, #4 if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80023c6: 429a cmp r2, r3 80023c8: d123 bne.n 8002412 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 80023ca: 697b ldr r3, [r7, #20] 80023cc: f403 42fe and.w r2, r3, #32512 @ 0x7f00 80023d0: 687b ldr r3, [r7, #4] 80023d2: 6a9b ldr r3, [r3, #40] @ 0x28 80023d4: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 80023d6: 429a cmp r2, r3 80023d8: d11b bne.n 8002412 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 80023da: 697b ldr r3, [r7, #20] 80023dc: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000 80023e0: 687b ldr r3, [r7, #4] 80023e2: 6adb ldr r3, [r3, #44] @ 0x2c 80023e4: 06db lsls r3, r3, #27 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 80023e6: 429a cmp r2, r3 80023e8: d113 bne.n 8002412 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 80023ea: 697b ldr r3, [r7, #20] 80023ec: f403 02c0 and.w r2, r3, #6291456 @ 0x600000 80023f0: 687b ldr r3, [r7, #4] 80023f2: 6b1b ldr r3, [r3, #48] @ 0x30 80023f4: 085b lsrs r3, r3, #1 80023f6: 3b01 subs r3, #1 80023f8: 055b lsls r3, r3, #21 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 80023fa: 429a cmp r2, r3 80023fc: d109 bne.n 8002412 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 80023fe: 697b ldr r3, [r7, #20] 8002400: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000 8002404: 687b ldr r3, [r7, #4] 8002406: 6b5b ldr r3, [r3, #52] @ 0x34 8002408: 085b lsrs r3, r3, #1 800240a: 3b01 subs r3, #1 800240c: 065b lsls r3, r3, #25 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 800240e: 429a cmp r2, r3 8002410: d001 beq.n 8002416 { return HAL_ERROR; 8002412: 2301 movs r3, #1 8002414: e000 b.n 8002418 } } } } return HAL_OK; 8002416: 2300 movs r3, #0 } 8002418: 4618 mov r0, r3 800241a: 3720 adds r7, #32 800241c: 46bd mov sp, r7 800241e: bd80 pop {r7, pc} 8002420: 40021000 .word 0x40021000 8002424: 019f800c .word 0x019f800c 8002428: feeefffc .word 0xfeeefffc 0800242c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800242c: b580 push {r7, lr} 800242e: b086 sub sp, #24 8002430: af00 add r7, sp, #0 8002432: 6078 str r0, [r7, #4] 8002434: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t pllfreq; uint32_t hpre = RCC_SYSCLK_DIV1; 8002436: 2300 movs r3, #0 8002438: 617b str r3, [r7, #20] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800243a: 687b ldr r3, [r7, #4] 800243c: 2b00 cmp r3, #0 800243e: d101 bne.n 8002444 { return HAL_ERROR; 8002440: 2301 movs r3, #1 8002442: e11e b.n 8002682 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8002444: 4b91 ldr r3, [pc, #580] @ (800268c ) 8002446: 681b ldr r3, [r3, #0] 8002448: f003 030f and.w r3, r3, #15 800244c: 683a ldr r2, [r7, #0] 800244e: 429a cmp r2, r3 8002450: d910 bls.n 8002474 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8002452: 4b8e ldr r3, [pc, #568] @ (800268c ) 8002454: 681b ldr r3, [r3, #0] 8002456: f023 020f bic.w r2, r3, #15 800245a: 498c ldr r1, [pc, #560] @ (800268c ) 800245c: 683b ldr r3, [r7, #0] 800245e: 4313 orrs r3, r2 8002460: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8002462: 4b8a ldr r3, [pc, #552] @ (800268c ) 8002464: 681b ldr r3, [r3, #0] 8002466: f003 030f and.w r3, r3, #15 800246a: 683a ldr r2, [r7, #0] 800246c: 429a cmp r2, r3 800246e: d001 beq.n 8002474 { return HAL_ERROR; 8002470: 2301 movs r3, #1 8002472: e106 b.n 8002682 } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8002474: 687b ldr r3, [r7, #4] 8002476: 681b ldr r3, [r3, #0] 8002478: f003 0301 and.w r3, r3, #1 800247c: 2b00 cmp r3, #0 800247e: d073 beq.n 8002568 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8002480: 687b ldr r3, [r7, #4] 8002482: 685b ldr r3, [r3, #4] 8002484: 2b03 cmp r3, #3 8002486: d129 bne.n 80024dc { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8002488: 4b81 ldr r3, [pc, #516] @ (8002690 ) 800248a: 681b ldr r3, [r3, #0] 800248c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8002490: 2b00 cmp r3, #0 8002492: d101 bne.n 8002498 { return HAL_ERROR; 8002494: 2301 movs r3, #1 8002496: e0f4 b.n 8002682 } /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); 8002498: f000 f99e bl 80027d8 800249c: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ if(pllfreq > 80000000U) 800249e: 693b ldr r3, [r7, #16] 80024a0: 4a7c ldr r2, [pc, #496] @ (8002694 ) 80024a2: 4293 cmp r3, r2 80024a4: d93f bls.n 8002526 { if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 80024a6: 4b7a ldr r3, [pc, #488] @ (8002690 ) 80024a8: 689b ldr r3, [r3, #8] 80024aa: f003 03f0 and.w r3, r3, #240 @ 0xf0 80024ae: 2b00 cmp r3, #0 80024b0: d009 beq.n 80024c6 (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 80024b2: 687b ldr r3, [r7, #4] 80024b4: 681b ldr r3, [r3, #0] 80024b6: f003 0302 and.w r3, r3, #2 if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 80024ba: 2b00 cmp r3, #0 80024bc: d033 beq.n 8002526 (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) 80024be: 687b ldr r3, [r7, #4] 80024c0: 689b ldr r3, [r3, #8] (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 80024c2: 2b00 cmp r3, #0 80024c4: d12f bne.n 8002526 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 80024c6: 4b72 ldr r3, [pc, #456] @ (8002690 ) 80024c8: 689b ldr r3, [r3, #8] 80024ca: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80024ce: 4a70 ldr r2, [pc, #448] @ (8002690 ) 80024d0: f043 0380 orr.w r3, r3, #128 @ 0x80 80024d4: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 80024d6: 2380 movs r3, #128 @ 0x80 80024d8: 617b str r3, [r7, #20] 80024da: e024 b.n 8002526 } } else { /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80024dc: 687b ldr r3, [r7, #4] 80024de: 685b ldr r3, [r3, #4] 80024e0: 2b02 cmp r3, #2 80024e2: d107 bne.n 80024f4 { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80024e4: 4b6a ldr r3, [pc, #424] @ (8002690 ) 80024e6: 681b ldr r3, [r3, #0] 80024e8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80024ec: 2b00 cmp r3, #0 80024ee: d109 bne.n 8002504 { return HAL_ERROR; 80024f0: 2301 movs r3, #1 80024f2: e0c6 b.n 8002682 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 80024f4: 4b66 ldr r3, [pc, #408] @ (8002690 ) 80024f6: 681b ldr r3, [r3, #0] 80024f8: f403 6380 and.w r3, r3, #1024 @ 0x400 80024fc: 2b00 cmp r3, #0 80024fe: d101 bne.n 8002504 { return HAL_ERROR; 8002500: 2301 movs r3, #1 8002502: e0be b.n 8002682 } } /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); 8002504: f000 f8ce bl 80026a4 8002508: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) 800250a: 693b ldr r3, [r7, #16] 800250c: 4a61 ldr r2, [pc, #388] @ (8002694 ) 800250e: 4293 cmp r3, r2 8002510: d909 bls.n 8002526 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 8002512: 4b5f ldr r3, [pc, #380] @ (8002690 ) 8002514: 689b ldr r3, [r3, #8] 8002516: f023 03f0 bic.w r3, r3, #240 @ 0xf0 800251a: 4a5d ldr r2, [pc, #372] @ (8002690 ) 800251c: f043 0380 orr.w r3, r3, #128 @ 0x80 8002520: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 8002522: 2380 movs r3, #128 @ 0x80 8002524: 617b str r3, [r7, #20] } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8002526: 4b5a ldr r3, [pc, #360] @ (8002690 ) 8002528: 689b ldr r3, [r3, #8] 800252a: f023 0203 bic.w r2, r3, #3 800252e: 687b ldr r3, [r7, #4] 8002530: 685b ldr r3, [r3, #4] 8002532: 4957 ldr r1, [pc, #348] @ (8002690 ) 8002534: 4313 orrs r3, r2 8002536: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002538: f7ff f82e bl 8001598 800253c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800253e: e00a b.n 8002556 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8002540: f7ff f82a bl 8001598 8002544: 4602 mov r2, r0 8002546: 68fb ldr r3, [r7, #12] 8002548: 1ad3 subs r3, r2, r3 800254a: f241 3288 movw r2, #5000 @ 0x1388 800254e: 4293 cmp r3, r2 8002550: d901 bls.n 8002556 { return HAL_TIMEOUT; 8002552: 2303 movs r3, #3 8002554: e095 b.n 8002682 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8002556: 4b4e ldr r3, [pc, #312] @ (8002690 ) 8002558: 689b ldr r3, [r3, #8] 800255a: f003 020c and.w r2, r3, #12 800255e: 687b ldr r3, [r7, #4] 8002560: 685b ldr r3, [r3, #4] 8002562: 009b lsls r3, r3, #2 8002564: 429a cmp r2, r3 8002566: d1eb bne.n 8002540 } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8002568: 687b ldr r3, [r7, #4] 800256a: 681b ldr r3, [r3, #0] 800256c: f003 0302 and.w r3, r3, #2 8002570: 2b00 cmp r3, #0 8002572: d023 beq.n 80025bc { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002574: 687b ldr r3, [r7, #4] 8002576: 681b ldr r3, [r3, #0] 8002578: f003 0304 and.w r3, r3, #4 800257c: 2b00 cmp r3, #0 800257e: d005 beq.n 800258c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8002580: 4b43 ldr r3, [pc, #268] @ (8002690 ) 8002582: 689b ldr r3, [r3, #8] 8002584: 4a42 ldr r2, [pc, #264] @ (8002690 ) 8002586: f443 63e0 orr.w r3, r3, #1792 @ 0x700 800258a: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800258c: 687b ldr r3, [r7, #4] 800258e: 681b ldr r3, [r3, #0] 8002590: f003 0308 and.w r3, r3, #8 8002594: 2b00 cmp r3, #0 8002596: d007 beq.n 80025a8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); 8002598: 4b3d ldr r3, [pc, #244] @ (8002690 ) 800259a: 689b ldr r3, [r3, #8] 800259c: f423 537c bic.w r3, r3, #16128 @ 0x3f00 80025a0: 4a3b ldr r2, [pc, #236] @ (8002690 ) 80025a2: f443 63e0 orr.w r3, r3, #1792 @ 0x700 80025a6: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80025a8: 4b39 ldr r3, [pc, #228] @ (8002690 ) 80025aa: 689b ldr r3, [r3, #8] 80025ac: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80025b0: 687b ldr r3, [r7, #4] 80025b2: 689b ldr r3, [r3, #8] 80025b4: 4936 ldr r1, [pc, #216] @ (8002690 ) 80025b6: 4313 orrs r3, r2 80025b8: 608b str r3, [r1, #8] 80025ba: e008 b.n 80025ce } else { /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ if(hpre == RCC_SYSCLK_DIV2) 80025bc: 697b ldr r3, [r7, #20] 80025be: 2b80 cmp r3, #128 @ 0x80 80025c0: d105 bne.n 80025ce { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); 80025c2: 4b33 ldr r3, [pc, #204] @ (8002690 ) 80025c4: 689b ldr r3, [r3, #8] 80025c6: 4a32 ldr r2, [pc, #200] @ (8002690 ) 80025c8: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80025cc: 6093 str r3, [r2, #8] } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80025ce: 4b2f ldr r3, [pc, #188] @ (800268c ) 80025d0: 681b ldr r3, [r3, #0] 80025d2: f003 030f and.w r3, r3, #15 80025d6: 683a ldr r2, [r7, #0] 80025d8: 429a cmp r2, r3 80025da: d21d bcs.n 8002618 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80025dc: 4b2b ldr r3, [pc, #172] @ (800268c ) 80025de: 681b ldr r3, [r3, #0] 80025e0: f023 020f bic.w r2, r3, #15 80025e4: 4929 ldr r1, [pc, #164] @ (800268c ) 80025e6: 683b ldr r3, [r7, #0] 80025e8: 4313 orrs r3, r2 80025ea: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 80025ec: f7fe ffd4 bl 8001598 80025f0: 60f8 str r0, [r7, #12] while (__HAL_FLASH_GET_LATENCY() != FLatency) 80025f2: e00a b.n 800260a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80025f4: f7fe ffd0 bl 8001598 80025f8: 4602 mov r2, r0 80025fa: 68fb ldr r3, [r7, #12] 80025fc: 1ad3 subs r3, r2, r3 80025fe: f241 3288 movw r2, #5000 @ 0x1388 8002602: 4293 cmp r3, r2 8002604: d901 bls.n 800260a { return HAL_TIMEOUT; 8002606: 2303 movs r3, #3 8002608: e03b b.n 8002682 while (__HAL_FLASH_GET_LATENCY() != FLatency) 800260a: 4b20 ldr r3, [pc, #128] @ (800268c ) 800260c: 681b ldr r3, [r3, #0] 800260e: f003 030f and.w r3, r3, #15 8002612: 683a ldr r2, [r7, #0] 8002614: 429a cmp r2, r3 8002616: d1ed bne.n 80025f4 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8002618: 687b ldr r3, [r7, #4] 800261a: 681b ldr r3, [r3, #0] 800261c: f003 0304 and.w r3, r3, #4 8002620: 2b00 cmp r3, #0 8002622: d008 beq.n 8002636 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8002624: 4b1a ldr r3, [pc, #104] @ (8002690 ) 8002626: 689b ldr r3, [r3, #8] 8002628: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800262c: 687b ldr r3, [r7, #4] 800262e: 68db ldr r3, [r3, #12] 8002630: 4917 ldr r1, [pc, #92] @ (8002690 ) 8002632: 4313 orrs r3, r2 8002634: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8002636: 687b ldr r3, [r7, #4] 8002638: 681b ldr r3, [r3, #0] 800263a: f003 0308 and.w r3, r3, #8 800263e: 2b00 cmp r3, #0 8002640: d009 beq.n 8002656 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8002642: 4b13 ldr r3, [pc, #76] @ (8002690 ) 8002644: 689b ldr r3, [r3, #8] 8002646: f423 5260 bic.w r2, r3, #14336 @ 0x3800 800264a: 687b ldr r3, [r7, #4] 800264c: 691b ldr r3, [r3, #16] 800264e: 00db lsls r3, r3, #3 8002650: 490f ldr r1, [pc, #60] @ (8002690 ) 8002652: 4313 orrs r3, r2 8002654: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8002656: f000 f825 bl 80026a4 800265a: 4602 mov r2, r0 800265c: 4b0c ldr r3, [pc, #48] @ (8002690 ) 800265e: 689b ldr r3, [r3, #8] 8002660: 091b lsrs r3, r3, #4 8002662: f003 030f and.w r3, r3, #15 8002666: 490c ldr r1, [pc, #48] @ (8002698 ) 8002668: 5ccb ldrb r3, [r1, r3] 800266a: f003 031f and.w r3, r3, #31 800266e: fa22 f303 lsr.w r3, r2, r3 8002672: 4a0a ldr r2, [pc, #40] @ (800269c ) 8002674: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8002676: 4b0a ldr r3, [pc, #40] @ (80026a0 ) 8002678: 681b ldr r3, [r3, #0] 800267a: 4618 mov r0, r3 800267c: f7fe ff40 bl 8001500 8002680: 4603 mov r3, r0 } 8002682: 4618 mov r0, r3 8002684: 3718 adds r7, #24 8002686: 46bd mov sp, r7 8002688: bd80 pop {r7, pc} 800268a: bf00 nop 800268c: 40022000 .word 0x40022000 8002690: 40021000 .word 0x40021000 8002694: 04c4b400 .word 0x04c4b400 8002698: 08005798 .word 0x08005798 800269c: 20000000 .word 0x20000000 80026a0: 20000004 .word 0x20000004 080026a4 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80026a4: b480 push {r7} 80026a6: b087 sub sp, #28 80026a8: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 80026aa: 4b2c ldr r3, [pc, #176] @ (800275c ) 80026ac: 689b ldr r3, [r3, #8] 80026ae: f003 030c and.w r3, r3, #12 80026b2: 2b04 cmp r3, #4 80026b4: d102 bne.n 80026bc { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 80026b6: 4b2a ldr r3, [pc, #168] @ (8002760 ) 80026b8: 613b str r3, [r7, #16] 80026ba: e047 b.n 800274c } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 80026bc: 4b27 ldr r3, [pc, #156] @ (800275c ) 80026be: 689b ldr r3, [r3, #8] 80026c0: f003 030c and.w r3, r3, #12 80026c4: 2b08 cmp r3, #8 80026c6: d102 bne.n 80026ce { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 80026c8: 4b26 ldr r3, [pc, #152] @ (8002764 ) 80026ca: 613b str r3, [r7, #16] 80026cc: e03e b.n 800274c } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) 80026ce: 4b23 ldr r3, [pc, #140] @ (800275c ) 80026d0: 689b ldr r3, [r3, #8] 80026d2: f003 030c and.w r3, r3, #12 80026d6: 2b0c cmp r3, #12 80026d8: d136 bne.n 8002748 /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 80026da: 4b20 ldr r3, [pc, #128] @ (800275c ) 80026dc: 68db ldr r3, [r3, #12] 80026de: f003 0303 and.w r3, r3, #3 80026e2: 60fb str r3, [r7, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80026e4: 4b1d ldr r3, [pc, #116] @ (800275c ) 80026e6: 68db ldr r3, [r3, #12] 80026e8: 091b lsrs r3, r3, #4 80026ea: f003 030f and.w r3, r3, #15 80026ee: 3301 adds r3, #1 80026f0: 60bb str r3, [r7, #8] switch (pllsource) 80026f2: 68fb ldr r3, [r7, #12] 80026f4: 2b03 cmp r3, #3 80026f6: d10c bne.n 8002712 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80026f8: 4a1a ldr r2, [pc, #104] @ (8002764 ) 80026fa: 68bb ldr r3, [r7, #8] 80026fc: fbb2 f3f3 udiv r3, r2, r3 8002700: 4a16 ldr r2, [pc, #88] @ (800275c ) 8002702: 68d2 ldr r2, [r2, #12] 8002704: 0a12 lsrs r2, r2, #8 8002706: f002 027f and.w r2, r2, #127 @ 0x7f 800270a: fb02 f303 mul.w r3, r2, r3 800270e: 617b str r3, [r7, #20] break; 8002710: e00c b.n 800272c case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002712: 4a13 ldr r2, [pc, #76] @ (8002760 ) 8002714: 68bb ldr r3, [r7, #8] 8002716: fbb2 f3f3 udiv r3, r2, r3 800271a: 4a10 ldr r2, [pc, #64] @ (800275c ) 800271c: 68d2 ldr r2, [r2, #12] 800271e: 0a12 lsrs r2, r2, #8 8002720: f002 027f and.w r2, r2, #127 @ 0x7f 8002724: fb02 f303 mul.w r3, r2, r3 8002728: 617b str r3, [r7, #20] break; 800272a: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 800272c: 4b0b ldr r3, [pc, #44] @ (800275c ) 800272e: 68db ldr r3, [r3, #12] 8002730: 0e5b lsrs r3, r3, #25 8002732: f003 0303 and.w r3, r3, #3 8002736: 3301 adds r3, #1 8002738: 005b lsls r3, r3, #1 800273a: 607b str r3, [r7, #4] sysclockfreq = pllvco/pllr; 800273c: 697a ldr r2, [r7, #20] 800273e: 687b ldr r3, [r7, #4] 8002740: fbb2 f3f3 udiv r3, r2, r3 8002744: 613b str r3, [r7, #16] 8002746: e001 b.n 800274c } else { sysclockfreq = 0U; 8002748: 2300 movs r3, #0 800274a: 613b str r3, [r7, #16] } return sysclockfreq; 800274c: 693b ldr r3, [r7, #16] } 800274e: 4618 mov r0, r3 8002750: 371c adds r7, #28 8002752: 46bd mov sp, r7 8002754: f85d 7b04 ldr.w r7, [sp], #4 8002758: 4770 bx lr 800275a: bf00 nop 800275c: 40021000 .word 0x40021000 8002760: 00f42400 .word 0x00f42400 8002764: 007a1200 .word 0x007a1200 08002768 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8002768: b480 push {r7} 800276a: af00 add r7, sp, #0 return SystemCoreClock; 800276c: 4b03 ldr r3, [pc, #12] @ (800277c ) 800276e: 681b ldr r3, [r3, #0] } 8002770: 4618 mov r0, r3 8002772: 46bd mov sp, r7 8002774: f85d 7b04 ldr.w r7, [sp], #4 8002778: 4770 bx lr 800277a: bf00 nop 800277c: 20000000 .word 0x20000000 08002780 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8002780: b580 push {r7, lr} 8002782: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); 8002784: f7ff fff0 bl 8002768 8002788: 4602 mov r2, r0 800278a: 4b06 ldr r3, [pc, #24] @ (80027a4 ) 800278c: 689b ldr r3, [r3, #8] 800278e: 0a1b lsrs r3, r3, #8 8002790: f003 0307 and.w r3, r3, #7 8002794: 4904 ldr r1, [pc, #16] @ (80027a8 ) 8002796: 5ccb ldrb r3, [r1, r3] 8002798: f003 031f and.w r3, r3, #31 800279c: fa22 f303 lsr.w r3, r2, r3 } 80027a0: 4618 mov r0, r3 80027a2: bd80 pop {r7, pc} 80027a4: 40021000 .word 0x40021000 80027a8: 080057a8 .word 0x080057a8 080027ac : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 80027ac: b580 push {r7, lr} 80027ae: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); 80027b0: f7ff ffda bl 8002768 80027b4: 4602 mov r2, r0 80027b6: 4b06 ldr r3, [pc, #24] @ (80027d0 ) 80027b8: 689b ldr r3, [r3, #8] 80027ba: 0adb lsrs r3, r3, #11 80027bc: f003 0307 and.w r3, r3, #7 80027c0: 4904 ldr r1, [pc, #16] @ (80027d4 ) 80027c2: 5ccb ldrb r3, [r1, r3] 80027c4: f003 031f and.w r3, r3, #31 80027c8: fa22 f303 lsr.w r3, r2, r3 } 80027cc: 4618 mov r0, r3 80027ce: bd80 pop {r7, pc} 80027d0: 40021000 .word 0x40021000 80027d4: 080057a8 .word 0x080057a8 080027d8 : /** * @brief Compute SYSCLK frequency based on PLL SYSCLK source. * @retval SYSCLK frequency */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { 80027d8: b480 push {r7} 80027da: b087 sub sp, #28 80027dc: af00 add r7, sp, #0 uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 80027de: 4b1e ldr r3, [pc, #120] @ (8002858 ) 80027e0: 68db ldr r3, [r3, #12] 80027e2: f003 0303 and.w r3, r3, #3 80027e6: 613b str r3, [r7, #16] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80027e8: 4b1b ldr r3, [pc, #108] @ (8002858 ) 80027ea: 68db ldr r3, [r3, #12] 80027ec: 091b lsrs r3, r3, #4 80027ee: f003 030f and.w r3, r3, #15 80027f2: 3301 adds r3, #1 80027f4: 60fb str r3, [r7, #12] switch (pllsource) 80027f6: 693b ldr r3, [r7, #16] 80027f8: 2b03 cmp r3, #3 80027fa: d10c bne.n 8002816 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 80027fc: 4a17 ldr r2, [pc, #92] @ (800285c ) 80027fe: 68fb ldr r3, [r7, #12] 8002800: fbb2 f3f3 udiv r3, r2, r3 8002804: 4a14 ldr r2, [pc, #80] @ (8002858 ) 8002806: 68d2 ldr r2, [r2, #12] 8002808: 0a12 lsrs r2, r2, #8 800280a: f002 027f and.w r2, r2, #127 @ 0x7f 800280e: fb02 f303 mul.w r3, r2, r3 8002812: 617b str r3, [r7, #20] break; 8002814: e00c b.n 8002830 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8002816: 4a12 ldr r2, [pc, #72] @ (8002860 ) 8002818: 68fb ldr r3, [r7, #12] 800281a: fbb2 f3f3 udiv r3, r2, r3 800281e: 4a0e ldr r2, [pc, #56] @ (8002858 ) 8002820: 68d2 ldr r2, [r2, #12] 8002822: 0a12 lsrs r2, r2, #8 8002824: f002 027f and.w r2, r2, #127 @ 0x7f 8002828: fb02 f303 mul.w r3, r2, r3 800282c: 617b str r3, [r7, #20] break; 800282e: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8002830: 4b09 ldr r3, [pc, #36] @ (8002858 ) 8002832: 68db ldr r3, [r3, #12] 8002834: 0e5b lsrs r3, r3, #25 8002836: f003 0303 and.w r3, r3, #3 800283a: 3301 adds r3, #1 800283c: 005b lsls r3, r3, #1 800283e: 60bb str r3, [r7, #8] sysclockfreq = pllvco/pllr; 8002840: 697a ldr r2, [r7, #20] 8002842: 68bb ldr r3, [r7, #8] 8002844: fbb2 f3f3 udiv r3, r2, r3 8002848: 607b str r3, [r7, #4] return sysclockfreq; 800284a: 687b ldr r3, [r7, #4] } 800284c: 4618 mov r0, r3 800284e: 371c adds r7, #28 8002850: 46bd mov sp, r7 8002852: f85d 7b04 ldr.w r7, [sp], #4 8002856: 4770 bx lr 8002858: 40021000 .word 0x40021000 800285c: 007a1200 .word 0x007a1200 8002860: 00f42400 .word 0x00f42400 08002864 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef const *PeriphClkInit) { 8002864: b580 push {r7, lr} 8002866: b086 sub sp, #24 8002868: af00 add r7, sp, #0 800286a: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800286c: 2300 movs r3, #0 800286e: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8002870: 2300 movs r3, #0 8002872: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8002874: 687b ldr r3, [r7, #4] 8002876: 681b ldr r3, [r3, #0] 8002878: f403 2300 and.w r3, r3, #524288 @ 0x80000 800287c: 2b00 cmp r3, #0 800287e: f000 8098 beq.w 80029b2 { FlagStatus pwrclkchanged = RESET; 8002882: 2300 movs r3, #0 8002884: 747b strb r3, [r7, #17] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8002886: 4b43 ldr r3, [pc, #268] @ (8002994 ) 8002888: 6d9b ldr r3, [r3, #88] @ 0x58 800288a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800288e: 2b00 cmp r3, #0 8002890: d10d bne.n 80028ae { __HAL_RCC_PWR_CLK_ENABLE(); 8002892: 4b40 ldr r3, [pc, #256] @ (8002994 ) 8002894: 6d9b ldr r3, [r3, #88] @ 0x58 8002896: 4a3f ldr r2, [pc, #252] @ (8002994 ) 8002898: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800289c: 6593 str r3, [r2, #88] @ 0x58 800289e: 4b3d ldr r3, [pc, #244] @ (8002994 ) 80028a0: 6d9b ldr r3, [r3, #88] @ 0x58 80028a2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80028a6: 60bb str r3, [r7, #8] 80028a8: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80028aa: 2301 movs r3, #1 80028ac: 747b strb r3, [r7, #17] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 80028ae: 4b3a ldr r3, [pc, #232] @ (8002998 ) 80028b0: 681b ldr r3, [r3, #0] 80028b2: 4a39 ldr r2, [pc, #228] @ (8002998 ) 80028b4: f443 7380 orr.w r3, r3, #256 @ 0x100 80028b8: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80028ba: f7fe fe6d bl 8001598 80028be: 60f8 str r0, [r7, #12] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 80028c0: e009 b.n 80028d6 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80028c2: f7fe fe69 bl 8001598 80028c6: 4602 mov r2, r0 80028c8: 68fb ldr r3, [r7, #12] 80028ca: 1ad3 subs r3, r2, r3 80028cc: 2b02 cmp r3, #2 80028ce: d902 bls.n 80028d6 { ret = HAL_TIMEOUT; 80028d0: 2303 movs r3, #3 80028d2: 74fb strb r3, [r7, #19] break; 80028d4: e005 b.n 80028e2 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 80028d6: 4b30 ldr r3, [pc, #192] @ (8002998 ) 80028d8: 681b ldr r3, [r3, #0] 80028da: f403 7380 and.w r3, r3, #256 @ 0x100 80028de: 2b00 cmp r3, #0 80028e0: d0ef beq.n 80028c2 } } if(ret == HAL_OK) 80028e2: 7cfb ldrb r3, [r7, #19] 80028e4: 2b00 cmp r3, #0 80028e6: d159 bne.n 800299c { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 80028e8: 4b2a ldr r3, [pc, #168] @ (8002994 ) 80028ea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80028ee: f403 7340 and.w r3, r3, #768 @ 0x300 80028f2: 617b str r3, [r7, #20] if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 80028f4: 697b ldr r3, [r7, #20] 80028f6: 2b00 cmp r3, #0 80028f8: d01e beq.n 8002938 80028fa: 687b ldr r3, [r7, #4] 80028fc: 6c1b ldr r3, [r3, #64] @ 0x40 80028fe: 697a ldr r2, [r7, #20] 8002900: 429a cmp r2, r3 8002902: d019 beq.n 8002938 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 8002904: 4b23 ldr r3, [pc, #140] @ (8002994 ) 8002906: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800290a: f423 7340 bic.w r3, r3, #768 @ 0x300 800290e: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8002910: 4b20 ldr r3, [pc, #128] @ (8002994 ) 8002912: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002916: 4a1f ldr r2, [pc, #124] @ (8002994 ) 8002918: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800291c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 8002920: 4b1c ldr r3, [pc, #112] @ (8002994 ) 8002922: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002926: 4a1b ldr r2, [pc, #108] @ (8002994 ) 8002928: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800292c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 8002930: 4a18 ldr r2, [pc, #96] @ (8002994 ) 8002932: 697b ldr r3, [r7, #20] 8002934: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 8002938: 697b ldr r3, [r7, #20] 800293a: f003 0301 and.w r3, r3, #1 800293e: 2b00 cmp r3, #0 8002940: d016 beq.n 8002970 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002942: f7fe fe29 bl 8001598 8002946: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002948: e00b b.n 8002962 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800294a: f7fe fe25 bl 8001598 800294e: 4602 mov r2, r0 8002950: 68fb ldr r3, [r7, #12] 8002952: 1ad3 subs r3, r2, r3 8002954: f241 3288 movw r2, #5000 @ 0x1388 8002958: 4293 cmp r3, r2 800295a: d902 bls.n 8002962 { ret = HAL_TIMEOUT; 800295c: 2303 movs r3, #3 800295e: 74fb strb r3, [r7, #19] break; 8002960: e006 b.n 8002970 while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8002962: 4b0c ldr r3, [pc, #48] @ (8002994 ) 8002964: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8002968: f003 0302 and.w r3, r3, #2 800296c: 2b00 cmp r3, #0 800296e: d0ec beq.n 800294a } } } if(ret == HAL_OK) 8002970: 7cfb ldrb r3, [r7, #19] 8002972: 2b00 cmp r3, #0 8002974: d10b bne.n 800298e { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8002976: 4b07 ldr r3, [pc, #28] @ (8002994 ) 8002978: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800297c: f423 7240 bic.w r2, r3, #768 @ 0x300 8002980: 687b ldr r3, [r7, #4] 8002982: 6c1b ldr r3, [r3, #64] @ 0x40 8002984: 4903 ldr r1, [pc, #12] @ (8002994 ) 8002986: 4313 orrs r3, r2 8002988: f8c1 3090 str.w r3, [r1, #144] @ 0x90 800298c: e008 b.n 80029a0 } else { /* set overall return value */ status = ret; 800298e: 7cfb ldrb r3, [r7, #19] 8002990: 74bb strb r3, [r7, #18] 8002992: e005 b.n 80029a0 8002994: 40021000 .word 0x40021000 8002998: 40007000 .word 0x40007000 } } else { /* set overall return value */ status = ret; 800299c: 7cfb ldrb r3, [r7, #19] 800299e: 74bb strb r3, [r7, #18] } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 80029a0: 7c7b ldrb r3, [r7, #17] 80029a2: 2b01 cmp r3, #1 80029a4: d105 bne.n 80029b2 { __HAL_RCC_PWR_CLK_DISABLE(); 80029a6: 4ba6 ldr r3, [pc, #664] @ (8002c40 ) 80029a8: 6d9b ldr r3, [r3, #88] @ 0x58 80029aa: 4aa5 ldr r2, [pc, #660] @ (8002c40 ) 80029ac: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80029b0: 6593 str r3, [r2, #88] @ 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 80029b2: 687b ldr r3, [r7, #4] 80029b4: 681b ldr r3, [r3, #0] 80029b6: f003 0301 and.w r3, r3, #1 80029ba: 2b00 cmp r3, #0 80029bc: d00a beq.n 80029d4 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 80029be: 4ba0 ldr r3, [pc, #640] @ (8002c40 ) 80029c0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80029c4: f023 0203 bic.w r2, r3, #3 80029c8: 687b ldr r3, [r7, #4] 80029ca: 685b ldr r3, [r3, #4] 80029cc: 499c ldr r1, [pc, #624] @ (8002c40 ) 80029ce: 4313 orrs r3, r2 80029d0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 80029d4: 687b ldr r3, [r7, #4] 80029d6: 681b ldr r3, [r3, #0] 80029d8: f003 0302 and.w r3, r3, #2 80029dc: 2b00 cmp r3, #0 80029de: d00a beq.n 80029f6 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 80029e0: 4b97 ldr r3, [pc, #604] @ (8002c40 ) 80029e2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80029e6: f023 020c bic.w r2, r3, #12 80029ea: 687b ldr r3, [r7, #4] 80029ec: 689b ldr r3, [r3, #8] 80029ee: 4994 ldr r1, [pc, #592] @ (8002c40 ) 80029f0: 4313 orrs r3, r2 80029f2: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(USART3) /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 80029f6: 687b ldr r3, [r7, #4] 80029f8: 681b ldr r3, [r3, #0] 80029fa: f003 0304 and.w r3, r3, #4 80029fe: 2b00 cmp r3, #0 8002a00: d00a beq.n 8002a18 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 8002a02: 4b8f ldr r3, [pc, #572] @ (8002c40 ) 8002a04: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002a08: f023 0230 bic.w r2, r3, #48 @ 0x30 8002a0c: 687b ldr r3, [r7, #4] 8002a0e: 68db ldr r3, [r3, #12] 8002a10: 498b ldr r1, [pc, #556] @ (8002c40 ) 8002a12: 4313 orrs r3, r2 8002a14: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* USART3 */ #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8002a18: 687b ldr r3, [r7, #4] 8002a1a: 681b ldr r3, [r3, #0] 8002a1c: f003 0308 and.w r3, r3, #8 8002a20: 2b00 cmp r3, #0 8002a22: d00a beq.n 8002a3a { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 8002a24: 4b86 ldr r3, [pc, #536] @ (8002c40 ) 8002a26: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002a2a: f023 02c0 bic.w r2, r3, #192 @ 0xc0 8002a2e: 687b ldr r3, [r7, #4] 8002a30: 691b ldr r3, [r3, #16] 8002a32: 4983 ldr r1, [pc, #524] @ (8002c40 ) 8002a34: 4313 orrs r3, r2 8002a36: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8002a3a: 687b ldr r3, [r7, #4] 8002a3c: 681b ldr r3, [r3, #0] 8002a3e: f003 0320 and.w r3, r3, #32 8002a42: 2b00 cmp r3, #0 8002a44: d00a beq.n 8002a5c { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8002a46: 4b7e ldr r3, [pc, #504] @ (8002c40 ) 8002a48: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002a4c: f423 6240 bic.w r2, r3, #3072 @ 0xc00 8002a50: 687b ldr r3, [r7, #4] 8002a52: 695b ldr r3, [r3, #20] 8002a54: 497a ldr r1, [pc, #488] @ (8002c40 ) 8002a56: 4313 orrs r3, r2 8002a58: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8002a5c: 687b ldr r3, [r7, #4] 8002a5e: 681b ldr r3, [r3, #0] 8002a60: f003 0340 and.w r3, r3, #64 @ 0x40 8002a64: 2b00 cmp r3, #0 8002a66: d00a beq.n 8002a7e { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8002a68: 4b75 ldr r3, [pc, #468] @ (8002c40 ) 8002a6a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002a6e: f423 5240 bic.w r2, r3, #12288 @ 0x3000 8002a72: 687b ldr r3, [r7, #4] 8002a74: 699b ldr r3, [r3, #24] 8002a76: 4972 ldr r1, [pc, #456] @ (8002c40 ) 8002a78: 4313 orrs r3, r2 8002a7a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 8002a7e: 687b ldr r3, [r7, #4] 8002a80: 681b ldr r3, [r3, #0] 8002a82: f003 0380 and.w r3, r3, #128 @ 0x80 8002a86: 2b00 cmp r3, #0 8002a88: d00a beq.n 8002aa0 { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 8002a8a: 4b6d ldr r3, [pc, #436] @ (8002c40 ) 8002a8c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002a90: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8002a94: 687b ldr r3, [r7, #4] 8002a96: 69db ldr r3, [r3, #28] 8002a98: 4969 ldr r1, [pc, #420] @ (8002c40 ) 8002a9a: 4313 orrs r3, r2 8002a9c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 8002aa0: 687b ldr r3, [r7, #4] 8002aa2: 681b ldr r3, [r3, #0] 8002aa4: f403 7380 and.w r3, r3, #256 @ 0x100 8002aa8: 2b00 cmp r3, #0 8002aaa: d00a beq.n 8002ac2 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 8002aac: 4b64 ldr r3, [pc, #400] @ (8002c40 ) 8002aae: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002ab2: f423 3240 bic.w r2, r3, #196608 @ 0x30000 8002ab6: 687b ldr r3, [r7, #4] 8002ab8: 6a1b ldr r3, [r3, #32] 8002aba: 4961 ldr r1, [pc, #388] @ (8002c40 ) 8002abc: 4313 orrs r3, r2 8002abe: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8002ac2: 687b ldr r3, [r7, #4] 8002ac4: 681b ldr r3, [r3, #0] 8002ac6: f403 7300 and.w r3, r3, #512 @ 0x200 8002aca: 2b00 cmp r3, #0 8002acc: d00a beq.n 8002ae4 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8002ace: 4b5c ldr r3, [pc, #368] @ (8002c40 ) 8002ad0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002ad4: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 8002ad8: 687b ldr r3, [r7, #4] 8002ada: 6a5b ldr r3, [r3, #36] @ 0x24 8002adc: 4958 ldr r1, [pc, #352] @ (8002c40 ) 8002ade: 4313 orrs r3, r2 8002ae0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8002ae4: 687b ldr r3, [r7, #4] 8002ae6: 681b ldr r3, [r3, #0] 8002ae8: f403 6380 and.w r3, r3, #1024 @ 0x400 8002aec: 2b00 cmp r3, #0 8002aee: d015 beq.n 8002b1c { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8002af0: 4b53 ldr r3, [pc, #332] @ (8002c40 ) 8002af2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002af6: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8002afa: 687b ldr r3, [r7, #4] 8002afc: 6a9b ldr r3, [r3, #40] @ 0x28 8002afe: 4950 ldr r1, [pc, #320] @ (8002c40 ) 8002b00: 4313 orrs r3, r2 8002b02: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 8002b06: 687b ldr r3, [r7, #4] 8002b08: 6a9b ldr r3, [r3, #40] @ 0x28 8002b0a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8002b0e: d105 bne.n 8002b1c { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8002b10: 4b4b ldr r3, [pc, #300] @ (8002c40 ) 8002b12: 68db ldr r3, [r3, #12] 8002b14: 4a4a ldr r2, [pc, #296] @ (8002c40 ) 8002b16: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8002b1a: 60d3 str r3, [r2, #12] #endif /* SAI1 */ #if defined(SPI_I2S_SUPPORT) /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 8002b1c: 687b ldr r3, [r7, #4] 8002b1e: 681b ldr r3, [r3, #0] 8002b20: f403 6300 and.w r3, r3, #2048 @ 0x800 8002b24: 2b00 cmp r3, #0 8002b26: d015 beq.n 8002b54 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 8002b28: 4b45 ldr r3, [pc, #276] @ (8002c40 ) 8002b2a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002b2e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8002b32: 687b ldr r3, [r7, #4] 8002b34: 6adb ldr r3, [r3, #44] @ 0x2c 8002b36: 4942 ldr r1, [pc, #264] @ (8002c40 ) 8002b38: 4313 orrs r3, r2 8002b3a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 8002b3e: 687b ldr r3, [r7, #4] 8002b40: 6adb ldr r3, [r3, #44] @ 0x2c 8002b42: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8002b46: d105 bne.n 8002b54 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8002b48: 4b3d ldr r3, [pc, #244] @ (8002c40 ) 8002b4a: 68db ldr r3, [r3, #12] 8002b4c: 4a3c ldr r2, [pc, #240] @ (8002c40 ) 8002b4e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8002b52: 60d3 str r3, [r2, #12] #endif /* SPI_I2S_SUPPORT */ #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8002b54: 687b ldr r3, [r7, #4] 8002b56: 681b ldr r3, [r3, #0] 8002b58: f403 5380 and.w r3, r3, #4096 @ 0x1000 8002b5c: 2b00 cmp r3, #0 8002b5e: d015 beq.n 8002b8c { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8002b60: 4b37 ldr r3, [pc, #220] @ (8002c40 ) 8002b62: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002b66: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 6b1b ldr r3, [r3, #48] @ 0x30 8002b6e: 4934 ldr r1, [pc, #208] @ (8002c40 ) 8002b70: 4313 orrs r3, r2 8002b72: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 8002b76: 687b ldr r3, [r7, #4] 8002b78: 6b1b ldr r3, [r3, #48] @ 0x30 8002b7a: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002b7e: d105 bne.n 8002b8c { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8002b80: 4b2f ldr r3, [pc, #188] @ (8002c40 ) 8002b82: 68db ldr r3, [r3, #12] 8002b84: 4a2e ldr r2, [pc, #184] @ (8002c40 ) 8002b86: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8002b8a: 60d3 str r3, [r2, #12] #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 8002b8c: 687b ldr r3, [r7, #4] 8002b8e: 681b ldr r3, [r3, #0] 8002b90: f403 5300 and.w r3, r3, #8192 @ 0x2000 8002b94: 2b00 cmp r3, #0 8002b96: d015 beq.n 8002bc4 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8002b98: 4b29 ldr r3, [pc, #164] @ (8002c40 ) 8002b9a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002b9e: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 8002ba2: 687b ldr r3, [r7, #4] 8002ba4: 6b5b ldr r3, [r3, #52] @ 0x34 8002ba6: 4926 ldr r1, [pc, #152] @ (8002c40 ) 8002ba8: 4313 orrs r3, r2 8002baa: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 8002bae: 687b ldr r3, [r7, #4] 8002bb0: 6b5b ldr r3, [r3, #52] @ 0x34 8002bb2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8002bb6: d105 bne.n 8002bc4 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8002bb8: 4b21 ldr r3, [pc, #132] @ (8002c40 ) 8002bba: 68db ldr r3, [r3, #12] 8002bbc: 4a20 ldr r2, [pc, #128] @ (8002c40 ) 8002bbe: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8002bc2: 60d3 str r3, [r2, #12] } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 8002bc4: 687b ldr r3, [r7, #4] 8002bc6: 681b ldr r3, [r3, #0] 8002bc8: f403 4380 and.w r3, r3, #16384 @ 0x4000 8002bcc: 2b00 cmp r3, #0 8002bce: d015 beq.n 8002bfc { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 8002bd0: 4b1b ldr r3, [pc, #108] @ (8002c40 ) 8002bd2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002bd6: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 8002bda: 687b ldr r3, [r7, #4] 8002bdc: 6b9b ldr r3, [r3, #56] @ 0x38 8002bde: 4918 ldr r1, [pc, #96] @ (8002c40 ) 8002be0: 4313 orrs r3, r2 8002be2: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 8002be6: 687b ldr r3, [r7, #4] 8002be8: 6b9b ldr r3, [r3, #56] @ 0x38 8002bea: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8002bee: d105 bne.n 8002bfc { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8002bf0: 4b13 ldr r3, [pc, #76] @ (8002c40 ) 8002bf2: 68db ldr r3, [r3, #12] 8002bf4: 4a12 ldr r2, [pc, #72] @ (8002c40 ) 8002bf6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8002bfa: 60d3 str r3, [r2, #12] } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 8002bfc: 687b ldr r3, [r7, #4] 8002bfe: 681b ldr r3, [r3, #0] 8002c00: f403 4300 and.w r3, r3, #32768 @ 0x8000 8002c04: 2b00 cmp r3, #0 8002c06: d015 beq.n 8002c34 { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 8002c08: 4b0d ldr r3, [pc, #52] @ (8002c40 ) 8002c0a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8002c0e: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 8002c12: 687b ldr r3, [r7, #4] 8002c14: 6bdb ldr r3, [r3, #60] @ 0x3c 8002c16: 490a ldr r1, [pc, #40] @ (8002c40 ) 8002c18: 4313 orrs r3, r2 8002c1a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 8002c1e: 687b ldr r3, [r7, #4] 8002c20: 6bdb ldr r3, [r3, #60] @ 0x3c 8002c22: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8002c26: d105 bne.n 8002c34 { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 8002c28: 4b05 ldr r3, [pc, #20] @ (8002c40 ) 8002c2a: 68db ldr r3, [r3, #12] 8002c2c: 4a04 ldr r2, [pc, #16] @ (8002c40 ) 8002c2e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8002c32: 60d3 str r3, [r2, #12] } } #endif /* QUADSPI */ return status; 8002c34: 7cbb ldrb r3, [r7, #18] } 8002c36: 4618 mov r0, r3 8002c38: 3718 adds r7, #24 8002c3a: 46bd mov sp, r7 8002c3c: bd80 pop {r7, pc} 8002c3e: bf00 nop 8002c40: 40021000 .word 0x40021000 08002c44 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8002c44: b580 push {r7, lr} 8002c46: b084 sub sp, #16 8002c48: af00 add r7, sp, #0 8002c4a: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 8002c4c: 687b ldr r3, [r7, #4] 8002c4e: 2b00 cmp r3, #0 8002c50: d101 bne.n 8002c56 { return HAL_ERROR; 8002c52: 2301 movs r3, #1 8002c54: e09d b.n 8002d92 assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 8002c56: 687b ldr r3, [r7, #4] 8002c58: 6a5b ldr r3, [r3, #36] @ 0x24 8002c5a: 2b00 cmp r3, #0 8002c5c: d108 bne.n 8002c70 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 8002c5e: 687b ldr r3, [r7, #4] 8002c60: 685b ldr r3, [r3, #4] 8002c62: f5b3 7f82 cmp.w r3, #260 @ 0x104 8002c66: d009 beq.n 8002c7c assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8002c68: 687b ldr r3, [r7, #4] 8002c6a: 2200 movs r2, #0 8002c6c: 61da str r2, [r3, #28] 8002c6e: e005 b.n 8002c7c else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 8002c70: 687b ldr r3, [r7, #4] 8002c72: 2200 movs r2, #0 8002c74: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 8002c76: 687b ldr r3, [r7, #4] 8002c78: 2200 movs r2, #0 8002c7a: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8002c7c: 687b ldr r3, [r7, #4] 8002c7e: 2200 movs r2, #0 8002c80: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 8002c82: 687b ldr r3, [r7, #4] 8002c84: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8002c88: b2db uxtb r3, r3 8002c8a: 2b00 cmp r3, #0 8002c8c: d106 bne.n 8002c9c { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 8002c8e: 687b ldr r3, [r7, #4] 8002c90: 2200 movs r2, #0 8002c92: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 8002c96: 6878 ldr r0, [r7, #4] 8002c98: f7fe fb02 bl 80012a0 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 8002c9c: 687b ldr r3, [r7, #4] 8002c9e: 2202 movs r2, #2 8002ca0: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8002ca4: 687b ldr r3, [r7, #4] 8002ca6: 681b ldr r3, [r3, #0] 8002ca8: 681a ldr r2, [r3, #0] 8002caa: 687b ldr r3, [r7, #4] 8002cac: 681b ldr r3, [r3, #0] 8002cae: f022 0240 bic.w r2, r2, #64 @ 0x40 8002cb2: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8002cb4: 687b ldr r3, [r7, #4] 8002cb6: 68db ldr r3, [r3, #12] 8002cb8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 8002cbc: d902 bls.n 8002cc4 { frxth = SPI_RXFIFO_THRESHOLD_HF; 8002cbe: 2300 movs r3, #0 8002cc0: 60fb str r3, [r7, #12] 8002cc2: e002 b.n 8002cca } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 8002cc4: f44f 5380 mov.w r3, #4096 @ 0x1000 8002cc8: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 8002cca: 687b ldr r3, [r7, #4] 8002ccc: 68db ldr r3, [r3, #12] 8002cce: f5b3 6f70 cmp.w r3, #3840 @ 0xf00 8002cd2: d007 beq.n 8002ce4 8002cd4: 687b ldr r3, [r7, #4] 8002cd6: 68db ldr r3, [r3, #12] 8002cd8: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 8002cdc: d002 beq.n 8002ce4 { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8002cde: 687b ldr r3, [r7, #4] 8002ce0: 2200 movs r2, #0 8002ce2: 629a str r2, [r3, #40] @ 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 8002ce4: 687b ldr r3, [r7, #4] 8002ce6: 685b ldr r3, [r3, #4] 8002ce8: f403 7282 and.w r2, r3, #260 @ 0x104 8002cec: 687b ldr r3, [r7, #4] 8002cee: 689b ldr r3, [r3, #8] 8002cf0: f403 4304 and.w r3, r3, #33792 @ 0x8400 8002cf4: 431a orrs r2, r3 8002cf6: 687b ldr r3, [r7, #4] 8002cf8: 691b ldr r3, [r3, #16] 8002cfa: f003 0302 and.w r3, r3, #2 8002cfe: 431a orrs r2, r3 8002d00: 687b ldr r3, [r7, #4] 8002d02: 695b ldr r3, [r3, #20] 8002d04: f003 0301 and.w r3, r3, #1 8002d08: 431a orrs r2, r3 8002d0a: 687b ldr r3, [r7, #4] 8002d0c: 699b ldr r3, [r3, #24] 8002d0e: f403 7300 and.w r3, r3, #512 @ 0x200 8002d12: 431a orrs r2, r3 8002d14: 687b ldr r3, [r7, #4] 8002d16: 69db ldr r3, [r3, #28] 8002d18: f003 0338 and.w r3, r3, #56 @ 0x38 8002d1c: 431a orrs r2, r3 8002d1e: 687b ldr r3, [r7, #4] 8002d20: 6a1b ldr r3, [r3, #32] 8002d22: f003 0380 and.w r3, r3, #128 @ 0x80 8002d26: ea42 0103 orr.w r1, r2, r3 8002d2a: 687b ldr r3, [r7, #4] 8002d2c: 6a9b ldr r3, [r3, #40] @ 0x28 8002d2e: f403 5200 and.w r2, r3, #8192 @ 0x2000 8002d32: 687b ldr r3, [r7, #4] 8002d34: 681b ldr r3, [r3, #0] 8002d36: 430a orrs r2, r1 8002d38: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 8002d3a: 687b ldr r3, [r7, #4] 8002d3c: 699b ldr r3, [r3, #24] 8002d3e: 0c1b lsrs r3, r3, #16 8002d40: f003 0204 and.w r2, r3, #4 8002d44: 687b ldr r3, [r7, #4] 8002d46: 6a5b ldr r3, [r3, #36] @ 0x24 8002d48: f003 0310 and.w r3, r3, #16 8002d4c: 431a orrs r2, r3 8002d4e: 687b ldr r3, [r7, #4] 8002d50: 6b5b ldr r3, [r3, #52] @ 0x34 8002d52: f003 0308 and.w r3, r3, #8 8002d56: 431a orrs r2, r3 8002d58: 687b ldr r3, [r7, #4] 8002d5a: 68db ldr r3, [r3, #12] 8002d5c: f403 6370 and.w r3, r3, #3840 @ 0xf00 8002d60: ea42 0103 orr.w r1, r2, r3 8002d64: 68fb ldr r3, [r7, #12] 8002d66: f403 5280 and.w r2, r3, #4096 @ 0x1000 8002d6a: 687b ldr r3, [r7, #4] 8002d6c: 681b ldr r3, [r3, #0] 8002d6e: 430a orrs r2, r1 8002d70: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 8002d72: 687b ldr r3, [r7, #4] 8002d74: 681b ldr r3, [r3, #0] 8002d76: 69da ldr r2, [r3, #28] 8002d78: 687b ldr r3, [r7, #4] 8002d7a: 681b ldr r3, [r3, #0] 8002d7c: f422 6200 bic.w r2, r2, #2048 @ 0x800 8002d80: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8002d82: 687b ldr r3, [r7, #4] 8002d84: 2200 movs r2, #0 8002d86: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 8002d88: 687b ldr r3, [r7, #4] 8002d8a: 2201 movs r2, #1 8002d8c: f883 205d strb.w r2, [r3, #93] @ 0x5d return HAL_OK; 8002d90: 2300 movs r3, #0 } 8002d92: 4618 mov r0, r3 8002d94: 3710 adds r7, #16 8002d96: 46bd mov sp, r7 8002d98: bd80 pop {r7, pc} 08002d9a : * @param Size amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration in ms * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8002d9a: b580 push {r7, lr} 8002d9c: b088 sub sp, #32 8002d9e: af00 add r7, sp, #0 8002da0: 60f8 str r0, [r7, #12] 8002da2: 60b9 str r1, [r7, #8] 8002da4: 603b str r3, [r7, #0] 8002da6: 4613 mov r3, r2 8002da8: 80fb strh r3, [r7, #6] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8002daa: f7fe fbf5 bl 8001598 8002dae: 61f8 str r0, [r7, #28] initial_TxXferCount = Size; 8002db0: 88fb ldrh r3, [r7, #6] 8002db2: 837b strh r3, [r7, #26] if (hspi->State != HAL_SPI_STATE_READY) 8002db4: 68fb ldr r3, [r7, #12] 8002db6: f893 305d ldrb.w r3, [r3, #93] @ 0x5d 8002dba: b2db uxtb r3, r3 8002dbc: 2b01 cmp r3, #1 8002dbe: d001 beq.n 8002dc4 { return HAL_BUSY; 8002dc0: 2302 movs r3, #2 8002dc2: e15c b.n 800307e } if ((pData == NULL) || (Size == 0U)) 8002dc4: 68bb ldr r3, [r7, #8] 8002dc6: 2b00 cmp r3, #0 8002dc8: d002 beq.n 8002dd0 8002dca: 88fb ldrh r3, [r7, #6] 8002dcc: 2b00 cmp r3, #0 8002dce: d101 bne.n 8002dd4 { return HAL_ERROR; 8002dd0: 2301 movs r3, #1 8002dd2: e154 b.n 800307e } /* Process Locked */ __HAL_LOCK(hspi); 8002dd4: 68fb ldr r3, [r7, #12] 8002dd6: f893 305c ldrb.w r3, [r3, #92] @ 0x5c 8002dda: 2b01 cmp r3, #1 8002ddc: d101 bne.n 8002de2 8002dde: 2302 movs r3, #2 8002de0: e14d b.n 800307e 8002de2: 68fb ldr r3, [r7, #12] 8002de4: 2201 movs r2, #1 8002de6: f883 205c strb.w r2, [r3, #92] @ 0x5c /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; 8002dea: 68fb ldr r3, [r7, #12] 8002dec: 2203 movs r2, #3 8002dee: f883 205d strb.w r2, [r3, #93] @ 0x5d hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8002df2: 68fb ldr r3, [r7, #12] 8002df4: 2200 movs r2, #0 8002df6: 661a str r2, [r3, #96] @ 0x60 hspi->pTxBuffPtr = (const uint8_t *)pData; 8002df8: 68fb ldr r3, [r7, #12] 8002dfa: 68ba ldr r2, [r7, #8] 8002dfc: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = Size; 8002dfe: 68fb ldr r3, [r7, #12] 8002e00: 88fa ldrh r2, [r7, #6] 8002e02: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = Size; 8002e04: 68fb ldr r3, [r7, #12] 8002e06: 88fa ldrh r2, [r7, #6] 8002e08: 87da strh r2, [r3, #62] @ 0x3e /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; 8002e0a: 68fb ldr r3, [r7, #12] 8002e0c: 2200 movs r2, #0 8002e0e: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = 0U; 8002e10: 68fb ldr r3, [r7, #12] 8002e12: 2200 movs r2, #0 8002e14: f8a3 2044 strh.w r2, [r3, #68] @ 0x44 hspi->RxXferCount = 0U; 8002e18: 68fb ldr r3, [r7, #12] 8002e1a: 2200 movs r2, #0 8002e1c: f8a3 2046 strh.w r2, [r3, #70] @ 0x46 hspi->TxISR = NULL; 8002e20: 68fb ldr r3, [r7, #12] 8002e22: 2200 movs r2, #0 8002e24: 651a str r2, [r3, #80] @ 0x50 hspi->RxISR = NULL; 8002e26: 68fb ldr r3, [r7, #12] 8002e28: 2200 movs r2, #0 8002e2a: 64da str r2, [r3, #76] @ 0x4c /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 8002e2c: 68fb ldr r3, [r7, #12] 8002e2e: 689b ldr r3, [r3, #8] 8002e30: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8002e34: d10f bne.n 8002e56 { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 8002e36: 68fb ldr r3, [r7, #12] 8002e38: 681b ldr r3, [r3, #0] 8002e3a: 681a ldr r2, [r3, #0] 8002e3c: 68fb ldr r3, [r7, #12] 8002e3e: 681b ldr r3, [r3, #0] 8002e40: f022 0240 bic.w r2, r2, #64 @ 0x40 8002e44: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); 8002e46: 68fb ldr r3, [r7, #12] 8002e48: 681b ldr r3, [r3, #0] 8002e4a: 681a ldr r2, [r3, #0] 8002e4c: 68fb ldr r3, [r7, #12] 8002e4e: 681b ldr r3, [r3, #0] 8002e50: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8002e54: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8002e56: 68fb ldr r3, [r7, #12] 8002e58: 681b ldr r3, [r3, #0] 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: f003 0340 and.w r3, r3, #64 @ 0x40 8002e60: 2b40 cmp r3, #64 @ 0x40 8002e62: d007 beq.n 8002e74 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8002e64: 68fb ldr r3, [r7, #12] 8002e66: 681b ldr r3, [r3, #0] 8002e68: 681a ldr r2, [r3, #0] 8002e6a: 68fb ldr r3, [r7, #12] 8002e6c: 681b ldr r3, [r3, #0] 8002e6e: f042 0240 orr.w r2, r2, #64 @ 0x40 8002e72: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8002e74: 68fb ldr r3, [r7, #12] 8002e76: 68db ldr r3, [r3, #12] 8002e78: f5b3 6fe0 cmp.w r3, #1792 @ 0x700 8002e7c: d952 bls.n 8002f24 { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8002e7e: 68fb ldr r3, [r7, #12] 8002e80: 685b ldr r3, [r3, #4] 8002e82: 2b00 cmp r3, #0 8002e84: d002 beq.n 8002e8c 8002e86: 8b7b ldrh r3, [r7, #26] 8002e88: 2b01 cmp r3, #1 8002e8a: d145 bne.n 8002f18 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8002e8c: 68fb ldr r3, [r7, #12] 8002e8e: 6b9b ldr r3, [r3, #56] @ 0x38 8002e90: 881a ldrh r2, [r3, #0] 8002e92: 68fb ldr r3, [r7, #12] 8002e94: 681b ldr r3, [r3, #0] 8002e96: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8002e98: 68fb ldr r3, [r7, #12] 8002e9a: 6b9b ldr r3, [r3, #56] @ 0x38 8002e9c: 1c9a adds r2, r3, #2 8002e9e: 68fb ldr r3, [r7, #12] 8002ea0: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8002ea2: 68fb ldr r3, [r7, #12] 8002ea4: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002ea6: b29b uxth r3, r3 8002ea8: 3b01 subs r3, #1 8002eaa: b29a uxth r2, r3 8002eac: 68fb ldr r3, [r7, #12] 8002eae: 87da strh r2, [r3, #62] @ 0x3e } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) 8002eb0: e032 b.n 8002f18 { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 8002eb2: 68fb ldr r3, [r7, #12] 8002eb4: 681b ldr r3, [r3, #0] 8002eb6: 689b ldr r3, [r3, #8] 8002eb8: f003 0302 and.w r3, r3, #2 8002ebc: 2b02 cmp r3, #2 8002ebe: d112 bne.n 8002ee6 { hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8002ec0: 68fb ldr r3, [r7, #12] 8002ec2: 6b9b ldr r3, [r3, #56] @ 0x38 8002ec4: 881a ldrh r2, [r3, #0] 8002ec6: 68fb ldr r3, [r7, #12] 8002ec8: 681b ldr r3, [r3, #0] 8002eca: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8002ecc: 68fb ldr r3, [r7, #12] 8002ece: 6b9b ldr r3, [r3, #56] @ 0x38 8002ed0: 1c9a adds r2, r3, #2 8002ed2: 68fb ldr r3, [r7, #12] 8002ed4: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8002ed6: 68fb ldr r3, [r7, #12] 8002ed8: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002eda: b29b uxth r3, r3 8002edc: 3b01 subs r3, #1 8002ede: b29a uxth r2, r3 8002ee0: 68fb ldr r3, [r7, #12] 8002ee2: 87da strh r2, [r3, #62] @ 0x3e 8002ee4: e018 b.n 8002f18 } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8002ee6: f7fe fb57 bl 8001598 8002eea: 4602 mov r2, r0 8002eec: 69fb ldr r3, [r7, #28] 8002eee: 1ad3 subs r3, r2, r3 8002ef0: 683a ldr r2, [r7, #0] 8002ef2: 429a cmp r2, r3 8002ef4: d803 bhi.n 8002efe 8002ef6: 683b ldr r3, [r7, #0] 8002ef8: f1b3 3fff cmp.w r3, #4294967295 8002efc: d102 bne.n 8002f04 8002efe: 683b ldr r3, [r7, #0] 8002f00: 2b00 cmp r3, #0 8002f02: d109 bne.n 8002f18 { hspi->State = HAL_SPI_STATE_READY; 8002f04: 68fb ldr r3, [r7, #12] 8002f06: 2201 movs r2, #1 8002f08: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 8002f0c: 68fb ldr r3, [r7, #12] 8002f0e: 2200 movs r2, #0 8002f10: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 8002f14: 2303 movs r3, #3 8002f16: e0b2 b.n 800307e while (hspi->TxXferCount > 0U) 8002f18: 68fb ldr r3, [r7, #12] 8002f1a: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002f1c: b29b uxth r3, r3 8002f1e: 2b00 cmp r3, #0 8002f20: d1c7 bne.n 8002eb2 8002f22: e083 b.n 800302c } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8002f24: 68fb ldr r3, [r7, #12] 8002f26: 685b ldr r3, [r3, #4] 8002f28: 2b00 cmp r3, #0 8002f2a: d002 beq.n 8002f32 8002f2c: 8b7b ldrh r3, [r7, #26] 8002f2e: 2b01 cmp r3, #1 8002f30: d177 bne.n 8003022 { if (hspi->TxXferCount > 1U) 8002f32: 68fb ldr r3, [r7, #12] 8002f34: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002f36: b29b uxth r3, r3 8002f38: 2b01 cmp r3, #1 8002f3a: d912 bls.n 8002f62 { /* write on the data register in packing mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8002f3c: 68fb ldr r3, [r7, #12] 8002f3e: 6b9b ldr r3, [r3, #56] @ 0x38 8002f40: 881a ldrh r2, [r3, #0] 8002f42: 68fb ldr r3, [r7, #12] 8002f44: 681b ldr r3, [r3, #0] 8002f46: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8002f48: 68fb ldr r3, [r7, #12] 8002f4a: 6b9b ldr r3, [r3, #56] @ 0x38 8002f4c: 1c9a adds r2, r3, #2 8002f4e: 68fb ldr r3, [r7, #12] 8002f50: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 8002f52: 68fb ldr r3, [r7, #12] 8002f54: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002f56: b29b uxth r3, r3 8002f58: 3b02 subs r3, #2 8002f5a: b29a uxth r2, r3 8002f5c: 68fb ldr r3, [r7, #12] 8002f5e: 87da strh r2, [r3, #62] @ 0x3e 8002f60: e05f b.n 8003022 } else { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 8002f62: 68fb ldr r3, [r7, #12] 8002f64: 6b9a ldr r2, [r3, #56] @ 0x38 8002f66: 68fb ldr r3, [r7, #12] 8002f68: 681b ldr r3, [r3, #0] 8002f6a: 330c adds r3, #12 8002f6c: 7812 ldrb r2, [r2, #0] 8002f6e: 701a strb r2, [r3, #0] hspi->pTxBuffPtr ++; 8002f70: 68fb ldr r3, [r7, #12] 8002f72: 6b9b ldr r3, [r3, #56] @ 0x38 8002f74: 1c5a adds r2, r3, #1 8002f76: 68fb ldr r3, [r7, #12] 8002f78: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8002f7a: 68fb ldr r3, [r7, #12] 8002f7c: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002f7e: b29b uxth r3, r3 8002f80: 3b01 subs r3, #1 8002f82: b29a uxth r2, r3 8002f84: 68fb ldr r3, [r7, #12] 8002f86: 87da strh r2, [r3, #62] @ 0x3e } } while (hspi->TxXferCount > 0U) 8002f88: e04b b.n 8003022 { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 8002f8a: 68fb ldr r3, [r7, #12] 8002f8c: 681b ldr r3, [r3, #0] 8002f8e: 689b ldr r3, [r3, #8] 8002f90: f003 0302 and.w r3, r3, #2 8002f94: 2b02 cmp r3, #2 8002f96: d12b bne.n 8002ff0 { if (hspi->TxXferCount > 1U) 8002f98: 68fb ldr r3, [r7, #12] 8002f9a: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002f9c: b29b uxth r3, r3 8002f9e: 2b01 cmp r3, #1 8002fa0: d912 bls.n 8002fc8 { /* write on the data register in packing mode */ hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); 8002fa2: 68fb ldr r3, [r7, #12] 8002fa4: 6b9b ldr r3, [r3, #56] @ 0x38 8002fa6: 881a ldrh r2, [r3, #0] 8002fa8: 68fb ldr r3, [r7, #12] 8002faa: 681b ldr r3, [r3, #0] 8002fac: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8002fae: 68fb ldr r3, [r7, #12] 8002fb0: 6b9b ldr r3, [r3, #56] @ 0x38 8002fb2: 1c9a adds r2, r3, #2 8002fb4: 68fb ldr r3, [r7, #12] 8002fb6: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount -= 2U; 8002fb8: 68fb ldr r3, [r7, #12] 8002fba: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002fbc: b29b uxth r3, r3 8002fbe: 3b02 subs r3, #2 8002fc0: b29a uxth r2, r3 8002fc2: 68fb ldr r3, [r7, #12] 8002fc4: 87da strh r2, [r3, #62] @ 0x3e 8002fc6: e02c b.n 8003022 } else { *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); 8002fc8: 68fb ldr r3, [r7, #12] 8002fca: 6b9a ldr r2, [r3, #56] @ 0x38 8002fcc: 68fb ldr r3, [r7, #12] 8002fce: 681b ldr r3, [r3, #0] 8002fd0: 330c adds r3, #12 8002fd2: 7812 ldrb r2, [r2, #0] 8002fd4: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 8002fd6: 68fb ldr r3, [r7, #12] 8002fd8: 6b9b ldr r3, [r3, #56] @ 0x38 8002fda: 1c5a adds r2, r3, #1 8002fdc: 68fb ldr r3, [r7, #12] 8002fde: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8002fe0: 68fb ldr r3, [r7, #12] 8002fe2: 8fdb ldrh r3, [r3, #62] @ 0x3e 8002fe4: b29b uxth r3, r3 8002fe6: 3b01 subs r3, #1 8002fe8: b29a uxth r2, r3 8002fea: 68fb ldr r3, [r7, #12] 8002fec: 87da strh r2, [r3, #62] @ 0x3e 8002fee: e018 b.n 8003022 } } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8002ff0: f7fe fad2 bl 8001598 8002ff4: 4602 mov r2, r0 8002ff6: 69fb ldr r3, [r7, #28] 8002ff8: 1ad3 subs r3, r2, r3 8002ffa: 683a ldr r2, [r7, #0] 8002ffc: 429a cmp r2, r3 8002ffe: d803 bhi.n 8003008 8003000: 683b ldr r3, [r7, #0] 8003002: f1b3 3fff cmp.w r3, #4294967295 8003006: d102 bne.n 800300e 8003008: 683b ldr r3, [r7, #0] 800300a: 2b00 cmp r3, #0 800300c: d109 bne.n 8003022 { hspi->State = HAL_SPI_STATE_READY; 800300e: 68fb ldr r3, [r7, #12] 8003010: 2201 movs r2, #1 8003012: f883 205d strb.w r2, [r3, #93] @ 0x5d __HAL_UNLOCK(hspi); 8003016: 68fb ldr r3, [r7, #12] 8003018: 2200 movs r2, #0 800301a: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 800301e: 2303 movs r3, #3 8003020: e02d b.n 800307e while (hspi->TxXferCount > 0U) 8003022: 68fb ldr r3, [r7, #12] 8003024: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003026: b29b uxth r3, r3 8003028: 2b00 cmp r3, #0 800302a: d1ae bne.n 8002f8a SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800302c: 69fa ldr r2, [r7, #28] 800302e: 6839 ldr r1, [r7, #0] 8003030: 68f8 ldr r0, [r7, #12] 8003032: f000 f947 bl 80032c4 8003036: 4603 mov r3, r0 8003038: 2b00 cmp r3, #0 800303a: d002 beq.n 8003042 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 800303c: 68fb ldr r3, [r7, #12] 800303e: 2220 movs r2, #32 8003040: 661a str r2, [r3, #96] @ 0x60 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 8003042: 68fb ldr r3, [r7, #12] 8003044: 689b ldr r3, [r3, #8] 8003046: 2b00 cmp r3, #0 8003048: d10a bne.n 8003060 { __HAL_SPI_CLEAR_OVRFLAG(hspi); 800304a: 2300 movs r3, #0 800304c: 617b str r3, [r7, #20] 800304e: 68fb ldr r3, [r7, #12] 8003050: 681b ldr r3, [r3, #0] 8003052: 68db ldr r3, [r3, #12] 8003054: 617b str r3, [r7, #20] 8003056: 68fb ldr r3, [r7, #12] 8003058: 681b ldr r3, [r3, #0] 800305a: 689b ldr r3, [r3, #8] 800305c: 617b str r3, [r7, #20] 800305e: 697b ldr r3, [r7, #20] } hspi->State = HAL_SPI_STATE_READY; 8003060: 68fb ldr r3, [r7, #12] 8003062: 2201 movs r2, #1 8003064: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 8003068: 68fb ldr r3, [r7, #12] 800306a: 2200 movs r2, #0 800306c: f883 205c strb.w r2, [r3, #92] @ 0x5c if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8003070: 68fb ldr r3, [r7, #12] 8003072: 6e1b ldr r3, [r3, #96] @ 0x60 8003074: 2b00 cmp r3, #0 8003076: d001 beq.n 800307c { return HAL_ERROR; 8003078: 2301 movs r3, #1 800307a: e000 b.n 800307e } else { return HAL_OK; 800307c: 2300 movs r3, #0 } } 800307e: 4618 mov r0, r3 8003080: 3720 adds r7, #32 8003082: 46bd mov sp, r7 8003084: bd80 pop {r7, pc} ... 08003088 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 8003088: b580 push {r7, lr} 800308a: b088 sub sp, #32 800308c: af00 add r7, sp, #0 800308e: 60f8 str r0, [r7, #12] 8003090: 60b9 str r1, [r7, #8] 8003092: 603b str r3, [r7, #0] 8003094: 4613 mov r3, r2 8003096: 71fb strb r3, [r7, #7] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 8003098: f7fe fa7e bl 8001598 800309c: 4602 mov r2, r0 800309e: 6abb ldr r3, [r7, #40] @ 0x28 80030a0: 1a9b subs r3, r3, r2 80030a2: 683a ldr r2, [r7, #0] 80030a4: 4413 add r3, r2 80030a6: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 80030a8: f7fe fa76 bl 8001598 80030ac: 61b8 str r0, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 80030ae: 4b39 ldr r3, [pc, #228] @ (8003194 ) 80030b0: 681b ldr r3, [r3, #0] 80030b2: 015b lsls r3, r3, #5 80030b4: 0d1b lsrs r3, r3, #20 80030b6: 69fa ldr r2, [r7, #28] 80030b8: fb02 f303 mul.w r3, r2, r3 80030bc: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 80030be: e055 b.n 800316c { if (Timeout != HAL_MAX_DELAY) 80030c0: 683b ldr r3, [r7, #0] 80030c2: f1b3 3fff cmp.w r3, #4294967295 80030c6: d051 beq.n 800316c { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 80030c8: f7fe fa66 bl 8001598 80030cc: 4602 mov r2, r0 80030ce: 69bb ldr r3, [r7, #24] 80030d0: 1ad3 subs r3, r2, r3 80030d2: 69fa ldr r2, [r7, #28] 80030d4: 429a cmp r2, r3 80030d6: d902 bls.n 80030de 80030d8: 69fb ldr r3, [r7, #28] 80030da: 2b00 cmp r3, #0 80030dc: d13d bne.n 800315a /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 80030de: 68fb ldr r3, [r7, #12] 80030e0: 681b ldr r3, [r3, #0] 80030e2: 685a ldr r2, [r3, #4] 80030e4: 68fb ldr r3, [r7, #12] 80030e6: 681b ldr r3, [r3, #0] 80030e8: f022 02e0 bic.w r2, r2, #224 @ 0xe0 80030ec: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 80030ee: 68fb ldr r3, [r7, #12] 80030f0: 685b ldr r3, [r3, #4] 80030f2: f5b3 7f82 cmp.w r3, #260 @ 0x104 80030f6: d111 bne.n 800311c 80030f8: 68fb ldr r3, [r7, #12] 80030fa: 689b ldr r3, [r3, #8] 80030fc: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8003100: d004 beq.n 800310c || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 8003102: 68fb ldr r3, [r7, #12] 8003104: 689b ldr r3, [r3, #8] 8003106: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800310a: d107 bne.n 800311c { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 800310c: 68fb ldr r3, [r7, #12] 800310e: 681b ldr r3, [r3, #0] 8003110: 681a ldr r2, [r3, #0] 8003112: 68fb ldr r3, [r7, #12] 8003114: 681b ldr r3, [r3, #0] 8003116: f022 0240 bic.w r2, r2, #64 @ 0x40 800311a: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 800311c: 68fb ldr r3, [r7, #12] 800311e: 6a9b ldr r3, [r3, #40] @ 0x28 8003120: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8003124: d10f bne.n 8003146 { SPI_RESET_CRC(hspi); 8003126: 68fb ldr r3, [r7, #12] 8003128: 681b ldr r3, [r3, #0] 800312a: 681a ldr r2, [r3, #0] 800312c: 68fb ldr r3, [r7, #12] 800312e: 681b ldr r3, [r3, #0] 8003130: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8003134: 601a str r2, [r3, #0] 8003136: 68fb ldr r3, [r7, #12] 8003138: 681b ldr r3, [r3, #0] 800313a: 681a ldr r2, [r3, #0] 800313c: 68fb ldr r3, [r7, #12] 800313e: 681b ldr r3, [r3, #0] 8003140: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8003144: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 8003146: 68fb ldr r3, [r7, #12] 8003148: 2201 movs r2, #1 800314a: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 800314e: 68fb ldr r3, [r7, #12] 8003150: 2200 movs r2, #0 8003152: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 8003156: 2303 movs r3, #3 8003158: e018 b.n 800318c } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 800315a: 697b ldr r3, [r7, #20] 800315c: 2b00 cmp r3, #0 800315e: d102 bne.n 8003166 { tmp_timeout = 0U; 8003160: 2300 movs r3, #0 8003162: 61fb str r3, [r7, #28] 8003164: e002 b.n 800316c } else { count--; 8003166: 697b ldr r3, [r7, #20] 8003168: 3b01 subs r3, #1 800316a: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 800316c: 68fb ldr r3, [r7, #12] 800316e: 681b ldr r3, [r3, #0] 8003170: 689a ldr r2, [r3, #8] 8003172: 68bb ldr r3, [r7, #8] 8003174: 4013 ands r3, r2 8003176: 68ba ldr r2, [r7, #8] 8003178: 429a cmp r2, r3 800317a: bf0c ite eq 800317c: 2301 moveq r3, #1 800317e: 2300 movne r3, #0 8003180: b2db uxtb r3, r3 8003182: 461a mov r2, r3 8003184: 79fb ldrb r3, [r7, #7] 8003186: 429a cmp r2, r3 8003188: d19a bne.n 80030c0 } } } return HAL_OK; 800318a: 2300 movs r3, #0 } 800318c: 4618 mov r0, r3 800318e: 3720 adds r7, #32 8003190: 46bd mov sp, r7 8003192: bd80 pop {r7, pc} 8003194: 20000000 .word 0x20000000 08003198 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { 8003198: b580 push {r7, lr} 800319a: b08a sub sp, #40 @ 0x28 800319c: af00 add r7, sp, #0 800319e: 60f8 str r0, [r7, #12] 80031a0: 60b9 str r1, [r7, #8] 80031a2: 607a str r2, [r7, #4] 80031a4: 603b str r3, [r7, #0] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; 80031a6: 2300 movs r3, #0 80031a8: 75fb strb r3, [r7, #23] /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 80031aa: f7fe f9f5 bl 8001598 80031ae: 4602 mov r2, r0 80031b0: 6b3b ldr r3, [r7, #48] @ 0x30 80031b2: 1a9b subs r3, r3, r2 80031b4: 683a ldr r2, [r7, #0] 80031b6: 4413 add r3, r2 80031b8: 627b str r3, [r7, #36] @ 0x24 tmp_tickstart = HAL_GetTick(); 80031ba: f7fe f9ed bl 8001598 80031be: 6238 str r0, [r7, #32] /* Initialize the 8bit temporary pointer */ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; 80031c0: 68fb ldr r3, [r7, #12] 80031c2: 681b ldr r3, [r3, #0] 80031c4: 330c adds r3, #12 80031c6: 61fb str r3, [r7, #28] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); 80031c8: 4b3d ldr r3, [pc, #244] @ (80032c0 ) 80031ca: 681a ldr r2, [r3, #0] 80031cc: 4613 mov r3, r2 80031ce: 009b lsls r3, r3, #2 80031d0: 4413 add r3, r2 80031d2: 00da lsls r2, r3, #3 80031d4: 1ad3 subs r3, r2, r3 80031d6: 0d1b lsrs r3, r3, #20 80031d8: 6a7a ldr r2, [r7, #36] @ 0x24 80031da: fb02 f303 mul.w r3, r2, r3 80031de: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 80031e0: e061 b.n 80032a6 { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) 80031e2: 68bb ldr r3, [r7, #8] 80031e4: f5b3 6fc0 cmp.w r3, #1536 @ 0x600 80031e8: d107 bne.n 80031fa 80031ea: 687b ldr r3, [r7, #4] 80031ec: 2b00 cmp r3, #0 80031ee: d104 bne.n 80031fa { /* Flush Data Register by a blank read */ tmpreg8 = *ptmpreg8; 80031f0: 69fb ldr r3, [r7, #28] 80031f2: 781b ldrb r3, [r3, #0] 80031f4: b2db uxtb r3, r3 80031f6: 75fb strb r3, [r7, #23] /* To avoid GCC warning */ UNUSED(tmpreg8); 80031f8: 7dfb ldrb r3, [r7, #23] } if (Timeout != HAL_MAX_DELAY) 80031fa: 683b ldr r3, [r7, #0] 80031fc: f1b3 3fff cmp.w r3, #4294967295 8003200: d051 beq.n 80032a6 { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 8003202: f7fe f9c9 bl 8001598 8003206: 4602 mov r2, r0 8003208: 6a3b ldr r3, [r7, #32] 800320a: 1ad3 subs r3, r2, r3 800320c: 6a7a ldr r2, [r7, #36] @ 0x24 800320e: 429a cmp r2, r3 8003210: d902 bls.n 8003218 8003212: 6a7b ldr r3, [r7, #36] @ 0x24 8003214: 2b00 cmp r3, #0 8003216: d13d bne.n 8003294 /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 8003218: 68fb ldr r3, [r7, #12] 800321a: 681b ldr r3, [r3, #0] 800321c: 685a ldr r2, [r3, #4] 800321e: 68fb ldr r3, [r7, #12] 8003220: 681b ldr r3, [r3, #0] 8003222: f022 02e0 bic.w r2, r2, #224 @ 0xe0 8003226: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 8003228: 68fb ldr r3, [r7, #12] 800322a: 685b ldr r3, [r3, #4] 800322c: f5b3 7f82 cmp.w r3, #260 @ 0x104 8003230: d111 bne.n 8003256 8003232: 68fb ldr r3, [r7, #12] 8003234: 689b ldr r3, [r3, #8] 8003236: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800323a: d004 beq.n 8003246 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800323c: 68fb ldr r3, [r7, #12] 800323e: 689b ldr r3, [r3, #8] 8003240: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003244: d107 bne.n 8003256 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8003246: 68fb ldr r3, [r7, #12] 8003248: 681b ldr r3, [r3, #0] 800324a: 681a ldr r2, [r3, #0] 800324c: 68fb ldr r3, [r7, #12] 800324e: 681b ldr r3, [r3, #0] 8003250: f022 0240 bic.w r2, r2, #64 @ 0x40 8003254: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 8003256: 68fb ldr r3, [r7, #12] 8003258: 6a9b ldr r3, [r3, #40] @ 0x28 800325a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800325e: d10f bne.n 8003280 { SPI_RESET_CRC(hspi); 8003260: 68fb ldr r3, [r7, #12] 8003262: 681b ldr r3, [r3, #0] 8003264: 681a ldr r2, [r3, #0] 8003266: 68fb ldr r3, [r7, #12] 8003268: 681b ldr r3, [r3, #0] 800326a: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800326e: 601a str r2, [r3, #0] 8003270: 68fb ldr r3, [r7, #12] 8003272: 681b ldr r3, [r3, #0] 8003274: 681a ldr r2, [r3, #0] 8003276: 68fb ldr r3, [r7, #12] 8003278: 681b ldr r3, [r3, #0] 800327a: f442 5200 orr.w r2, r2, #8192 @ 0x2000 800327e: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 8003280: 68fb ldr r3, [r7, #12] 8003282: 2201 movs r2, #1 8003284: f883 205d strb.w r2, [r3, #93] @ 0x5d /* Process Unlocked */ __HAL_UNLOCK(hspi); 8003288: 68fb ldr r3, [r7, #12] 800328a: 2200 movs r2, #0 800328c: f883 205c strb.w r2, [r3, #92] @ 0x5c return HAL_TIMEOUT; 8003290: 2303 movs r3, #3 8003292: e011 b.n 80032b8 } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 8003294: 69bb ldr r3, [r7, #24] 8003296: 2b00 cmp r3, #0 8003298: d102 bne.n 80032a0 { tmp_timeout = 0U; 800329a: 2300 movs r3, #0 800329c: 627b str r3, [r7, #36] @ 0x24 800329e: e002 b.n 80032a6 } else { count--; 80032a0: 69bb ldr r3, [r7, #24] 80032a2: 3b01 subs r3, #1 80032a4: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 80032a6: 68fb ldr r3, [r7, #12] 80032a8: 681b ldr r3, [r3, #0] 80032aa: 689a ldr r2, [r3, #8] 80032ac: 68bb ldr r3, [r7, #8] 80032ae: 4013 ands r3, r2 80032b0: 687a ldr r2, [r7, #4] 80032b2: 429a cmp r2, r3 80032b4: d195 bne.n 80031e2 } } } return HAL_OK; 80032b6: 2300 movs r3, #0 } 80032b8: 4618 mov r0, r3 80032ba: 3728 adds r7, #40 @ 0x28 80032bc: 46bd mov sp, r7 80032be: bd80 pop {r7, pc} 80032c0: 20000000 .word 0x20000000 080032c4 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 80032c4: b580 push {r7, lr} 80032c6: b086 sub sp, #24 80032c8: af02 add r7, sp, #8 80032ca: 60f8 str r0, [r7, #12] 80032cc: 60b9 str r1, [r7, #8] 80032ce: 607a str r2, [r7, #4] /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 80032d0: 687b ldr r3, [r7, #4] 80032d2: 9300 str r3, [sp, #0] 80032d4: 68bb ldr r3, [r7, #8] 80032d6: 2200 movs r2, #0 80032d8: f44f 51c0 mov.w r1, #6144 @ 0x1800 80032dc: 68f8 ldr r0, [r7, #12] 80032de: f7ff ff5b bl 8003198 80032e2: 4603 mov r3, r0 80032e4: 2b00 cmp r3, #0 80032e6: d007 beq.n 80032f8 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 80032e8: 68fb ldr r3, [r7, #12] 80032ea: 6e1b ldr r3, [r3, #96] @ 0x60 80032ec: f043 0220 orr.w r2, r3, #32 80032f0: 68fb ldr r3, [r7, #12] 80032f2: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 80032f4: 2303 movs r3, #3 80032f6: e027 b.n 8003348 } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 80032f8: 687b ldr r3, [r7, #4] 80032fa: 9300 str r3, [sp, #0] 80032fc: 68bb ldr r3, [r7, #8] 80032fe: 2200 movs r2, #0 8003300: 2180 movs r1, #128 @ 0x80 8003302: 68f8 ldr r0, [r7, #12] 8003304: f7ff fec0 bl 8003088 8003308: 4603 mov r3, r0 800330a: 2b00 cmp r3, #0 800330c: d007 beq.n 800331e { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800330e: 68fb ldr r3, [r7, #12] 8003310: 6e1b ldr r3, [r3, #96] @ 0x60 8003312: f043 0220 orr.w r2, r3, #32 8003316: 68fb ldr r3, [r7, #12] 8003318: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800331a: 2303 movs r3, #3 800331c: e014 b.n 8003348 } /* Control if the RX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 800331e: 687b ldr r3, [r7, #4] 8003320: 9300 str r3, [sp, #0] 8003322: 68bb ldr r3, [r7, #8] 8003324: 2200 movs r2, #0 8003326: f44f 61c0 mov.w r1, #1536 @ 0x600 800332a: 68f8 ldr r0, [r7, #12] 800332c: f7ff ff34 bl 8003198 8003330: 4603 mov r3, r0 8003332: 2b00 cmp r3, #0 8003334: d007 beq.n 8003346 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8003336: 68fb ldr r3, [r7, #12] 8003338: 6e1b ldr r3, [r3, #96] @ 0x60 800333a: f043 0220 orr.w r2, r3, #32 800333e: 68fb ldr r3, [r7, #12] 8003340: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 8003342: 2303 movs r3, #3 8003344: e000 b.n 8003348 } return HAL_OK; 8003346: 2300 movs r3, #0 } 8003348: 4618 mov r0, r3 800334a: 3710 adds r7, #16 800334c: 46bd mov sp, r7 800334e: bd80 pop {r7, pc} 08003350 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8003350: b580 push {r7, lr} 8003352: b082 sub sp, #8 8003354: af00 add r7, sp, #0 8003356: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8003358: 687b ldr r3, [r7, #4] 800335a: 2b00 cmp r3, #0 800335c: d101 bne.n 8003362 { return HAL_ERROR; 800335e: 2301 movs r3, #1 8003360: e042 b.n 80033e8 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8003362: 687b ldr r3, [r7, #4] 8003364: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003368: 2b00 cmp r3, #0 800336a: d106 bne.n 800337a { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 800336c: 687b ldr r3, [r7, #4] 800336e: 2200 movs r2, #0 8003370: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8003374: 6878 ldr r0, [r7, #4] 8003376: f7fd ffd5 bl 8001324 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 800337a: 687b ldr r3, [r7, #4] 800337c: 2224 movs r2, #36 @ 0x24 800337e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 8003382: 687b ldr r3, [r7, #4] 8003384: 681b ldr r3, [r3, #0] 8003386: 681a ldr r2, [r3, #0] 8003388: 687b ldr r3, [r7, #4] 800338a: 681b ldr r3, [r3, #0] 800338c: f022 0201 bic.w r2, r2, #1 8003390: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8003392: 687b ldr r3, [r7, #4] 8003394: 6a9b ldr r3, [r3, #40] @ 0x28 8003396: 2b00 cmp r3, #0 8003398: d002 beq.n 80033a0 { UART_AdvFeatureConfig(huart); 800339a: 6878 ldr r0, [r7, #4] 800339c: f000 fea2 bl 80040e4 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80033a0: 6878 ldr r0, [r7, #4] 80033a2: f000 fbd3 bl 8003b4c 80033a6: 4603 mov r3, r0 80033a8: 2b01 cmp r3, #1 80033aa: d101 bne.n 80033b0 { return HAL_ERROR; 80033ac: 2301 movs r3, #1 80033ae: e01b b.n 80033e8 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80033b0: 687b ldr r3, [r7, #4] 80033b2: 681b ldr r3, [r3, #0] 80033b4: 685a ldr r2, [r3, #4] 80033b6: 687b ldr r3, [r7, #4] 80033b8: 681b ldr r3, [r3, #0] 80033ba: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80033be: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80033c0: 687b ldr r3, [r7, #4] 80033c2: 681b ldr r3, [r3, #0] 80033c4: 689a ldr r2, [r3, #8] 80033c6: 687b ldr r3, [r7, #4] 80033c8: 681b ldr r3, [r3, #0] 80033ca: f022 022a bic.w r2, r2, #42 @ 0x2a 80033ce: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80033d0: 687b ldr r3, [r7, #4] 80033d2: 681b ldr r3, [r3, #0] 80033d4: 681a ldr r2, [r3, #0] 80033d6: 687b ldr r3, [r7, #4] 80033d8: 681b ldr r3, [r3, #0] 80033da: f042 0201 orr.w r2, r2, #1 80033de: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80033e0: 6878 ldr r0, [r7, #4] 80033e2: f000 ff21 bl 8004228 80033e6: 4603 mov r3, r0 } 80033e8: 4618 mov r0, r3 80033ea: 3708 adds r7, #8 80033ec: 46bd mov sp, r7 80033ee: bd80 pop {r7, pc} 080033f0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80033f0: b580 push {r7, lr} 80033f2: b08a sub sp, #40 @ 0x28 80033f4: af00 add r7, sp, #0 80033f6: 60f8 str r0, [r7, #12] 80033f8: 60b9 str r1, [r7, #8] 80033fa: 4613 mov r3, r2 80033fc: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 80033fe: 68fb ldr r3, [r7, #12] 8003400: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8003404: 2b20 cmp r3, #32 8003406: d137 bne.n 8003478 { if ((pData == NULL) || (Size == 0U)) 8003408: 68bb ldr r3, [r7, #8] 800340a: 2b00 cmp r3, #0 800340c: d002 beq.n 8003414 800340e: 88fb ldrh r3, [r7, #6] 8003410: 2b00 cmp r3, #0 8003412: d101 bne.n 8003418 { return HAL_ERROR; 8003414: 2301 movs r3, #1 8003416: e030 b.n 800347a } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8003418: 68fb ldr r3, [r7, #12] 800341a: 2200 movs r2, #0 800341c: 66da str r2, [r3, #108] @ 0x6c if (!(IS_LPUART_INSTANCE(huart->Instance))) 800341e: 68fb ldr r3, [r7, #12] 8003420: 681b ldr r3, [r3, #0] 8003422: 4a18 ldr r2, [pc, #96] @ (8003484 ) 8003424: 4293 cmp r3, r2 8003426: d01f beq.n 8003468 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8003428: 68fb ldr r3, [r7, #12] 800342a: 681b ldr r3, [r3, #0] 800342c: 685b ldr r3, [r3, #4] 800342e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8003432: 2b00 cmp r3, #0 8003434: d018 beq.n 8003468 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8003436: 68fb ldr r3, [r7, #12] 8003438: 681b ldr r3, [r3, #0] 800343a: 617b str r3, [r7, #20] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800343c: 697b ldr r3, [r7, #20] 800343e: e853 3f00 ldrex r3, [r3] 8003442: 613b str r3, [r7, #16] return(result); 8003444: 693b ldr r3, [r7, #16] 8003446: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800344a: 627b str r3, [r7, #36] @ 0x24 800344c: 68fb ldr r3, [r7, #12] 800344e: 681b ldr r3, [r3, #0] 8003450: 461a mov r2, r3 8003452: 6a7b ldr r3, [r7, #36] @ 0x24 8003454: 623b str r3, [r7, #32] 8003456: 61fa str r2, [r7, #28] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8003458: 69f9 ldr r1, [r7, #28] 800345a: 6a3a ldr r2, [r7, #32] 800345c: e841 2300 strex r3, r2, [r1] 8003460: 61bb str r3, [r7, #24] return(result); 8003462: 69bb ldr r3, [r7, #24] 8003464: 2b00 cmp r3, #0 8003466: d1e6 bne.n 8003436 } } return (UART_Start_Receive_IT(huart, pData, Size)); 8003468: 88fb ldrh r3, [r7, #6] 800346a: 461a mov r2, r3 800346c: 68b9 ldr r1, [r7, #8] 800346e: 68f8 ldr r0, [r7, #12] 8003470: f000 fff2 bl 8004458 8003474: 4603 mov r3, r0 8003476: e000 b.n 800347a } else { return HAL_BUSY; 8003478: 2302 movs r3, #2 } } 800347a: 4618 mov r0, r3 800347c: 3728 adds r7, #40 @ 0x28 800347e: 46bd mov sp, r7 8003480: bd80 pop {r7, pc} 8003482: bf00 nop 8003484: 40008000 .word 0x40008000 08003488 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8003488: b580 push {r7, lr} 800348a: b0ba sub sp, #232 @ 0xe8 800348c: af00 add r7, sp, #0 800348e: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8003490: 687b ldr r3, [r7, #4] 8003492: 681b ldr r3, [r3, #0] 8003494: 69db ldr r3, [r3, #28] 8003496: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800349a: 687b ldr r3, [r7, #4] 800349c: 681b ldr r3, [r3, #0] 800349e: 681b ldr r3, [r3, #0] 80034a0: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80034a4: 687b ldr r3, [r7, #4] 80034a6: 681b ldr r3, [r3, #0] 80034a8: 689b ldr r3, [r3, #8] 80034aa: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 80034ae: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 80034b2: f640 030f movw r3, #2063 @ 0x80f 80034b6: 4013 ands r3, r2 80034b8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 80034bc: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80034c0: 2b00 cmp r3, #0 80034c2: d11b bne.n 80034fc { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80034c4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80034c8: f003 0320 and.w r3, r3, #32 80034cc: 2b00 cmp r3, #0 80034ce: d015 beq.n 80034fc && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80034d0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80034d4: f003 0320 and.w r3, r3, #32 80034d8: 2b00 cmp r3, #0 80034da: d105 bne.n 80034e8 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80034dc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80034e0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80034e4: 2b00 cmp r3, #0 80034e6: d009 beq.n 80034fc { if (huart->RxISR != NULL) 80034e8: 687b ldr r3, [r7, #4] 80034ea: 6f5b ldr r3, [r3, #116] @ 0x74 80034ec: 2b00 cmp r3, #0 80034ee: f000 8300 beq.w 8003af2 { huart->RxISR(huart); 80034f2: 687b ldr r3, [r7, #4] 80034f4: 6f5b ldr r3, [r3, #116] @ 0x74 80034f6: 6878 ldr r0, [r7, #4] 80034f8: 4798 blx r3 } return; 80034fa: e2fa b.n 8003af2 } } /* If some errors occur */ if ((errorflags != 0U) 80034fc: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8003500: 2b00 cmp r3, #0 8003502: f000 8123 beq.w 800374c && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8003506: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 800350a: 4b8d ldr r3, [pc, #564] @ (8003740 ) 800350c: 4013 ands r3, r2 800350e: 2b00 cmp r3, #0 8003510: d106 bne.n 8003520 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8003512: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8003516: 4b8b ldr r3, [pc, #556] @ (8003744 ) 8003518: 4013 ands r3, r2 800351a: 2b00 cmp r3, #0 800351c: f000 8116 beq.w 800374c { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8003520: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003524: f003 0301 and.w r3, r3, #1 8003528: 2b00 cmp r3, #0 800352a: d011 beq.n 8003550 800352c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8003530: f403 7380 and.w r3, r3, #256 @ 0x100 8003534: 2b00 cmp r3, #0 8003536: d00b beq.n 8003550 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8003538: 687b ldr r3, [r7, #4] 800353a: 681b ldr r3, [r3, #0] 800353c: 2201 movs r2, #1 800353e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8003540: 687b ldr r3, [r7, #4] 8003542: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003546: f043 0201 orr.w r2, r3, #1 800354a: 687b ldr r3, [r7, #4] 800354c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8003550: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003554: f003 0302 and.w r3, r3, #2 8003558: 2b00 cmp r3, #0 800355a: d011 beq.n 8003580 800355c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8003560: f003 0301 and.w r3, r3, #1 8003564: 2b00 cmp r3, #0 8003566: d00b beq.n 8003580 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8003568: 687b ldr r3, [r7, #4] 800356a: 681b ldr r3, [r3, #0] 800356c: 2202 movs r2, #2 800356e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8003570: 687b ldr r3, [r7, #4] 8003572: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003576: f043 0204 orr.w r2, r3, #4 800357a: 687b ldr r3, [r7, #4] 800357c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8003580: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003584: f003 0304 and.w r3, r3, #4 8003588: 2b00 cmp r3, #0 800358a: d011 beq.n 80035b0 800358c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8003590: f003 0301 and.w r3, r3, #1 8003594: 2b00 cmp r3, #0 8003596: d00b beq.n 80035b0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8003598: 687b ldr r3, [r7, #4] 800359a: 681b ldr r3, [r3, #0] 800359c: 2204 movs r2, #4 800359e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80035a0: 687b ldr r3, [r7, #4] 80035a2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80035a6: f043 0202 orr.w r2, r3, #2 80035aa: 687b ldr r3, [r7, #4] 80035ac: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 80035b0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80035b4: f003 0308 and.w r3, r3, #8 80035b8: 2b00 cmp r3, #0 80035ba: d017 beq.n 80035ec && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80035bc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80035c0: f003 0320 and.w r3, r3, #32 80035c4: 2b00 cmp r3, #0 80035c6: d105 bne.n 80035d4 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80035c8: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80035cc: 4b5c ldr r3, [pc, #368] @ (8003740 ) 80035ce: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80035d0: 2b00 cmp r3, #0 80035d2: d00b beq.n 80035ec { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80035d4: 687b ldr r3, [r7, #4] 80035d6: 681b ldr r3, [r3, #0] 80035d8: 2208 movs r2, #8 80035da: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80035dc: 687b ldr r3, [r7, #4] 80035de: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80035e2: f043 0208 orr.w r2, r3, #8 80035e6: 687b ldr r3, [r7, #4] 80035e8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80035ec: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80035f0: f403 6300 and.w r3, r3, #2048 @ 0x800 80035f4: 2b00 cmp r3, #0 80035f6: d012 beq.n 800361e 80035f8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80035fc: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8003600: 2b00 cmp r3, #0 8003602: d00c beq.n 800361e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8003604: 687b ldr r3, [r7, #4] 8003606: 681b ldr r3, [r3, #0] 8003608: f44f 6200 mov.w r2, #2048 @ 0x800 800360c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 800360e: 687b ldr r3, [r7, #4] 8003610: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003614: f043 0220 orr.w r2, r3, #32 8003618: 687b ldr r3, [r7, #4] 800361a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800361e: 687b ldr r3, [r7, #4] 8003620: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003624: 2b00 cmp r3, #0 8003626: f000 8266 beq.w 8003af6 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800362a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800362e: f003 0320 and.w r3, r3, #32 8003632: 2b00 cmp r3, #0 8003634: d013 beq.n 800365e && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8003636: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 800363a: f003 0320 and.w r3, r3, #32 800363e: 2b00 cmp r3, #0 8003640: d105 bne.n 800364e || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8003642: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8003646: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800364a: 2b00 cmp r3, #0 800364c: d007 beq.n 800365e { if (huart->RxISR != NULL) 800364e: 687b ldr r3, [r7, #4] 8003650: 6f5b ldr r3, [r3, #116] @ 0x74 8003652: 2b00 cmp r3, #0 8003654: d003 beq.n 800365e { huart->RxISR(huart); 8003656: 687b ldr r3, [r7, #4] 8003658: 6f5b ldr r3, [r3, #116] @ 0x74 800365a: 6878 ldr r0, [r7, #4] 800365c: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 800365e: 687b ldr r3, [r7, #4] 8003660: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003664: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8003668: 687b ldr r3, [r7, #4] 800366a: 681b ldr r3, [r3, #0] 800366c: 689b ldr r3, [r3, #8] 800366e: f003 0340 and.w r3, r3, #64 @ 0x40 8003672: 2b40 cmp r3, #64 @ 0x40 8003674: d005 beq.n 8003682 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8003676: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 800367a: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800367e: 2b00 cmp r3, #0 8003680: d054 beq.n 800372c { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8003682: 6878 ldr r0, [r7, #4] 8003684: f001 f80a bl 800469c /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8003688: 687b ldr r3, [r7, #4] 800368a: 681b ldr r3, [r3, #0] 800368c: 689b ldr r3, [r3, #8] 800368e: f003 0340 and.w r3, r3, #64 @ 0x40 8003692: 2b40 cmp r3, #64 @ 0x40 8003694: d146 bne.n 8003724 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8003696: 687b ldr r3, [r7, #4] 8003698: 681b ldr r3, [r3, #0] 800369a: 3308 adds r3, #8 800369c: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80036a0: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80036a4: e853 3f00 ldrex r3, [r3] 80036a8: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80036ac: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80036b0: f023 0340 bic.w r3, r3, #64 @ 0x40 80036b4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80036b8: 687b ldr r3, [r7, #4] 80036ba: 681b ldr r3, [r3, #0] 80036bc: 3308 adds r3, #8 80036be: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80036c2: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80036c6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80036ca: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80036ce: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80036d2: e841 2300 strex r3, r2, [r1] 80036d6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80036da: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80036de: 2b00 cmp r3, #0 80036e0: d1d9 bne.n 8003696 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80036e2: 687b ldr r3, [r7, #4] 80036e4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80036e8: 2b00 cmp r3, #0 80036ea: d017 beq.n 800371c { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80036ec: 687b ldr r3, [r7, #4] 80036ee: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80036f2: 4a15 ldr r2, [pc, #84] @ (8003748 ) 80036f4: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80036f6: 687b ldr r3, [r7, #4] 80036f8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80036fc: 4618 mov r0, r3 80036fe: f7fe f8c4 bl 800188a 8003702: 4603 mov r3, r0 8003704: 2b00 cmp r3, #0 8003706: d019 beq.n 800373c { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8003708: 687b ldr r3, [r7, #4] 800370a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800370e: 6b9b ldr r3, [r3, #56] @ 0x38 8003710: 687a ldr r2, [r7, #4] 8003712: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8003716: 4610 mov r0, r2 8003718: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800371a: e00f b.n 800373c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800371c: 6878 ldr r0, [r7, #4] 800371e: f000 f9ff bl 8003b20 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8003722: e00b b.n 800373c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8003724: 6878 ldr r0, [r7, #4] 8003726: f000 f9fb bl 8003b20 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800372a: e007 b.n 800373c #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800372c: 6878 ldr r0, [r7, #4] 800372e: f000 f9f7 bl 8003b20 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8003732: 687b ldr r3, [r7, #4] 8003734: 2200 movs r2, #0 8003736: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 800373a: e1dc b.n 8003af6 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800373c: bf00 nop return; 800373e: e1da b.n 8003af6 8003740: 10000001 .word 0x10000001 8003744: 04000120 .word 0x04000120 8003748: 08004769 .word 0x08004769 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800374c: 687b ldr r3, [r7, #4] 800374e: 6edb ldr r3, [r3, #108] @ 0x6c 8003750: 2b01 cmp r3, #1 8003752: f040 8170 bne.w 8003a36 && ((isrflags & USART_ISR_IDLE) != 0U) 8003756: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800375a: f003 0310 and.w r3, r3, #16 800375e: 2b00 cmp r3, #0 8003760: f000 8169 beq.w 8003a36 && ((cr1its & USART_ISR_IDLE) != 0U)) 8003764: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8003768: f003 0310 and.w r3, r3, #16 800376c: 2b00 cmp r3, #0 800376e: f000 8162 beq.w 8003a36 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8003772: 687b ldr r3, [r7, #4] 8003774: 681b ldr r3, [r3, #0] 8003776: 2210 movs r2, #16 8003778: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800377a: 687b ldr r3, [r7, #4] 800377c: 681b ldr r3, [r3, #0] 800377e: 689b ldr r3, [r3, #8] 8003780: f003 0340 and.w r3, r3, #64 @ 0x40 8003784: 2b40 cmp r3, #64 @ 0x40 8003786: f040 80d8 bne.w 800393a { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 800378a: 687b ldr r3, [r7, #4] 800378c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8003790: 681b ldr r3, [r3, #0] 8003792: 685b ldr r3, [r3, #4] 8003794: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8003798: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 800379c: 2b00 cmp r3, #0 800379e: f000 80af beq.w 8003900 && (nb_remaining_rx_data < huart->RxXferSize)) 80037a2: 687b ldr r3, [r7, #4] 80037a4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80037a8: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80037ac: 429a cmp r2, r3 80037ae: f080 80a7 bcs.w 8003900 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80037b2: 687b ldr r3, [r7, #4] 80037b4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80037b8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) 80037bc: 687b ldr r3, [r7, #4] 80037be: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80037c2: 681b ldr r3, [r3, #0] 80037c4: 681b ldr r3, [r3, #0] 80037c6: f003 0320 and.w r3, r3, #32 80037ca: 2b00 cmp r3, #0 80037cc: f040 8087 bne.w 80038de { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80037d0: 687b ldr r3, [r7, #4] 80037d2: 681b ldr r3, [r3, #0] 80037d4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80037d8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80037dc: e853 3f00 ldrex r3, [r3] 80037e0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80037e4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80037e8: f423 7380 bic.w r3, r3, #256 @ 0x100 80037ec: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80037f0: 687b ldr r3, [r7, #4] 80037f2: 681b ldr r3, [r3, #0] 80037f4: 461a mov r2, r3 80037f6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 80037fa: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80037fe: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8003802: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8003806: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800380a: e841 2300 strex r3, r2, [r1] 800380e: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8003812: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8003816: 2b00 cmp r3, #0 8003818: d1da bne.n 80037d0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800381a: 687b ldr r3, [r7, #4] 800381c: 681b ldr r3, [r3, #0] 800381e: 3308 adds r3, #8 8003820: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8003822: 6f7b ldr r3, [r7, #116] @ 0x74 8003824: e853 3f00 ldrex r3, [r3] 8003828: 673b str r3, [r7, #112] @ 0x70 return(result); 800382a: 6f3b ldr r3, [r7, #112] @ 0x70 800382c: f023 0301 bic.w r3, r3, #1 8003830: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8003834: 687b ldr r3, [r7, #4] 8003836: 681b ldr r3, [r3, #0] 8003838: 3308 adds r3, #8 800383a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 800383e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8003842: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8003844: 6ff9 ldr r1, [r7, #124] @ 0x7c 8003846: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800384a: e841 2300 strex r3, r2, [r1] 800384e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8003850: 6fbb ldr r3, [r7, #120] @ 0x78 8003852: 2b00 cmp r3, #0 8003854: d1e1 bne.n 800381a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8003856: 687b ldr r3, [r7, #4] 8003858: 681b ldr r3, [r3, #0] 800385a: 3308 adds r3, #8 800385c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800385e: 6e3b ldr r3, [r7, #96] @ 0x60 8003860: e853 3f00 ldrex r3, [r3] 8003864: 65fb str r3, [r7, #92] @ 0x5c return(result); 8003866: 6dfb ldr r3, [r7, #92] @ 0x5c 8003868: f023 0340 bic.w r3, r3, #64 @ 0x40 800386c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8003870: 687b ldr r3, [r7, #4] 8003872: 681b ldr r3, [r3, #0] 8003874: 3308 adds r3, #8 8003876: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 800387a: 66fa str r2, [r7, #108] @ 0x6c 800387c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800387e: 6eb9 ldr r1, [r7, #104] @ 0x68 8003880: 6efa ldr r2, [r7, #108] @ 0x6c 8003882: e841 2300 strex r3, r2, [r1] 8003886: 667b str r3, [r7, #100] @ 0x64 return(result); 8003888: 6e7b ldr r3, [r7, #100] @ 0x64 800388a: 2b00 cmp r3, #0 800388c: d1e3 bne.n 8003856 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800388e: 687b ldr r3, [r7, #4] 8003890: 2220 movs r2, #32 8003892: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8003896: 687b ldr r3, [r7, #4] 8003898: 2200 movs r2, #0 800389a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800389c: 687b ldr r3, [r7, #4] 800389e: 681b ldr r3, [r3, #0] 80038a0: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80038a2: 6cfb ldr r3, [r7, #76] @ 0x4c 80038a4: e853 3f00 ldrex r3, [r3] 80038a8: 64bb str r3, [r7, #72] @ 0x48 return(result); 80038aa: 6cbb ldr r3, [r7, #72] @ 0x48 80038ac: f023 0310 bic.w r3, r3, #16 80038b0: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80038b4: 687b ldr r3, [r7, #4] 80038b6: 681b ldr r3, [r3, #0] 80038b8: 461a mov r2, r3 80038ba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80038be: 65bb str r3, [r7, #88] @ 0x58 80038c0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80038c2: 6d79 ldr r1, [r7, #84] @ 0x54 80038c4: 6dba ldr r2, [r7, #88] @ 0x58 80038c6: e841 2300 strex r3, r2, [r1] 80038ca: 653b str r3, [r7, #80] @ 0x50 return(result); 80038cc: 6d3b ldr r3, [r7, #80] @ 0x50 80038ce: 2b00 cmp r3, #0 80038d0: d1e4 bne.n 800389c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80038d2: 687b ldr r3, [r7, #4] 80038d4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80038d8: 4618 mov r0, r3 80038da: f7fd ff78 bl 80017ce } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80038de: 687b ldr r3, [r7, #4] 80038e0: 2202 movs r2, #2 80038e2: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80038e4: 687b ldr r3, [r7, #4] 80038e6: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 80038ea: 687b ldr r3, [r7, #4] 80038ec: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80038f0: b29b uxth r3, r3 80038f2: 1ad3 subs r3, r2, r3 80038f4: b29b uxth r3, r3 80038f6: 4619 mov r1, r3 80038f8: 6878 ldr r0, [r7, #4] 80038fa: f000 f91b bl 8003b34 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 80038fe: e0fc b.n 8003afa if (nb_remaining_rx_data == huart->RxXferSize) 8003900: 687b ldr r3, [r7, #4] 8003902: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8003906: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800390a: 429a cmp r2, r3 800390c: f040 80f5 bne.w 8003afa if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) 8003910: 687b ldr r3, [r7, #4] 8003912: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8003916: 681b ldr r3, [r3, #0] 8003918: 681b ldr r3, [r3, #0] 800391a: f003 0320 and.w r3, r3, #32 800391e: 2b20 cmp r3, #32 8003920: f040 80eb bne.w 8003afa huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8003924: 687b ldr r3, [r7, #4] 8003926: 2202 movs r2, #2 8003928: 671a str r2, [r3, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800392a: 687b ldr r3, [r7, #4] 800392c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8003930: 4619 mov r1, r3 8003932: 6878 ldr r0, [r7, #4] 8003934: f000 f8fe bl 8003b34 return; 8003938: e0df b.n 8003afa else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 800393a: 687b ldr r3, [r7, #4] 800393c: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8003940: 687b ldr r3, [r7, #4] 8003942: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8003946: b29b uxth r3, r3 8003948: 1ad3 subs r3, r2, r3 800394a: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 800394e: 687b ldr r3, [r7, #4] 8003950: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8003954: b29b uxth r3, r3 8003956: 2b00 cmp r3, #0 8003958: f000 80d1 beq.w 8003afe && (nb_rx_data > 0U)) 800395c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8003960: 2b00 cmp r3, #0 8003962: f000 80cc beq.w 8003afe { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8003966: 687b ldr r3, [r7, #4] 8003968: 681b ldr r3, [r3, #0] 800396a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800396c: 6bbb ldr r3, [r7, #56] @ 0x38 800396e: e853 3f00 ldrex r3, [r3] 8003972: 637b str r3, [r7, #52] @ 0x34 return(result); 8003974: 6b7b ldr r3, [r7, #52] @ 0x34 8003976: f423 7390 bic.w r3, r3, #288 @ 0x120 800397a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800397e: 687b ldr r3, [r7, #4] 8003980: 681b ldr r3, [r3, #0] 8003982: 461a mov r2, r3 8003984: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8003988: 647b str r3, [r7, #68] @ 0x44 800398a: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800398c: 6c39 ldr r1, [r7, #64] @ 0x40 800398e: 6c7a ldr r2, [r7, #68] @ 0x44 8003990: e841 2300 strex r3, r2, [r1] 8003994: 63fb str r3, [r7, #60] @ 0x3c return(result); 8003996: 6bfb ldr r3, [r7, #60] @ 0x3c 8003998: 2b00 cmp r3, #0 800399a: d1e4 bne.n 8003966 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800399c: 687b ldr r3, [r7, #4] 800399e: 681b ldr r3, [r3, #0] 80039a0: 3308 adds r3, #8 80039a2: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80039a4: 6a7b ldr r3, [r7, #36] @ 0x24 80039a6: e853 3f00 ldrex r3, [r3] 80039aa: 623b str r3, [r7, #32] return(result); 80039ac: 6a3b ldr r3, [r7, #32] 80039ae: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80039b2: f023 0301 bic.w r3, r3, #1 80039b6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80039ba: 687b ldr r3, [r7, #4] 80039bc: 681b ldr r3, [r3, #0] 80039be: 3308 adds r3, #8 80039c0: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80039c4: 633a str r2, [r7, #48] @ 0x30 80039c6: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80039c8: 6af9 ldr r1, [r7, #44] @ 0x2c 80039ca: 6b3a ldr r2, [r7, #48] @ 0x30 80039cc: e841 2300 strex r3, r2, [r1] 80039d0: 62bb str r3, [r7, #40] @ 0x28 return(result); 80039d2: 6abb ldr r3, [r7, #40] @ 0x28 80039d4: 2b00 cmp r3, #0 80039d6: d1e1 bne.n 800399c /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80039d8: 687b ldr r3, [r7, #4] 80039da: 2220 movs r2, #32 80039dc: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80039e0: 687b ldr r3, [r7, #4] 80039e2: 2200 movs r2, #0 80039e4: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80039e6: 687b ldr r3, [r7, #4] 80039e8: 2200 movs r2, #0 80039ea: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80039ec: 687b ldr r3, [r7, #4] 80039ee: 681b ldr r3, [r3, #0] 80039f0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80039f2: 693b ldr r3, [r7, #16] 80039f4: e853 3f00 ldrex r3, [r3] 80039f8: 60fb str r3, [r7, #12] return(result); 80039fa: 68fb ldr r3, [r7, #12] 80039fc: f023 0310 bic.w r3, r3, #16 8003a00: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8003a04: 687b ldr r3, [r7, #4] 8003a06: 681b ldr r3, [r3, #0] 8003a08: 461a mov r2, r3 8003a0a: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8003a0e: 61fb str r3, [r7, #28] 8003a10: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8003a12: 69b9 ldr r1, [r7, #24] 8003a14: 69fa ldr r2, [r7, #28] 8003a16: e841 2300 strex r3, r2, [r1] 8003a1a: 617b str r3, [r7, #20] return(result); 8003a1c: 697b ldr r3, [r7, #20] 8003a1e: 2b00 cmp r3, #0 8003a20: d1e4 bne.n 80039ec /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8003a22: 687b ldr r3, [r7, #4] 8003a24: 2202 movs r2, #2 8003a26: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8003a28: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8003a2c: 4619 mov r1, r3 8003a2e: 6878 ldr r0, [r7, #4] 8003a30: f000 f880 bl 8003b34 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8003a34: e063 b.n 8003afe } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8003a36: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003a3a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003a3e: 2b00 cmp r3, #0 8003a40: d00e beq.n 8003a60 8003a42: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8003a46: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8003a4a: 2b00 cmp r3, #0 8003a4c: d008 beq.n 8003a60 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8003a4e: 687b ldr r3, [r7, #4] 8003a50: 681b ldr r3, [r3, #0] 8003a52: f44f 1280 mov.w r2, #1048576 @ 0x100000 8003a56: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8003a58: 6878 ldr r0, [r7, #4] 8003a5a: f001 fbdf bl 800521c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8003a5e: e051 b.n 8003b04 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8003a60: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003a64: f003 0380 and.w r3, r3, #128 @ 0x80 8003a68: 2b00 cmp r3, #0 8003a6a: d014 beq.n 8003a96 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8003a6c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8003a70: f003 0380 and.w r3, r3, #128 @ 0x80 8003a74: 2b00 cmp r3, #0 8003a76: d105 bne.n 8003a84 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8003a78: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8003a7c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8003a80: 2b00 cmp r3, #0 8003a82: d008 beq.n 8003a96 { if (huart->TxISR != NULL) 8003a84: 687b ldr r3, [r7, #4] 8003a86: 6f9b ldr r3, [r3, #120] @ 0x78 8003a88: 2b00 cmp r3, #0 8003a8a: d03a beq.n 8003b02 { huart->TxISR(huart); 8003a8c: 687b ldr r3, [r7, #4] 8003a8e: 6f9b ldr r3, [r3, #120] @ 0x78 8003a90: 6878 ldr r0, [r7, #4] 8003a92: 4798 blx r3 } return; 8003a94: e035 b.n 8003b02 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8003a96: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003a9a: f003 0340 and.w r3, r3, #64 @ 0x40 8003a9e: 2b00 cmp r3, #0 8003aa0: d009 beq.n 8003ab6 8003aa2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8003aa6: f003 0340 and.w r3, r3, #64 @ 0x40 8003aaa: 2b00 cmp r3, #0 8003aac: d003 beq.n 8003ab6 { UART_EndTransmit_IT(huart); 8003aae: 6878 ldr r0, [r7, #4] 8003ab0: f000 fe68 bl 8004784 return; 8003ab4: e026 b.n 8003b04 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8003ab6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003aba: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8003abe: 2b00 cmp r3, #0 8003ac0: d009 beq.n 8003ad6 8003ac2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8003ac6: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8003aca: 2b00 cmp r3, #0 8003acc: d003 beq.n 8003ad6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8003ace: 6878 ldr r0, [r7, #4] 8003ad0: f001 fbb8 bl 8005244 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8003ad4: e016 b.n 8003b04 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8003ad6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8003ada: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003ade: 2b00 cmp r3, #0 8003ae0: d010 beq.n 8003b04 8003ae2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8003ae6: 2b00 cmp r3, #0 8003ae8: da0c bge.n 8003b04 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8003aea: 6878 ldr r0, [r7, #4] 8003aec: f001 fba0 bl 8005230 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8003af0: e008 b.n 8003b04 return; 8003af2: bf00 nop 8003af4: e006 b.n 8003b04 return; 8003af6: bf00 nop 8003af8: e004 b.n 8003b04 return; 8003afa: bf00 nop 8003afc: e002 b.n 8003b04 return; 8003afe: bf00 nop 8003b00: e000 b.n 8003b04 return; 8003b02: bf00 nop } } 8003b04: 37e8 adds r7, #232 @ 0xe8 8003b06: 46bd mov sp, r7 8003b08: bd80 pop {r7, pc} 8003b0a: bf00 nop 08003b0c : * @brief Tx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8003b0c: b480 push {r7} 8003b0e: b083 sub sp, #12 8003b10: af00 add r7, sp, #0 8003b12: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_TxCpltCallback can be implemented in the user file. */ } 8003b14: bf00 nop 8003b16: 370c adds r7, #12 8003b18: 46bd mov sp, r7 8003b1a: f85d 7b04 ldr.w r7, [sp], #4 8003b1e: 4770 bx lr 08003b20 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8003b20: b480 push {r7} 8003b22: b083 sub sp, #12 8003b24: af00 add r7, sp, #0 8003b26: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8003b28: bf00 nop 8003b2a: 370c adds r7, #12 8003b2c: 46bd mov sp, r7 8003b2e: f85d 7b04 ldr.w r7, [sp], #4 8003b32: 4770 bx lr 08003b34 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8003b34: b480 push {r7} 8003b36: b083 sub sp, #12 8003b38: af00 add r7, sp, #0 8003b3a: 6078 str r0, [r7, #4] 8003b3c: 460b mov r3, r1 8003b3e: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 8003b40: bf00 nop 8003b42: 370c adds r7, #12 8003b44: 46bd mov sp, r7 8003b46: f85d 7b04 ldr.w r7, [sp], #4 8003b4a: 4770 bx lr 08003b4c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8003b4c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8003b50: b08c sub sp, #48 @ 0x30 8003b52: af00 add r7, sp, #0 8003b54: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8003b56: 2300 movs r3, #0 8003b58: f887 302a strb.w r3, [r7, #42] @ 0x2a * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8003b5c: 697b ldr r3, [r7, #20] 8003b5e: 689a ldr r2, [r3, #8] 8003b60: 697b ldr r3, [r7, #20] 8003b62: 691b ldr r3, [r3, #16] 8003b64: 431a orrs r2, r3 8003b66: 697b ldr r3, [r7, #20] 8003b68: 695b ldr r3, [r3, #20] 8003b6a: 431a orrs r2, r3 8003b6c: 697b ldr r3, [r7, #20] 8003b6e: 69db ldr r3, [r3, #28] 8003b70: 4313 orrs r3, r2 8003b72: 62fb str r3, [r7, #44] @ 0x2c MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8003b74: 697b ldr r3, [r7, #20] 8003b76: 681b ldr r3, [r3, #0] 8003b78: 681a ldr r2, [r3, #0] 8003b7a: 4bab ldr r3, [pc, #684] @ (8003e28 ) 8003b7c: 4013 ands r3, r2 8003b7e: 697a ldr r2, [r7, #20] 8003b80: 6812 ldr r2, [r2, #0] 8003b82: 6af9 ldr r1, [r7, #44] @ 0x2c 8003b84: 430b orrs r3, r1 8003b86: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8003b88: 697b ldr r3, [r7, #20] 8003b8a: 681b ldr r3, [r3, #0] 8003b8c: 685b ldr r3, [r3, #4] 8003b8e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8003b92: 697b ldr r3, [r7, #20] 8003b94: 68da ldr r2, [r3, #12] 8003b96: 697b ldr r3, [r7, #20] 8003b98: 681b ldr r3, [r3, #0] 8003b9a: 430a orrs r2, r1 8003b9c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8003b9e: 697b ldr r3, [r7, #20] 8003ba0: 699b ldr r3, [r3, #24] 8003ba2: 62fb str r3, [r7, #44] @ 0x2c if (!(UART_INSTANCE_LOWPOWER(huart))) 8003ba4: 697b ldr r3, [r7, #20] 8003ba6: 681b ldr r3, [r3, #0] 8003ba8: 4aa0 ldr r2, [pc, #640] @ (8003e2c ) 8003baa: 4293 cmp r3, r2 8003bac: d004 beq.n 8003bb8 { tmpreg |= huart->Init.OneBitSampling; 8003bae: 697b ldr r3, [r7, #20] 8003bb0: 6a1b ldr r3, [r3, #32] 8003bb2: 6afa ldr r2, [r7, #44] @ 0x2c 8003bb4: 4313 orrs r3, r2 8003bb6: 62fb str r3, [r7, #44] @ 0x2c } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8003bb8: 697b ldr r3, [r7, #20] 8003bba: 681b ldr r3, [r3, #0] 8003bbc: 689b ldr r3, [r3, #8] 8003bbe: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 8003bc2: f423 6330 bic.w r3, r3, #2816 @ 0xb00 8003bc6: 697a ldr r2, [r7, #20] 8003bc8: 6812 ldr r2, [r2, #0] 8003bca: 6af9 ldr r1, [r7, #44] @ 0x2c 8003bcc: 430b orrs r3, r1 8003bce: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8003bd0: 697b ldr r3, [r7, #20] 8003bd2: 681b ldr r3, [r3, #0] 8003bd4: 6adb ldr r3, [r3, #44] @ 0x2c 8003bd6: f023 010f bic.w r1, r3, #15 8003bda: 697b ldr r3, [r7, #20] 8003bdc: 6a5a ldr r2, [r3, #36] @ 0x24 8003bde: 697b ldr r3, [r7, #20] 8003be0: 681b ldr r3, [r3, #0] 8003be2: 430a orrs r2, r1 8003be4: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8003be6: 697b ldr r3, [r7, #20] 8003be8: 681b ldr r3, [r3, #0] 8003bea: 4a91 ldr r2, [pc, #580] @ (8003e30 ) 8003bec: 4293 cmp r3, r2 8003bee: d125 bne.n 8003c3c 8003bf0: 4b90 ldr r3, [pc, #576] @ (8003e34 ) 8003bf2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003bf6: f003 0303 and.w r3, r3, #3 8003bfa: 2b03 cmp r3, #3 8003bfc: d81a bhi.n 8003c34 8003bfe: a201 add r2, pc, #4 @ (adr r2, 8003c04 ) 8003c00: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003c04: 08003c15 .word 0x08003c15 8003c08: 08003c25 .word 0x08003c25 8003c0c: 08003c1d .word 0x08003c1d 8003c10: 08003c2d .word 0x08003c2d 8003c14: 2301 movs r3, #1 8003c16: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c1a: e0d6 b.n 8003dca 8003c1c: 2302 movs r3, #2 8003c1e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c22: e0d2 b.n 8003dca 8003c24: 2304 movs r3, #4 8003c26: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c2a: e0ce b.n 8003dca 8003c2c: 2308 movs r3, #8 8003c2e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c32: e0ca b.n 8003dca 8003c34: 2310 movs r3, #16 8003c36: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c3a: e0c6 b.n 8003dca 8003c3c: 697b ldr r3, [r7, #20] 8003c3e: 681b ldr r3, [r3, #0] 8003c40: 4a7d ldr r2, [pc, #500] @ (8003e38 ) 8003c42: 4293 cmp r3, r2 8003c44: d138 bne.n 8003cb8 8003c46: 4b7b ldr r3, [pc, #492] @ (8003e34 ) 8003c48: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003c4c: f003 030c and.w r3, r3, #12 8003c50: 2b0c cmp r3, #12 8003c52: d82d bhi.n 8003cb0 8003c54: a201 add r2, pc, #4 @ (adr r2, 8003c5c ) 8003c56: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003c5a: bf00 nop 8003c5c: 08003c91 .word 0x08003c91 8003c60: 08003cb1 .word 0x08003cb1 8003c64: 08003cb1 .word 0x08003cb1 8003c68: 08003cb1 .word 0x08003cb1 8003c6c: 08003ca1 .word 0x08003ca1 8003c70: 08003cb1 .word 0x08003cb1 8003c74: 08003cb1 .word 0x08003cb1 8003c78: 08003cb1 .word 0x08003cb1 8003c7c: 08003c99 .word 0x08003c99 8003c80: 08003cb1 .word 0x08003cb1 8003c84: 08003cb1 .word 0x08003cb1 8003c88: 08003cb1 .word 0x08003cb1 8003c8c: 08003ca9 .word 0x08003ca9 8003c90: 2300 movs r3, #0 8003c92: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c96: e098 b.n 8003dca 8003c98: 2302 movs r3, #2 8003c9a: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003c9e: e094 b.n 8003dca 8003ca0: 2304 movs r3, #4 8003ca2: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003ca6: e090 b.n 8003dca 8003ca8: 2308 movs r3, #8 8003caa: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003cae: e08c b.n 8003dca 8003cb0: 2310 movs r3, #16 8003cb2: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003cb6: e088 b.n 8003dca 8003cb8: 697b ldr r3, [r7, #20] 8003cba: 681b ldr r3, [r3, #0] 8003cbc: 4a5f ldr r2, [pc, #380] @ (8003e3c ) 8003cbe: 4293 cmp r3, r2 8003cc0: d125 bne.n 8003d0e 8003cc2: 4b5c ldr r3, [pc, #368] @ (8003e34 ) 8003cc4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003cc8: f003 0330 and.w r3, r3, #48 @ 0x30 8003ccc: 2b30 cmp r3, #48 @ 0x30 8003cce: d016 beq.n 8003cfe 8003cd0: 2b30 cmp r3, #48 @ 0x30 8003cd2: d818 bhi.n 8003d06 8003cd4: 2b20 cmp r3, #32 8003cd6: d00a beq.n 8003cee 8003cd8: 2b20 cmp r3, #32 8003cda: d814 bhi.n 8003d06 8003cdc: 2b00 cmp r3, #0 8003cde: d002 beq.n 8003ce6 8003ce0: 2b10 cmp r3, #16 8003ce2: d008 beq.n 8003cf6 8003ce4: e00f b.n 8003d06 8003ce6: 2300 movs r3, #0 8003ce8: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003cec: e06d b.n 8003dca 8003cee: 2302 movs r3, #2 8003cf0: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003cf4: e069 b.n 8003dca 8003cf6: 2304 movs r3, #4 8003cf8: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003cfc: e065 b.n 8003dca 8003cfe: 2308 movs r3, #8 8003d00: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d04: e061 b.n 8003dca 8003d06: 2310 movs r3, #16 8003d08: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d0c: e05d b.n 8003dca 8003d0e: 697b ldr r3, [r7, #20] 8003d10: 681b ldr r3, [r3, #0] 8003d12: 4a4b ldr r2, [pc, #300] @ (8003e40 ) 8003d14: 4293 cmp r3, r2 8003d16: d125 bne.n 8003d64 8003d18: 4b46 ldr r3, [pc, #280] @ (8003e34 ) 8003d1a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003d1e: f003 03c0 and.w r3, r3, #192 @ 0xc0 8003d22: 2bc0 cmp r3, #192 @ 0xc0 8003d24: d016 beq.n 8003d54 8003d26: 2bc0 cmp r3, #192 @ 0xc0 8003d28: d818 bhi.n 8003d5c 8003d2a: 2b80 cmp r3, #128 @ 0x80 8003d2c: d00a beq.n 8003d44 8003d2e: 2b80 cmp r3, #128 @ 0x80 8003d30: d814 bhi.n 8003d5c 8003d32: 2b00 cmp r3, #0 8003d34: d002 beq.n 8003d3c 8003d36: 2b40 cmp r3, #64 @ 0x40 8003d38: d008 beq.n 8003d4c 8003d3a: e00f b.n 8003d5c 8003d3c: 2300 movs r3, #0 8003d3e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d42: e042 b.n 8003dca 8003d44: 2302 movs r3, #2 8003d46: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d4a: e03e b.n 8003dca 8003d4c: 2304 movs r3, #4 8003d4e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d52: e03a b.n 8003dca 8003d54: 2308 movs r3, #8 8003d56: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d5a: e036 b.n 8003dca 8003d5c: 2310 movs r3, #16 8003d5e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003d62: e032 b.n 8003dca 8003d64: 697b ldr r3, [r7, #20] 8003d66: 681b ldr r3, [r3, #0] 8003d68: 4a30 ldr r2, [pc, #192] @ (8003e2c ) 8003d6a: 4293 cmp r3, r2 8003d6c: d12a bne.n 8003dc4 8003d6e: 4b31 ldr r3, [pc, #196] @ (8003e34 ) 8003d70: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003d74: f403 6340 and.w r3, r3, #3072 @ 0xc00 8003d78: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8003d7c: d01a beq.n 8003db4 8003d7e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8003d82: d81b bhi.n 8003dbc 8003d84: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003d88: d00c beq.n 8003da4 8003d8a: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8003d8e: d815 bhi.n 8003dbc 8003d90: 2b00 cmp r3, #0 8003d92: d003 beq.n 8003d9c 8003d94: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003d98: d008 beq.n 8003dac 8003d9a: e00f b.n 8003dbc 8003d9c: 2300 movs r3, #0 8003d9e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003da2: e012 b.n 8003dca 8003da4: 2302 movs r3, #2 8003da6: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003daa: e00e b.n 8003dca 8003dac: 2304 movs r3, #4 8003dae: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003db2: e00a b.n 8003dca 8003db4: 2308 movs r3, #8 8003db6: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003dba: e006 b.n 8003dca 8003dbc: 2310 movs r3, #16 8003dbe: f887 302b strb.w r3, [r7, #43] @ 0x2b 8003dc2: e002 b.n 8003dca 8003dc4: 2310 movs r3, #16 8003dc6: f887 302b strb.w r3, [r7, #43] @ 0x2b /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8003dca: 697b ldr r3, [r7, #20] 8003dcc: 681b ldr r3, [r3, #0] 8003dce: 4a17 ldr r2, [pc, #92] @ (8003e2c ) 8003dd0: 4293 cmp r3, r2 8003dd2: f040 80a8 bne.w 8003f26 { /* Retrieve frequency clock */ switch (clocksource) 8003dd6: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8003dda: 2b08 cmp r3, #8 8003ddc: d834 bhi.n 8003e48 8003dde: a201 add r2, pc, #4 @ (adr r2, 8003de4 ) 8003de0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003de4: 08003e09 .word 0x08003e09 8003de8: 08003e49 .word 0x08003e49 8003dec: 08003e11 .word 0x08003e11 8003df0: 08003e49 .word 0x08003e49 8003df4: 08003e17 .word 0x08003e17 8003df8: 08003e49 .word 0x08003e49 8003dfc: 08003e49 .word 0x08003e49 8003e00: 08003e49 .word 0x08003e49 8003e04: 08003e1f .word 0x08003e1f { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8003e08: f7fe fcba bl 8002780 8003e0c: 6278 str r0, [r7, #36] @ 0x24 break; 8003e0e: e021 b.n 8003e54 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8003e10: 4b0c ldr r3, [pc, #48] @ (8003e44 ) 8003e12: 627b str r3, [r7, #36] @ 0x24 break; 8003e14: e01e b.n 8003e54 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8003e16: f7fe fc45 bl 80026a4 8003e1a: 6278 str r0, [r7, #36] @ 0x24 break; 8003e1c: e01a b.n 8003e54 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8003e1e: f44f 4300 mov.w r3, #32768 @ 0x8000 8003e22: 627b str r3, [r7, #36] @ 0x24 break; 8003e24: e016 b.n 8003e54 8003e26: bf00 nop 8003e28: cfff69f3 .word 0xcfff69f3 8003e2c: 40008000 .word 0x40008000 8003e30: 40013800 .word 0x40013800 8003e34: 40021000 .word 0x40021000 8003e38: 40004400 .word 0x40004400 8003e3c: 40004800 .word 0x40004800 8003e40: 40004c00 .word 0x40004c00 8003e44: 00f42400 .word 0x00f42400 default: pclk = 0U; 8003e48: 2300 movs r3, #0 8003e4a: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 8003e4c: 2301 movs r3, #1 8003e4e: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 8003e52: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 8003e54: 6a7b ldr r3, [r7, #36] @ 0x24 8003e56: 2b00 cmp r3, #0 8003e58: f000 812a beq.w 80040b0 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8003e5c: 697b ldr r3, [r7, #20] 8003e5e: 6a5b ldr r3, [r3, #36] @ 0x24 8003e60: 4a9e ldr r2, [pc, #632] @ (80040dc ) 8003e62: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8003e66: 461a mov r2, r3 8003e68: 6a7b ldr r3, [r7, #36] @ 0x24 8003e6a: fbb3 f3f2 udiv r3, r3, r2 8003e6e: 61bb str r3, [r7, #24] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8003e70: 697b ldr r3, [r7, #20] 8003e72: 685a ldr r2, [r3, #4] 8003e74: 4613 mov r3, r2 8003e76: 005b lsls r3, r3, #1 8003e78: 4413 add r3, r2 8003e7a: 69ba ldr r2, [r7, #24] 8003e7c: 429a cmp r2, r3 8003e7e: d305 bcc.n 8003e8c (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8003e80: 697b ldr r3, [r7, #20] 8003e82: 685b ldr r3, [r3, #4] 8003e84: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8003e86: 69ba ldr r2, [r7, #24] 8003e88: 429a cmp r2, r3 8003e8a: d903 bls.n 8003e94 { ret = HAL_ERROR; 8003e8c: 2301 movs r3, #1 8003e8e: f887 302a strb.w r3, [r7, #42] @ 0x2a 8003e92: e10d b.n 80040b0 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8003e94: 6a7b ldr r3, [r7, #36] @ 0x24 8003e96: 2200 movs r2, #0 8003e98: 60bb str r3, [r7, #8] 8003e9a: 60fa str r2, [r7, #12] 8003e9c: 697b ldr r3, [r7, #20] 8003e9e: 6a5b ldr r3, [r3, #36] @ 0x24 8003ea0: 4a8e ldr r2, [pc, #568] @ (80040dc ) 8003ea2: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8003ea6: b29b uxth r3, r3 8003ea8: 2200 movs r2, #0 8003eaa: 603b str r3, [r7, #0] 8003eac: 607a str r2, [r7, #4] 8003eae: e9d7 2300 ldrd r2, r3, [r7] 8003eb2: e9d7 0102 ldrd r0, r1, [r7, #8] 8003eb6: f7fc f9af bl 8000218 <__aeabi_uldivmod> 8003eba: 4602 mov r2, r0 8003ebc: 460b mov r3, r1 8003ebe: 4610 mov r0, r2 8003ec0: 4619 mov r1, r3 8003ec2: f04f 0200 mov.w r2, #0 8003ec6: f04f 0300 mov.w r3, #0 8003eca: 020b lsls r3, r1, #8 8003ecc: ea43 6310 orr.w r3, r3, r0, lsr #24 8003ed0: 0202 lsls r2, r0, #8 8003ed2: 6979 ldr r1, [r7, #20] 8003ed4: 6849 ldr r1, [r1, #4] 8003ed6: 0849 lsrs r1, r1, #1 8003ed8: 2000 movs r0, #0 8003eda: 460c mov r4, r1 8003edc: 4605 mov r5, r0 8003ede: eb12 0804 adds.w r8, r2, r4 8003ee2: eb43 0905 adc.w r9, r3, r5 8003ee6: 697b ldr r3, [r7, #20] 8003ee8: 685b ldr r3, [r3, #4] 8003eea: 2200 movs r2, #0 8003eec: 469a mov sl, r3 8003eee: 4693 mov fp, r2 8003ef0: 4652 mov r2, sl 8003ef2: 465b mov r3, fp 8003ef4: 4640 mov r0, r8 8003ef6: 4649 mov r1, r9 8003ef8: f7fc f98e bl 8000218 <__aeabi_uldivmod> 8003efc: 4602 mov r2, r0 8003efe: 460b mov r3, r1 8003f00: 4613 mov r3, r2 8003f02: 623b str r3, [r7, #32] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8003f04: 6a3b ldr r3, [r7, #32] 8003f06: f5b3 7f40 cmp.w r3, #768 @ 0x300 8003f0a: d308 bcc.n 8003f1e 8003f0c: 6a3b ldr r3, [r7, #32] 8003f0e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003f12: d204 bcs.n 8003f1e { huart->Instance->BRR = usartdiv; 8003f14: 697b ldr r3, [r7, #20] 8003f16: 681b ldr r3, [r3, #0] 8003f18: 6a3a ldr r2, [r7, #32] 8003f1a: 60da str r2, [r3, #12] 8003f1c: e0c8 b.n 80040b0 } else { ret = HAL_ERROR; 8003f1e: 2301 movs r3, #1 8003f20: f887 302a strb.w r3, [r7, #42] @ 0x2a 8003f24: e0c4 b.n 80040b0 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8003f26: 697b ldr r3, [r7, #20] 8003f28: 69db ldr r3, [r3, #28] 8003f2a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8003f2e: d167 bne.n 8004000 { switch (clocksource) 8003f30: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8003f34: 2b08 cmp r3, #8 8003f36: d828 bhi.n 8003f8a 8003f38: a201 add r2, pc, #4 @ (adr r2, 8003f40 ) 8003f3a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003f3e: bf00 nop 8003f40: 08003f65 .word 0x08003f65 8003f44: 08003f6d .word 0x08003f6d 8003f48: 08003f75 .word 0x08003f75 8003f4c: 08003f8b .word 0x08003f8b 8003f50: 08003f7b .word 0x08003f7b 8003f54: 08003f8b .word 0x08003f8b 8003f58: 08003f8b .word 0x08003f8b 8003f5c: 08003f8b .word 0x08003f8b 8003f60: 08003f83 .word 0x08003f83 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8003f64: f7fe fc0c bl 8002780 8003f68: 6278 str r0, [r7, #36] @ 0x24 break; 8003f6a: e014 b.n 8003f96 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8003f6c: f7fe fc1e bl 80027ac 8003f70: 6278 str r0, [r7, #36] @ 0x24 break; 8003f72: e010 b.n 8003f96 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8003f74: 4b5a ldr r3, [pc, #360] @ (80040e0 ) 8003f76: 627b str r3, [r7, #36] @ 0x24 break; 8003f78: e00d b.n 8003f96 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8003f7a: f7fe fb93 bl 80026a4 8003f7e: 6278 str r0, [r7, #36] @ 0x24 break; 8003f80: e009 b.n 8003f96 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8003f82: f44f 4300 mov.w r3, #32768 @ 0x8000 8003f86: 627b str r3, [r7, #36] @ 0x24 break; 8003f88: e005 b.n 8003f96 default: pclk = 0U; 8003f8a: 2300 movs r3, #0 8003f8c: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 8003f8e: 2301 movs r3, #1 8003f90: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 8003f94: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8003f96: 6a7b ldr r3, [r7, #36] @ 0x24 8003f98: 2b00 cmp r3, #0 8003f9a: f000 8089 beq.w 80040b0 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8003f9e: 697b ldr r3, [r7, #20] 8003fa0: 6a5b ldr r3, [r3, #36] @ 0x24 8003fa2: 4a4e ldr r2, [pc, #312] @ (80040dc ) 8003fa4: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8003fa8: 461a mov r2, r3 8003faa: 6a7b ldr r3, [r7, #36] @ 0x24 8003fac: fbb3 f3f2 udiv r3, r3, r2 8003fb0: 005a lsls r2, r3, #1 8003fb2: 697b ldr r3, [r7, #20] 8003fb4: 685b ldr r3, [r3, #4] 8003fb6: 085b lsrs r3, r3, #1 8003fb8: 441a add r2, r3 8003fba: 697b ldr r3, [r7, #20] 8003fbc: 685b ldr r3, [r3, #4] 8003fbe: fbb2 f3f3 udiv r3, r2, r3 8003fc2: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8003fc4: 6a3b ldr r3, [r7, #32] 8003fc6: 2b0f cmp r3, #15 8003fc8: d916 bls.n 8003ff8 8003fca: 6a3b ldr r3, [r7, #32] 8003fcc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8003fd0: d212 bcs.n 8003ff8 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8003fd2: 6a3b ldr r3, [r7, #32] 8003fd4: b29b uxth r3, r3 8003fd6: f023 030f bic.w r3, r3, #15 8003fda: 83fb strh r3, [r7, #30] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8003fdc: 6a3b ldr r3, [r7, #32] 8003fde: 085b lsrs r3, r3, #1 8003fe0: b29b uxth r3, r3 8003fe2: f003 0307 and.w r3, r3, #7 8003fe6: b29a uxth r2, r3 8003fe8: 8bfb ldrh r3, [r7, #30] 8003fea: 4313 orrs r3, r2 8003fec: 83fb strh r3, [r7, #30] huart->Instance->BRR = brrtemp; 8003fee: 697b ldr r3, [r7, #20] 8003ff0: 681b ldr r3, [r3, #0] 8003ff2: 8bfa ldrh r2, [r7, #30] 8003ff4: 60da str r2, [r3, #12] 8003ff6: e05b b.n 80040b0 } else { ret = HAL_ERROR; 8003ff8: 2301 movs r3, #1 8003ffa: f887 302a strb.w r3, [r7, #42] @ 0x2a 8003ffe: e057 b.n 80040b0 } } } else { switch (clocksource) 8004000: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8004004: 2b08 cmp r3, #8 8004006: d828 bhi.n 800405a 8004008: a201 add r2, pc, #4 @ (adr r2, 8004010 ) 800400a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800400e: bf00 nop 8004010: 08004035 .word 0x08004035 8004014: 0800403d .word 0x0800403d 8004018: 08004045 .word 0x08004045 800401c: 0800405b .word 0x0800405b 8004020: 0800404b .word 0x0800404b 8004024: 0800405b .word 0x0800405b 8004028: 0800405b .word 0x0800405b 800402c: 0800405b .word 0x0800405b 8004030: 08004053 .word 0x08004053 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8004034: f7fe fba4 bl 8002780 8004038: 6278 str r0, [r7, #36] @ 0x24 break; 800403a: e014 b.n 8004066 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 800403c: f7fe fbb6 bl 80027ac 8004040: 6278 str r0, [r7, #36] @ 0x24 break; 8004042: e010 b.n 8004066 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8004044: 4b26 ldr r3, [pc, #152] @ (80040e0 ) 8004046: 627b str r3, [r7, #36] @ 0x24 break; 8004048: e00d b.n 8004066 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 800404a: f7fe fb2b bl 80026a4 800404e: 6278 str r0, [r7, #36] @ 0x24 break; 8004050: e009 b.n 8004066 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8004052: f44f 4300 mov.w r3, #32768 @ 0x8000 8004056: 627b str r3, [r7, #36] @ 0x24 break; 8004058: e005 b.n 8004066 default: pclk = 0U; 800405a: 2300 movs r3, #0 800405c: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 800405e: 2301 movs r3, #1 8004060: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 8004064: bf00 nop } if (pclk != 0U) 8004066: 6a7b ldr r3, [r7, #36] @ 0x24 8004068: 2b00 cmp r3, #0 800406a: d021 beq.n 80040b0 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800406c: 697b ldr r3, [r7, #20] 800406e: 6a5b ldr r3, [r3, #36] @ 0x24 8004070: 4a1a ldr r2, [pc, #104] @ (80040dc ) 8004072: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8004076: 461a mov r2, r3 8004078: 6a7b ldr r3, [r7, #36] @ 0x24 800407a: fbb3 f2f2 udiv r2, r3, r2 800407e: 697b ldr r3, [r7, #20] 8004080: 685b ldr r3, [r3, #4] 8004082: 085b lsrs r3, r3, #1 8004084: 441a add r2, r3 8004086: 697b ldr r3, [r7, #20] 8004088: 685b ldr r3, [r3, #4] 800408a: fbb2 f3f3 udiv r3, r2, r3 800408e: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8004090: 6a3b ldr r3, [r7, #32] 8004092: 2b0f cmp r3, #15 8004094: d909 bls.n 80040aa 8004096: 6a3b ldr r3, [r7, #32] 8004098: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800409c: d205 bcs.n 80040aa { huart->Instance->BRR = (uint16_t)usartdiv; 800409e: 6a3b ldr r3, [r7, #32] 80040a0: b29a uxth r2, r3 80040a2: 697b ldr r3, [r7, #20] 80040a4: 681b ldr r3, [r3, #0] 80040a6: 60da str r2, [r3, #12] 80040a8: e002 b.n 80040b0 } else { ret = HAL_ERROR; 80040aa: 2301 movs r3, #1 80040ac: f887 302a strb.w r3, [r7, #42] @ 0x2a } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 80040b0: 697b ldr r3, [r7, #20] 80040b2: 2201 movs r2, #1 80040b4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 80040b8: 697b ldr r3, [r7, #20] 80040ba: 2201 movs r2, #1 80040bc: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 80040c0: 697b ldr r3, [r7, #20] 80040c2: 2200 movs r2, #0 80040c4: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 80040c6: 697b ldr r3, [r7, #20] 80040c8: 2200 movs r2, #0 80040ca: 679a str r2, [r3, #120] @ 0x78 return ret; 80040cc: f897 302a ldrb.w r3, [r7, #42] @ 0x2a } 80040d0: 4618 mov r0, r3 80040d2: 3730 adds r7, #48 @ 0x30 80040d4: 46bd mov sp, r7 80040d6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80040da: bf00 nop 80040dc: 080057b0 .word 0x080057b0 80040e0: 00f42400 .word 0x00f42400 080040e4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 80040e4: b480 push {r7} 80040e6: b083 sub sp, #12 80040e8: af00 add r7, sp, #0 80040ea: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 80040ec: 687b ldr r3, [r7, #4] 80040ee: 6a9b ldr r3, [r3, #40] @ 0x28 80040f0: f003 0308 and.w r3, r3, #8 80040f4: 2b00 cmp r3, #0 80040f6: d00a beq.n 800410e { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 80040f8: 687b ldr r3, [r7, #4] 80040fa: 681b ldr r3, [r3, #0] 80040fc: 685b ldr r3, [r3, #4] 80040fe: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8004102: 687b ldr r3, [r7, #4] 8004104: 6b9a ldr r2, [r3, #56] @ 0x38 8004106: 687b ldr r3, [r7, #4] 8004108: 681b ldr r3, [r3, #0] 800410a: 430a orrs r2, r1 800410c: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800410e: 687b ldr r3, [r7, #4] 8004110: 6a9b ldr r3, [r3, #40] @ 0x28 8004112: f003 0301 and.w r3, r3, #1 8004116: 2b00 cmp r3, #0 8004118: d00a beq.n 8004130 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 800411a: 687b ldr r3, [r7, #4] 800411c: 681b ldr r3, [r3, #0] 800411e: 685b ldr r3, [r3, #4] 8004120: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8004124: 687b ldr r3, [r7, #4] 8004126: 6ada ldr r2, [r3, #44] @ 0x2c 8004128: 687b ldr r3, [r7, #4] 800412a: 681b ldr r3, [r3, #0] 800412c: 430a orrs r2, r1 800412e: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8004130: 687b ldr r3, [r7, #4] 8004132: 6a9b ldr r3, [r3, #40] @ 0x28 8004134: f003 0302 and.w r3, r3, #2 8004138: 2b00 cmp r3, #0 800413a: d00a beq.n 8004152 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 800413c: 687b ldr r3, [r7, #4] 800413e: 681b ldr r3, [r3, #0] 8004140: 685b ldr r3, [r3, #4] 8004142: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8004146: 687b ldr r3, [r7, #4] 8004148: 6b1a ldr r2, [r3, #48] @ 0x30 800414a: 687b ldr r3, [r7, #4] 800414c: 681b ldr r3, [r3, #0] 800414e: 430a orrs r2, r1 8004150: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8004152: 687b ldr r3, [r7, #4] 8004154: 6a9b ldr r3, [r3, #40] @ 0x28 8004156: f003 0304 and.w r3, r3, #4 800415a: 2b00 cmp r3, #0 800415c: d00a beq.n 8004174 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 800415e: 687b ldr r3, [r7, #4] 8004160: 681b ldr r3, [r3, #0] 8004162: 685b ldr r3, [r3, #4] 8004164: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8004168: 687b ldr r3, [r7, #4] 800416a: 6b5a ldr r2, [r3, #52] @ 0x34 800416c: 687b ldr r3, [r7, #4] 800416e: 681b ldr r3, [r3, #0] 8004170: 430a orrs r2, r1 8004172: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8004174: 687b ldr r3, [r7, #4] 8004176: 6a9b ldr r3, [r3, #40] @ 0x28 8004178: f003 0310 and.w r3, r3, #16 800417c: 2b00 cmp r3, #0 800417e: d00a beq.n 8004196 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8004180: 687b ldr r3, [r7, #4] 8004182: 681b ldr r3, [r3, #0] 8004184: 689b ldr r3, [r3, #8] 8004186: f423 5180 bic.w r1, r3, #4096 @ 0x1000 800418a: 687b ldr r3, [r7, #4] 800418c: 6bda ldr r2, [r3, #60] @ 0x3c 800418e: 687b ldr r3, [r7, #4] 8004190: 681b ldr r3, [r3, #0] 8004192: 430a orrs r2, r1 8004194: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8004196: 687b ldr r3, [r7, #4] 8004198: 6a9b ldr r3, [r3, #40] @ 0x28 800419a: f003 0320 and.w r3, r3, #32 800419e: 2b00 cmp r3, #0 80041a0: d00a beq.n 80041b8 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 80041a2: 687b ldr r3, [r7, #4] 80041a4: 681b ldr r3, [r3, #0] 80041a6: 689b ldr r3, [r3, #8] 80041a8: f423 5100 bic.w r1, r3, #8192 @ 0x2000 80041ac: 687b ldr r3, [r7, #4] 80041ae: 6c1a ldr r2, [r3, #64] @ 0x40 80041b0: 687b ldr r3, [r7, #4] 80041b2: 681b ldr r3, [r3, #0] 80041b4: 430a orrs r2, r1 80041b6: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 80041b8: 687b ldr r3, [r7, #4] 80041ba: 6a9b ldr r3, [r3, #40] @ 0x28 80041bc: f003 0340 and.w r3, r3, #64 @ 0x40 80041c0: 2b00 cmp r3, #0 80041c2: d01a beq.n 80041fa { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 80041c4: 687b ldr r3, [r7, #4] 80041c6: 681b ldr r3, [r3, #0] 80041c8: 685b ldr r3, [r3, #4] 80041ca: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 80041ce: 687b ldr r3, [r7, #4] 80041d0: 6c5a ldr r2, [r3, #68] @ 0x44 80041d2: 687b ldr r3, [r7, #4] 80041d4: 681b ldr r3, [r3, #0] 80041d6: 430a orrs r2, r1 80041d8: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 80041da: 687b ldr r3, [r7, #4] 80041dc: 6c5b ldr r3, [r3, #68] @ 0x44 80041de: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80041e2: d10a bne.n 80041fa { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 80041e4: 687b ldr r3, [r7, #4] 80041e6: 681b ldr r3, [r3, #0] 80041e8: 685b ldr r3, [r3, #4] 80041ea: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 80041ee: 687b ldr r3, [r7, #4] 80041f0: 6c9a ldr r2, [r3, #72] @ 0x48 80041f2: 687b ldr r3, [r7, #4] 80041f4: 681b ldr r3, [r3, #0] 80041f6: 430a orrs r2, r1 80041f8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 80041fa: 687b ldr r3, [r7, #4] 80041fc: 6a9b ldr r3, [r3, #40] @ 0x28 80041fe: f003 0380 and.w r3, r3, #128 @ 0x80 8004202: 2b00 cmp r3, #0 8004204: d00a beq.n 800421c { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8004206: 687b ldr r3, [r7, #4] 8004208: 681b ldr r3, [r3, #0] 800420a: 685b ldr r3, [r3, #4] 800420c: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8004210: 687b ldr r3, [r7, #4] 8004212: 6cda ldr r2, [r3, #76] @ 0x4c 8004214: 687b ldr r3, [r7, #4] 8004216: 681b ldr r3, [r3, #0] 8004218: 430a orrs r2, r1 800421a: 605a str r2, [r3, #4] } } 800421c: bf00 nop 800421e: 370c adds r7, #12 8004220: 46bd mov sp, r7 8004222: f85d 7b04 ldr.w r7, [sp], #4 8004226: 4770 bx lr 08004228 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8004228: b580 push {r7, lr} 800422a: b098 sub sp, #96 @ 0x60 800422c: af02 add r7, sp, #8 800422e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004230: 687b ldr r3, [r7, #4] 8004232: 2200 movs r2, #0 8004234: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8004238: f7fd f9ae bl 8001598 800423c: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800423e: 687b ldr r3, [r7, #4] 8004240: 681b ldr r3, [r3, #0] 8004242: 681b ldr r3, [r3, #0] 8004244: f003 0308 and.w r3, r3, #8 8004248: 2b08 cmp r3, #8 800424a: d12f bne.n 80042ac { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800424c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8004250: 9300 str r3, [sp, #0] 8004252: 6d7b ldr r3, [r7, #84] @ 0x54 8004254: 2200 movs r2, #0 8004256: f44f 1100 mov.w r1, #2097152 @ 0x200000 800425a: 6878 ldr r0, [r7, #4] 800425c: f000 f88e bl 800437c 8004260: 4603 mov r3, r0 8004262: 2b00 cmp r3, #0 8004264: d022 beq.n 80042ac { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8004266: 687b ldr r3, [r7, #4] 8004268: 681b ldr r3, [r3, #0] 800426a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800426c: 6bbb ldr r3, [r7, #56] @ 0x38 800426e: e853 3f00 ldrex r3, [r3] 8004272: 637b str r3, [r7, #52] @ 0x34 return(result); 8004274: 6b7b ldr r3, [r7, #52] @ 0x34 8004276: f023 0380 bic.w r3, r3, #128 @ 0x80 800427a: 653b str r3, [r7, #80] @ 0x50 800427c: 687b ldr r3, [r7, #4] 800427e: 681b ldr r3, [r3, #0] 8004280: 461a mov r2, r3 8004282: 6d3b ldr r3, [r7, #80] @ 0x50 8004284: 647b str r3, [r7, #68] @ 0x44 8004286: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004288: 6c39 ldr r1, [r7, #64] @ 0x40 800428a: 6c7a ldr r2, [r7, #68] @ 0x44 800428c: e841 2300 strex r3, r2, [r1] 8004290: 63fb str r3, [r7, #60] @ 0x3c return(result); 8004292: 6bfb ldr r3, [r7, #60] @ 0x3c 8004294: 2b00 cmp r3, #0 8004296: d1e6 bne.n 8004266 huart->gState = HAL_UART_STATE_READY; 8004298: 687b ldr r3, [r7, #4] 800429a: 2220 movs r2, #32 800429c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 80042a0: 687b ldr r3, [r7, #4] 80042a2: 2200 movs r2, #0 80042a4: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 80042a8: 2303 movs r3, #3 80042aa: e063 b.n 8004374 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 80042ac: 687b ldr r3, [r7, #4] 80042ae: 681b ldr r3, [r3, #0] 80042b0: 681b ldr r3, [r3, #0] 80042b2: f003 0304 and.w r3, r3, #4 80042b6: 2b04 cmp r3, #4 80042b8: d149 bne.n 800434e { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80042ba: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80042be: 9300 str r3, [sp, #0] 80042c0: 6d7b ldr r3, [r7, #84] @ 0x54 80042c2: 2200 movs r2, #0 80042c4: f44f 0180 mov.w r1, #4194304 @ 0x400000 80042c8: 6878 ldr r0, [r7, #4] 80042ca: f000 f857 bl 800437c 80042ce: 4603 mov r3, r0 80042d0: 2b00 cmp r3, #0 80042d2: d03c beq.n 800434e { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80042d4: 687b ldr r3, [r7, #4] 80042d6: 681b ldr r3, [r3, #0] 80042d8: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80042da: 6a7b ldr r3, [r7, #36] @ 0x24 80042dc: e853 3f00 ldrex r3, [r3] 80042e0: 623b str r3, [r7, #32] return(result); 80042e2: 6a3b ldr r3, [r7, #32] 80042e4: f423 7390 bic.w r3, r3, #288 @ 0x120 80042e8: 64fb str r3, [r7, #76] @ 0x4c 80042ea: 687b ldr r3, [r7, #4] 80042ec: 681b ldr r3, [r3, #0] 80042ee: 461a mov r2, r3 80042f0: 6cfb ldr r3, [r7, #76] @ 0x4c 80042f2: 633b str r3, [r7, #48] @ 0x30 80042f4: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80042f6: 6af9 ldr r1, [r7, #44] @ 0x2c 80042f8: 6b3a ldr r2, [r7, #48] @ 0x30 80042fa: e841 2300 strex r3, r2, [r1] 80042fe: 62bb str r3, [r7, #40] @ 0x28 return(result); 8004300: 6abb ldr r3, [r7, #40] @ 0x28 8004302: 2b00 cmp r3, #0 8004304: d1e6 bne.n 80042d4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004306: 687b ldr r3, [r7, #4] 8004308: 681b ldr r3, [r3, #0] 800430a: 3308 adds r3, #8 800430c: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800430e: 693b ldr r3, [r7, #16] 8004310: e853 3f00 ldrex r3, [r3] 8004314: 60fb str r3, [r7, #12] return(result); 8004316: 68fb ldr r3, [r7, #12] 8004318: f023 0301 bic.w r3, r3, #1 800431c: 64bb str r3, [r7, #72] @ 0x48 800431e: 687b ldr r3, [r7, #4] 8004320: 681b ldr r3, [r3, #0] 8004322: 3308 adds r3, #8 8004324: 6cba ldr r2, [r7, #72] @ 0x48 8004326: 61fa str r2, [r7, #28] 8004328: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800432a: 69b9 ldr r1, [r7, #24] 800432c: 69fa ldr r2, [r7, #28] 800432e: e841 2300 strex r3, r2, [r1] 8004332: 617b str r3, [r7, #20] return(result); 8004334: 697b ldr r3, [r7, #20] 8004336: 2b00 cmp r3, #0 8004338: d1e5 bne.n 8004306 huart->RxState = HAL_UART_STATE_READY; 800433a: 687b ldr r3, [r7, #4] 800433c: 2220 movs r2, #32 800433e: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8004342: 687b ldr r3, [r7, #4] 8004344: 2200 movs r2, #0 8004346: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 800434a: 2303 movs r3, #3 800434c: e012 b.n 8004374 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 800434e: 687b ldr r3, [r7, #4] 8004350: 2220 movs r2, #32 8004352: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8004356: 687b ldr r3, [r7, #4] 8004358: 2220 movs r2, #32 800435a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800435e: 687b ldr r3, [r7, #4] 8004360: 2200 movs r2, #0 8004362: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8004364: 687b ldr r3, [r7, #4] 8004366: 2200 movs r2, #0 8004368: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 800436a: 687b ldr r3, [r7, #4] 800436c: 2200 movs r2, #0 800436e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8004372: 2300 movs r3, #0 } 8004374: 4618 mov r0, r3 8004376: 3758 adds r7, #88 @ 0x58 8004378: 46bd mov sp, r7 800437a: bd80 pop {r7, pc} 0800437c : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 800437c: b580 push {r7, lr} 800437e: b084 sub sp, #16 8004380: af00 add r7, sp, #0 8004382: 60f8 str r0, [r7, #12] 8004384: 60b9 str r1, [r7, #8] 8004386: 603b str r3, [r7, #0] 8004388: 4613 mov r3, r2 800438a: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800438c: e04f b.n 800442e { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 800438e: 69bb ldr r3, [r7, #24] 8004390: f1b3 3fff cmp.w r3, #4294967295 8004394: d04b beq.n 800442e { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004396: f7fd f8ff bl 8001598 800439a: 4602 mov r2, r0 800439c: 683b ldr r3, [r7, #0] 800439e: 1ad3 subs r3, r2, r3 80043a0: 69ba ldr r2, [r7, #24] 80043a2: 429a cmp r2, r3 80043a4: d302 bcc.n 80043ac 80043a6: 69bb ldr r3, [r7, #24] 80043a8: 2b00 cmp r3, #0 80043aa: d101 bne.n 80043b0 { return HAL_TIMEOUT; 80043ac: 2303 movs r3, #3 80043ae: e04e b.n 800444e } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 80043b0: 68fb ldr r3, [r7, #12] 80043b2: 681b ldr r3, [r3, #0] 80043b4: 681b ldr r3, [r3, #0] 80043b6: f003 0304 and.w r3, r3, #4 80043ba: 2b00 cmp r3, #0 80043bc: d037 beq.n 800442e 80043be: 68bb ldr r3, [r7, #8] 80043c0: 2b80 cmp r3, #128 @ 0x80 80043c2: d034 beq.n 800442e 80043c4: 68bb ldr r3, [r7, #8] 80043c6: 2b40 cmp r3, #64 @ 0x40 80043c8: d031 beq.n 800442e { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 80043ca: 68fb ldr r3, [r7, #12] 80043cc: 681b ldr r3, [r3, #0] 80043ce: 69db ldr r3, [r3, #28] 80043d0: f003 0308 and.w r3, r3, #8 80043d4: 2b08 cmp r3, #8 80043d6: d110 bne.n 80043fa { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80043d8: 68fb ldr r3, [r7, #12] 80043da: 681b ldr r3, [r3, #0] 80043dc: 2208 movs r2, #8 80043de: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80043e0: 68f8 ldr r0, [r7, #12] 80043e2: f000 f95b bl 800469c huart->ErrorCode = HAL_UART_ERROR_ORE; 80043e6: 68fb ldr r3, [r7, #12] 80043e8: 2208 movs r2, #8 80043ea: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 80043ee: 68fb ldr r3, [r7, #12] 80043f0: 2200 movs r2, #0 80043f2: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 80043f6: 2301 movs r3, #1 80043f8: e029 b.n 800444e } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 80043fa: 68fb ldr r3, [r7, #12] 80043fc: 681b ldr r3, [r3, #0] 80043fe: 69db ldr r3, [r3, #28] 8004400: f403 6300 and.w r3, r3, #2048 @ 0x800 8004404: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8004408: d111 bne.n 800442e { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800440a: 68fb ldr r3, [r7, #12] 800440c: 681b ldr r3, [r3, #0] 800440e: f44f 6200 mov.w r2, #2048 @ 0x800 8004412: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8004414: 68f8 ldr r0, [r7, #12] 8004416: f000 f941 bl 800469c huart->ErrorCode = HAL_UART_ERROR_RTO; 800441a: 68fb ldr r3, [r7, #12] 800441c: 2220 movs r2, #32 800441e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8004422: 68fb ldr r3, [r7, #12] 8004424: 2200 movs r2, #0 8004426: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 800442a: 2303 movs r3, #3 800442c: e00f b.n 800444e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800442e: 68fb ldr r3, [r7, #12] 8004430: 681b ldr r3, [r3, #0] 8004432: 69da ldr r2, [r3, #28] 8004434: 68bb ldr r3, [r7, #8] 8004436: 4013 ands r3, r2 8004438: 68ba ldr r2, [r7, #8] 800443a: 429a cmp r2, r3 800443c: bf0c ite eq 800443e: 2301 moveq r3, #1 8004440: 2300 movne r3, #0 8004442: b2db uxtb r3, r3 8004444: 461a mov r2, r3 8004446: 79fb ldrb r3, [r7, #7] 8004448: 429a cmp r2, r3 800444a: d0a0 beq.n 800438e } } } } return HAL_OK; 800444c: 2300 movs r3, #0 } 800444e: 4618 mov r0, r3 8004450: 3710 adds r7, #16 8004452: 46bd mov sp, r7 8004454: bd80 pop {r7, pc} ... 08004458 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8004458: b480 push {r7} 800445a: b0a3 sub sp, #140 @ 0x8c 800445c: af00 add r7, sp, #0 800445e: 60f8 str r0, [r7, #12] 8004460: 60b9 str r1, [r7, #8] 8004462: 4613 mov r3, r2 8004464: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8004466: 68fb ldr r3, [r7, #12] 8004468: 68ba ldr r2, [r7, #8] 800446a: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 800446c: 68fb ldr r3, [r7, #12] 800446e: 88fa ldrh r2, [r7, #6] 8004470: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8004474: 68fb ldr r3, [r7, #12] 8004476: 88fa ldrh r2, [r7, #6] 8004478: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 800447c: 68fb ldr r3, [r7, #12] 800447e: 2200 movs r2, #0 8004480: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8004482: 68fb ldr r3, [r7, #12] 8004484: 689b ldr r3, [r3, #8] 8004486: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800448a: d10e bne.n 80044aa 800448c: 68fb ldr r3, [r7, #12] 800448e: 691b ldr r3, [r3, #16] 8004490: 2b00 cmp r3, #0 8004492: d105 bne.n 80044a0 8004494: 68fb ldr r3, [r7, #12] 8004496: f240 12ff movw r2, #511 @ 0x1ff 800449a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800449e: e02d b.n 80044fc 80044a0: 68fb ldr r3, [r7, #12] 80044a2: 22ff movs r2, #255 @ 0xff 80044a4: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80044a8: e028 b.n 80044fc 80044aa: 68fb ldr r3, [r7, #12] 80044ac: 689b ldr r3, [r3, #8] 80044ae: 2b00 cmp r3, #0 80044b0: d10d bne.n 80044ce 80044b2: 68fb ldr r3, [r7, #12] 80044b4: 691b ldr r3, [r3, #16] 80044b6: 2b00 cmp r3, #0 80044b8: d104 bne.n 80044c4 80044ba: 68fb ldr r3, [r7, #12] 80044bc: 22ff movs r2, #255 @ 0xff 80044be: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80044c2: e01b b.n 80044fc 80044c4: 68fb ldr r3, [r7, #12] 80044c6: 227f movs r2, #127 @ 0x7f 80044c8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80044cc: e016 b.n 80044fc 80044ce: 68fb ldr r3, [r7, #12] 80044d0: 689b ldr r3, [r3, #8] 80044d2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80044d6: d10d bne.n 80044f4 80044d8: 68fb ldr r3, [r7, #12] 80044da: 691b ldr r3, [r3, #16] 80044dc: 2b00 cmp r3, #0 80044de: d104 bne.n 80044ea 80044e0: 68fb ldr r3, [r7, #12] 80044e2: 227f movs r2, #127 @ 0x7f 80044e4: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80044e8: e008 b.n 80044fc 80044ea: 68fb ldr r3, [r7, #12] 80044ec: 223f movs r2, #63 @ 0x3f 80044ee: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80044f2: e003 b.n 80044fc 80044f4: 68fb ldr r3, [r7, #12] 80044f6: 2200 movs r2, #0 80044f8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 80044fc: 68fb ldr r3, [r7, #12] 80044fe: 2200 movs r2, #0 8004500: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8004504: 68fb ldr r3, [r7, #12] 8004506: 2222 movs r2, #34 @ 0x22 8004508: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800450c: 68fb ldr r3, [r7, #12] 800450e: 681b ldr r3, [r3, #0] 8004510: 3308 adds r3, #8 8004512: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004514: 6e7b ldr r3, [r7, #100] @ 0x64 8004516: e853 3f00 ldrex r3, [r3] 800451a: 663b str r3, [r7, #96] @ 0x60 return(result); 800451c: 6e3b ldr r3, [r7, #96] @ 0x60 800451e: f043 0301 orr.w r3, r3, #1 8004522: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8004526: 68fb ldr r3, [r7, #12] 8004528: 681b ldr r3, [r3, #0] 800452a: 3308 adds r3, #8 800452c: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8004530: 673a str r2, [r7, #112] @ 0x70 8004532: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004534: 6ef9 ldr r1, [r7, #108] @ 0x6c 8004536: 6f3a ldr r2, [r7, #112] @ 0x70 8004538: e841 2300 strex r3, r2, [r1] 800453c: 66bb str r3, [r7, #104] @ 0x68 return(result); 800453e: 6ebb ldr r3, [r7, #104] @ 0x68 8004540: 2b00 cmp r3, #0 8004542: d1e3 bne.n 800450c /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8004544: 68fb ldr r3, [r7, #12] 8004546: 6e5b ldr r3, [r3, #100] @ 0x64 8004548: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800454c: d14f bne.n 80045ee 800454e: 68fb ldr r3, [r7, #12] 8004550: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8004554: 88fa ldrh r2, [r7, #6] 8004556: 429a cmp r2, r3 8004558: d349 bcc.n 80045ee { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800455a: 68fb ldr r3, [r7, #12] 800455c: 689b ldr r3, [r3, #8] 800455e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004562: d107 bne.n 8004574 8004564: 68fb ldr r3, [r7, #12] 8004566: 691b ldr r3, [r3, #16] 8004568: 2b00 cmp r3, #0 800456a: d103 bne.n 8004574 { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 800456c: 68fb ldr r3, [r7, #12] 800456e: 4a47 ldr r2, [pc, #284] @ (800468c ) 8004570: 675a str r2, [r3, #116] @ 0x74 8004572: e002 b.n 800457a } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8004574: 68fb ldr r3, [r7, #12] 8004576: 4a46 ldr r2, [pc, #280] @ (8004690 ) 8004578: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 800457a: 68fb ldr r3, [r7, #12] 800457c: 691b ldr r3, [r3, #16] 800457e: 2b00 cmp r3, #0 8004580: d01a beq.n 80045b8 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8004582: 68fb ldr r3, [r7, #12] 8004584: 681b ldr r3, [r3, #0] 8004586: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004588: 6d3b ldr r3, [r7, #80] @ 0x50 800458a: e853 3f00 ldrex r3, [r3] 800458e: 64fb str r3, [r7, #76] @ 0x4c return(result); 8004590: 6cfb ldr r3, [r7, #76] @ 0x4c 8004592: f443 7380 orr.w r3, r3, #256 @ 0x100 8004596: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800459a: 68fb ldr r3, [r7, #12] 800459c: 681b ldr r3, [r3, #0] 800459e: 461a mov r2, r3 80045a0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80045a4: 65fb str r3, [r7, #92] @ 0x5c 80045a6: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80045a8: 6db9 ldr r1, [r7, #88] @ 0x58 80045aa: 6dfa ldr r2, [r7, #92] @ 0x5c 80045ac: e841 2300 strex r3, r2, [r1] 80045b0: 657b str r3, [r7, #84] @ 0x54 return(result); 80045b2: 6d7b ldr r3, [r7, #84] @ 0x54 80045b4: 2b00 cmp r3, #0 80045b6: d1e4 bne.n 8004582 } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80045b8: 68fb ldr r3, [r7, #12] 80045ba: 681b ldr r3, [r3, #0] 80045bc: 3308 adds r3, #8 80045be: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80045c0: 6bfb ldr r3, [r7, #60] @ 0x3c 80045c2: e853 3f00 ldrex r3, [r3] 80045c6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80045c8: 6bbb ldr r3, [r7, #56] @ 0x38 80045ca: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80045ce: 67fb str r3, [r7, #124] @ 0x7c 80045d0: 68fb ldr r3, [r7, #12] 80045d2: 681b ldr r3, [r3, #0] 80045d4: 3308 adds r3, #8 80045d6: 6ffa ldr r2, [r7, #124] @ 0x7c 80045d8: 64ba str r2, [r7, #72] @ 0x48 80045da: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80045dc: 6c79 ldr r1, [r7, #68] @ 0x44 80045de: 6cba ldr r2, [r7, #72] @ 0x48 80045e0: e841 2300 strex r3, r2, [r1] 80045e4: 643b str r3, [r7, #64] @ 0x40 return(result); 80045e6: 6c3b ldr r3, [r7, #64] @ 0x40 80045e8: 2b00 cmp r3, #0 80045ea: d1e5 bne.n 80045b8 80045ec: e046 b.n 800467c } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80045ee: 68fb ldr r3, [r7, #12] 80045f0: 689b ldr r3, [r3, #8] 80045f2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80045f6: d107 bne.n 8004608 80045f8: 68fb ldr r3, [r7, #12] 80045fa: 691b ldr r3, [r3, #16] 80045fc: 2b00 cmp r3, #0 80045fe: d103 bne.n 8004608 { huart->RxISR = UART_RxISR_16BIT; 8004600: 68fb ldr r3, [r7, #12] 8004602: 4a24 ldr r2, [pc, #144] @ (8004694 ) 8004604: 675a str r2, [r3, #116] @ 0x74 8004606: e002 b.n 800460e } else { huart->RxISR = UART_RxISR_8BIT; 8004608: 68fb ldr r3, [r7, #12] 800460a: 4a23 ldr r2, [pc, #140] @ (8004698 ) 800460c: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 800460e: 68fb ldr r3, [r7, #12] 8004610: 691b ldr r3, [r3, #16] 8004612: 2b00 cmp r3, #0 8004614: d019 beq.n 800464a { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8004616: 68fb ldr r3, [r7, #12] 8004618: 681b ldr r3, [r3, #0] 800461a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800461c: 6abb ldr r3, [r7, #40] @ 0x28 800461e: e853 3f00 ldrex r3, [r3] 8004622: 627b str r3, [r7, #36] @ 0x24 return(result); 8004624: 6a7b ldr r3, [r7, #36] @ 0x24 8004626: f443 7390 orr.w r3, r3, #288 @ 0x120 800462a: 677b str r3, [r7, #116] @ 0x74 800462c: 68fb ldr r3, [r7, #12] 800462e: 681b ldr r3, [r3, #0] 8004630: 461a mov r2, r3 8004632: 6f7b ldr r3, [r7, #116] @ 0x74 8004634: 637b str r3, [r7, #52] @ 0x34 8004636: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004638: 6b39 ldr r1, [r7, #48] @ 0x30 800463a: 6b7a ldr r2, [r7, #52] @ 0x34 800463c: e841 2300 strex r3, r2, [r1] 8004640: 62fb str r3, [r7, #44] @ 0x2c return(result); 8004642: 6afb ldr r3, [r7, #44] @ 0x2c 8004644: 2b00 cmp r3, #0 8004646: d1e6 bne.n 8004616 8004648: e018 b.n 800467c } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800464a: 68fb ldr r3, [r7, #12] 800464c: 681b ldr r3, [r3, #0] 800464e: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004650: 697b ldr r3, [r7, #20] 8004652: e853 3f00 ldrex r3, [r3] 8004656: 613b str r3, [r7, #16] return(result); 8004658: 693b ldr r3, [r7, #16] 800465a: f043 0320 orr.w r3, r3, #32 800465e: 67bb str r3, [r7, #120] @ 0x78 8004660: 68fb ldr r3, [r7, #12] 8004662: 681b ldr r3, [r3, #0] 8004664: 461a mov r2, r3 8004666: 6fbb ldr r3, [r7, #120] @ 0x78 8004668: 623b str r3, [r7, #32] 800466a: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800466c: 69f9 ldr r1, [r7, #28] 800466e: 6a3a ldr r2, [r7, #32] 8004670: e841 2300 strex r3, r2, [r1] 8004674: 61bb str r3, [r7, #24] return(result); 8004676: 69bb ldr r3, [r7, #24] 8004678: 2b00 cmp r3, #0 800467a: d1e6 bne.n 800464a } } return HAL_OK; 800467c: 2300 movs r3, #0 } 800467e: 4618 mov r0, r3 8004680: 378c adds r7, #140 @ 0x8c 8004682: 46bd mov sp, r7 8004684: f85d 7b04 ldr.w r7, [sp], #4 8004688: 4770 bx lr 800468a: bf00 nop 800468c: 08004eb1 .word 0x08004eb1 8004690: 08004b4d .word 0x08004b4d 8004694: 08004995 .word 0x08004995 8004698: 080047dd .word 0x080047dd 0800469c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800469c: b480 push {r7} 800469e: b095 sub sp, #84 @ 0x54 80046a0: af00 add r7, sp, #0 80046a2: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80046a4: 687b ldr r3, [r7, #4] 80046a6: 681b ldr r3, [r3, #0] 80046a8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80046aa: 6b7b ldr r3, [r7, #52] @ 0x34 80046ac: e853 3f00 ldrex r3, [r3] 80046b0: 633b str r3, [r7, #48] @ 0x30 return(result); 80046b2: 6b3b ldr r3, [r7, #48] @ 0x30 80046b4: f423 7390 bic.w r3, r3, #288 @ 0x120 80046b8: 64fb str r3, [r7, #76] @ 0x4c 80046ba: 687b ldr r3, [r7, #4] 80046bc: 681b ldr r3, [r3, #0] 80046be: 461a mov r2, r3 80046c0: 6cfb ldr r3, [r7, #76] @ 0x4c 80046c2: 643b str r3, [r7, #64] @ 0x40 80046c4: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80046c6: 6bf9 ldr r1, [r7, #60] @ 0x3c 80046c8: 6c3a ldr r2, [r7, #64] @ 0x40 80046ca: e841 2300 strex r3, r2, [r1] 80046ce: 63bb str r3, [r7, #56] @ 0x38 return(result); 80046d0: 6bbb ldr r3, [r7, #56] @ 0x38 80046d2: 2b00 cmp r3, #0 80046d4: d1e6 bne.n 80046a4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80046d6: 687b ldr r3, [r7, #4] 80046d8: 681b ldr r3, [r3, #0] 80046da: 3308 adds r3, #8 80046dc: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80046de: 6a3b ldr r3, [r7, #32] 80046e0: e853 3f00 ldrex r3, [r3] 80046e4: 61fb str r3, [r7, #28] return(result); 80046e6: 69fb ldr r3, [r7, #28] 80046e8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80046ec: f023 0301 bic.w r3, r3, #1 80046f0: 64bb str r3, [r7, #72] @ 0x48 80046f2: 687b ldr r3, [r7, #4] 80046f4: 681b ldr r3, [r3, #0] 80046f6: 3308 adds r3, #8 80046f8: 6cba ldr r2, [r7, #72] @ 0x48 80046fa: 62fa str r2, [r7, #44] @ 0x2c 80046fc: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80046fe: 6ab9 ldr r1, [r7, #40] @ 0x28 8004700: 6afa ldr r2, [r7, #44] @ 0x2c 8004702: e841 2300 strex r3, r2, [r1] 8004706: 627b str r3, [r7, #36] @ 0x24 return(result); 8004708: 6a7b ldr r3, [r7, #36] @ 0x24 800470a: 2b00 cmp r3, #0 800470c: d1e3 bne.n 80046d6 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800470e: 687b ldr r3, [r7, #4] 8004710: 6edb ldr r3, [r3, #108] @ 0x6c 8004712: 2b01 cmp r3, #1 8004714: d118 bne.n 8004748 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004716: 687b ldr r3, [r7, #4] 8004718: 681b ldr r3, [r3, #0] 800471a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800471c: 68fb ldr r3, [r7, #12] 800471e: e853 3f00 ldrex r3, [r3] 8004722: 60bb str r3, [r7, #8] return(result); 8004724: 68bb ldr r3, [r7, #8] 8004726: f023 0310 bic.w r3, r3, #16 800472a: 647b str r3, [r7, #68] @ 0x44 800472c: 687b ldr r3, [r7, #4] 800472e: 681b ldr r3, [r3, #0] 8004730: 461a mov r2, r3 8004732: 6c7b ldr r3, [r7, #68] @ 0x44 8004734: 61bb str r3, [r7, #24] 8004736: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004738: 6979 ldr r1, [r7, #20] 800473a: 69ba ldr r2, [r7, #24] 800473c: e841 2300 strex r3, r2, [r1] 8004740: 613b str r3, [r7, #16] return(result); 8004742: 693b ldr r3, [r7, #16] 8004744: 2b00 cmp r3, #0 8004746: d1e6 bne.n 8004716 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004748: 687b ldr r3, [r7, #4] 800474a: 2220 movs r2, #32 800474c: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004750: 687b ldr r3, [r7, #4] 8004752: 2200 movs r2, #0 8004754: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8004756: 687b ldr r3, [r7, #4] 8004758: 2200 movs r2, #0 800475a: 675a str r2, [r3, #116] @ 0x74 } 800475c: bf00 nop 800475e: 3754 adds r7, #84 @ 0x54 8004760: 46bd mov sp, r7 8004762: f85d 7b04 ldr.w r7, [sp], #4 8004766: 4770 bx lr 08004768 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8004768: b580 push {r7, lr} 800476a: b084 sub sp, #16 800476c: af00 add r7, sp, #0 800476e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8004770: 687b ldr r3, [r7, #4] 8004772: 6a9b ldr r3, [r3, #40] @ 0x28 8004774: 60fb str r3, [r7, #12] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004776: 68f8 ldr r0, [r7, #12] 8004778: f7ff f9d2 bl 8003b20 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800477c: bf00 nop 800477e: 3710 adds r7, #16 8004780: 46bd mov sp, r7 8004782: bd80 pop {r7, pc} 08004784 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8004784: b580 push {r7, lr} 8004786: b088 sub sp, #32 8004788: af00 add r7, sp, #0 800478a: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800478c: 687b ldr r3, [r7, #4] 800478e: 681b ldr r3, [r3, #0] 8004790: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004792: 68fb ldr r3, [r7, #12] 8004794: e853 3f00 ldrex r3, [r3] 8004798: 60bb str r3, [r7, #8] return(result); 800479a: 68bb ldr r3, [r7, #8] 800479c: f023 0340 bic.w r3, r3, #64 @ 0x40 80047a0: 61fb str r3, [r7, #28] 80047a2: 687b ldr r3, [r7, #4] 80047a4: 681b ldr r3, [r3, #0] 80047a6: 461a mov r2, r3 80047a8: 69fb ldr r3, [r7, #28] 80047aa: 61bb str r3, [r7, #24] 80047ac: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80047ae: 6979 ldr r1, [r7, #20] 80047b0: 69ba ldr r2, [r7, #24] 80047b2: e841 2300 strex r3, r2, [r1] 80047b6: 613b str r3, [r7, #16] return(result); 80047b8: 693b ldr r3, [r7, #16] 80047ba: 2b00 cmp r3, #0 80047bc: d1e6 bne.n 800478c /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 80047be: 687b ldr r3, [r7, #4] 80047c0: 2220 movs r2, #32 80047c2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 80047c6: 687b ldr r3, [r7, #4] 80047c8: 2200 movs r2, #0 80047ca: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 80047cc: 6878 ldr r0, [r7, #4] 80047ce: f7ff f99d bl 8003b0c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80047d2: bf00 nop 80047d4: 3720 adds r7, #32 80047d6: 46bd mov sp, r7 80047d8: bd80 pop {r7, pc} ... 080047dc : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 80047dc: b580 push {r7, lr} 80047de: b09c sub sp, #112 @ 0x70 80047e0: af00 add r7, sp, #0 80047e2: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80047e4: 687b ldr r3, [r7, #4] 80047e6: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80047ea: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80047ee: 687b ldr r3, [r7, #4] 80047f0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80047f4: 2b22 cmp r3, #34 @ 0x22 80047f6: f040 80be bne.w 8004976 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80047fa: 687b ldr r3, [r7, #4] 80047fc: 681b ldr r3, [r3, #0] 80047fe: 6a5b ldr r3, [r3, #36] @ 0x24 8004800: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8004804: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8004808: b2d9 uxtb r1, r3 800480a: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 800480e: b2da uxtb r2, r3 8004810: 687b ldr r3, [r7, #4] 8004812: 6d9b ldr r3, [r3, #88] @ 0x58 8004814: 400a ands r2, r1 8004816: b2d2 uxtb r2, r2 8004818: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 800481a: 687b ldr r3, [r7, #4] 800481c: 6d9b ldr r3, [r3, #88] @ 0x58 800481e: 1c5a adds r2, r3, #1 8004820: 687b ldr r3, [r7, #4] 8004822: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8004824: 687b ldr r3, [r7, #4] 8004826: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800482a: b29b uxth r3, r3 800482c: 3b01 subs r3, #1 800482e: b29a uxth r2, r3 8004830: 687b ldr r3, [r7, #4] 8004832: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8004836: 687b ldr r3, [r7, #4] 8004838: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800483c: b29b uxth r3, r3 800483e: 2b00 cmp r3, #0 8004840: f040 80a1 bne.w 8004986 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8004844: 687b ldr r3, [r7, #4] 8004846: 681b ldr r3, [r3, #0] 8004848: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800484a: 6cfb ldr r3, [r7, #76] @ 0x4c 800484c: e853 3f00 ldrex r3, [r3] 8004850: 64bb str r3, [r7, #72] @ 0x48 return(result); 8004852: 6cbb ldr r3, [r7, #72] @ 0x48 8004854: f423 7390 bic.w r3, r3, #288 @ 0x120 8004858: 66bb str r3, [r7, #104] @ 0x68 800485a: 687b ldr r3, [r7, #4] 800485c: 681b ldr r3, [r3, #0] 800485e: 461a mov r2, r3 8004860: 6ebb ldr r3, [r7, #104] @ 0x68 8004862: 65bb str r3, [r7, #88] @ 0x58 8004864: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004866: 6d79 ldr r1, [r7, #84] @ 0x54 8004868: 6dba ldr r2, [r7, #88] @ 0x58 800486a: e841 2300 strex r3, r2, [r1] 800486e: 653b str r3, [r7, #80] @ 0x50 return(result); 8004870: 6d3b ldr r3, [r7, #80] @ 0x50 8004872: 2b00 cmp r3, #0 8004874: d1e6 bne.n 8004844 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004876: 687b ldr r3, [r7, #4] 8004878: 681b ldr r3, [r3, #0] 800487a: 3308 adds r3, #8 800487c: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800487e: 6bbb ldr r3, [r7, #56] @ 0x38 8004880: e853 3f00 ldrex r3, [r3] 8004884: 637b str r3, [r7, #52] @ 0x34 return(result); 8004886: 6b7b ldr r3, [r7, #52] @ 0x34 8004888: f023 0301 bic.w r3, r3, #1 800488c: 667b str r3, [r7, #100] @ 0x64 800488e: 687b ldr r3, [r7, #4] 8004890: 681b ldr r3, [r3, #0] 8004892: 3308 adds r3, #8 8004894: 6e7a ldr r2, [r7, #100] @ 0x64 8004896: 647a str r2, [r7, #68] @ 0x44 8004898: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800489a: 6c39 ldr r1, [r7, #64] @ 0x40 800489c: 6c7a ldr r2, [r7, #68] @ 0x44 800489e: e841 2300 strex r3, r2, [r1] 80048a2: 63fb str r3, [r7, #60] @ 0x3c return(result); 80048a4: 6bfb ldr r3, [r7, #60] @ 0x3c 80048a6: 2b00 cmp r3, #0 80048a8: d1e5 bne.n 8004876 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80048aa: 687b ldr r3, [r7, #4] 80048ac: 2220 movs r2, #32 80048ae: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80048b2: 687b ldr r3, [r7, #4] 80048b4: 2200 movs r2, #0 80048b6: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80048b8: 687b ldr r3, [r7, #4] 80048ba: 2200 movs r2, #0 80048bc: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80048be: 687b ldr r3, [r7, #4] 80048c0: 681b ldr r3, [r3, #0] 80048c2: 4a33 ldr r2, [pc, #204] @ (8004990 ) 80048c4: 4293 cmp r3, r2 80048c6: d01f beq.n 8004908 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80048c8: 687b ldr r3, [r7, #4] 80048ca: 681b ldr r3, [r3, #0] 80048cc: 685b ldr r3, [r3, #4] 80048ce: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80048d2: 2b00 cmp r3, #0 80048d4: d018 beq.n 8004908 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80048d6: 687b ldr r3, [r7, #4] 80048d8: 681b ldr r3, [r3, #0] 80048da: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80048dc: 6a7b ldr r3, [r7, #36] @ 0x24 80048de: e853 3f00 ldrex r3, [r3] 80048e2: 623b str r3, [r7, #32] return(result); 80048e4: 6a3b ldr r3, [r7, #32] 80048e6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80048ea: 663b str r3, [r7, #96] @ 0x60 80048ec: 687b ldr r3, [r7, #4] 80048ee: 681b ldr r3, [r3, #0] 80048f0: 461a mov r2, r3 80048f2: 6e3b ldr r3, [r7, #96] @ 0x60 80048f4: 633b str r3, [r7, #48] @ 0x30 80048f6: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80048f8: 6af9 ldr r1, [r7, #44] @ 0x2c 80048fa: 6b3a ldr r2, [r7, #48] @ 0x30 80048fc: e841 2300 strex r3, r2, [r1] 8004900: 62bb str r3, [r7, #40] @ 0x28 return(result); 8004902: 6abb ldr r3, [r7, #40] @ 0x28 8004904: 2b00 cmp r3, #0 8004906: d1e6 bne.n 80048d6 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004908: 687b ldr r3, [r7, #4] 800490a: 6edb ldr r3, [r3, #108] @ 0x6c 800490c: 2b01 cmp r3, #1 800490e: d12e bne.n 800496e { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004910: 687b ldr r3, [r7, #4] 8004912: 2200 movs r2, #0 8004914: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004916: 687b ldr r3, [r7, #4] 8004918: 681b ldr r3, [r3, #0] 800491a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800491c: 693b ldr r3, [r7, #16] 800491e: e853 3f00 ldrex r3, [r3] 8004922: 60fb str r3, [r7, #12] return(result); 8004924: 68fb ldr r3, [r7, #12] 8004926: f023 0310 bic.w r3, r3, #16 800492a: 65fb str r3, [r7, #92] @ 0x5c 800492c: 687b ldr r3, [r7, #4] 800492e: 681b ldr r3, [r3, #0] 8004930: 461a mov r2, r3 8004932: 6dfb ldr r3, [r7, #92] @ 0x5c 8004934: 61fb str r3, [r7, #28] 8004936: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004938: 69b9 ldr r1, [r7, #24] 800493a: 69fa ldr r2, [r7, #28] 800493c: e841 2300 strex r3, r2, [r1] 8004940: 617b str r3, [r7, #20] return(result); 8004942: 697b ldr r3, [r7, #20] 8004944: 2b00 cmp r3, #0 8004946: d1e6 bne.n 8004916 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8004948: 687b ldr r3, [r7, #4] 800494a: 681b ldr r3, [r3, #0] 800494c: 69db ldr r3, [r3, #28] 800494e: f003 0310 and.w r3, r3, #16 8004952: 2b10 cmp r3, #16 8004954: d103 bne.n 800495e { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8004956: 687b ldr r3, [r7, #4] 8004958: 681b ldr r3, [r3, #0] 800495a: 2210 movs r2, #16 800495c: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800495e: 687b ldr r3, [r7, #4] 8004960: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8004964: 4619 mov r1, r3 8004966: 6878 ldr r0, [r7, #4] 8004968: f7ff f8e4 bl 8003b34 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800496c: e00b b.n 8004986 HAL_UART_RxCpltCallback(huart); 800496e: 6878 ldr r0, [r7, #4] 8004970: f7fc fa6e bl 8000e50 } 8004974: e007 b.n 8004986 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8004976: 687b ldr r3, [r7, #4] 8004978: 681b ldr r3, [r3, #0] 800497a: 699a ldr r2, [r3, #24] 800497c: 687b ldr r3, [r7, #4] 800497e: 681b ldr r3, [r3, #0] 8004980: f042 0208 orr.w r2, r2, #8 8004984: 619a str r2, [r3, #24] } 8004986: bf00 nop 8004988: 3770 adds r7, #112 @ 0x70 800498a: 46bd mov sp, r7 800498c: bd80 pop {r7, pc} 800498e: bf00 nop 8004990: 40008000 .word 0x40008000 08004994 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8004994: b580 push {r7, lr} 8004996: b09c sub sp, #112 @ 0x70 8004998: af00 add r7, sp, #0 800499a: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 800499c: 687b ldr r3, [r7, #4] 800499e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80049a2: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80049a6: 687b ldr r3, [r7, #4] 80049a8: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80049ac: 2b22 cmp r3, #34 @ 0x22 80049ae: f040 80be bne.w 8004b2e { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80049b2: 687b ldr r3, [r7, #4] 80049b4: 681b ldr r3, [r3, #0] 80049b6: 6a5b ldr r3, [r3, #36] @ 0x24 80049b8: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 80049bc: 687b ldr r3, [r7, #4] 80049be: 6d9b ldr r3, [r3, #88] @ 0x58 80049c0: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 80049c2: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 80049c6: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 80049ca: 4013 ands r3, r2 80049cc: b29a uxth r2, r3 80049ce: 6ebb ldr r3, [r7, #104] @ 0x68 80049d0: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 80049d2: 687b ldr r3, [r7, #4] 80049d4: 6d9b ldr r3, [r3, #88] @ 0x58 80049d6: 1c9a adds r2, r3, #2 80049d8: 687b ldr r3, [r7, #4] 80049da: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 80049dc: 687b ldr r3, [r7, #4] 80049de: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80049e2: b29b uxth r3, r3 80049e4: 3b01 subs r3, #1 80049e6: b29a uxth r2, r3 80049e8: 687b ldr r3, [r7, #4] 80049ea: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 80049ee: 687b ldr r3, [r7, #4] 80049f0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80049f4: b29b uxth r3, r3 80049f6: 2b00 cmp r3, #0 80049f8: f040 80a1 bne.w 8004b3e { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80049fc: 687b ldr r3, [r7, #4] 80049fe: 681b ldr r3, [r3, #0] 8004a00: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004a02: 6cbb ldr r3, [r7, #72] @ 0x48 8004a04: e853 3f00 ldrex r3, [r3] 8004a08: 647b str r3, [r7, #68] @ 0x44 return(result); 8004a0a: 6c7b ldr r3, [r7, #68] @ 0x44 8004a0c: f423 7390 bic.w r3, r3, #288 @ 0x120 8004a10: 667b str r3, [r7, #100] @ 0x64 8004a12: 687b ldr r3, [r7, #4] 8004a14: 681b ldr r3, [r3, #0] 8004a16: 461a mov r2, r3 8004a18: 6e7b ldr r3, [r7, #100] @ 0x64 8004a1a: 657b str r3, [r7, #84] @ 0x54 8004a1c: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004a1e: 6d39 ldr r1, [r7, #80] @ 0x50 8004a20: 6d7a ldr r2, [r7, #84] @ 0x54 8004a22: e841 2300 strex r3, r2, [r1] 8004a26: 64fb str r3, [r7, #76] @ 0x4c return(result); 8004a28: 6cfb ldr r3, [r7, #76] @ 0x4c 8004a2a: 2b00 cmp r3, #0 8004a2c: d1e6 bne.n 80049fc /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004a2e: 687b ldr r3, [r7, #4] 8004a30: 681b ldr r3, [r3, #0] 8004a32: 3308 adds r3, #8 8004a34: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004a36: 6b7b ldr r3, [r7, #52] @ 0x34 8004a38: e853 3f00 ldrex r3, [r3] 8004a3c: 633b str r3, [r7, #48] @ 0x30 return(result); 8004a3e: 6b3b ldr r3, [r7, #48] @ 0x30 8004a40: f023 0301 bic.w r3, r3, #1 8004a44: 663b str r3, [r7, #96] @ 0x60 8004a46: 687b ldr r3, [r7, #4] 8004a48: 681b ldr r3, [r3, #0] 8004a4a: 3308 adds r3, #8 8004a4c: 6e3a ldr r2, [r7, #96] @ 0x60 8004a4e: 643a str r2, [r7, #64] @ 0x40 8004a50: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004a52: 6bf9 ldr r1, [r7, #60] @ 0x3c 8004a54: 6c3a ldr r2, [r7, #64] @ 0x40 8004a56: e841 2300 strex r3, r2, [r1] 8004a5a: 63bb str r3, [r7, #56] @ 0x38 return(result); 8004a5c: 6bbb ldr r3, [r7, #56] @ 0x38 8004a5e: 2b00 cmp r3, #0 8004a60: d1e5 bne.n 8004a2e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004a62: 687b ldr r3, [r7, #4] 8004a64: 2220 movs r2, #32 8004a66: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8004a6a: 687b ldr r3, [r7, #4] 8004a6c: 2200 movs r2, #0 8004a6e: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8004a70: 687b ldr r3, [r7, #4] 8004a72: 2200 movs r2, #0 8004a74: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8004a76: 687b ldr r3, [r7, #4] 8004a78: 681b ldr r3, [r3, #0] 8004a7a: 4a33 ldr r2, [pc, #204] @ (8004b48 ) 8004a7c: 4293 cmp r3, r2 8004a7e: d01f beq.n 8004ac0 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8004a80: 687b ldr r3, [r7, #4] 8004a82: 681b ldr r3, [r3, #0] 8004a84: 685b ldr r3, [r3, #4] 8004a86: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8004a8a: 2b00 cmp r3, #0 8004a8c: d018 beq.n 8004ac0 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8004a8e: 687b ldr r3, [r7, #4] 8004a90: 681b ldr r3, [r3, #0] 8004a92: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004a94: 6a3b ldr r3, [r7, #32] 8004a96: e853 3f00 ldrex r3, [r3] 8004a9a: 61fb str r3, [r7, #28] return(result); 8004a9c: 69fb ldr r3, [r7, #28] 8004a9e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8004aa2: 65fb str r3, [r7, #92] @ 0x5c 8004aa4: 687b ldr r3, [r7, #4] 8004aa6: 681b ldr r3, [r3, #0] 8004aa8: 461a mov r2, r3 8004aaa: 6dfb ldr r3, [r7, #92] @ 0x5c 8004aac: 62fb str r3, [r7, #44] @ 0x2c 8004aae: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004ab0: 6ab9 ldr r1, [r7, #40] @ 0x28 8004ab2: 6afa ldr r2, [r7, #44] @ 0x2c 8004ab4: e841 2300 strex r3, r2, [r1] 8004ab8: 627b str r3, [r7, #36] @ 0x24 return(result); 8004aba: 6a7b ldr r3, [r7, #36] @ 0x24 8004abc: 2b00 cmp r3, #0 8004abe: d1e6 bne.n 8004a8e } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004ac0: 687b ldr r3, [r7, #4] 8004ac2: 6edb ldr r3, [r3, #108] @ 0x6c 8004ac4: 2b01 cmp r3, #1 8004ac6: d12e bne.n 8004b26 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004ac8: 687b ldr r3, [r7, #4] 8004aca: 2200 movs r2, #0 8004acc: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004ace: 687b ldr r3, [r7, #4] 8004ad0: 681b ldr r3, [r3, #0] 8004ad2: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004ad4: 68fb ldr r3, [r7, #12] 8004ad6: e853 3f00 ldrex r3, [r3] 8004ada: 60bb str r3, [r7, #8] return(result); 8004adc: 68bb ldr r3, [r7, #8] 8004ade: f023 0310 bic.w r3, r3, #16 8004ae2: 65bb str r3, [r7, #88] @ 0x58 8004ae4: 687b ldr r3, [r7, #4] 8004ae6: 681b ldr r3, [r3, #0] 8004ae8: 461a mov r2, r3 8004aea: 6dbb ldr r3, [r7, #88] @ 0x58 8004aec: 61bb str r3, [r7, #24] 8004aee: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004af0: 6979 ldr r1, [r7, #20] 8004af2: 69ba ldr r2, [r7, #24] 8004af4: e841 2300 strex r3, r2, [r1] 8004af8: 613b str r3, [r7, #16] return(result); 8004afa: 693b ldr r3, [r7, #16] 8004afc: 2b00 cmp r3, #0 8004afe: d1e6 bne.n 8004ace if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8004b00: 687b ldr r3, [r7, #4] 8004b02: 681b ldr r3, [r3, #0] 8004b04: 69db ldr r3, [r3, #28] 8004b06: f003 0310 and.w r3, r3, #16 8004b0a: 2b10 cmp r3, #16 8004b0c: d103 bne.n 8004b16 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8004b0e: 687b ldr r3, [r7, #4] 8004b10: 681b ldr r3, [r3, #0] 8004b12: 2210 movs r2, #16 8004b14: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8004b16: 687b ldr r3, [r7, #4] 8004b18: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8004b1c: 4619 mov r1, r3 8004b1e: 6878 ldr r0, [r7, #4] 8004b20: f7ff f808 bl 8003b34 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8004b24: e00b b.n 8004b3e HAL_UART_RxCpltCallback(huart); 8004b26: 6878 ldr r0, [r7, #4] 8004b28: f7fc f992 bl 8000e50 } 8004b2c: e007 b.n 8004b3e __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8004b2e: 687b ldr r3, [r7, #4] 8004b30: 681b ldr r3, [r3, #0] 8004b32: 699a ldr r2, [r3, #24] 8004b34: 687b ldr r3, [r7, #4] 8004b36: 681b ldr r3, [r3, #0] 8004b38: f042 0208 orr.w r2, r2, #8 8004b3c: 619a str r2, [r3, #24] } 8004b3e: bf00 nop 8004b40: 3770 adds r7, #112 @ 0x70 8004b42: 46bd mov sp, r7 8004b44: bd80 pop {r7, pc} 8004b46: bf00 nop 8004b48: 40008000 .word 0x40008000 08004b4c : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8004b4c: b580 push {r7, lr} 8004b4e: b0ac sub sp, #176 @ 0xb0 8004b50: af00 add r7, sp, #0 8004b52: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8004b54: 687b ldr r3, [r7, #4] 8004b56: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8004b5a: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8004b5e: 687b ldr r3, [r7, #4] 8004b60: 681b ldr r3, [r3, #0] 8004b62: 69db ldr r3, [r3, #28] 8004b64: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 8004b68: 687b ldr r3, [r7, #4] 8004b6a: 681b ldr r3, [r3, #0] 8004b6c: 681b ldr r3, [r3, #0] 8004b6e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8004b72: 687b ldr r3, [r7, #4] 8004b74: 681b ldr r3, [r3, #0] 8004b76: 689b ldr r3, [r3, #8] 8004b78: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8004b7c: 687b ldr r3, [r7, #4] 8004b7e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004b82: 2b22 cmp r3, #34 @ 0x22 8004b84: f040 8183 bne.w 8004e8e { nb_rx_data = huart->NbRxDataToProcess; 8004b88: 687b ldr r3, [r7, #4] 8004b8a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8004b8e: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8004b92: e126 b.n 8004de2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8004b94: 687b ldr r3, [r7, #4] 8004b96: 681b ldr r3, [r3, #0] 8004b98: 6a5b ldr r3, [r3, #36] @ 0x24 8004b9a: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8004b9e: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8004ba2: b2d9 uxtb r1, r3 8004ba4: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 8004ba8: b2da uxtb r2, r3 8004baa: 687b ldr r3, [r7, #4] 8004bac: 6d9b ldr r3, [r3, #88] @ 0x58 8004bae: 400a ands r2, r1 8004bb0: b2d2 uxtb r2, r2 8004bb2: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8004bb4: 687b ldr r3, [r7, #4] 8004bb6: 6d9b ldr r3, [r3, #88] @ 0x58 8004bb8: 1c5a adds r2, r3, #1 8004bba: 687b ldr r3, [r7, #4] 8004bbc: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8004bbe: 687b ldr r3, [r7, #4] 8004bc0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8004bc4: b29b uxth r3, r3 8004bc6: 3b01 subs r3, #1 8004bc8: b29a uxth r2, r3 8004bca: 687b ldr r3, [r7, #4] 8004bcc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8004bd0: 687b ldr r3, [r7, #4] 8004bd2: 681b ldr r3, [r3, #0] 8004bd4: 69db ldr r3, [r3, #28] 8004bd6: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8004bda: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004bde: f003 0307 and.w r3, r3, #7 8004be2: 2b00 cmp r3, #0 8004be4: d053 beq.n 8004c8e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8004be6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004bea: f003 0301 and.w r3, r3, #1 8004bee: 2b00 cmp r3, #0 8004bf0: d011 beq.n 8004c16 8004bf2: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8004bf6: f403 7380 and.w r3, r3, #256 @ 0x100 8004bfa: 2b00 cmp r3, #0 8004bfc: d00b beq.n 8004c16 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8004bfe: 687b ldr r3, [r7, #4] 8004c00: 681b ldr r3, [r3, #0] 8004c02: 2201 movs r2, #1 8004c04: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8004c06: 687b ldr r3, [r7, #4] 8004c08: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004c0c: f043 0201 orr.w r2, r3, #1 8004c10: 687b ldr r3, [r7, #4] 8004c12: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004c16: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004c1a: f003 0302 and.w r3, r3, #2 8004c1e: 2b00 cmp r3, #0 8004c20: d011 beq.n 8004c46 8004c22: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8004c26: f003 0301 and.w r3, r3, #1 8004c2a: 2b00 cmp r3, #0 8004c2c: d00b beq.n 8004c46 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8004c2e: 687b ldr r3, [r7, #4] 8004c30: 681b ldr r3, [r3, #0] 8004c32: 2202 movs r2, #2 8004c34: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8004c36: 687b ldr r3, [r7, #4] 8004c38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004c3c: f043 0204 orr.w r2, r3, #4 8004c40: 687b ldr r3, [r7, #4] 8004c42: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004c46: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004c4a: f003 0304 and.w r3, r3, #4 8004c4e: 2b00 cmp r3, #0 8004c50: d011 beq.n 8004c76 8004c52: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8004c56: f003 0301 and.w r3, r3, #1 8004c5a: 2b00 cmp r3, #0 8004c5c: d00b beq.n 8004c76 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8004c5e: 687b ldr r3, [r7, #4] 8004c60: 681b ldr r3, [r3, #0] 8004c62: 2204 movs r2, #4 8004c64: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8004c66: 687b ldr r3, [r7, #4] 8004c68: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004c6c: f043 0202 orr.w r2, r3, #2 8004c70: 687b ldr r3, [r7, #4] 8004c72: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8004c76: 687b ldr r3, [r7, #4] 8004c78: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004c7c: 2b00 cmp r3, #0 8004c7e: d006 beq.n 8004c8e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004c80: 6878 ldr r0, [r7, #4] 8004c82: f7fe ff4d bl 8003b20 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004c86: 687b ldr r3, [r7, #4] 8004c88: 2200 movs r2, #0 8004c8a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8004c8e: 687b ldr r3, [r7, #4] 8004c90: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8004c94: b29b uxth r3, r3 8004c96: 2b00 cmp r3, #0 8004c98: f040 80a3 bne.w 8004de2 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8004c9c: 687b ldr r3, [r7, #4] 8004c9e: 681b ldr r3, [r3, #0] 8004ca0: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004ca2: 6f3b ldr r3, [r7, #112] @ 0x70 8004ca4: e853 3f00 ldrex r3, [r3] 8004ca8: 66fb str r3, [r7, #108] @ 0x6c return(result); 8004caa: 6efb ldr r3, [r7, #108] @ 0x6c 8004cac: f423 7380 bic.w r3, r3, #256 @ 0x100 8004cb0: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8004cb4: 687b ldr r3, [r7, #4] 8004cb6: 681b ldr r3, [r3, #0] 8004cb8: 461a mov r2, r3 8004cba: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004cbe: 67fb str r3, [r7, #124] @ 0x7c 8004cc0: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004cc2: 6fb9 ldr r1, [r7, #120] @ 0x78 8004cc4: 6ffa ldr r2, [r7, #124] @ 0x7c 8004cc6: e841 2300 strex r3, r2, [r1] 8004cca: 677b str r3, [r7, #116] @ 0x74 return(result); 8004ccc: 6f7b ldr r3, [r7, #116] @ 0x74 8004cce: 2b00 cmp r3, #0 8004cd0: d1e4 bne.n 8004c9c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8004cd2: 687b ldr r3, [r7, #4] 8004cd4: 681b ldr r3, [r3, #0] 8004cd6: 3308 adds r3, #8 8004cd8: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004cda: 6dfb ldr r3, [r7, #92] @ 0x5c 8004cdc: e853 3f00 ldrex r3, [r3] 8004ce0: 65bb str r3, [r7, #88] @ 0x58 return(result); 8004ce2: 6dbb ldr r3, [r7, #88] @ 0x58 8004ce4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8004ce8: f023 0301 bic.w r3, r3, #1 8004cec: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8004cf0: 687b ldr r3, [r7, #4] 8004cf2: 681b ldr r3, [r3, #0] 8004cf4: 3308 adds r3, #8 8004cf6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8004cfa: 66ba str r2, [r7, #104] @ 0x68 8004cfc: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004cfe: 6e79 ldr r1, [r7, #100] @ 0x64 8004d00: 6eba ldr r2, [r7, #104] @ 0x68 8004d02: e841 2300 strex r3, r2, [r1] 8004d06: 663b str r3, [r7, #96] @ 0x60 return(result); 8004d08: 6e3b ldr r3, [r7, #96] @ 0x60 8004d0a: 2b00 cmp r3, #0 8004d0c: d1e1 bne.n 8004cd2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8004d0e: 687b ldr r3, [r7, #4] 8004d10: 2220 movs r2, #32 8004d12: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8004d16: 687b ldr r3, [r7, #4] 8004d18: 2200 movs r2, #0 8004d1a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8004d1c: 687b ldr r3, [r7, #4] 8004d1e: 2200 movs r2, #0 8004d20: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8004d22: 687b ldr r3, [r7, #4] 8004d24: 681b ldr r3, [r3, #0] 8004d26: 4a60 ldr r2, [pc, #384] @ (8004ea8 ) 8004d28: 4293 cmp r3, r2 8004d2a: d021 beq.n 8004d70 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8004d2c: 687b ldr r3, [r7, #4] 8004d2e: 681b ldr r3, [r3, #0] 8004d30: 685b ldr r3, [r3, #4] 8004d32: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8004d36: 2b00 cmp r3, #0 8004d38: d01a beq.n 8004d70 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: 681b ldr r3, [r3, #0] 8004d3e: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004d40: 6cbb ldr r3, [r7, #72] @ 0x48 8004d42: e853 3f00 ldrex r3, [r3] 8004d46: 647b str r3, [r7, #68] @ 0x44 return(result); 8004d48: 6c7b ldr r3, [r7, #68] @ 0x44 8004d4a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8004d4e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8004d52: 687b ldr r3, [r7, #4] 8004d54: 681b ldr r3, [r3, #0] 8004d56: 461a mov r2, r3 8004d58: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8004d5c: 657b str r3, [r7, #84] @ 0x54 8004d5e: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004d60: 6d39 ldr r1, [r7, #80] @ 0x50 8004d62: 6d7a ldr r2, [r7, #84] @ 0x54 8004d64: e841 2300 strex r3, r2, [r1] 8004d68: 64fb str r3, [r7, #76] @ 0x4c return(result); 8004d6a: 6cfb ldr r3, [r7, #76] @ 0x4c 8004d6c: 2b00 cmp r3, #0 8004d6e: d1e4 bne.n 8004d3a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004d70: 687b ldr r3, [r7, #4] 8004d72: 6edb ldr r3, [r3, #108] @ 0x6c 8004d74: 2b01 cmp r3, #1 8004d76: d130 bne.n 8004dda { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004d78: 687b ldr r3, [r7, #4] 8004d7a: 2200 movs r2, #0 8004d7c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004d7e: 687b ldr r3, [r7, #4] 8004d80: 681b ldr r3, [r3, #0] 8004d82: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004d84: 6b7b ldr r3, [r7, #52] @ 0x34 8004d86: e853 3f00 ldrex r3, [r3] 8004d8a: 633b str r3, [r7, #48] @ 0x30 return(result); 8004d8c: 6b3b ldr r3, [r7, #48] @ 0x30 8004d8e: f023 0310 bic.w r3, r3, #16 8004d92: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8004d96: 687b ldr r3, [r7, #4] 8004d98: 681b ldr r3, [r3, #0] 8004d9a: 461a mov r2, r3 8004d9c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8004da0: 643b str r3, [r7, #64] @ 0x40 8004da2: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004da4: 6bf9 ldr r1, [r7, #60] @ 0x3c 8004da6: 6c3a ldr r2, [r7, #64] @ 0x40 8004da8: e841 2300 strex r3, r2, [r1] 8004dac: 63bb str r3, [r7, #56] @ 0x38 return(result); 8004dae: 6bbb ldr r3, [r7, #56] @ 0x38 8004db0: 2b00 cmp r3, #0 8004db2: d1e4 bne.n 8004d7e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8004db4: 687b ldr r3, [r7, #4] 8004db6: 681b ldr r3, [r3, #0] 8004db8: 69db ldr r3, [r3, #28] 8004dba: f003 0310 and.w r3, r3, #16 8004dbe: 2b10 cmp r3, #16 8004dc0: d103 bne.n 8004dca { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8004dc2: 687b ldr r3, [r7, #4] 8004dc4: 681b ldr r3, [r3, #0] 8004dc6: 2210 movs r2, #16 8004dc8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8004dca: 687b ldr r3, [r7, #4] 8004dcc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8004dd0: 4619 mov r1, r3 8004dd2: 6878 ldr r0, [r7, #4] 8004dd4: f7fe feae bl 8003b34 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; 8004dd8: e00e b.n 8004df8 HAL_UART_RxCpltCallback(huart); 8004dda: 6878 ldr r0, [r7, #4] 8004ddc: f7fc f838 bl 8000e50 break; 8004de0: e00a b.n 8004df8 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8004de2: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 8004de6: 2b00 cmp r3, #0 8004de8: d006 beq.n 8004df8 8004dea: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004dee: f003 0320 and.w r3, r3, #32 8004df2: 2b00 cmp r3, #0 8004df4: f47f aece bne.w 8004b94 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8004df8: 687b ldr r3, [r7, #4] 8004dfa: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8004dfe: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8004e02: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8004e06: 2b00 cmp r3, #0 8004e08: d049 beq.n 8004e9e 8004e0a: 687b ldr r3, [r7, #4] 8004e0c: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8004e10: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8004e14: 429a cmp r2, r3 8004e16: d242 bcs.n 8004e9e { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8004e18: 687b ldr r3, [r7, #4] 8004e1a: 681b ldr r3, [r3, #0] 8004e1c: 3308 adds r3, #8 8004e1e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004e20: 6a3b ldr r3, [r7, #32] 8004e22: e853 3f00 ldrex r3, [r3] 8004e26: 61fb str r3, [r7, #28] return(result); 8004e28: 69fb ldr r3, [r7, #28] 8004e2a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8004e2e: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8004e32: 687b ldr r3, [r7, #4] 8004e34: 681b ldr r3, [r3, #0] 8004e36: 3308 adds r3, #8 8004e38: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8004e3c: 62fa str r2, [r7, #44] @ 0x2c 8004e3e: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004e40: 6ab9 ldr r1, [r7, #40] @ 0x28 8004e42: 6afa ldr r2, [r7, #44] @ 0x2c 8004e44: e841 2300 strex r3, r2, [r1] 8004e48: 627b str r3, [r7, #36] @ 0x24 return(result); 8004e4a: 6a7b ldr r3, [r7, #36] @ 0x24 8004e4c: 2b00 cmp r3, #0 8004e4e: d1e3 bne.n 8004e18 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8004e50: 687b ldr r3, [r7, #4] 8004e52: 4a16 ldr r2, [pc, #88] @ (8004eac ) 8004e54: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8004e56: 687b ldr r3, [r7, #4] 8004e58: 681b ldr r3, [r3, #0] 8004e5a: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004e5c: 68fb ldr r3, [r7, #12] 8004e5e: e853 3f00 ldrex r3, [r3] 8004e62: 60bb str r3, [r7, #8] return(result); 8004e64: 68bb ldr r3, [r7, #8] 8004e66: f043 0320 orr.w r3, r3, #32 8004e6a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8004e6e: 687b ldr r3, [r7, #4] 8004e70: 681b ldr r3, [r3, #0] 8004e72: 461a mov r2, r3 8004e74: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8004e78: 61bb str r3, [r7, #24] 8004e7a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004e7c: 6979 ldr r1, [r7, #20] 8004e7e: 69ba ldr r2, [r7, #24] 8004e80: e841 2300 strex r3, r2, [r1] 8004e84: 613b str r3, [r7, #16] return(result); 8004e86: 693b ldr r3, [r7, #16] 8004e88: 2b00 cmp r3, #0 8004e8a: d1e4 bne.n 8004e56 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8004e8c: e007 b.n 8004e9e __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8004e8e: 687b ldr r3, [r7, #4] 8004e90: 681b ldr r3, [r3, #0] 8004e92: 699a ldr r2, [r3, #24] 8004e94: 687b ldr r3, [r7, #4] 8004e96: 681b ldr r3, [r3, #0] 8004e98: f042 0208 orr.w r2, r2, #8 8004e9c: 619a str r2, [r3, #24] } 8004e9e: bf00 nop 8004ea0: 37b0 adds r7, #176 @ 0xb0 8004ea2: 46bd mov sp, r7 8004ea4: bd80 pop {r7, pc} 8004ea6: bf00 nop 8004ea8: 40008000 .word 0x40008000 8004eac: 080047dd .word 0x080047dd 08004eb0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8004eb0: b580 push {r7, lr} 8004eb2: b0ae sub sp, #184 @ 0xb8 8004eb4: af00 add r7, sp, #0 8004eb6: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8004eb8: 687b ldr r3, [r7, #4] 8004eba: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8004ebe: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8004ec2: 687b ldr r3, [r7, #4] 8004ec4: 681b ldr r3, [r3, #0] 8004ec6: 69db ldr r3, [r3, #28] 8004ec8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8004ecc: 687b ldr r3, [r7, #4] 8004ece: 681b ldr r3, [r3, #0] 8004ed0: 681b ldr r3, [r3, #0] 8004ed2: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 8004ed6: 687b ldr r3, [r7, #4] 8004ed8: 681b ldr r3, [r3, #0] 8004eda: 689b ldr r3, [r3, #8] 8004edc: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8004ee0: 687b ldr r3, [r7, #4] 8004ee2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004ee6: 2b22 cmp r3, #34 @ 0x22 8004ee8: f040 8187 bne.w 80051fa { nb_rx_data = huart->NbRxDataToProcess; 8004eec: 687b ldr r3, [r7, #4] 8004eee: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8004ef2: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8004ef6: e12a b.n 800514e { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8004ef8: 687b ldr r3, [r7, #4] 8004efa: 681b ldr r3, [r3, #0] 8004efc: 6a5b ldr r3, [r3, #36] @ 0x24 8004efe: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8004f02: 687b ldr r3, [r7, #4] 8004f04: 6d9b ldr r3, [r3, #88] @ 0x58 8004f06: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8004f0a: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8004f0e: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8004f12: 4013 ands r3, r2 8004f14: b29a uxth r2, r3 8004f16: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8004f1a: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8004f1c: 687b ldr r3, [r7, #4] 8004f1e: 6d9b ldr r3, [r3, #88] @ 0x58 8004f20: 1c9a adds r2, r3, #2 8004f22: 687b ldr r3, [r7, #4] 8004f24: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8004f26: 687b ldr r3, [r7, #4] 8004f28: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8004f2c: b29b uxth r3, r3 8004f2e: 3b01 subs r3, #1 8004f30: b29a uxth r2, r3 8004f32: 687b ldr r3, [r7, #4] 8004f34: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8004f38: 687b ldr r3, [r7, #4] 8004f3a: 681b ldr r3, [r3, #0] 8004f3c: 69db ldr r3, [r3, #28] 8004f3e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8004f42: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8004f46: f003 0307 and.w r3, r3, #7 8004f4a: 2b00 cmp r3, #0 8004f4c: d053 beq.n 8004ff6 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8004f4e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8004f52: f003 0301 and.w r3, r3, #1 8004f56: 2b00 cmp r3, #0 8004f58: d011 beq.n 8004f7e 8004f5a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8004f5e: f403 7380 and.w r3, r3, #256 @ 0x100 8004f62: 2b00 cmp r3, #0 8004f64: d00b beq.n 8004f7e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8004f66: 687b ldr r3, [r7, #4] 8004f68: 681b ldr r3, [r3, #0] 8004f6a: 2201 movs r2, #1 8004f6c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8004f6e: 687b ldr r3, [r7, #4] 8004f70: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004f74: f043 0201 orr.w r2, r3, #1 8004f78: 687b ldr r3, [r7, #4] 8004f7a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004f7e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8004f82: f003 0302 and.w r3, r3, #2 8004f86: 2b00 cmp r3, #0 8004f88: d011 beq.n 8004fae 8004f8a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004f8e: f003 0301 and.w r3, r3, #1 8004f92: 2b00 cmp r3, #0 8004f94: d00b beq.n 8004fae { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8004f96: 687b ldr r3, [r7, #4] 8004f98: 681b ldr r3, [r3, #0] 8004f9a: 2202 movs r2, #2 8004f9c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8004f9e: 687b ldr r3, [r7, #4] 8004fa0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004fa4: f043 0204 orr.w r2, r3, #4 8004fa8: 687b ldr r3, [r7, #4] 8004faa: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004fae: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8004fb2: f003 0304 and.w r3, r3, #4 8004fb6: 2b00 cmp r3, #0 8004fb8: d011 beq.n 8004fde 8004fba: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8004fbe: f003 0301 and.w r3, r3, #1 8004fc2: 2b00 cmp r3, #0 8004fc4: d00b beq.n 8004fde { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8004fc6: 687b ldr r3, [r7, #4] 8004fc8: 681b ldr r3, [r3, #0] 8004fca: 2204 movs r2, #4 8004fcc: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8004fce: 687b ldr r3, [r7, #4] 8004fd0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004fd4: f043 0202 orr.w r2, r3, #2 8004fd8: 687b ldr r3, [r7, #4] 8004fda: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8004fde: 687b ldr r3, [r7, #4] 8004fe0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004fe4: 2b00 cmp r3, #0 8004fe6: d006 beq.n 8004ff6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004fe8: 6878 ldr r0, [r7, #4] 8004fea: f7fe fd99 bl 8003b20 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004fee: 687b ldr r3, [r7, #4] 8004ff0: 2200 movs r2, #0 8004ff2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8004ff6: 687b ldr r3, [r7, #4] 8004ff8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8004ffc: b29b uxth r3, r3 8004ffe: 2b00 cmp r3, #0 8005000: f040 80a5 bne.w 800514e { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005004: 687b ldr r3, [r7, #4] 8005006: 681b ldr r3, [r3, #0] 8005008: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800500a: 6f7b ldr r3, [r7, #116] @ 0x74 800500c: e853 3f00 ldrex r3, [r3] 8005010: 673b str r3, [r7, #112] @ 0x70 return(result); 8005012: 6f3b ldr r3, [r7, #112] @ 0x70 8005014: f423 7380 bic.w r3, r3, #256 @ 0x100 8005018: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800501c: 687b ldr r3, [r7, #4] 800501e: 681b ldr r3, [r3, #0] 8005020: 461a mov r2, r3 8005022: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8005026: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800502a: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800502c: 6ff9 ldr r1, [r7, #124] @ 0x7c 800502e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8005032: e841 2300 strex r3, r2, [r1] 8005036: 67bb str r3, [r7, #120] @ 0x78 return(result); 8005038: 6fbb ldr r3, [r7, #120] @ 0x78 800503a: 2b00 cmp r3, #0 800503c: d1e2 bne.n 8005004 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800503e: 687b ldr r3, [r7, #4] 8005040: 681b ldr r3, [r3, #0] 8005042: 3308 adds r3, #8 8005044: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005046: 6e3b ldr r3, [r7, #96] @ 0x60 8005048: e853 3f00 ldrex r3, [r3] 800504c: 65fb str r3, [r7, #92] @ 0x5c return(result); 800504e: 6dfb ldr r3, [r7, #92] @ 0x5c 8005050: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005054: f023 0301 bic.w r3, r3, #1 8005058: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800505c: 687b ldr r3, [r7, #4] 800505e: 681b ldr r3, [r3, #0] 8005060: 3308 adds r3, #8 8005062: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8005066: 66fa str r2, [r7, #108] @ 0x6c 8005068: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800506a: 6eb9 ldr r1, [r7, #104] @ 0x68 800506c: 6efa ldr r2, [r7, #108] @ 0x6c 800506e: e841 2300 strex r3, r2, [r1] 8005072: 667b str r3, [r7, #100] @ 0x64 return(result); 8005074: 6e7b ldr r3, [r7, #100] @ 0x64 8005076: 2b00 cmp r3, #0 8005078: d1e1 bne.n 800503e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800507a: 687b ldr r3, [r7, #4] 800507c: 2220 movs r2, #32 800507e: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8005082: 687b ldr r3, [r7, #4] 8005084: 2200 movs r2, #0 8005086: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8005088: 687b ldr r3, [r7, #4] 800508a: 2200 movs r2, #0 800508c: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800508e: 687b ldr r3, [r7, #4] 8005090: 681b ldr r3, [r3, #0] 8005092: 4a60 ldr r2, [pc, #384] @ (8005214 ) 8005094: 4293 cmp r3, r2 8005096: d021 beq.n 80050dc { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8005098: 687b ldr r3, [r7, #4] 800509a: 681b ldr r3, [r3, #0] 800509c: 685b ldr r3, [r3, #4] 800509e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80050a2: 2b00 cmp r3, #0 80050a4: d01a beq.n 80050dc { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80050a6: 687b ldr r3, [r7, #4] 80050a8: 681b ldr r3, [r3, #0] 80050aa: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80050ac: 6cfb ldr r3, [r7, #76] @ 0x4c 80050ae: e853 3f00 ldrex r3, [r3] 80050b2: 64bb str r3, [r7, #72] @ 0x48 return(result); 80050b4: 6cbb ldr r3, [r7, #72] @ 0x48 80050b6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80050ba: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80050be: 687b ldr r3, [r7, #4] 80050c0: 681b ldr r3, [r3, #0] 80050c2: 461a mov r2, r3 80050c4: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 80050c8: 65bb str r3, [r7, #88] @ 0x58 80050ca: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80050cc: 6d79 ldr r1, [r7, #84] @ 0x54 80050ce: 6dba ldr r2, [r7, #88] @ 0x58 80050d0: e841 2300 strex r3, r2, [r1] 80050d4: 653b str r3, [r7, #80] @ 0x50 return(result); 80050d6: 6d3b ldr r3, [r7, #80] @ 0x50 80050d8: 2b00 cmp r3, #0 80050da: d1e4 bne.n 80050a6 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80050dc: 687b ldr r3, [r7, #4] 80050de: 6edb ldr r3, [r3, #108] @ 0x6c 80050e0: 2b01 cmp r3, #1 80050e2: d130 bne.n 8005146 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80050e4: 687b ldr r3, [r7, #4] 80050e6: 2200 movs r2, #0 80050e8: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80050ea: 687b ldr r3, [r7, #4] 80050ec: 681b ldr r3, [r3, #0] 80050ee: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80050f0: 6bbb ldr r3, [r7, #56] @ 0x38 80050f2: e853 3f00 ldrex r3, [r3] 80050f6: 637b str r3, [r7, #52] @ 0x34 return(result); 80050f8: 6b7b ldr r3, [r7, #52] @ 0x34 80050fa: f023 0310 bic.w r3, r3, #16 80050fe: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8005102: 687b ldr r3, [r7, #4] 8005104: 681b ldr r3, [r3, #0] 8005106: 461a mov r2, r3 8005108: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800510c: 647b str r3, [r7, #68] @ 0x44 800510e: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005110: 6c39 ldr r1, [r7, #64] @ 0x40 8005112: 6c7a ldr r2, [r7, #68] @ 0x44 8005114: e841 2300 strex r3, r2, [r1] 8005118: 63fb str r3, [r7, #60] @ 0x3c return(result); 800511a: 6bfb ldr r3, [r7, #60] @ 0x3c 800511c: 2b00 cmp r3, #0 800511e: d1e4 bne.n 80050ea if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8005120: 687b ldr r3, [r7, #4] 8005122: 681b ldr r3, [r3, #0] 8005124: 69db ldr r3, [r3, #28] 8005126: f003 0310 and.w r3, r3, #16 800512a: 2b10 cmp r3, #16 800512c: d103 bne.n 8005136 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800512e: 687b ldr r3, [r7, #4] 8005130: 681b ldr r3, [r3, #0] 8005132: 2210 movs r2, #16 8005134: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8005136: 687b ldr r3, [r7, #4] 8005138: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800513c: 4619 mov r1, r3 800513e: 6878 ldr r0, [r7, #4] 8005140: f7fe fcf8 bl 8003b34 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; 8005144: e00e b.n 8005164 HAL_UART_RxCpltCallback(huart); 8005146: 6878 ldr r0, [r7, #4] 8005148: f7fb fe82 bl 8000e50 break; 800514c: e00a b.n 8005164 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800514e: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8005152: 2b00 cmp r3, #0 8005154: d006 beq.n 8005164 8005156: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800515a: f003 0320 and.w r3, r3, #32 800515e: 2b00 cmp r3, #0 8005160: f47f aeca bne.w 8004ef8 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8005164: 687b ldr r3, [r7, #4] 8005166: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800516a: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800516e: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8005172: 2b00 cmp r3, #0 8005174: d049 beq.n 800520a 8005176: 687b ldr r3, [r7, #4] 8005178: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800517c: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8005180: 429a cmp r2, r3 8005182: d242 bcs.n 800520a { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8005184: 687b ldr r3, [r7, #4] 8005186: 681b ldr r3, [r3, #0] 8005188: 3308 adds r3, #8 800518a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800518c: 6a7b ldr r3, [r7, #36] @ 0x24 800518e: e853 3f00 ldrex r3, [r3] 8005192: 623b str r3, [r7, #32] return(result); 8005194: 6a3b ldr r3, [r7, #32] 8005196: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800519a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800519e: 687b ldr r3, [r7, #4] 80051a0: 681b ldr r3, [r3, #0] 80051a2: 3308 adds r3, #8 80051a4: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 80051a8: 633a str r2, [r7, #48] @ 0x30 80051aa: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80051ac: 6af9 ldr r1, [r7, #44] @ 0x2c 80051ae: 6b3a ldr r2, [r7, #48] @ 0x30 80051b0: e841 2300 strex r3, r2, [r1] 80051b4: 62bb str r3, [r7, #40] @ 0x28 return(result); 80051b6: 6abb ldr r3, [r7, #40] @ 0x28 80051b8: 2b00 cmp r3, #0 80051ba: d1e3 bne.n 8005184 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 80051bc: 687b ldr r3, [r7, #4] 80051be: 4a16 ldr r2, [pc, #88] @ (8005218 ) 80051c0: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 80051c2: 687b ldr r3, [r7, #4] 80051c4: 681b ldr r3, [r3, #0] 80051c6: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80051c8: 693b ldr r3, [r7, #16] 80051ca: e853 3f00 ldrex r3, [r3] 80051ce: 60fb str r3, [r7, #12] return(result); 80051d0: 68fb ldr r3, [r7, #12] 80051d2: f043 0320 orr.w r3, r3, #32 80051d6: f8c7 3084 str.w r3, [r7, #132] @ 0x84 80051da: 687b ldr r3, [r7, #4] 80051dc: 681b ldr r3, [r3, #0] 80051de: 461a mov r2, r3 80051e0: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80051e4: 61fb str r3, [r7, #28] 80051e6: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80051e8: 69b9 ldr r1, [r7, #24] 80051ea: 69fa ldr r2, [r7, #28] 80051ec: e841 2300 strex r3, r2, [r1] 80051f0: 617b str r3, [r7, #20] return(result); 80051f2: 697b ldr r3, [r7, #20] 80051f4: 2b00 cmp r3, #0 80051f6: d1e4 bne.n 80051c2 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80051f8: e007 b.n 800520a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80051fa: 687b ldr r3, [r7, #4] 80051fc: 681b ldr r3, [r3, #0] 80051fe: 699a ldr r2, [r3, #24] 8005200: 687b ldr r3, [r7, #4] 8005202: 681b ldr r3, [r3, #0] 8005204: f042 0208 orr.w r2, r2, #8 8005208: 619a str r2, [r3, #24] } 800520a: bf00 nop 800520c: 37b8 adds r7, #184 @ 0xb8 800520e: 46bd mov sp, r7 8005210: bd80 pop {r7, pc} 8005212: bf00 nop 8005214: 40008000 .word 0x40008000 8005218: 08004995 .word 0x08004995 0800521c : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 800521c: b480 push {r7} 800521e: b083 sub sp, #12 8005220: af00 add r7, sp, #0 8005222: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8005224: bf00 nop 8005226: 370c adds r7, #12 8005228: 46bd mov sp, r7 800522a: f85d 7b04 ldr.w r7, [sp], #4 800522e: 4770 bx lr 08005230 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8005230: b480 push {r7} 8005232: b083 sub sp, #12 8005234: af00 add r7, sp, #0 8005236: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8005238: bf00 nop 800523a: 370c adds r7, #12 800523c: 46bd mov sp, r7 800523e: f85d 7b04 ldr.w r7, [sp], #4 8005242: 4770 bx lr 08005244 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8005244: b480 push {r7} 8005246: b083 sub sp, #12 8005248: af00 add r7, sp, #0 800524a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 800524c: bf00 nop 800524e: 370c adds r7, #12 8005250: 46bd mov sp, r7 8005252: f85d 7b04 ldr.w r7, [sp], #4 8005256: 4770 bx lr 08005258 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8005258: b480 push {r7} 800525a: b085 sub sp, #20 800525c: af00 add r7, sp, #0 800525e: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8005260: 687b ldr r3, [r7, #4] 8005262: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8005266: 2b01 cmp r3, #1 8005268: d101 bne.n 800526e 800526a: 2302 movs r3, #2 800526c: e027 b.n 80052be 800526e: 687b ldr r3, [r7, #4] 8005270: 2201 movs r2, #1 8005272: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8005276: 687b ldr r3, [r7, #4] 8005278: 2224 movs r2, #36 @ 0x24 800527a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800527e: 687b ldr r3, [r7, #4] 8005280: 681b ldr r3, [r3, #0] 8005282: 681b ldr r3, [r3, #0] 8005284: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8005286: 687b ldr r3, [r7, #4] 8005288: 681b ldr r3, [r3, #0] 800528a: 681a ldr r2, [r3, #0] 800528c: 687b ldr r3, [r7, #4] 800528e: 681b ldr r3, [r3, #0] 8005290: f022 0201 bic.w r2, r2, #1 8005294: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8005296: 68fb ldr r3, [r7, #12] 8005298: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 800529c: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 800529e: 687b ldr r3, [r7, #4] 80052a0: 2200 movs r2, #0 80052a2: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80052a4: 687b ldr r3, [r7, #4] 80052a6: 681b ldr r3, [r3, #0] 80052a8: 68fa ldr r2, [r7, #12] 80052aa: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80052ac: 687b ldr r3, [r7, #4] 80052ae: 2220 movs r2, #32 80052b0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80052b4: 687b ldr r3, [r7, #4] 80052b6: 2200 movs r2, #0 80052b8: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80052bc: 2300 movs r3, #0 } 80052be: 4618 mov r0, r3 80052c0: 3714 adds r7, #20 80052c2: 46bd mov sp, r7 80052c4: f85d 7b04 ldr.w r7, [sp], #4 80052c8: 4770 bx lr 080052ca : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80052ca: b580 push {r7, lr} 80052cc: b084 sub sp, #16 80052ce: af00 add r7, sp, #0 80052d0: 6078 str r0, [r7, #4] 80052d2: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80052d4: 687b ldr r3, [r7, #4] 80052d6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80052da: 2b01 cmp r3, #1 80052dc: d101 bne.n 80052e2 80052de: 2302 movs r3, #2 80052e0: e02d b.n 800533e 80052e2: 687b ldr r3, [r7, #4] 80052e4: 2201 movs r2, #1 80052e6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80052ea: 687b ldr r3, [r7, #4] 80052ec: 2224 movs r2, #36 @ 0x24 80052ee: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80052f2: 687b ldr r3, [r7, #4] 80052f4: 681b ldr r3, [r3, #0] 80052f6: 681b ldr r3, [r3, #0] 80052f8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80052fa: 687b ldr r3, [r7, #4] 80052fc: 681b ldr r3, [r3, #0] 80052fe: 681a ldr r2, [r3, #0] 8005300: 687b ldr r3, [r7, #4] 8005302: 681b ldr r3, [r3, #0] 8005304: f022 0201 bic.w r2, r2, #1 8005308: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800530a: 687b ldr r3, [r7, #4] 800530c: 681b ldr r3, [r3, #0] 800530e: 689b ldr r3, [r3, #8] 8005310: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8005314: 687b ldr r3, [r7, #4] 8005316: 681b ldr r3, [r3, #0] 8005318: 683a ldr r2, [r7, #0] 800531a: 430a orrs r2, r1 800531c: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800531e: 6878 ldr r0, [r7, #4] 8005320: f000 f850 bl 80053c4 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8005324: 687b ldr r3, [r7, #4] 8005326: 681b ldr r3, [r3, #0] 8005328: 68fa ldr r2, [r7, #12] 800532a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800532c: 687b ldr r3, [r7, #4] 800532e: 2220 movs r2, #32 8005330: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8005334: 687b ldr r3, [r7, #4] 8005336: 2200 movs r2, #0 8005338: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800533c: 2300 movs r3, #0 } 800533e: 4618 mov r0, r3 8005340: 3710 adds r7, #16 8005342: 46bd mov sp, r7 8005344: bd80 pop {r7, pc} 08005346 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8005346: b580 push {r7, lr} 8005348: b084 sub sp, #16 800534a: af00 add r7, sp, #0 800534c: 6078 str r0, [r7, #4] 800534e: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8005350: 687b ldr r3, [r7, #4] 8005352: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8005356: 2b01 cmp r3, #1 8005358: d101 bne.n 800535e 800535a: 2302 movs r3, #2 800535c: e02d b.n 80053ba 800535e: 687b ldr r3, [r7, #4] 8005360: 2201 movs r2, #1 8005362: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8005366: 687b ldr r3, [r7, #4] 8005368: 2224 movs r2, #36 @ 0x24 800536a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800536e: 687b ldr r3, [r7, #4] 8005370: 681b ldr r3, [r3, #0] 8005372: 681b ldr r3, [r3, #0] 8005374: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8005376: 687b ldr r3, [r7, #4] 8005378: 681b ldr r3, [r3, #0] 800537a: 681a ldr r2, [r3, #0] 800537c: 687b ldr r3, [r7, #4] 800537e: 681b ldr r3, [r3, #0] 8005380: f022 0201 bic.w r2, r2, #1 8005384: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8005386: 687b ldr r3, [r7, #4] 8005388: 681b ldr r3, [r3, #0] 800538a: 689b ldr r3, [r3, #8] 800538c: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8005390: 687b ldr r3, [r7, #4] 8005392: 681b ldr r3, [r3, #0] 8005394: 683a ldr r2, [r7, #0] 8005396: 430a orrs r2, r1 8005398: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800539a: 6878 ldr r0, [r7, #4] 800539c: f000 f812 bl 80053c4 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80053a0: 687b ldr r3, [r7, #4] 80053a2: 681b ldr r3, [r3, #0] 80053a4: 68fa ldr r2, [r7, #12] 80053a6: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80053a8: 687b ldr r3, [r7, #4] 80053aa: 2220 movs r2, #32 80053ac: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 80053b0: 687b ldr r3, [r7, #4] 80053b2: 2200 movs r2, #0 80053b4: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80053b8: 2300 movs r3, #0 } 80053ba: 4618 mov r0, r3 80053bc: 3710 adds r7, #16 80053be: 46bd mov sp, r7 80053c0: bd80 pop {r7, pc} ... 080053c4 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80053c4: b480 push {r7} 80053c6: b085 sub sp, #20 80053c8: af00 add r7, sp, #0 80053ca: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80053cc: 687b ldr r3, [r7, #4] 80053ce: 6e5b ldr r3, [r3, #100] @ 0x64 80053d0: 2b00 cmp r3, #0 80053d2: d108 bne.n 80053e6 { huart->NbTxDataToProcess = 1U; 80053d4: 687b ldr r3, [r7, #4] 80053d6: 2201 movs r2, #1 80053d8: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 80053dc: 687b ldr r3, [r7, #4] 80053de: 2201 movs r2, #1 80053e0: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 80053e4: e031 b.n 800544a rx_fifo_depth = RX_FIFO_DEPTH; 80053e6: 2308 movs r3, #8 80053e8: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 80053ea: 2308 movs r3, #8 80053ec: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 80053ee: 687b ldr r3, [r7, #4] 80053f0: 681b ldr r3, [r3, #0] 80053f2: 689b ldr r3, [r3, #8] 80053f4: 0e5b lsrs r3, r3, #25 80053f6: b2db uxtb r3, r3 80053f8: f003 0307 and.w r3, r3, #7 80053fc: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 80053fe: 687b ldr r3, [r7, #4] 8005400: 681b ldr r3, [r3, #0] 8005402: 689b ldr r3, [r3, #8] 8005404: 0f5b lsrs r3, r3, #29 8005406: b2db uxtb r3, r3 8005408: f003 0307 and.w r3, r3, #7 800540c: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800540e: 7bbb ldrb r3, [r7, #14] 8005410: 7b3a ldrb r2, [r7, #12] 8005412: 4911 ldr r1, [pc, #68] @ (8005458 ) 8005414: 5c8a ldrb r2, [r1, r2] 8005416: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800541a: 7b3a ldrb r2, [r7, #12] 800541c: 490f ldr r1, [pc, #60] @ (800545c ) 800541e: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8005420: fb93 f3f2 sdiv r3, r3, r2 8005424: b29a uxth r2, r3 8005426: 687b ldr r3, [r7, #4] 8005428: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800542c: 7bfb ldrb r3, [r7, #15] 800542e: 7b7a ldrb r2, [r7, #13] 8005430: 4909 ldr r1, [pc, #36] @ (8005458 ) 8005432: 5c8a ldrb r2, [r1, r2] 8005434: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8005438: 7b7a ldrb r2, [r7, #13] 800543a: 4908 ldr r1, [pc, #32] @ (800545c ) 800543c: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800543e: fb93 f3f2 sdiv r3, r3, r2 8005442: b29a uxth r2, r3 8005444: 687b ldr r3, [r7, #4] 8005446: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 800544a: bf00 nop 800544c: 3714 adds r7, #20 800544e: 46bd mov sp, r7 8005450: f85d 7b04 ldr.w r7, [sp], #4 8005454: 4770 bx lr 8005456: bf00 nop 8005458: 080057c8 .word 0x080057c8 800545c: 080057d0 .word 0x080057d0 08005460 : 8005460: 4402 add r2, r0 8005462: 4603 mov r3, r0 8005464: 4293 cmp r3, r2 8005466: d100 bne.n 800546a 8005468: 4770 bx lr 800546a: f803 1b01 strb.w r1, [r3], #1 800546e: e7f9 b.n 8005464 08005470 <__libc_init_array>: 8005470: b570 push {r4, r5, r6, lr} 8005472: 4b0d ldr r3, [pc, #52] @ (80054a8 <__libc_init_array+0x38>) 8005474: 4d0d ldr r5, [pc, #52] @ (80054ac <__libc_init_array+0x3c>) 8005476: 1b5b subs r3, r3, r5 8005478: 109c asrs r4, r3, #2 800547a: 2600 movs r6, #0 800547c: 42a6 cmp r6, r4 800547e: d109 bne.n 8005494 <__libc_init_array+0x24> 8005480: f000 f828 bl 80054d4 <_init> 8005484: 4d0a ldr r5, [pc, #40] @ (80054b0 <__libc_init_array+0x40>) 8005486: 4b0b ldr r3, [pc, #44] @ (80054b4 <__libc_init_array+0x44>) 8005488: 1b5b subs r3, r3, r5 800548a: 109c asrs r4, r3, #2 800548c: 2600 movs r6, #0 800548e: 42a6 cmp r6, r4 8005490: d105 bne.n 800549e <__libc_init_array+0x2e> 8005492: bd70 pop {r4, r5, r6, pc} 8005494: f855 3b04 ldr.w r3, [r5], #4 8005498: 4798 blx r3 800549a: 3601 adds r6, #1 800549c: e7ee b.n 800547c <__libc_init_array+0xc> 800549e: f855 3b04 ldr.w r3, [r5], #4 80054a2: 4798 blx r3 80054a4: 3601 adds r6, #1 80054a6: e7f2 b.n 800548e <__libc_init_array+0x1e> 80054a8: 080057e0 .word 0x080057e0 80054ac: 080057e0 .word 0x080057e0 80054b0: 080057e0 .word 0x080057e0 80054b4: 080057e4 .word 0x080057e4 080054b8 : 80054b8: 440a add r2, r1 80054ba: 4291 cmp r1, r2 80054bc: f100 33ff add.w r3, r0, #4294967295 80054c0: d100 bne.n 80054c4 80054c2: 4770 bx lr 80054c4: b510 push {r4, lr} 80054c6: f811 4b01 ldrb.w r4, [r1], #1 80054ca: f803 4f01 strb.w r4, [r3, #1]! 80054ce: 4291 cmp r1, r2 80054d0: d1f9 bne.n 80054c6 80054d2: bd10 pop {r4, pc} 080054d4 <_init>: 80054d4: b5f8 push {r3, r4, r5, r6, r7, lr} 80054d6: bf00 nop 80054d8: bcf8 pop {r3, r4, r5, r6, r7} 80054da: bc08 pop {r3} 80054dc: 469e mov lr, r3 80054de: 4770 bx lr 080054e0 <_fini>: 80054e0: b5f8 push {r3, r4, r5, r6, r7, lr} 80054e2: bf00 nop 80054e4: bcf8 pop {r3, r4, r5, r6, r7} 80054e6: bc08 pop {r3} 80054e8: 469e mov lr, r3 80054ea: 4770 bx lr