--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=10 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF" --VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END -- Copyright (C) 2025 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and any partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, the Altera Quartus Prime License Agreement, -- the Altera IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Altera and sold by Altera or its authorized distributors. Please -- refer to the Altera Software License Subscription Agreements -- on the Quartus Prime software download page. FUNCTION sign_div_unsign_7nh (denominator[9..0], numerator[15..0]) RETURNS ( quotient[15..0], remainder[9..0]); --synthesis_resources = lut 132 SUBDESIGN lpm_divide_fkm ( denom[9..0] : input; numer[15..0] : input; quotient[15..0] : output; remain[9..0] : output; ) VARIABLE divider : sign_div_unsign_7nh; numer_tmp[15..0] : WIRE; BEGIN divider.denominator[] = denom[]; divider.numerator[] = numer_tmp[]; numer_tmp[] = numer[]; quotient[] = divider.quotient[]; remain[] = divider.remainder[]; END; --VALID FILE