diff --git a/.gitignore b/.gitignore
index 017cd1e..ea9f189 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,11 +12,20 @@ logging/
*.summary
*.pin
-# Quartus compilation phase outputs
+# Quartus compilation phase outputs (wildcards + explicit compound forms)
*.fit.*
*.map.*
*.sta.*
*.asm.*
+*.flow.rpt
+*.asm.rpt
+*.fit.rpt
+*.fit.smsg
+*.fit.summary
+*.map.rpt
+*.map.summary
+*.sta.rpt
+*.sta.summary
# Compiled database files
*.qdb
@@ -27,7 +36,8 @@ logging/
*.vho
*.vwo
-# Programmer files (keep .sof)
+# Programmer and bitstream files
+*.sof
*.pof
*.rbf
*.rpd
@@ -41,6 +51,12 @@ logging/
*.vcd
*.wlf
+# Quartus JTAG / SignalTap / device info
+*.jdi
+*.jditmp
+*.sld
+*.done
+
# Quartus workspace
*.qws
diff --git a/db/.cmp.kpt b/db/.cmp.kpt
deleted file mode 100644
index ab9f0de..0000000
Binary files a/db/.cmp.kpt and /dev/null differ
diff --git a/db/add_sub_7pc.tdf b/db/add_sub_7pc.tdf
deleted file mode 100644
index 903fa7a..0000000
--- a/db/add_sub_7pc.tdf
+++ /dev/null
@@ -1,44 +0,0 @@
---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=1 cout dataa datab result
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-
---synthesis_resources =
-SUBDESIGN add_sub_7pc
-(
- cout : output;
- dataa[0..0] : input;
- datab[0..0] : input;
- result[0..0] : output;
-)
-VARIABLE
- carry_eqn[0..0] : WIRE;
- cin_wire : WIRE;
- datab_node[0..0] : WIRE;
- sum_eqn[0..0] : WIRE;
-
-BEGIN
- carry_eqn[] = ( ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
- cin_wire = B"1";
- cout = carry_eqn[0..0];
- datab_node[] = (! datab[]);
- result[] = sum_eqn[];
- sum_eqn[] = ( ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
-END;
---VALID FILE
diff --git a/db/add_sub_8pc.tdf b/db/add_sub_8pc.tdf
deleted file mode 100644
index 1f1c31f..0000000
--- a/db/add_sub_8pc.tdf
+++ /dev/null
@@ -1,44 +0,0 @@
---lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-
---synthesis_resources =
-SUBDESIGN add_sub_8pc
-(
- cout : output;
- dataa[1..0] : input;
- datab[1..0] : input;
- result[1..0] : output;
-)
-VARIABLE
- carry_eqn[1..0] : WIRE;
- cin_wire : WIRE;
- datab_node[1..0] : WIRE;
- sum_eqn[1..0] : WIRE;
-
-BEGIN
- carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
- cin_wire = B"1";
- cout = carry_eqn[1..1];
- datab_node[] = (! datab[]);
- result[] = sum_eqn[];
- sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
-END;
---VALID FILE
diff --git a/db/alt_u_div_2af.tdf b/db/alt_u_div_2af.tdf
deleted file mode 100644
index ecbbf14..0000000
--- a/db/alt_u_div_2af.tdf
+++ /dev/null
@@ -1,212 +0,0 @@
---alt_u_div DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=10 WIDTH_N=16 WIDTH_Q=16 WIDTH_R=10 denominator numerator quotient remainder
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION add_sub_7pc (dataa[0..0], datab[0..0])
-RETURNS ( cout, result[0..0]);
-FUNCTION add_sub_8pc (dataa[1..0], datab[1..0])
-RETURNS ( cout, result[1..0]);
-
---synthesis_resources = lut 132
-SUBDESIGN alt_u_div_2af
-(
- denominator[9..0] : input;
- numerator[15..0] : input;
- quotient[15..0] : output;
- remainder[9..0] : output;
-)
-VARIABLE
- add_sub_0 : add_sub_7pc;
- add_sub_1 : add_sub_8pc;
- add_sub_10_result_int[11..0] : WIRE;
- add_sub_10_cout : WIRE;
- add_sub_10_dataa[10..0] : WIRE;
- add_sub_10_datab[10..0] : WIRE;
- add_sub_10_result[10..0] : WIRE;
- add_sub_11_result_int[11..0] : WIRE;
- add_sub_11_cout : WIRE;
- add_sub_11_dataa[10..0] : WIRE;
- add_sub_11_datab[10..0] : WIRE;
- add_sub_11_result[10..0] : WIRE;
- add_sub_12_result_int[11..0] : WIRE;
- add_sub_12_cout : WIRE;
- add_sub_12_dataa[10..0] : WIRE;
- add_sub_12_datab[10..0] : WIRE;
- add_sub_12_result[10..0] : WIRE;
- add_sub_13_result_int[11..0] : WIRE;
- add_sub_13_cout : WIRE;
- add_sub_13_dataa[10..0] : WIRE;
- add_sub_13_datab[10..0] : WIRE;
- add_sub_13_result[10..0] : WIRE;
- add_sub_14_result_int[11..0] : WIRE;
- add_sub_14_cout : WIRE;
- add_sub_14_dataa[10..0] : WIRE;
- add_sub_14_datab[10..0] : WIRE;
- add_sub_14_result[10..0] : WIRE;
- add_sub_15_result_int[11..0] : WIRE;
- add_sub_15_cout : WIRE;
- add_sub_15_dataa[10..0] : WIRE;
- add_sub_15_datab[10..0] : WIRE;
- add_sub_15_result[10..0] : WIRE;
- add_sub_2_result_int[3..0] : WIRE;
- add_sub_2_cout : WIRE;
- add_sub_2_dataa[2..0] : WIRE;
- add_sub_2_datab[2..0] : WIRE;
- add_sub_2_result[2..0] : WIRE;
- add_sub_3_result_int[4..0] : WIRE;
- add_sub_3_cout : WIRE;
- add_sub_3_dataa[3..0] : WIRE;
- add_sub_3_datab[3..0] : WIRE;
- add_sub_3_result[3..0] : WIRE;
- add_sub_4_result_int[5..0] : WIRE;
- add_sub_4_cout : WIRE;
- add_sub_4_dataa[4..0] : WIRE;
- add_sub_4_datab[4..0] : WIRE;
- add_sub_4_result[4..0] : WIRE;
- add_sub_5_result_int[6..0] : WIRE;
- add_sub_5_cout : WIRE;
- add_sub_5_dataa[5..0] : WIRE;
- add_sub_5_datab[5..0] : WIRE;
- add_sub_5_result[5..0] : WIRE;
- add_sub_6_result_int[7..0] : WIRE;
- add_sub_6_cout : WIRE;
- add_sub_6_dataa[6..0] : WIRE;
- add_sub_6_datab[6..0] : WIRE;
- add_sub_6_result[6..0] : WIRE;
- add_sub_7_result_int[8..0] : WIRE;
- add_sub_7_cout : WIRE;
- add_sub_7_dataa[7..0] : WIRE;
- add_sub_7_datab[7..0] : WIRE;
- add_sub_7_result[7..0] : WIRE;
- add_sub_8_result_int[9..0] : WIRE;
- add_sub_8_cout : WIRE;
- add_sub_8_dataa[8..0] : WIRE;
- add_sub_8_datab[8..0] : WIRE;
- add_sub_8_result[8..0] : WIRE;
- add_sub_9_result_int[10..0] : WIRE;
- add_sub_9_cout : WIRE;
- add_sub_9_dataa[9..0] : WIRE;
- add_sub_9_datab[9..0] : WIRE;
- add_sub_9_result[9..0] : WIRE;
- DenominatorIn[186..0] : WIRE;
- DenominatorIn_tmp[186..0] : WIRE;
- gnd_wire : WIRE;
- nose[271..0] : WIRE;
- NumeratorIn[271..0] : WIRE;
- NumeratorIn_tmp[271..0] : WIRE;
- prestg[175..0] : WIRE;
- quotient_tmp[15..0] : WIRE;
- sel[169..0] : WIRE;
- selnose[271..0] : WIRE;
- StageIn[186..0] : WIRE;
- StageIn_tmp[186..0] : WIRE;
- StageOut[175..0] : WIRE;
-
-BEGIN
- add_sub_0.dataa[0..0] = NumeratorIn[15..15];
- add_sub_0.datab[0..0] = DenominatorIn[0..0];
- add_sub_1.dataa[] = ( StageIn[11..11], NumeratorIn[30..30]);
- add_sub_1.datab[1..0] = DenominatorIn[12..11];
- add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
- add_sub_10_result[] = add_sub_10_result_int[10..0];
- add_sub_10_cout = !add_sub_10_result_int[11];
- add_sub_10_dataa[] = ( StageIn[119..110], NumeratorIn[165..165]);
- add_sub_10_datab[] = DenominatorIn[120..110];
- add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
- add_sub_11_result[] = add_sub_11_result_int[10..0];
- add_sub_11_cout = !add_sub_11_result_int[11];
- add_sub_11_dataa[] = ( StageIn[130..121], NumeratorIn[180..180]);
- add_sub_11_datab[] = DenominatorIn[131..121];
- add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
- add_sub_12_result[] = add_sub_12_result_int[10..0];
- add_sub_12_cout = !add_sub_12_result_int[11];
- add_sub_12_dataa[] = ( StageIn[141..132], NumeratorIn[195..195]);
- add_sub_12_datab[] = DenominatorIn[142..132];
- add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
- add_sub_13_result[] = add_sub_13_result_int[10..0];
- add_sub_13_cout = !add_sub_13_result_int[11];
- add_sub_13_dataa[] = ( StageIn[152..143], NumeratorIn[210..210]);
- add_sub_13_datab[] = DenominatorIn[153..143];
- add_sub_14_result_int[] = (0, add_sub_14_dataa[]) - (0, add_sub_14_datab[]);
- add_sub_14_result[] = add_sub_14_result_int[10..0];
- add_sub_14_cout = !add_sub_14_result_int[11];
- add_sub_14_dataa[] = ( StageIn[163..154], NumeratorIn[225..225]);
- add_sub_14_datab[] = DenominatorIn[164..154];
- add_sub_15_result_int[] = (0, add_sub_15_dataa[]) - (0, add_sub_15_datab[]);
- add_sub_15_result[] = add_sub_15_result_int[10..0];
- add_sub_15_cout = !add_sub_15_result_int[11];
- add_sub_15_dataa[] = ( StageIn[174..165], NumeratorIn[240..240]);
- add_sub_15_datab[] = DenominatorIn[175..165];
- add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
- add_sub_2_result[] = add_sub_2_result_int[2..0];
- add_sub_2_cout = !add_sub_2_result_int[3];
- add_sub_2_dataa[] = ( StageIn[23..22], NumeratorIn[45..45]);
- add_sub_2_datab[] = DenominatorIn[24..22];
- add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
- add_sub_3_result[] = add_sub_3_result_int[3..0];
- add_sub_3_cout = !add_sub_3_result_int[4];
- add_sub_3_dataa[] = ( StageIn[35..33], NumeratorIn[60..60]);
- add_sub_3_datab[] = DenominatorIn[36..33];
- add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
- add_sub_4_result[] = add_sub_4_result_int[4..0];
- add_sub_4_cout = !add_sub_4_result_int[5];
- add_sub_4_dataa[] = ( StageIn[47..44], NumeratorIn[75..75]);
- add_sub_4_datab[] = DenominatorIn[48..44];
- add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
- add_sub_5_result[] = add_sub_5_result_int[5..0];
- add_sub_5_cout = !add_sub_5_result_int[6];
- add_sub_5_dataa[] = ( StageIn[59..55], NumeratorIn[90..90]);
- add_sub_5_datab[] = DenominatorIn[60..55];
- add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
- add_sub_6_result[] = add_sub_6_result_int[6..0];
- add_sub_6_cout = !add_sub_6_result_int[7];
- add_sub_6_dataa[] = ( StageIn[71..66], NumeratorIn[105..105]);
- add_sub_6_datab[] = DenominatorIn[72..66];
- add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
- add_sub_7_result[] = add_sub_7_result_int[7..0];
- add_sub_7_cout = !add_sub_7_result_int[8];
- add_sub_7_dataa[] = ( StageIn[83..77], NumeratorIn[120..120]);
- add_sub_7_datab[] = DenominatorIn[84..77];
- add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]);
- add_sub_8_result[] = add_sub_8_result_int[8..0];
- add_sub_8_cout = !add_sub_8_result_int[9];
- add_sub_8_dataa[] = ( StageIn[95..88], NumeratorIn[135..135]);
- add_sub_8_datab[] = DenominatorIn[96..88];
- add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]);
- add_sub_9_result[] = add_sub_9_result_int[9..0];
- add_sub_9_cout = !add_sub_9_result_int[10];
- add_sub_9_dataa[] = ( StageIn[107..99], NumeratorIn[150..150]);
- add_sub_9_datab[] = DenominatorIn[108..99];
- DenominatorIn[] = DenominatorIn_tmp[];
- DenominatorIn_tmp[] = ( DenominatorIn[175..0], ( gnd_wire, denominator[]));
- gnd_wire = B"0";
- nose[] = ( B"0000000000000000", add_sub_15_cout, B"0000000000000000", add_sub_14_cout, B"0000000000000000", add_sub_13_cout, B"0000000000000000", add_sub_12_cout, B"0000000000000000", add_sub_11_cout, B"0000000000000000", add_sub_10_cout, B"0000000000000000", add_sub_9_cout, B"0000000000000000", add_sub_8_cout, B"0000000000000000", add_sub_7_cout, B"0000000000000000", add_sub_6_cout, B"0000000000000000", add_sub_5_cout, B"0000000000000000", add_sub_4_cout, B"0000000000000000", add_sub_3_cout, B"0000000000000000", add_sub_2_cout, B"0000000000000000", add_sub_1.cout, B"0000000000000000", add_sub_0.cout);
- NumeratorIn[] = NumeratorIn_tmp[];
- NumeratorIn_tmp[] = ( NumeratorIn[255..0], numerator[]);
- prestg[] = ( add_sub_15_result[], add_sub_14_result[], add_sub_13_result[], add_sub_12_result[], add_sub_11_result[], add_sub_10_result[], GND, add_sub_9_result[], B"00", add_sub_8_result[], B"000", add_sub_7_result[], B"0000", add_sub_6_result[], B"00000", add_sub_5_result[], B"000000", add_sub_4_result[], B"0000000", add_sub_3_result[], B"00000000", add_sub_2_result[], B"000000000", add_sub_1.result[], B"0000000000", add_sub_0.result[]);
- quotient[] = quotient_tmp[];
- quotient_tmp[] = ( (! selnose[0..0]), (! selnose[17..17]), (! selnose[34..34]), (! selnose[51..51]), (! selnose[68..68]), (! selnose[85..85]), (! selnose[102..102]), (! selnose[119..119]), (! selnose[136..136]), (! selnose[153..153]), (! selnose[170..170]), (! selnose[187..187]), (! selnose[204..204]), (! selnose[221..221]), (! selnose[238..238]), (! selnose[255..255]));
- remainder[9..0] = StageIn[185..176];
- sel[] = ( gnd_wire, (sel[169..169] # DenominatorIn[185..185]), (sel[168..168] # DenominatorIn[184..184]), (sel[167..167] # DenominatorIn[183..183]), (sel[166..166] # DenominatorIn[182..182]), (sel[165..165] # DenominatorIn[181..181]), (sel[164..164] # DenominatorIn[180..180]), (sel[163..163] # DenominatorIn[179..179]), (sel[162..162] # DenominatorIn[178..178]), (sel[161..161] # DenominatorIn[177..177]), gnd_wire, (sel[159..159] # DenominatorIn[174..174]), (sel[158..158] # DenominatorIn[173..173]), (sel[157..157] # DenominatorIn[172..172]), (sel[156..156] # DenominatorIn[171..171]), (sel[155..155] # DenominatorIn[170..170]), (sel[154..154] # DenominatorIn[169..169]), (sel[153..153] # DenominatorIn[168..168]), (sel[152..152] # DenominatorIn[167..167]), (sel[151..151] # DenominatorIn[166..166]), gnd_wire, (sel[149..149] # DenominatorIn[163..163]), (sel[148..148] # DenominatorIn[162..162]), (sel[147..147] # DenominatorIn[161..161]), (sel[146..146] # DenominatorIn[160..160]), (sel[145..145] # DenominatorIn[159..159]), (sel[144..144] # DenominatorIn[158..158]), (sel[143..143] # DenominatorIn[157..157]), (sel[142..142] # DenominatorIn[156..156]), (sel[141..141] # DenominatorIn[155..155]), gnd_wire, (sel[139..139] # DenominatorIn[152..152]), (sel[138..138] # DenominatorIn[151..151]), (sel[137..137] # DenominatorIn[150..150]), (sel[136..136] # DenominatorIn[149..149]), (sel[135..135] # DenominatorIn[148..148]), (sel[134..134] # DenominatorIn[147..147]), (sel[133..133] # DenominatorIn[146..146]), (sel[132..132] # DenominatorIn[145..145]), (sel[131..131] # DenominatorIn[144..144]), gnd_wire, (sel[129..129] # DenominatorIn[141..141]), (sel[128..128] # DenominatorIn[140..140]), (sel[127..127] # DenominatorIn[139..139]), (sel[126..126] # DenominatorIn[138..138]), (sel[125..125] # DenominatorIn[137..137]), (sel[124..124] # DenominatorIn[136..136]), (sel[123..123] # DenominatorIn[135..135]), (sel[122..122] # DenominatorIn[134..134]), (sel[121..121] # DenominatorIn[133..133]), gnd_wire, (sel[119..119] # DenominatorIn[130..130]), (sel[118..118] # DenominatorIn[129..129]), (sel[117..117] # DenominatorIn[128..128]), (sel[116..116] # DenominatorIn[127..127]), (sel[115..115] # DenominatorIn[126..126]), (sel[114..114] # DenominatorIn[125..125]), (sel[113..113] # DenominatorIn[124..124]), (sel[112..112] # DenominatorIn[123..123]), (sel[111..111] # DenominatorIn[122..122]), gnd_wire, (sel[109..109] # DenominatorIn[119..119]), (sel[108..108] # DenominatorIn[118..118]), (sel[107..107] # DenominatorIn[117..117]), (sel[106..106] # DenominatorIn[116..116]), (sel[105..105] # DenominatorIn[115..115]), (sel[104..104] # DenominatorIn[114..114]), (sel[103..103] # DenominatorIn[113..113]), (sel[102..102] # DenominatorIn[112..112]), (sel[101..101] # DenominatorIn[111..111]), gnd_wire, (sel[99..99] # DenominatorIn[108..108]), (sel[98..98] # DenominatorIn[107..107]), (sel[97..97] # DenominatorIn[106..106]), (sel[96..96] # DenominatorIn[105..105]), (sel[95..95] # DenominatorIn[104..104]), (sel[94..94] # DenominatorIn[103..103]), (sel[93..93] # DenominatorIn[102..102]), (sel[92..92] # DenominatorIn[101..101]), (sel[91..91] # DenominatorIn[100..100]), gnd_wire, (sel[89..89] # DenominatorIn[97..97]), (sel[88..88] # DenominatorIn[96..96]), (sel[87..87] # DenominatorIn[95..95]), (sel[86..86] # DenominatorIn[94..94]), (sel[85..85] # DenominatorIn[93..93]), (sel[84..84] # DenominatorIn[92..92]), (sel[83..83] # DenominatorIn[91..91]), (sel[82..82] # DenominatorIn[90..90]), (sel[81..81] # DenominatorIn[89..89]), gnd_wire, (sel[79..79] # DenominatorIn[86..86]), (sel[78..78] # DenominatorIn[85..85]), (sel[77..77] # DenominatorIn[84..84]), (sel[76..76] # DenominatorIn[83..83]), (sel[75..75] # DenominatorIn[82..82]), (sel[74..74] # DenominatorIn[81..81]), (sel[73..73] # DenominatorIn[80..80]), (sel[72..72] # DenominatorIn[79..79]), (sel[71..71] # DenominatorIn[78..78]), gnd_wire, (sel[69..69] # DenominatorIn[75..75]), (sel[68..68] # DenominatorIn[74..74]), (sel[67..67] # DenominatorIn[73..73]), (sel[66..66] # DenominatorIn[72..72]), (sel[65..65] # DenominatorIn[71..71]), (sel[64..64] # DenominatorIn[70..70]), (sel[63..63] # DenominatorIn[69..69]), (sel[62..62] # DenominatorIn[68..68]), (sel[61..61] # DenominatorIn[67..67]), gnd_wire, (sel[59..59] # DenominatorIn[64..64]), (sel[58..58] # DenominatorIn[63..63]), (sel[57..57] # DenominatorIn[62..62]), (sel[56..56] # DenominatorIn[61..61]), (sel[55..55] # DenominatorIn[60..60]), (sel[54..54] # DenominatorIn[59..59]), (sel[53..53] # DenominatorIn[58..58]), (sel[52..52] # DenominatorIn[57..57]), (sel[51..51] # DenominatorIn[56..56]), gnd_wire, (sel[49..49] # DenominatorIn[53..53]), (sel[48..48] # DenominatorIn[52..52]), (sel[47..47] # DenominatorIn[51..51]), (sel[46..46] # DenominatorIn[50..50]), (sel[45..45] # DenominatorIn[49..49]), (sel[44..44] # DenominatorIn[48..48]), (sel[43..43] # DenominatorIn[47..47]), (sel[42..42] # DenominatorIn[46..46]), (sel[41..41] # DenominatorIn[45..45]), gnd_wire, (sel[39..39] # DenominatorIn[42..42]), (sel[38..38] # DenominatorIn[41..41]), (sel[37..37] # DenominatorIn[40..40]), (sel[36..36] # DenominatorIn[39..39]), (sel[35..35] # DenominatorIn[38..38]), (sel[34..34] # DenominatorIn[37..37]), (sel[33..33] # DenominatorIn[36..36]), (sel[32..32] # DenominatorIn[35..35]), (sel[31..31] # DenominatorIn[34..34]), gnd_wire, (sel[29..29] # DenominatorIn[31..31]), (sel[28..28] # DenominatorIn[30..30]), (sel[27..27] # DenominatorIn[29..29]), (sel[26..26] # DenominatorIn[28..28]), (sel[25..25] # DenominatorIn[27..27]), (sel[24..24] # DenominatorIn[26..26]), (sel[23..23] # DenominatorIn[25..25]), (sel[22..22] # DenominatorIn[24..24]), (sel[21..21] # DenominatorIn[23..23]), gnd_wire, (sel[19..19] # DenominatorIn[20..20]), (sel[18..18] # DenominatorIn[19..19]), (sel[17..17] # DenominatorIn[18..18]), (sel[16..16] # DenominatorIn[17..17]), (sel[15..15] # DenominatorIn[16..16]), (sel[14..14] # DenominatorIn[15..15]), (sel[13..13] # DenominatorIn[14..14]), (sel[12..12] # DenominatorIn[13..13]), (sel[11..11] # DenominatorIn[12..12]), gnd_wire, (sel[9..9] # DenominatorIn[9..9]), (sel[8..8] # DenominatorIn[8..8]), (sel[7..7] # DenominatorIn[7..7]), (sel[6..6] # DenominatorIn[6..6]), (sel[5..5] # DenominatorIn[5..5]), (sel[4..4] # DenominatorIn[4..4]), (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
- selnose[] = ( (! nose[271..271]), (! nose[270..270]), (! nose[269..269]), (! nose[268..268]), (! nose[267..267]), (! nose[266..266]), ((! nose[265..265]) # sel[169..169]), ((! nose[264..264]) # sel[168..168]), ((! nose[263..263]) # sel[167..167]), ((! nose[262..262]) # sel[166..166]), ((! nose[261..261]) # sel[165..165]), ((! nose[260..260]) # sel[164..164]), ((! nose[259..259]) # sel[163..163]), ((! nose[258..258]) # sel[162..162]), ((! nose[257..257]) # sel[161..161]), ((! nose[256..256]) # sel[160..160]), (! nose[255..255]), (! nose[254..254]), (! nose[253..253]), (! nose[252..252]), (! nose[251..251]), (! nose[250..250]), ((! nose[249..249]) # sel[159..159]), ((! nose[248..248]) # sel[158..158]), ((! nose[247..247]) # sel[157..157]), ((! nose[246..246]) # sel[156..156]), ((! nose[245..245]) # sel[155..155]), ((! nose[244..244]) # sel[154..154]), ((! nose[243..243]) # sel[153..153]), ((! nose[242..242]) # sel[152..152]), ((! nose[241..241]) # sel[151..151]), ((! nose[240..240]) # sel[150..150]), (! nose[239..239]), (! nose[238..238]), (! nose[237..237]), (! nose[236..236]), (! nose[235..235]), (! nose[234..234]), ((! nose[233..233]) # sel[149..149]), ((! nose[232..232]) # sel[148..148]), ((! nose[231..231]) # sel[147..147]), ((! nose[230..230]) # sel[146..146]), ((! nose[229..229]) # sel[145..145]), ((! nose[228..228]) # sel[144..144]), ((! nose[227..227]) # sel[143..143]), ((! nose[226..226]) # sel[142..142]), ((! nose[225..225]) # sel[141..141]), ((! nose[224..224]) # sel[140..140]), (! nose[223..223]), (! nose[222..222]), (! nose[221..221]), (! nose[220..220]), (! nose[219..219]), (! nose[218..218]), ((! nose[217..217]) # sel[139..139]), ((! nose[216..216]) # sel[138..138]), ((! nose[215..215]) # sel[137..137]), ((! nose[214..214]) # sel[136..136]), ((! nose[213..213]) # sel[135..135]), ((! nose[212..212]) # sel[134..134]), ((! nose[211..211]) # sel[133..133]), ((! nose[210..210]) # sel[132..132]), ((! nose[209..209]) # sel[131..131]), ((! nose[208..208]) # sel[130..130]), (! nose[207..207]), (! nose[206..206]), (! nose[205..205]), (! nose[204..204]), (! nose[203..203]), (! nose[202..202]), ((! nose[201..201]) # sel[129..129]), ((! nose[200..200]) # sel[128..128]), ((! nose[199..199]) # sel[127..127]), ((! nose[198..198]) # sel[126..126]), ((! nose[197..197]) # sel[125..125]), ((! nose[196..196]) # sel[124..124]), ((! nose[195..195]) # sel[123..123]), ((! nose[194..194]) # sel[122..122]), ((! nose[193..193]) # sel[121..121]), ((! nose[192..192]) # sel[120..120]), (! nose[191..191]), (! nose[190..190]), (! nose[189..189]), (! nose[188..188]), (! nose[187..187]), (! nose[186..186]), ((! nose[185..185]) # sel[119..119]), ((! nose[184..184]) # sel[118..118]), ((! nose[183..183]) # sel[117..117]), ((! nose[182..182]) # sel[116..116]), ((! nose[181..181]) # sel[115..115]), ((! nose[180..180]) # sel[114..114]), ((! nose[179..179]) # sel[113..113]), ((! nose[178..178]) # sel[112..112]), ((! nose[177..177]) # sel[111..111]), ((! nose[176..176]) # sel[110..110]), (! nose[175..175]), (! nose[174..174]), (! nose[173..173]), (! nose[172..172]), (! nose[171..171]), (! nose[170..170]), ((! nose[169..169]) # sel[109..109]), ((! nose[168..168]) # sel[108..108]), ((! nose[167..167]) # sel[107..107]), ((! nose[166..166]) # sel[106..106]), ((! nose[165..165]) # sel[105..105]), ((! nose[164..164]) # sel[104..104]), ((! nose[163..163]) # sel[103..103]), ((! nose[162..162]) # sel[102..102]), ((! nose[161..161]) # sel[101..101]), ((! nose[160..160]) # sel[100..100]), (! nose[159..159]), (! nose[158..158]), (! nose[157..157]), (! nose[156..156]), (! nose[155..155]), (! nose[154..154]), ((! nose[153..153]) # sel[99..99]), ((! nose[152..152]) # sel[98..98]), ((! nose[151..151]) # sel[97..97]), ((! nose[150..150]) # sel[96..96]), ((! nose[149..149]) # sel[95..95]), ((! nose[148..148]) # sel[94..94]), ((! nose[147..147]) # sel[93..93]), ((! nose[146..146]) # sel[92..92]), ((! nose[145..145]) # sel[91..91]), ((! nose[144..144]) # sel[90..90]), (! nose[143..143]), (! nose[142..142]), (! nose[141..141]), (! nose[140..140]), (! nose[139..139]), (! nose[138..138]), ((! nose[137..137]) # sel[89..89]), ((! nose[136..136]) # sel[88..88]), ((! nose[135..135]) # sel[87..87]), ((! nose[134..134]) # sel[86..86]), ((! nose[133..133]) # sel[85..85]), ((! nose[132..132]) # sel[84..84]), ((! nose[131..131]) # sel[83..83]), ((! nose[130..130]) # sel[82..82]), ((! nose[129..129]) # sel[81..81]), ((! nose[128..128]) # sel[80..80]), (! nose[127..127]), (! nose[126..126]), (! nose[125..125]), (! nose[124..124]), (! nose[123..123]), (! nose[122..122]), ((! nose[121..121]) # sel[79..79]), ((! nose[120..120]) # sel[78..78]), ((! nose[119..119]) # sel[77..77]), ((! nose[118..118]) # sel[76..76]), ((! nose[117..117]) # sel[75..75]), ((! nose[116..116]) # sel[74..74]), ((! nose[115..115]) # sel[73..73]), ((! nose[114..114]) # sel[72..72]), ((! nose[113..113]) # sel[71..71]), ((! nose[112..112]) # sel[70..70]), (! nose[111..111]), (! nose[110..110]), (! nose[109..109]), (! nose[108..108]), (! nose[107..107]), (! nose[106..106]), ((! nose[105..105]) # sel[69..69]), ((! nose[104..104]) # sel[68..68]), ((! nose[103..103]) # sel[67..67]), ((! nose[102..102]) # sel[66..66]), ((! nose[101..101]) # sel[65..65]), ((! nose[100..100]) # sel[64..64]), ((! nose[99..99]) # sel[63..63]), ((! nose[98..98]) # sel[62..62]), ((! nose[97..97]) # sel[61..61]), ((! nose[96..96]) # sel[60..60]), (! nose[95..95]), (! nose[94..94]), (! nose[93..93]), (! nose[92..92]), (! nose[91..91]), (! nose[90..90]), ((! nose[89..89]) # sel[59..59]), ((! nose[88..88]) # sel[58..58]), ((! nose[87..87]) # sel[57..57]), ((! nose[86..86]) # sel[56..56]), ((! nose[85..85]) # sel[55..55]), ((! nose[84..84]) # sel[54..54]), ((! nose[83..83]) # sel[53..53]), ((! nose[82..82]) # sel[52..52]), ((! nose[81..81]) # sel[51..51]), ((! nose[80..80]) # sel[50..50]), (! nose[79..79]), (! nose[78..78]), (! nose[77..77]), (! nose[76..76]), (! nose[75..75]), (! nose[74..74]), ((! nose[73..73]) # sel[49..49]), ((! nose[72..72]) # sel[48..48]), ((! nose[71..71]) # sel[47..47]), ((! nose[70..70]) # sel[46..46]), ((! nose[69..69]) # sel[45..45]), ((! nose[68..68]) # sel[44..44]), ((! nose[67..67]) # sel[43..43]), ((! nose[66..66]) # sel[42..42]), ((! nose[65..65]) # sel[41..41]), ((! nose[64..64]) # sel[40..40]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), (! nose[59..59]), (! nose[58..58]), ((! nose[57..57]) # sel[39..39]), ((! nose[56..56]) # sel[38..38]), ((! nose[55..55]) # sel[37..37]), ((! nose[54..54]) # sel[36..36]), ((! nose[53..53]) # sel[35..35]), ((! nose[52..52]) # sel[34..34]), ((! nose[51..51]) # sel[33..33]), ((! nose[50..50]) # sel[32..32]), ((! nose[49..49]) # sel[31..31]), ((! nose[48..48]) # sel[30..30]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), (! nose[43..43]), (! nose[42..42]), ((! nose[41..41]) # sel[29..29]), ((! nose[40..40]) # sel[28..28]), ((! nose[39..39]) # sel[27..27]), ((! nose[38..38]) # sel[26..26]), ((! nose[37..37]) # sel[25..25]), ((! nose[36..36]) # sel[24..24]), ((! nose[35..35]) # sel[23..23]), ((! nose[34..34]) # sel[22..22]), ((! nose[33..33]) # sel[21..21]), ((! nose[32..32]) # sel[20..20]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), (! nose[27..27]), (! nose[26..26]), ((! nose[25..25]) # sel[19..19]), ((! nose[24..24]) # sel[18..18]), ((! nose[23..23]) # sel[17..17]), ((! nose[22..22]) # sel[16..16]), ((! nose[21..21]) # sel[15..15]), ((! nose[20..20]) # sel[14..14]), ((! nose[19..19]) # sel[13..13]), ((! nose[18..18]) # sel[12..12]), ((! nose[17..17]) # sel[11..11]), ((! nose[16..16]) # sel[10..10]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), (! nose[11..11]), (! nose[10..10]), ((! nose[9..9]) # sel[9..9]), ((! nose[8..8]) # sel[8..8]), ((! nose[7..7]) # sel[7..7]), ((! nose[6..6]) # sel[6..6]), ((! nose[5..5]) # sel[5..5]), ((! nose[4..4]) # sel[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
- StageIn[] = StageIn_tmp[];
- StageIn_tmp[] = ( StageOut[175..0], B"00000000000");
- StageOut[] = ( ((( StageIn[174..165], NumeratorIn[240..240]) & selnose[255..255]) # (prestg[175..165] & (! selnose[255..255]))), ((( StageIn[163..154], NumeratorIn[225..225]) & selnose[238..238]) # (prestg[164..154] & (! selnose[238..238]))), ((( StageIn[152..143], NumeratorIn[210..210]) & selnose[221..221]) # (prestg[153..143] & (! selnose[221..221]))), ((( StageIn[141..132], NumeratorIn[195..195]) & selnose[204..204]) # (prestg[142..132] & (! selnose[204..204]))), ((( StageIn[130..121], NumeratorIn[180..180]) & selnose[187..187]) # (prestg[131..121] & (! selnose[187..187]))), ((( StageIn[119..110], NumeratorIn[165..165]) & selnose[170..170]) # (prestg[120..110] & (! selnose[170..170]))), ((( StageIn[108..99], NumeratorIn[150..150]) & selnose[153..153]) # (prestg[109..99] & (! selnose[153..153]))), ((( StageIn[97..88], NumeratorIn[135..135]) & selnose[136..136]) # (prestg[98..88] & (! selnose[136..136]))), ((( StageIn[86..77], NumeratorIn[120..120]) & selnose[119..119]) # (prestg[87..77] & (! selnose[119..119]))), ((( StageIn[75..66], NumeratorIn[105..105]) & selnose[102..102]) # (prestg[76..66] & (! selnose[102..102]))), ((( StageIn[64..55], NumeratorIn[90..90]) & selnose[85..85]) # (prestg[65..55] & (! selnose[85..85]))), ((( StageIn[53..44], NumeratorIn[75..75]) & selnose[68..68]) # (prestg[54..44] & (! selnose[68..68]))), ((( StageIn[42..33], NumeratorIn[60..60]) & selnose[51..51]) # (prestg[43..33] & (! selnose[51..51]))), ((( StageIn[31..22], NumeratorIn[45..45]) & selnose[34..34]) # (prestg[32..22] & (! selnose[34..34]))), ((( StageIn[20..11], NumeratorIn[30..30]) & selnose[17..17]) # (prestg[21..11] & (! selnose[17..17]))), ((( StageIn[9..0], NumeratorIn[15..15]) & selnose[0..0]) # (prestg[10..0] & (! selnose[0..0]))));
-END;
---VALID FILE
diff --git a/db/alt_u_div_87f.tdf b/db/alt_u_div_87f.tdf
deleted file mode 100644
index 3bff289..0000000
--- a/db/alt_u_div_87f.tdf
+++ /dev/null
@@ -1,212 +0,0 @@
---alt_u_div DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=16 WIDTH_Q=16 WIDTH_R=4 denominator numerator quotient remainder
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION add_sub_7pc (dataa[0..0], datab[0..0])
-RETURNS ( cout, result[0..0]);
-FUNCTION add_sub_8pc (dataa[1..0], datab[1..0])
-RETURNS ( cout, result[1..0]);
-
---synthesis_resources = lut 81
-SUBDESIGN alt_u_div_87f
-(
- denominator[3..0] : input;
- numerator[15..0] : input;
- quotient[15..0] : output;
- remainder[3..0] : output;
-)
-VARIABLE
- add_sub_0 : add_sub_7pc;
- add_sub_1 : add_sub_8pc;
- add_sub_10_result_int[5..0] : WIRE;
- add_sub_10_cout : WIRE;
- add_sub_10_dataa[4..0] : WIRE;
- add_sub_10_datab[4..0] : WIRE;
- add_sub_10_result[4..0] : WIRE;
- add_sub_11_result_int[5..0] : WIRE;
- add_sub_11_cout : WIRE;
- add_sub_11_dataa[4..0] : WIRE;
- add_sub_11_datab[4..0] : WIRE;
- add_sub_11_result[4..0] : WIRE;
- add_sub_12_result_int[5..0] : WIRE;
- add_sub_12_cout : WIRE;
- add_sub_12_dataa[4..0] : WIRE;
- add_sub_12_datab[4..0] : WIRE;
- add_sub_12_result[4..0] : WIRE;
- add_sub_13_result_int[5..0] : WIRE;
- add_sub_13_cout : WIRE;
- add_sub_13_dataa[4..0] : WIRE;
- add_sub_13_datab[4..0] : WIRE;
- add_sub_13_result[4..0] : WIRE;
- add_sub_14_result_int[5..0] : WIRE;
- add_sub_14_cout : WIRE;
- add_sub_14_dataa[4..0] : WIRE;
- add_sub_14_datab[4..0] : WIRE;
- add_sub_14_result[4..0] : WIRE;
- add_sub_15_result_int[5..0] : WIRE;
- add_sub_15_cout : WIRE;
- add_sub_15_dataa[4..0] : WIRE;
- add_sub_15_datab[4..0] : WIRE;
- add_sub_15_result[4..0] : WIRE;
- add_sub_2_result_int[3..0] : WIRE;
- add_sub_2_cout : WIRE;
- add_sub_2_dataa[2..0] : WIRE;
- add_sub_2_datab[2..0] : WIRE;
- add_sub_2_result[2..0] : WIRE;
- add_sub_3_result_int[4..0] : WIRE;
- add_sub_3_cout : WIRE;
- add_sub_3_dataa[3..0] : WIRE;
- add_sub_3_datab[3..0] : WIRE;
- add_sub_3_result[3..0] : WIRE;
- add_sub_4_result_int[5..0] : WIRE;
- add_sub_4_cout : WIRE;
- add_sub_4_dataa[4..0] : WIRE;
- add_sub_4_datab[4..0] : WIRE;
- add_sub_4_result[4..0] : WIRE;
- add_sub_5_result_int[5..0] : WIRE;
- add_sub_5_cout : WIRE;
- add_sub_5_dataa[4..0] : WIRE;
- add_sub_5_datab[4..0] : WIRE;
- add_sub_5_result[4..0] : WIRE;
- add_sub_6_result_int[5..0] : WIRE;
- add_sub_6_cout : WIRE;
- add_sub_6_dataa[4..0] : WIRE;
- add_sub_6_datab[4..0] : WIRE;
- add_sub_6_result[4..0] : WIRE;
- add_sub_7_result_int[5..0] : WIRE;
- add_sub_7_cout : WIRE;
- add_sub_7_dataa[4..0] : WIRE;
- add_sub_7_datab[4..0] : WIRE;
- add_sub_7_result[4..0] : WIRE;
- add_sub_8_result_int[5..0] : WIRE;
- add_sub_8_cout : WIRE;
- add_sub_8_dataa[4..0] : WIRE;
- add_sub_8_datab[4..0] : WIRE;
- add_sub_8_result[4..0] : WIRE;
- add_sub_9_result_int[5..0] : WIRE;
- add_sub_9_cout : WIRE;
- add_sub_9_dataa[4..0] : WIRE;
- add_sub_9_datab[4..0] : WIRE;
- add_sub_9_result[4..0] : WIRE;
- DenominatorIn[84..0] : WIRE;
- DenominatorIn_tmp[84..0] : WIRE;
- gnd_wire : WIRE;
- nose[271..0] : WIRE;
- NumeratorIn[271..0] : WIRE;
- NumeratorIn_tmp[271..0] : WIRE;
- prestg[79..0] : WIRE;
- quotient_tmp[15..0] : WIRE;
- sel[67..0] : WIRE;
- selnose[271..0] : WIRE;
- StageIn[84..0] : WIRE;
- StageIn_tmp[84..0] : WIRE;
- StageOut[79..0] : WIRE;
-
-BEGIN
- add_sub_0.dataa[0..0] = NumeratorIn[15..15];
- add_sub_0.datab[0..0] = DenominatorIn[0..0];
- add_sub_1.dataa[] = ( StageIn[5..5], NumeratorIn[30..30]);
- add_sub_1.datab[1..0] = DenominatorIn[6..5];
- add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
- add_sub_10_result[] = add_sub_10_result_int[4..0];
- add_sub_10_cout = !add_sub_10_result_int[5];
- add_sub_10_dataa[] = ( StageIn[53..50], NumeratorIn[165..165]);
- add_sub_10_datab[] = DenominatorIn[54..50];
- add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
- add_sub_11_result[] = add_sub_11_result_int[4..0];
- add_sub_11_cout = !add_sub_11_result_int[5];
- add_sub_11_dataa[] = ( StageIn[58..55], NumeratorIn[180..180]);
- add_sub_11_datab[] = DenominatorIn[59..55];
- add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
- add_sub_12_result[] = add_sub_12_result_int[4..0];
- add_sub_12_cout = !add_sub_12_result_int[5];
- add_sub_12_dataa[] = ( StageIn[63..60], NumeratorIn[195..195]);
- add_sub_12_datab[] = DenominatorIn[64..60];
- add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
- add_sub_13_result[] = add_sub_13_result_int[4..0];
- add_sub_13_cout = !add_sub_13_result_int[5];
- add_sub_13_dataa[] = ( StageIn[68..65], NumeratorIn[210..210]);
- add_sub_13_datab[] = DenominatorIn[69..65];
- add_sub_14_result_int[] = (0, add_sub_14_dataa[]) - (0, add_sub_14_datab[]);
- add_sub_14_result[] = add_sub_14_result_int[4..0];
- add_sub_14_cout = !add_sub_14_result_int[5];
- add_sub_14_dataa[] = ( StageIn[73..70], NumeratorIn[225..225]);
- add_sub_14_datab[] = DenominatorIn[74..70];
- add_sub_15_result_int[] = (0, add_sub_15_dataa[]) - (0, add_sub_15_datab[]);
- add_sub_15_result[] = add_sub_15_result_int[4..0];
- add_sub_15_cout = !add_sub_15_result_int[5];
- add_sub_15_dataa[] = ( StageIn[78..75], NumeratorIn[240..240]);
- add_sub_15_datab[] = DenominatorIn[79..75];
- add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
- add_sub_2_result[] = add_sub_2_result_int[2..0];
- add_sub_2_cout = !add_sub_2_result_int[3];
- add_sub_2_dataa[] = ( StageIn[11..10], NumeratorIn[45..45]);
- add_sub_2_datab[] = DenominatorIn[12..10];
- add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
- add_sub_3_result[] = add_sub_3_result_int[3..0];
- add_sub_3_cout = !add_sub_3_result_int[4];
- add_sub_3_dataa[] = ( StageIn[17..15], NumeratorIn[60..60]);
- add_sub_3_datab[] = DenominatorIn[18..15];
- add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
- add_sub_4_result[] = add_sub_4_result_int[4..0];
- add_sub_4_cout = !add_sub_4_result_int[5];
- add_sub_4_dataa[] = ( StageIn[23..20], NumeratorIn[75..75]);
- add_sub_4_datab[] = DenominatorIn[24..20];
- add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
- add_sub_5_result[] = add_sub_5_result_int[4..0];
- add_sub_5_cout = !add_sub_5_result_int[5];
- add_sub_5_dataa[] = ( StageIn[28..25], NumeratorIn[90..90]);
- add_sub_5_datab[] = DenominatorIn[29..25];
- add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
- add_sub_6_result[] = add_sub_6_result_int[4..0];
- add_sub_6_cout = !add_sub_6_result_int[5];
- add_sub_6_dataa[] = ( StageIn[33..30], NumeratorIn[105..105]);
- add_sub_6_datab[] = DenominatorIn[34..30];
- add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
- add_sub_7_result[] = add_sub_7_result_int[4..0];
- add_sub_7_cout = !add_sub_7_result_int[5];
- add_sub_7_dataa[] = ( StageIn[38..35], NumeratorIn[120..120]);
- add_sub_7_datab[] = DenominatorIn[39..35];
- add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]);
- add_sub_8_result[] = add_sub_8_result_int[4..0];
- add_sub_8_cout = !add_sub_8_result_int[5];
- add_sub_8_dataa[] = ( StageIn[43..40], NumeratorIn[135..135]);
- add_sub_8_datab[] = DenominatorIn[44..40];
- add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]);
- add_sub_9_result[] = add_sub_9_result_int[4..0];
- add_sub_9_cout = !add_sub_9_result_int[5];
- add_sub_9_dataa[] = ( StageIn[48..45], NumeratorIn[150..150]);
- add_sub_9_datab[] = DenominatorIn[49..45];
- DenominatorIn[] = DenominatorIn_tmp[];
- DenominatorIn_tmp[] = ( DenominatorIn[79..0], ( gnd_wire, denominator[]));
- gnd_wire = B"0";
- nose[] = ( B"0000000000000000", add_sub_15_cout, B"0000000000000000", add_sub_14_cout, B"0000000000000000", add_sub_13_cout, B"0000000000000000", add_sub_12_cout, B"0000000000000000", add_sub_11_cout, B"0000000000000000", add_sub_10_cout, B"0000000000000000", add_sub_9_cout, B"0000000000000000", add_sub_8_cout, B"0000000000000000", add_sub_7_cout, B"0000000000000000", add_sub_6_cout, B"0000000000000000", add_sub_5_cout, B"0000000000000000", add_sub_4_cout, B"0000000000000000", add_sub_3_cout, B"0000000000000000", add_sub_2_cout, B"0000000000000000", add_sub_1.cout, B"0000000000000000", add_sub_0.cout);
- NumeratorIn[] = NumeratorIn_tmp[];
- NumeratorIn_tmp[] = ( NumeratorIn[255..0], numerator[]);
- prestg[] = ( add_sub_15_result[], add_sub_14_result[], add_sub_13_result[], add_sub_12_result[], add_sub_11_result[], add_sub_10_result[], add_sub_9_result[], add_sub_8_result[], add_sub_7_result[], add_sub_6_result[], add_sub_5_result[], add_sub_4_result[], GND, add_sub_3_result[], B"00", add_sub_2_result[], B"000", add_sub_1.result[], B"0000", add_sub_0.result[]);
- quotient[] = quotient_tmp[];
- quotient_tmp[] = ( (! selnose[0..0]), (! selnose[17..17]), (! selnose[34..34]), (! selnose[51..51]), (! selnose[68..68]), (! selnose[85..85]), (! selnose[102..102]), (! selnose[119..119]), (! selnose[136..136]), (! selnose[153..153]), (! selnose[170..170]), (! selnose[187..187]), (! selnose[204..204]), (! selnose[221..221]), (! selnose[238..238]), (! selnose[255..255]));
- remainder[3..0] = StageIn[83..80];
- sel[] = ( gnd_wire, (sel[67..67] # DenominatorIn[83..83]), (sel[66..66] # DenominatorIn[82..82]), (sel[65..65] # DenominatorIn[81..81]), gnd_wire, (sel[63..63] # DenominatorIn[78..78]), (sel[62..62] # DenominatorIn[77..77]), (sel[61..61] # DenominatorIn[76..76]), gnd_wire, (sel[59..59] # DenominatorIn[73..73]), (sel[58..58] # DenominatorIn[72..72]), (sel[57..57] # DenominatorIn[71..71]), gnd_wire, (sel[55..55] # DenominatorIn[68..68]), (sel[54..54] # DenominatorIn[67..67]), (sel[53..53] # DenominatorIn[66..66]), gnd_wire, (sel[51..51] # DenominatorIn[63..63]), (sel[50..50] # DenominatorIn[62..62]), (sel[49..49] # DenominatorIn[61..61]), gnd_wire, (sel[47..47] # DenominatorIn[58..58]), (sel[46..46] # DenominatorIn[57..57]), (sel[45..45] # DenominatorIn[56..56]), gnd_wire, (sel[43..43] # DenominatorIn[53..53]), (sel[42..42] # DenominatorIn[52..52]), (sel[41..41] # DenominatorIn[51..51]), gnd_wire, (sel[39..39] # DenominatorIn[48..48]), (sel[38..38] # DenominatorIn[47..47]), (sel[37..37] # DenominatorIn[46..46]), gnd_wire, (sel[35..35] # DenominatorIn[43..43]), (sel[34..34] # DenominatorIn[42..42]), (sel[33..33] # DenominatorIn[41..41]), gnd_wire, (sel[31..31] # DenominatorIn[38..38]), (sel[30..30] # DenominatorIn[37..37]), (sel[29..29] # DenominatorIn[36..36]), gnd_wire, (sel[27..27] # DenominatorIn[33..33]), (sel[26..26] # DenominatorIn[32..32]), (sel[25..25] # DenominatorIn[31..31]), gnd_wire, (sel[23..23] # DenominatorIn[28..28]), (sel[22..22] # DenominatorIn[27..27]), (sel[21..21] # DenominatorIn[26..26]), gnd_wire, (sel[19..19] # DenominatorIn[23..23]), (sel[18..18] # DenominatorIn[22..22]), (sel[17..17] # DenominatorIn[21..21]), gnd_wire, (sel[15..15] # DenominatorIn[18..18]), (sel[14..14] # DenominatorIn[17..17]), (sel[13..13] # DenominatorIn[16..16]), gnd_wire, (sel[11..11] # DenominatorIn[13..13]), (sel[10..10] # DenominatorIn[12..12]), (sel[9..9] # DenominatorIn[11..11]), gnd_wire, (sel[7..7] # DenominatorIn[8..8]), (sel[6..6] # DenominatorIn[7..7]), (sel[5..5] # DenominatorIn[6..6]), gnd_wire, (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
- selnose[] = ( (! nose[271..271]), (! nose[270..270]), (! nose[269..269]), (! nose[268..268]), (! nose[267..267]), (! nose[266..266]), (! nose[265..265]), (! nose[264..264]), (! nose[263..263]), (! nose[262..262]), (! nose[261..261]), (! nose[260..260]), ((! nose[259..259]) # sel[67..67]), ((! nose[258..258]) # sel[66..66]), ((! nose[257..257]) # sel[65..65]), ((! nose[256..256]) # sel[64..64]), (! nose[255..255]), (! nose[254..254]), (! nose[253..253]), (! nose[252..252]), (! nose[251..251]), (! nose[250..250]), (! nose[249..249]), (! nose[248..248]), (! nose[247..247]), (! nose[246..246]), (! nose[245..245]), (! nose[244..244]), ((! nose[243..243]) # sel[63..63]), ((! nose[242..242]) # sel[62..62]), ((! nose[241..241]) # sel[61..61]), ((! nose[240..240]) # sel[60..60]), (! nose[239..239]), (! nose[238..238]), (! nose[237..237]), (! nose[236..236]), (! nose[235..235]), (! nose[234..234]), (! nose[233..233]), (! nose[232..232]), (! nose[231..231]), (! nose[230..230]), (! nose[229..229]), (! nose[228..228]), ((! nose[227..227]) # sel[59..59]), ((! nose[226..226]) # sel[58..58]), ((! nose[225..225]) # sel[57..57]), ((! nose[224..224]) # sel[56..56]), (! nose[223..223]), (! nose[222..222]), (! nose[221..221]), (! nose[220..220]), (! nose[219..219]), (! nose[218..218]), (! nose[217..217]), (! nose[216..216]), (! nose[215..215]), (! nose[214..214]), (! nose[213..213]), (! nose[212..212]), ((! nose[211..211]) # sel[55..55]), ((! nose[210..210]) # sel[54..54]), ((! nose[209..209]) # sel[53..53]), ((! nose[208..208]) # sel[52..52]), (! nose[207..207]), (! nose[206..206]), (! nose[205..205]), (! nose[204..204]), (! nose[203..203]), (! nose[202..202]), (! nose[201..201]), (! nose[200..200]), (! nose[199..199]), (! nose[198..198]), (! nose[197..197]), (! nose[196..196]), ((! nose[195..195]) # sel[51..51]), ((! nose[194..194]) # sel[50..50]), ((! nose[193..193]) # sel[49..49]), ((! nose[192..192]) # sel[48..48]), (! nose[191..191]), (! nose[190..190]), (! nose[189..189]), (! nose[188..188]), (! nose[187..187]), (! nose[186..186]), (! nose[185..185]), (! nose[184..184]), (! nose[183..183]), (! nose[182..182]), (! nose[181..181]), (! nose[180..180]), ((! nose[179..179]) # sel[47..47]), ((! nose[178..178]) # sel[46..46]), ((! nose[177..177]) # sel[45..45]), ((! nose[176..176]) # sel[44..44]), (! nose[175..175]), (! nose[174..174]), (! nose[173..173]), (! nose[172..172]), (! nose[171..171]), (! nose[170..170]), (! nose[169..169]), (! nose[168..168]), (! nose[167..167]), (! nose[166..166]), (! nose[165..165]), (! nose[164..164]), ((! nose[163..163]) # sel[43..43]), ((! nose[162..162]) # sel[42..42]), ((! nose[161..161]) # sel[41..41]), ((! nose[160..160]) # sel[40..40]), (! nose[159..159]), (! nose[158..158]), (! nose[157..157]), (! nose[156..156]), (! nose[155..155]), (! nose[154..154]), (! nose[153..153]), (! nose[152..152]), (! nose[151..151]), (! nose[150..150]), (! nose[149..149]), (! nose[148..148]), ((! nose[147..147]) # sel[39..39]), ((! nose[146..146]) # sel[38..38]), ((! nose[145..145]) # sel[37..37]), ((! nose[144..144]) # sel[36..36]), (! nose[143..143]), (! nose[142..142]), (! nose[141..141]), (! nose[140..140]), (! nose[139..139]), (! nose[138..138]), (! nose[137..137]), (! nose[136..136]), (! nose[135..135]), (! nose[134..134]), (! nose[133..133]), (! nose[132..132]), ((! nose[131..131]) # sel[35..35]), ((! nose[130..130]) # sel[34..34]), ((! nose[129..129]) # sel[33..33]), ((! nose[128..128]) # sel[32..32]), (! nose[127..127]), (! nose[126..126]), (! nose[125..125]), (! nose[124..124]), (! nose[123..123]), (! nose[122..122]), (! nose[121..121]), (! nose[120..120]), (! nose[119..119]), (! nose[118..118]), (! nose[117..117]), (! nose[116..116]), ((! nose[115..115]) # sel[31..31]), ((! nose[114..114]) # sel[30..30]), ((! nose[113..113]) # sel[29..29]), ((! nose[112..112]) # sel[28..28]), (! nose[111..111]), (! nose[110..110]), (! nose[109..109]), (! nose[108..108]), (! nose[107..107]), (! nose[106..106]), (! nose[105..105]), (! nose[104..104]), (! nose[103..103]), (! nose[102..102]), (! nose[101..101]), (! nose[100..100]), ((! nose[99..99]) # sel[27..27]), ((! nose[98..98]) # sel[26..26]), ((! nose[97..97]) # sel[25..25]), ((! nose[96..96]) # sel[24..24]), (! nose[95..95]), (! nose[94..94]), (! nose[93..93]), (! nose[92..92]), (! nose[91..91]), (! nose[90..90]), (! nose[89..89]), (! nose[88..88]), (! nose[87..87]), (! nose[86..86]), (! nose[85..85]), (! nose[84..84]), ((! nose[83..83]) # sel[23..23]), ((! nose[82..82]) # sel[22..22]), ((! nose[81..81]) # sel[21..21]), ((! nose[80..80]) # sel[20..20]), (! nose[79..79]), (! nose[78..78]), (! nose[77..77]), (! nose[76..76]), (! nose[75..75]), (! nose[74..74]), (! nose[73..73]), (! nose[72..72]), (! nose[71..71]), (! nose[70..70]), (! nose[69..69]), (! nose[68..68]), ((! nose[67..67]) # sel[19..19]), ((! nose[66..66]) # sel[18..18]), ((! nose[65..65]) # sel[17..17]), ((! nose[64..64]) # sel[16..16]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), (! nose[59..59]), (! nose[58..58]), (! nose[57..57]), (! nose[56..56]), (! nose[55..55]), (! nose[54..54]), (! nose[53..53]), (! nose[52..52]), ((! nose[51..51]) # sel[15..15]), ((! nose[50..50]) # sel[14..14]), ((! nose[49..49]) # sel[13..13]), ((! nose[48..48]) # sel[12..12]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), (! nose[43..43]), (! nose[42..42]), (! nose[41..41]), (! nose[40..40]), (! nose[39..39]), (! nose[38..38]), (! nose[37..37]), (! nose[36..36]), ((! nose[35..35]) # sel[11..11]), ((! nose[34..34]) # sel[10..10]), ((! nose[33..33]) # sel[9..9]), ((! nose[32..32]) # sel[8..8]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), (! nose[27..27]), (! nose[26..26]), (! nose[25..25]), (! nose[24..24]), (! nose[23..23]), (! nose[22..22]), (! nose[21..21]), (! nose[20..20]), ((! nose[19..19]) # sel[7..7]), ((! nose[18..18]) # sel[6..6]), ((! nose[17..17]) # sel[5..5]), ((! nose[16..16]) # sel[4..4]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), (! nose[11..11]), (! nose[10..10]), (! nose[9..9]), (! nose[8..8]), (! nose[7..7]), (! nose[6..6]), (! nose[5..5]), (! nose[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
- StageIn[] = StageIn_tmp[];
- StageIn_tmp[] = ( StageOut[79..0], B"00000");
- StageOut[] = ( ((( StageIn[78..75], NumeratorIn[240..240]) & selnose[255..255]) # (prestg[79..75] & (! selnose[255..255]))), ((( StageIn[73..70], NumeratorIn[225..225]) & selnose[238..238]) # (prestg[74..70] & (! selnose[238..238]))), ((( StageIn[68..65], NumeratorIn[210..210]) & selnose[221..221]) # (prestg[69..65] & (! selnose[221..221]))), ((( StageIn[63..60], NumeratorIn[195..195]) & selnose[204..204]) # (prestg[64..60] & (! selnose[204..204]))), ((( StageIn[58..55], NumeratorIn[180..180]) & selnose[187..187]) # (prestg[59..55] & (! selnose[187..187]))), ((( StageIn[53..50], NumeratorIn[165..165]) & selnose[170..170]) # (prestg[54..50] & (! selnose[170..170]))), ((( StageIn[48..45], NumeratorIn[150..150]) & selnose[153..153]) # (prestg[49..45] & (! selnose[153..153]))), ((( StageIn[43..40], NumeratorIn[135..135]) & selnose[136..136]) # (prestg[44..40] & (! selnose[136..136]))), ((( StageIn[38..35], NumeratorIn[120..120]) & selnose[119..119]) # (prestg[39..35] & (! selnose[119..119]))), ((( StageIn[33..30], NumeratorIn[105..105]) & selnose[102..102]) # (prestg[34..30] & (! selnose[102..102]))), ((( StageIn[28..25], NumeratorIn[90..90]) & selnose[85..85]) # (prestg[29..25] & (! selnose[85..85]))), ((( StageIn[23..20], NumeratorIn[75..75]) & selnose[68..68]) # (prestg[24..20] & (! selnose[68..68]))), ((( StageIn[18..15], NumeratorIn[60..60]) & selnose[51..51]) # (prestg[19..15] & (! selnose[51..51]))), ((( StageIn[13..10], NumeratorIn[45..45]) & selnose[34..34]) # (prestg[14..10] & (! selnose[34..34]))), ((( StageIn[8..5], NumeratorIn[30..30]) & selnose[17..17]) # (prestg[9..5] & (! selnose[17..17]))), ((( StageIn[3..0], NumeratorIn[15..15]) & selnose[0..0]) # (prestg[4..0] & (! selnose[0..0]))));
-END;
---VALID FILE
diff --git a/db/alt_u_div_e7f.tdf b/db/alt_u_div_e7f.tdf
deleted file mode 100644
index c835f5e..0000000
--- a/db/alt_u_div_e7f.tdf
+++ /dev/null
@@ -1,212 +0,0 @@
---alt_u_div DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=7 WIDTH_N=16 WIDTH_Q=16 WIDTH_R=7 denominator numerator quotient remainder
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION add_sub_7pc (dataa[0..0], datab[0..0])
-RETURNS ( cout, result[0..0]);
-FUNCTION add_sub_8pc (dataa[1..0], datab[1..0])
-RETURNS ( cout, result[1..0]);
-
---synthesis_resources = lut 111
-SUBDESIGN alt_u_div_e7f
-(
- denominator[6..0] : input;
- numerator[15..0] : input;
- quotient[15..0] : output;
- remainder[6..0] : output;
-)
-VARIABLE
- add_sub_0 : add_sub_7pc;
- add_sub_1 : add_sub_8pc;
- add_sub_10_result_int[8..0] : WIRE;
- add_sub_10_cout : WIRE;
- add_sub_10_dataa[7..0] : WIRE;
- add_sub_10_datab[7..0] : WIRE;
- add_sub_10_result[7..0] : WIRE;
- add_sub_11_result_int[8..0] : WIRE;
- add_sub_11_cout : WIRE;
- add_sub_11_dataa[7..0] : WIRE;
- add_sub_11_datab[7..0] : WIRE;
- add_sub_11_result[7..0] : WIRE;
- add_sub_12_result_int[8..0] : WIRE;
- add_sub_12_cout : WIRE;
- add_sub_12_dataa[7..0] : WIRE;
- add_sub_12_datab[7..0] : WIRE;
- add_sub_12_result[7..0] : WIRE;
- add_sub_13_result_int[8..0] : WIRE;
- add_sub_13_cout : WIRE;
- add_sub_13_dataa[7..0] : WIRE;
- add_sub_13_datab[7..0] : WIRE;
- add_sub_13_result[7..0] : WIRE;
- add_sub_14_result_int[8..0] : WIRE;
- add_sub_14_cout : WIRE;
- add_sub_14_dataa[7..0] : WIRE;
- add_sub_14_datab[7..0] : WIRE;
- add_sub_14_result[7..0] : WIRE;
- add_sub_15_result_int[8..0] : WIRE;
- add_sub_15_cout : WIRE;
- add_sub_15_dataa[7..0] : WIRE;
- add_sub_15_datab[7..0] : WIRE;
- add_sub_15_result[7..0] : WIRE;
- add_sub_2_result_int[3..0] : WIRE;
- add_sub_2_cout : WIRE;
- add_sub_2_dataa[2..0] : WIRE;
- add_sub_2_datab[2..0] : WIRE;
- add_sub_2_result[2..0] : WIRE;
- add_sub_3_result_int[4..0] : WIRE;
- add_sub_3_cout : WIRE;
- add_sub_3_dataa[3..0] : WIRE;
- add_sub_3_datab[3..0] : WIRE;
- add_sub_3_result[3..0] : WIRE;
- add_sub_4_result_int[5..0] : WIRE;
- add_sub_4_cout : WIRE;
- add_sub_4_dataa[4..0] : WIRE;
- add_sub_4_datab[4..0] : WIRE;
- add_sub_4_result[4..0] : WIRE;
- add_sub_5_result_int[6..0] : WIRE;
- add_sub_5_cout : WIRE;
- add_sub_5_dataa[5..0] : WIRE;
- add_sub_5_datab[5..0] : WIRE;
- add_sub_5_result[5..0] : WIRE;
- add_sub_6_result_int[7..0] : WIRE;
- add_sub_6_cout : WIRE;
- add_sub_6_dataa[6..0] : WIRE;
- add_sub_6_datab[6..0] : WIRE;
- add_sub_6_result[6..0] : WIRE;
- add_sub_7_result_int[8..0] : WIRE;
- add_sub_7_cout : WIRE;
- add_sub_7_dataa[7..0] : WIRE;
- add_sub_7_datab[7..0] : WIRE;
- add_sub_7_result[7..0] : WIRE;
- add_sub_8_result_int[8..0] : WIRE;
- add_sub_8_cout : WIRE;
- add_sub_8_dataa[7..0] : WIRE;
- add_sub_8_datab[7..0] : WIRE;
- add_sub_8_result[7..0] : WIRE;
- add_sub_9_result_int[8..0] : WIRE;
- add_sub_9_cout : WIRE;
- add_sub_9_dataa[7..0] : WIRE;
- add_sub_9_datab[7..0] : WIRE;
- add_sub_9_result[7..0] : WIRE;
- DenominatorIn[135..0] : WIRE;
- DenominatorIn_tmp[135..0] : WIRE;
- gnd_wire : WIRE;
- nose[271..0] : WIRE;
- NumeratorIn[271..0] : WIRE;
- NumeratorIn_tmp[271..0] : WIRE;
- prestg[127..0] : WIRE;
- quotient_tmp[15..0] : WIRE;
- sel[118..0] : WIRE;
- selnose[271..0] : WIRE;
- StageIn[135..0] : WIRE;
- StageIn_tmp[135..0] : WIRE;
- StageOut[127..0] : WIRE;
-
-BEGIN
- add_sub_0.dataa[0..0] = NumeratorIn[15..15];
- add_sub_0.datab[0..0] = DenominatorIn[0..0];
- add_sub_1.dataa[] = ( StageIn[8..8], NumeratorIn[30..30]);
- add_sub_1.datab[1..0] = DenominatorIn[9..8];
- add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
- add_sub_10_result[] = add_sub_10_result_int[7..0];
- add_sub_10_cout = !add_sub_10_result_int[8];
- add_sub_10_dataa[] = ( StageIn[86..80], NumeratorIn[165..165]);
- add_sub_10_datab[] = DenominatorIn[87..80];
- add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
- add_sub_11_result[] = add_sub_11_result_int[7..0];
- add_sub_11_cout = !add_sub_11_result_int[8];
- add_sub_11_dataa[] = ( StageIn[94..88], NumeratorIn[180..180]);
- add_sub_11_datab[] = DenominatorIn[95..88];
- add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
- add_sub_12_result[] = add_sub_12_result_int[7..0];
- add_sub_12_cout = !add_sub_12_result_int[8];
- add_sub_12_dataa[] = ( StageIn[102..96], NumeratorIn[195..195]);
- add_sub_12_datab[] = DenominatorIn[103..96];
- add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
- add_sub_13_result[] = add_sub_13_result_int[7..0];
- add_sub_13_cout = !add_sub_13_result_int[8];
- add_sub_13_dataa[] = ( StageIn[110..104], NumeratorIn[210..210]);
- add_sub_13_datab[] = DenominatorIn[111..104];
- add_sub_14_result_int[] = (0, add_sub_14_dataa[]) - (0, add_sub_14_datab[]);
- add_sub_14_result[] = add_sub_14_result_int[7..0];
- add_sub_14_cout = !add_sub_14_result_int[8];
- add_sub_14_dataa[] = ( StageIn[118..112], NumeratorIn[225..225]);
- add_sub_14_datab[] = DenominatorIn[119..112];
- add_sub_15_result_int[] = (0, add_sub_15_dataa[]) - (0, add_sub_15_datab[]);
- add_sub_15_result[] = add_sub_15_result_int[7..0];
- add_sub_15_cout = !add_sub_15_result_int[8];
- add_sub_15_dataa[] = ( StageIn[126..120], NumeratorIn[240..240]);
- add_sub_15_datab[] = DenominatorIn[127..120];
- add_sub_2_result_int[] = (0, add_sub_2_dataa[]) - (0, add_sub_2_datab[]);
- add_sub_2_result[] = add_sub_2_result_int[2..0];
- add_sub_2_cout = !add_sub_2_result_int[3];
- add_sub_2_dataa[] = ( StageIn[17..16], NumeratorIn[45..45]);
- add_sub_2_datab[] = DenominatorIn[18..16];
- add_sub_3_result_int[] = (0, add_sub_3_dataa[]) - (0, add_sub_3_datab[]);
- add_sub_3_result[] = add_sub_3_result_int[3..0];
- add_sub_3_cout = !add_sub_3_result_int[4];
- add_sub_3_dataa[] = ( StageIn[26..24], NumeratorIn[60..60]);
- add_sub_3_datab[] = DenominatorIn[27..24];
- add_sub_4_result_int[] = (0, add_sub_4_dataa[]) - (0, add_sub_4_datab[]);
- add_sub_4_result[] = add_sub_4_result_int[4..0];
- add_sub_4_cout = !add_sub_4_result_int[5];
- add_sub_4_dataa[] = ( StageIn[35..32], NumeratorIn[75..75]);
- add_sub_4_datab[] = DenominatorIn[36..32];
- add_sub_5_result_int[] = (0, add_sub_5_dataa[]) - (0, add_sub_5_datab[]);
- add_sub_5_result[] = add_sub_5_result_int[5..0];
- add_sub_5_cout = !add_sub_5_result_int[6];
- add_sub_5_dataa[] = ( StageIn[44..40], NumeratorIn[90..90]);
- add_sub_5_datab[] = DenominatorIn[45..40];
- add_sub_6_result_int[] = (0, add_sub_6_dataa[]) - (0, add_sub_6_datab[]);
- add_sub_6_result[] = add_sub_6_result_int[6..0];
- add_sub_6_cout = !add_sub_6_result_int[7];
- add_sub_6_dataa[] = ( StageIn[53..48], NumeratorIn[105..105]);
- add_sub_6_datab[] = DenominatorIn[54..48];
- add_sub_7_result_int[] = (0, add_sub_7_dataa[]) - (0, add_sub_7_datab[]);
- add_sub_7_result[] = add_sub_7_result_int[7..0];
- add_sub_7_cout = !add_sub_7_result_int[8];
- add_sub_7_dataa[] = ( StageIn[62..56], NumeratorIn[120..120]);
- add_sub_7_datab[] = DenominatorIn[63..56];
- add_sub_8_result_int[] = (0, add_sub_8_dataa[]) - (0, add_sub_8_datab[]);
- add_sub_8_result[] = add_sub_8_result_int[7..0];
- add_sub_8_cout = !add_sub_8_result_int[8];
- add_sub_8_dataa[] = ( StageIn[70..64], NumeratorIn[135..135]);
- add_sub_8_datab[] = DenominatorIn[71..64];
- add_sub_9_result_int[] = (0, add_sub_9_dataa[]) - (0, add_sub_9_datab[]);
- add_sub_9_result[] = add_sub_9_result_int[7..0];
- add_sub_9_cout = !add_sub_9_result_int[8];
- add_sub_9_dataa[] = ( StageIn[78..72], NumeratorIn[150..150]);
- add_sub_9_datab[] = DenominatorIn[79..72];
- DenominatorIn[] = DenominatorIn_tmp[];
- DenominatorIn_tmp[] = ( DenominatorIn[127..0], ( gnd_wire, denominator[]));
- gnd_wire = B"0";
- nose[] = ( B"0000000000000000", add_sub_15_cout, B"0000000000000000", add_sub_14_cout, B"0000000000000000", add_sub_13_cout, B"0000000000000000", add_sub_12_cout, B"0000000000000000", add_sub_11_cout, B"0000000000000000", add_sub_10_cout, B"0000000000000000", add_sub_9_cout, B"0000000000000000", add_sub_8_cout, B"0000000000000000", add_sub_7_cout, B"0000000000000000", add_sub_6_cout, B"0000000000000000", add_sub_5_cout, B"0000000000000000", add_sub_4_cout, B"0000000000000000", add_sub_3_cout, B"0000000000000000", add_sub_2_cout, B"0000000000000000", add_sub_1.cout, B"0000000000000000", add_sub_0.cout);
- NumeratorIn[] = NumeratorIn_tmp[];
- NumeratorIn_tmp[] = ( NumeratorIn[255..0], numerator[]);
- prestg[] = ( add_sub_15_result[], add_sub_14_result[], add_sub_13_result[], add_sub_12_result[], add_sub_11_result[], add_sub_10_result[], add_sub_9_result[], add_sub_8_result[], add_sub_7_result[], GND, add_sub_6_result[], B"00", add_sub_5_result[], B"000", add_sub_4_result[], B"0000", add_sub_3_result[], B"00000", add_sub_2_result[], B"000000", add_sub_1.result[], B"0000000", add_sub_0.result[]);
- quotient[] = quotient_tmp[];
- quotient_tmp[] = ( (! selnose[0..0]), (! selnose[17..17]), (! selnose[34..34]), (! selnose[51..51]), (! selnose[68..68]), (! selnose[85..85]), (! selnose[102..102]), (! selnose[119..119]), (! selnose[136..136]), (! selnose[153..153]), (! selnose[170..170]), (! selnose[187..187]), (! selnose[204..204]), (! selnose[221..221]), (! selnose[238..238]), (! selnose[255..255]));
- remainder[6..0] = StageIn[134..128];
- sel[] = ( gnd_wire, (sel[118..118] # DenominatorIn[134..134]), (sel[117..117] # DenominatorIn[133..133]), (sel[116..116] # DenominatorIn[132..132]), (sel[115..115] # DenominatorIn[131..131]), (sel[114..114] # DenominatorIn[130..130]), (sel[113..113] # DenominatorIn[129..129]), gnd_wire, (sel[111..111] # DenominatorIn[126..126]), (sel[110..110] # DenominatorIn[125..125]), (sel[109..109] # DenominatorIn[124..124]), (sel[108..108] # DenominatorIn[123..123]), (sel[107..107] # DenominatorIn[122..122]), (sel[106..106] # DenominatorIn[121..121]), gnd_wire, (sel[104..104] # DenominatorIn[118..118]), (sel[103..103] # DenominatorIn[117..117]), (sel[102..102] # DenominatorIn[116..116]), (sel[101..101] # DenominatorIn[115..115]), (sel[100..100] # DenominatorIn[114..114]), (sel[99..99] # DenominatorIn[113..113]), gnd_wire, (sel[97..97] # DenominatorIn[110..110]), (sel[96..96] # DenominatorIn[109..109]), (sel[95..95] # DenominatorIn[108..108]), (sel[94..94] # DenominatorIn[107..107]), (sel[93..93] # DenominatorIn[106..106]), (sel[92..92] # DenominatorIn[105..105]), gnd_wire, (sel[90..90] # DenominatorIn[102..102]), (sel[89..89] # DenominatorIn[101..101]), (sel[88..88] # DenominatorIn[100..100]), (sel[87..87] # DenominatorIn[99..99]), (sel[86..86] # DenominatorIn[98..98]), (sel[85..85] # DenominatorIn[97..97]), gnd_wire, (sel[83..83] # DenominatorIn[94..94]), (sel[82..82] # DenominatorIn[93..93]), (sel[81..81] # DenominatorIn[92..92]), (sel[80..80] # DenominatorIn[91..91]), (sel[79..79] # DenominatorIn[90..90]), (sel[78..78] # DenominatorIn[89..89]), gnd_wire, (sel[76..76] # DenominatorIn[86..86]), (sel[75..75] # DenominatorIn[85..85]), (sel[74..74] # DenominatorIn[84..84]), (sel[73..73] # DenominatorIn[83..83]), (sel[72..72] # DenominatorIn[82..82]), (sel[71..71] # DenominatorIn[81..81]), gnd_wire, (sel[69..69] # DenominatorIn[78..78]), (sel[68..68] # DenominatorIn[77..77]), (sel[67..67] # DenominatorIn[76..76]), (sel[66..66] # DenominatorIn[75..75]), (sel[65..65] # DenominatorIn[74..74]), (sel[64..64] # DenominatorIn[73..73]), gnd_wire, (sel[62..62] # DenominatorIn[70..70]), (sel[61..61] # DenominatorIn[69..69]), (sel[60..60] # DenominatorIn[68..68]), (sel[59..59] # DenominatorIn[67..67]), (sel[58..58] # DenominatorIn[66..66]), (sel[57..57] # DenominatorIn[65..65]), gnd_wire, (sel[55..55] # DenominatorIn[62..62]), (sel[54..54] # DenominatorIn[61..61]), (sel[53..53] # DenominatorIn[60..60]), (sel[52..52] # DenominatorIn[59..59]), (sel[51..51] # DenominatorIn[58..58]), (sel[50..50] # DenominatorIn[57..57]), gnd_wire, (sel[48..48] # DenominatorIn[54..54]), (sel[47..47] # DenominatorIn[53..53]), (sel[46..46] # DenominatorIn[52..52]), (sel[45..45] # DenominatorIn[51..51]), (sel[44..44] # DenominatorIn[50..50]), (sel[43..43] # DenominatorIn[49..49]), gnd_wire, (sel[41..41] # DenominatorIn[46..46]), (sel[40..40] # DenominatorIn[45..45]), (sel[39..39] # DenominatorIn[44..44]), (sel[38..38] # DenominatorIn[43..43]), (sel[37..37] # DenominatorIn[42..42]), (sel[36..36] # DenominatorIn[41..41]), gnd_wire, (sel[34..34] # DenominatorIn[38..38]), (sel[33..33] # DenominatorIn[37..37]), (sel[32..32] # DenominatorIn[36..36]), (sel[31..31] # DenominatorIn[35..35]), (sel[30..30] # DenominatorIn[34..34]), (sel[29..29] # DenominatorIn[33..33]), gnd_wire, (sel[27..27] # DenominatorIn[30..30]), (sel[26..26] # DenominatorIn[29..29]), (sel[25..25] # DenominatorIn[28..28]), (sel[24..24] # DenominatorIn[27..27]), (sel[23..23] # DenominatorIn[26..26]), (sel[22..22] # DenominatorIn[25..25]), gnd_wire, (sel[20..20] # DenominatorIn[22..22]), (sel[19..19] # DenominatorIn[21..21]), (sel[18..18] # DenominatorIn[20..20]), (sel[17..17] # DenominatorIn[19..19]), (sel[16..16] # DenominatorIn[18..18]), (sel[15..15] # DenominatorIn[17..17]), gnd_wire, (sel[13..13] # DenominatorIn[14..14]), (sel[12..12] # DenominatorIn[13..13]), (sel[11..11] # DenominatorIn[12..12]), (sel[10..10] # DenominatorIn[11..11]), (sel[9..9] # DenominatorIn[10..10]), (sel[8..8] # DenominatorIn[9..9]), gnd_wire, (sel[6..6] # DenominatorIn[6..6]), (sel[5..5] # DenominatorIn[5..5]), (sel[4..4] # DenominatorIn[4..4]), (sel[3..3] # DenominatorIn[3..3]), (sel[2..2] # DenominatorIn[2..2]), (sel[1..1] # DenominatorIn[1..1]));
- selnose[] = ( (! nose[271..271]), (! nose[270..270]), (! nose[269..269]), (! nose[268..268]), (! nose[267..267]), (! nose[266..266]), (! nose[265..265]), (! nose[264..264]), (! nose[263..263]), ((! nose[262..262]) # sel[118..118]), ((! nose[261..261]) # sel[117..117]), ((! nose[260..260]) # sel[116..116]), ((! nose[259..259]) # sel[115..115]), ((! nose[258..258]) # sel[114..114]), ((! nose[257..257]) # sel[113..113]), ((! nose[256..256]) # sel[112..112]), (! nose[255..255]), (! nose[254..254]), (! nose[253..253]), (! nose[252..252]), (! nose[251..251]), (! nose[250..250]), (! nose[249..249]), (! nose[248..248]), (! nose[247..247]), ((! nose[246..246]) # sel[111..111]), ((! nose[245..245]) # sel[110..110]), ((! nose[244..244]) # sel[109..109]), ((! nose[243..243]) # sel[108..108]), ((! nose[242..242]) # sel[107..107]), ((! nose[241..241]) # sel[106..106]), ((! nose[240..240]) # sel[105..105]), (! nose[239..239]), (! nose[238..238]), (! nose[237..237]), (! nose[236..236]), (! nose[235..235]), (! nose[234..234]), (! nose[233..233]), (! nose[232..232]), (! nose[231..231]), ((! nose[230..230]) # sel[104..104]), ((! nose[229..229]) # sel[103..103]), ((! nose[228..228]) # sel[102..102]), ((! nose[227..227]) # sel[101..101]), ((! nose[226..226]) # sel[100..100]), ((! nose[225..225]) # sel[99..99]), ((! nose[224..224]) # sel[98..98]), (! nose[223..223]), (! nose[222..222]), (! nose[221..221]), (! nose[220..220]), (! nose[219..219]), (! nose[218..218]), (! nose[217..217]), (! nose[216..216]), (! nose[215..215]), ((! nose[214..214]) # sel[97..97]), ((! nose[213..213]) # sel[96..96]), ((! nose[212..212]) # sel[95..95]), ((! nose[211..211]) # sel[94..94]), ((! nose[210..210]) # sel[93..93]), ((! nose[209..209]) # sel[92..92]), ((! nose[208..208]) # sel[91..91]), (! nose[207..207]), (! nose[206..206]), (! nose[205..205]), (! nose[204..204]), (! nose[203..203]), (! nose[202..202]), (! nose[201..201]), (! nose[200..200]), (! nose[199..199]), ((! nose[198..198]) # sel[90..90]), ((! nose[197..197]) # sel[89..89]), ((! nose[196..196]) # sel[88..88]), ((! nose[195..195]) # sel[87..87]), ((! nose[194..194]) # sel[86..86]), ((! nose[193..193]) # sel[85..85]), ((! nose[192..192]) # sel[84..84]), (! nose[191..191]), (! nose[190..190]), (! nose[189..189]), (! nose[188..188]), (! nose[187..187]), (! nose[186..186]), (! nose[185..185]), (! nose[184..184]), (! nose[183..183]), ((! nose[182..182]) # sel[83..83]), ((! nose[181..181]) # sel[82..82]), ((! nose[180..180]) # sel[81..81]), ((! nose[179..179]) # sel[80..80]), ((! nose[178..178]) # sel[79..79]), ((! nose[177..177]) # sel[78..78]), ((! nose[176..176]) # sel[77..77]), (! nose[175..175]), (! nose[174..174]), (! nose[173..173]), (! nose[172..172]), (! nose[171..171]), (! nose[170..170]), (! nose[169..169]), (! nose[168..168]), (! nose[167..167]), ((! nose[166..166]) # sel[76..76]), ((! nose[165..165]) # sel[75..75]), ((! nose[164..164]) # sel[74..74]), ((! nose[163..163]) # sel[73..73]), ((! nose[162..162]) # sel[72..72]), ((! nose[161..161]) # sel[71..71]), ((! nose[160..160]) # sel[70..70]), (! nose[159..159]), (! nose[158..158]), (! nose[157..157]), (! nose[156..156]), (! nose[155..155]), (! nose[154..154]), (! nose[153..153]), (! nose[152..152]), (! nose[151..151]), ((! nose[150..150]) # sel[69..69]), ((! nose[149..149]) # sel[68..68]), ((! nose[148..148]) # sel[67..67]), ((! nose[147..147]) # sel[66..66]), ((! nose[146..146]) # sel[65..65]), ((! nose[145..145]) # sel[64..64]), ((! nose[144..144]) # sel[63..63]), (! nose[143..143]), (! nose[142..142]), (! nose[141..141]), (! nose[140..140]), (! nose[139..139]), (! nose[138..138]), (! nose[137..137]), (! nose[136..136]), (! nose[135..135]), ((! nose[134..134]) # sel[62..62]), ((! nose[133..133]) # sel[61..61]), ((! nose[132..132]) # sel[60..60]), ((! nose[131..131]) # sel[59..59]), ((! nose[130..130]) # sel[58..58]), ((! nose[129..129]) # sel[57..57]), ((! nose[128..128]) # sel[56..56]), (! nose[127..127]), (! nose[126..126]), (! nose[125..125]), (! nose[124..124]), (! nose[123..123]), (! nose[122..122]), (! nose[121..121]), (! nose[120..120]), (! nose[119..119]), ((! nose[118..118]) # sel[55..55]), ((! nose[117..117]) # sel[54..54]), ((! nose[116..116]) # sel[53..53]), ((! nose[115..115]) # sel[52..52]), ((! nose[114..114]) # sel[51..51]), ((! nose[113..113]) # sel[50..50]), ((! nose[112..112]) # sel[49..49]), (! nose[111..111]), (! nose[110..110]), (! nose[109..109]), (! nose[108..108]), (! nose[107..107]), (! nose[106..106]), (! nose[105..105]), (! nose[104..104]), (! nose[103..103]), ((! nose[102..102]) # sel[48..48]), ((! nose[101..101]) # sel[47..47]), ((! nose[100..100]) # sel[46..46]), ((! nose[99..99]) # sel[45..45]), ((! nose[98..98]) # sel[44..44]), ((! nose[97..97]) # sel[43..43]), ((! nose[96..96]) # sel[42..42]), (! nose[95..95]), (! nose[94..94]), (! nose[93..93]), (! nose[92..92]), (! nose[91..91]), (! nose[90..90]), (! nose[89..89]), (! nose[88..88]), (! nose[87..87]), ((! nose[86..86]) # sel[41..41]), ((! nose[85..85]) # sel[40..40]), ((! nose[84..84]) # sel[39..39]), ((! nose[83..83]) # sel[38..38]), ((! nose[82..82]) # sel[37..37]), ((! nose[81..81]) # sel[36..36]), ((! nose[80..80]) # sel[35..35]), (! nose[79..79]), (! nose[78..78]), (! nose[77..77]), (! nose[76..76]), (! nose[75..75]), (! nose[74..74]), (! nose[73..73]), (! nose[72..72]), (! nose[71..71]), ((! nose[70..70]) # sel[34..34]), ((! nose[69..69]) # sel[33..33]), ((! nose[68..68]) # sel[32..32]), ((! nose[67..67]) # sel[31..31]), ((! nose[66..66]) # sel[30..30]), ((! nose[65..65]) # sel[29..29]), ((! nose[64..64]) # sel[28..28]), (! nose[63..63]), (! nose[62..62]), (! nose[61..61]), (! nose[60..60]), (! nose[59..59]), (! nose[58..58]), (! nose[57..57]), (! nose[56..56]), (! nose[55..55]), ((! nose[54..54]) # sel[27..27]), ((! nose[53..53]) # sel[26..26]), ((! nose[52..52]) # sel[25..25]), ((! nose[51..51]) # sel[24..24]), ((! nose[50..50]) # sel[23..23]), ((! nose[49..49]) # sel[22..22]), ((! nose[48..48]) # sel[21..21]), (! nose[47..47]), (! nose[46..46]), (! nose[45..45]), (! nose[44..44]), (! nose[43..43]), (! nose[42..42]), (! nose[41..41]), (! nose[40..40]), (! nose[39..39]), ((! nose[38..38]) # sel[20..20]), ((! nose[37..37]) # sel[19..19]), ((! nose[36..36]) # sel[18..18]), ((! nose[35..35]) # sel[17..17]), ((! nose[34..34]) # sel[16..16]), ((! nose[33..33]) # sel[15..15]), ((! nose[32..32]) # sel[14..14]), (! nose[31..31]), (! nose[30..30]), (! nose[29..29]), (! nose[28..28]), (! nose[27..27]), (! nose[26..26]), (! nose[25..25]), (! nose[24..24]), (! nose[23..23]), ((! nose[22..22]) # sel[13..13]), ((! nose[21..21]) # sel[12..12]), ((! nose[20..20]) # sel[11..11]), ((! nose[19..19]) # sel[10..10]), ((! nose[18..18]) # sel[9..9]), ((! nose[17..17]) # sel[8..8]), ((! nose[16..16]) # sel[7..7]), (! nose[15..15]), (! nose[14..14]), (! nose[13..13]), (! nose[12..12]), (! nose[11..11]), (! nose[10..10]), (! nose[9..9]), (! nose[8..8]), (! nose[7..7]), ((! nose[6..6]) # sel[6..6]), ((! nose[5..5]) # sel[5..5]), ((! nose[4..4]) # sel[4..4]), ((! nose[3..3]) # sel[3..3]), ((! nose[2..2]) # sel[2..2]), ((! nose[1..1]) # sel[1..1]), ((! nose[0..0]) # sel[0..0]));
- StageIn[] = StageIn_tmp[];
- StageIn_tmp[] = ( StageOut[127..0], B"00000000");
- StageOut[] = ( ((( StageIn[126..120], NumeratorIn[240..240]) & selnose[255..255]) # (prestg[127..120] & (! selnose[255..255]))), ((( StageIn[118..112], NumeratorIn[225..225]) & selnose[238..238]) # (prestg[119..112] & (! selnose[238..238]))), ((( StageIn[110..104], NumeratorIn[210..210]) & selnose[221..221]) # (prestg[111..104] & (! selnose[221..221]))), ((( StageIn[102..96], NumeratorIn[195..195]) & selnose[204..204]) # (prestg[103..96] & (! selnose[204..204]))), ((( StageIn[94..88], NumeratorIn[180..180]) & selnose[187..187]) # (prestg[95..88] & (! selnose[187..187]))), ((( StageIn[86..80], NumeratorIn[165..165]) & selnose[170..170]) # (prestg[87..80] & (! selnose[170..170]))), ((( StageIn[78..72], NumeratorIn[150..150]) & selnose[153..153]) # (prestg[79..72] & (! selnose[153..153]))), ((( StageIn[70..64], NumeratorIn[135..135]) & selnose[136..136]) # (prestg[71..64] & (! selnose[136..136]))), ((( StageIn[62..56], NumeratorIn[120..120]) & selnose[119..119]) # (prestg[63..56] & (! selnose[119..119]))), ((( StageIn[54..48], NumeratorIn[105..105]) & selnose[102..102]) # (prestg[55..48] & (! selnose[102..102]))), ((( StageIn[46..40], NumeratorIn[90..90]) & selnose[85..85]) # (prestg[47..40] & (! selnose[85..85]))), ((( StageIn[38..32], NumeratorIn[75..75]) & selnose[68..68]) # (prestg[39..32] & (! selnose[68..68]))), ((( StageIn[30..24], NumeratorIn[60..60]) & selnose[51..51]) # (prestg[31..24] & (! selnose[51..51]))), ((( StageIn[22..16], NumeratorIn[45..45]) & selnose[34..34]) # (prestg[23..16] & (! selnose[34..34]))), ((( StageIn[14..8], NumeratorIn[30..30]) & selnose[17..17]) # (prestg[15..8] & (! selnose[17..17]))), ((( StageIn[6..0], NumeratorIn[15..15]) & selnose[0..0]) # (prestg[7..0] & (! selnose[0..0]))));
-END;
---VALID FILE
diff --git a/db/lpm_divide_2jm.tdf b/db/lpm_divide_2jm.tdf
deleted file mode 100644
index c54c10b..0000000
--- a/db/lpm_divide_2jm.tdf
+++ /dev/null
@@ -1,43 +0,0 @@
---lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION sign_div_unsign_qlh (denominator[3..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[3..0]);
-
---synthesis_resources = lut 81
-SUBDESIGN lpm_divide_2jm
-(
- denom[3..0] : input;
- numer[15..0] : input;
- quotient[15..0] : output;
- remain[3..0] : output;
-)
-VARIABLE
- divider : sign_div_unsign_qlh;
- numer_tmp[15..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denom[];
- divider.numerator[] = numer_tmp[];
- numer_tmp[] = numer[];
- quotient[] = divider.quotient[];
- remain[] = divider.remainder[];
-END;
---VALID FILE
diff --git a/db/lpm_divide_5bm.tdf b/db/lpm_divide_5bm.tdf
deleted file mode 100644
index a53fb4a..0000000
--- a/db/lpm_divide_5bm.tdf
+++ /dev/null
@@ -1,43 +0,0 @@
---lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer remain CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION sign_div_unsign_qlh (denominator[3..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[3..0]);
-
---synthesis_resources =
-SUBDESIGN lpm_divide_5bm
-(
- denom[3..0] : input;
- numer[15..0] : input;
- quotient[15..0] : output;
- remain[3..0] : output;
-)
-VARIABLE
- divider : sign_div_unsign_qlh;
- numer_tmp[15..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denom[];
- divider.numerator[] = numer_tmp[];
- numer_tmp[] = numer[];
- quotient[] = divider.quotient[];
- remain[] = divider.remainder[];
-END;
---VALID FILE
diff --git a/db/lpm_divide_5jm.tdf b/db/lpm_divide_5jm.tdf
deleted file mode 100644
index 45b989d..0000000
--- a/db/lpm_divide_5jm.tdf
+++ /dev/null
@@ -1,43 +0,0 @@
---lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=7 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION sign_div_unsign_tlh (denominator[6..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[6..0]);
-
---synthesis_resources = lut 111
-SUBDESIGN lpm_divide_5jm
-(
- denom[6..0] : input;
- numer[15..0] : input;
- quotient[15..0] : output;
- remain[6..0] : output;
-)
-VARIABLE
- divider : sign_div_unsign_tlh;
- numer_tmp[15..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denom[];
- divider.numerator[] = numer_tmp[];
- numer_tmp[] = numer[];
- quotient[] = divider.quotient[];
- remain[] = divider.remainder[];
-END;
---VALID FILE
diff --git a/db/lpm_divide_fkm.tdf b/db/lpm_divide_fkm.tdf
deleted file mode 100644
index 4d8b829..0000000
--- a/db/lpm_divide_fkm.tdf
+++ /dev/null
@@ -1,43 +0,0 @@
---lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=10 LPM_WIDTHN=16 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF"
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION sign_div_unsign_7nh (denominator[9..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[9..0]);
-
---synthesis_resources = lut 132
-SUBDESIGN lpm_divide_fkm
-(
- denom[9..0] : input;
- numer[15..0] : input;
- quotient[15..0] : output;
- remain[9..0] : output;
-)
-VARIABLE
- divider : sign_div_unsign_7nh;
- numer_tmp[15..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denom[];
- divider.numerator[] = numer_tmp[];
- numer_tmp[] = numer[];
- quotient[] = divider.quotient[];
- remain[] = divider.remainder[];
-END;
---VALID FILE
diff --git a/db/lvds_monitor.(0).cnf.cdb b/db/lvds_monitor.(0).cnf.cdb
deleted file mode 100644
index 4efa79a..0000000
Binary files a/db/lvds_monitor.(0).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(0).cnf.hdb b/db/lvds_monitor.(0).cnf.hdb
deleted file mode 100644
index edb0150..0000000
Binary files a/db/lvds_monitor.(0).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(1).cnf.cdb b/db/lvds_monitor.(1).cnf.cdb
deleted file mode 100644
index 24330ef..0000000
Binary files a/db/lvds_monitor.(1).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(1).cnf.hdb b/db/lvds_monitor.(1).cnf.hdb
deleted file mode 100644
index 148f709..0000000
Binary files a/db/lvds_monitor.(1).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(10).cnf.cdb b/db/lvds_monitor.(10).cnf.cdb
deleted file mode 100644
index e9e20ac..0000000
Binary files a/db/lvds_monitor.(10).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(10).cnf.hdb b/db/lvds_monitor.(10).cnf.hdb
deleted file mode 100644
index 960ae6a..0000000
Binary files a/db/lvds_monitor.(10).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(11).cnf.cdb b/db/lvds_monitor.(11).cnf.cdb
deleted file mode 100644
index eba47d8..0000000
Binary files a/db/lvds_monitor.(11).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(11).cnf.hdb b/db/lvds_monitor.(11).cnf.hdb
deleted file mode 100644
index 2a2da5d..0000000
Binary files a/db/lvds_monitor.(11).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(12).cnf.cdb b/db/lvds_monitor.(12).cnf.cdb
deleted file mode 100644
index 1cc59a8..0000000
Binary files a/db/lvds_monitor.(12).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(12).cnf.hdb b/db/lvds_monitor.(12).cnf.hdb
deleted file mode 100644
index 6f8ec01..0000000
Binary files a/db/lvds_monitor.(12).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(13).cnf.cdb b/db/lvds_monitor.(13).cnf.cdb
deleted file mode 100644
index 0c0d973..0000000
Binary files a/db/lvds_monitor.(13).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(13).cnf.hdb b/db/lvds_monitor.(13).cnf.hdb
deleted file mode 100644
index 98165f7..0000000
Binary files a/db/lvds_monitor.(13).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(14).cnf.cdb b/db/lvds_monitor.(14).cnf.cdb
deleted file mode 100644
index 6e41b01..0000000
Binary files a/db/lvds_monitor.(14).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(14).cnf.hdb b/db/lvds_monitor.(14).cnf.hdb
deleted file mode 100644
index 883fed0..0000000
Binary files a/db/lvds_monitor.(14).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(15).cnf.cdb b/db/lvds_monitor.(15).cnf.cdb
deleted file mode 100644
index 3d45caf..0000000
Binary files a/db/lvds_monitor.(15).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(15).cnf.hdb b/db/lvds_monitor.(15).cnf.hdb
deleted file mode 100644
index 43948d7..0000000
Binary files a/db/lvds_monitor.(15).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(16).cnf.cdb b/db/lvds_monitor.(16).cnf.cdb
deleted file mode 100644
index e5058d6..0000000
Binary files a/db/lvds_monitor.(16).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(16).cnf.hdb b/db/lvds_monitor.(16).cnf.hdb
deleted file mode 100644
index 38cf8ec..0000000
Binary files a/db/lvds_monitor.(16).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(17).cnf.cdb b/db/lvds_monitor.(17).cnf.cdb
deleted file mode 100644
index 30ede65..0000000
Binary files a/db/lvds_monitor.(17).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(17).cnf.hdb b/db/lvds_monitor.(17).cnf.hdb
deleted file mode 100644
index 8c416d3..0000000
Binary files a/db/lvds_monitor.(17).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(18).cnf.cdb b/db/lvds_monitor.(18).cnf.cdb
deleted file mode 100644
index 032abda..0000000
Binary files a/db/lvds_monitor.(18).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(18).cnf.hdb b/db/lvds_monitor.(18).cnf.hdb
deleted file mode 100644
index 6d6f23d..0000000
Binary files a/db/lvds_monitor.(18).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(2).cnf.cdb b/db/lvds_monitor.(2).cnf.cdb
deleted file mode 100644
index ab7e08f..0000000
Binary files a/db/lvds_monitor.(2).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(2).cnf.hdb b/db/lvds_monitor.(2).cnf.hdb
deleted file mode 100644
index 45d5724..0000000
Binary files a/db/lvds_monitor.(2).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(3).cnf.cdb b/db/lvds_monitor.(3).cnf.cdb
deleted file mode 100644
index 0577556..0000000
Binary files a/db/lvds_monitor.(3).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(3).cnf.hdb b/db/lvds_monitor.(3).cnf.hdb
deleted file mode 100644
index 6ce2c3b..0000000
Binary files a/db/lvds_monitor.(3).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(4).cnf.cdb b/db/lvds_monitor.(4).cnf.cdb
deleted file mode 100644
index f91cbbb..0000000
Binary files a/db/lvds_monitor.(4).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(4).cnf.hdb b/db/lvds_monitor.(4).cnf.hdb
deleted file mode 100644
index 13bd0ec..0000000
Binary files a/db/lvds_monitor.(4).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(5).cnf.cdb b/db/lvds_monitor.(5).cnf.cdb
deleted file mode 100644
index ba3ad41..0000000
Binary files a/db/lvds_monitor.(5).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(5).cnf.hdb b/db/lvds_monitor.(5).cnf.hdb
deleted file mode 100644
index 1a06559..0000000
Binary files a/db/lvds_monitor.(5).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(6).cnf.cdb b/db/lvds_monitor.(6).cnf.cdb
deleted file mode 100644
index db608b1..0000000
Binary files a/db/lvds_monitor.(6).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(6).cnf.hdb b/db/lvds_monitor.(6).cnf.hdb
deleted file mode 100644
index 5ccebed..0000000
Binary files a/db/lvds_monitor.(6).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(7).cnf.cdb b/db/lvds_monitor.(7).cnf.cdb
deleted file mode 100644
index 490b02d..0000000
Binary files a/db/lvds_monitor.(7).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(7).cnf.hdb b/db/lvds_monitor.(7).cnf.hdb
deleted file mode 100644
index e37d5d3..0000000
Binary files a/db/lvds_monitor.(7).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(8).cnf.cdb b/db/lvds_monitor.(8).cnf.cdb
deleted file mode 100644
index bda0089..0000000
Binary files a/db/lvds_monitor.(8).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(8).cnf.hdb b/db/lvds_monitor.(8).cnf.hdb
deleted file mode 100644
index 8257cf1..0000000
Binary files a/db/lvds_monitor.(8).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.(9).cnf.cdb b/db/lvds_monitor.(9).cnf.cdb
deleted file mode 100644
index 3189859..0000000
Binary files a/db/lvds_monitor.(9).cnf.cdb and /dev/null differ
diff --git a/db/lvds_monitor.(9).cnf.hdb b/db/lvds_monitor.(9).cnf.hdb
deleted file mode 100644
index 5311903..0000000
Binary files a/db/lvds_monitor.(9).cnf.hdb and /dev/null differ
diff --git a/db/lvds_monitor.asm.qmsg b/db/lvds_monitor.asm.qmsg
deleted file mode 100644
index 8575edc..0000000
--- a/db/lvds_monitor.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075228905 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075228905 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:07:08 2026 " "Processing started: Wed Jun 10 09:07:08 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075228905 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1781075228905 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor " "Command: quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1781075228905 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1781075229287 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1781075229298 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4744 " "Peak virtual memory: 4744 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075229383 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:09 2026 " "Processing ended: Wed Jun 10 09:07:09 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075229383 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075229383 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075229383 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1781075229383 ""}
diff --git a/db/lvds_monitor.asm.rdb b/db/lvds_monitor.asm.rdb
deleted file mode 100644
index 6a32ba5..0000000
Binary files a/db/lvds_monitor.asm.rdb and /dev/null differ
diff --git a/db/lvds_monitor.asm_labs.ddb b/db/lvds_monitor.asm_labs.ddb
deleted file mode 100644
index 9210a31..0000000
Binary files a/db/lvds_monitor.asm_labs.ddb and /dev/null differ
diff --git a/db/lvds_monitor.cbx.xml b/db/lvds_monitor.cbx.xml
deleted file mode 100644
index cea5f84..0000000
--- a/db/lvds_monitor.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-
-
-
-
-
diff --git a/db/lvds_monitor.cmp.bpm b/db/lvds_monitor.cmp.bpm
deleted file mode 100644
index 1a7de98..0000000
Binary files a/db/lvds_monitor.cmp.bpm and /dev/null differ
diff --git a/db/lvds_monitor.cmp.cdb b/db/lvds_monitor.cmp.cdb
deleted file mode 100644
index 932239f..0000000
Binary files a/db/lvds_monitor.cmp.cdb and /dev/null differ
diff --git a/db/lvds_monitor.cmp.hdb b/db/lvds_monitor.cmp.hdb
deleted file mode 100644
index 3813a09..0000000
Binary files a/db/lvds_monitor.cmp.hdb and /dev/null differ
diff --git a/db/lvds_monitor.cmp.idb b/db/lvds_monitor.cmp.idb
deleted file mode 100644
index b30fcd3..0000000
Binary files a/db/lvds_monitor.cmp.idb and /dev/null differ
diff --git a/db/lvds_monitor.cmp.logdb b/db/lvds_monitor.cmp.logdb
deleted file mode 100644
index b7982a1..0000000
--- a/db/lvds_monitor.cmp.logdb
+++ /dev/null
@@ -1,48 +0,0 @@
-v1
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
-IO_RULES_MATRIX,Total Pass,7;0;7;0;0;7;7;0;7;7;0;0;0;0;6;0;0;6;0;0;0;0;0;0;0;0;0;7;0;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,0;7;0;7;7;0;0;7;0;0;7;7;7;7;1;7;7;1;7;7;7;7;7;7;7;7;7;0;7;7,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,vsync,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,hsync,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,uart_tx_pin,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,clk_50mhz,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,rst_n_pin,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,rx_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_MATRIX,de,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,30,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
diff --git a/db/lvds_monitor.cmp.rdb b/db/lvds_monitor.cmp.rdb
deleted file mode 100644
index e0734df..0000000
Binary files a/db/lvds_monitor.cmp.rdb and /dev/null differ
diff --git a/db/lvds_monitor.cmp_merge.kpt b/db/lvds_monitor.cmp_merge.kpt
deleted file mode 100644
index 7bb0fd4..0000000
Binary files a/db/lvds_monitor.cmp_merge.kpt and /dev/null differ
diff --git a/db/lvds_monitor.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/db/lvds_monitor.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
deleted file mode 100644
index 1d92ce1..0000000
Binary files a/db/lvds_monitor.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd and /dev/null differ
diff --git a/db/lvds_monitor.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/db/lvds_monitor.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
deleted file mode 100644
index 12b712b..0000000
Binary files a/db/lvds_monitor.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd and /dev/null differ
diff --git a/db/lvds_monitor.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/db/lvds_monitor.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
deleted file mode 100644
index 1d0d4c2..0000000
Binary files a/db/lvds_monitor.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd and /dev/null differ
diff --git a/db/lvds_monitor.db_info b/db/lvds_monitor.db_info
deleted file mode 100644
index 665592d..0000000
--- a/db/lvds_monitor.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-Version_Index = 604268800
-Creation_Time = Wed Jun 10 08:48:23 2026
diff --git a/db/lvds_monitor.fit.qmsg b/db/lvds_monitor.fit.qmsg
deleted file mode 100644
index 926f200..0000000
--- a/db/lvds_monitor.fit.qmsg
+++ /dev/null
@@ -1,49 +0,0 @@
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1781075223819 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "lvds_monitor EP4CE6E22C8 " "Selected device EP4CE6E22C8 for design \"lvds_monitor\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1781075223828 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1781075223859 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1781075223859 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1781075223932 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1781075223935 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C8 " "Device EP4CE10E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1781075223991 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C8 " "Device EP4CE15E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1781075223991 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C8 " "Device EP4CE22E22C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1781075223991 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1781075223991 ""}
-{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3188 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3190 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3192 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3194 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1781075223993 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1781075223993 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1781075223994 ""}
-{ "Info" "ISTA_SDC_FOUND" "lvds_monitor.sdc " "Reading SDC File: 'lvds_monitor.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1781075224324 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Fitter" 0 -1 1781075224326 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1781075224335 ""}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1781075224335 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 clk_50mhz " " 20.000 clk_50mhz" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 13.500 rx_clk " " 13.500 rx_clk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1781075224335 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1781075224335 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rx_clk~input (placed in PIN 30 (DIFFIO_L8p, DQS1L/CQ1L#,DPCLK1)) " "Automatically promoted node rx_clk~input (placed in PIN 30 (DIFFIO_L8p, DQS1L/CQ1L#,DPCLK1))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 24 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3184 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_50mhz~input (placed in PIN 24 (CLK2, DIFFCLK_1p)) " "Automatically promoted node clk_50mhz~input (placed in PIN 24 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 23 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3182 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n_pin~input (placed in PIN 88 (CLK7, DIFFCLK_3n)) " "Automatically promoted node rst_n_pin~input (placed in PIN 88 (CLK7, DIFFCLK_3n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 28 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 3183 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_sync_pix\[2\] " "Automatically promoted node rst_sync_pix\[2\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 57 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 200 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
-{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_sync_uart\[2\] " "Automatically promoted node rst_sync_uart\[2\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1781075224426 ""} } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 51 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 197 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1781075224426 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1781075224604 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1781075224605 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1781075224605 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1781075224606 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1781075224607 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1781075224607 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1781075224608 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1781075224608 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1781075224655 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1781075224655 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1781075224655 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075224675 ""}
-{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1781075224680 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1781075225007 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075225151 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1781075225164 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1781075225798 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075225798 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1781075226066 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1781075226561 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1781075226561 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1781075226671 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1781075226671 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1781075226671 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075226672 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.33 " "Total time spent on timing analysis during the Fitter is 0.33 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1781075226756 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1781075226769 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1781075226945 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1781075226946 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1781075227149 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1781075227477 ""}
-{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "6 Cyclone IV E " "6 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "vsync 3.3-V LVTTL 32 " "Pin vsync uses I/O standard 3.3-V LVTTL at 32" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { vsync } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "vsync" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 26 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "hsync 3.3-V LVTTL 33 " "Pin hsync uses I/O standard 3.3-V LVTTL at 33" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { hsync } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "hsync" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 27 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk_50mhz 3.3-V LVTTL 24 " "Pin clk_50mhz uses I/O standard 3.3-V LVTTL at 24" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { clk_50mhz } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk_50mhz" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 23 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 5 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n_pin 3.3-V LVTTL 88 " "Pin rst_n_pin uses I/O standard 3.3-V LVTTL at 88" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { rst_n_pin } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n_pin" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 28 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rx_clk 3.3-V LVTTL 30 " "Pin rx_clk uses I/O standard 3.3-V LVTTL at 30" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { rx_clk } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rx_clk" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 24 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 6 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "de 3.3-V LVTTL 31 " "Pin de uses I/O standard 3.3-V LVTTL at 31" { } { { "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/25.1std/quartus/bin64/pin_planner.ppl" { de } } } { "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/25.1std/quartus/bin64/Assignment Editor.qase" 1 { { 0 "de" } } } } { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 25 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/DavidRice/Documents/fpga/lvds_monitor/" { { 0 { 0 ""} 0 7 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1781075227622 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1781075227622 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.fit.smsg " "Generated suppressed messages file C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1781075227671 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "6367 " "Peak virtual memory: 6367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075227977 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:07 2026 " "Processing ended: Wed Jun 10 09:07:07 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075227977 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075227977 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075227977 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1781075227977 ""}
diff --git a/db/lvds_monitor.hier_info b/db/lvds_monitor.hier_info
deleted file mode 100644
index 148889c..0000000
--- a/db/lvds_monitor.hier_info
+++ /dev/null
@@ -1,463 +0,0 @@
-|top
-clk_50mhz => clk_uart.IN1
-rx_clk => rx_clk.IN1
-de => de.IN1
-vsync => ~NO_FANOUT~
-hsync => ~NO_FANOUT~
-rst_n_pin => rst_sync_uart[0].ACLR
-rst_n_pin => rst_sync_uart[1].ACLR
-rst_n_pin => rst_sync_uart[2].ACLR
-rst_n_pin => rst_sync_pix[0].ACLR
-rst_n_pin => rst_sync_pix[1].ACLR
-rst_n_pin => rst_sync_pix[2].ACLR
-uart_tx_pin << uart_tx:u_uart.tx
-
-
-|top|de_monitor:u_mon
-pix_clk => anomaly_o~reg0.CLK
-pix_clk => width_o[0]~reg0.CLK
-pix_clk => width_o[1]~reg0.CLK
-pix_clk => width_o[2]~reg0.CLK
-pix_clk => width_o[3]~reg0.CLK
-pix_clk => width_o[4]~reg0.CLK
-pix_clk => width_o[5]~reg0.CLK
-pix_clk => width_o[6]~reg0.CLK
-pix_clk => width_o[7]~reg0.CLK
-pix_clk => width_o[8]~reg0.CLK
-pix_clk => width_o[9]~reg0.CLK
-pix_clk => width_o[10]~reg0.CLK
-pix_clk => width_o[11]~reg0.CLK
-pix_clk => width_o[12]~reg0.CLK
-pix_clk => width_o[13]~reg0.CLK
-pix_clk => width_o[14]~reg0.CLK
-pix_clk => width_o[15]~reg0.CLK
-pix_clk => lines_o[0]~reg0.CLK
-pix_clk => lines_o[1]~reg0.CLK
-pix_clk => lines_o[2]~reg0.CLK
-pix_clk => lines_o[3]~reg0.CLK
-pix_clk => lines_o[4]~reg0.CLK
-pix_clk => lines_o[5]~reg0.CLK
-pix_clk => lines_o[6]~reg0.CLK
-pix_clk => lines_o[7]~reg0.CLK
-pix_clk => lines_o[8]~reg0.CLK
-pix_clk => lines_o[9]~reg0.CLK
-pix_clk => lines_o[10]~reg0.CLK
-pix_clk => lines_o[11]~reg0.CLK
-pix_clk => lines_o[12]~reg0.CLK
-pix_clk => lines_o[13]~reg0.CLK
-pix_clk => lines_o[14]~reg0.CLK
-pix_clk => lines_o[15]~reg0.CLK
-pix_clk => frame_done~reg0.CLK
-pix_clk => frame_active.CLK
-pix_clk => gap_count[0].CLK
-pix_clk => gap_count[1].CLK
-pix_clk => gap_count[2].CLK
-pix_clk => gap_count[3].CLK
-pix_clk => gap_count[4].CLK
-pix_clk => gap_count[5].CLK
-pix_clk => gap_count[6].CLK
-pix_clk => gap_count[7].CLK
-pix_clk => gap_count[8].CLK
-pix_clk => gap_count[9].CLK
-pix_clk => gap_count[10].CLK
-pix_clk => gap_count[11].CLK
-pix_clk => gap_count[12].CLK
-pix_clk => gap_count[13].CLK
-pix_clk => gap_count[14].CLK
-pix_clk => gap_count[15].CLK
-pix_clk => line_count[0].CLK
-pix_clk => line_count[1].CLK
-pix_clk => line_count[2].CLK
-pix_clk => line_count[3].CLK
-pix_clk => line_count[4].CLK
-pix_clk => line_count[5].CLK
-pix_clk => line_count[6].CLK
-pix_clk => line_count[7].CLK
-pix_clk => line_count[8].CLK
-pix_clk => line_count[9].CLK
-pix_clk => line_count[10].CLK
-pix_clk => line_count[11].CLK
-pix_clk => line_count[12].CLK
-pix_clk => line_count[13].CLK
-pix_clk => line_count[14].CLK
-pix_clk => line_count[15].CLK
-pix_clk => any_bad_width.CLK
-pix_clk => bad_width[0].CLK
-pix_clk => bad_width[1].CLK
-pix_clk => bad_width[2].CLK
-pix_clk => bad_width[3].CLK
-pix_clk => bad_width[4].CLK
-pix_clk => bad_width[5].CLK
-pix_clk => bad_width[6].CLK
-pix_clk => bad_width[7].CLK
-pix_clk => bad_width[8].CLK
-pix_clk => bad_width[9].CLK
-pix_clk => bad_width[10].CLK
-pix_clk => bad_width[11].CLK
-pix_clk => bad_width[12].CLK
-pix_clk => bad_width[13].CLK
-pix_clk => bad_width[14].CLK
-pix_clk => bad_width[15].CLK
-pix_clk => last_width[0].CLK
-pix_clk => last_width[1].CLK
-pix_clk => last_width[2].CLK
-pix_clk => last_width[3].CLK
-pix_clk => last_width[4].CLK
-pix_clk => last_width[5].CLK
-pix_clk => last_width[6].CLK
-pix_clk => last_width[7].CLK
-pix_clk => last_width[8].CLK
-pix_clk => last_width[9].CLK
-pix_clk => last_width[10].CLK
-pix_clk => last_width[11].CLK
-pix_clk => last_width[12].CLK
-pix_clk => last_width[13].CLK
-pix_clk => last_width[14].CLK
-pix_clk => last_width[15].CLK
-pix_clk => line_width[0].CLK
-pix_clk => line_width[1].CLK
-pix_clk => line_width[2].CLK
-pix_clk => line_width[3].CLK
-pix_clk => line_width[4].CLK
-pix_clk => line_width[5].CLK
-pix_clk => line_width[6].CLK
-pix_clk => line_width[7].CLK
-pix_clk => line_width[8].CLK
-pix_clk => line_width[9].CLK
-pix_clk => line_width[10].CLK
-pix_clk => line_width[11].CLK
-pix_clk => line_width[12].CLK
-pix_clk => line_width[13].CLK
-pix_clk => line_width[14].CLK
-pix_clk => line_width[15].CLK
-pix_clk => de_q.CLK
-rst_n => anomaly_o~reg0.ACLR
-rst_n => width_o[0]~reg0.ACLR
-rst_n => width_o[1]~reg0.ACLR
-rst_n => width_o[2]~reg0.ACLR
-rst_n => width_o[3]~reg0.ACLR
-rst_n => width_o[4]~reg0.ACLR
-rst_n => width_o[5]~reg0.ACLR
-rst_n => width_o[6]~reg0.ACLR
-rst_n => width_o[7]~reg0.ACLR
-rst_n => width_o[8]~reg0.ACLR
-rst_n => width_o[9]~reg0.ACLR
-rst_n => width_o[10]~reg0.ACLR
-rst_n => width_o[11]~reg0.ACLR
-rst_n => width_o[12]~reg0.ACLR
-rst_n => width_o[13]~reg0.ACLR
-rst_n => width_o[14]~reg0.ACLR
-rst_n => width_o[15]~reg0.ACLR
-rst_n => lines_o[0]~reg0.ACLR
-rst_n => lines_o[1]~reg0.ACLR
-rst_n => lines_o[2]~reg0.ACLR
-rst_n => lines_o[3]~reg0.ACLR
-rst_n => lines_o[4]~reg0.ACLR
-rst_n => lines_o[5]~reg0.ACLR
-rst_n => lines_o[6]~reg0.ACLR
-rst_n => lines_o[7]~reg0.ACLR
-rst_n => lines_o[8]~reg0.ACLR
-rst_n => lines_o[9]~reg0.ACLR
-rst_n => lines_o[10]~reg0.ACLR
-rst_n => lines_o[11]~reg0.ACLR
-rst_n => lines_o[12]~reg0.ACLR
-rst_n => lines_o[13]~reg0.ACLR
-rst_n => lines_o[14]~reg0.ACLR
-rst_n => lines_o[15]~reg0.ACLR
-rst_n => frame_done~reg0.ACLR
-rst_n => frame_active.ACLR
-rst_n => gap_count[0].ACLR
-rst_n => gap_count[1].ACLR
-rst_n => gap_count[2].ACLR
-rst_n => gap_count[3].ACLR
-rst_n => gap_count[4].ACLR
-rst_n => gap_count[5].ACLR
-rst_n => gap_count[6].ACLR
-rst_n => gap_count[7].ACLR
-rst_n => gap_count[8].ACLR
-rst_n => gap_count[9].ACLR
-rst_n => gap_count[10].ACLR
-rst_n => gap_count[11].ACLR
-rst_n => gap_count[12].ACLR
-rst_n => gap_count[13].ACLR
-rst_n => gap_count[14].ACLR
-rst_n => gap_count[15].ACLR
-rst_n => line_count[0].ACLR
-rst_n => line_count[1].ACLR
-rst_n => line_count[2].ACLR
-rst_n => line_count[3].ACLR
-rst_n => line_count[4].ACLR
-rst_n => line_count[5].ACLR
-rst_n => line_count[6].ACLR
-rst_n => line_count[7].ACLR
-rst_n => line_count[8].ACLR
-rst_n => line_count[9].ACLR
-rst_n => line_count[10].ACLR
-rst_n => line_count[11].ACLR
-rst_n => line_count[12].ACLR
-rst_n => line_count[13].ACLR
-rst_n => line_count[14].ACLR
-rst_n => line_count[15].ACLR
-rst_n => any_bad_width.ACLR
-rst_n => bad_width[0].ACLR
-rst_n => bad_width[1].ACLR
-rst_n => bad_width[2].ACLR
-rst_n => bad_width[3].ACLR
-rst_n => bad_width[4].ACLR
-rst_n => bad_width[5].ACLR
-rst_n => bad_width[6].ACLR
-rst_n => bad_width[7].ACLR
-rst_n => bad_width[8].ACLR
-rst_n => bad_width[9].ACLR
-rst_n => bad_width[10].ACLR
-rst_n => bad_width[11].ACLR
-rst_n => bad_width[12].ACLR
-rst_n => bad_width[13].ACLR
-rst_n => bad_width[14].ACLR
-rst_n => bad_width[15].ACLR
-rst_n => last_width[0].ACLR
-rst_n => last_width[1].ACLR
-rst_n => last_width[2].ACLR
-rst_n => last_width[3].ACLR
-rst_n => last_width[4].ACLR
-rst_n => last_width[5].ACLR
-rst_n => last_width[6].ACLR
-rst_n => last_width[7].ACLR
-rst_n => last_width[8].ACLR
-rst_n => last_width[9].ACLR
-rst_n => last_width[10].ACLR
-rst_n => last_width[11].ACLR
-rst_n => last_width[12].ACLR
-rst_n => last_width[13].ACLR
-rst_n => last_width[14].ACLR
-rst_n => last_width[15].ACLR
-rst_n => line_width[0].ACLR
-rst_n => line_width[1].ACLR
-rst_n => line_width[2].ACLR
-rst_n => line_width[3].ACLR
-rst_n => line_width[4].ACLR
-rst_n => line_width[5].ACLR
-rst_n => line_width[6].ACLR
-rst_n => line_width[7].ACLR
-rst_n => line_width[8].ACLR
-rst_n => line_width[9].ACLR
-rst_n => line_width[10].ACLR
-rst_n => line_width[11].ACLR
-rst_n => line_width[12].ACLR
-rst_n => line_width[13].ACLR
-rst_n => line_width[14].ACLR
-rst_n => line_width[15].ACLR
-rst_n => de_q.ACLR
-de => de_rise.IN1
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => line_width.OUTPUTSELECT
-de => de_q.DATAIN
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => gap_count.OUTPUTSELECT
-de => frame_done.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => lines_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => width_o.OUTPUTSELECT
-de => anomaly_o.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => line_count.OUTPUTSELECT
-de => any_bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => bad_width.OUTPUTSELECT
-de => frame_active.OUTPUTSELECT
-de => de_fall.IN1
-frame_done <= frame_done~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[0] <= lines_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[1] <= lines_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[2] <= lines_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[3] <= lines_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[4] <= lines_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[5] <= lines_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[6] <= lines_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[7] <= lines_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[8] <= lines_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[9] <= lines_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[10] <= lines_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[11] <= lines_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[12] <= lines_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[13] <= lines_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[14] <= lines_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-lines_o[15] <= lines_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[0] <= width_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[1] <= width_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[2] <= width_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[3] <= width_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[4] <= width_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[5] <= width_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[6] <= width_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[7] <= width_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[8] <= width_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[9] <= width_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[10] <= width_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[11] <= width_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[12] <= width_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[13] <= width_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[14] <= width_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-width_o[15] <= width_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-anomaly_o <= anomaly_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|top|uart_tx:u_uart
-clk => busy~reg0.CLK
-clk => tx~reg0.CLK
-clk => shift[0].CLK
-clk => shift[1].CLK
-clk => shift[2].CLK
-clk => shift[3].CLK
-clk => shift[4].CLK
-clk => shift[5].CLK
-clk => shift[6].CLK
-clk => shift[7].CLK
-clk => tick[0].CLK
-clk => tick[1].CLK
-clk => tick[2].CLK
-clk => tick[3].CLK
-clk => tick[4].CLK
-clk => tick[5].CLK
-clk => tick[6].CLK
-clk => tick[7].CLK
-clk => tick[8].CLK
-clk => state~12.DATAIN
-rst_n => busy~reg0.ACLR
-rst_n => tx~reg0.PRESET
-rst_n => shift[0].ACLR
-rst_n => shift[1].ACLR
-rst_n => shift[2].ACLR
-rst_n => shift[3].ACLR
-rst_n => shift[4].ACLR
-rst_n => shift[5].ACLR
-rst_n => shift[6].ACLR
-rst_n => shift[7].ACLR
-rst_n => tick[0].ACLR
-rst_n => tick[1].ACLR
-rst_n => tick[2].ACLR
-rst_n => tick[3].ACLR
-rst_n => tick[4].ACLR
-rst_n => tick[5].ACLR
-rst_n => tick[6].ACLR
-rst_n => tick[7].ACLR
-rst_n => tick[8].ACLR
-rst_n => state~14.DATAIN
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => shift.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => state.OUTPUTSELECT
-start => busy.DATAB
-start => tx.DATAB
-data[0] => shift.DATAB
-data[1] => shift.DATAB
-data[2] => shift.DATAB
-data[3] => shift.DATAB
-data[4] => shift.DATAB
-data[5] => shift.DATAB
-data[6] => shift.DATAB
-data[7] => shift.DATAB
-tx <= tx~reg0.DB_MAX_OUTPUT_PORT_TYPE
-busy <= busy~reg0.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/db/lvds_monitor.hif b/db/lvds_monitor.hif
deleted file mode 100644
index 65721a6..0000000
Binary files a/db/lvds_monitor.hif and /dev/null differ
diff --git a/db/lvds_monitor.lpc.html b/db/lvds_monitor.lpc.html
deleted file mode 100644
index 1dd606f..0000000
--- a/db/lvds_monitor.lpc.html
+++ /dev/null
@@ -1,50 +0,0 @@
-
-
-| Hierarchy |
-Input |
-Constant Input |
-Unused Input |
-Floating Input |
-Output |
-Constant Output |
-Unused Output |
-Floating Output |
-Bidir |
-Constant Bidir |
-Unused Bidir |
-Input only Bidir |
-Output only Bidir |
-
-
-| u_uart |
-11 |
-0 |
-0 |
-0 |
-2 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
-| u_mon |
-3 |
-0 |
-0 |
-0 |
-34 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-0 |
-
-
diff --git a/db/lvds_monitor.lpc.rdb b/db/lvds_monitor.lpc.rdb
deleted file mode 100644
index 802bd88..0000000
Binary files a/db/lvds_monitor.lpc.rdb and /dev/null differ
diff --git a/db/lvds_monitor.lpc.txt b/db/lvds_monitor.lpc.txt
deleted file mode 100644
index de20728..0000000
--- a/db/lvds_monitor.lpc.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; u_uart ; 11 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; u_mon ; 3 ; 0 ; 0 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/db/lvds_monitor.map.ammdb b/db/lvds_monitor.map.ammdb
deleted file mode 100644
index 25b1b34..0000000
Binary files a/db/lvds_monitor.map.ammdb and /dev/null differ
diff --git a/db/lvds_monitor.map.bpm b/db/lvds_monitor.map.bpm
deleted file mode 100644
index c3dad79..0000000
Binary files a/db/lvds_monitor.map.bpm and /dev/null differ
diff --git a/db/lvds_monitor.map.cdb b/db/lvds_monitor.map.cdb
deleted file mode 100644
index a153884..0000000
Binary files a/db/lvds_monitor.map.cdb and /dev/null differ
diff --git a/db/lvds_monitor.map.hdb b/db/lvds_monitor.map.hdb
deleted file mode 100644
index e54c716..0000000
Binary files a/db/lvds_monitor.map.hdb and /dev/null differ
diff --git a/db/lvds_monitor.map.kpt b/db/lvds_monitor.map.kpt
deleted file mode 100644
index 1ad2930..0000000
Binary files a/db/lvds_monitor.map.kpt and /dev/null differ
diff --git a/db/lvds_monitor.map.logdb b/db/lvds_monitor.map.logdb
deleted file mode 100644
index 626799f..0000000
--- a/db/lvds_monitor.map.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/db/lvds_monitor.map.qmsg b/db/lvds_monitor.map.qmsg
deleted file mode 100644
index 6e42a4e..0000000
--- a/db/lvds_monitor.map.qmsg
+++ /dev/null
@@ -1,28 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075213461 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075213462 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:06:53 2026 " "Processing started: Wed Jun 10 09:06:53 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075213462 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075213462 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor " "Command: quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075213462 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1781075213684 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de_monitor.v 1 1 " "Found 1 design units, including 1 entities, in source file de_monitor.v" { { "Info" "ISGN_ENTITY_NAME" "1 de_monitor " "Found entity 1: de_monitor" { } { { "de_monitor.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218864 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218866 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1781075218867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075218867 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1781075218897 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "_unused top.v(33) " "Verilog HDL or VHDL warning at top.v(33): object \"_unused\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 33 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218900 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L0_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L0_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218900 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L1_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L1_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L2_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L2_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L3_r top.v(136) " "Verilog HDL or VHDL warning at top.v(136): object \"L3_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 136 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W0_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W0_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W1_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W1_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W2_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W2_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "W3_r top.v(137) " "Verilog HDL or VHDL warning at top.v(137): object \"W3_r\" assigned a value but never read" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 137 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 "|top"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "de_monitor de_monitor:u_mon " "Elaborating entity \"de_monitor\" for hierarchy \"de_monitor:u_mon\"" { } { { "top.v" "u_mon" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075218901 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart\"" { } { { "top.v" "u_uart" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 359 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075218903 ""}
-{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "uart_tx.v(60) " "Verilog HDL Case Statement information at uart_tx.v(60): all case item expressions in this case statement are onehot" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 60 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1781075218910 "|top|uart_tx:u_uart"}
-{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "uart_tx.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v" 18 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1781075219700 ""}
-{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1781075219700 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1781075220414 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1781075222360 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1781075222473 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1781075222473 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "2 " "Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "vsync " "No output dependent on input pin \"vsync\"" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 26 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1781075222547 "|top|vsync"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "hsync " "No output dependent on input pin \"hsync\"" { } { { "top.v" "" { Text "C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v" 27 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1781075222547 "|top|hsync"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1781075222547 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "2001 " "Implemented 2001 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1781075222547 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1781075222547 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1994 " "Implemented 1994 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1781075222547 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1781075222547 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4878 " "Peak virtual memory: 4878 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:02 2026 " "Processing ended: Wed Jun 10 09:07:02 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075222558 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1781075222558 ""}
diff --git a/db/lvds_monitor.map.rdb b/db/lvds_monitor.map.rdb
deleted file mode 100644
index a9bf265..0000000
Binary files a/db/lvds_monitor.map.rdb and /dev/null differ
diff --git a/db/lvds_monitor.map_bb.cdb b/db/lvds_monitor.map_bb.cdb
deleted file mode 100644
index d1d5f47..0000000
Binary files a/db/lvds_monitor.map_bb.cdb and /dev/null differ
diff --git a/db/lvds_monitor.map_bb.hdb b/db/lvds_monitor.map_bb.hdb
deleted file mode 100644
index bc5f3bd..0000000
Binary files a/db/lvds_monitor.map_bb.hdb and /dev/null differ
diff --git a/db/lvds_monitor.map_bb.logdb b/db/lvds_monitor.map_bb.logdb
deleted file mode 100644
index 626799f..0000000
--- a/db/lvds_monitor.map_bb.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/db/lvds_monitor.pre_map.hdb b/db/lvds_monitor.pre_map.hdb
deleted file mode 100644
index 73a7f1a..0000000
Binary files a/db/lvds_monitor.pre_map.hdb and /dev/null differ
diff --git a/db/lvds_monitor.root_partition.map.reg_db.cdb b/db/lvds_monitor.root_partition.map.reg_db.cdb
deleted file mode 100644
index 03e65dc..0000000
Binary files a/db/lvds_monitor.root_partition.map.reg_db.cdb and /dev/null differ
diff --git a/db/lvds_monitor.routing.rdb b/db/lvds_monitor.routing.rdb
deleted file mode 100644
index deab7c8..0000000
Binary files a/db/lvds_monitor.routing.rdb and /dev/null differ
diff --git a/db/lvds_monitor.rtlv.hdb b/db/lvds_monitor.rtlv.hdb
deleted file mode 100644
index 05f2df1..0000000
Binary files a/db/lvds_monitor.rtlv.hdb and /dev/null differ
diff --git a/db/lvds_monitor.rtlv_sg.cdb b/db/lvds_monitor.rtlv_sg.cdb
deleted file mode 100644
index adf588e..0000000
Binary files a/db/lvds_monitor.rtlv_sg.cdb and /dev/null differ
diff --git a/db/lvds_monitor.rtlv_sg_swap.cdb b/db/lvds_monitor.rtlv_sg_swap.cdb
deleted file mode 100644
index 80194d7..0000000
Binary files a/db/lvds_monitor.rtlv_sg_swap.cdb and /dev/null differ
diff --git a/db/lvds_monitor.sld_design_entry_dsc.sci b/db/lvds_monitor.sld_design_entry_dsc.sci
deleted file mode 100644
index eb0e36d..0000000
Binary files a/db/lvds_monitor.sld_design_entry_dsc.sci and /dev/null differ
diff --git a/db/lvds_monitor.smart_action.txt b/db/lvds_monitor.smart_action.txt
deleted file mode 100644
index c8e8a13..0000000
--- a/db/lvds_monitor.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/db/lvds_monitor.smp_dump.txt b/db/lvds_monitor.smp_dump.txt
deleted file mode 100644
index df2d123..0000000
--- a/db/lvds_monitor.smp_dump.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-
-State Machine - |top|fstate
-Name fstate.F_WAIT fstate.F_LOAD fstate.F_CONVERT fstate.F_IDLE
-fstate.F_IDLE 0 0 0 0
-fstate.F_CONVERT 0 0 1 1
-fstate.F_LOAD 0 1 0 1
-fstate.F_WAIT 1 0 0 1
-
-State Machine - |top|uart_tx:u_uart|state
-Name state.S_STOP state.S_D7 state.S_D6 state.S_D5 state.S_D4 state.S_D3 state.S_D2 state.S_D1 state.S_D0 state.S_START state.S_IDLE
-state.S_IDLE 0 0 0 0 0 0 0 0 0 0 0
-state.S_START 0 0 0 0 0 0 0 0 0 1 1
-state.S_D0 0 0 0 0 0 0 0 0 1 0 1
-state.S_D1 0 0 0 0 0 0 0 1 0 0 1
-state.S_D2 0 0 0 0 0 0 1 0 0 0 1
-state.S_D3 0 0 0 0 0 1 0 0 0 0 1
-state.S_D4 0 0 0 0 1 0 0 0 0 0 1
-state.S_D5 0 0 0 1 0 0 0 0 0 0 1
-state.S_D6 0 0 1 0 0 0 0 0 0 0 1
-state.S_D7 0 1 0 0 0 0 0 0 0 0 1
-state.S_STOP 1 0 0 0 0 0 0 0 0 0 1
diff --git a/db/lvds_monitor.sta.qmsg b/db/lvds_monitor.sta.qmsg
deleted file mode 100644
index 16a545e..0000000
--- a/db/lvds_monitor.sta.qmsg
+++ /dev/null
@@ -1,39 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1781075230414 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition " "Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1781075230415 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 10 09:07:10 2026 " "Processing started: Wed Jun 10 09:07:10 2026" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1781075230415 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230415 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta lvds_monitor -c lvds_monitor " "Command: quartus_sta lvds_monitor -c lvds_monitor" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230415 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1781075230517 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "14 14 " "Parallel compilation is enabled and will use 14 of the 14 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1781075230601 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1781075230633 ""}
-{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1781075230634 ""}
-{ "Info" "ISTA_SDC_FOUND" "lvds_monitor.sdc " "Reading SDC File: 'lvds_monitor.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1781075230777 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "Timing Analyzer" 0 -1 1781075230779 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230788 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1781075230789 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1781075230795 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.242 " "Worst-case setup slack is 4.242" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.242 0.000 clk_50mhz " " 4.242 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.059 0.000 rx_clk " " 7.059 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230816 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 clk_50mhz " " 0.452 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 rx_clk " " 0.452 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230821 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230821 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 8.730 " "Worst-case recovery slack is 8.730" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 8.730 0.000 rx_clk " " 8.730 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 15.869 0.000 clk_50mhz " " 15.869 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230824 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230824 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 3.067 " "Worst-case removal slack is 3.067" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.067 0.000 clk_50mhz " " 3.067 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.061 0.000 rx_clk " " 4.061 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230827 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230827 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 6.480 " "Worst-case minimum pulse width slack is 6.480" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.480 0.000 rx_clk " " 6.480 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.735 0.000 clk_50mhz " " 9.735 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075230830 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075230830 ""}
-{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 46 synchronizer chains. " "Report Metastability: Found 46 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 46 " "Number of Synchronizer Chains Found: 46" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.327 ns " "Worst Case Available Settling Time: 12.327 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075230879 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075230879 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1781075230885 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1781075230900 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1781075231132 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231208 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.201 " "Worst-case setup slack is 5.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.201 0.000 clk_50mhz " " 5.201 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.569 0.000 rx_clk " " 7.569 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231225 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 clk_50mhz " " 0.401 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 rx_clk " " 0.401 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231231 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231231 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 9.063 " "Worst-case recovery slack is 9.063" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.063 0.000 rx_clk " " 9.063 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 16.187 0.000 clk_50mhz " " 16.187 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231238 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231238 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.755 " "Worst-case removal slack is 2.755" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.755 0.000 clk_50mhz " " 2.755 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.637 0.000 rx_clk " " 3.637 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231244 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231244 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 6.498 " "Worst-case minimum pulse width slack is 6.498" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.498 0.000 rx_clk " " 6.498 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.750 0.000 clk_50mhz " " 9.750 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231247 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231247 ""}
-{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 46 synchronizer chains. " "Report Metastability: Found 46 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 46 " "Number of Synchronizer Chains Found: 46" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.424 ns " "Worst Case Available Settling Time: 12.424 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231325 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231325 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1781075231331 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231416 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 10.706 " "Worst-case setup slack is 10.706" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 10.706 0.000 rx_clk " " 10.706 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 13.064 0.000 clk_50mhz " " 13.064 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231425 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 clk_50mhz " " 0.186 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 rx_clk " " 0.186 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231432 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231432 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 11.259 " "Worst-case recovery slack is 11.259" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 11.259 0.000 rx_clk " " 11.259 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 18.082 0.000 clk_50mhz " " 18.082 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231439 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231439 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.361 " "Worst-case removal slack is 1.361" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.361 0.000 clk_50mhz " " 1.361 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.805 0.000 rx_clk " " 1.805 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231447 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 6.002 " "Worst-case minimum pulse width slack is 6.002" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.002 0.000 rx_clk " " 6.002 0.000 rx_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.262 0.000 clk_50mhz " " 9.262 0.000 clk_50mhz " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1781075231451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1781075231451 ""}
-{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 46 synchronizer chains. " "Report Metastability: Found 46 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 46 " "Number of Synchronizer Chains Found: 46" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.010 ns " "Worst Case Available Settling Time: 13.010 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1781075231530 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1781075231530 ""}
-{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1781075231746 ""}
-{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" { } { } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1781075231746 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4946 " "Peak virtual memory: 4946 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1781075231805 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 10 09:07:11 2026 " "Processing ended: Wed Jun 10 09:07:11 2026" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1781075231805 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1781075231805 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1781075231805 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1781075231805 ""}
diff --git a/db/lvds_monitor.sta.rdb b/db/lvds_monitor.sta.rdb
deleted file mode 100644
index 155e2a6..0000000
Binary files a/db/lvds_monitor.sta.rdb and /dev/null differ
diff --git a/db/lvds_monitor.sta_cmp.8_slow_1200mv_85c.tdb b/db/lvds_monitor.sta_cmp.8_slow_1200mv_85c.tdb
deleted file mode 100644
index 6e08553..0000000
Binary files a/db/lvds_monitor.sta_cmp.8_slow_1200mv_85c.tdb and /dev/null differ
diff --git a/db/lvds_monitor.tis_db_list.ddb b/db/lvds_monitor.tis_db_list.ddb
deleted file mode 100644
index cb523f6..0000000
Binary files a/db/lvds_monitor.tis_db_list.ddb and /dev/null differ
diff --git a/db/lvds_monitor.tiscmp.fast_1200mv_0c.ddb b/db/lvds_monitor.tiscmp.fast_1200mv_0c.ddb
deleted file mode 100644
index 3b0055e..0000000
Binary files a/db/lvds_monitor.tiscmp.fast_1200mv_0c.ddb and /dev/null differ
diff --git a/db/lvds_monitor.tiscmp.fastest_slow_1200mv_0c.ddb b/db/lvds_monitor.tiscmp.fastest_slow_1200mv_0c.ddb
deleted file mode 100644
index b584131..0000000
Binary files a/db/lvds_monitor.tiscmp.fastest_slow_1200mv_0c.ddb and /dev/null differ
diff --git a/db/lvds_monitor.tiscmp.fastest_slow_1200mv_85c.ddb b/db/lvds_monitor.tiscmp.fastest_slow_1200mv_85c.ddb
deleted file mode 100644
index 85627af..0000000
Binary files a/db/lvds_monitor.tiscmp.fastest_slow_1200mv_85c.ddb and /dev/null differ
diff --git a/db/lvds_monitor.tiscmp.slow_1200mv_0c.ddb b/db/lvds_monitor.tiscmp.slow_1200mv_0c.ddb
deleted file mode 100644
index 5fed341..0000000
Binary files a/db/lvds_monitor.tiscmp.slow_1200mv_0c.ddb and /dev/null differ
diff --git a/db/lvds_monitor.tiscmp.slow_1200mv_85c.ddb b/db/lvds_monitor.tiscmp.slow_1200mv_85c.ddb
deleted file mode 100644
index 0def5aa..0000000
Binary files a/db/lvds_monitor.tiscmp.slow_1200mv_85c.ddb and /dev/null differ
diff --git a/db/lvds_monitor.vpr.ammdb b/db/lvds_monitor.vpr.ammdb
deleted file mode 100644
index 321a932..0000000
Binary files a/db/lvds_monitor.vpr.ammdb and /dev/null differ
diff --git a/db/lvds_monitor_partition_pins.json b/db/lvds_monitor_partition_pins.json
deleted file mode 100644
index efdda00..0000000
--- a/db/lvds_monitor_partition_pins.json
+++ /dev/null
@@ -1,29 +0,0 @@
-{
- "partitions" : [
- {
- "name" : "Top",
- "pins" : [
- {
- "name" : "uart_tx_pin",
- "strict" : false
- },
- {
- "name" : "clk_50mhz",
- "strict" : false
- },
- {
- "name" : "rst_n_pin",
- "strict" : false
- },
- {
- "name" : "rx_clk",
- "strict" : false
- },
- {
- "name" : "de",
- "strict" : false
- }
- ]
- }
- ]
-}
\ No newline at end of file
diff --git a/db/sign_div_unsign_7nh.tdf b/db/sign_div_unsign_7nh.tdf
deleted file mode 100644
index 3c5b630..0000000
--- a/db/sign_div_unsign_7nh.tdf
+++ /dev/null
@@ -1,47 +0,0 @@
---sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=10 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=16 SKIP_BITS=0 denominator numerator quotient remainder
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION alt_u_div_2af (denominator[9..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[9..0]);
-
---synthesis_resources = lut 132
-SUBDESIGN sign_div_unsign_7nh
-(
- denominator[9..0] : input;
- numerator[15..0] : input;
- quotient[15..0] : output;
- remainder[9..0] : output;
-)
-VARIABLE
- divider : alt_u_div_2af;
- norm_num[15..0] : WIRE;
- protect_quotient[15..0] : WIRE;
- protect_remainder[9..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denominator[];
- divider.numerator[] = norm_num[];
- norm_num[] = numerator[];
- protect_quotient[] = divider.quotient[];
- protect_remainder[] = divider.remainder[];
- quotient[] = protect_quotient[];
- remainder[] = protect_remainder[];
-END;
---VALID FILE
diff --git a/db/sign_div_unsign_qlh.tdf b/db/sign_div_unsign_qlh.tdf
deleted file mode 100644
index 72cede4..0000000
--- a/db/sign_div_unsign_qlh.tdf
+++ /dev/null
@@ -1,47 +0,0 @@
---sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=16 SKIP_BITS=0 denominator numerator quotient remainder
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION alt_u_div_87f (denominator[3..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[3..0]);
-
---synthesis_resources = lut 81
-SUBDESIGN sign_div_unsign_qlh
-(
- denominator[3..0] : input;
- numerator[15..0] : input;
- quotient[15..0] : output;
- remainder[3..0] : output;
-)
-VARIABLE
- divider : alt_u_div_87f;
- norm_num[15..0] : WIRE;
- protect_quotient[15..0] : WIRE;
- protect_remainder[3..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denominator[];
- divider.numerator[] = norm_num[];
- norm_num[] = numerator[];
- protect_quotient[] = divider.quotient[];
- protect_remainder[] = divider.remainder[];
- quotient[] = protect_quotient[];
- remainder[] = protect_remainder[];
-END;
---VALID FILE
diff --git a/db/sign_div_unsign_tlh.tdf b/db/sign_div_unsign_tlh.tdf
deleted file mode 100644
index 11ed986..0000000
--- a/db/sign_div_unsign_tlh.tdf
+++ /dev/null
@@ -1,47 +0,0 @@
---sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=7 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=16 SKIP_BITS=0 denominator numerator quotient remainder
---VERSION_BEGIN 25.1 cbx_cycloneii 2025:10:22:10:31:27:SC cbx_lpm_abs 2025:10:22:10:31:27:SC cbx_lpm_add_sub 2025:10:22:10:31:27:SC cbx_lpm_divide 2025:10:22:10:31:27:SC cbx_mgl 2025:10:22:10:31:44:SC cbx_nadder 2025:10:22:10:31:27:SC cbx_stratix 2025:10:22:10:31:27:SC cbx_stratixii 2025:10:22:10:31:26:SC cbx_util_mgl 2025:10:22:10:31:27:SC VERSION_END
-
-
--- Copyright (C) 2025 Altera Corporation. All rights reserved.
--- Your use of Altera Corporation's design tools, logic functions
--- and other software and tools, and any partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Altera Program License
--- Subscription Agreement, the Altera Quartus Prime License Agreement,
--- the Altera IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Altera and sold by Altera or its authorized distributors. Please
--- refer to the Altera Software License Subscription Agreements
--- on the Quartus Prime software download page.
-
-
-FUNCTION alt_u_div_e7f (denominator[6..0], numerator[15..0])
-RETURNS ( quotient[15..0], remainder[6..0]);
-
---synthesis_resources = lut 111
-SUBDESIGN sign_div_unsign_tlh
-(
- denominator[6..0] : input;
- numerator[15..0] : input;
- quotient[15..0] : output;
- remainder[6..0] : output;
-)
-VARIABLE
- divider : alt_u_div_e7f;
- norm_num[15..0] : WIRE;
- protect_quotient[15..0] : WIRE;
- protect_remainder[6..0] : WIRE;
-
-BEGIN
- divider.denominator[] = denominator[];
- divider.numerator[] = norm_num[];
- norm_num[] = numerator[];
- protect_quotient[] = divider.quotient[];
- protect_remainder[] = divider.remainder[];
- quotient[] = protect_quotient[];
- remainder[] = protect_remainder[];
-END;
---VALID FILE
diff --git a/incremental_db/README b/incremental_db/README
deleted file mode 100644
index 9f62dcd..0000000
--- a/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/incremental_db/compiled_partitions/lvds_monitor.db_info b/incremental_db/compiled_partitions/lvds_monitor.db_info
deleted file mode 100644
index 0b451d8..0000000
--- a/incremental_db/compiled_partitions/lvds_monitor.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-Version_Index = 604268800
-Creation_Time = Wed Jun 10 08:50:00 2026
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.ammdb
deleted file mode 100644
index a5b5042..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.ammdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.cdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.cdb
deleted file mode 100644
index dd0c2dd..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.cdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.dfp b/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.dfp
deleted file mode 100644
index b1c67d6..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.dfp and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.hdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.hdb
deleted file mode 100644
index 5aaa373..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.hdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.logdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.logdb
deleted file mode 100644
index 626799f..0000000
--- a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.rcfdb
deleted file mode 100644
index 840323a..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.cmp.rcfdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.cdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.cdb
deleted file mode 100644
index bbd4b23..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.cdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.dpi b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.dpi
deleted file mode 100644
index 02ef3ad..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.dpi and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.cdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.cdb
deleted file mode 100644
index 215427d..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.cdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.hb_info b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.hb_info and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.hdb
deleted file mode 100644
index ea4a5f6..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.hdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.sig b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.sig
deleted file mode 100644
index 6c0af65..0000000
--- a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hdb b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hdb
deleted file mode 100644
index 2d6a685..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.hdb and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.kpt b/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.kpt
deleted file mode 100644
index 80fc183..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.root_partition.map.kpt and /dev/null differ
diff --git a/incremental_db/compiled_partitions/lvds_monitor.rrp.hdb b/incremental_db/compiled_partitions/lvds_monitor.rrp.hdb
deleted file mode 100644
index 971bc1d..0000000
Binary files a/incremental_db/compiled_partitions/lvds_monitor.rrp.hdb and /dev/null differ
diff --git a/lvds_monitor.asm.rpt b/lvds_monitor.asm.rpt
deleted file mode 100644
index d94eb91..0000000
--- a/lvds_monitor.asm.rpt
+++ /dev/null
@@ -1,91 +0,0 @@
-Assembler report for lvds_monitor
-Wed Jun 10 09:07:09 2026
-Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2025 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Altera and sold by Altera or its authorized distributors. Please
-refer to the Altera Software License Subscription Agreements
-on the Quartus Prime software download page.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Jun 10 09:07:09 2026 ;
-; Revision Name ; lvds_monitor ;
-; Top-level Entity Name ; top ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE6E22C8 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+-----------------------------------------------------------------+
-; Assembler Generated Files ;
-+-----------------------------------------------------------------+
-; File Name ;
-+-----------------------------------------------------------------+
-; C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.sof ;
-+-----------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.sof ;
-+----------------+--------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+--------------------------------------------------------------------------+
-; JTAG usercode ; 0x001B1109 ;
-; Checksum ; 0x001B1109 ;
-+----------------+--------------------------------------------------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Wed Jun 10 09:07:08 2026
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor
-Info (115031): Writing out detailed assembly data for power analysis
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 4744 megabytes
- Info: Processing ended: Wed Jun 10 09:07:09 2026
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
-
-
diff --git a/lvds_monitor.done b/lvds_monitor.done
deleted file mode 100644
index 3bc3b65..0000000
--- a/lvds_monitor.done
+++ /dev/null
@@ -1 +0,0 @@
-Wed Jun 10 09:07:12 2026
diff --git a/lvds_monitor.fit.rpt b/lvds_monitor.fit.rpt
deleted file mode 100644
index a2d3925..0000000
--- a/lvds_monitor.fit.rpt
+++ /dev/null
@@ -1,1075 +0,0 @@
-Fitter report for lvds_monitor
-Wed Jun 10 09:07:07 2026
-Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Incremental Compilation Preservation Summary
- 6. Incremental Compilation Partition Settings
- 7. Incremental Compilation Placement Preservation
- 8. Pin-Out File
- 9. Fitter Resource Usage Summary
- 10. Fitter Partition Statistics
- 11. Input Pins
- 12. Output Pins
- 13. Dual Purpose and Dedicated Pins
- 14. I/O Bank Usage
- 15. All Package Pins
- 16. I/O Assignment Warnings
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Control Signals
- 21. Global & Other Fast Signals
- 22. Routing Usage Summary
- 23. LAB Logic Elements
- 24. LAB-wide Signals
- 25. LAB Signals Sourced
- 26. LAB Signals Sourced Out
- 27. LAB Distinct Inputs
- 28. I/O Rules Summary
- 29. I/O Rules Details
- 30. I/O Rules Matrix
- 31. Fitter Device Options
- 32. Operating Settings and Conditions
- 33. Fitter Messages
- 34. Fitter Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2025 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Altera and sold by Altera or its authorized distributors. Please
-refer to the Altera Software License Subscription Agreements
-on the Quartus Prime software download page.
-
-
-
-+--------------------------------------------------------------------------------------+
-; Fitter Summary ;
-+------------------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Wed Jun 10 09:07:07 2026 ;
-; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
-; Revision Name ; lvds_monitor ;
-; Top-level Entity Name ; top ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE6E22C8 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1,953 / 6,272 ( 31 % ) ;
-; Total combinational functions ; 1,856 / 6,272 ( 30 % ) ;
-; Dedicated logic registers ; 319 / 6,272 ( 5 % ) ;
-; Total registers ; 319 ;
-; Total pins ; 7 / 92 ( 8 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 276,480 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
-; Total PLLs ; 0 / 2 ( 0 % ) ;
-+------------------------------------+-------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; EP4CE6E22C8 ; ;
-; Maximum processors allowed for parallel compilation ; All ; ;
-; Fit Attempts to Skip ; 0 ; 0.0 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Auto Merge PLLs ; On ; On ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Router Effort Multiplier ; 1.0 ; 1.0 ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Limit to One Fitting Attempt ; Off ; Off ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; PCI I/O ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 20 ;
-; Maximum allowed ; 14 ;
-; ; ;
-; Average used ; 1.32 ;
-; Maximum used ; 14 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 2.9% ;
-; Processor 3 ; 2.7% ;
-; Processor 4 ; 2.6% ;
-; Processor 5 ; 2.6% ;
-; Processor 6 ; 2.5% ;
-; Processor 7 ; 2.5% ;
-; Processor 8 ; 2.4% ;
-; Processors 9-14 ; 2.4% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+---------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+---------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 2199 ) ; 0.00 % ( 0 / 2199 ) ; 0.00 % ( 0 / 2199 ) ;
-; -- Achieved ; 0.00 % ( 0 / 2199 ) ; 0.00 % ( 0 / 2199 ) ; 0.00 % ( 0 / 2199 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+---------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 2191 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 8 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.pin.
-
-
-+----------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+------------------------+
-; Total logic elements ; 1,953 / 6,272 ( 31 % ) ;
-; -- Combinational with no register ; 1634 ;
-; -- Register only ; 97 ;
-; -- Combinational with a register ; 222 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 855 ;
-; -- 3 input functions ; 149 ;
-; -- <=2 input functions ; 852 ;
-; -- Register only ; 97 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1131 ;
-; -- arithmetic mode ; 725 ;
-; ; ;
-; Total registers* ; 319 / 6,684 ( 5 % ) ;
-; -- Dedicated logic registers ; 319 / 6,272 ( 5 % ) ;
-; -- I/O registers ; 0 / 412 ( 0 % ) ;
-; ; ;
-; Total LABs: partially or completely used ; 152 / 392 ( 39 % ) ;
-; Virtual pins ; 0 ;
-; I/O pins ; 7 / 92 ( 8 % ) ;
-; -- Clock pins ; 2 / 3 ( 67 % ) ;
-; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
-; ; ;
-; M9Ks ; 0 / 30 ( 0 % ) ;
-; Total block memory bits ; 0 / 276,480 ( 0 % ) ;
-; Total block memory implementation bits ; 0 / 276,480 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
-; PLLs ; 0 / 2 ( 0 % ) ;
-; Global signals ; 5 ;
-; -- Global clocks ; 5 / 10 ( 50 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; ASMI blocks ; 0 / 1 ( 0 % ) ;
-; Oscillator blocks ; 0 / 1 ( 0 % ) ;
-; Impedance control blocks ; 0 / 4 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 6.2% / 5.9% / 6.7% ;
-; Peak interconnect usage (total/H/V) ; 18.6% / 17.6% / 20.0% ;
-; Maximum fan-out ; 162 ;
-; Highest non-global fan-out ; 57 ;
-; Total fan-out ; 6914 ;
-; Average fan-out ; 3.04 ;
-+---------------------------------------------+------------------------+
-* Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+---------------------------------------------+----------------------+--------------------------------+
-; Difficulty Clustering Region ; Low ; Low ;
-; ; ; ;
-; Total logic elements ; 1953 / 6272 ( 31 % ) ; 0 / 6272 ( 0 % ) ;
-; -- Combinational with no register ; 1634 ; 0 ;
-; -- Register only ; 97 ; 0 ;
-; -- Combinational with a register ; 222 ; 0 ;
-; ; ; ;
-; Logic element usage by number of LUT inputs ; ; ;
-; -- 4 input functions ; 855 ; 0 ;
-; -- 3 input functions ; 149 ; 0 ;
-; -- <=2 input functions ; 852 ; 0 ;
-; -- Register only ; 97 ; 0 ;
-; ; ; ;
-; Logic elements by mode ; ; ;
-; -- normal mode ; 1131 ; 0 ;
-; -- arithmetic mode ; 725 ; 0 ;
-; ; ; ;
-; Total registers ; 319 ; 0 ;
-; -- Dedicated logic registers ; 319 / 6272 ( 5 % ) ; 0 / 6272 ( 0 % ) ;
-; -- I/O registers ; 0 ; 0 ;
-; ; ; ;
-; Total LABs: partially or completely used ; 152 / 392 ( 39 % ) ; 0 / 392 ( 0 % ) ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 7 ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ;
-; Total memory bits ; 0 ; 0 ;
-; Total RAM block bits ; 0 ; 0 ;
-; Clock control block ; 5 / 12 ( 41 % ) ; 0 / 12 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 6910 ; 4 ;
-; -- Registered Connections ; 1970 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 6 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+---------------------------------------------+----------------------+--------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; clk_50mhz ; 24 ; 2 ; 0 ; 11 ; 14 ; 157 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; de ; 31 ; 2 ; 0 ; 7 ; 0 ; 57 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; hsync ; 33 ; 2 ; 0 ; 6 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; rst_n_pin ; 88 ; 5 ; 34 ; 12 ; 21 ; 6 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; rx_clk ; 30 ; 2 ; 0 ; 8 ; 14 ; 162 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-; vsync ; 32 ; 2 ; 0 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; no ;
-+-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-; uart_tx_pin ; 10 ; 1 ; 0 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-; 6 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
-; 8 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
-; 9 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
-; 12 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
-; 13 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
-; 14 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
-; 21 ; nCE ; - ; - ; Dedicated Programming Pin ;
-; 92 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
-; 94 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
-; 96 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
-; 97 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
-; 97 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
-+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
-
-
-+-----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+-----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+-----------------+---------------+--------------+
-; 1 ; 5 / 11 ( 45 % ) ; 3.3V ; -- ;
-; 2 ; 5 / 8 ( 63 % ) ; 3.3V ; -- ;
-; 3 ; 0 / 11 ( 0 % ) ; 2.5V ; -- ;
-; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ;
-; 5 ; 1 / 13 ( 8 % ) ; 3.3V ; -- ;
-; 6 ; 0 / 10 ( 0 % ) ; 2.5V ; -- ;
-; 7 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ;
-; 8 ; 0 / 12 ( 0 % ) ; 2.5V ; -- ;
-+----------+-----------------+---------------+--------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; 1 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 3 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 6 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 7 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; 8 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 9 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; 10 ; 13 ; 1 ; uart_tx_pin ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 11 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 12 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 13 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
-; 14 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; 15 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; 16 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; 17 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 18 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 20 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; 21 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; 22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 23 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 24 ; 25 ; 2 ; clk_50mhz ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 25 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 26 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 28 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 29 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 30 ; 34 ; 2 ; rx_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 31 ; 36 ; 2 ; de ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 32 ; 39 ; 2 ; vsync ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 33 ; 40 ; 2 ; hsync ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 34 ; 41 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 35 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 36 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
-; 37 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 38 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 39 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 40 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 41 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 42 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 43 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 44 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 45 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 46 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; 47 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 48 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 49 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 50 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 51 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 52 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 53 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 54 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 55 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 56 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 57 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 58 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 59 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 60 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 61 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 62 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 64 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 65 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; 66 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 67 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 68 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 69 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 70 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 71 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 72 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 73 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 74 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 75 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 76 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 77 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 78 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 80 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; 81 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 82 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 83 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 84 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 85 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 86 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 87 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 88 ; 125 ; 5 ; rst_n_pin ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
-; 89 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 90 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 91 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
-; 92 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; 93 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 94 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 96 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; 97 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; 97 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; 98 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 99 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 100 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 101 ; 139 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 102 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 103 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 104 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 105 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; 106 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; 107 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 108 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
-; 109 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 110 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 111 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 112 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 113 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 114 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 115 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 116 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 117 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 118 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 119 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; 120 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 121 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 122 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 124 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 125 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 126 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 127 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 128 ; 177 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 129 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 130 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 131 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 132 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 133 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 134 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; 135 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 136 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
-; 137 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 138 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 139 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 141 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 142 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 143 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; 144 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; EPAD ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
-+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+--------------------------------------+
-; I/O Assignment Warnings ;
-+-------------+------------------------+
-; Pin Name ; Reason ;
-+-------------+------------------------+
-; uart_tx_pin ; Missing drive strength ;
-+-------------+------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+-------------+--------------+
-; |top ; 1953 (1759) ; 319 (173) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 1634 (1585) ; 97 (55) ; 222 (119) ; |top ; top ; work ;
-; |de_monitor:u_mon| ; 159 (159) ; 117 (117) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (42) ; 31 (31) ; 86 (86) ; |top|de_monitor:u_mon ; de_monitor ; work ;
-; |uart_tx:u_uart| ; 36 (36) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 11 (11) ; 18 (18) ; |top|uart_tx:u_uart ; uart_tx ; work ;
-+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+---------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+-------------+----------+---------------+---------------+-----------------------+-----+------+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
-+-------------+----------+---------------+---------------+-----------------------+-----+------+
-; vsync ; Input ; -- ; -- ; -- ; -- ; -- ;
-; hsync ; Input ; -- ; -- ; -- ; -- ; -- ;
-; uart_tx_pin ; Output ; -- ; -- ; -- ; -- ; -- ;
-; clk_50mhz ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-; rst_n_pin ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-; rx_clk ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
-; de ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
-+-------------+----------+---------------+---------------+-----------------------+-----+------+
-
-
-+------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+------------------------------------------+-------------------+---------+
-; vsync ; ; ;
-; hsync ; ; ;
-; clk_50mhz ; ; ;
-; rst_n_pin ; ; ;
-; rx_clk ; ; ;
-; de ; ; ;
-; - de_monitor:u_mon|line_width[0] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[1] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[2] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[3] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[4] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[5] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[6] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[7] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[8] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[9] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[10] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[11] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[12] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[13] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[14] ; 0 ; 6 ;
-; - de_monitor:u_mon|line_width[15] ; 0 ; 6 ;
-; - de_monitor:u_mon|lines_o[2]~0 ; 0 ; 6 ;
-; - de_monitor:u_mon|de_q ; 0 ; 6 ;
-; - de_monitor:u_mon|de_rise ; 0 ; 6 ;
-; - de_monitor:u_mon|line_count[4]~48 ; 0 ; 6 ;
-; - de_monitor:u_mon|de_fall ; 0 ; 6 ;
-; - de_monitor:u_mon|any_bad_width~1 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~32 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~33 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~34 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~35 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~36 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~37 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~38 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~39 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~40 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~41 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~42 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~43 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~44 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~45 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~46 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~47 ; 0 ; 6 ;
-; - de_monitor:u_mon|Add2~48 ; 0 ; 6 ;
-; - de_monitor:u_mon|frame_active~0 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~0 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width[0]~1 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~2 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~3 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~4 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~5 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~6 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~7 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~8 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~9 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~10 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~11 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~12 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~13 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~14 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~15 ; 0 ; 6 ;
-; - de_monitor:u_mon|bad_width~16 ; 0 ; 6 ;
-+------------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+-----------------------------------+--------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+-----------------------------------+--------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
-; L0_r[3]~6 ; LCCOMB_X19_Y13_N18 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
-; L1_r[3]~2 ; LCCOMB_X19_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; L2_r[3]~15 ; LCCOMB_X19_Y13_N22 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
-; Selector19~5 ; LCCOMB_X19_Y13_N28 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; Selector39~1 ; LCCOMB_X19_Y13_N2 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
-; Selector40~3 ; LCCOMB_X19_Y13_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; clk_50mhz ; PIN_24 ; 157 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
-; conv_step[1]~1 ; LCCOMB_X19_Y13_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; de ; PIN_31 ; 57 ; Clock enable ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|Add2~33 ; LCCOMB_X10_Y7_N2 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|bad_width[0]~1 ; LCCOMB_X5_Y7_N4 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|de_fall ; LCCOMB_X10_Y7_N22 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|de_rise ; LCCOMB_X10_Y7_N18 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|frame_done ; FF_X9_Y7_N1 ; 42 ; Clock enable ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|line_count[4]~48 ; LCCOMB_X10_Y7_N28 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
-; de_monitor:u_mon|lines_o[2]~0 ; LCCOMB_X10_Y7_N16 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
-; fstate.F_CONVERT ; FF_X19_Y13_N25 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ;
-; fstate.F_IDLE ; FF_X18_Y13_N19 ; 16 ; Sync. load ; no ; -- ; -- ; -- ;
-; fstate.F_WAIT ; FF_X19_Y13_N21 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;
-; idx[5]~12 ; LCCOMB_X22_Y14_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
-; is_err_msg~0 ; LCCOMB_X18_Y13_N12 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
-; l_rem[15]~96 ; LCCOMB_X16_Y15_N16 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; l_rem~117 ; LCCOMB_X14_Y14_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; req_edge ; LCCOMB_X18_Y13_N16 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
-; rst_n_pin ; PIN_88 ; 6 ; Async. clear ; yes ; Global Clock ; GCLK8 ; -- ;
-; rst_sync_pix[2] ; FF_X3_Y11_N17 ; 159 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ;
-; rst_sync_uart[2] ; FF_X31_Y9_N1 ; 154 ; Async. clear ; yes ; Global Clock ; GCLK9 ; -- ;
-; rx_clk ; PIN_30 ; 162 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ;
-; uart_tx:u_uart|shift[6]~0 ; LCCOMB_X29_Y14_N10 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
-; uart_tx:u_uart|state.S_IDLE ; FF_X29_Y14_N13 ; 7 ; Sync. load ; no ; -- ; -- ; -- ;
-; uart_tx:u_uart|state~35 ; LCCOMB_X29_Y14_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; uart_tx:u_uart|tick[2]~13 ; LCCOMB_X28_Y14_N24 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ;
-; w_rem[12]~47 ; LCCOMB_X16_Y15_N8 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; w_rem~24 ; LCCOMB_X19_Y13_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
-+-----------------------------------+--------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; clk_50mhz ; PIN_24 ; 157 ; 0 ; Global Clock ; GCLK4 ; -- ;
-; rst_n_pin ; PIN_88 ; 6 ; 0 ; Global Clock ; GCLK8 ; -- ;
-; rst_sync_pix[2] ; FF_X3_Y11_N17 ; 159 ; 0 ; Global Clock ; GCLK5 ; -- ;
-; rst_sync_uart[2] ; FF_X31_Y9_N1 ; 154 ; 0 ; Global Clock ; GCLK9 ; -- ;
-; rx_clk ; PIN_30 ; 162 ; 0 ; Global Clock ; GCLK1 ; -- ;
-+------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-
-
-+------------------------------------------------+
-; Routing Usage Summary ;
-+-----------------------+------------------------+
-; Routing Resource Type ; Usage ;
-+-----------------------+------------------------+
-; Block interconnects ; 2,768 / 32,401 ( 9 % ) ;
-; C16 interconnects ; 3 / 1,326 ( < 1 % ) ;
-; C4 interconnects ; 1,502 / 21,816 ( 7 % ) ;
-; Direct links ; 260 / 32,401 ( < 1 % ) ;
-; Global clocks ; 5 / 10 ( 50 % ) ;
-; Local interconnects ; 729 / 10,320 ( 7 % ) ;
-; R24 interconnects ; 19 / 1,289 ( 1 % ) ;
-; R4 interconnects ; 1,688 / 28,186 ( 6 % ) ;
-+-----------------------+------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+---------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 12.85) ; Number of LABs (Total = 152) ;
-+---------------------------------------------+-------------------------------+
-; 1 ; 12 ;
-; 2 ; 3 ;
-; 3 ; 2 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-; 6 ; 0 ;
-; 7 ; 2 ;
-; 8 ; 3 ;
-; 9 ; 2 ;
-; 10 ; 2 ;
-; 11 ; 2 ;
-; 12 ; 6 ;
-; 13 ; 16 ;
-; 14 ; 21 ;
-; 15 ; 28 ;
-; 16 ; 52 ;
-+---------------------------------------------+-------------------------------+
-
-
-+--------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 0.97) ; Number of LABs (Total = 152) ;
-+------------------------------------+-------------------------------+
-; 1 Async. clear ; 48 ;
-; 1 Clock ; 48 ;
-; 1 Clock enable ; 16 ;
-; 1 Sync. clear ; 2 ;
-; 1 Sync. load ; 4 ;
-; 2 Async. clears ; 1 ;
-; 2 Clock enables ; 27 ;
-; 2 Clocks ; 1 ;
-+------------------------------------+-------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+----------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 14.78) ; Number of LABs (Total = 152) ;
-+----------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 9 ;
-; 2 ; 6 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-; 6 ; 2 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 1 ;
-; 10 ; 2 ;
-; 11 ; 4 ;
-; 12 ; 5 ;
-; 13 ; 9 ;
-; 14 ; 18 ;
-; 15 ; 23 ;
-; 16 ; 34 ;
-; 17 ; 2 ;
-; 18 ; 6 ;
-; 19 ; 2 ;
-; 20 ; 4 ;
-; 21 ; 4 ;
-; 22 ; 4 ;
-; 23 ; 3 ;
-; 24 ; 3 ;
-; 25 ; 2 ;
-; 26 ; 0 ;
-; 27 ; 1 ;
-; 28 ; 1 ;
-; 29 ; 1 ;
-; 30 ; 1 ;
-; 31 ; 0 ;
-; 32 ; 2 ;
-+----------------------------------------------+-------------------------------+
-
-
-+---------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 9.09) ; Number of LABs (Total = 152) ;
-+-------------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 15 ;
-; 2 ; 8 ;
-; 3 ; 7 ;
-; 4 ; 12 ;
-; 5 ; 10 ;
-; 6 ; 5 ;
-; 7 ; 6 ;
-; 8 ; 9 ;
-; 9 ; 2 ;
-; 10 ; 9 ;
-; 11 ; 2 ;
-; 12 ; 8 ;
-; 13 ; 14 ;
-; 14 ; 17 ;
-; 15 ; 18 ;
-; 16 ; 9 ;
-; 17 ; 0 ;
-; 18 ; 0 ;
-; 19 ; 0 ;
-; 20 ; 0 ;
-; 21 ; 0 ;
-; 22 ; 0 ;
-; 23 ; 0 ;
-; 24 ; 0 ;
-; 25 ; 0 ;
-; 26 ; 0 ;
-; 27 ; 1 ;
-+-------------------------------------------------+-------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 18.14) ; Number of LABs (Total = 152) ;
-+----------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 3 ;
-; 3 ; 4 ;
-; 4 ; 8 ;
-; 5 ; 3 ;
-; 6 ; 1 ;
-; 7 ; 4 ;
-; 8 ; 3 ;
-; 9 ; 1 ;
-; 10 ; 1 ;
-; 11 ; 2 ;
-; 12 ; 6 ;
-; 13 ; 11 ;
-; 14 ; 11 ;
-; 15 ; 13 ;
-; 16 ; 4 ;
-; 17 ; 3 ;
-; 18 ; 9 ;
-; 19 ; 5 ;
-; 20 ; 4 ;
-; 21 ; 3 ;
-; 22 ; 5 ;
-; 23 ; 4 ;
-; 24 ; 3 ;
-; 25 ; 1 ;
-; 26 ; 3 ;
-; 27 ; 6 ;
-; 28 ; 3 ;
-; 29 ; 5 ;
-; 30 ; 5 ;
-; 31 ; 2 ;
-; 32 ; 5 ;
-; 33 ; 5 ;
-; 34 ; 3 ;
-; 35 ; 1 ;
-; 36 ; 2 ;
-+----------------------------------------------+-------------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 30 ;
-; Number of I/O Rules Passed ; 9 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 21 ;
-+----------------------------------+-------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass ; 7 ; 0 ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 0 ; 7 ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 0 ; 0 ; 7 ; 7 ; 7 ; 7 ; 1 ; 7 ; 7 ; 1 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 0 ; 7 ; 7 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; vsync ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; hsync ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; uart_tx_pin ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; clk_50mhz ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; rst_n_pin ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; rx_clk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; de ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+--------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Active Serial ;
-; Error detection CRC ; Off ;
-; Enable open drain on CRC_ERROR pin ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; nCEO ; Unreserved ;
-; Data[0] ; As input tri-stated ;
-; Data[1]/ASDO ; As input tri-stated ;
-; Data[7..2] ; Unreserved ;
-; FLASH_nCE/nCSO ; As input tri-stated ;
-; Other Active Parallel pins ; Unreserved ;
-; DCLK ; As output driving ground ;
-+------------------------------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.20 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Info (20030): Parallel compilation is enabled and will use 14 of the 14 processors detected
-Info (119006): Selected device EP4CE6E22C8 for design "lvds_monitor"
-Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
-Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
-Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE10E22C8 is compatible
- Info (176445): Device EP4CE15E22C8 is compatible
- Info (176445): Device EP4CE22E22C8 is compatible
-Info (169124): Fitter converted 4 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (332104): Reading SDC File: 'lvds_monitor.sdc'
-Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
-Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
-Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
-Info (332111): Found 2 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 20.000 clk_50mhz
- Info (332111): 13.500 rx_clk
-Info (176353): Automatically promoted node rx_clk~input (placed in PIN 30 (DIFFIO_L8p, DQS1L/CQ1L#,DPCLK1)) File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 24
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
-Info (176353): Automatically promoted node clk_50mhz~input (placed in PIN 24 (CLK2, DIFFCLK_1p)) File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 23
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
-Info (176353): Automatically promoted node rst_n_pin~input (placed in PIN 88 (CLK7, DIFFCLK_3n)) File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 28
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
-Info (176353): Automatically promoted node rst_sync_pix[2] File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 57
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
-Info (176353): Automatically promoted node rst_sync_uart[2] File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 51
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
-Info (176233): Starting register packing
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
-Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
-Info (170189): Fitter placement preparation operations beginning
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 5% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
- Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.33 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
-Warning (169177): 6 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
- Info (169178): Pin vsync uses I/O standard 3.3-V LVTTL at 32 File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 26
- Info (169178): Pin hsync uses I/O standard 3.3-V LVTTL at 33 File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 27
- Info (169178): Pin clk_50mhz uses I/O standard 3.3-V LVTTL at 24 File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 23
- Info (169178): Pin rst_n_pin uses I/O standard 3.3-V LVTTL at 88 File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 28
- Info (169178): Pin rx_clk uses I/O standard 3.3-V LVTTL at 30 File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 24
- Info (169178): Pin de uses I/O standard 3.3-V LVTTL at 31 File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 25
-Info (144001): Generated suppressed messages file C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.fit.smsg
-Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 6367 megabytes
- Info: Processing ended: Wed Jun 10 09:07:07 2026
- Info: Elapsed time: 00:00:04
- Info: Total CPU time (on all processors): 00:00:09
-
-
-+----------------------------+
-; Fitter Suppressed Messages ;
-+----------------------------+
-The suppressed messages can be found in C:/Users/DavidRice/Documents/fpga/lvds_monitor/lvds_monitor.fit.smsg.
-
-
diff --git a/lvds_monitor.fit.smsg b/lvds_monitor.fit.smsg
deleted file mode 100644
index 7121cbb..0000000
--- a/lvds_monitor.fit.smsg
+++ /dev/null
@@ -1,8 +0,0 @@
-Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
-Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
-Extra Info (176236): Started Fast Input/Output/OE register processing
-Extra Info (176237): Finished Fast Input/Output/OE register processing
-Extra Info (176238): Start inferring scan chains for DSP blocks
-Extra Info (176239): Inferring scan chains for DSP blocks is complete
-Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/lvds_monitor.fit.summary b/lvds_monitor.fit.summary
deleted file mode 100644
index f89f239..0000000
--- a/lvds_monitor.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Wed Jun 10 09:07:07 2026
-Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-Revision Name : lvds_monitor
-Top-level Entity Name : top
-Family : Cyclone IV E
-Device : EP4CE6E22C8
-Timing Models : Final
-Total logic elements : 1,953 / 6,272 ( 31 % )
- Total combinational functions : 1,856 / 6,272 ( 30 % )
- Dedicated logic registers : 319 / 6,272 ( 5 % )
-Total registers : 319
-Total pins : 7 / 92 ( 8 % )
-Total virtual pins : 0
-Total memory bits : 0 / 276,480 ( 0 % )
-Embedded Multiplier 9-bit elements : 0 / 30 ( 0 % )
-Total PLLs : 0 / 2 ( 0 % )
diff --git a/lvds_monitor.flow.rpt b/lvds_monitor.flow.rpt
deleted file mode 100644
index 11ce338..0000000
--- a/lvds_monitor.flow.rpt
+++ /dev/null
@@ -1,120 +0,0 @@
-Flow report for lvds_monitor
-Wed Jun 10 09:07:11 2026
-Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2025 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Altera and sold by Altera or its authorized distributors. Please
-refer to the Altera Software License Subscription Agreements
-on the Quartus Prime software download page.
-
-
-
-+--------------------------------------------------------------------------------------+
-; Flow Summary ;
-+------------------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Wed Jun 10 09:07:09 2026 ;
-; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
-; Revision Name ; lvds_monitor ;
-; Top-level Entity Name ; top ;
-; Family ; Cyclone IV E ;
-; Device ; EP4CE6E22C8 ;
-; Timing Models ; Final ;
-; Total logic elements ; 1,953 / 6,272 ( 31 % ) ;
-; Total combinational functions ; 1,856 / 6,272 ( 30 % ) ;
-; Dedicated logic registers ; 319 / 6,272 ( 5 % ) ;
-; Total registers ; 319 ;
-; Total pins ; 7 / 92 ( 8 % ) ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 / 276,480 ( 0 % ) ;
-; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
-; Total PLLs ; 0 / 2 ( 0 % ) ;
-+------------------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 06/10/2026 09:06:53 ;
-; Main task ; Compilation ;
-; Revision Name ; lvds_monitor ;
-+-------------------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------+---------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------+---------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 266223544113564.178107521313648 ; -- ; -- ; -- ;
-; NUM_PARALLEL_PROCESSORS ; All ; -- ; -- ; -- ;
-; TOP_LEVEL_ENTITY ; top ; lvds_monitor ; -- ; -- ;
-; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
-+-------------------------+---------------------------------+---------------+-------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4878 MB ; 00:00:16 ;
-; Fitter ; 00:00:04 ; 1.3 ; 6367 MB ; 00:00:08 ;
-; Assembler ; 00:00:01 ; 1.0 ; 4743 MB ; 00:00:01 ;
-; Timing Analyzer ; 00:00:01 ; 1.4 ; 4946 MB ; 00:00:02 ;
-; Total ; 00:00:15 ; -- ; -- ; 00:00:27 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+------------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+------------+------------+----------------+
-; Analysis & Synthesis ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
-; Fitter ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
-; Assembler ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
-; Timing Analyzer ; LT-8M62C04 ; Windows 10 ; 10.0 ; x86_64 ;
-+----------------------+------------------+------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor
-quartus_fit --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor
-quartus_asm --read_settings_files=off --write_settings_files=off lvds_monitor -c lvds_monitor
-quartus_sta lvds_monitor -c lvds_monitor
-
-
-
diff --git a/lvds_monitor.jdi b/lvds_monitor.jdi
deleted file mode 100644
index 39819e1..0000000
--- a/lvds_monitor.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/lvds_monitor.jditmp b/lvds_monitor.jditmp
deleted file mode 100644
index 39819e1..0000000
--- a/lvds_monitor.jditmp
+++ /dev/null
@@ -1,8 +0,0 @@
-
-
-
-
-
-
-
-
diff --git a/lvds_monitor.map.rpt b/lvds_monitor.map.rpt
deleted file mode 100644
index d56604b..0000000
--- a/lvds_monitor.map.rpt
+++ /dev/null
@@ -1,450 +0,0 @@
-Analysis & Synthesis report for lvds_monitor
-Wed Jun 10 09:07:02 2026
-Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. State Machine - |top|fstate
- 9. State Machine - |top|uart_tx:u_uart|state
- 10. Registers Removed During Synthesis
- 11. Removed Registers Triggering Further Register Optimizations
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Parameter Settings for User Entity Instance: de_monitor:u_mon
- 16. Parameter Settings for User Entity Instance: uart_tx:u_uart
- 17. Post-Synthesis Netlist Statistics for Top Partition
- 18. Elapsed Time Per Partition
- 19. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2025 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Altera and sold by Altera or its authorized distributors. Please
-refer to the Altera Software License Subscription Agreements
-on the Quartus Prime software download page.
-
-
-
-+--------------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+------------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Jun 10 09:07:02 2026 ;
-; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
-; Revision Name ; lvds_monitor ;
-; Top-level Entity Name ; top ;
-; Family ; Cyclone IV E ;
-; Total logic elements ; 1,990 ;
-; Total combinational functions ; 1,853 ;
-; Dedicated logic registers ; 319 ;
-; Total registers ; 319 ;
-; Total pins ; 7 ;
-; Total virtual pins ; 0 ;
-; Total memory bits ; 0 ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; Total PLLs ; 0 ;
-+------------------------------------+-------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+------------------------------------------------------------------+--------------------+--------------------+
-; Device ; EP4CE6E22C8 ; ;
-; Top-level entity name ; top ; lvds_monitor ;
-; Family name ; Cyclone IV E ; Cyclone V ;
-; Maximum processors allowed for parallel compilation ; All ; ;
-; Verilog Version ; SystemVerilog_2005 ; Verilog_2001 ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto RAM Block Balancing ; On ; On ;
-; Auto RAM to Logic Cell Conversion ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 2 ; 2 ;
-; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-+------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 20 ;
-; Maximum allowed ; 14 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 14 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.1% ;
-; Processor 3 ; 0.1% ;
-; Processor 4 ; 0.0% ;
-; Processor 5 ; 0.0% ;
-; Processors 6-14 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+------------------------+-------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+------------------------+-------------------------------------------------------------+---------+
-; de_monitor.v ; yes ; User Verilog HDL File ; C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v ; ;
-; uart_tx.v ; yes ; User Verilog HDL File ; C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v ; ;
-; top.v ; yes ; User Verilog HDL File ; C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v ; ;
-+----------------------------------+-----------------+------------------------+-------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+--------------+
-; Resource ; Usage ;
-+---------------------------------------------+--------------+
-; Estimated Total logic elements ; 1,990 ;
-; ; ;
-; Total combinational functions ; 1853 ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 855 ;
-; -- 3 input functions ; 149 ;
-; -- <=2 input functions ; 849 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 1128 ;
-; -- arithmetic mode ; 725 ;
-; ; ;
-; Total registers ; 319 ;
-; -- Dedicated logic registers ; 319 ;
-; -- I/O registers ; 0 ;
-; ; ;
-; I/O pins ; 7 ;
-; ; ;
-; Embedded Multiplier 9-bit elements ; 0 ;
-; ; ;
-; Maximum fan-out node ; rx_clk~input ;
-; Maximum fan-out ; 162 ;
-; Total fan-out ; 6831 ;
-; Average fan-out ; 3.12 ;
-+---------------------------------------------+--------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
-; |top ; 1853 (1701) ; 319 (173) ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |top ; top ; work ;
-; |de_monitor:u_mon| ; 127 (127) ; 117 (117) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|de_monitor:u_mon ; de_monitor ; work ;
-; |uart_tx:u_uart| ; 25 (25) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |top|uart_tx:u_uart ; uart_tx ; work ;
-+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-Encoding Type: One-Hot
-+-------------------------------------------------------------------------------------+
-; State Machine - |top|fstate ;
-+------------------+---------------+---------------+------------------+---------------+
-; Name ; fstate.F_WAIT ; fstate.F_LOAD ; fstate.F_CONVERT ; fstate.F_IDLE ;
-+------------------+---------------+---------------+------------------+---------------+
-; fstate.F_IDLE ; 0 ; 0 ; 0 ; 0 ;
-; fstate.F_CONVERT ; 0 ; 0 ; 1 ; 1 ;
-; fstate.F_LOAD ; 0 ; 1 ; 0 ; 1 ;
-; fstate.F_WAIT ; 1 ; 0 ; 0 ; 1 ;
-+------------------+---------------+---------------+------------------+---------------+
-
-
-Encoding Type: One-Hot
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |top|uart_tx:u_uart|state ;
-+---------------+--------------+------------+------------+------------+------------+------------+------------+------------+------------+---------------+--------------+
-; Name ; state.S_STOP ; state.S_D7 ; state.S_D6 ; state.S_D5 ; state.S_D4 ; state.S_D3 ; state.S_D2 ; state.S_D1 ; state.S_D0 ; state.S_START ; state.S_IDLE ;
-+---------------+--------------+------------+------------+------------+------------+------------+------------+------------+------------+---------------+--------------+
-; state.S_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; state.S_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
-; state.S_D0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
-; state.S_D1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
-; state.S_D2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
-; state.S_D3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; state.S_D4 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; state.S_D5 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; state.S_D6 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; state.S_D7 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-; state.S_STOP ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
-+---------------+--------------+------------+------------+------------+------------+------------+------------+------------+------------+---------------+--------------+
-
-
-+---------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+----------------------------------------+----------------------------------------+
-; Register name ; Reason for Removal ;
-+----------------------------------------+----------------------------------------+
-; msg_len[2,5] ; Stuck at GND due to stuck port data_in ;
-; tx_byte[7] ; Stuck at GND due to stuck port data_in ;
-; uart_tx:u_uart|shift[7] ; Stuck at GND due to stuck port data_in ;
-; msg_len[3,4] ; Merged with is_err_msg ;
-; fstate~8 ; Lost fanout ;
-; fstate~9 ; Lost fanout ;
-; uart_tx:u_uart|state~15 ; Lost fanout ;
-; uart_tx:u_uart|state~16 ; Lost fanout ;
-; uart_tx:u_uart|state~17 ; Lost fanout ;
-; uart_tx:u_uart|state~18 ; Lost fanout ;
-; req_tog ; Merged with hb_count[0] ;
-; Total Number of Removed Registers = 13 ; ;
-+----------------------------------------+----------------------------------------+
-
-
-+------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations ;
-+---------------+---------------------------+----------------------------------------+
-; Register name ; Reason for Removal ; Registers Removed due to This Register ;
-+---------------+---------------------------+----------------------------------------+
-; tx_byte[7] ; Stuck at GND ; uart_tx:u_uart|shift[7] ;
-; ; due to stuck port data_in ; ;
-+---------------+---------------------------+----------------------------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 319 ;
-; Number of registers using Synchronous Clear ; 32 ;
-; Number of registers using Synchronous Load ; 25 ;
-; Number of registers using Asynchronous Clear ; 319 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 287 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+--------------------------------------------------+
-; Inverted Register Statistics ;
-+----------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+----------------------------------------+---------+
-; uart_tx:u_uart|tx ; 2 ;
-; Total number of inverted registers = 1 ; ;
-+----------------------------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
-; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |top|uart_tx:u_uart|tick[2] ;
-; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |top|de_monitor:u_mon|line_width[0] ;
-; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |top|de_monitor:u_mon|line_count[4] ;
-; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |top|de_monitor:u_mon|bad_width[0] ;
-; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |top|conv_step[1] ;
-; 5:1 ; 16 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |top|de_monitor:u_mon|gap_count[12] ;
-; 5:1 ; 6 bits ; 18 LEs ; 6 LEs ; 12 LEs ; Yes ; |top|idx[5] ;
-; 65:1 ; 4 bits ; 172 LEs ; 80 LEs ; 92 LEs ; Yes ; |top|tx_byte[0] ;
-; 34:1 ; 10 bits ; 220 LEs ; 180 LEs ; 40 LEs ; Yes ; |top|l_rem[15] ;
-; 34:1 ; 10 bits ; 220 LEs ; 180 LEs ; 40 LEs ; Yes ; |top|w_rem[12] ;
-; 3:1 ; 9 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |top|uart_tx:u_uart|state ;
-; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |top|Selector39 ;
-; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |top|Selector40 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------+
-
-
-+---------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: de_monitor:u_mon ;
-+----------------+------------------+---------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+------------------+---------------------------+
-; EXPECTED_LINES ; 0000001100100000 ; Unsigned Binary ;
-; EXPECTED_WIDTH ; 0000010100000000 ; Unsigned Binary ;
-; FRAME_GAP_PIX ; 0000100000000000 ; Unsigned Binary ;
-+----------------+------------------+---------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: uart_tx:u_uart ;
-+----------------+----------+---------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+----------+---------------------------------+
-; CLK_HZ ; 50000000 ; Signed Integer ;
-; BAUD ; 115200 ; Signed Integer ;
-+----------------+----------+---------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; boundary_port ; 7 ;
-; cycloneiii_ff ; 319 ;
-; CLR ; 22 ;
-; CLR SCLR ; 9 ;
-; CLR SLD ; 1 ;
-; ENA CLR ; 240 ;
-; ENA CLR SCLR ; 23 ;
-; ENA CLR SLD ; 24 ;
-; cycloneiii_lcell_comb ; 1854 ;
-; arith ; 725 ;
-; 2 data inputs ; 725 ;
-; normal ; 1129 ;
-; 0 data inputs ; 1 ;
-; 1 data inputs ; 63 ;
-; 2 data inputs ; 61 ;
-; 3 data inputs ; 149 ;
-; 4 data inputs ; 855 ;
-; ; ;
-; Max LUT depth ; 13.00 ;
-; Average LUT depth ; 7.35 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:03 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Wed Jun 10 09:06:53 2026
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lvds_monitor -c lvds_monitor
-Info (20030): Parallel compilation is enabled and will use 14 of the 14 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file de_monitor.v
- Info (12023): Found entity 1: de_monitor File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/de_monitor.v Line: 23
-Info (12021): Found 1 design units, including 1 entities, in source file uart_tx.v
- Info (12023): Found entity 1: uart_tx File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v Line: 10
-Info (12021): Found 1 design units, including 1 entities, in source file top.v
- Info (12023): Found entity 1: top File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 22
-Info (12127): Elaborating entity "top" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at top.v(33): object "_unused" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 33
-Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L0_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
-Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L1_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
-Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L2_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
-Warning (10036): Verilog HDL or VHDL warning at top.v(136): object "L3_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 136
-Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W0_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
-Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W1_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
-Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W2_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
-Warning (10036): Verilog HDL or VHDL warning at top.v(137): object "W3_r" assigned a value but never read File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 137
-Info (12128): Elaborating entity "de_monitor" for hierarchy "de_monitor:u_mon" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 81
-Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:u_uart" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 359
-Info (10264): Verilog HDL Case Statement information at uart_tx.v(60): all case item expressions in this case statement are onehot File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v Line: 60
-Info (13000): Registers with preset signals will power-up high File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/uart_tx.v Line: 18
-Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 6 registers lost all their fanouts during netlist optimizations.
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 2 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "vsync" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 26
- Warning (15610): No output dependent on input pin "hsync" File: C:/Users/DavidRice/Documents/fpga/lvds_monitor/top.v Line: 27
-Info (21057): Implemented 2001 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 6 input pins
- Info (21059): Implemented 1 output pins
- Info (21061): Implemented 1994 logic cells
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
- Info: Peak virtual memory: 4878 megabytes
- Info: Processing ended: Wed Jun 10 09:07:02 2026
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:16
-
-
diff --git a/lvds_monitor.map.summary b/lvds_monitor.map.summary
deleted file mode 100644
index ddf135b..0000000
--- a/lvds_monitor.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Wed Jun 10 09:07:02 2026
-Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-Revision Name : lvds_monitor
-Top-level Entity Name : top
-Family : Cyclone IV E
-Total logic elements : 1,990
- Total combinational functions : 1,853
- Dedicated logic registers : 319
-Total registers : 319
-Total pins : 7
-Total virtual pins : 0
-Total memory bits : 0
-Embedded Multiplier 9-bit elements : 0
-Total PLLs : 0
diff --git a/lvds_monitor.pin b/lvds_monitor.pin
deleted file mode 100644
index c27da00..0000000
--- a/lvds_monitor.pin
+++ /dev/null
@@ -1,216 +0,0 @@
- -- Copyright (C) 2025 Altera Corporation. All rights reserved.
- -- Your use of Altera Corporation's design tools, logic functions
- -- and other software and tools, and any partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Altera Program License
- -- Subscription Agreement, the Altera Quartus Prime License Agreement,
- -- the Altera IP License Agreement, or other applicable license
- -- agreement, including, without limitation, that your use is for
- -- the sole purpose of programming logic devices manufactured by
- -- Altera and sold by Altera or its authorized distributors. Please
- -- refer to the Altera Software License Subscription Agreements
- -- on the Quartus Prime software download page.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 1: 3.3V
- -- Bank 2: 3.3V
- -- Bank 3: 2.5V
- -- Bank 4: 2.5V
- -- Bank 5: 3.3V
- -- Bank 6: 2.5V
- -- Bank 7: 2.5V
- -- Bank 8: 2.5V
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-CHIP "lvds_monitor" ASSIGNED TO AN: EP4CE6E22C8
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 :
-GND : 4 : gnd : : : :
-VCCINT : 5 : power : : 1.2V : :
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 3.3-V LVTTL : : 1 : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 :
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 3.3-V LVTTL : : 1 : N
-nSTATUS : 9 : : : : 1 :
-uart_tx_pin : 10 : output : 3.3-V LVTTL : : 1 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 :
-~ALTERA_DCLK~ : 12 : output : 3.3-V LVTTL : : 1 : N
-~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 3.3-V LVTTL : : 1 : N
-nCONFIG : 14 : : : : 1 :
-TDI : 15 : input : : : 1 :
-TCK : 16 : input : : : 1 :
-VCCIO1 : 17 : power : : 3.3V : 1 :
-TMS : 18 : input : : : 1 :
-GND : 19 : gnd : : : :
-TDO : 20 : output : : : 1 :
-nCE : 21 : : : : 1 :
-GND : 22 : gnd : : : :
-GND+ : 23 : : : : 1 :
-clk_50mhz : 24 : input : 3.3-V LVTTL : : 2 : Y
-GND+ : 25 : : : : 2 :
-VCCIO2 : 26 : power : : 3.3V : 2 :
-GND : 27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 :
-VCCINT : 29 : power : : 1.2V : :
-rx_clk : 30 : input : 3.3-V LVTTL : : 2 : Y
-de : 31 : input : 3.3-V LVTTL : : 2 : Y
-vsync : 32 : input : 3.3-V LVTTL : : 2 : Y
-hsync : 33 : input : 3.3-V LVTTL : : 2 : Y
-RESERVED_INPUT_WITH_WEAK_PULLUP : 34 : : : : 2 :
-VCCA1 : 35 : power : : 2.5V : :
-GNDA1 : 36 : gnd : : : :
-VCCD_PLL1 : 37 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 :
-VCCIO3 : 40 : power : : 2.5V : 3 :
-GND : 41 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 :
-VCCINT : 45 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 :
-VCCIO3 : 47 : power : : 2.5V : 3 :
-GND : 48 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 :
-VCCIO4 : 56 : power : : 2.5V : 4 :
-GND : 57 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 :
-VCCINT : 61 : power : : 1.2V : :
-VCCIO4 : 62 : power : : 2.5V : 4 :
-GND : 63 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 74 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 :
-VCCINT : 78 : power : : 1.2V : :
-GND : 79 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 5 :
-VCCIO5 : 81 : power : : 3.3V : 5 :
-GND : 82 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 :
-rst_n_pin : 88 : input : 3.3-V LVTTL : : 5 : Y
-GND+ : 89 : : : : 5 :
-GND+ : 90 : : : : 6 :
-GND+ : 91 : : : : 6 :
-CONF_DONE : 92 : : : : 6 :
-VCCIO6 : 93 : power : : 2.5V : 6 :
-MSEL0 : 94 : : : : 6 :
-GND : 95 : gnd : : : :
-MSEL1 : 96 : : : : 6 :
-MSEL2 : 97 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 101 : : : : 6 :
-VCCINT : 102 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 :
-VCCA2 : 107 : power : : 2.5V : :
-GNDA2 : 108 : gnd : : : :
-VCCD_PLL2 : 109 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 :
-VCCINT : 116 : power : : 1.2V : :
-VCCIO7 : 117 : power : : 2.5V : 7 :
-GND : 118 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 119 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 120 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 121 : : : : 7 :
-VCCIO7 : 122 : power : : 2.5V : 7 :
-GND : 123 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 124 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 125 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 127 : : : : 7 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 128 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 :
-VCCIO8 : 130 : power : : 2.5V : 8 :
-GND : 131 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 132 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 133 : : : : 8 :
-VCCINT : 134 : power : : 1.2V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 135 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 136 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 137 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 138 : : : : 8 :
-VCCIO8 : 139 : power : : 2.5V : 8 :
-GND : 140 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 :
-GND : EPAD : : : : :
diff --git a/lvds_monitor.qpf b/lvds_monitor.qpf
deleted file mode 100644
index e1c01b3..0000000
--- a/lvds_monitor.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2025 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, the Altera Quartus Prime License Agreement,
-# the Altera IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Altera and sold by Altera or its authorized distributors. Please
-# refer to the Altera Software License Subscription Agreements
-# on the Quartus Prime software download page.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-# Date created = 08:48:23 June 10, 2026
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "25.1"
-DATE = "08:48:23 June 10, 2026"
-
-# Revisions
-
-PROJECT_REVISION = "lvds_monitor"
diff --git a/lvds_monitor.qsf b/lvds_monitor.qsf
deleted file mode 100644
index f25b171..0000000
--- a/lvds_monitor.qsf
+++ /dev/null
@@ -1,68 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2025 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and any partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, the Altera Quartus Prime License Agreement,
-# the Altera IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Altera and sold by Altera or its authorized distributors. Please
-# refer to the Altera Software License Subscription Agreements
-# on the Quartus Prime software download page.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-# Date created = 08:48:23 June 10, 2026
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# lvds_monitor_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Intel recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE6E22C8
-set_global_assignment -name TOP_LEVEL_ENTITY top
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 25.1STD.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:48:23 JUNE 10, 2026"
-set_global_assignment -name LAST_QUARTUS_VERSION "25.1std.0 Lite Edition"
-set_global_assignment -name VERILOG_FILE de_monitor.v
-set_global_assignment -name VERILOG_FILE uart_tx.v
-set_global_assignment -name VERILOG_FILE top.v
-set_global_assignment -name SDC_FILE lvds_monitor.sdc
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_location_assignment PIN_24 -to clk_50mhz
-set_location_assignment PIN_10 -to uart_tx_pin
-set_location_assignment PIN_88 -to rst_n_pin
-set_location_assignment PIN_30 -to rx_clk
-set_location_assignment PIN_31 -to de
-set_location_assignment PIN_32 -to vsync
-set_location_assignment PIN_33 -to hsync
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_50mhz
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_tx_pin
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n_pin
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rx_clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to de
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vsync
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hsync
\ No newline at end of file
diff --git a/lvds_monitor.sld b/lvds_monitor.sld
deleted file mode 100644
index f7d3ed7..0000000
--- a/lvds_monitor.sld
+++ /dev/null
@@ -1 +0,0 @@
-
diff --git a/lvds_monitor.sof b/lvds_monitor.sof
deleted file mode 100644
index 6b2288b..0000000
Binary files a/lvds_monitor.sof and /dev/null differ
diff --git a/lvds_monitor.sta.rpt b/lvds_monitor.sta.rpt
deleted file mode 100644
index 43e3af7..0000000
--- a/lvds_monitor.sta.rpt
+++ /dev/null
@@ -1,3234 +0,0 @@
-Timing Analyzer report for lvds_monitor
-Wed Jun 10 09:07:11 2026
-Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Timing Analyzer Summary
- 3. Parallel Compilation
- 4. SDC File List
- 5. Clocks
- 6. Slow 1200mV 85C Model Fmax Summary
- 7. Timing Closure Recommendations
- 8. Slow 1200mV 85C Model Setup Summary
- 9. Slow 1200mV 85C Model Hold Summary
- 10. Slow 1200mV 85C Model Recovery Summary
- 11. Slow 1200mV 85C Model Removal Summary
- 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 13. Slow 1200mV 85C Model Setup: 'clk_50mhz'
- 14. Slow 1200mV 85C Model Setup: 'rx_clk'
- 15. Slow 1200mV 85C Model Hold: 'clk_50mhz'
- 16. Slow 1200mV 85C Model Hold: 'rx_clk'
- 17. Slow 1200mV 85C Model Recovery: 'rx_clk'
- 18. Slow 1200mV 85C Model Recovery: 'clk_50mhz'
- 19. Slow 1200mV 85C Model Removal: 'clk_50mhz'
- 20. Slow 1200mV 85C Model Removal: 'rx_clk'
- 21. Slow 1200mV 85C Model Metastability Summary
- 22. Slow 1200mV 0C Model Fmax Summary
- 23. Slow 1200mV 0C Model Setup Summary
- 24. Slow 1200mV 0C Model Hold Summary
- 25. Slow 1200mV 0C Model Recovery Summary
- 26. Slow 1200mV 0C Model Removal Summary
- 27. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 28. Slow 1200mV 0C Model Setup: 'clk_50mhz'
- 29. Slow 1200mV 0C Model Setup: 'rx_clk'
- 30. Slow 1200mV 0C Model Hold: 'clk_50mhz'
- 31. Slow 1200mV 0C Model Hold: 'rx_clk'
- 32. Slow 1200mV 0C Model Recovery: 'rx_clk'
- 33. Slow 1200mV 0C Model Recovery: 'clk_50mhz'
- 34. Slow 1200mV 0C Model Removal: 'clk_50mhz'
- 35. Slow 1200mV 0C Model Removal: 'rx_clk'
- 36. Slow 1200mV 0C Model Metastability Summary
- 37. Fast 1200mV 0C Model Setup Summary
- 38. Fast 1200mV 0C Model Hold Summary
- 39. Fast 1200mV 0C Model Recovery Summary
- 40. Fast 1200mV 0C Model Removal Summary
- 41. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 42. Fast 1200mV 0C Model Setup: 'rx_clk'
- 43. Fast 1200mV 0C Model Setup: 'clk_50mhz'
- 44. Fast 1200mV 0C Model Hold: 'clk_50mhz'
- 45. Fast 1200mV 0C Model Hold: 'rx_clk'
- 46. Fast 1200mV 0C Model Recovery: 'rx_clk'
- 47. Fast 1200mV 0C Model Recovery: 'clk_50mhz'
- 48. Fast 1200mV 0C Model Removal: 'clk_50mhz'
- 49. Fast 1200mV 0C Model Removal: 'rx_clk'
- 50. Fast 1200mV 0C Model Metastability Summary
- 51. Multicorner Timing Analysis Summary
- 52. Board Trace Model Assignments
- 53. Input Transition Times
- 54. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 55. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 56. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 57. Setup Transfers
- 58. Hold Transfers
- 59. Recovery Transfers
- 60. Removal Transfers
- 61. Report TCCS
- 62. Report RSKM
- 63. Unconstrained Paths Summary
- 64. Clock Status Summary
- 65. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2025 Altera Corporation. All rights reserved.
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and any partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, the Altera Quartus Prime License Agreement,
-the Altera IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Altera and sold by Altera or its authorized distributors. Please
-refer to the Altera Software License Subscription Agreements
-on the Quartus Prime software download page.
-
-
-
-+---------------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+-----------------------+---------------------------------------------------------+
-; Quartus Prime Version ; Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ;
-; Timing Analyzer ; Legacy Timing Analyzer ;
-; Revision Name ; lvds_monitor ;
-; Device Family ; Cyclone IV E ;
-; Device Name ; EP4CE6E22C8 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+---------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 20 ;
-; Maximum allowed ; 14 ;
-; ; ;
-; Average used ; 1.42 ;
-; Maximum used ; 14 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 5.1% ;
-; Processors 3-14 ; 3.1% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------+
-; SDC File List ;
-+------------------+--------+--------------------------+
-; SDC File Path ; Status ; Read at ;
-+------------------+--------+--------------------------+
-; lvds_monitor.sdc ; OK ; Wed Jun 10 09:07:10 2026 ;
-+------------------+--------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
-; clk_50mhz ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { clk_50mhz } ;
-; rx_clk ; Base ; 13.500 ; 74.07 MHz ; 0.000 ; 6.750 ; ; ; ; ; ; ; ; ; ; ; { rx_clk } ;
-+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
-
-
-+--------------------------------------------------+
-; Slow 1200mV 85C Model Fmax Summary ;
-+------------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 63.46 MHz ; 63.46 MHz ; clk_50mhz ; ;
-; 155.26 MHz ; 155.26 MHz ; rx_clk ; ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+-------------------------------------+
-; Slow 1200mV 85C Model Setup Summary ;
-+-----------+-------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+-----------------+
-; clk_50mhz ; 4.242 ; 0.000 ;
-; rx_clk ; 7.059 ; 0.000 ;
-+-----------+-------+-----------------+
-
-
-+------------------------------------+
-; Slow 1200mV 85C Model Hold Summary ;
-+-----------+-------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+----------------+
-; clk_50mhz ; 0.452 ; 0.000 ;
-; rx_clk ; 0.452 ; 0.000 ;
-+-----------+-------+----------------+
-
-
-+----------------------------------------+
-; Slow 1200mV 85C Model Recovery Summary ;
-+-----------+--------+-------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+--------+-------------------+
-; rx_clk ; 8.730 ; 0.000 ;
-; clk_50mhz ; 15.869 ; 0.000 ;
-+-----------+--------+-------------------+
-
-
-+---------------------------------------+
-; Slow 1200mV 85C Model Removal Summary ;
-+-----------+-------+-------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+-------------------+
-; clk_50mhz ; 3.067 ; 0.000 ;
-; rx_clk ; 4.061 ; 0.000 ;
-+-----------+-------+-------------------+
-
-
-+---------------------------------------------------+
-; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-+-----------+-------+-------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+-------------------------------+
-; rx_clk ; 6.480 ; 0.000 ;
-; clk_50mhz ; 9.735 ; 0.000 ;
-+-----------+-------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'clk_50mhz' ;
-+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-; 4.242 ; l_rem[6] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 15.677 ;
-; 4.611 ; l_rem[7] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 15.315 ;
-; 4.700 ; l_rem[3] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 15.209 ;
-; 4.810 ; w_rem[7] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 15.110 ;
-; 4.854 ; w_rem[6] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 15.059 ;
-; 4.933 ; l_rem[6] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 14.986 ;
-; 4.940 ; l_rem[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 14.994 ;
-; 4.953 ; l_rem[6] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 14.966 ;
-; 5.177 ; l_rem[6] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 14.736 ;
-; 5.222 ; l_rem[8] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.698 ;
-; 5.268 ; l_rem[6] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 14.645 ;
-; 5.300 ; l_rem[6] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 14.619 ;
-; 5.302 ; l_rem[7] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 14.624 ;
-; 5.322 ; l_rem[7] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 14.604 ;
-; 5.375 ; w_rem[5] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.534 ;
-; 5.391 ; l_rem[3] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.518 ;
-; 5.411 ; l_rem[3] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.498 ;
-; 5.422 ; w_rem[3] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 14.485 ;
-; 5.443 ; l_rem[5] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.466 ;
-; 5.504 ; l_rem[4] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.405 ;
-; 5.527 ; l_rem[12] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.393 ;
-; 5.546 ; l_rem[7] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.374 ;
-; 5.568 ; w_rem[3] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.341 ;
-; 5.570 ; w_rem[2] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.063 ; 14.368 ;
-; 5.578 ; l_rem[6] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.342 ;
-; 5.586 ; l_rem[10] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.334 ;
-; 5.595 ; w_rem[11] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.080 ; 14.326 ;
-; 5.631 ; l_rem[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 14.303 ;
-; 5.635 ; l_rem[3] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.098 ; 14.268 ;
-; 5.637 ; l_rem[7] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.283 ;
-; 5.651 ; l_rem[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 14.283 ;
-; 5.662 ; w_rem[8] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 14.268 ;
-; 5.669 ; l_rem[7] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 14.257 ;
-; 5.709 ; w_rem[6] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.090 ; 14.202 ;
-; 5.726 ; l_rem[3] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.098 ; 14.177 ;
-; 5.726 ; l_rem[9] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 14.200 ;
-; 5.745 ; l_rem[11] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.175 ;
-; 5.758 ; l_rem[3] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 14.151 ;
-; 5.874 ; w_rem[4] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 14.033 ;
-; 5.875 ; l_rem[2] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 14.053 ;
-; 5.913 ; l_rem[8] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 14.007 ;
-; 5.933 ; l_rem[8] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.987 ;
-; 5.944 ; w_rem[13] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.976 ;
-; 5.966 ; l_rem[2] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.962 ;
-; 5.982 ; w_rem[5] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 13.925 ;
-; 5.988 ; w_rem[7] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.932 ;
-; 5.992 ; w_rem[12] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.928 ;
-; 5.998 ; l_rem[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 13.936 ;
-; 6.001 ; w_rem[10] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.919 ;
-; 6.010 ; w_rem[7] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.091 ; 13.900 ;
-; 6.012 ; l_rem[1] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.101 ; 13.888 ;
-; 6.014 ; w_rem[7] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.087 ; 13.900 ;
-; 6.020 ; l_rem[14] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.899 ;
-; 6.031 ; l_rem[7] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.074 ; 13.896 ;
-; 6.032 ; w_rem[6] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 13.881 ;
-; 6.036 ; l_rem[12] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.884 ;
-; 6.049 ; l_rem[6] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 13.864 ;
-; 6.054 ; w_rem[6] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.098 ; 13.849 ;
-; 6.067 ; l_rem[6] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.853 ;
-; 6.070 ; w_rem[6] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.849 ;
-; 6.095 ; l_rem[10] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.825 ;
-; 6.102 ; w_rem[9] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.818 ;
-; 6.113 ; l_rem[3] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.091 ; 13.797 ;
-; 6.134 ; l_rem[5] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 13.775 ;
-; 6.148 ; l_rem[15] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 13.778 ;
-; 6.151 ; w_rem[3] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 13.757 ;
-; 6.154 ; l_rem[5] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 13.755 ;
-; 6.157 ; l_rem[8] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.087 ; 13.757 ;
-; 6.161 ; w_rem[4] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 13.748 ;
-; 6.167 ; w_rem[3] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 13.740 ;
-; 6.195 ; l_rem[4] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 13.714 ;
-; 6.196 ; w_rem[9] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 13.722 ;
-; 6.215 ; l_rem[4] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 13.694 ;
-; 6.216 ; l_rem[13] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.703 ;
-; 6.218 ; l_rem[12] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.702 ;
-; 6.238 ; l_rem[12] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.682 ;
-; 6.241 ; w_rem[3] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 13.666 ;
-; 6.248 ; l_rem[8] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.087 ; 13.666 ;
-; 6.254 ; l_rem[11] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.666 ;
-; 6.260 ; l_rem[5] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 13.649 ;
-; 6.277 ; l_rem[10] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.643 ;
-; 6.280 ; l_rem[8] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.640 ;
-; 6.295 ; l_rem[5] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.625 ;
-; 6.297 ; l_rem[10] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.623 ;
-; 6.352 ; w_rem[14] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.080 ; 13.569 ;
-; 6.378 ; l_rem[5] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.098 ; 13.525 ;
-; 6.381 ; w_rem[9] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 13.537 ;
-; 6.381 ; l_rem[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.066 ; 13.554 ;
-; 6.388 ; l_rem[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.532 ;
-; 6.397 ; w_rem[3] ; w_rem[9] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 13.511 ;
-; 6.401 ; l_rem[12] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.080 ; 13.520 ;
-; 6.403 ; l_rem[6] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 13.527 ;
-; 6.405 ; w_rem[7] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 13.513 ;
-; 6.416 ; w_rem[8] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.512 ;
-; 6.417 ; l_rem[9] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 13.509 ;
-; 6.423 ; l_rem[6] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 13.507 ;
-; 6.430 ; w_rem[3] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.489 ;
-; 6.436 ; l_rem[7] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.074 ; 13.491 ;
-; 6.436 ; l_rem[11] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.484 ;
-; 6.437 ; l_rem[9] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 13.489 ;
-+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Setup: 'rx_clk' ;
-+-------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-; 7.059 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.105 ; 6.337 ;
-; 7.059 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.105 ; 6.337 ;
-; 7.059 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.105 ; 6.337 ;
-; 7.059 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.105 ; 6.337 ;
-; 7.059 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.105 ; 6.337 ;
-; 7.059 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.105 ; 6.337 ;
-; 7.070 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.111 ; 6.320 ;
-; 7.070 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.111 ; 6.320 ;
-; 7.070 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.111 ; 6.320 ;
-; 7.070 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.111 ; 6.320 ;
-; 7.231 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.164 ;
-; 7.231 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.164 ;
-; 7.231 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.164 ;
-; 7.231 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.164 ;
-; 7.231 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.164 ;
-; 7.231 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.164 ;
-; 7.241 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.154 ;
-; 7.241 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.154 ;
-; 7.241 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.154 ;
-; 7.241 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.154 ;
-; 7.241 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.154 ;
-; 7.241 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.154 ;
-; 7.242 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.147 ;
-; 7.242 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.147 ;
-; 7.242 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.147 ;
-; 7.242 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.147 ;
-; 7.252 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.137 ;
-; 7.252 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.137 ;
-; 7.252 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.137 ;
-; 7.252 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.137 ;
-; 7.334 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.061 ;
-; 7.334 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.061 ;
-; 7.334 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.061 ;
-; 7.334 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.061 ;
-; 7.334 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.061 ;
-; 7.334 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 6.061 ;
-; 7.345 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.044 ;
-; 7.345 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.044 ;
-; 7.345 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.044 ;
-; 7.345 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 6.044 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.506 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.905 ;
-; 7.507 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.096 ; 5.898 ;
-; 7.529 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.881 ;
-; 7.529 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.881 ;
-; 7.529 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.881 ;
-; 7.529 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.881 ;
-; 7.529 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.881 ;
-; 7.529 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.881 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.539 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 5.872 ;
-; 7.574 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 5.821 ;
-; 7.574 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 5.821 ;
-; 7.574 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 5.821 ;
-; 7.574 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 5.821 ;
-; 7.574 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 5.821 ;
-; 7.574 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.106 ; 5.821 ;
-; 7.588 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 5.801 ;
-; 7.588 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 5.801 ;
-; 7.588 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 5.801 ;
-; 7.588 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.112 ; 5.801 ;
-; 7.616 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.092 ; 5.793 ;
-; 7.616 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.092 ; 5.793 ;
-; 7.616 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.092 ; 5.793 ;
-; 7.616 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.092 ; 5.793 ;
-; 7.616 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.092 ; 5.793 ;
-; 7.616 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.092 ; 5.793 ;
-; 7.664 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.081 ; 5.756 ;
-; 7.664 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.081 ; 5.756 ;
-; 7.664 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.081 ; 5.756 ;
-; 7.664 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.081 ; 5.756 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.678 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.732 ;
-; 7.679 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.097 ; 5.725 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-; 7.688 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.091 ; 5.722 ;
-+-------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'clk_50mhz' ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.452 ; w_rem[5] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.746 ;
-; 0.452 ; w_rem[3] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.746 ;
-; 0.452 ; w_rem[4] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.746 ;
-; 0.453 ; l_rem[5] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; l_rem[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; l_rem[4] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; uart_tx:u_uart|busy ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; fstate.F_WAIT ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; conv_step[1] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.453 ; conv_step[0] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.746 ;
-; 0.500 ; rst_sync_uart[1] ; rst_sync_uart[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.794 ;
-; 0.500 ; rst_sync_uart[0] ; rst_sync_uart[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.794 ;
-; 0.500 ; uart_tx:u_uart|state.S_D6 ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.794 ;
-; 0.501 ; uart_tx:u_uart|tick[8] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.794 ;
-; 0.503 ; width_u[0] ; w_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.797 ;
-; 0.503 ; lines_u[2] ; l_rem[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.080 ; 0.795 ;
-; 0.508 ; uart_tx:u_uart|state.S_D2 ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.802 ;
-; 0.508 ; uart_tx:u_uart|state.S_D1 ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.802 ;
-; 0.509 ; uart_tx:u_uart|state.S_D3 ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.803 ;
-; 0.525 ; uart_tx:u_uart|state.S_D5 ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.819 ;
-; 0.544 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.837 ;
-; 0.555 ; conv_step[0] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.848 ;
-; 0.594 ; fstate.F_CONVERT ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.887 ;
-; 0.667 ; uart_tx:u_uart|state.S_START ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.960 ;
-; 0.697 ; lines_u[1] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.991 ;
-; 0.697 ; uart_tx:u_uart|state.S_D0 ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.991 ;
-; 0.698 ; lines_u[0] ; l_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.992 ;
-; 0.699 ; width_u[4] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.993 ;
-; 0.699 ; lines_u[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.992 ;
-; 0.701 ; width_u[5] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 0.995 ;
-; 0.701 ; lines_u[4] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.994 ;
-; 0.706 ; uart_tx:u_uart|state.S_D4 ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.000 ;
-; 0.706 ; req_sync[1] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 0.999 ;
-; 0.722 ; uart_tx:u_uart|state.S_D7 ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.016 ;
-; 0.727 ; uart_tx:u_uart|state.S_STOP ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.020 ;
-; 0.729 ; uart_tx:u_uart|state.S_STOP ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.022 ;
-; 0.730 ; fstate.F_LOAD ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.024 ;
-; 0.744 ; uart_tx:u_uart|tick[1] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.037 ;
-; 0.744 ; uart_tx:u_uart|tick[3] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.037 ;
-; 0.745 ; uart_tx:u_uart|tick[5] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.038 ;
-; 0.746 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.039 ;
-; 0.747 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.040 ;
-; 0.747 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.040 ;
-; 0.747 ; uart_tx:u_uart|tick[7] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.040 ;
-; 0.769 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.062 ;
-; 0.774 ; idx[5] ; idx[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.067 ;
-; 0.802 ; idx[1] ; idx[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.095 ;
-; 0.813 ; idx[4] ; idx[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.106 ;
-; 0.819 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|tx ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.112 ;
-; 0.821 ; idx[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.114 ;
-; 0.830 ; width_u[12] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.123 ;
-; 0.830 ; width_u[6] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.124 ;
-; 0.830 ; lines_u[10] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.123 ;
-; 0.831 ; width_u[14] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.125 ;
-; 0.831 ; lines_u[13] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.124 ;
-; 0.832 ; W3_r[3] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.126 ;
-; 0.832 ; lines_u[11] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.125 ;
-; 0.832 ; idx[4] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.125 ;
-; 0.837 ; idx[4] ; tx_byte[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.130 ;
-; 0.841 ; tx_start ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.134 ;
-; 0.871 ; req_sync[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.164 ;
-; 0.901 ; width_u[1] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.195 ;
-; 0.913 ; heartbeat_u ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.206 ;
-; 0.914 ; fstate.F_CONVERT ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.207 ;
-; 0.968 ; fstate.F_LOAD ; tx_start ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.262 ;
-; 0.981 ; width_u[7] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.275 ;
-; 0.982 ; width_u[15] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.276 ;
-; 0.982 ; width_u[10] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.275 ;
-; 1.008 ; W3_r[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.302 ;
-; 1.012 ; idx[3] ; idx[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.305 ;
-; 1.016 ; idx[0] ; idx[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.309 ;
-; 1.040 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.333 ;
-; 1.046 ; fstate.F_LOAD ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.339 ;
-; 1.090 ; lines_u[15] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.383 ;
-; 1.092 ; lines_u[9] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.385 ;
-; 1.093 ; lines_u[7] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.386 ;
-; 1.096 ; idx[1] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.389 ;
-; 1.098 ; lines_u[12] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.391 ;
-; 1.098 ; uart_tx:u_uart|tick[1] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.391 ;
-; 1.099 ; uart_tx:u_uart|tick[3] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.392 ;
-; 1.100 ; lines_u[6] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.393 ;
-; 1.100 ; uart_tx:u_uart|tick[5] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.393 ;
-; 1.101 ; lines_u[8] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.394 ;
-; 1.101 ; uart_tx:u_uart|tick[7] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.394 ;
-; 1.104 ; width_u[8] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.397 ;
-; 1.105 ; width_u[9] ; w_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.399 ;
-; 1.107 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.400 ;
-; 1.107 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.400 ;
-; 1.108 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.401 ;
-; 1.108 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.401 ;
-; 1.116 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.409 ;
-; 1.116 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.409 ;
-; 1.117 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.410 ;
-; 1.117 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.410 ;
-; 1.125 ; fstate.F_IDLE ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.419 ;
-; 1.135 ; W3_r[0] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.429 ;
-; 1.149 ; W3_r[1] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 1.443 ;
-; 1.157 ; idx[1] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.450 ;
-; 1.157 ; req_edge_q ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 1.450 ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Hold: 'rx_clk' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.452 ; de_monitor:u_mon|any_bad_width ; de_monitor:u_mon|any_bad_width ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.746 ;
-; 0.491 ; hb_count[7] ; hb_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.785 ;
-; 0.499 ; de_monitor:u_mon|lines_o[5] ; lines_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.793 ;
-; 0.500 ; de_monitor:u_mon|width_o[7] ; width_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.793 ;
-; 0.501 ; de_monitor:u_mon|width_o[11] ; width_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.794 ;
-; 0.501 ; de_monitor:u_mon|lines_o[14] ; lines_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.794 ;
-; 0.501 ; de_monitor:u_mon|lines_o[6] ; lines_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.795 ;
-; 0.501 ; de_monitor:u_mon|lines_o[13] ; lines_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.794 ;
-; 0.501 ; de_monitor:u_mon|lines_o[12] ; lines_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.794 ;
-; 0.501 ; de_monitor:u_mon|lines_o[1] ; lines_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.795 ;
-; 0.501 ; de_monitor:u_mon|lines_o[11] ; lines_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.794 ;
-; 0.501 ; de_monitor:u_mon|lines_o[3] ; lines_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.795 ;
-; 0.501 ; de_monitor:u_mon|lines_o[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.795 ;
-; 0.501 ; rst_sync_pix[0] ; rst_sync_pix[1] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.794 ;
-; 0.502 ; de_monitor:u_mon|width_o[15] ; width_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|width_o[2] ; width_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|width_o[9] ; width_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|width_o[10] ; width_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|width_o[3] ; width_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|width_o[1] ; width_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|lines_o[9] ; lines_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|lines_o[7] ; lines_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; de_monitor:u_mon|lines_o[8] ; lines_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.502 ; rst_sync_pix[1] ; rst_sync_pix[2] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.795 ;
-; 0.503 ; de_monitor:u_mon|width_o[13] ; width_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.796 ;
-; 0.503 ; de_monitor:u_mon|lines_o[15] ; lines_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.796 ;
-; 0.504 ; de_monitor:u_mon|width_o[0] ; width_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.797 ;
-; 0.504 ; de_monitor:u_mon|lines_o[10] ; lines_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.797 ;
-; 0.698 ; de_monitor:u_mon|lines_o[0] ; lines_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.991 ;
-; 0.698 ; de_monitor:u_mon|width_o[6] ; width_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.991 ;
-; 0.699 ; de_monitor:u_mon|width_o[14] ; width_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.992 ;
-; 0.699 ; de_monitor:u_mon|width_o[4] ; width_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.992 ;
-; 0.699 ; de_monitor:u_mon|lines_o[4] ; lines_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 0.993 ;
-; 0.699 ; de_monitor:u_mon|anomaly_o ; anomaly_lat ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.992 ;
-; 0.700 ; de_monitor:u_mon|width_o[8] ; width_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.993 ;
-; 0.700 ; de_monitor:u_mon|width_o[12] ; width_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.993 ;
-; 0.700 ; de_monitor:u_mon|width_o[5] ; width_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 0.993 ;
-; 0.713 ; de_monitor:u_mon|line_count[4] ; de_monitor:u_mon|lines_o[4] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 1.006 ;
-; 0.740 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.035 ;
-; 0.742 ; de_monitor:u_mon|line_count[5] ; de_monitor:u_mon|lines_o[5] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 1.035 ;
-; 0.742 ; hb_count[1] ; hb_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.036 ;
-; 0.747 ; de_monitor:u_mon|line_count[1] ; de_monitor:u_mon|lines_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 1.040 ;
-; 0.751 ; de_monitor:u_mon|line_count[6] ; de_monitor:u_mon|lines_o[6] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 1.044 ;
-; 0.760 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.054 ;
-; 0.760 ; de_monitor:u_mon|line_count[3] ; de_monitor:u_mon|line_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.054 ;
-; 0.761 ; de_monitor:u_mon|line_width[13] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_width[5] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_count[13] ; de_monitor:u_mon|line_count[13] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_count[11] ; de_monitor:u_mon|line_count[11] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_count[5] ; de_monitor:u_mon|line_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.761 ; de_monitor:u_mon|line_count[1] ; de_monitor:u_mon|line_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.055 ;
-; 0.762 ; de_monitor:u_mon|line_count[15] ; de_monitor:u_mon|line_count[15] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.056 ;
-; 0.762 ; de_monitor:u_mon|line_width[15] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.056 ;
-; 0.763 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_width[6] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_count[9] ; de_monitor:u_mon|line_count[9] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_count[7] ; de_monitor:u_mon|line_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_count[6] ; de_monitor:u_mon|line_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.763 ; de_monitor:u_mon|line_count[2] ; de_monitor:u_mon|line_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.057 ;
-; 0.764 ; de_monitor:u_mon|line_width[14] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.058 ;
-; 0.764 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.058 ;
-; 0.764 ; de_monitor:u_mon|line_count[14] ; de_monitor:u_mon|line_count[14] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.058 ;
-; 0.764 ; de_monitor:u_mon|line_count[4] ; de_monitor:u_mon|line_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.058 ;
-; 0.765 ; de_monitor:u_mon|line_width[12] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.059 ;
-; 0.765 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.059 ;
-; 0.765 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.059 ;
-; 0.765 ; de_monitor:u_mon|line_count[12] ; de_monitor:u_mon|line_count[12] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.059 ;
-; 0.765 ; de_monitor:u_mon|line_count[10] ; de_monitor:u_mon|line_count[10] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.059 ;
-; 0.765 ; de_monitor:u_mon|line_count[8] ; de_monitor:u_mon|line_count[8] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.059 ;
-; 0.766 ; hb_count[6] ; hb_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.060 ;
-; 0.769 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.064 ;
-; 0.769 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.064 ;
-; 0.777 ; hb_count[0] ; hb_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.071 ;
-; 0.785 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.079 ;
-; 0.785 ; de_monitor:u_mon|line_count[0] ; de_monitor:u_mon|line_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.079 ;
-; 0.874 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.168 ;
-; 0.882 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.176 ;
-; 0.885 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|bad_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.180 ;
-; 0.913 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.207 ;
-; 0.921 ; hb_count[5] ; hb_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.215 ;
-; 0.922 ; hb_count[5] ; hb_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.216 ;
-; 0.922 ; hb_count[5] ; hb_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.216 ;
-; 0.922 ; hb_count[5] ; hb_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.216 ;
-; 0.924 ; de_monitor:u_mon|line_count[2] ; de_monitor:u_mon|lines_o[2] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 1.217 ;
-; 0.929 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|bad_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.224 ;
-; 0.932 ; de_monitor:u_mon|line_count[3] ; de_monitor:u_mon|lines_o[3] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 1.225 ;
-; 0.933 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.227 ;
-; 0.941 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.235 ;
-; 0.942 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.237 ;
-; 0.943 ; hb_count[5] ; heartbeat_lat ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.237 ;
-; 0.946 ; de_monitor:u_mon|line_width[5] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.241 ;
-; 0.968 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 1.262 ;
-; 0.984 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|bad_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.279 ;
-; 0.988 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.283 ;
-; 1.025 ; de_monitor:u_mon|last_width[1] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 1.309 ;
-; 1.032 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|bad_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 1.327 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Recovery: 'rx_clk' ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 8.730 ; rst_sync_pix[2] ; lines_lat[6] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; lines_lat[1] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; lines_lat[3] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; lines_lat[4] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; lines_lat[5] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.077 ; 4.694 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[7] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; heartbeat_lat ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[5] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[2] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[3] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[4] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[6] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[1] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; hb_count[0] ; rx_clk ; rx_clk ; 13.500 ; -0.086 ; 4.685 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|de_q ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[1] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[2] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[3] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[5] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[12] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[13] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[15] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[6] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|frame_active ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|frame_done ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.697 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.072 ; 4.699 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 4.688 ;
-; 8.730 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 4.698 ;
-; 8.731 ; rst_sync_pix[2] ; lines_lat[0] ; rx_clk ; rx_clk ; 13.500 ; -0.088 ; 4.682 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[0] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[14] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[15] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[2] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[6] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[7] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[8] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[9] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[11] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[13] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[12] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[10] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[3] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[4] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[1] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-; 8.731 ; rst_sync_pix[2] ; width_lat[5] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 4.688 ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Recovery: 'clk_50mhz' ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 15.869 ; rst_sync_uart[2] ; req_sync[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 4.057 ;
-; 16.314 ; rst_sync_uart[2] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 3.612 ;
-; 16.314 ; rst_sync_uart[2] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.617 ;
-; 16.314 ; rst_sync_uart[2] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 3.612 ;
-; 16.314 ; rst_sync_uart[2] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 3.612 ;
-; 16.314 ; rst_sync_uart[2] ; W0_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.076 ; 3.611 ;
-; 16.314 ; rst_sync_uart[2] ; W0_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.076 ; 3.611 ;
-; 16.314 ; rst_sync_uart[2] ; lines_u[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.617 ;
-; 16.314 ; rst_sync_uart[2] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.617 ;
-; 16.314 ; rst_sync_uart[2] ; width_u[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 3.612 ;
-; 16.314 ; rst_sync_uart[2] ; width_u[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.617 ;
-; 16.314 ; rst_sync_uart[2] ; width_u[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 3.612 ;
-; 16.314 ; rst_sync_uart[2] ; width_u[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 3.620 ;
-; 16.314 ; rst_sync_uart[2] ; L1_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.065 ; 3.622 ;
-; 16.315 ; rst_sync_uart[2] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.602 ;
-; 16.315 ; rst_sync_uart[2] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.602 ;
-; 16.315 ; rst_sync_uart[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.602 ;
-; 16.315 ; rst_sync_uart[2] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.602 ;
-; 16.315 ; rst_sync_uart[2] ; W0_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 3.592 ;
-; 16.315 ; rst_sync_uart[2] ; W0_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.094 ; 3.592 ;
-; 16.315 ; rst_sync_uart[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.607 ;
-; 16.315 ; rst_sync_uart[2] ; W2_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; W2_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; W3_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.602 ;
-; 16.315 ; rst_sync_uart[2] ; req_sync[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 3.594 ;
-; 16.315 ; rst_sync_uart[2] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; heartbeat_u ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; anomaly_u ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 3.594 ;
-; 16.315 ; rst_sync_uart[2] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 3.594 ;
-; 16.315 ; rst_sync_uart[2] ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 3.594 ;
-; 16.315 ; rst_sync_uart[2] ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; msg_len[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; msg_len[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; idx[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; idx[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; idx[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; is_err_msg ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; idx[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; idx[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; fstate.F_LOAD ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.093 ; 3.593 ;
-; 16.315 ; rst_sync_uart[2] ; tx_start ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.092 ; 3.594 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 3.608 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 3.608 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 3.608 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.089 ; 3.597 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.095 ; 3.591 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.095 ; 3.591 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 3.598 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 3.598 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 3.608 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 3.608 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 3.598 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 3.598 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.095 ; 3.591 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.095 ; 3.591 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[9] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.095 ; 3.591 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.095 ; 3.591 ;
-; 16.315 ; rst_sync_uart[2] ; lines_u[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 3.598 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 3.598 ;
-; 16.315 ; rst_sync_uart[2] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 3.608 ;
-; 16.315 ; rst_sync_uart[2] ; width_u[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.618 ;
-; 16.315 ; rst_sync_uart[2] ; width_u[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.618 ;
-; 16.315 ; rst_sync_uart[2] ; width_u[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.607 ;
-; 16.315 ; rst_sync_uart[2] ; tx_byte[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.602 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.086 ; 3.600 ;
-; 16.315 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 3.603 ;
-; 16.315 ; rst_sync_uart[2] ; L1_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.063 ; 3.623 ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Removal: 'clk_50mhz' ;
-+-------+------------------+-----------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+------------------+-----------------------------+--------------+-------------+--------------+------------+------------+
-; 3.067 ; rst_sync_uart[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.376 ;
-; 3.067 ; rst_sync_uart[2] ; width_u[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.376 ;
-; 3.073 ; rst_sync_uart[2] ; width_u[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.109 ; 3.394 ;
-; 3.074 ; rst_sync_uart[2] ; lines_u[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 3.358 ;
-; 3.074 ; rst_sync_uart[2] ; l_rem[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 3.358 ;
-; 3.074 ; rst_sync_uart[2] ; L1_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.113 ; 3.399 ;
-; 3.074 ; rst_sync_uart[2] ; L1_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.113 ; 3.399 ;
-; 3.075 ; rst_sync_uart[2] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.101 ; 3.388 ;
-; 3.075 ; rst_sync_uart[2] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.101 ; 3.388 ;
-; 3.075 ; rst_sync_uart[2] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.101 ; 3.388 ;
-; 3.075 ; rst_sync_uart[2] ; W3_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; width_u[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.101 ; 3.388 ;
-; 3.075 ; rst_sync_uart[2] ; width_u[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.101 ; 3.388 ;
-; 3.075 ; rst_sync_uart[2] ; width_u[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.108 ; 3.395 ;
-; 3.075 ; rst_sync_uart[2] ; width_u[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.108 ; 3.395 ;
-; 3.075 ; rst_sync_uart[2] ; tx_byte[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; W3_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; W3_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.075 ; rst_sync_uart[2] ; L1_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.111 ; 3.398 ;
-; 3.075 ; rst_sync_uart[2] ; W3_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.092 ; 3.379 ;
-; 3.076 ; rst_sync_uart[2] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.106 ; 3.394 ;
-; 3.076 ; rst_sync_uart[2] ; W0_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.100 ; 3.388 ;
-; 3.076 ; rst_sync_uart[2] ; W0_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.100 ; 3.388 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.385 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.385 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.385 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.106 ; 3.394 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.106 ; 3.394 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.375 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.375 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.385 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.385 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.375 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.375 ;
-; 3.076 ; rst_sync_uart[2] ; lines_u[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.375 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.375 ;
-; 3.076 ; rst_sync_uart[2] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.097 ; 3.385 ;
-; 3.076 ; rst_sync_uart[2] ; width_u[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.106 ; 3.394 ;
-; 3.076 ; rst_sync_uart[2] ; L0_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.386 ;
-; 3.076 ; rst_sync_uart[2] ; L0_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.386 ;
-; 3.076 ; rst_sync_uart[2] ; L0_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.386 ;
-; 3.076 ; rst_sync_uart[2] ; L1_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.386 ;
-; 3.077 ; rst_sync_uart[2] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.378 ;
-; 3.077 ; rst_sync_uart[2] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.378 ;
-; 3.077 ; rst_sync_uart[2] ; w_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.379 ;
-; 3.077 ; rst_sync_uart[2] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.378 ;
-; 3.077 ; rst_sync_uart[2] ; w_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.379 ;
-; 3.077 ; rst_sync_uart[2] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.379 ;
-; 3.077 ; rst_sync_uart[2] ; width_u[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.379 ;
-; 3.077 ; rst_sync_uart[2] ; width_u[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.379 ;
-; 3.077 ; rst_sync_uart[2] ; width_u[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.378 ;
-; 3.077 ; rst_sync_uart[2] ; width_u[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.378 ;
-; 3.078 ; rst_sync_uart[2] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.380 ;
-; 3.078 ; rst_sync_uart[2] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.380 ;
-; 3.078 ; rst_sync_uart[2] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.080 ; 3.370 ;
-; 3.078 ; rst_sync_uart[2] ; req_sync[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.083 ; 3.373 ;
-; 3.078 ; rst_sync_uart[2] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; heartbeat_u ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; anomaly_u ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.083 ; 3.373 ;
-; 3.078 ; rst_sync_uart[2] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.083 ; 3.373 ;
-; 3.078 ; rst_sync_uart[2] ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.083 ; 3.373 ;
-; 3.078 ; rst_sync_uart[2] ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; msg_len[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.078 ; rst_sync_uart[2] ; msg_len[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.078 ; rst_sync_uart[2] ; is_err_msg ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.078 ; rst_sync_uart[2] ; fstate.F_LOAD ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.372 ;
-; 3.078 ; rst_sync_uart[2] ; tx_start ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.083 ; 3.373 ;
-; 3.078 ; rst_sync_uart[2] ; width_u[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.380 ;
-; 3.078 ; rst_sync_uart[2] ; width_u[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.090 ; 3.380 ;
-; 3.078 ; rst_sync_uart[2] ; width_u[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.080 ; 3.370 ;
-; 3.078 ; rst_sync_uart[2] ; width_u[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.078 ; rst_sync_uart[2] ; w_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.078 ; rst_sync_uart[2] ; lines_u[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.078 ; rst_sync_uart[2] ; l_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.377 ;
-; 3.079 ; rst_sync_uart[2] ; W0_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 3.372 ;
-; 3.079 ; rst_sync_uart[2] ; W0_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.081 ; 3.372 ;
-; 3.079 ; rst_sync_uart[2] ; W2_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.373 ;
-; 3.079 ; rst_sync_uart[2] ; W2_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.082 ; 3.373 ;
-; 3.079 ; rst_sync_uart[2] ; idx[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.380 ;
-; 3.079 ; rst_sync_uart[2] ; idx[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.380 ;
-; 3.079 ; rst_sync_uart[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.380 ;
-; 3.079 ; rst_sync_uart[2] ; idx[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.380 ;
-; 3.079 ; rst_sync_uart[2] ; idx[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.380 ;
-; 3.079 ; rst_sync_uart[2] ; idx[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.380 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.093 ; 3.384 ;
-; 3.079 ; rst_sync_uart[2] ; lines_u[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.377 ;
-+-------+------------------+-----------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 85C Model Removal: 'rx_clk' ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 4.061 ; rst_sync_pix[2] ; lines_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 4.347 ;
-; 4.061 ; rst_sync_pix[2] ; lines_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; lines_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; lines_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; lines_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; lines_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; anomaly_lat ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 4.338 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[0] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 4.347 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; heartbeat_lat ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; hb_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.077 ; 4.350 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.061 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.353 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; width_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.062 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 0.000 ; 0.080 ; 4.354 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[8] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[9] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[10] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[11] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[14] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.065 ; rst_sync_pix[2] ; de_monitor:u_mon|any_bad_width ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.367 ;
-; 4.066 ; rst_sync_pix[2] ; lines_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.086 ; 4.364 ;
-; 4.066 ; rst_sync_pix[2] ; lines_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.086 ; 4.364 ;
-; 4.066 ; rst_sync_pix[2] ; lines_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.086 ; 4.364 ;
-; 4.066 ; rst_sync_pix[2] ; lines_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.086 ; 4.364 ;
-; 4.066 ; rst_sync_pix[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.086 ; 4.364 ;
-; 4.066 ; rst_sync_pix[2] ; lines_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.086 ; 4.364 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[15] ; rx_clk ; rx_clk ; 0.000 ; 0.087 ; 4.365 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.091 ; 4.369 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.091 ; 4.369 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.091 ; 4.369 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.091 ; 4.369 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.091 ; 4.369 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.090 ; 4.368 ;
-; 4.066 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.091 ; 4.369 ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
------------------------------------------------
-; Slow 1200mV 85C Model Metastability Summary ;
------------------------------------------------
-The design MTBF is not calculated because there are no specified synchronizers in the design.
-Number of Synchronizer Chains Found: 46
-Shortest Synchronizer Chain: 2 Registers
-Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
-Worst Case Available Settling Time: 12.327 ns
-
-
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Fmax Summary ;
-+------------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+------------+-----------------+------------+------+
-; 67.57 MHz ; 67.57 MHz ; clk_50mhz ; ;
-; 168.61 MHz ; 168.61 MHz ; rx_clk ; ;
-+------------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+------------------------------------+
-; Slow 1200mV 0C Model Setup Summary ;
-+-----------+-------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+----------------+
-; clk_50mhz ; 5.201 ; 0.000 ;
-; rx_clk ; 7.569 ; 0.000 ;
-+-----------+-------+----------------+
-
-
-+-----------------------------------+
-; Slow 1200mV 0C Model Hold Summary ;
-+-----------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+---------------+
-; clk_50mhz ; 0.401 ; 0.000 ;
-; rx_clk ; 0.401 ; 0.000 ;
-+-----------+-------+---------------+
-
-
-+---------------------------------------+
-; Slow 1200mV 0C Model Recovery Summary ;
-+-----------+--------+------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+--------+------------------+
-; rx_clk ; 9.063 ; 0.000 ;
-; clk_50mhz ; 16.187 ; 0.000 ;
-+-----------+--------+------------------+
-
-
-+--------------------------------------+
-; Slow 1200mV 0C Model Removal Summary ;
-+-----------+-------+------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+------------------+
-; clk_50mhz ; 2.755 ; 0.000 ;
-; rx_clk ; 3.637 ; 0.000 ;
-+-----------+-------+------------------+
-
-
-+--------------------------------------------------+
-; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
-+-----------+-------+------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+------------------------------+
-; rx_clk ; 6.498 ; 0.000 ;
-; clk_50mhz ; 9.750 ; 0.000 ;
-+-----------+-------+------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'clk_50mhz' ;
-+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-; 5.201 ; l_rem[6] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 14.730 ;
-; 5.547 ; l_rem[7] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 14.388 ;
-; 5.622 ; l_rem[3] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 14.298 ;
-; 5.682 ; w_rem[7] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.072 ; 14.248 ;
-; 5.705 ; w_rem[6] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 14.218 ;
-; 5.833 ; l_rem[6] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 14.098 ;
-; 5.835 ; l_rem[6] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 14.096 ;
-; 5.836 ; l_rem[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.060 ; 14.106 ;
-; 6.121 ; l_rem[6] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.076 ; 13.805 ;
-; 6.132 ; l_rem[6] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.076 ; 13.794 ;
-; 6.146 ; l_rem[6] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 13.785 ;
-; 6.151 ; l_rem[8] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.778 ;
-; 6.179 ; l_rem[7] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 13.756 ;
-; 6.181 ; l_rem[7] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 13.754 ;
-; 6.185 ; w_rem[5] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.735 ;
-; 6.254 ; l_rem[3] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.666 ;
-; 6.256 ; l_rem[3] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.664 ;
-; 6.308 ; w_rem[3] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 13.610 ;
-; 6.344 ; l_rem[5] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.576 ;
-; 6.357 ; l_rem[6] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.572 ;
-; 6.376 ; l_rem[4] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.544 ;
-; 6.385 ; w_rem[11] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 13.546 ;
-; 6.399 ; l_rem[12] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.530 ;
-; 6.412 ; w_rem[3] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.508 ;
-; 6.419 ; w_rem[2] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.059 ; 13.524 ;
-; 6.442 ; w_rem[8] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.063 ; 13.497 ;
-; 6.453 ; l_rem[10] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.476 ;
-; 6.467 ; l_rem[7] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.072 ; 13.463 ;
-; 6.468 ; l_rem[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.060 ; 13.474 ;
-; 6.470 ; l_rem[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.060 ; 13.472 ;
-; 6.478 ; l_rem[7] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.072 ; 13.452 ;
-; 6.492 ; l_rem[7] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 13.443 ;
-; 6.542 ; l_rem[3] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.087 ; 13.373 ;
-; 6.553 ; l_rem[3] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.087 ; 13.362 ;
-; 6.558 ; w_rem[6] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 13.363 ;
-; 6.567 ; l_rem[3] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 13.353 ;
-; 6.584 ; l_rem[11] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.345 ;
-; 6.594 ; l_rem[9] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 13.341 ;
-; 6.688 ; w_rem[13] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.072 ; 13.242 ;
-; 6.706 ; w_rem[4] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 13.212 ;
-; 6.738 ; w_rem[12] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.191 ;
-; 6.745 ; w_rem[10] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.184 ;
-; 6.756 ; l_rem[2] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.065 ; 13.181 ;
-; 6.767 ; l_rem[2] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.065 ; 13.170 ;
-; 6.775 ; l_rem[12] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.154 ;
-; 6.781 ; l_rem[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.060 ; 13.161 ;
-; 6.783 ; l_rem[8] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.146 ;
-; 6.785 ; l_rem[8] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.144 ;
-; 6.808 ; w_rem[5] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 13.110 ;
-; 6.827 ; l_rem[7] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.069 ; 13.106 ;
-; 6.829 ; l_rem[10] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.100 ;
-; 6.835 ; w_rem[9] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.072 ; 13.095 ;
-; 6.843 ; w_rem[7] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.072 ; 13.087 ;
-; 6.843 ; l_rem[1] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.090 ; 13.069 ;
-; 6.866 ; w_rem[6] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 13.057 ;
-; 6.872 ; l_rem[6] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.057 ;
-; 6.876 ; w_rem[7] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.076 ; 13.050 ;
-; 6.883 ; l_rem[14] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 13.048 ;
-; 6.894 ; l_rem[3] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 13.024 ;
-; 6.896 ; l_rem[6] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.076 ; 13.030 ;
-; 6.909 ; w_rem[6] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 13.020 ;
-; 6.953 ; w_rem[4] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 12.967 ;
-; 6.960 ; l_rem[11] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.969 ;
-; 6.974 ; w_rem[3] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.083 ; 12.945 ;
-; 6.983 ; l_rem[5] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 12.937 ;
-; 6.984 ; w_rem[9] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.945 ;
-; 6.986 ; l_rem[5] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 12.934 ;
-; 6.988 ; w_rem[7] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.081 ; 12.933 ;
-; 7.005 ; l_rem[15] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 12.930 ;
-; 7.008 ; l_rem[4] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 12.912 ;
-; 7.010 ; l_rem[4] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 12.910 ;
-; 7.011 ; w_rem[6] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.088 ; 12.903 ;
-; 7.012 ; l_rem[13] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 12.919 ;
-; 7.031 ; l_rem[12] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.898 ;
-; 7.033 ; l_rem[12] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.896 ;
-; 7.058 ; l_rem[12] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 12.869 ;
-; 7.069 ; l_rem[5] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 12.851 ;
-; 7.071 ; l_rem[8] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 12.853 ;
-; 7.082 ; l_rem[8] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.078 ; 12.842 ;
-; 7.083 ; w_rem[3] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 12.835 ;
-; 7.085 ; l_rem[10] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.844 ;
-; 7.086 ; w_rem[3] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.843 ;
-; 7.087 ; l_rem[5] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.842 ;
-; 7.087 ; l_rem[10] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.842 ;
-; 7.096 ; l_rem[8] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.833 ;
-; 7.099 ; w_rem[3] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 12.819 ;
-; 7.112 ; l_rem[10] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.075 ; 12.815 ;
-; 7.134 ; l_rem[6] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 12.806 ;
-; 7.151 ; l_rem[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 12.789 ;
-; 7.158 ; w_rem[14] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 12.773 ;
-; 7.173 ; w_rem[9] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.074 ; 12.755 ;
-; 7.176 ; l_rem[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.753 ;
-; 7.201 ; w_rem[8] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.065 ; 12.736 ;
-; 7.216 ; l_rem[11] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.713 ;
-; 7.218 ; l_rem[7] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.069 ; 12.715 ;
-; 7.218 ; l_rem[11] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.711 ;
-; 7.221 ; w_rem[8] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.064 ; 12.717 ;
-; 7.221 ; w_rem[7] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.073 ; 12.708 ;
-; 7.224 ; w_rem[6] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.080 ; 12.698 ;
-; 7.226 ; l_rem[9] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 12.709 ;
-+-------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Setup: 'rx_clk' ;
-+-------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-; 7.569 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.835 ;
-; 7.569 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.835 ;
-; 7.569 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.835 ;
-; 7.569 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.835 ;
-; 7.569 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.835 ;
-; 7.569 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.835 ;
-; 7.590 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.811 ;
-; 7.590 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.811 ;
-; 7.590 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.811 ;
-; 7.590 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.811 ;
-; 7.741 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.663 ;
-; 7.741 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.663 ;
-; 7.741 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.663 ;
-; 7.741 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.663 ;
-; 7.741 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.663 ;
-; 7.741 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.663 ;
-; 7.746 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.655 ;
-; 7.746 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.655 ;
-; 7.746 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.655 ;
-; 7.746 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.655 ;
-; 7.749 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.655 ;
-; 7.749 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.655 ;
-; 7.749 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.655 ;
-; 7.749 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.655 ;
-; 7.749 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.655 ;
-; 7.749 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.655 ;
-; 7.754 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.647 ;
-; 7.754 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.647 ;
-; 7.754 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.647 ;
-; 7.754 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.647 ;
-; 7.827 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.577 ;
-; 7.827 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.577 ;
-; 7.827 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.577 ;
-; 7.827 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.577 ;
-; 7.827 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.577 ;
-; 7.827 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.577 ;
-; 7.832 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.569 ;
-; 7.832 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.569 ;
-; 7.832 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.569 ;
-; 7.832 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.569 ;
-; 7.887 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.532 ;
-; 7.887 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.532 ;
-; 7.887 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.532 ;
-; 7.887 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.532 ;
-; 7.887 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.532 ;
-; 7.887 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.532 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.946 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.474 ;
-; 7.954 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.089 ; 5.459 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 7.980 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.082 ; 5.440 ;
-; 8.001 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.403 ;
-; 8.001 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.403 ;
-; 8.001 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.403 ;
-; 8.001 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.403 ;
-; 8.001 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.403 ;
-; 8.001 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.098 ; 5.403 ;
-; 8.007 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 5.422 ;
-; 8.007 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 5.422 ;
-; 8.007 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 5.422 ;
-; 8.007 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.073 ; 5.422 ;
-; 8.030 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.371 ;
-; 8.030 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.371 ;
-; 8.030 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.371 ;
-; 8.030 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.101 ; 5.371 ;
-; 8.033 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.385 ;
-; 8.033 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.385 ;
-; 8.033 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.385 ;
-; 8.033 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.385 ;
-; 8.033 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.385 ;
-; 8.033 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.385 ;
-; 8.109 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.310 ;
-; 8.109 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.310 ;
-; 8.109 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.310 ;
-; 8.109 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.310 ;
-; 8.109 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.310 ;
-; 8.109 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.310 ;
-; 8.111 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.308 ;
-; 8.111 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.308 ;
-; 8.111 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.308 ;
-; 8.111 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.308 ;
-; 8.111 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.308 ;
-; 8.111 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.083 ; 5.308 ;
-; 8.117 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.301 ;
-; 8.117 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.301 ;
-; 8.117 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.301 ;
-; 8.117 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.301 ;
-; 8.117 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.084 ; 5.301 ;
-+-------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'clk_50mhz' ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.401 ; w_rem[5] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; w_rem[3] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; w_rem[4] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; l_rem[5] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; l_rem[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; l_rem[4] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; uart_tx:u_uart|busy ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; fstate.F_WAIT ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; conv_step[1] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.401 ; conv_step[0] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.669 ;
-; 0.462 ; uart_tx:u_uart|tick[8] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.730 ;
-; 0.470 ; rst_sync_uart[1] ; rst_sync_uart[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.738 ;
-; 0.470 ; rst_sync_uart[0] ; rst_sync_uart[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.738 ;
-; 0.470 ; uart_tx:u_uart|state.S_D6 ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.738 ;
-; 0.472 ; lines_u[2] ; l_rem[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 0.739 ;
-; 0.473 ; width_u[0] ; w_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.741 ;
-; 0.476 ; uart_tx:u_uart|state.S_D1 ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.744 ;
-; 0.478 ; uart_tx:u_uart|state.S_D3 ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.746 ;
-; 0.478 ; uart_tx:u_uart|state.S_D2 ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.746 ;
-; 0.491 ; uart_tx:u_uart|state.S_D5 ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.759 ;
-; 0.501 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.769 ;
-; 0.521 ; conv_step[0] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.789 ;
-; 0.550 ; fstate.F_CONVERT ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.818 ;
-; 0.619 ; uart_tx:u_uart|state.S_D0 ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.887 ;
-; 0.620 ; uart_tx:u_uart|state.S_START ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.888 ;
-; 0.645 ; lines_u[1] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.913 ;
-; 0.645 ; fstate.F_LOAD ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.076 ; 0.916 ;
-; 0.646 ; lines_u[0] ; l_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.914 ;
-; 0.646 ; lines_u[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.914 ;
-; 0.647 ; width_u[4] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.915 ;
-; 0.647 ; lines_u[4] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.915 ;
-; 0.648 ; width_u[5] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.916 ;
-; 0.654 ; uart_tx:u_uart|state.S_D4 ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.922 ;
-; 0.654 ; req_sync[1] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.922 ;
-; 0.665 ; uart_tx:u_uart|state.S_D7 ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.933 ;
-; 0.678 ; uart_tx:u_uart|state.S_STOP ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.946 ;
-; 0.681 ; uart_tx:u_uart|state.S_STOP ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.949 ;
-; 0.691 ; uart_tx:u_uart|tick[5] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.959 ;
-; 0.692 ; uart_tx:u_uart|tick[3] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.960 ;
-; 0.693 ; uart_tx:u_uart|tick[1] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.961 ;
-; 0.695 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.963 ;
-; 0.696 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.964 ;
-; 0.696 ; uart_tx:u_uart|tick[7] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.964 ;
-; 0.697 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.965 ;
-; 0.718 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.986 ;
-; 0.719 ; idx[5] ; idx[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 0.987 ;
-; 0.740 ; width_u[12] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.008 ;
-; 0.740 ; lines_u[10] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.008 ;
-; 0.740 ; idx[1] ; idx[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.008 ;
-; 0.741 ; width_u[6] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.009 ;
-; 0.741 ; lines_u[13] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.009 ;
-; 0.742 ; width_u[14] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.010 ;
-; 0.742 ; lines_u[11] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.010 ;
-; 0.743 ; W3_r[3] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.011 ;
-; 0.762 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|tx ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.030 ;
-; 0.762 ; idx[4] ; idx[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.030 ;
-; 0.768 ; idx[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.036 ;
-; 0.777 ; req_sync[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.045 ;
-; 0.785 ; idx[4] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.053 ;
-; 0.786 ; tx_start ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.054 ;
-; 0.792 ; idx[4] ; tx_byte[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.060 ;
-; 0.834 ; width_u[1] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.102 ;
-; 0.841 ; heartbeat_u ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.109 ;
-; 0.864 ; fstate.F_CONVERT ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.132 ;
-; 0.882 ; fstate.F_LOAD ; tx_start ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.076 ; 1.153 ;
-; 0.886 ; width_u[7] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.154 ;
-; 0.887 ; width_u[10] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.155 ;
-; 0.888 ; width_u[15] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.156 ;
-; 0.906 ; W3_r[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.174 ;
-; 0.933 ; idx[3] ; idx[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.201 ;
-; 0.951 ; idx[0] ; idx[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.219 ;
-; 0.958 ; fstate.F_LOAD ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.226 ;
-; 0.965 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.233 ;
-; 0.974 ; lines_u[15] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 1.241 ;
-; 0.975 ; lines_u[9] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 1.242 ;
-; 0.977 ; lines_u[7] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 1.244 ;
-; 0.979 ; lines_u[12] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.247 ;
-; 0.980 ; lines_u[6] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.248 ;
-; 0.981 ; lines_u[8] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.249 ;
-; 0.998 ; width_u[9] ; w_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.266 ;
-; 1.004 ; width_u[8] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.072 ; 1.271 ;
-; 1.012 ; fstate.F_IDLE ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.076 ; 1.283 ;
-; 1.013 ; uart_tx:u_uart|tick[5] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.281 ;
-; 1.013 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.281 ;
-; 1.014 ; uart_tx:u_uart|tick[3] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.282 ;
-; 1.014 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.282 ;
-; 1.015 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.283 ;
-; 1.016 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.284 ;
-; 1.017 ; uart_tx:u_uart|tick[1] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.285 ;
-; 1.019 ; W3_r[0] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.287 ;
-; 1.020 ; uart_tx:u_uart|tick[7] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.288 ;
-; 1.022 ; idx[1] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.290 ;
-; 1.028 ; W3_r[1] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.296 ;
-; 1.028 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.296 ;
-; 1.029 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.297 ;
-; 1.030 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.298 ;
-; 1.031 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.299 ;
-; 1.058 ; l_rem[0] ; L3_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.069 ; 1.322 ;
-; 1.062 ; idx[1] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 1.330 ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Hold: 'rx_clk' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.401 ; de_monitor:u_mon|any_bad_width ; de_monitor:u_mon|any_bad_width ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.669 ;
-; 0.456 ; hb_count[7] ; hb_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.724 ;
-; 0.468 ; de_monitor:u_mon|width_o[7] ; width_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.737 ;
-; 0.469 ; de_monitor:u_mon|width_o[11] ; width_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.738 ;
-; 0.469 ; de_monitor:u_mon|width_o[10] ; width_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.738 ;
-; 0.469 ; de_monitor:u_mon|lines_o[5] ; lines_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.737 ;
-; 0.470 ; de_monitor:u_mon|width_o[13] ; width_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.739 ;
-; 0.470 ; de_monitor:u_mon|lines_o[1] ; lines_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.738 ;
-; 0.470 ; de_monitor:u_mon|lines_o[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.738 ;
-; 0.470 ; rst_sync_pix[1] ; rst_sync_pix[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.738 ;
-; 0.470 ; rst_sync_pix[0] ; rst_sync_pix[1] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.738 ;
-; 0.471 ; de_monitor:u_mon|width_o[15] ; width_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|width_o[2] ; width_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|width_o[9] ; width_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|width_o[3] ; width_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|width_o[1] ; width_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|lines_o[14] ; lines_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.738 ;
-; 0.471 ; de_monitor:u_mon|lines_o[9] ; lines_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|lines_o[15] ; lines_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|lines_o[6] ; lines_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|lines_o[13] ; lines_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.738 ;
-; 0.471 ; de_monitor:u_mon|lines_o[7] ; lines_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|lines_o[8] ; lines_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.471 ; de_monitor:u_mon|lines_o[12] ; lines_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.738 ;
-; 0.471 ; de_monitor:u_mon|lines_o[11] ; lines_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.738 ;
-; 0.471 ; de_monitor:u_mon|lines_o[3] ; lines_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.739 ;
-; 0.472 ; de_monitor:u_mon|width_o[0] ; width_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.740 ;
-; 0.473 ; de_monitor:u_mon|lines_o[10] ; lines_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.741 ;
-; 0.633 ; de_monitor:u_mon|line_count[4] ; de_monitor:u_mon|lines_o[4] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.900 ;
-; 0.644 ; de_monitor:u_mon|lines_o[0] ; lines_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.912 ;
-; 0.644 ; de_monitor:u_mon|width_o[6] ; width_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.913 ;
-; 0.645 ; de_monitor:u_mon|width_o[12] ; width_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.914 ;
-; 0.645 ; de_monitor:u_mon|width_o[4] ; width_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.914 ;
-; 0.645 ; de_monitor:u_mon|width_o[5] ; width_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.074 ; 0.914 ;
-; 0.645 ; de_monitor:u_mon|anomaly_o ; anomaly_lat ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.913 ;
-; 0.646 ; de_monitor:u_mon|width_o[14] ; width_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.914 ;
-; 0.646 ; de_monitor:u_mon|width_o[8] ; width_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.914 ;
-; 0.646 ; de_monitor:u_mon|lines_o[4] ; lines_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.914 ;
-; 0.656 ; de_monitor:u_mon|line_count[5] ; de_monitor:u_mon|lines_o[5] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.923 ;
-; 0.661 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.929 ;
-; 0.661 ; de_monitor:u_mon|line_count[1] ; de_monitor:u_mon|lines_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.928 ;
-; 0.665 ; de_monitor:u_mon|line_count[6] ; de_monitor:u_mon|lines_o[6] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 0.932 ;
-; 0.686 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.954 ;
-; 0.687 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.955 ;
-; 0.690 ; hb_count[1] ; hb_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.958 ;
-; 0.705 ; de_monitor:u_mon|line_width[13] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.973 ;
-; 0.705 ; de_monitor:u_mon|line_width[5] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.973 ;
-; 0.705 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.973 ;
-; 0.705 ; de_monitor:u_mon|line_count[13] ; de_monitor:u_mon|line_count[13] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.973 ;
-; 0.705 ; de_monitor:u_mon|line_count[5] ; de_monitor:u_mon|line_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.973 ;
-; 0.705 ; de_monitor:u_mon|line_count[3] ; de_monitor:u_mon|line_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.973 ;
-; 0.706 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.974 ;
-; 0.706 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.974 ;
-; 0.706 ; de_monitor:u_mon|line_count[11] ; de_monitor:u_mon|line_count[11] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.974 ;
-; 0.706 ; de_monitor:u_mon|line_count[1] ; de_monitor:u_mon|line_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.974 ;
-; 0.707 ; de_monitor:u_mon|line_count[15] ; de_monitor:u_mon|line_count[15] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.975 ;
-; 0.707 ; de_monitor:u_mon|line_width[15] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.975 ;
-; 0.707 ; de_monitor:u_mon|line_width[6] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.975 ;
-; 0.707 ; de_monitor:u_mon|line_count[6] ; de_monitor:u_mon|line_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.975 ;
-; 0.708 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.976 ;
-; 0.708 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.976 ;
-; 0.708 ; de_monitor:u_mon|line_count[9] ; de_monitor:u_mon|line_count[9] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.976 ;
-; 0.708 ; de_monitor:u_mon|line_count[7] ; de_monitor:u_mon|line_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.976 ;
-; 0.710 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.978 ;
-; 0.710 ; de_monitor:u_mon|line_count[2] ; de_monitor:u_mon|line_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.978 ;
-; 0.711 ; de_monitor:u_mon|line_width[14] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_width[12] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_count[14] ; de_monitor:u_mon|line_count[14] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_count[12] ; de_monitor:u_mon|line_count[12] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_count[10] ; de_monitor:u_mon|line_count[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.711 ; de_monitor:u_mon|line_count[4] ; de_monitor:u_mon|line_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.979 ;
-; 0.712 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.980 ;
-; 0.712 ; de_monitor:u_mon|line_count[8] ; de_monitor:u_mon|line_count[8] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.980 ;
-; 0.712 ; hb_count[6] ; hb_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.980 ;
-; 0.728 ; hb_count[0] ; hb_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 0.996 ;
-; 0.733 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.001 ;
-; 0.733 ; de_monitor:u_mon|line_count[0] ; de_monitor:u_mon|line_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.001 ;
-; 0.809 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.077 ;
-; 0.809 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.077 ;
-; 0.825 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|bad_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.093 ;
-; 0.833 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.101 ;
-; 0.849 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|bad_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.117 ;
-; 0.861 ; de_monitor:u_mon|line_count[3] ; de_monitor:u_mon|lines_o[3] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 1.128 ;
-; 0.862 ; de_monitor:u_mon|line_count[2] ; de_monitor:u_mon|lines_o[2] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 1.129 ;
-; 0.862 ; hb_count[5] ; hb_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.130 ;
-; 0.862 ; hb_count[5] ; hb_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.130 ;
-; 0.862 ; hb_count[5] ; hb_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.130 ;
-; 0.863 ; hb_count[5] ; hb_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.131 ;
-; 0.871 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.139 ;
-; 0.872 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.140 ;
-; 0.875 ; hb_count[5] ; heartbeat_lat ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.143 ;
-; 0.884 ; de_monitor:u_mon|line_width[5] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.152 ;
-; 0.886 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.154 ;
-; 0.891 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.159 ;
-; 0.892 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|bad_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.160 ;
-; 0.912 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.180 ;
-; 0.916 ; de_monitor:u_mon|last_width[1] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.064 ; 1.175 ;
-; 0.920 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|bad_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 1.188 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Recovery: 'rx_clk' ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 9.063 ; rst_sync_pix[2] ; width_lat[0] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[14] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[15] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[2] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[6] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[7] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[8] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[9] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[11] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[13] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[12] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[10] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[3] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[4] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[1] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; width_lat[5] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.074 ; 4.365 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[9] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[15] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[6] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[7] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[8] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[10] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[1] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[3] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[4] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; lines_lat[5] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; anomaly_lat ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.075 ; 4.364 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.075 ; 4.364 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.075 ; 4.364 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.075 ; 4.364 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.075 ; 4.364 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.064 ; 4.375 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.090 ; 4.349 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.071 ; 4.368 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|de_q ; rx_clk ; rx_clk ; 13.500 ; -0.066 ; 4.373 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[0] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[1] ; rx_clk ; rx_clk ; 13.500 ; -0.066 ; 4.373 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[2] ; rx_clk ; rx_clk ; 13.500 ; -0.066 ; 4.373 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[3] ; rx_clk ; rx_clk ; 13.500 ; -0.066 ; 4.373 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[4] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[5] ; rx_clk ; rx_clk ; 13.500 ; -0.066 ; 4.373 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[7] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[8] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[9] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[10] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[11] ; rx_clk ; rx_clk ; 13.500 ; -0.065 ; 4.374 ;
-; 9.063 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[12] ; rx_clk ; rx_clk ; 13.500 ; -0.066 ; 4.373 ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Recovery: 'clk_50mhz' ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 16.187 ; rst_sync_uart[2] ; req_sync[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.069 ; 3.746 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.332 ;
-; 16.602 ; rst_sync_uart[2] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 3.338 ;
-; 16.602 ; rst_sync_uart[2] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.332 ;
-; 16.602 ; rst_sync_uart[2] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.332 ;
-; 16.602 ; rst_sync_uart[2] ; W3_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; msg_len[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; msg_len[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; idx[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; idx[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; idx[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; is_err_msg ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; idx[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; idx[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; lines_u[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 3.338 ;
-; 16.602 ; rst_sync_uart[2] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 3.338 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.332 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 3.338 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.068 ; 3.332 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.062 ; 3.338 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.059 ; 3.341 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.059 ; 3.341 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; L1_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.055 ; 3.345 ;
-; 16.602 ; rst_sync_uart[2] ; W3_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; L1_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.055 ; 3.345 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; width_u[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; w_rem[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; W3_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; lines_u[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; l_rem[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.321 ;
-; 16.602 ; rst_sync_uart[2] ; L1_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.059 ; 3.341 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; W3_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.602 ; rst_sync_uart[2] ; tx_byte[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.077 ; 3.323 ;
-; 16.602 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.329 ;
-; 16.603 ; rst_sync_uart[2] ; W0_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; W0_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; W0_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 3.332 ;
-; 16.603 ; rst_sync_uart[2] ; W0_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.067 ; 3.332 ;
-; 16.603 ; rst_sync_uart[2] ; W2_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; W2_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; req_sync[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; heartbeat_u ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; anomaly_u ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; fstate.F_LOAD ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.085 ; 3.314 ;
-; 16.603 ; rst_sync_uart[2] ; tx_start ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.082 ; 3.317 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.071 ; 3.328 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.329 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.091 ; 3.308 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.329 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.070 ; 3.329 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.079 ; 3.320 ;
-; 16.603 ; rst_sync_uart[2] ; lines_u[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.084 ; 3.315 ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Removal: 'clk_50mhz' ;
-+-------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 2.755 ; rst_sync_uart[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.035 ;
-; 2.755 ; rst_sync_uart[2] ; width_u[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.035 ;
-; 2.756 ; rst_sync_uart[2] ; L1_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.102 ; 3.053 ;
-; 2.756 ; rst_sync_uart[2] ; L1_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.102 ; 3.053 ;
-; 2.757 ; rst_sync_uart[2] ; W0_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.041 ;
-; 2.757 ; rst_sync_uart[2] ; W0_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.089 ; 3.041 ;
-; 2.757 ; rst_sync_uart[2] ; width_u[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.050 ;
-; 2.757 ; rst_sync_uart[2] ; width_u[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.050 ;
-; 2.758 ; rst_sync_uart[2] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.088 ; 3.041 ;
-; 2.758 ; rst_sync_uart[2] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.088 ; 3.041 ;
-; 2.758 ; rst_sync_uart[2] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.088 ; 3.041 ;
-; 2.758 ; rst_sync_uart[2] ; lines_u[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.039 ;
-; 2.758 ; rst_sync_uart[2] ; lines_u[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.039 ;
-; 2.758 ; rst_sync_uart[2] ; lines_u[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.039 ;
-; 2.758 ; rst_sync_uart[2] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.039 ;
-; 2.758 ; rst_sync_uart[2] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.039 ;
-; 2.758 ; rst_sync_uart[2] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.086 ; 3.039 ;
-; 2.758 ; rst_sync_uart[2] ; width_u[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.088 ; 3.041 ;
-; 2.758 ; rst_sync_uart[2] ; width_u[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.088 ; 3.041 ;
-; 2.758 ; rst_sync_uart[2] ; L0_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.040 ;
-; 2.758 ; rst_sync_uart[2] ; L1_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.098 ; 3.051 ;
-; 2.758 ; rst_sync_uart[2] ; L0_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.040 ;
-; 2.758 ; rst_sync_uart[2] ; L0_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.040 ;
-; 2.758 ; rst_sync_uart[2] ; L1_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.087 ; 3.040 ;
-; 2.759 ; rst_sync_uart[2] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.094 ; 3.048 ;
-; 2.759 ; rst_sync_uart[2] ; W3_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.074 ; 3.028 ;
-; 2.759 ; rst_sync_uart[2] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.074 ; 3.028 ;
-; 2.759 ; rst_sync_uart[2] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.074 ; 3.028 ;
-; 2.759 ; rst_sync_uart[2] ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.074 ; 3.028 ;
-; 2.759 ; rst_sync_uart[2] ; tx_start ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.074 ; 3.028 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; lines_u[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.064 ; 3.018 ;
-; 2.759 ; rst_sync_uart[2] ; lines_u[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; lines_u[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.094 ; 3.048 ;
-; 2.759 ; rst_sync_uart[2] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.094 ; 3.048 ;
-; 2.759 ; rst_sync_uart[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; lines_u[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; lines_u[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; lines_u[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.031 ;
-; 2.759 ; rst_sync_uart[2] ; l_rem[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.064 ; 3.018 ;
-; 2.759 ; rst_sync_uart[2] ; width_u[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.094 ; 3.048 ;
-; 2.759 ; rst_sync_uart[2] ; width_u[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.095 ; 3.049 ;
-; 2.759 ; rst_sync_uart[2] ; tx_byte[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; W3_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; W3_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; W3_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.079 ; 3.033 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.759 ; rst_sync_uart[2] ; uart_tx:u_uart|tx ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.085 ; 3.039 ;
-; 2.760 ; rst_sync_uart[2] ; W2_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 3.028 ;
-; 2.760 ; rst_sync_uart[2] ; W2_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 3.028 ;
-; 2.760 ; rst_sync_uart[2] ; msg_len[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.032 ;
-; 2.760 ; rst_sync_uart[2] ; msg_len[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.032 ;
-; 2.760 ; rst_sync_uart[2] ; is_err_msg ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.077 ; 3.032 ;
-; 2.760 ; rst_sync_uart[2] ; lines_u[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.071 ; 3.026 ;
-; 2.760 ; rst_sync_uart[2] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.071 ; 3.026 ;
-; 2.760 ; rst_sync_uart[2] ; lines_u[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.075 ; 3.030 ;
-; 2.760 ; rst_sync_uart[2] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.075 ; 3.030 ;
-; 2.760 ; rst_sync_uart[2] ; lines_u[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.075 ; 3.030 ;
-; 2.760 ; rst_sync_uart[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.075 ; 3.030 ;
-; 2.760 ; rst_sync_uart[2] ; lines_u[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.071 ; 3.026 ;
-; 2.760 ; rst_sync_uart[2] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.071 ; 3.026 ;
-; 2.760 ; rst_sync_uart[2] ; lines_u[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.071 ; 3.026 ;
-; 2.760 ; rst_sync_uart[2] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.071 ; 3.026 ;
-; 2.760 ; rst_sync_uart[2] ; lines_u[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.075 ; 3.030 ;
-; 2.760 ; rst_sync_uart[2] ; l_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.075 ; 3.030 ;
-; 2.760 ; rst_sync_uart[2] ; L3_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.073 ; 3.028 ;
-+-------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Slow 1200mV 0C Model Removal: 'rx_clk' ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 3.637 ; rst_sync_pix[2] ; width_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; width_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 0.000 ; 0.073 ; 3.905 ;
-; 3.637 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; width_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.072 ; 3.905 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.638 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.071 ; 3.904 ;
-; 3.639 ; rst_sync_pix[2] ; lines_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 3.899 ;
-; 3.639 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[0] ; rx_clk ; rx_clk ; 0.000 ; 0.065 ; 3.899 ;
-; 3.640 ; rst_sync_pix[2] ; lines_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; lines_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; lines_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; lines_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; lines_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; anomaly_lat ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 0.000 ; 0.056 ; 3.891 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; heartbeat_lat ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; hb_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.066 ; 3.901 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.083 ; 3.918 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.640 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.917 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.082 ; 3.918 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|de_q ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 3.917 ;
-; 3.641 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.081 ; 3.917 ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Slow 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-The design MTBF is not calculated because there are no specified synchronizers in the design.
-Number of Synchronizer Chains Found: 46
-Shortest Synchronizer Chain: 2 Registers
-Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
-Worst Case Available Settling Time: 12.424 ns
-
-
-
-
-+------------------------------------+
-; Fast 1200mV 0C Model Setup Summary ;
-+-----------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+--------+---------------+
-; rx_clk ; 10.706 ; 0.000 ;
-; clk_50mhz ; 13.064 ; 0.000 ;
-+-----------+--------+---------------+
-
-
-+-----------------------------------+
-; Fast 1200mV 0C Model Hold Summary ;
-+-----------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+---------------+
-; clk_50mhz ; 0.186 ; 0.000 ;
-; rx_clk ; 0.186 ; 0.000 ;
-+-----------+-------+---------------+
-
-
-+---------------------------------------+
-; Fast 1200mV 0C Model Recovery Summary ;
-+-----------+--------+------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+--------+------------------+
-; rx_clk ; 11.259 ; 0.000 ;
-; clk_50mhz ; 18.082 ; 0.000 ;
-+-----------+--------+------------------+
-
-
-+--------------------------------------+
-; Fast 1200mV 0C Model Removal Summary ;
-+-----------+-------+------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+------------------+
-; clk_50mhz ; 1.361 ; 0.000 ;
-; rx_clk ; 1.805 ; 0.000 ;
-+-----------+-------+------------------+
-
-
-+--------------------------------------------------+
-; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
-+-----------+-------+------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+-----------+-------+------------------------------+
-; rx_clk ; 6.002 ; 0.000 ;
-; clk_50mhz ; 9.262 ; 0.000 ;
-+-----------+-------+------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'rx_clk' ;
-+--------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-; 10.706 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.727 ;
-; 10.706 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.727 ;
-; 10.706 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.727 ;
-; 10.706 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.727 ;
-; 10.706 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.727 ;
-; 10.706 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.727 ;
-; 10.712 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.053 ; 2.722 ;
-; 10.712 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.053 ; 2.722 ;
-; 10.712 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.053 ; 2.722 ;
-; 10.712 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.053 ; 2.722 ;
-; 10.791 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.641 ;
-; 10.791 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.641 ;
-; 10.791 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.641 ;
-; 10.791 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.641 ;
-; 10.791 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.641 ;
-; 10.791 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.641 ;
-; 10.795 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.637 ;
-; 10.795 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.637 ;
-; 10.795 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.637 ;
-; 10.795 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.637 ;
-; 10.795 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.637 ;
-; 10.795 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.637 ;
-; 10.797 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.636 ;
-; 10.797 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.636 ;
-; 10.797 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.636 ;
-; 10.797 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.636 ;
-; 10.801 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.632 ;
-; 10.801 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.632 ;
-; 10.801 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.632 ;
-; 10.801 ; de_monitor:u_mon|gap_count[10] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.632 ;
-; 10.839 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.593 ;
-; 10.839 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.593 ;
-; 10.839 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.593 ;
-; 10.839 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.593 ;
-; 10.839 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.593 ;
-; 10.839 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.593 ;
-; 10.845 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.588 ;
-; 10.845 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.588 ;
-; 10.845 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.588 ;
-; 10.845 ; de_monitor:u_mon|gap_count[8] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.588 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.906 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.542 ;
-; 10.910 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.537 ;
-; 10.910 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.537 ;
-; 10.910 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.537 ;
-; 10.910 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.537 ;
-; 10.910 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.537 ;
-; 10.910 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.537 ;
-; 10.911 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|lines_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.045 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.917 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.039 ; 2.531 ;
-; 10.932 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.500 ;
-; 10.932 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.500 ;
-; 10.932 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.500 ;
-; 10.932 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.500 ;
-; 10.932 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.500 ;
-; 10.932 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.055 ; 2.500 ;
-; 10.942 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.491 ;
-; 10.942 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.491 ;
-; 10.942 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.491 ;
-; 10.942 ; de_monitor:u_mon|gap_count[11] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.491 ;
-; 10.966 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.036 ; 2.485 ;
-; 10.966 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.036 ; 2.485 ;
-; 10.966 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.036 ; 2.485 ;
-; 10.966 ; de_monitor:u_mon|gap_count[15] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.036 ; 2.485 ;
-; 10.986 ; de_monitor:u_mon|gap_count[1] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[12] ; de_monitor:u_mon|lines_o[15] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[1] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[12] ; de_monitor:u_mon|anomaly_o ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[1] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[12] ; de_monitor:u_mon|lines_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[1] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[12] ; de_monitor:u_mon|lines_o[9] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[1] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[12] ; de_monitor:u_mon|lines_o[8] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[1] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.986 ; de_monitor:u_mon|gap_count[12] ; de_monitor:u_mon|lines_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.054 ; 2.447 ;
-; 10.989 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.041 ; 2.457 ;
-; 10.989 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.041 ; 2.457 ;
-; 10.989 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.041 ; 2.457 ;
-; 10.989 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.041 ; 2.457 ;
-; 10.989 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.041 ; 2.457 ;
-; 10.989 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|bad_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.041 ; 2.457 ;
-; 10.991 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.456 ;
-; 10.991 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.456 ;
-; 10.991 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.456 ;
-; 10.991 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.456 ;
-; 10.991 ; de_monitor:u_mon|gap_count[9] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.040 ; 2.456 ;
-+--------+--------------------------------+--------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Setup: 'clk_50mhz' ;
-+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-; 13.064 ; l_rem[6] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 6.888 ;
-; 13.260 ; l_rem[7] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 6.697 ;
-; 13.281 ; w_rem[7] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.670 ;
-; 13.288 ; w_rem[6] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.660 ;
-; 13.317 ; l_rem[3] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.631 ;
-; 13.374 ; l_rem[6] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 6.578 ;
-; 13.381 ; l_rem[6] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 6.571 ;
-; 13.412 ; l_rem[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.028 ; 6.547 ;
-; 13.454 ; l_rem[6] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 6.492 ;
-; 13.508 ; l_rem[8] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.443 ;
-; 13.531 ; w_rem[5] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 6.418 ;
-; 13.536 ; l_rem[6] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 6.410 ;
-; 13.564 ; w_rem[3] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 6.385 ;
-; 13.570 ; l_rem[7] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 6.387 ;
-; 13.577 ; l_rem[7] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 6.380 ;
-; 13.611 ; l_rem[6] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 6.341 ;
-; 13.614 ; w_rem[2] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.026 ; 6.347 ;
-; 13.625 ; l_rem[5] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.323 ;
-; 13.627 ; l_rem[3] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.321 ;
-; 13.634 ; l_rem[3] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.314 ;
-; 13.650 ; l_rem[7] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.301 ;
-; 13.653 ; l_rem[12] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.298 ;
-; 13.655 ; l_rem[4] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.293 ;
-; 13.665 ; w_rem[3] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 6.282 ;
-; 13.670 ; w_rem[8] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.026 ; 6.291 ;
-; 13.672 ; l_rem[10] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.279 ;
-; 13.682 ; w_rem[7] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 6.263 ;
-; 13.697 ; w_rem[6] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.253 ;
-; 13.707 ; l_rem[3] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 6.235 ;
-; 13.722 ; l_rem[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.028 ; 6.237 ;
-; 13.724 ; l_rem[9] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 6.233 ;
-; 13.729 ; l_rem[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.028 ; 6.230 ;
-; 13.732 ; l_rem[7] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.219 ;
-; 13.733 ; l_rem[1] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.048 ; 6.206 ;
-; 13.734 ; l_rem[6] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.216 ;
-; 13.744 ; l_rem[11] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.207 ;
-; 13.750 ; w_rem[11] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 6.202 ;
-; 13.780 ; l_rem[6] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 6.166 ;
-; 13.789 ; l_rem[3] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 6.153 ;
-; 13.794 ; w_rem[7] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.157 ;
-; 13.801 ; w_rem[6] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.147 ;
-; 13.802 ; l_rem[2] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.034 ; 6.151 ;
-; 13.802 ; w_rem[6] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 6.144 ;
-; 13.807 ; l_rem[7] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 6.150 ;
-; 13.808 ; w_rem[7] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.046 ; 6.133 ;
-; 13.815 ; w_rem[6] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.049 ; 6.123 ;
-; 13.817 ; w_rem[4] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 6.132 ;
-; 13.818 ; l_rem[8] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.133 ;
-; 13.820 ; l_rem[14] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 6.132 ;
-; 13.824 ; w_rem[9] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.127 ;
-; 13.824 ; l_rem[3] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.124 ;
-; 13.825 ; l_rem[8] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.126 ;
-; 13.874 ; l_rem[5] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.074 ;
-; 13.877 ; l_rem[6] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.073 ;
-; 13.878 ; w_rem[4] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 6.069 ;
-; 13.884 ; l_rem[2] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.034 ; 6.069 ;
-; 13.898 ; l_rem[8] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 6.047 ;
-; 13.900 ; l_rem[5] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.048 ;
-; 13.907 ; w_rem[13] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.044 ;
-; 13.908 ; l_rem[15] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 6.049 ;
-; 13.922 ; l_rem[12] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.029 ;
-; 13.929 ; w_rem[9] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 6.015 ;
-; 13.930 ; l_rem[7] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.032 ; 6.025 ;
-; 13.931 ; w_rem[12] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.019 ;
-; 13.931 ; w_rem[10] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.019 ;
-; 13.933 ; l_rem[5] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.017 ;
-; 13.935 ; w_rem[3] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 6.015 ;
-; 13.935 ; l_rem[5] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 6.013 ;
-; 13.940 ; w_rem[5] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.011 ;
-; 13.941 ; l_rem[10] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 6.010 ;
-; 13.943 ; w_rem[5] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 6.004 ;
-; 13.953 ; l_rem[13] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 5.999 ;
-; 13.954 ; w_rem[14] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.035 ; 5.998 ;
-; 13.959 ; l_rem[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.028 ; 6.000 ;
-; 13.960 ; l_rem[12] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 5.991 ;
-; 13.962 ; w_rem[3] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 5.985 ;
-; 13.962 ; l_rem[4] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 5.986 ;
-; 13.969 ; w_rem[3] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 5.980 ;
-; 13.969 ; l_rem[12] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 5.982 ;
-; 13.970 ; l_rem[6] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.033 ; 5.984 ;
-; 13.971 ; l_rem[4] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 5.977 ;
-; 13.972 ; w_rem[7] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 5.977 ;
-; 13.974 ; w_rem[3] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 5.977 ;
-; 13.979 ; l_rem[10] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 5.972 ;
-; 13.980 ; l_rem[8] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 5.965 ;
-; 13.987 ; l_rem[3] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 5.959 ;
-; 13.988 ; l_rem[10] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 5.963 ;
-; 13.990 ; l_rem[5] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 5.960 ;
-; 13.996 ; l_rem[4] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.039 ; 5.952 ;
-; 13.997 ; w_rem[3] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 5.950 ;
-; 13.998 ; l_rem[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.037 ; 5.952 ;
-; 14.009 ; w_rem[9] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 5.940 ;
-; 14.009 ; l_rem[8] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.034 ; 5.944 ;
-; 14.013 ; l_rem[11] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 5.938 ;
-; 14.013 ; l_rem[6] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.033 ; 5.941 ;
-; 14.015 ; w_rem[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.032 ; 5.940 ;
-; 14.015 ; l_rem[5] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 5.927 ;
-; 14.027 ; w_rem[8] ; w_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.028 ; 5.932 ;
-; 14.031 ; l_rem[9] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.030 ; 5.926 ;
-; 14.032 ; l_rem[12] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 5.917 ;
-+--------+-----------+-----------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'clk_50mhz' ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.186 ; w_rem[5] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; w_rem[3] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; w_rem[4] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; l_rem[5] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; l_rem[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; l_rem[4] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; uart_tx:u_uart|busy ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.186 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.307 ;
-; 0.187 ; fstate.F_WAIT ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.307 ;
-; 0.187 ; conv_step[1] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.307 ;
-; 0.187 ; conv_step[0] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.307 ;
-; 0.193 ; uart_tx:u_uart|state.S_D6 ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.314 ;
-; 0.193 ; rst_sync_uart[1] ; rst_sync_uart[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.314 ;
-; 0.193 ; rst_sync_uart[0] ; rst_sync_uart[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.314 ;
-; 0.195 ; lines_u[2] ; l_rem[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.315 ;
-; 0.196 ; width_u[0] ; w_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.317 ;
-; 0.197 ; uart_tx:u_uart|state.S_D2 ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.318 ;
-; 0.197 ; uart_tx:u_uart|state.S_D1 ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.318 ;
-; 0.198 ; uart_tx:u_uart|state.S_D3 ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.319 ;
-; 0.201 ; uart_tx:u_uart|tick[8] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.321 ;
-; 0.204 ; uart_tx:u_uart|state.S_D5 ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.325 ;
-; 0.225 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.346 ;
-; 0.234 ; conv_step[0] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.354 ;
-; 0.239 ; fstate.F_CONVERT ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.359 ;
-; 0.264 ; uart_tx:u_uart|state.S_START ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.385 ;
-; 0.265 ; uart_tx:u_uart|state.S_D0 ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.386 ;
-; 0.267 ; lines_u[0] ; l_rem[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.388 ;
-; 0.267 ; lines_u[3] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.388 ;
-; 0.267 ; lines_u[1] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.387 ;
-; 0.268 ; width_u[4] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.389 ;
-; 0.268 ; lines_u[4] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.389 ;
-; 0.269 ; width_u[5] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.390 ;
-; 0.272 ; uart_tx:u_uart|state.S_D4 ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.393 ;
-; 0.272 ; req_sync[1] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.392 ;
-; 0.277 ; uart_tx:u_uart|state.S_D7 ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.398 ;
-; 0.278 ; fstate.F_LOAD ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.038 ; 0.400 ;
-; 0.278 ; uart_tx:u_uart|state.S_STOP ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.399 ;
-; 0.280 ; uart_tx:u_uart|state.S_STOP ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.401 ;
-; 0.298 ; uart_tx:u_uart|tick[1] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.418 ;
-; 0.298 ; uart_tx:u_uart|tick[3] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.418 ;
-; 0.298 ; uart_tx:u_uart|tick[5] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.418 ;
-; 0.299 ; uart_tx:u_uart|tick[7] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.419 ;
-; 0.300 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.420 ;
-; 0.300 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.420 ;
-; 0.301 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.421 ;
-; 0.309 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.429 ;
-; 0.311 ; idx[5] ; idx[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.431 ;
-; 0.325 ; idx[1] ; idx[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.445 ;
-; 0.333 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|tx ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.454 ;
-; 0.335 ; width_u[1] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.455 ;
-; 0.336 ; idx[4] ; idx[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.456 ;
-; 0.337 ; width_u[12] ; w_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.458 ;
-; 0.338 ; width_u[6] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.459 ;
-; 0.338 ; lines_u[13] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.459 ;
-; 0.338 ; lines_u[10] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.458 ;
-; 0.338 ; width_u[14] ; w_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.459 ;
-; 0.339 ; W3_r[3] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.460 ;
-; 0.339 ; lines_u[11] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.459 ;
-; 0.340 ; idx[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.460 ;
-; 0.340 ; tx_start ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.460 ;
-; 0.342 ; idx[4] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.462 ;
-; 0.347 ; idx[4] ; tx_byte[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.467 ;
-; 0.354 ; heartbeat_u ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.474 ;
-; 0.357 ; req_sync[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.477 ;
-; 0.359 ; fstate.F_CONVERT ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.479 ;
-; 0.376 ; fstate.F_LOAD ; tx_start ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.038 ; 0.498 ;
-; 0.395 ; width_u[10] ; w_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.516 ;
-; 0.397 ; width_u[15] ; w_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.518 ;
-; 0.397 ; width_u[7] ; w_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.517 ;
-; 0.399 ; W3_r[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.520 ;
-; 0.400 ; idx[3] ; idx[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.520 ;
-; 0.404 ; idx[0] ; idx[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.524 ;
-; 0.427 ; uart_tx:u_uart|state.S_IDLE ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.548 ;
-; 0.438 ; lines_u[6] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.559 ;
-; 0.438 ; width_u[8] ; w_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.558 ;
-; 0.439 ; lines_u[15] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.559 ;
-; 0.439 ; width_u[9] ; w_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.559 ;
-; 0.441 ; fstate.F_LOAD ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.561 ;
-; 0.442 ; idx[1] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.562 ;
-; 0.445 ; lines_u[12] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.565 ;
-; 0.447 ; lines_u[9] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.567 ;
-; 0.447 ; lines_u[8] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.567 ;
-; 0.447 ; uart_tx:u_uart|tick[1] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.567 ;
-; 0.447 ; uart_tx:u_uart|tick[5] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.567 ;
-; 0.447 ; uart_tx:u_uart|tick[3] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.567 ;
-; 0.448 ; lines_u[7] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.568 ;
-; 0.448 ; uart_tx:u_uart|tick[7] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.568 ;
-; 0.451 ; l_rem[0] ; L3_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.031 ; 0.566 ;
-; 0.455 ; lines_u[5] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.576 ;
-; 0.456 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.576 ;
-; 0.458 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.578 ;
-; 0.458 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.578 ;
-; 0.459 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.579 ;
-; 0.459 ; uart_tx:u_uart|tick[0] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.579 ;
-; 0.461 ; req_edge_q ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.581 ;
-; 0.461 ; uart_tx:u_uart|tick[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.581 ;
-; 0.461 ; uart_tx:u_uart|tick[6] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.581 ;
-; 0.462 ; uart_tx:u_uart|tick[4] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 0.582 ;
-; 0.464 ; fstate.F_WAIT ; fstate.F_LOAD ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.034 ; 0.582 ;
-; 0.465 ; W3_r[0] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 0.586 ;
-+-------+------------------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Hold: 'rx_clk' ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.186 ; de_monitor:u_mon|any_bad_width ; de_monitor:u_mon|any_bad_width ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.307 ;
-; 0.193 ; de_monitor:u_mon|width_o[7] ; width_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.314 ;
-; 0.193 ; de_monitor:u_mon|width_o[11] ; width_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.314 ;
-; 0.193 ; de_monitor:u_mon|width_o[10] ; width_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.314 ;
-; 0.193 ; de_monitor:u_mon|lines_o[1] ; lines_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.314 ;
-; 0.193 ; de_monitor:u_mon|lines_o[5] ; lines_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.314 ;
-; 0.194 ; de_monitor:u_mon|width_o[13] ; width_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.315 ;
-; 0.194 ; de_monitor:u_mon|lines_o[14] ; lines_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.314 ;
-; 0.194 ; de_monitor:u_mon|lines_o[6] ; lines_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.315 ;
-; 0.194 ; de_monitor:u_mon|lines_o[13] ; lines_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.314 ;
-; 0.194 ; de_monitor:u_mon|lines_o[12] ; lines_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.314 ;
-; 0.194 ; de_monitor:u_mon|lines_o[11] ; lines_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.314 ;
-; 0.194 ; de_monitor:u_mon|lines_o[3] ; lines_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.315 ;
-; 0.194 ; de_monitor:u_mon|lines_o[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.315 ;
-; 0.194 ; rst_sync_pix[1] ; rst_sync_pix[2] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.314 ;
-; 0.194 ; rst_sync_pix[0] ; rst_sync_pix[1] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.314 ;
-; 0.195 ; de_monitor:u_mon|width_o[15] ; width_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|width_o[2] ; width_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|width_o[9] ; width_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|width_o[3] ; width_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|width_o[1] ; width_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|lines_o[9] ; lines_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|lines_o[7] ; lines_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.195 ; de_monitor:u_mon|lines_o[8] ; lines_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.315 ;
-; 0.196 ; de_monitor:u_mon|width_o[0] ; width_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.316 ;
-; 0.196 ; de_monitor:u_mon|lines_o[15] ; lines_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.316 ;
-; 0.197 ; de_monitor:u_mon|lines_o[10] ; lines_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.317 ;
-; 0.197 ; hb_count[7] ; hb_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.318 ;
-; 0.265 ; de_monitor:u_mon|lines_o[0] ; lines_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.386 ;
-; 0.266 ; de_monitor:u_mon|width_o[6] ; width_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.387 ;
-; 0.267 ; de_monitor:u_mon|lines_o[4] ; lines_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.388 ;
-; 0.268 ; de_monitor:u_mon|width_o[14] ; width_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.388 ;
-; 0.268 ; de_monitor:u_mon|width_o[12] ; width_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.389 ;
-; 0.268 ; de_monitor:u_mon|width_o[4] ; width_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.389 ;
-; 0.268 ; de_monitor:u_mon|width_o[5] ; width_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.389 ;
-; 0.268 ; de_monitor:u_mon|anomaly_o ; anomaly_lat ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.388 ;
-; 0.269 ; de_monitor:u_mon|width_o[8] ; width_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.389 ;
-; 0.272 ; de_monitor:u_mon|line_count[4] ; de_monitor:u_mon|lines_o[4] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.392 ;
-; 0.280 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.402 ;
-; 0.282 ; de_monitor:u_mon|line_count[5] ; de_monitor:u_mon|lines_o[5] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.402 ;
-; 0.283 ; de_monitor:u_mon|line_count[1] ; de_monitor:u_mon|lines_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.403 ;
-; 0.284 ; de_monitor:u_mon|line_count[6] ; de_monitor:u_mon|lines_o[6] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.404 ;
-; 0.291 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.413 ;
-; 0.292 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.414 ;
-; 0.296 ; hb_count[1] ; hb_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.417 ;
-; 0.303 ; de_monitor:u_mon|line_count[15] ; de_monitor:u_mon|line_count[15] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.424 ;
-; 0.303 ; de_monitor:u_mon|line_width[15] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.424 ;
-; 0.304 ; de_monitor:u_mon|line_width[13] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_width[5] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_width[1] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_count[13] ; de_monitor:u_mon|line_count[13] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_count[11] ; de_monitor:u_mon|line_count[11] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_count[5] ; de_monitor:u_mon|line_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_count[3] ; de_monitor:u_mon|line_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.304 ; de_monitor:u_mon|line_count[1] ; de_monitor:u_mon|line_count[1] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.425 ;
-; 0.305 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.426 ;
-; 0.305 ; de_monitor:u_mon|line_width[7] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.426 ;
-; 0.305 ; de_monitor:u_mon|line_width[6] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.426 ;
-; 0.305 ; de_monitor:u_mon|line_count[9] ; de_monitor:u_mon|line_count[9] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.426 ;
-; 0.305 ; de_monitor:u_mon|line_count[7] ; de_monitor:u_mon|line_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.426 ;
-; 0.305 ; de_monitor:u_mon|line_count[6] ; de_monitor:u_mon|line_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.426 ;
-; 0.306 ; de_monitor:u_mon|line_width[14] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_count[14] ; de_monitor:u_mon|line_count[14] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_count[8] ; de_monitor:u_mon|line_count[8] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_count[4] ; de_monitor:u_mon|line_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; de_monitor:u_mon|line_count[2] ; de_monitor:u_mon|line_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.306 ; hb_count[6] ; hb_count[6] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.427 ;
-; 0.307 ; de_monitor:u_mon|line_width[12] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.428 ;
-; 0.307 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.428 ;
-; 0.307 ; de_monitor:u_mon|line_count[12] ; de_monitor:u_mon|line_count[12] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.428 ;
-; 0.307 ; de_monitor:u_mon|line_count[10] ; de_monitor:u_mon|line_count[10] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.428 ;
-; 0.315 ; hb_count[0] ; hb_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.436 ;
-; 0.316 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.437 ;
-; 0.316 ; de_monitor:u_mon|line_count[0] ; de_monitor:u_mon|line_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.437 ;
-; 0.338 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.459 ;
-; 0.338 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.459 ;
-; 0.341 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|bad_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.463 ;
-; 0.349 ; de_monitor:u_mon|line_count[3] ; de_monitor:u_mon|lines_o[3] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.469 ;
-; 0.349 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.470 ;
-; 0.350 ; de_monitor:u_mon|line_count[2] ; de_monitor:u_mon|lines_o[2] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 0.470 ;
-; 0.353 ; de_monitor:u_mon|line_width[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.474 ;
-; 0.353 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|bad_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.475 ;
-; 0.354 ; de_monitor:u_mon|line_width[10] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.476 ;
-; 0.354 ; de_monitor:u_mon|line_width[3] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.475 ;
-; 0.355 ; de_monitor:u_mon|line_width[5] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.477 ;
-; 0.360 ; de_monitor:u_mon|line_width[0] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.481 ;
-; 0.368 ; de_monitor:u_mon|line_width[4] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.490 ;
-; 0.368 ; hb_count[5] ; heartbeat_lat ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.489 ;
-; 0.368 ; hb_count[5] ; hb_count[2] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.489 ;
-; 0.368 ; hb_count[5] ; hb_count[3] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.489 ;
-; 0.368 ; hb_count[5] ; hb_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.489 ;
-; 0.369 ; hb_count[5] ; hb_count[5] ; rx_clk ; rx_clk ; 0.000 ; 0.037 ; 0.490 ;
-; 0.382 ; de_monitor:u_mon|line_width[8] ; de_monitor:u_mon|bad_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.504 ;
-; 0.398 ; de_monitor:u_mon|line_width[9] ; de_monitor:u_mon|bad_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.520 ;
-; 0.399 ; de_monitor:u_mon|line_width[11] ; de_monitor:u_mon|bad_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.038 ; 0.521 ;
-+-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Recovery: 'rx_clk' ;
-+--------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.194 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|de_q ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[1] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[2] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[3] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[5] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[12] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[13] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[15] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[6] ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|frame_active ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.259 ; rst_sync_pix[2] ; de_monitor:u_mon|frame_done ; rx_clk ; rx_clk ; 13.500 ; -0.035 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; lines_lat[6] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; lines_lat[1] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; lines_lat[3] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; lines_lat[4] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; lines_lat[5] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[15] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[14] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[13] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[12] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[11] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[10] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[9] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[8] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[7] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[6] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[5] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[5] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[4] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[3] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[3] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[2] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[2] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[1] ; rx_clk ; rx_clk ; 13.500 ; -0.038 ; 2.189 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[1] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[0] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.190 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[0] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[4] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[7] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[8] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[9] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[10] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[11] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[14] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|any_bad_width ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[5] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[1] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[4] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[3] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[10] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[11] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[9] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[8] ; rx_clk ; rx_clk ; 13.500 ; -0.033 ; 2.194 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[2] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.260 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[0] ; rx_clk ; rx_clk ; 13.500 ; -0.034 ; 2.193 ;
-; 11.261 ; rst_sync_pix[2] ; lines_lat[0] ; rx_clk ; rx_clk ; 13.500 ; -0.043 ; 2.183 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[6] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[7] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[11] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[13] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[12] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[10] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[4] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-; 11.261 ; rst_sync_pix[2] ; width_lat[5] ; rx_clk ; rx_clk ; 13.500 ; -0.037 ; 2.189 ;
-+--------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Recovery: 'clk_50mhz' ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 18.082 ; rst_sync_uart[2] ; req_sync[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.036 ; 1.869 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; L1_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.032 ; 1.681 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; L1_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.032 ; 1.681 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.274 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.675 ;
-; 18.275 ; rst_sync_uart[2] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 1.671 ;
-; 18.275 ; rst_sync_uart[2] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 1.671 ;
-; 18.275 ; rst_sync_uart[2] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 1.671 ;
-; 18.275 ; rst_sync_uart[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 1.672 ;
-; 18.275 ; rst_sync_uart[2] ; W0_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 1.672 ;
-; 18.275 ; rst_sync_uart[2] ; W0_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 1.672 ;
-; 18.275 ; rst_sync_uart[2] ; W2_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; W2_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; W3_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; req_sync[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; req_sync[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; heartbeat_u ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; req_edge_q ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; anomaly_u ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; fstate.F_IDLE ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; msg_len[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; msg_len[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; is_err_msg ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; fstate.F_LOAD ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.051 ; 1.661 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.038 ; 1.674 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.047 ; 1.665 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.047 ; 1.665 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.047 ; 1.665 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.047 ; 1.665 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.047 ; 1.665 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[14] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.047 ; 1.665 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[5] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 1.671 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[4] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.041 ; 1.671 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.033 ; 1.679 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[13] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.032 ; 1.680 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[11] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.032 ; 1.680 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.040 ; 1.672 ;
-; 18.275 ; rst_sync_uart[2] ; tx_byte[6] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; L0_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 1.670 ;
-; 18.275 ; rst_sync_uart[2] ; L3_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; L2_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; W3_r[1] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; L2_r[2] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; width_u[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; w_rem[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; W3_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; L2_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; lines_u[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; l_rem[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.045 ; 1.667 ;
-; 18.275 ; rst_sync_uart[2] ; L3_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; L1_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.033 ; 1.679 ;
-; 18.275 ; rst_sync_uart[2] ; L0_r[0] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 1.670 ;
-; 18.275 ; rst_sync_uart[2] ; W3_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.043 ; 1.669 ;
-; 18.275 ; rst_sync_uart[2] ; L0_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 1.670 ;
-; 18.275 ; rst_sync_uart[2] ; L1_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.042 ; 1.670 ;
-; 18.275 ; rst_sync_uart[2] ; L3_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-; 18.275 ; rst_sync_uart[2] ; L2_r[3] ; clk_50mhz ; clk_50mhz ; 20.000 ; -0.050 ; 1.662 ;
-+--------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Removal: 'clk_50mhz' ;
-+-------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-; 1.361 ; rst_sync_uart[2] ; w_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.042 ; 1.487 ;
-; 1.361 ; rst_sync_uart[2] ; W0_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.042 ; 1.487 ;
-; 1.361 ; rst_sync_uart[2] ; W0_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.042 ; 1.487 ;
-; 1.361 ; rst_sync_uart[2] ; uart_tx:u_uart|busy ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.489 ;
-; 1.361 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_START ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.489 ;
-; 1.361 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D0 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.489 ;
-; 1.361 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_IDLE ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.489 ;
-; 1.361 ; rst_sync_uart[2] ; lines_u[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.484 ;
-; 1.361 ; rst_sync_uart[2] ; lines_u[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.484 ;
-; 1.361 ; rst_sync_uart[2] ; lines_u[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.484 ;
-; 1.361 ; rst_sync_uart[2] ; l_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.484 ;
-; 1.361 ; rst_sync_uart[2] ; l_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.484 ;
-; 1.361 ; rst_sync_uart[2] ; l_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.484 ;
-; 1.361 ; rst_sync_uart[2] ; width_u[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.049 ; 1.494 ;
-; 1.361 ; rst_sync_uart[2] ; width_u[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.050 ; 1.495 ;
-; 1.361 ; rst_sync_uart[2] ; width_u[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.050 ; 1.495 ;
-; 1.361 ; rst_sync_uart[2] ; width_u[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.042 ; 1.487 ;
-; 1.361 ; rst_sync_uart[2] ; L0_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.040 ; 1.485 ;
-; 1.361 ; rst_sync_uart[2] ; L1_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.049 ; 1.494 ;
-; 1.361 ; rst_sync_uart[2] ; L0_r[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.040 ; 1.485 ;
-; 1.361 ; rst_sync_uart[2] ; L0_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.040 ; 1.485 ;
-; 1.361 ; rst_sync_uart[2] ; L1_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.040 ; 1.485 ;
-; 1.361 ; rst_sync_uart[2] ; uart_tx:u_uart|tx ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; tx_byte[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; tx_byte[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; tx_byte[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; tx_byte[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; W0_r[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; W0_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; w_rem[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.041 ; 1.487 ;
-; 1.362 ; rst_sync_uart[2] ; w_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.048 ; 1.494 ;
-; 1.362 ; rst_sync_uart[2] ; w_rem[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.041 ; 1.487 ;
-; 1.362 ; rst_sync_uart[2] ; w_rem[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.041 ; 1.487 ;
-; 1.362 ; rst_sync_uart[2] ; W3_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; fstate.F_WAIT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.032 ; 1.478 ;
-; 1.362 ; rst_sync_uart[2] ; conv_step[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.032 ; 1.478 ;
-; 1.362 ; rst_sync_uart[2] ; conv_step[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.032 ; 1.478 ;
-; 1.362 ; rst_sync_uart[2] ; fstate.F_CONVERT ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.032 ; 1.478 ;
-; 1.362 ; rst_sync_uart[2] ; msg_len[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 1.483 ;
-; 1.362 ; rst_sync_uart[2] ; msg_len[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 1.483 ;
-; 1.362 ; rst_sync_uart[2] ; idx[0] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; idx[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; idx[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; idx[3] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; is_err_msg ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.037 ; 1.483 ;
-; 1.362 ; rst_sync_uart[2] ; idx[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; idx[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; tx_start ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.032 ; 1.478 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D1 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D2 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D3 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D4 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D5 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D6 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_D7 ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|state.S_STOP ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|tick[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.043 ; 1.489 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.028 ; 1.474 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.048 ; 1.494 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.048 ; 1.494 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[11] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[10] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[12] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[8] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.036 ; 1.482 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[7] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.035 ; 1.481 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[13] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.035 ; 1.481 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.035 ; 1.481 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.035 ; 1.481 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[15] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[9] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.030 ; 1.476 ;
-; 1.362 ; rst_sync_uart[2] ; lines_u[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.035 ; 1.481 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[14] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.035 ; 1.481 ;
-; 1.362 ; rst_sync_uart[2] ; l_rem[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.028 ; 1.474 ;
-; 1.362 ; rst_sync_uart[2] ; width_u[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.041 ; 1.487 ;
-; 1.362 ; rst_sync_uart[2] ; width_u[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.048 ; 1.494 ;
-; 1.362 ; rst_sync_uart[2] ; width_u[4] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.041 ; 1.487 ;
-; 1.362 ; rst_sync_uart[2] ; tx_byte[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[6] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; tx_byte[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[5] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; L1_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.050 ; 1.496 ;
-; 1.362 ; rst_sync_uart[2] ; W3_r[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.039 ; 1.485 ;
-; 1.362 ; rst_sync_uart[2] ; uart_tx:u_uart|shift[1] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.044 ; 1.490 ;
-; 1.362 ; rst_sync_uart[2] ; L1_r[2] ; clk_50mhz ; clk_50mhz ; 0.000 ; 0.050 ; 1.496 ;
-+-------+------------------+------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Fast 1200mV 0C Model Removal: 'rx_clk' ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-; 1.805 ; rst_sync_pix[2] ; width_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[6] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[7] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[7] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[11] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[13] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[12] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[10] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[10] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[4] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; width_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[5] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.925 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[0] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[4] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[7] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[8] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[9] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[10] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[11] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|gap_count[14] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|any_bad_width ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.928 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.805 ; rst_sync_pix[2] ; de_monitor:u_mon|bad_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.040 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.030 ; 1.920 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[0] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[0] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[14] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[15] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[15] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[2] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[8] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[8] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[9] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[9] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[3] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; width_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|width_o[1] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[14] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[6] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[13] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[12] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[1] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[11] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[3] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[4] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[2] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; lines_lat[5] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[15] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.926 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[15] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[14] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[13] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[12] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[11] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[10] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[9] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[8] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[7] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.035 ; 1.925 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[6] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[5] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[4] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[3] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[2] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[1] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|last_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_width[0] ; rx_clk ; rx_clk ; 0.000 ; 0.039 ; 1.929 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[14] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[14] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.926 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[13] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[13] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.926 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[12] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[12] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.926 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|lines_o[11] ; rx_clk ; rx_clk ; 0.000 ; 0.021 ; 1.911 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[11] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.926 ;
-; 1.806 ; rst_sync_pix[2] ; de_monitor:u_mon|line_count[10] ; rx_clk ; rx_clk ; 0.000 ; 0.036 ; 1.926 ;
-+-------+-----------------+---------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-----------------------------------------------
-; Fast 1200mV 0C Model Metastability Summary ;
-----------------------------------------------
-The design MTBF is not calculated because there are no specified synchronizers in the design.
-Number of Synchronizer Chains Found: 46
-Shortest Synchronizer Chain: 2 Registers
-Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
-Worst Case Available Settling Time: 13.010 ns
-
-
-
-
-+-----------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------+-------+----------+---------+---------------------+
-; Worst-case Slack ; 4.242 ; 0.186 ; 8.730 ; 1.361 ; 6.002 ;
-; clk_50mhz ; 4.242 ; 0.186 ; 15.869 ; 1.361 ; 9.262 ;
-; rx_clk ; 7.059 ; 0.186 ; 8.730 ; 1.805 ; 6.002 ;
-; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-; clk_50mhz ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;
-; rx_clk ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;
-+------------------+-------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; uart_tx_pin ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; vsync ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; hsync ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; clk_50mhz ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; rst_n_pin ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; rx_clk ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; de ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; uart_tx_pin ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.51e-09 V ; 3.18 V ; -0.157 V ; 0.147 V ; 0.259 V ; 2.81e-10 s ; 2.53e-10 s ; Yes ; Yes ; 3.08 V ; 3.51e-09 V ; 3.18 V ; -0.157 V ; 0.147 V ; 0.259 V ; 2.81e-10 s ; 2.53e-10 s ; Yes ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; uart_tx_pin ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.6e-07 V ; 3.13 V ; -0.103 V ; 0.164 V ; 0.134 V ; 3.14e-10 s ; 4.05e-10 s ; Yes ; No ; 3.08 V ; 2.6e-07 V ; 3.13 V ; -0.103 V ; 0.164 V ; 0.134 V ; 3.14e-10 s ; 4.05e-10 s ; Yes ; No ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; uart_tx_pin ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ;
-; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+----------------------------------------------------------------------+
-; Setup Transfers ;
-+------------+-----------+------------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+-----------+------------+----------+----------+----------+
-; clk_50mhz ; clk_50mhz ; 29227 ; 0 ; 0 ; 0 ;
-; rx_clk ; clk_50mhz ; false path ; 0 ; 0 ; 0 ;
-; rx_clk ; rx_clk ; 3018 ; 0 ; 0 ; 0 ;
-+------------+-----------+------------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+----------------------------------------------------------------------+
-; Hold Transfers ;
-+------------+-----------+------------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+-----------+------------+----------+----------+----------+
-; clk_50mhz ; clk_50mhz ; 29227 ; 0 ; 0 ; 0 ;
-; rx_clk ; clk_50mhz ; false path ; 0 ; 0 ; 0 ;
-; rx_clk ; rx_clk ; 3018 ; 0 ; 0 ; 0 ;
-+------------+-----------+------------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+--------------------------------------------------------------------+
-; Recovery Transfers ;
-+------------+-----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+-----------+----------+----------+----------+----------+
-; clk_50mhz ; clk_50mhz ; 154 ; 0 ; 0 ; 0 ;
-; rx_clk ; rx_clk ; 159 ; 0 ; 0 ; 0 ;
-+------------+-----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+--------------------------------------------------------------------+
-; Removal Transfers ;
-+------------+-----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+-----------+----------+----------+----------+----------+
-; clk_50mhz ; clk_50mhz ; 154 ; 0 ; 0 ; 0 ;
-; rx_clk ; rx_clk ; 159 ; 0 ; 0 ; 0 ;
-+------------+-----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 0 ; 0 ;
-; Unconstrained Input Port Paths ; 0 ; 0 ;
-; Unconstrained Output Ports ; 0 ; 0 ;
-; Unconstrained Output Port Paths ; 0 ; 0 ;
-+---------------------------------+-------+------+
-
-
-+--------------------------------------------+
-; Clock Status Summary ;
-+-----------+-----------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+-----------+-----------+------+-------------+
-; clk_50mhz ; clk_50mhz ; Base ; Constrained ;
-; rx_clk ; rx_clk ; Base ; Constrained ;
-+-----------+-----------+------+-------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Timing Analyzer
- Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
- Info: Processing started: Wed Jun 10 09:07:10 2026
-Info: Command: quartus_sta lvds_monitor -c lvds_monitor
-Info: qsta_default_script.tcl version: #1
-Info (20030): Parallel compilation is enabled and will use 14 of the 14 processors detected
-Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
-Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
-Info (332104): Reading SDC File: 'lvds_monitor.sdc'
-Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1200mV 85C Model
-Info (332146): Worst-case setup slack is 4.242
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 4.242 0.000 clk_50mhz
- Info (332119): 7.059 0.000 rx_clk
-Info (332146): Worst-case hold slack is 0.452
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.452 0.000 clk_50mhz
- Info (332119): 0.452 0.000 rx_clk
-Info (332146): Worst-case recovery slack is 8.730
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 8.730 0.000 rx_clk
- Info (332119): 15.869 0.000 clk_50mhz
-Info (332146): Worst-case removal slack is 3.067
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 3.067 0.000 clk_50mhz
- Info (332119): 4.061 0.000 rx_clk
-Info (332146): Worst-case minimum pulse width slack is 6.480
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 6.480 0.000 rx_clk
- Info (332119): 9.735 0.000 clk_50mhz
-Info (332114): Report Metastability: Found 46 synchronizer chains.
- Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
- Info (332114): Number of Synchronizer Chains Found: 46
- Info (332114): Shortest Synchronizer Chain: 2 Registers
- Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
- Info (332114): Worst Case Available Settling Time: 12.327 ns
- Info (332114):
-Info: Analyzing Slow 1200mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info (332146): Worst-case setup slack is 5.201
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 5.201 0.000 clk_50mhz
- Info (332119): 7.569 0.000 rx_clk
-Info (332146): Worst-case hold slack is 0.401
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.401 0.000 clk_50mhz
- Info (332119): 0.401 0.000 rx_clk
-Info (332146): Worst-case recovery slack is 9.063
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 9.063 0.000 rx_clk
- Info (332119): 16.187 0.000 clk_50mhz
-Info (332146): Worst-case removal slack is 2.755
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 2.755 0.000 clk_50mhz
- Info (332119): 3.637 0.000 rx_clk
-Info (332146): Worst-case minimum pulse width slack is 6.498
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 6.498 0.000 rx_clk
- Info (332119): 9.750 0.000 clk_50mhz
-Info (332114): Report Metastability: Found 46 synchronizer chains.
- Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
- Info (332114): Number of Synchronizer Chains Found: 46
- Info (332114): Shortest Synchronizer Chain: 2 Registers
- Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
- Info (332114): Worst Case Available Settling Time: 12.424 ns
- Info (332114):
-Info: Analyzing Fast 1200mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
-Info (332146): Worst-case setup slack is 10.706
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 10.706 0.000 rx_clk
- Info (332119): 13.064 0.000 clk_50mhz
-Info (332146): Worst-case hold slack is 0.186
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.186 0.000 clk_50mhz
- Info (332119): 0.186 0.000 rx_clk
-Info (332146): Worst-case recovery slack is 11.259
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 11.259 0.000 rx_clk
- Info (332119): 18.082 0.000 clk_50mhz
-Info (332146): Worst-case removal slack is 1.361
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 1.361 0.000 clk_50mhz
- Info (332119): 1.805 0.000 rx_clk
-Info (332146): Worst-case minimum pulse width slack is 6.002
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 6.002 0.000 rx_clk
- Info (332119): 9.262 0.000 clk_50mhz
-Info (332114): Report Metastability: Found 46 synchronizer chains.
- Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
- Info (332114): Number of Synchronizer Chains Found: 46
- Info (332114): Shortest Synchronizer Chain: 2 Registers
- Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
- Info (332114): Worst Case Available Settling Time: 13.010 ns
- Info (332114):
-Info (332101): Design is fully constrained for setup requirements
-Info (332101): Design is fully constrained for hold requirements
-Info: Quartus Prime Timing Analyzer was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 4946 megabytes
- Info: Processing ended: Wed Jun 10 09:07:11 2026
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:02
-
-
diff --git a/lvds_monitor.sta.summary b/lvds_monitor.sta.summary
deleted file mode 100644
index b5ca7d0..0000000
--- a/lvds_monitor.sta.summary
+++ /dev/null
@@ -1,125 +0,0 @@
-------------------------------------------------------------
-Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1200mV 85C Model Setup 'clk_50mhz'
-Slack : 4.242
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Setup 'rx_clk'
-Slack : 7.059
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Hold 'clk_50mhz'
-Slack : 0.452
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Hold 'rx_clk'
-Slack : 0.452
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Recovery 'rx_clk'
-Slack : 8.730
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Recovery 'clk_50mhz'
-Slack : 15.869
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Removal 'clk_50mhz'
-Slack : 3.067
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Removal 'rx_clk'
-Slack : 4.061
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'rx_clk'
-Slack : 6.480
-TNS : 0.000
-
-Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_50mhz'
-Slack : 9.735
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Setup 'clk_50mhz'
-Slack : 5.201
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Setup 'rx_clk'
-Slack : 7.569
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Hold 'clk_50mhz'
-Slack : 0.401
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Hold 'rx_clk'
-Slack : 0.401
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Recovery 'rx_clk'
-Slack : 9.063
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Recovery 'clk_50mhz'
-Slack : 16.187
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Removal 'clk_50mhz'
-Slack : 2.755
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Removal 'rx_clk'
-Slack : 3.637
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'rx_clk'
-Slack : 6.498
-TNS : 0.000
-
-Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_50mhz'
-Slack : 9.750
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Setup 'rx_clk'
-Slack : 10.706
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Setup 'clk_50mhz'
-Slack : 13.064
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Hold 'clk_50mhz'
-Slack : 0.186
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Hold 'rx_clk'
-Slack : 0.186
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Recovery 'rx_clk'
-Slack : 11.259
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Recovery 'clk_50mhz'
-Slack : 18.082
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Removal 'clk_50mhz'
-Slack : 1.361
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Removal 'rx_clk'
-Slack : 1.805
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'rx_clk'
-Slack : 6.002
-TNS : 0.000
-
-Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_50mhz'
-Slack : 9.262
-TNS : 0.000
-
-------------------------------------------------------------