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e22e0a0e5a6dabf3dfcba9ca1393c35c3e15f21c
Automotive-Power-Simulator/Debug/POWER_SWITCH.list
David Rice e22e0a0e5a updates
2026-02-18 16:23:27 +00:00

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824 KiB
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POWER_SWITCH.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001d8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00007ea0 080001d8 080001d8 000011d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000074 08008078 08008078 00009078 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080080ec 080080ec 0000a028 2**0
CONTENTS, READONLY
4 .ARM 00000008 080080ec 080080ec 000090ec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080080f4 080080f4 0000a028 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080080f4 080080f4 000090f4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080080f8 080080f8 000090f8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000028 20000000 080080fc 0000a000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000033c 20000028 08008124 0000a028 2**2
ALLOC
10 ._user_heap_stack 00000604 20000364 08008124 0000a364 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000a028 2**0
CONTENTS, READONLY
12 .debug_info 00017526 00000000 00000000 0000a058 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00002a3a 00000000 00000000 0002157e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000014c0 00000000 00000000 00023fb8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00001039 00000000 00000000 00025478 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00020283 00000000 00000000 000264b1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00016aa4 00000000 00000000 00046734 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000db157 00000000 00000000 0005d1d8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 0013832f 2**0
CONTENTS, READONLY
20 .debug_frame 00005a34 00000000 00000000 00138374 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 0000006d 00000000 00000000 0013dda8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d8 <__do_global_dtors_aux>:
80001d8: b510 push {r4, lr}
80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
80001dc: 7823 ldrb r3, [r4, #0]
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
80001e6: f3af 8000 nop.w
80001ea: 2301 movs r3, #1
80001ec: 7023 strb r3, [r4, #0]
80001ee: bd10 pop {r4, pc}
80001f0: 20000028 .word 0x20000028
80001f4: 00000000 .word 0x00000000
80001f8: 08008060 .word 0x08008060
080001fc <frame_dummy>:
80001fc: b508 push {r3, lr}
80001fe: 4b03 ldr r3, [pc, #12] @ (800020c <frame_dummy+0x10>)
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
8000202: 4903 ldr r1, [pc, #12] @ (8000210 <frame_dummy+0x14>)
8000204: 4803 ldr r0, [pc, #12] @ (8000214 <frame_dummy+0x18>)
8000206: f3af 8000 nop.w
800020a: bd08 pop {r3, pc}
800020c: 00000000 .word 0x00000000
8000210: 2000002c .word 0x2000002c
8000214: 08008060 .word 0x08008060
08000218 <__aeabi_uldivmod>:
8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18>
800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18>
800021c: 2900 cmp r1, #0
800021e: bf08 it eq
8000220: 2800 cmpeq r0, #0
8000222: bf1c itt ne
8000224: f04f 31ff movne.w r1, #4294967295
8000228: f04f 30ff movne.w r0, #4294967295
800022c: f000 b988 b.w 8000540 <__aeabi_idiv0>
8000230: f1ad 0c08 sub.w ip, sp, #8
8000234: e96d ce04 strd ip, lr, [sp, #-16]!
8000238: f000 f806 bl 8000248 <__udivmoddi4>
800023c: f8dd e004 ldr.w lr, [sp, #4]
8000240: e9dd 2302 ldrd r2, r3, [sp, #8]
8000244: b004 add sp, #16
8000246: 4770 bx lr
08000248 <__udivmoddi4>:
8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800024c: 9d08 ldr r5, [sp, #32]
800024e: 468e mov lr, r1
8000250: 4604 mov r4, r0
8000252: 4688 mov r8, r1
8000254: 2b00 cmp r3, #0
8000256: d14a bne.n 80002ee <__udivmoddi4+0xa6>
8000258: 428a cmp r2, r1
800025a: 4617 mov r7, r2
800025c: d962 bls.n 8000324 <__udivmoddi4+0xdc>
800025e: fab2 f682 clz r6, r2
8000262: b14e cbz r6, 8000278 <__udivmoddi4+0x30>
8000264: f1c6 0320 rsb r3, r6, #32
8000268: fa01 f806 lsl.w r8, r1, r6
800026c: fa20 f303 lsr.w r3, r0, r3
8000270: 40b7 lsls r7, r6
8000272: ea43 0808 orr.w r8, r3, r8
8000276: 40b4 lsls r4, r6
8000278: ea4f 4e17 mov.w lr, r7, lsr #16
800027c: fa1f fc87 uxth.w ip, r7
8000280: fbb8 f1fe udiv r1, r8, lr
8000284: 0c23 lsrs r3, r4, #16
8000286: fb0e 8811 mls r8, lr, r1, r8
800028a: ea43 4308 orr.w r3, r3, r8, lsl #16
800028e: fb01 f20c mul.w r2, r1, ip
8000292: 429a cmp r2, r3
8000294: d909 bls.n 80002aa <__udivmoddi4+0x62>
8000296: 18fb adds r3, r7, r3
8000298: f101 30ff add.w r0, r1, #4294967295
800029c: f080 80ea bcs.w 8000474 <__udivmoddi4+0x22c>
80002a0: 429a cmp r2, r3
80002a2: f240 80e7 bls.w 8000474 <__udivmoddi4+0x22c>
80002a6: 3902 subs r1, #2
80002a8: 443b add r3, r7
80002aa: 1a9a subs r2, r3, r2
80002ac: b2a3 uxth r3, r4
80002ae: fbb2 f0fe udiv r0, r2, lr
80002b2: fb0e 2210 mls r2, lr, r0, r2
80002b6: ea43 4302 orr.w r3, r3, r2, lsl #16
80002ba: fb00 fc0c mul.w ip, r0, ip
80002be: 459c cmp ip, r3
80002c0: d909 bls.n 80002d6 <__udivmoddi4+0x8e>
80002c2: 18fb adds r3, r7, r3
80002c4: f100 32ff add.w r2, r0, #4294967295
80002c8: f080 80d6 bcs.w 8000478 <__udivmoddi4+0x230>
80002cc: 459c cmp ip, r3
80002ce: f240 80d3 bls.w 8000478 <__udivmoddi4+0x230>
80002d2: 443b add r3, r7
80002d4: 3802 subs r0, #2
80002d6: ea40 4001 orr.w r0, r0, r1, lsl #16
80002da: eba3 030c sub.w r3, r3, ip
80002de: 2100 movs r1, #0
80002e0: b11d cbz r5, 80002ea <__udivmoddi4+0xa2>
80002e2: 40f3 lsrs r3, r6
80002e4: 2200 movs r2, #0
80002e6: e9c5 3200 strd r3, r2, [r5]
80002ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ee: 428b cmp r3, r1
80002f0: d905 bls.n 80002fe <__udivmoddi4+0xb6>
80002f2: b10d cbz r5, 80002f8 <__udivmoddi4+0xb0>
80002f4: e9c5 0100 strd r0, r1, [r5]
80002f8: 2100 movs r1, #0
80002fa: 4608 mov r0, r1
80002fc: e7f5 b.n 80002ea <__udivmoddi4+0xa2>
80002fe: fab3 f183 clz r1, r3
8000302: 2900 cmp r1, #0
8000304: d146 bne.n 8000394 <__udivmoddi4+0x14c>
8000306: 4573 cmp r3, lr
8000308: d302 bcc.n 8000310 <__udivmoddi4+0xc8>
800030a: 4282 cmp r2, r0
800030c: f200 8105 bhi.w 800051a <__udivmoddi4+0x2d2>
8000310: 1a84 subs r4, r0, r2
8000312: eb6e 0203 sbc.w r2, lr, r3
8000316: 2001 movs r0, #1
8000318: 4690 mov r8, r2
800031a: 2d00 cmp r5, #0
800031c: d0e5 beq.n 80002ea <__udivmoddi4+0xa2>
800031e: e9c5 4800 strd r4, r8, [r5]
8000322: e7e2 b.n 80002ea <__udivmoddi4+0xa2>
8000324: 2a00 cmp r2, #0
8000326: f000 8090 beq.w 800044a <__udivmoddi4+0x202>
800032a: fab2 f682 clz r6, r2
800032e: 2e00 cmp r6, #0
8000330: f040 80a4 bne.w 800047c <__udivmoddi4+0x234>
8000334: 1a8a subs r2, r1, r2
8000336: 0c03 lsrs r3, r0, #16
8000338: ea4f 4e17 mov.w lr, r7, lsr #16
800033c: b280 uxth r0, r0
800033e: b2bc uxth r4, r7
8000340: 2101 movs r1, #1
8000342: fbb2 fcfe udiv ip, r2, lr
8000346: fb0e 221c mls r2, lr, ip, r2
800034a: ea43 4302 orr.w r3, r3, r2, lsl #16
800034e: fb04 f20c mul.w r2, r4, ip
8000352: 429a cmp r2, r3
8000354: d907 bls.n 8000366 <__udivmoddi4+0x11e>
8000356: 18fb adds r3, r7, r3
8000358: f10c 38ff add.w r8, ip, #4294967295
800035c: d202 bcs.n 8000364 <__udivmoddi4+0x11c>
800035e: 429a cmp r2, r3
8000360: f200 80e0 bhi.w 8000524 <__udivmoddi4+0x2dc>
8000364: 46c4 mov ip, r8
8000366: 1a9b subs r3, r3, r2
8000368: fbb3 f2fe udiv r2, r3, lr
800036c: fb0e 3312 mls r3, lr, r2, r3
8000370: ea40 4303 orr.w r3, r0, r3, lsl #16
8000374: fb02 f404 mul.w r4, r2, r4
8000378: 429c cmp r4, r3
800037a: d907 bls.n 800038c <__udivmoddi4+0x144>
800037c: 18fb adds r3, r7, r3
800037e: f102 30ff add.w r0, r2, #4294967295
8000382: d202 bcs.n 800038a <__udivmoddi4+0x142>
8000384: 429c cmp r4, r3
8000386: f200 80ca bhi.w 800051e <__udivmoddi4+0x2d6>
800038a: 4602 mov r2, r0
800038c: 1b1b subs r3, r3, r4
800038e: ea42 400c orr.w r0, r2, ip, lsl #16
8000392: e7a5 b.n 80002e0 <__udivmoddi4+0x98>
8000394: f1c1 0620 rsb r6, r1, #32
8000398: 408b lsls r3, r1
800039a: fa22 f706 lsr.w r7, r2, r6
800039e: 431f orrs r7, r3
80003a0: fa0e f401 lsl.w r4, lr, r1
80003a4: fa20 f306 lsr.w r3, r0, r6
80003a8: fa2e fe06 lsr.w lr, lr, r6
80003ac: ea4f 4917 mov.w r9, r7, lsr #16
80003b0: 4323 orrs r3, r4
80003b2: fa00 f801 lsl.w r8, r0, r1
80003b6: fa1f fc87 uxth.w ip, r7
80003ba: fbbe f0f9 udiv r0, lr, r9
80003be: 0c1c lsrs r4, r3, #16
80003c0: fb09 ee10 mls lr, r9, r0, lr
80003c4: ea44 440e orr.w r4, r4, lr, lsl #16
80003c8: fb00 fe0c mul.w lr, r0, ip
80003cc: 45a6 cmp lr, r4
80003ce: fa02 f201 lsl.w r2, r2, r1
80003d2: d909 bls.n 80003e8 <__udivmoddi4+0x1a0>
80003d4: 193c adds r4, r7, r4
80003d6: f100 3aff add.w sl, r0, #4294967295
80003da: f080 809c bcs.w 8000516 <__udivmoddi4+0x2ce>
80003de: 45a6 cmp lr, r4
80003e0: f240 8099 bls.w 8000516 <__udivmoddi4+0x2ce>
80003e4: 3802 subs r0, #2
80003e6: 443c add r4, r7
80003e8: eba4 040e sub.w r4, r4, lr
80003ec: fa1f fe83 uxth.w lr, r3
80003f0: fbb4 f3f9 udiv r3, r4, r9
80003f4: fb09 4413 mls r4, r9, r3, r4
80003f8: ea4e 4404 orr.w r4, lr, r4, lsl #16
80003fc: fb03 fc0c mul.w ip, r3, ip
8000400: 45a4 cmp ip, r4
8000402: d908 bls.n 8000416 <__udivmoddi4+0x1ce>
8000404: 193c adds r4, r7, r4
8000406: f103 3eff add.w lr, r3, #4294967295
800040a: f080 8082 bcs.w 8000512 <__udivmoddi4+0x2ca>
800040e: 45a4 cmp ip, r4
8000410: d97f bls.n 8000512 <__udivmoddi4+0x2ca>
8000412: 3b02 subs r3, #2
8000414: 443c add r4, r7
8000416: ea43 4000 orr.w r0, r3, r0, lsl #16
800041a: eba4 040c sub.w r4, r4, ip
800041e: fba0 ec02 umull lr, ip, r0, r2
8000422: 4564 cmp r4, ip
8000424: 4673 mov r3, lr
8000426: 46e1 mov r9, ip
8000428: d362 bcc.n 80004f0 <__udivmoddi4+0x2a8>
800042a: d05f beq.n 80004ec <__udivmoddi4+0x2a4>
800042c: b15d cbz r5, 8000446 <__udivmoddi4+0x1fe>
800042e: ebb8 0203 subs.w r2, r8, r3
8000432: eb64 0409 sbc.w r4, r4, r9
8000436: fa04 f606 lsl.w r6, r4, r6
800043a: fa22 f301 lsr.w r3, r2, r1
800043e: 431e orrs r6, r3
8000440: 40cc lsrs r4, r1
8000442: e9c5 6400 strd r6, r4, [r5]
8000446: 2100 movs r1, #0
8000448: e74f b.n 80002ea <__udivmoddi4+0xa2>
800044a: fbb1 fcf2 udiv ip, r1, r2
800044e: 0c01 lsrs r1, r0, #16
8000450: ea41 410e orr.w r1, r1, lr, lsl #16
8000454: b280 uxth r0, r0
8000456: ea40 4201 orr.w r2, r0, r1, lsl #16
800045a: 463b mov r3, r7
800045c: 4638 mov r0, r7
800045e: 463c mov r4, r7
8000460: 46b8 mov r8, r7
8000462: 46be mov lr, r7
8000464: 2620 movs r6, #32
8000466: fbb1 f1f7 udiv r1, r1, r7
800046a: eba2 0208 sub.w r2, r2, r8
800046e: ea41 410c orr.w r1, r1, ip, lsl #16
8000472: e766 b.n 8000342 <__udivmoddi4+0xfa>
8000474: 4601 mov r1, r0
8000476: e718 b.n 80002aa <__udivmoddi4+0x62>
8000478: 4610 mov r0, r2
800047a: e72c b.n 80002d6 <__udivmoddi4+0x8e>
800047c: f1c6 0220 rsb r2, r6, #32
8000480: fa2e f302 lsr.w r3, lr, r2
8000484: 40b7 lsls r7, r6
8000486: 40b1 lsls r1, r6
8000488: fa20 f202 lsr.w r2, r0, r2
800048c: ea4f 4e17 mov.w lr, r7, lsr #16
8000490: 430a orrs r2, r1
8000492: fbb3 f8fe udiv r8, r3, lr
8000496: b2bc uxth r4, r7
8000498: fb0e 3318 mls r3, lr, r8, r3
800049c: 0c11 lsrs r1, r2, #16
800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
80004a2: fb08 f904 mul.w r9, r8, r4
80004a6: 40b0 lsls r0, r6
80004a8: 4589 cmp r9, r1
80004aa: ea4f 4310 mov.w r3, r0, lsr #16
80004ae: b280 uxth r0, r0
80004b0: d93e bls.n 8000530 <__udivmoddi4+0x2e8>
80004b2: 1879 adds r1, r7, r1
80004b4: f108 3cff add.w ip, r8, #4294967295
80004b8: d201 bcs.n 80004be <__udivmoddi4+0x276>
80004ba: 4589 cmp r9, r1
80004bc: d81f bhi.n 80004fe <__udivmoddi4+0x2b6>
80004be: eba1 0109 sub.w r1, r1, r9
80004c2: fbb1 f9fe udiv r9, r1, lr
80004c6: fb09 f804 mul.w r8, r9, r4
80004ca: fb0e 1119 mls r1, lr, r9, r1
80004ce: b292 uxth r2, r2
80004d0: ea42 4201 orr.w r2, r2, r1, lsl #16
80004d4: 4542 cmp r2, r8
80004d6: d229 bcs.n 800052c <__udivmoddi4+0x2e4>
80004d8: 18ba adds r2, r7, r2
80004da: f109 31ff add.w r1, r9, #4294967295
80004de: d2c4 bcs.n 800046a <__udivmoddi4+0x222>
80004e0: 4542 cmp r2, r8
80004e2: d2c2 bcs.n 800046a <__udivmoddi4+0x222>
80004e4: f1a9 0102 sub.w r1, r9, #2
80004e8: 443a add r2, r7
80004ea: e7be b.n 800046a <__udivmoddi4+0x222>
80004ec: 45f0 cmp r8, lr
80004ee: d29d bcs.n 800042c <__udivmoddi4+0x1e4>
80004f0: ebbe 0302 subs.w r3, lr, r2
80004f4: eb6c 0c07 sbc.w ip, ip, r7
80004f8: 3801 subs r0, #1
80004fa: 46e1 mov r9, ip
80004fc: e796 b.n 800042c <__udivmoddi4+0x1e4>
80004fe: eba7 0909 sub.w r9, r7, r9
8000502: 4449 add r1, r9
8000504: f1a8 0c02 sub.w ip, r8, #2
8000508: fbb1 f9fe udiv r9, r1, lr
800050c: fb09 f804 mul.w r8, r9, r4
8000510: e7db b.n 80004ca <__udivmoddi4+0x282>
8000512: 4673 mov r3, lr
8000514: e77f b.n 8000416 <__udivmoddi4+0x1ce>
8000516: 4650 mov r0, sl
8000518: e766 b.n 80003e8 <__udivmoddi4+0x1a0>
800051a: 4608 mov r0, r1
800051c: e6fd b.n 800031a <__udivmoddi4+0xd2>
800051e: 443b add r3, r7
8000520: 3a02 subs r2, #2
8000522: e733 b.n 800038c <__udivmoddi4+0x144>
8000524: f1ac 0c02 sub.w ip, ip, #2
8000528: 443b add r3, r7
800052a: e71c b.n 8000366 <__udivmoddi4+0x11e>
800052c: 4649 mov r1, r9
800052e: e79c b.n 800046a <__udivmoddi4+0x222>
8000530: eba1 0109 sub.w r1, r1, r9
8000534: 46c4 mov ip, r8
8000536: fbb1 f9fe udiv r9, r1, lr
800053a: fb09 f804 mul.w r8, r9, r4
800053e: e7c4 b.n 80004ca <__udivmoddi4+0x282>
08000540 <__aeabi_idiv0>:
8000540: 4770 bx lr
8000542: bf00 nop
08000544 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000544: b580 push {r7, lr}
8000546: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000548: f001 f8f3 bl 8001732 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800054c: f000 f938 bl 80007c0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000550: f000 fb74 bl 8000c3c <MX_GPIO_Init>
MX_USART2_UART_Init();
8000554: f000 fb26 bl 8000ba4 <MX_USART2_UART_Init>
MX_ADC2_Init();
8000558: f000 f9f6 bl 8000948 <MX_ADC2_Init>
MX_TIM2_Init();
800055c: f000 fa5a bl 8000a14 <MX_TIM2_Init>
MX_ADC1_Init();
8000560: f000 f97a bl 8000858 <MX_ADC1_Init>
MX_TIM16_Init();
8000564: f000 faa4 bl 8000ab0 <MX_TIM16_Init>
/* USER CODE BEGIN 2 */
/*Configure GPIO pin output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000568: 2200 movs r2, #0
800056a: f44f 7180 mov.w r1, #256 @ 0x100
800056e: 4878 ldr r0, [pc, #480] @ (8000750 <main+0x20c>)
8000570: f003 f960 bl 8003834 <HAL_GPIO_WritePin>
/* Run ADC calibration */
HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
8000574: 217f movs r1, #127 @ 0x7f
8000576: 4877 ldr r0, [pc, #476] @ (8000754 <main+0x210>)
8000578: f002 fd04 bl 8002f84 <HAL_ADCEx_Calibration_Start>
HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED);
800057c: 217f movs r1, #127 @ 0x7f
800057e: 4876 ldr r0, [pc, #472] @ (8000758 <main+0x214>)
8000580: f002 fd00 bl 8002f84 <HAL_ADCEx_Calibration_Start>
/* Setup UART interrupts */
/* Make sure UART Rx counters and flags are reset */
rx_counter = 0x00;
8000584: 4b75 ldr r3, [pc, #468] @ (800075c <main+0x218>)
8000586: 2200 movs r2, #0
8000588: 701a strb r2, [r3, #0]
rx_len = 0x00;
800058a: 4b75 ldr r3, [pc, #468] @ (8000760 <main+0x21c>)
800058c: 2200 movs r2, #0
800058e: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
8000590: 4b74 ldr r3, [pc, #464] @ (8000764 <main+0x220>)
8000592: 2200 movs r2, #0
8000594: 701a strb r2, [r3, #0]
adc_task_flag = 0x00;
8000596: 4b74 ldr r3, [pc, #464] @ (8000768 <main+0x224>)
8000598: 2200 movs r2, #0
800059a: 701a strb r2, [r3, #0]
pwm_value = 0x0000;
800059c: 4b73 ldr r3, [pc, #460] @ (800076c <main+0x228>)
800059e: 2200 movs r2, #0
80005a0: 801a strh r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
80005a2: 2201 movs r2, #1
80005a4: 4972 ldr r1, [pc, #456] @ (8000770 <main+0x22c>)
80005a6: 4873 ldr r0, [pc, #460] @ (8000774 <main+0x230>)
80005a8: f005 fcfc bl 8005fa4 <HAL_UART_Receive_IT>
/* Get real VDDA value */
vdd_ref = get_actual_vdda(&hadc1);
80005ac: 4869 ldr r0, [pc, #420] @ (8000754 <main+0x210>)
80005ae: f000 fc15 bl 8000ddc <get_actual_vdda>
80005b2: eef0 7a40 vmov.f32 s15, s0
80005b6: 4b70 ldr r3, [pc, #448] @ (8000778 <main+0x234>)
80005b8: edc3 7a00 vstr s15, [r3]
/* Start output PWM at zero */
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
80005bc: 4b6f ldr r3, [pc, #444] @ (800077c <main+0x238>)
80005be: 681b ldr r3, [r3, #0]
80005c0: 2200 movs r2, #0
80005c2: 635a str r2, [r3, #52] @ 0x34
HAL_TIM_PWM_Start(&htim16, TIM_CHANNEL_1);
80005c4: 2100 movs r1, #0
80005c6: 486d ldr r0, [pc, #436] @ (800077c <main+0x238>)
80005c8: f004 f9d6 bl 8004978 <HAL_TIM_PWM_Start>
ADC_Filter_Init(&v_out_filter);
80005cc: 486c ldr r0, [pc, #432] @ (8000780 <main+0x23c>)
80005ce: f000 fb75 bl 8000cbc <ADC_Filter_Init>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
if (adc_task_flag == 0xff)
80005d2: 4b65 ldr r3, [pc, #404] @ (8000768 <main+0x224>)
80005d4: 781b ldrb r3, [r3, #0]
80005d6: 2bff cmp r3, #255 @ 0xff
80005d8: d15f bne.n 800069a <main+0x156>
{
adc_task_flag = 0x00;
80005da: 4b63 ldr r3, [pc, #396] @ (8000768 <main+0x224>)
80005dc: 2200 movs r2, #0
80005de: 701a strb r2, [r3, #0]
tx_len = 0x04;
80005e0: 4b68 ldr r3, [pc, #416] @ (8000784 <main+0x240>)
80005e2: 2204 movs r2, #4
80005e4: 701a strb r2, [r3, #0]
tx_buffer[0] = IN_SYNC_BYTE_1;
80005e6: 4b68 ldr r3, [pc, #416] @ (8000788 <main+0x244>)
80005e8: 2241 movs r2, #65 @ 0x41
80005ea: 701a strb r2, [r3, #0]
tx_buffer[1] = IN_SYNC_BYTE_2;
80005ec: 4b66 ldr r3, [pc, #408] @ (8000788 <main+0x244>)
80005ee: 2252 movs r2, #82 @ 0x52
80005f0: 705a strb r2, [r3, #1]
tx_buffer[2] = tx_len;
80005f2: 4b64 ldr r3, [pc, #400] @ (8000784 <main+0x240>)
80005f4: 781a ldrb r2, [r3, #0]
80005f6: 4b64 ldr r3, [pc, #400] @ (8000788 <main+0x244>)
80005f8: 709a strb r2, [r3, #2]
tx_buffer[3] = (uint8_t)((vout_adj_uint >> 24) & 0xFF);
80005fa: 4b64 ldr r3, [pc, #400] @ (800078c <main+0x248>)
80005fc: 681b ldr r3, [r3, #0]
80005fe: 0e1b lsrs r3, r3, #24
8000600: b2da uxtb r2, r3
8000602: 4b61 ldr r3, [pc, #388] @ (8000788 <main+0x244>)
8000604: 70da strb r2, [r3, #3]
tx_buffer[4] = (uint8_t)((vout_adj_uint >> 16) & 0xFF);
8000606: 4b61 ldr r3, [pc, #388] @ (800078c <main+0x248>)
8000608: 681b ldr r3, [r3, #0]
800060a: 0c1b lsrs r3, r3, #16
800060c: b2da uxtb r2, r3
800060e: 4b5e ldr r3, [pc, #376] @ (8000788 <main+0x244>)
8000610: 711a strb r2, [r3, #4]
tx_buffer[5] = (uint8_t)((vout_adj_uint >> 8) & 0xFF);
8000612: 4b5e ldr r3, [pc, #376] @ (800078c <main+0x248>)
8000614: 681b ldr r3, [r3, #0]
8000616: 0a1b lsrs r3, r3, #8
8000618: b2da uxtb r2, r3
800061a: 4b5b ldr r3, [pc, #364] @ (8000788 <main+0x244>)
800061c: 715a strb r2, [r3, #5]
tx_buffer[6] = (uint8_t)(vout_adj_uint & 0xFF);
800061e: 4b5b ldr r3, [pc, #364] @ (800078c <main+0x248>)
8000620: 681b ldr r3, [r3, #0]
8000622: b2da uxtb r2, r3
8000624: 4b58 ldr r3, [pc, #352] @ (8000788 <main+0x244>)
8000626: 719a strb r2, [r3, #6]
/* Need to apply checksum to all data bits */
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8000628: 4b59 ldr r3, [pc, #356] @ (8000790 <main+0x24c>)
800062a: 2200 movs r2, #0
800062c: 701a strb r2, [r3, #0]
800062e: e011 b.n 8000654 <main+0x110>
{
tx_checksum += tx_buffer[tx_len_counter + 3];
8000630: 4b57 ldr r3, [pc, #348] @ (8000790 <main+0x24c>)
8000632: 781b ldrb r3, [r3, #0]
8000634: 3303 adds r3, #3
8000636: 4a54 ldr r2, [pc, #336] @ (8000788 <main+0x244>)
8000638: 5cd3 ldrb r3, [r2, r3]
800063a: 461a mov r2, r3
800063c: 4b55 ldr r3, [pc, #340] @ (8000794 <main+0x250>)
800063e: 881b ldrh r3, [r3, #0]
8000640: 4413 add r3, r2
8000642: b29a uxth r2, r3
8000644: 4b53 ldr r3, [pc, #332] @ (8000794 <main+0x250>)
8000646: 801a strh r2, [r3, #0]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8000648: 4b51 ldr r3, [pc, #324] @ (8000790 <main+0x24c>)
800064a: 781b ldrb r3, [r3, #0]
800064c: 3301 adds r3, #1
800064e: b2da uxtb r2, r3
8000650: 4b4f ldr r3, [pc, #316] @ (8000790 <main+0x24c>)
8000652: 701a strb r2, [r3, #0]
8000654: 4b4e ldr r3, [pc, #312] @ (8000790 <main+0x24c>)
8000656: 781a ldrb r2, [r3, #0]
8000658: 4b4a ldr r3, [pc, #296] @ (8000784 <main+0x240>)
800065a: 781b ldrb r3, [r3, #0]
800065c: 429a cmp r2, r3
800065e: d3e7 bcc.n 8000630 <main+0xec>
}
tx_checksum = ~tx_checksum;
8000660: 4b4c ldr r3, [pc, #304] @ (8000794 <main+0x250>)
8000662: 881b ldrh r3, [r3, #0]
8000664: 43db mvns r3, r3
8000666: b29a uxth r2, r3
8000668: 4b4a ldr r3, [pc, #296] @ (8000794 <main+0x250>)
800066a: 801a strh r2, [r3, #0]
tx_buffer[7] = (uint8_t)((tx_checksum >> 8) & 0xFF);
800066c: 4b49 ldr r3, [pc, #292] @ (8000794 <main+0x250>)
800066e: 881b ldrh r3, [r3, #0]
8000670: 0a1b lsrs r3, r3, #8
8000672: b29b uxth r3, r3
8000674: b2da uxtb r2, r3
8000676: 4b44 ldr r3, [pc, #272] @ (8000788 <main+0x244>)
8000678: 71da strb r2, [r3, #7]
tx_buffer[8] = (uint8_t)(tx_checksum & 0xFF);
800067a: 4b46 ldr r3, [pc, #280] @ (8000794 <main+0x250>)
800067c: 881b ldrh r3, [r3, #0]
800067e: b2da uxtb r2, r3
8000680: 4b41 ldr r3, [pc, #260] @ (8000788 <main+0x244>)
8000682: 721a strb r2, [r3, #8]
tx_len = 0x13;
8000684: 4b3f ldr r3, [pc, #252] @ (8000784 <main+0x240>)
8000686: 2213 movs r2, #19
8000688: 701a strb r2, [r3, #0]
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
800068a: 4b3e ldr r3, [pc, #248] @ (8000784 <main+0x240>)
800068c: 781b ldrb r3, [r3, #0]
800068e: 461a mov r2, r3
8000690: 2364 movs r3, #100 @ 0x64
8000692: 493d ldr r1, [pc, #244] @ (8000788 <main+0x244>)
8000694: 4837 ldr r0, [pc, #220] @ (8000774 <main+0x230>)
8000696: f005 fbf7 bl 8005e88 <HAL_UART_Transmit>
}
if (serial_number_flag == 0xff)
800069a: 4b3f ldr r3, [pc, #252] @ (8000798 <main+0x254>)
800069c: 781b ldrb r3, [r3, #0]
800069e: 2bff cmp r3, #255 @ 0xff
80006a0: d104 bne.n 80006ac <main+0x168>
{
serial_number_flag = 0x00;
80006a2: 4b3d ldr r3, [pc, #244] @ (8000798 <main+0x254>)
80006a4: 2200 movs r2, #0
80006a6: 701a strb r2, [r3, #0]
serial_number_task ();
80006a8: f000 fbd4 bl 8000e54 <serial_number_task>
}
if (vset_task_flag == 0xff)
80006ac: 4b3b ldr r3, [pc, #236] @ (800079c <main+0x258>)
80006ae: 781b ldrb r3, [r3, #0]
80006b0: 2bff cmp r3, #255 @ 0xff
80006b2: d143 bne.n 800073c <main+0x1f8>
{
adc_task();
80006b4: f000 fc66 bl 8000f84 <adc_task>
filtered_adc = ADC_Filter_Update(&v_out_filter, vout_adc_val);
80006b8: 4b39 ldr r3, [pc, #228] @ (80007a0 <main+0x25c>)
80006ba: 681b ldr r3, [r3, #0]
80006bc: 4619 mov r1, r3
80006be: 4830 ldr r0, [pc, #192] @ (8000780 <main+0x23c>)
80006c0: f000 fb12 bl 8000ce8 <ADC_Filter_Update>
80006c4: 4603 mov r3, r0
80006c6: 4a37 ldr r2, [pc, #220] @ (80007a4 <main+0x260>)
80006c8: 6013 str r3, [r2, #0]
vout = ((float)filtered_adc / 4095.0f) * vdd_ref;
80006ca: 4b36 ldr r3, [pc, #216] @ (80007a4 <main+0x260>)
80006cc: 681b ldr r3, [r3, #0]
80006ce: ee07 3a90 vmov s15, r3
80006d2: eef8 7a67 vcvt.f32.u32 s15, s15
80006d6: eddf 6a34 vldr s13, [pc, #208] @ 80007a8 <main+0x264>
80006da: ee87 7aa6 vdiv.f32 s14, s15, s13
80006de: 4b26 ldr r3, [pc, #152] @ (8000778 <main+0x234>)
80006e0: edd3 7a00 vldr s15, [r3]
80006e4: ee67 7a27 vmul.f32 s15, s14, s15
80006e8: 4b30 ldr r3, [pc, #192] @ (80007ac <main+0x268>)
80006ea: edc3 7a00 vstr s15, [r3]
vout_adj = vout * 10.9f;
80006ee: 4b2f ldr r3, [pc, #188] @ (80007ac <main+0x268>)
80006f0: edd3 7a00 vldr s15, [r3]
80006f4: ed9f 7a2e vldr s14, [pc, #184] @ 80007b0 <main+0x26c>
80006f8: ee67 7a87 vmul.f32 s15, s15, s14
80006fc: 4b2d ldr r3, [pc, #180] @ (80007b4 <main+0x270>)
80006fe: edc3 7a00 vstr s15, [r3]
vout_adj_uint = (uint32_t)vout_adj;
8000702: 4b2c ldr r3, [pc, #176] @ (80007b4 <main+0x270>)
8000704: edd3 7a00 vldr s15, [r3]
8000708: eefc 7ae7 vcvt.u32.f32 s15, s15
800070c: ee17 2a90 vmov r2, s15
8000710: 4b1e ldr r3, [pc, #120] @ (800078c <main+0x248>)
8000712: 601a str r2, [r3, #0]
pwm_value_store = update_pwm(vout_adj_uint);
8000714: 4b1d ldr r3, [pc, #116] @ (800078c <main+0x248>)
8000716: 681b ldr r3, [r3, #0]
8000718: 4618 mov r0, r3
800071a: f000 fb23 bl 8000d64 <update_pwm>
800071e: 4603 mov r3, r0
8000720: 461a mov r2, r3
8000722: 4b25 ldr r3, [pc, #148] @ (80007b8 <main+0x274>)
8000724: 601a str r2, [r3, #0]
pwm_value = (uint16_t)pwm_value_store;
8000726: 4b24 ldr r3, [pc, #144] @ (80007b8 <main+0x274>)
8000728: 681b ldr r3, [r3, #0]
800072a: b29a uxth r2, r3
800072c: 4b0f ldr r3, [pc, #60] @ (800076c <main+0x228>)
800072e: 801a strh r2, [r3, #0]
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, pwm_value);
8000730: 4b0e ldr r3, [pc, #56] @ (800076c <main+0x228>)
8000732: 881a ldrh r2, [r3, #0]
8000734: 4b11 ldr r3, [pc, #68] @ (800077c <main+0x238>)
8000736: 681b ldr r3, [r3, #0]
8000738: 635a str r2, [r3, #52] @ 0x34
800073a: e74a b.n 80005d2 <main+0x8e>
}
else
{
if (solid_state_flag == 0x00)
800073c: 4b1f ldr r3, [pc, #124] @ (80007bc <main+0x278>)
800073e: 781b ldrb r3, [r3, #0]
8000740: 2b00 cmp r3, #0
8000742: f47f af46 bne.w 80005d2 <main+0x8e>
{
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
8000746: 4b0d ldr r3, [pc, #52] @ (800077c <main+0x238>)
8000748: 681b ldr r3, [r3, #0]
800074a: 2200 movs r2, #0
800074c: 635a str r2, [r3, #52] @ 0x34
if (adc_task_flag == 0xff)
800074e: e740 b.n 80005d2 <main+0x8e>
8000750: 48000400 .word 0x48000400
8000754: 20000044 .word 0x20000044
8000758: 200000b0 .word 0x200000b0
800075c: 20000292 .word 0x20000292
8000760: 20000293 .word 0x20000293
8000764: 20000294 .word 0x20000294
8000768: 200002a0 .word 0x200002a0
800076c: 200002ae .word 0x200002ae
8000770: 2000024c .word 0x2000024c
8000774: 200001b4 .word 0x200001b4
8000778: 200002a4 .word 0x200002a4
800077c: 20000168 .word 0x20000168
8000780: 200002d4 .word 0x200002d4
8000784: 20000290 .word 0x20000290
8000788: 20000270 .word 0x20000270
800078c: 200002c4 .word 0x200002c4
8000790: 20000291 .word 0x20000291
8000794: 20000298 .word 0x20000298
8000798: 200002ad .word 0x200002ad
800079c: 200002ac .word 0x200002ac
80007a0: 200002b4 .word 0x200002b4
80007a4: 200002b8 .word 0x200002b8
80007a8: 457ff000 .word 0x457ff000
80007ac: 200002bc .word 0x200002bc
80007b0: 412e6666 .word 0x412e6666
80007b4: 200002c0 .word 0x200002c0
80007b8: 200002b0 .word 0x200002b0
80007bc: 200002d0 .word 0x200002d0
080007c0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80007c0: b580 push {r7, lr}
80007c2: b094 sub sp, #80 @ 0x50
80007c4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80007c6: f107 0318 add.w r3, r7, #24
80007ca: 2238 movs r2, #56 @ 0x38
80007cc: 2100 movs r1, #0
80007ce: 4618 mov r0, r3
80007d0: f007 fc1a bl 8008008 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80007d4: 1d3b adds r3, r7, #4
80007d6: 2200 movs r2, #0
80007d8: 601a str r2, [r3, #0]
80007da: 605a str r2, [r3, #4]
80007dc: 609a str r2, [r3, #8]
80007de: 60da str r2, [r3, #12]
80007e0: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
80007e2: f44f 7000 mov.w r0, #512 @ 0x200
80007e6: f003 f83d bl 8003864 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80007ea: 2302 movs r3, #2
80007ec: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80007ee: f44f 7380 mov.w r3, #256 @ 0x100
80007f2: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80007f4: 2340 movs r3, #64 @ 0x40
80007f6: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80007f8: 2302 movs r3, #2
80007fa: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80007fc: 2302 movs r3, #2
80007fe: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
8000800: 2301 movs r3, #1
8000802: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLN = 16;
8000804: 2310 movs r3, #16
8000806: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000808: 2302 movs r3, #2
800080a: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
800080c: 2302 movs r3, #2
800080e: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
8000810: 2302 movs r3, #2
8000812: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000814: f107 0318 add.w r3, r7, #24
8000818: 4618 mov r0, r3
800081a: f003 f8d7 bl 80039cc <HAL_RCC_OscConfig>
800081e: 4603 mov r3, r0
8000820: 2b00 cmp r3, #0
8000822: d001 beq.n 8000828 <SystemClock_Config+0x68>
{
Error_Handler();
8000824: f000 fd80 bl 8001328 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000828: 230f movs r3, #15
800082a: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800082c: 2303 movs r3, #3
800082e: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000830: 2300 movs r3, #0
8000832: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000834: 2300 movs r3, #0
8000836: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000838: 2300 movs r3, #0
800083a: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
800083c: 1d3b adds r3, r7, #4
800083e: 2104 movs r1, #4
8000840: 4618 mov r0, r3
8000842: f003 fbd5 bl 8003ff0 <HAL_RCC_ClockConfig>
8000846: 4603 mov r3, r0
8000848: 2b00 cmp r3, #0
800084a: d001 beq.n 8000850 <SystemClock_Config+0x90>
{
Error_Handler();
800084c: f000 fd6c bl 8001328 <Error_Handler>
}
}
8000850: bf00 nop
8000852: 3750 adds r7, #80 @ 0x50
8000854: 46bd mov sp, r7
8000856: bd80 pop {r7, pc}
08000858 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000858: b580 push {r7, lr}
800085a: b08c sub sp, #48 @ 0x30
800085c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
800085e: f107 0324 add.w r3, r7, #36 @ 0x24
8000862: 2200 movs r2, #0
8000864: 601a str r2, [r3, #0]
8000866: 605a str r2, [r3, #4]
8000868: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
800086a: 1d3b adds r3, r7, #4
800086c: 2220 movs r2, #32
800086e: 2100 movs r1, #0
8000870: 4618 mov r0, r3
8000872: f007 fbc9 bl 8008008 <memset>
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
8000876: 4b32 ldr r3, [pc, #200] @ (8000940 <MX_ADC1_Init+0xe8>)
8000878: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
800087c: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
800087e: 4b30 ldr r3, [pc, #192] @ (8000940 <MX_ADC1_Init+0xe8>)
8000880: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000884: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000886: 4b2e ldr r3, [pc, #184] @ (8000940 <MX_ADC1_Init+0xe8>)
8000888: 2200 movs r2, #0
800088a: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800088c: 4b2c ldr r3, [pc, #176] @ (8000940 <MX_ADC1_Init+0xe8>)
800088e: 2200 movs r2, #0
8000890: 60da str r2, [r3, #12]
hadc1.Init.GainCompensation = 0;
8000892: 4b2b ldr r3, [pc, #172] @ (8000940 <MX_ADC1_Init+0xe8>)
8000894: 2200 movs r2, #0
8000896: 611a str r2, [r3, #16]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000898: 4b29 ldr r3, [pc, #164] @ (8000940 <MX_ADC1_Init+0xe8>)
800089a: 2200 movs r2, #0
800089c: 615a str r2, [r3, #20]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800089e: 4b28 ldr r3, [pc, #160] @ (8000940 <MX_ADC1_Init+0xe8>)
80008a0: 2204 movs r2, #4
80008a2: 619a str r2, [r3, #24]
hadc1.Init.LowPowerAutoWait = DISABLE;
80008a4: 4b26 ldr r3, [pc, #152] @ (8000940 <MX_ADC1_Init+0xe8>)
80008a6: 2200 movs r2, #0
80008a8: 771a strb r2, [r3, #28]
hadc1.Init.ContinuousConvMode = DISABLE;
80008aa: 4b25 ldr r3, [pc, #148] @ (8000940 <MX_ADC1_Init+0xe8>)
80008ac: 2200 movs r2, #0
80008ae: 775a strb r2, [r3, #29]
hadc1.Init.NbrOfConversion = 1;
80008b0: 4b23 ldr r3, [pc, #140] @ (8000940 <MX_ADC1_Init+0xe8>)
80008b2: 2201 movs r2, #1
80008b4: 621a str r2, [r3, #32]
hadc1.Init.DiscontinuousConvMode = DISABLE;
80008b6: 4b22 ldr r3, [pc, #136] @ (8000940 <MX_ADC1_Init+0xe8>)
80008b8: 2200 movs r2, #0
80008ba: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80008be: 4b20 ldr r3, [pc, #128] @ (8000940 <MX_ADC1_Init+0xe8>)
80008c0: 2200 movs r2, #0
80008c2: 62da str r2, [r3, #44] @ 0x2c
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80008c4: 4b1e ldr r3, [pc, #120] @ (8000940 <MX_ADC1_Init+0xe8>)
80008c6: 2200 movs r2, #0
80008c8: 631a str r2, [r3, #48] @ 0x30
hadc1.Init.DMAContinuousRequests = DISABLE;
80008ca: 4b1d ldr r3, [pc, #116] @ (8000940 <MX_ADC1_Init+0xe8>)
80008cc: 2200 movs r2, #0
80008ce: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
80008d2: 4b1b ldr r3, [pc, #108] @ (8000940 <MX_ADC1_Init+0xe8>)
80008d4: 2200 movs r2, #0
80008d6: 63da str r2, [r3, #60] @ 0x3c
hadc1.Init.OversamplingMode = DISABLE;
80008d8: 4b19 ldr r3, [pc, #100] @ (8000940 <MX_ADC1_Init+0xe8>)
80008da: 2200 movs r2, #0
80008dc: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80008e0: 4817 ldr r0, [pc, #92] @ (8000940 <MX_ADC1_Init+0xe8>)
80008e2: f001 fa11 bl 8001d08 <HAL_ADC_Init>
80008e6: 4603 mov r3, r0
80008e8: 2b00 cmp r3, #0
80008ea: d001 beq.n 80008f0 <MX_ADC1_Init+0x98>
{
Error_Handler();
80008ec: f000 fd1c bl 8001328 <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
80008f0: 2300 movs r3, #0
80008f2: 627b str r3, [r7, #36] @ 0x24
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
80008f4: f107 0324 add.w r3, r7, #36 @ 0x24
80008f8: 4619 mov r1, r3
80008fa: 4811 ldr r0, [pc, #68] @ (8000940 <MX_ADC1_Init+0xe8>)
80008fc: f002 fba4 bl 8003048 <HAL_ADCEx_MultiModeConfigChannel>
8000900: 4603 mov r3, r0
8000902: 2b00 cmp r3, #0
8000904: d001 beq.n 800090a <MX_ADC1_Init+0xb2>
{
Error_Handler();
8000906: f000 fd0f bl 8001328 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_VREFINT;
800090a: 4b0e ldr r3, [pc, #56] @ (8000944 <MX_ADC1_Init+0xec>)
800090c: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
800090e: 2306 movs r3, #6
8000910: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
8000912: 2307 movs r3, #7
8000914: 60fb str r3, [r7, #12]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000916: 237f movs r3, #127 @ 0x7f
8000918: 613b str r3, [r7, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
800091a: 2304 movs r3, #4
800091c: 617b str r3, [r7, #20]
sConfig.Offset = 0;
800091e: 2300 movs r3, #0
8000920: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000922: 1d3b adds r3, r7, #4
8000924: 4619 mov r1, r3
8000926: 4806 ldr r0, [pc, #24] @ (8000940 <MX_ADC1_Init+0xe8>)
8000928: f001 fd48 bl 80023bc <HAL_ADC_ConfigChannel>
800092c: 4603 mov r3, r0
800092e: 2b00 cmp r3, #0
8000930: d001 beq.n 8000936 <MX_ADC1_Init+0xde>
{
Error_Handler();
8000932: f000 fcf9 bl 8001328 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000936: bf00 nop
8000938: 3730 adds r7, #48 @ 0x30
800093a: 46bd mov sp, r7
800093c: bd80 pop {r7, pc}
800093e: bf00 nop
8000940: 20000044 .word 0x20000044
8000944: cb840000 .word 0xcb840000
08000948 <MX_ADC2_Init>:
* @brief ADC2 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC2_Init(void)
{
8000948: b580 push {r7, lr}
800094a: b088 sub sp, #32
800094c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800094e: 463b mov r3, r7
8000950: 2220 movs r2, #32
8000952: 2100 movs r1, #0
8000954: 4618 mov r0, r3
8000956: f007 fb57 bl 8008008 <memset>
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
800095a: 4b2b ldr r3, [pc, #172] @ (8000a08 <MX_ADC2_Init+0xc0>)
800095c: 4a2b ldr r2, [pc, #172] @ (8000a0c <MX_ADC2_Init+0xc4>)
800095e: 601a str r2, [r3, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000960: 4b29 ldr r3, [pc, #164] @ (8000a08 <MX_ADC2_Init+0xc0>)
8000962: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000966: 605a str r2, [r3, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
8000968: 4b27 ldr r3, [pc, #156] @ (8000a08 <MX_ADC2_Init+0xc0>)
800096a: 2200 movs r2, #0
800096c: 609a str r2, [r3, #8]
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800096e: 4b26 ldr r3, [pc, #152] @ (8000a08 <MX_ADC2_Init+0xc0>)
8000970: 2200 movs r2, #0
8000972: 60da str r2, [r3, #12]
hadc2.Init.GainCompensation = 0;
8000974: 4b24 ldr r3, [pc, #144] @ (8000a08 <MX_ADC2_Init+0xc0>)
8000976: 2200 movs r2, #0
8000978: 611a str r2, [r3, #16]
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
800097a: 4b23 ldr r3, [pc, #140] @ (8000a08 <MX_ADC2_Init+0xc0>)
800097c: 2200 movs r2, #0
800097e: 615a str r2, [r3, #20]
hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000980: 4b21 ldr r3, [pc, #132] @ (8000a08 <MX_ADC2_Init+0xc0>)
8000982: 2204 movs r2, #4
8000984: 619a str r2, [r3, #24]
hadc2.Init.LowPowerAutoWait = DISABLE;
8000986: 4b20 ldr r3, [pc, #128] @ (8000a08 <MX_ADC2_Init+0xc0>)
8000988: 2200 movs r2, #0
800098a: 771a strb r2, [r3, #28]
hadc2.Init.ContinuousConvMode = DISABLE;
800098c: 4b1e ldr r3, [pc, #120] @ (8000a08 <MX_ADC2_Init+0xc0>)
800098e: 2200 movs r2, #0
8000990: 775a strb r2, [r3, #29]
hadc2.Init.NbrOfConversion = 1;
8000992: 4b1d ldr r3, [pc, #116] @ (8000a08 <MX_ADC2_Init+0xc0>)
8000994: 2201 movs r2, #1
8000996: 621a str r2, [r3, #32]
hadc2.Init.DiscontinuousConvMode = DISABLE;
8000998: 4b1b ldr r3, [pc, #108] @ (8000a08 <MX_ADC2_Init+0xc0>)
800099a: 2200 movs r2, #0
800099c: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80009a0: 4b19 ldr r3, [pc, #100] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009a2: 2200 movs r2, #0
80009a4: 62da str r2, [r3, #44] @ 0x2c
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80009a6: 4b18 ldr r3, [pc, #96] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009a8: 2200 movs r2, #0
80009aa: 631a str r2, [r3, #48] @ 0x30
hadc2.Init.DMAContinuousRequests = DISABLE;
80009ac: 4b16 ldr r3, [pc, #88] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009ae: 2200 movs r2, #0
80009b0: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
80009b4: 4b14 ldr r3, [pc, #80] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009b6: 2200 movs r2, #0
80009b8: 63da str r2, [r3, #60] @ 0x3c
hadc2.Init.OversamplingMode = DISABLE;
80009ba: 4b13 ldr r3, [pc, #76] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009bc: 2200 movs r2, #0
80009be: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc2) != HAL_OK)
80009c2: 4811 ldr r0, [pc, #68] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009c4: f001 f9a0 bl 8001d08 <HAL_ADC_Init>
80009c8: 4603 mov r3, r0
80009ca: 2b00 cmp r3, #0
80009cc: d001 beq.n 80009d2 <MX_ADC2_Init+0x8a>
{
Error_Handler();
80009ce: f000 fcab bl 8001328 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_3;
80009d2: 4b0f ldr r3, [pc, #60] @ (8000a10 <MX_ADC2_Init+0xc8>)
80009d4: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
80009d6: 2306 movs r3, #6
80009d8: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
80009da: 2307 movs r3, #7
80009dc: 60bb str r3, [r7, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
80009de: 237f movs r3, #127 @ 0x7f
80009e0: 60fb str r3, [r7, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
80009e2: 2304 movs r3, #4
80009e4: 613b str r3, [r7, #16]
sConfig.Offset = 0;
80009e6: 2300 movs r3, #0
80009e8: 617b str r3, [r7, #20]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
80009ea: 463b mov r3, r7
80009ec: 4619 mov r1, r3
80009ee: 4806 ldr r0, [pc, #24] @ (8000a08 <MX_ADC2_Init+0xc0>)
80009f0: f001 fce4 bl 80023bc <HAL_ADC_ConfigChannel>
80009f4: 4603 mov r3, r0
80009f6: 2b00 cmp r3, #0
80009f8: d001 beq.n 80009fe <MX_ADC2_Init+0xb6>
{
Error_Handler();
80009fa: f000 fc95 bl 8001328 <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
80009fe: bf00 nop
8000a00: 3720 adds r7, #32
8000a02: 46bd mov sp, r7
8000a04: bd80 pop {r7, pc}
8000a06: bf00 nop
8000a08: 200000b0 .word 0x200000b0
8000a0c: 50000100 .word 0x50000100
8000a10: 0c900008 .word 0x0c900008
08000a14 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8000a14: b580 push {r7, lr}
8000a16: b088 sub sp, #32
8000a18: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000a1a: f107 0310 add.w r3, r7, #16
8000a1e: 2200 movs r2, #0
8000a20: 601a str r2, [r3, #0]
8000a22: 605a str r2, [r3, #4]
8000a24: 609a str r2, [r3, #8]
8000a26: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000a28: 1d3b adds r3, r7, #4
8000a2a: 2200 movs r2, #0
8000a2c: 601a str r2, [r3, #0]
8000a2e: 605a str r2, [r3, #4]
8000a30: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8000a32: 4b1e ldr r3, [pc, #120] @ (8000aac <MX_TIM2_Init+0x98>)
8000a34: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8000a38: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 12800-1;
8000a3a: 4b1c ldr r3, [pc, #112] @ (8000aac <MX_TIM2_Init+0x98>)
8000a3c: f243 12ff movw r2, #12799 @ 0x31ff
8000a40: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8000a42: 4b1a ldr r3, [pc, #104] @ (8000aac <MX_TIM2_Init+0x98>)
8000a44: 2200 movs r2, #0
8000a46: 609a str r2, [r3, #8]
htim2.Init.Period = 99;
8000a48: 4b18 ldr r3, [pc, #96] @ (8000aac <MX_TIM2_Init+0x98>)
8000a4a: 2263 movs r2, #99 @ 0x63
8000a4c: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000a4e: 4b17 ldr r3, [pc, #92] @ (8000aac <MX_TIM2_Init+0x98>)
8000a50: 2200 movs r2, #0
8000a52: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000a54: 4b15 ldr r3, [pc, #84] @ (8000aac <MX_TIM2_Init+0x98>)
8000a56: 2200 movs r2, #0
8000a58: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8000a5a: 4814 ldr r0, [pc, #80] @ (8000aac <MX_TIM2_Init+0x98>)
8000a5c: f003 fed4 bl 8004808 <HAL_TIM_Base_Init>
8000a60: 4603 mov r3, r0
8000a62: 2b00 cmp r3, #0
8000a64: d001 beq.n 8000a6a <MX_TIM2_Init+0x56>
{
Error_Handler();
8000a66: f000 fc5f bl 8001328 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000a6a: f44f 5380 mov.w r3, #4096 @ 0x1000
8000a6e: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
8000a70: f107 0310 add.w r3, r7, #16
8000a74: 4619 mov r1, r3
8000a76: 480d ldr r0, [pc, #52] @ (8000aac <MX_TIM2_Init+0x98>)
8000a78: f004 fae2 bl 8005040 <HAL_TIM_ConfigClockSource>
8000a7c: 4603 mov r3, r0
8000a7e: 2b00 cmp r3, #0
8000a80: d001 beq.n 8000a86 <MX_TIM2_Init+0x72>
{
Error_Handler();
8000a82: f000 fc51 bl 8001328 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000a86: 2300 movs r3, #0
8000a88: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000a8a: 2300 movs r3, #0
8000a8c: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8000a8e: 1d3b adds r3, r7, #4
8000a90: 4619 mov r1, r3
8000a92: 4806 ldr r0, [pc, #24] @ (8000aac <MX_TIM2_Init+0x98>)
8000a94: f005 f854 bl 8005b40 <HAL_TIMEx_MasterConfigSynchronization>
8000a98: 4603 mov r3, r0
8000a9a: 2b00 cmp r3, #0
8000a9c: d001 beq.n 8000aa2 <MX_TIM2_Init+0x8e>
{
Error_Handler();
8000a9e: f000 fc43 bl 8001328 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
8000aa2: bf00 nop
8000aa4: 3720 adds r7, #32
8000aa6: 46bd mov sp, r7
8000aa8: bd80 pop {r7, pc}
8000aaa: bf00 nop
8000aac: 2000011c .word 0x2000011c
08000ab0 <MX_TIM16_Init>:
* @brief TIM16 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM16_Init(void)
{
8000ab0: b580 push {r7, lr}
8000ab2: b094 sub sp, #80 @ 0x50
8000ab4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM16_Init 0 */
/* USER CODE END TIM16_Init 0 */
TIM_OC_InitTypeDef sConfigOC = {0};
8000ab6: f107 0334 add.w r3, r7, #52 @ 0x34
8000aba: 2200 movs r2, #0
8000abc: 601a str r2, [r3, #0]
8000abe: 605a str r2, [r3, #4]
8000ac0: 609a str r2, [r3, #8]
8000ac2: 60da str r2, [r3, #12]
8000ac4: 611a str r2, [r3, #16]
8000ac6: 615a str r2, [r3, #20]
8000ac8: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8000aca: 463b mov r3, r7
8000acc: 2234 movs r2, #52 @ 0x34
8000ace: 2100 movs r1, #0
8000ad0: 4618 mov r0, r3
8000ad2: f007 fa99 bl 8008008 <memset>
/* USER CODE BEGIN TIM16_Init 1 */
/* USER CODE END TIM16_Init 1 */
htim16.Instance = TIM16;
8000ad6: 4b31 ldr r3, [pc, #196] @ (8000b9c <MX_TIM16_Init+0xec>)
8000ad8: 4a31 ldr r2, [pc, #196] @ (8000ba0 <MX_TIM16_Init+0xf0>)
8000ada: 601a str r2, [r3, #0]
htim16.Init.Prescaler = 1;
8000adc: 4b2f ldr r3, [pc, #188] @ (8000b9c <MX_TIM16_Init+0xec>)
8000ade: 2201 movs r2, #1
8000ae0: 605a str r2, [r3, #4]
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
8000ae2: 4b2e ldr r3, [pc, #184] @ (8000b9c <MX_TIM16_Init+0xec>)
8000ae4: 2200 movs r2, #0
8000ae6: 609a str r2, [r3, #8]
htim16.Init.Period = 63999;
8000ae8: 4b2c ldr r3, [pc, #176] @ (8000b9c <MX_TIM16_Init+0xec>)
8000aea: f64f 12ff movw r2, #63999 @ 0xf9ff
8000aee: 60da str r2, [r3, #12]
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000af0: 4b2a ldr r3, [pc, #168] @ (8000b9c <MX_TIM16_Init+0xec>)
8000af2: 2200 movs r2, #0
8000af4: 611a str r2, [r3, #16]
htim16.Init.RepetitionCounter = 0;
8000af6: 4b29 ldr r3, [pc, #164] @ (8000b9c <MX_TIM16_Init+0xec>)
8000af8: 2200 movs r2, #0
8000afa: 615a str r2, [r3, #20]
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000afc: 4b27 ldr r3, [pc, #156] @ (8000b9c <MX_TIM16_Init+0xec>)
8000afe: 2200 movs r2, #0
8000b00: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
8000b02: 4826 ldr r0, [pc, #152] @ (8000b9c <MX_TIM16_Init+0xec>)
8000b04: f003 fe80 bl 8004808 <HAL_TIM_Base_Init>
8000b08: 4603 mov r3, r0
8000b0a: 2b00 cmp r3, #0
8000b0c: d001 beq.n 8000b12 <MX_TIM16_Init+0x62>
{
Error_Handler();
8000b0e: f000 fc0b bl 8001328 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim16) != HAL_OK)
8000b12: 4822 ldr r0, [pc, #136] @ (8000b9c <MX_TIM16_Init+0xec>)
8000b14: f003 fecf bl 80048b6 <HAL_TIM_PWM_Init>
8000b18: 4603 mov r3, r0
8000b1a: 2b00 cmp r3, #0
8000b1c: d001 beq.n 8000b22 <MX_TIM16_Init+0x72>
{
Error_Handler();
8000b1e: f000 fc03 bl 8001328 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8000b22: 2360 movs r3, #96 @ 0x60
8000b24: 637b str r3, [r7, #52] @ 0x34
sConfigOC.Pulse = 0;
8000b26: 2300 movs r3, #0
8000b28: 63bb str r3, [r7, #56] @ 0x38
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000b2a: 2300 movs r3, #0
8000b2c: 63fb str r3, [r7, #60] @ 0x3c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
8000b2e: 2300 movs r3, #0
8000b30: 643b str r3, [r7, #64] @ 0x40
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000b32: 2300 movs r3, #0
8000b34: 647b str r3, [r7, #68] @ 0x44
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8000b36: 2300 movs r3, #0
8000b38: 64bb str r3, [r7, #72] @ 0x48
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8000b3a: 2300 movs r3, #0
8000b3c: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_TIM_PWM_ConfigChannel(&htim16, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8000b3e: f107 0334 add.w r3, r7, #52 @ 0x34
8000b42: 2200 movs r2, #0
8000b44: 4619 mov r1, r3
8000b46: 4815 ldr r0, [pc, #84] @ (8000b9c <MX_TIM16_Init+0xec>)
8000b48: f004 f966 bl 8004e18 <HAL_TIM_PWM_ConfigChannel>
8000b4c: 4603 mov r3, r0
8000b4e: 2b00 cmp r3, #0
8000b50: d001 beq.n 8000b56 <MX_TIM16_Init+0xa6>
{
Error_Handler();
8000b52: f000 fbe9 bl 8001328 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
8000b56: 2300 movs r3, #0
8000b58: 603b str r3, [r7, #0]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8000b5a: 2300 movs r3, #0
8000b5c: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8000b5e: 2300 movs r3, #0
8000b60: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.DeadTime = 0;
8000b62: 2300 movs r3, #0
8000b64: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8000b66: 2300 movs r3, #0
8000b68: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8000b6a: f44f 5300 mov.w r3, #8192 @ 0x2000
8000b6e: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakFilter = 0;
8000b70: 2300 movs r3, #0
8000b72: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8000b74: 2300 movs r3, #0
8000b76: 633b str r3, [r7, #48] @ 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim16, &sBreakDeadTimeConfig) != HAL_OK)
8000b78: 463b mov r3, r7
8000b7a: 4619 mov r1, r3
8000b7c: 4807 ldr r0, [pc, #28] @ (8000b9c <MX_TIM16_Init+0xec>)
8000b7e: f005 f861 bl 8005c44 <HAL_TIMEx_ConfigBreakDeadTime>
8000b82: 4603 mov r3, r0
8000b84: 2b00 cmp r3, #0
8000b86: d001 beq.n 8000b8c <MX_TIM16_Init+0xdc>
{
Error_Handler();
8000b88: f000 fbce bl 8001328 <Error_Handler>
}
/* USER CODE BEGIN TIM16_Init 2 */
/* USER CODE END TIM16_Init 2 */
HAL_TIM_MspPostInit(&htim16);
8000b8c: 4803 ldr r0, [pc, #12] @ (8000b9c <MX_TIM16_Init+0xec>)
8000b8e: f000 fcb9 bl 8001504 <HAL_TIM_MspPostInit>
}
8000b92: bf00 nop
8000b94: 3750 adds r7, #80 @ 0x50
8000b96: 46bd mov sp, r7
8000b98: bd80 pop {r7, pc}
8000b9a: bf00 nop
8000b9c: 20000168 .word 0x20000168
8000ba0: 40014400 .word 0x40014400
08000ba4 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
8000ba4: b580 push {r7, lr}
8000ba6: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8000ba8: 4b22 ldr r3, [pc, #136] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000baa: 4a23 ldr r2, [pc, #140] @ (8000c38 <MX_USART2_UART_Init+0x94>)
8000bac: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000bae: 4b21 ldr r3, [pc, #132] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bb0: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000bb4: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8000bb6: 4b1f ldr r3, [pc, #124] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bb8: 2200 movs r2, #0
8000bba: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000bbc: 4b1d ldr r3, [pc, #116] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bbe: 2200 movs r2, #0
8000bc0: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000bc2: 4b1c ldr r3, [pc, #112] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bc4: 2200 movs r2, #0
8000bc6: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000bc8: 4b1a ldr r3, [pc, #104] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bca: 220c movs r2, #12
8000bcc: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000bce: 4b19 ldr r3, [pc, #100] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bd0: 2200 movs r2, #0
8000bd2: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000bd4: 4b17 ldr r3, [pc, #92] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bd6: 2200 movs r2, #0
8000bd8: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000bda: 4b16 ldr r3, [pc, #88] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bdc: 2200 movs r2, #0
8000bde: 621a str r2, [r3, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8000be0: 4b14 ldr r3, [pc, #80] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000be2: 2200 movs r2, #0
8000be4: 625a str r2, [r3, #36] @ 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000be6: 4b13 ldr r3, [pc, #76] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000be8: 2200 movs r2, #0
8000bea: 629a str r2, [r3, #40] @ 0x28
if (HAL_UART_Init(&huart2) != HAL_OK)
8000bec: 4811 ldr r0, [pc, #68] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000bee: f005 f8fb bl 8005de8 <HAL_UART_Init>
8000bf2: 4603 mov r3, r0
8000bf4: 2b00 cmp r3, #0
8000bf6: d001 beq.n 8000bfc <MX_USART2_UART_Init+0x58>
{
Error_Handler();
8000bf8: f000 fb96 bl 8001328 <Error_Handler>
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8000bfc: 2100 movs r1, #0
8000bfe: 480d ldr r0, [pc, #52] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000c00: f007 f937 bl 8007e72 <HAL_UARTEx_SetTxFifoThreshold>
8000c04: 4603 mov r3, r0
8000c06: 2b00 cmp r3, #0
8000c08: d001 beq.n 8000c0e <MX_USART2_UART_Init+0x6a>
{
Error_Handler();
8000c0a: f000 fb8d bl 8001328 <Error_Handler>
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
8000c0e: 2100 movs r1, #0
8000c10: 4808 ldr r0, [pc, #32] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000c12: f007 f96c bl 8007eee <HAL_UARTEx_SetRxFifoThreshold>
8000c16: 4603 mov r3, r0
8000c18: 2b00 cmp r3, #0
8000c1a: d001 beq.n 8000c20 <MX_USART2_UART_Init+0x7c>
{
Error_Handler();
8000c1c: f000 fb84 bl 8001328 <Error_Handler>
}
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
8000c20: 4804 ldr r0, [pc, #16] @ (8000c34 <MX_USART2_UART_Init+0x90>)
8000c22: f007 f8ed bl 8007e00 <HAL_UARTEx_DisableFifoMode>
8000c26: 4603 mov r3, r0
8000c28: 2b00 cmp r3, #0
8000c2a: d001 beq.n 8000c30 <MX_USART2_UART_Init+0x8c>
{
Error_Handler();
8000c2c: f000 fb7c bl 8001328 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8000c30: bf00 nop
8000c32: bd80 pop {r7, pc}
8000c34: 200001b4 .word 0x200001b4
8000c38: 40004400 .word 0x40004400
08000c3c <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000c3c: b580 push {r7, lr}
8000c3e: b088 sub sp, #32
8000c40: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c42: f107 030c add.w r3, r7, #12
8000c46: 2200 movs r2, #0
8000c48: 601a str r2, [r3, #0]
8000c4a: 605a str r2, [r3, #4]
8000c4c: 609a str r2, [r3, #8]
8000c4e: 60da str r2, [r3, #12]
8000c50: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000c52: 4b18 ldr r3, [pc, #96] @ (8000cb4 <MX_GPIO_Init+0x78>)
8000c54: 6cdb ldr r3, [r3, #76] @ 0x4c
8000c56: 4a17 ldr r2, [pc, #92] @ (8000cb4 <MX_GPIO_Init+0x78>)
8000c58: f043 0301 orr.w r3, r3, #1
8000c5c: 64d3 str r3, [r2, #76] @ 0x4c
8000c5e: 4b15 ldr r3, [pc, #84] @ (8000cb4 <MX_GPIO_Init+0x78>)
8000c60: 6cdb ldr r3, [r3, #76] @ 0x4c
8000c62: f003 0301 and.w r3, r3, #1
8000c66: 60bb str r3, [r7, #8]
8000c68: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000c6a: 4b12 ldr r3, [pc, #72] @ (8000cb4 <MX_GPIO_Init+0x78>)
8000c6c: 6cdb ldr r3, [r3, #76] @ 0x4c
8000c6e: 4a11 ldr r2, [pc, #68] @ (8000cb4 <MX_GPIO_Init+0x78>)
8000c70: f043 0302 orr.w r3, r3, #2
8000c74: 64d3 str r3, [r2, #76] @ 0x4c
8000c76: 4b0f ldr r3, [pc, #60] @ (8000cb4 <MX_GPIO_Init+0x78>)
8000c78: 6cdb ldr r3, [r3, #76] @ 0x4c
8000c7a: f003 0302 and.w r3, r3, #2
8000c7e: 607b str r3, [r7, #4]
8000c80: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000c82: 2200 movs r2, #0
8000c84: f44f 7180 mov.w r1, #256 @ 0x100
8000c88: 480b ldr r0, [pc, #44] @ (8000cb8 <MX_GPIO_Init+0x7c>)
8000c8a: f002 fdd3 bl 8003834 <HAL_GPIO_WritePin>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
8000c8e: f44f 7380 mov.w r3, #256 @ 0x100
8000c92: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c94: 2301 movs r3, #1
8000c96: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c98: 2300 movs r3, #0
8000c9a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c9c: 2300 movs r3, #0
8000c9e: 61bb str r3, [r7, #24]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
8000ca0: f107 030c add.w r3, r7, #12
8000ca4: 4619 mov r1, r3
8000ca6: 4804 ldr r0, [pc, #16] @ (8000cb8 <MX_GPIO_Init+0x7c>)
8000ca8: f002 fc42 bl 8003530 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000cac: bf00 nop
8000cae: 3720 adds r7, #32
8000cb0: 46bd mov sp, r7
8000cb2: bd80 pop {r7, pc}
8000cb4: 40021000 .word 0x40021000
8000cb8: 48000400 .word 0x48000400
08000cbc <ADC_Filter_Init>:
/* USER CODE BEGIN 4 */
void ADC_Filter_Init(ADC_Filter *f)
{
8000cbc: b580 push {r7, lr}
8000cbe: b082 sub sp, #8
8000cc0: af00 add r7, sp, #0
8000cc2: 6078 str r0, [r7, #4]
memset(f->buffer, 0, sizeof(f->buffer));
8000cc4: 687b ldr r3, [r7, #4]
8000cc6: 2280 movs r2, #128 @ 0x80
8000cc8: 2100 movs r1, #0
8000cca: 4618 mov r0, r3
8000ccc: f007 f99c bl 8008008 <memset>
f->sum = 0;
8000cd0: 687b ldr r3, [r7, #4]
8000cd2: 2200 movs r2, #0
8000cd4: f8c3 2084 str.w r2, [r3, #132] @ 0x84
f->index = 0;
8000cd8: 687b ldr r3, [r7, #4]
8000cda: 2200 movs r2, #0
8000cdc: f883 2080 strb.w r2, [r3, #128] @ 0x80
}
8000ce0: bf00 nop
8000ce2: 3708 adds r7, #8
8000ce4: 46bd mov sp, r7
8000ce6: bd80 pop {r7, pc}
08000ce8 <ADC_Filter_Update>:
uint32_t ADC_Filter_Update(ADC_Filter *f, uint32_t new_sample)
{
8000ce8: b480 push {r7}
8000cea: b083 sub sp, #12
8000cec: af00 add r7, sp, #0
8000cee: 6078 str r0, [r7, #4]
8000cf0: 6039 str r1, [r7, #0]
/* Remove the oldest sample from the running sum */
f->sum -= f->buffer[f->index];
8000cf2: 687b ldr r3, [r7, #4]
8000cf4: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
8000cf8: 687b ldr r3, [r7, #4]
8000cfa: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
8000cfe: 4619 mov r1, r3
8000d00: 687b ldr r3, [r7, #4]
8000d02: f853 3021 ldr.w r3, [r3, r1, lsl #2]
8000d06: 1ad2 subs r2, r2, r3
8000d08: 687b ldr r3, [r7, #4]
8000d0a: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Store the new sample in the buffer */
f->buffer[f->index] = new_sample;
8000d0e: 687b ldr r3, [r7, #4]
8000d10: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
8000d14: 4619 mov r1, r3
8000d16: 687b ldr r3, [r7, #4]
8000d18: 683a ldr r2, [r7, #0]
8000d1a: f843 2021 str.w r2, [r3, r1, lsl #2]
/* Add the new sample to the sum */
f->sum += new_sample;
8000d1e: 687b ldr r3, [r7, #4]
8000d20: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
8000d24: 683b ldr r3, [r7, #0]
8000d26: 441a add r2, r3
8000d28: 687b ldr r3, [r7, #4]
8000d2a: f8c3 2084 str.w r2, [r3, #132] @ 0x84
/* Move index to next position, wrap around if at end */
f->index++;
8000d2e: 687b ldr r3, [r7, #4]
8000d30: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
8000d34: 3301 adds r3, #1
8000d36: b2da uxtb r2, r3
8000d38: 687b ldr r3, [r7, #4]
8000d3a: f883 2080 strb.w r2, [r3, #128] @ 0x80
if (f->index >= AVG_WINDOW)
8000d3e: 687b ldr r3, [r7, #4]
8000d40: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
8000d44: 2b1f cmp r3, #31
8000d46: d903 bls.n 8000d50 <ADC_Filter_Update+0x68>
{
f->index = 0;
8000d48: 687b ldr r3, [r7, #4]
8000d4a: 2200 movs r2, #0
8000d4c: f883 2080 strb.w r2, [r3, #128] @ 0x80
}
/* Return the average */
return f->sum / AVG_WINDOW;
8000d50: 687b ldr r3, [r7, #4]
8000d52: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8000d56: 095b lsrs r3, r3, #5
}
8000d58: 4618 mov r0, r3
8000d5a: 370c adds r7, #12
8000d5c: 46bd mov sp, r7
8000d5e: f85d 7b04 ldr.w r7, [sp], #4
8000d62: 4770 bx lr
08000d64 <update_pwm>:
int32_t update_pwm (uint32_t measured_mv)
{
8000d64: b480 push {r7}
8000d66: b085 sub sp, #20
8000d68: af00 add r7, sp, #0
8000d6a: 6078 str r0, [r7, #4]
/* Calculate Error */
int32_t new_pwm = 0;
8000d6c: 2300 movs r3, #0
8000d6e: 60fb str r3, [r7, #12]
uint8_t direction_flag = 0x00;
8000d70: 2300 movs r3, #0
8000d72: 72fb strb r3, [r7, #11]
if (v_target >= measured_mv)
8000d74: 4b16 ldr r3, [pc, #88] @ (8000dd0 <update_pwm+0x6c>)
8000d76: 681b ldr r3, [r3, #0]
8000d78: 687a ldr r2, [r7, #4]
8000d7a: 429a cmp r2, r3
8000d7c: d802 bhi.n 8000d84 <update_pwm+0x20>
{
direction_flag = 0x00;
8000d7e: 2300 movs r3, #0
8000d80: 72fb strb r3, [r7, #11]
8000d82: e001 b.n 8000d88 <update_pwm+0x24>
}
else
{
direction_flag = 0xFF;
8000d84: 23ff movs r3, #255 @ 0xff
8000d86: 72fb strb r3, [r7, #11]
}
if (direction_flag == 0xFF)
8000d88: 7afb ldrb r3, [r7, #11]
8000d8a: 2bff cmp r3, #255 @ 0xff
8000d8c: d106 bne.n 8000d9c <update_pwm+0x38>
{
new_pwm = (uint32_t)pwm_value;
8000d8e: 4b11 ldr r3, [pc, #68] @ (8000dd4 <update_pwm+0x70>)
8000d90: 881b ldrh r3, [r3, #0]
8000d92: 60fb str r3, [r7, #12]
new_pwm--;
8000d94: 68fb ldr r3, [r7, #12]
8000d96: 3b01 subs r3, #1
8000d98: 60fb str r3, [r7, #12]
8000d9a: e005 b.n 8000da8 <update_pwm+0x44>
}
else
{
new_pwm = (uint32_t)pwm_value;
8000d9c: 4b0d ldr r3, [pc, #52] @ (8000dd4 <update_pwm+0x70>)
8000d9e: 881b ldrh r3, [r3, #0]
8000da0: 60fb str r3, [r7, #12]
new_pwm++;
8000da2: 68fb ldr r3, [r7, #12]
8000da4: 3301 adds r3, #1
8000da6: 60fb str r3, [r7, #12]
}
/* Output Saturation (Keep PWM within hardware limits) */
if (new_pwm > pwm_max)
8000da8: 68fa ldr r2, [r7, #12]
8000daa: 4b0b ldr r3, [pc, #44] @ (8000dd8 <update_pwm+0x74>)
8000dac: 681b ldr r3, [r3, #0]
8000dae: 429a cmp r2, r3
8000db0: d902 bls.n 8000db8 <update_pwm+0x54>
{
new_pwm = pwm_max;
8000db2: 4b09 ldr r3, [pc, #36] @ (8000dd8 <update_pwm+0x74>)
8000db4: 681b ldr r3, [r3, #0]
8000db6: 60fb str r3, [r7, #12]
}
if (new_pwm <= 1)
8000db8: 68fb ldr r3, [r7, #12]
8000dba: 2b01 cmp r3, #1
8000dbc: dc01 bgt.n 8000dc2 <update_pwm+0x5e>
{
new_pwm = 1;
8000dbe: 2301 movs r3, #1
8000dc0: 60fb str r3, [r7, #12]
}
return new_pwm;
8000dc2: 68fb ldr r3, [r7, #12]
}
8000dc4: 4618 mov r0, r3
8000dc6: 3714 adds r7, #20
8000dc8: 46bd mov sp, r7
8000dca: f85d 7b04 ldr.w r7, [sp], #4
8000dce: 4770 bx lr
8000dd0: 200002a8 .word 0x200002a8
8000dd4: 200002ae .word 0x200002ae
8000dd8: 20000018 .word 0x20000018
08000ddc <get_actual_vdda>:
float get_actual_vdda(ADC_HandleTypeDef *hadc)
{
8000ddc: b580 push {r7, lr}
8000dde: b084 sub sp, #16
8000de0: af00 add r7, sp, #0
8000de2: 6078 str r0, [r7, #4]
uint32_t vrefint_raw = 0;
8000de4: 2300 movs r3, #0
8000de6: 60fb str r3, [r7, #12]
/* Perform ADC reading of the VREFINT channel */
HAL_ADC_Start(hadc);
8000de8: 6878 ldr r0, [r7, #4]
8000dea: f001 f911 bl 8002010 <HAL_ADC_Start>
if (HAL_ADC_PollForConversion(hadc, 10) == HAL_OK)
8000dee: 210a movs r1, #10
8000df0: 6878 ldr r0, [r7, #4]
8000df2: f001 f9fd bl 80021f0 <HAL_ADC_PollForConversion>
8000df6: 4603 mov r3, r0
8000df8: 2b00 cmp r3, #0
8000dfa: d103 bne.n 8000e04 <get_actual_vdda+0x28>
{
vrefint_raw = HAL_ADC_GetValue(hadc);
8000dfc: 6878 ldr r0, [r7, #4]
8000dfe: f001 facf bl 80023a0 <HAL_ADC_GetValue>
8000e02: 60f8 str r0, [r7, #12]
}
HAL_ADC_Stop(hadc);
8000e04: 6878 ldr r0, [r7, #4]
8000e06: f001 f9bf bl 8002188 <HAL_ADC_Stop>
if (vrefint_raw == 0)
8000e0a: 68fb ldr r3, [r7, #12]
8000e0c: 2b00 cmp r3, #0
8000e0e: d102 bne.n 8000e16 <get_actual_vdda+0x3a>
{
return 0; /* Avoid division by zero */
8000e10: f04f 0300 mov.w r3, #0
8000e14: e014 b.n 8000e40 <get_actual_vdda+0x64>
}
/* Use the standard ST formula to calculate VDDA */
/* VDDA = VREFINT_CAL_VREF * VREFINT_CAL / VREFINT_DATA */
float vdda_mv = (VREFINT_CAL_VREF * (uint32_t)(*VREFINT_CAL_ADDR)) / (float)vrefint_raw;
8000e16: 4b0e ldr r3, [pc, #56] @ (8000e50 <get_actual_vdda+0x74>)
8000e18: 881b ldrh r3, [r3, #0]
8000e1a: 461a mov r2, r3
8000e1c: f640 33b8 movw r3, #3000 @ 0xbb8
8000e20: fb02 f303 mul.w r3, r2, r3
8000e24: ee07 3a90 vmov s15, r3
8000e28: eef8 6a67 vcvt.f32.u32 s13, s15
8000e2c: 68fb ldr r3, [r7, #12]
8000e2e: ee07 3a90 vmov s15, r3
8000e32: eeb8 7a67 vcvt.f32.u32 s14, s15
8000e36: eec6 7a87 vdiv.f32 s15, s13, s14
8000e3a: edc7 7a02 vstr s15, [r7, #8]
return vdda_mv;
8000e3e: 68bb ldr r3, [r7, #8]
}
8000e40: ee07 3a90 vmov s15, r3
8000e44: eeb0 0a67 vmov.f32 s0, s15
8000e48: 3710 adds r7, #16
8000e4a: 46bd mov sp, r7
8000e4c: bd80 pop {r7, pc}
8000e4e: bf00 nop
8000e50: 1fff75aa .word 0x1fff75aa
08000e54 <serial_number_task>:
void serial_number_task (void)
{
8000e54: b580 push {r7, lr}
8000e56: af00 add r7, sp, #0
tx_len = 0x13;
8000e58: 4b42 ldr r3, [pc, #264] @ (8000f64 <serial_number_task+0x110>)
8000e5a: 2213 movs r2, #19
8000e5c: 701a strb r2, [r3, #0]
tx_buffer[0] = IN_SYNC_BYTE_1;
8000e5e: 4b42 ldr r3, [pc, #264] @ (8000f68 <serial_number_task+0x114>)
8000e60: 2241 movs r2, #65 @ 0x41
8000e62: 701a strb r2, [r3, #0]
tx_buffer[1] = IN_SYNC_BYTE_2;
8000e64: 4b40 ldr r3, [pc, #256] @ (8000f68 <serial_number_task+0x114>)
8000e66: 2252 movs r2, #82 @ 0x52
8000e68: 705a strb r2, [r3, #1]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8000e6a: 4b40 ldr r3, [pc, #256] @ (8000f6c <serial_number_task+0x118>)
8000e6c: 2200 movs r2, #0
8000e6e: 701a strb r2, [r3, #0]
8000e70: e00f b.n 8000e92 <serial_number_task+0x3e>
{
tx_buffer[tx_len_counter + 3] = serial_number[tx_len_counter];
8000e72: 4b3e ldr r3, [pc, #248] @ (8000f6c <serial_number_task+0x118>)
8000e74: 781b ldrb r3, [r3, #0]
8000e76: 4619 mov r1, r3
8000e78: 4b3c ldr r3, [pc, #240] @ (8000f6c <serial_number_task+0x118>)
8000e7a: 781b ldrb r3, [r3, #0]
8000e7c: 3303 adds r3, #3
8000e7e: 4a3c ldr r2, [pc, #240] @ (8000f70 <serial_number_task+0x11c>)
8000e80: 5c51 ldrb r1, [r2, r1]
8000e82: 4a39 ldr r2, [pc, #228] @ (8000f68 <serial_number_task+0x114>)
8000e84: 54d1 strb r1, [r2, r3]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8000e86: 4b39 ldr r3, [pc, #228] @ (8000f6c <serial_number_task+0x118>)
8000e88: 781b ldrb r3, [r3, #0]
8000e8a: 3301 adds r3, #1
8000e8c: b2da uxtb r2, r3
8000e8e: 4b37 ldr r3, [pc, #220] @ (8000f6c <serial_number_task+0x118>)
8000e90: 701a strb r2, [r3, #0]
8000e92: 4b36 ldr r3, [pc, #216] @ (8000f6c <serial_number_task+0x118>)
8000e94: 781a ldrb r2, [r3, #0]
8000e96: 4b33 ldr r3, [pc, #204] @ (8000f64 <serial_number_task+0x110>)
8000e98: 781b ldrb r3, [r3, #0]
8000e9a: 429a cmp r2, r3
8000e9c: d3e9 bcc.n 8000e72 <serial_number_task+0x1e>
}
tx_buffer[tx_len + 3] = 0x3A;
8000e9e: 4b31 ldr r3, [pc, #196] @ (8000f64 <serial_number_task+0x110>)
8000ea0: 781b ldrb r3, [r3, #0]
8000ea2: 3303 adds r3, #3
8000ea4: 4a30 ldr r2, [pc, #192] @ (8000f68 <serial_number_task+0x114>)
8000ea6: 213a movs r1, #58 @ 0x3a
8000ea8: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 4] = fw_rev_h + 0x30;
8000eaa: 4b32 ldr r3, [pc, #200] @ (8000f74 <serial_number_task+0x120>)
8000eac: 781a ldrb r2, [r3, #0]
8000eae: 4b2d ldr r3, [pc, #180] @ (8000f64 <serial_number_task+0x110>)
8000eb0: 781b ldrb r3, [r3, #0]
8000eb2: 3304 adds r3, #4
8000eb4: 3230 adds r2, #48 @ 0x30
8000eb6: b2d1 uxtb r1, r2
8000eb8: 4a2b ldr r2, [pc, #172] @ (8000f68 <serial_number_task+0x114>)
8000eba: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 5] = fw_rev_l + 0x30;
8000ebc: 4b2e ldr r3, [pc, #184] @ (8000f78 <serial_number_task+0x124>)
8000ebe: 781a ldrb r2, [r3, #0]
8000ec0: 4b28 ldr r3, [pc, #160] @ (8000f64 <serial_number_task+0x110>)
8000ec2: 781b ldrb r3, [r3, #0]
8000ec4: 3305 adds r3, #5
8000ec6: 3230 adds r2, #48 @ 0x30
8000ec8: b2d1 uxtb r1, r2
8000eca: 4a27 ldr r2, [pc, #156] @ (8000f68 <serial_number_task+0x114>)
8000ecc: 54d1 strb r1, [r2, r3]
tx_len = 0x16;
8000ece: 4b25 ldr r3, [pc, #148] @ (8000f64 <serial_number_task+0x110>)
8000ed0: 2216 movs r2, #22
8000ed2: 701a strb r2, [r3, #0]
tx_buffer[2] = tx_len;
8000ed4: 4b23 ldr r3, [pc, #140] @ (8000f64 <serial_number_task+0x110>)
8000ed6: 781a ldrb r2, [r3, #0]
8000ed8: 4b23 ldr r3, [pc, #140] @ (8000f68 <serial_number_task+0x114>)
8000eda: 709a strb r2, [r3, #2]
tx_checksum = 0x00;
8000edc: 4b27 ldr r3, [pc, #156] @ (8000f7c <serial_number_task+0x128>)
8000ede: 2200 movs r2, #0
8000ee0: 801a strh r2, [r3, #0]
/* Need to apply checksum to all data bits */
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8000ee2: 4b22 ldr r3, [pc, #136] @ (8000f6c <serial_number_task+0x118>)
8000ee4: 2200 movs r2, #0
8000ee6: 701a strb r2, [r3, #0]
8000ee8: e011 b.n 8000f0e <serial_number_task+0xba>
{
tx_checksum += tx_buffer[tx_len_counter + 3];
8000eea: 4b20 ldr r3, [pc, #128] @ (8000f6c <serial_number_task+0x118>)
8000eec: 781b ldrb r3, [r3, #0]
8000eee: 3303 adds r3, #3
8000ef0: 4a1d ldr r2, [pc, #116] @ (8000f68 <serial_number_task+0x114>)
8000ef2: 5cd3 ldrb r3, [r2, r3]
8000ef4: 461a mov r2, r3
8000ef6: 4b21 ldr r3, [pc, #132] @ (8000f7c <serial_number_task+0x128>)
8000ef8: 881b ldrh r3, [r3, #0]
8000efa: 4413 add r3, r2
8000efc: b29a uxth r2, r3
8000efe: 4b1f ldr r3, [pc, #124] @ (8000f7c <serial_number_task+0x128>)
8000f00: 801a strh r2, [r3, #0]
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
8000f02: 4b1a ldr r3, [pc, #104] @ (8000f6c <serial_number_task+0x118>)
8000f04: 781b ldrb r3, [r3, #0]
8000f06: 3301 adds r3, #1
8000f08: b2da uxtb r2, r3
8000f0a: 4b18 ldr r3, [pc, #96] @ (8000f6c <serial_number_task+0x118>)
8000f0c: 701a strb r2, [r3, #0]
8000f0e: 4b17 ldr r3, [pc, #92] @ (8000f6c <serial_number_task+0x118>)
8000f10: 781a ldrb r2, [r3, #0]
8000f12: 4b14 ldr r3, [pc, #80] @ (8000f64 <serial_number_task+0x110>)
8000f14: 781b ldrb r3, [r3, #0]
8000f16: 429a cmp r2, r3
8000f18: d3e7 bcc.n 8000eea <serial_number_task+0x96>
}
tx_checksum = ~tx_checksum;
8000f1a: 4b18 ldr r3, [pc, #96] @ (8000f7c <serial_number_task+0x128>)
8000f1c: 881b ldrh r3, [r3, #0]
8000f1e: 43db mvns r3, r3
8000f20: b29a uxth r2, r3
8000f22: 4b16 ldr r3, [pc, #88] @ (8000f7c <serial_number_task+0x128>)
8000f24: 801a strh r2, [r3, #0]
tx_buffer[tx_len + 3] = (uint8_t)((tx_checksum >> 8) & 0xFF);
8000f26: 4b15 ldr r3, [pc, #84] @ (8000f7c <serial_number_task+0x128>)
8000f28: 881b ldrh r3, [r3, #0]
8000f2a: 0a1b lsrs r3, r3, #8
8000f2c: b29a uxth r2, r3
8000f2e: 4b0d ldr r3, [pc, #52] @ (8000f64 <serial_number_task+0x110>)
8000f30: 781b ldrb r3, [r3, #0]
8000f32: 3303 adds r3, #3
8000f34: b2d1 uxtb r1, r2
8000f36: 4a0c ldr r2, [pc, #48] @ (8000f68 <serial_number_task+0x114>)
8000f38: 54d1 strb r1, [r2, r3]
tx_buffer[tx_len + 4] = (uint8_t)(tx_checksum & 0xFF);
8000f3a: 4b10 ldr r3, [pc, #64] @ (8000f7c <serial_number_task+0x128>)
8000f3c: 881a ldrh r2, [r3, #0]
8000f3e: 4b09 ldr r3, [pc, #36] @ (8000f64 <serial_number_task+0x110>)
8000f40: 781b ldrb r3, [r3, #0]
8000f42: 3304 adds r3, #4
8000f44: b2d1 uxtb r1, r2
8000f46: 4a08 ldr r2, [pc, #32] @ (8000f68 <serial_number_task+0x114>)
8000f48: 54d1 strb r1, [r2, r3]
tx_len = 0x1B;
8000f4a: 4b06 ldr r3, [pc, #24] @ (8000f64 <serial_number_task+0x110>)
8000f4c: 221b movs r2, #27
8000f4e: 701a strb r2, [r3, #0]
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
8000f50: 4b04 ldr r3, [pc, #16] @ (8000f64 <serial_number_task+0x110>)
8000f52: 781b ldrb r3, [r3, #0]
8000f54: 461a mov r2, r3
8000f56: 2364 movs r3, #100 @ 0x64
8000f58: 4903 ldr r1, [pc, #12] @ (8000f68 <serial_number_task+0x114>)
8000f5a: 4809 ldr r0, [pc, #36] @ (8000f80 <serial_number_task+0x12c>)
8000f5c: f004 ff94 bl 8005e88 <HAL_UART_Transmit>
}
8000f60: bf00 nop
8000f62: bd80 pop {r7, pc}
8000f64: 20000290 .word 0x20000290
8000f68: 20000270 .word 0x20000270
8000f6c: 20000291 .word 0x20000291
8000f70: 20000004 .word 0x20000004
8000f74: 20000248 .word 0x20000248
8000f78: 20000000 .word 0x20000000
8000f7c: 20000298 .word 0x20000298
8000f80: 200001b4 .word 0x200001b4
08000f84 <adc_task>:
/* ADC task */
void adc_task (void)
{
8000f84: b580 push {r7, lr}
8000f86: af00 add r7, sp, #0
HAL_ADC_Start(&hadc2);
8000f88: 4809 ldr r0, [pc, #36] @ (8000fb0 <adc_task+0x2c>)
8000f8a: f001 f841 bl 8002010 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc2, 500);
8000f8e: f44f 71fa mov.w r1, #500 @ 0x1f4
8000f92: 4807 ldr r0, [pc, #28] @ (8000fb0 <adc_task+0x2c>)
8000f94: f001 f92c bl 80021f0 <HAL_ADC_PollForConversion>
vout_adc_val = HAL_ADC_GetValue(&hadc2);
8000f98: 4805 ldr r0, [pc, #20] @ (8000fb0 <adc_task+0x2c>)
8000f9a: f001 fa01 bl 80023a0 <HAL_ADC_GetValue>
8000f9e: 4603 mov r3, r0
8000fa0: 4a04 ldr r2, [pc, #16] @ (8000fb4 <adc_task+0x30>)
8000fa2: 6013 str r3, [r2, #0]
HAL_ADC_Stop(&hadc2);
8000fa4: 4802 ldr r0, [pc, #8] @ (8000fb0 <adc_task+0x2c>)
8000fa6: f001 f8ef bl 8002188 <HAL_ADC_Stop>
}
8000faa: bf00 nop
8000fac: bd80 pop {r7, pc}
8000fae: bf00 nop
8000fb0: 200000b0 .word 0x200000b0
8000fb4: 200002b4 .word 0x200002b4
08000fb8 <power_switch>:
/* Power switch function */
void power_switch (uint8_t state)
{
8000fb8: b580 push {r7, lr}
8000fba: b082 sub sp, #8
8000fbc: af00 add r7, sp, #0
8000fbe: 4603 mov r3, r0
8000fc0: 71fb strb r3, [r7, #7]
if (state == 1)
8000fc2: 79fb ldrb r3, [r7, #7]
8000fc4: 2b01 cmp r3, #1
8000fc6: d123 bne.n 8001010 <power_switch+0x58>
{
vset_task_flag = 0xFF;
8000fc8: 4b1a ldr r3, [pc, #104] @ (8001034 <power_switch+0x7c>)
8000fca: 22ff movs r2, #255 @ 0xff
8000fcc: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);
8000fce: 2201 movs r2, #1
8000fd0: f44f 7180 mov.w r1, #256 @ 0x100
8000fd4: 4818 ldr r0, [pc, #96] @ (8001038 <power_switch+0x80>)
8000fd6: f002 fc2d bl 8003834 <HAL_GPIO_WritePin>
v_scale = v_target / 1000;
8000fda: 4b18 ldr r3, [pc, #96] @ (800103c <power_switch+0x84>)
8000fdc: 681b ldr r3, [r3, #0]
8000fde: 4a18 ldr r2, [pc, #96] @ (8001040 <power_switch+0x88>)
8000fe0: fba2 2303 umull r2, r3, r2, r3
8000fe4: 099b lsrs r3, r3, #6
8000fe6: 4a17 ldr r2, [pc, #92] @ (8001044 <power_switch+0x8c>)
8000fe8: 6013 str r3, [r2, #0]
buffer_count = (uint8_t)v_scale;
8000fea: 4b16 ldr r3, [pc, #88] @ (8001044 <power_switch+0x8c>)
8000fec: 681b ldr r3, [r3, #0]
8000fee: b2da uxtb r2, r3
8000ff0: 4b15 ldr r3, [pc, #84] @ (8001048 <power_switch+0x90>)
8000ff2: 701a strb r2, [r3, #0]
pwm_value = dataBuffer[buffer_count];
8000ff4: 4b14 ldr r3, [pc, #80] @ (8001048 <power_switch+0x90>)
8000ff6: 781b ldrb r3, [r3, #0]
8000ff8: 461a mov r2, r3
8000ffa: 4b14 ldr r3, [pc, #80] @ (800104c <power_switch+0x94>)
8000ffc: f833 2012 ldrh.w r2, [r3, r2, lsl #1]
8001000: 4b13 ldr r3, [pc, #76] @ (8001050 <power_switch+0x98>)
8001002: 801a strh r2, [r3, #0]
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, pwm_value);
8001004: 4b12 ldr r3, [pc, #72] @ (8001050 <power_switch+0x98>)
8001006: 881a ldrh r2, [r3, #0]
8001008: 4b12 ldr r3, [pc, #72] @ (8001054 <power_switch+0x9c>)
800100a: 681b ldr r3, [r3, #0]
800100c: 635a str r2, [r3, #52] @ 0x34
{
vset_task_flag = 0x00;
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
}
}
800100e: e00c b.n 800102a <power_switch+0x72>
vset_task_flag = 0x00;
8001010: 4b08 ldr r3, [pc, #32] @ (8001034 <power_switch+0x7c>)
8001012: 2200 movs r2, #0
8001014: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8001016: 2200 movs r2, #0
8001018: f44f 7180 mov.w r1, #256 @ 0x100
800101c: 4806 ldr r0, [pc, #24] @ (8001038 <power_switch+0x80>)
800101e: f002 fc09 bl 8003834 <HAL_GPIO_WritePin>
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
8001022: 4b0c ldr r3, [pc, #48] @ (8001054 <power_switch+0x9c>)
8001024: 681b ldr r3, [r3, #0]
8001026: 2200 movs r2, #0
8001028: 635a str r2, [r3, #52] @ 0x34
}
800102a: bf00 nop
800102c: 3708 adds r7, #8
800102e: 46bd mov sp, r7
8001030: bd80 pop {r7, pc}
8001032: bf00 nop
8001034: 200002ac .word 0x200002ac
8001038: 48000400 .word 0x48000400
800103c: 200002a8 .word 0x200002a8
8001040: 10624dd3 .word 0x10624dd3
8001044: 200002cc .word 0x200002cc
8001048: 200002c8 .word 0x200002c8
800104c: 08008078 .word 0x08008078
8001050: 200002ae .word 0x200002ae
8001054: 20000168 .word 0x20000168
08001058 <power_switch_solid_state>:
/* Power switch solid state function */
void power_switch_solid_state (uint8_t state)
{
8001058: b580 push {r7, lr}
800105a: b082 sub sp, #8
800105c: af00 add r7, sp, #0
800105e: 4603 mov r3, r0
8001060: 71fb strb r3, [r7, #7]
if (state == 1)
8001062: 79fb ldrb r3, [r7, #7]
8001064: 2b01 cmp r3, #1
8001066: d10b bne.n 8001080 <power_switch_solid_state+0x28>
{
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);
8001068: 2201 movs r2, #1
800106a: f44f 7180 mov.w r1, #256 @ 0x100
800106e: 480b ldr r0, [pc, #44] @ (800109c <power_switch_solid_state+0x44>)
8001070: f002 fbe0 bl 8003834 <HAL_GPIO_WritePin>
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 63999);
8001074: 4b0a ldr r3, [pc, #40] @ (80010a0 <power_switch_solid_state+0x48>)
8001076: 681b ldr r3, [r3, #0]
8001078: f64f 12ff movw r2, #63999 @ 0xf9ff
800107c: 635a str r2, [r3, #52] @ 0x34
else
{
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
}
}
800107e: e009 b.n 8001094 <power_switch_solid_state+0x3c>
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8001080: 2200 movs r2, #0
8001082: f44f 7180 mov.w r1, #256 @ 0x100
8001086: 4805 ldr r0, [pc, #20] @ (800109c <power_switch_solid_state+0x44>)
8001088: f002 fbd4 bl 8003834 <HAL_GPIO_WritePin>
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
800108c: 4b04 ldr r3, [pc, #16] @ (80010a0 <power_switch_solid_state+0x48>)
800108e: 681b ldr r3, [r3, #0]
8001090: 2200 movs r2, #0
8001092: 635a str r2, [r3, #52] @ 0x34
}
8001094: bf00 nop
8001096: 3708 adds r7, #8
8001098: 46bd mov sp, r7
800109a: bd80 pop {r7, pc}
800109c: 48000400 .word 0x48000400
80010a0: 20000168 .word 0x20000168
080010a4 <HAL_UART_TxCpltCallback>:
/* UART Tx callback */
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
80010a4: b480 push {r7}
80010a6: b083 sub sp, #12
80010a8: af00 add r7, sp, #0
80010aa: 6078 str r0, [r7, #4]
/* Do nothing here for now */
}
80010ac: bf00 nop
80010ae: 370c adds r7, #12
80010b0: 46bd mov sp, r7
80010b2: f85d 7b04 ldr.w r7, [sp], #4
80010b6: 4770 bx lr
080010b8 <HAL_UART_RxCpltCallback>:
/* UART Rx callback */
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
80010b8: b580 push {r7, lr}
80010ba: b082 sub sp, #8
80010bc: af00 add r7, sp, #0
80010be: 6078 str r0, [r7, #4]
/* If data received on UART */
if(huart->Instance==USART2)
80010c0: 687b ldr r3, [r7, #4]
80010c2: 681b ldr r3, [r3, #0]
80010c4: 4a87 ldr r2, [pc, #540] @ (80012e4 <HAL_UART_RxCpltCallback+0x22c>)
80010c6: 4293 cmp r3, r2
80010c8: f040 8107 bne.w 80012da <HAL_UART_RxCpltCallback+0x222>
{
/* Act on received data */
switch (rx_counter)
80010cc: 4b86 ldr r3, [pc, #536] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
80010ce: 781b ldrb r3, [r3, #0]
80010d0: 2b05 cmp r3, #5
80010d2: f200 80f8 bhi.w 80012c6 <HAL_UART_RxCpltCallback+0x20e>
80010d6: a201 add r2, pc, #4 @ (adr r2, 80010dc <HAL_UART_RxCpltCallback+0x24>)
80010d8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80010dc: 080010f5 .word 0x080010f5
80010e0: 0800110d .word 0x0800110d
80010e4: 0800113b .word 0x0800113b
80010e8: 08001157 .word 0x08001157
80010ec: 08001193 .word 0x08001193
80010f0: 080011a9 .word 0x080011a9
{
case 0x00:
/* Check to see if first sync byte has been received */
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
80010f4: 4b7d ldr r3, [pc, #500] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
80010f6: 781b ldrb r3, [r3, #0]
80010f8: 2b41 cmp r3, #65 @ 0x41
80010fa: f040 80e6 bne.w 80012ca <HAL_UART_RxCpltCallback+0x212>
{
/* Got it, so now wait for the second sync byte */
rx_counter++;
80010fe: 4b7a ldr r3, [pc, #488] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001100: 781b ldrb r3, [r3, #0]
8001102: 3301 adds r3, #1
8001104: b2da uxtb r2, r3
8001106: 4b78 ldr r3, [pc, #480] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001108: 701a strb r2, [r3, #0]
}
break;
800110a: e0de b.n 80012ca <HAL_UART_RxCpltCallback+0x212>
case 0x01:
/* Check to see if second sync byte has been received */
if (rx_hold_buffer[0] == IN_SYNC_BYTE_2)
800110c: 4b77 ldr r3, [pc, #476] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
800110e: 781b ldrb r3, [r3, #0]
8001110: 2b52 cmp r3, #82 @ 0x52
8001112: d106 bne.n 8001122 <HAL_UART_RxCpltCallback+0x6a>
{
/* Got it, so now wait for the data byte */
rx_counter++;
8001114: 4b74 ldr r3, [pc, #464] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001116: 781b ldrb r3, [r3, #0]
8001118: 3301 adds r3, #1
800111a: b2da uxtb r2, r3
800111c: 4b72 ldr r3, [pc, #456] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
800111e: 701a strb r2, [r3, #0]
{
rx_counter = 0x00;
}
}
break;
8001120: e0d6 b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
8001122: 4b72 ldr r3, [pc, #456] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
8001124: 781b ldrb r3, [r3, #0]
8001126: 2b41 cmp r3, #65 @ 0x41
8001128: d103 bne.n 8001132 <HAL_UART_RxCpltCallback+0x7a>
rx_counter = 0x01;
800112a: 4b6f ldr r3, [pc, #444] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
800112c: 2201 movs r2, #1
800112e: 701a strb r2, [r3, #0]
break;
8001130: e0ce b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
rx_counter = 0x00;
8001132: 4b6d ldr r3, [pc, #436] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001134: 2200 movs r2, #0
8001136: 701a strb r2, [r3, #0]
break;
8001138: e0ca b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
case 0x02:
/* Get rx length and reset counter */
rx_len = rx_hold_buffer[0];
800113a: 4b6c ldr r3, [pc, #432] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
800113c: 781a ldrb r2, [r3, #0]
800113e: 4b6c ldr r3, [pc, #432] @ (80012f0 <HAL_UART_RxCpltCallback+0x238>)
8001140: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
8001142: 4b6c ldr r3, [pc, #432] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
8001144: 2200 movs r2, #0
8001146: 701a strb r2, [r3, #0]
rx_counter++;
8001148: 4b67 ldr r3, [pc, #412] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
800114a: 781b ldrb r3, [r3, #0]
800114c: 3301 adds r3, #1
800114e: b2da uxtb r2, r3
8001150: 4b65 ldr r3, [pc, #404] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001152: 701a strb r2, [r3, #0]
break;
8001154: e0bc b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
case 0x03:
/* Store entire length of Data bytes */
/* Increase count */
rx_len_counter++;
8001156: 4b67 ldr r3, [pc, #412] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
8001158: 781b ldrb r3, [r3, #0]
800115a: 3301 adds r3, #1
800115c: b2da uxtb r2, r3
800115e: 4b65 ldr r3, [pc, #404] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
8001160: 701a strb r2, [r3, #0]
/* Store data */
rx_buffer[rx_len_counter - 1] = rx_hold_buffer[0];
8001162: 4b64 ldr r3, [pc, #400] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
8001164: 781b ldrb r3, [r3, #0]
8001166: 3b01 subs r3, #1
8001168: 4a60 ldr r2, [pc, #384] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
800116a: 7811 ldrb r1, [r2, #0]
800116c: 4a62 ldr r2, [pc, #392] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
800116e: 54d1 strb r1, [r2, r3]
/* Check to see if we have all the expected data bytes */
/* If so, then move on the CRC */
if (rx_len_counter == rx_len)
8001170: 4b60 ldr r3, [pc, #384] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
8001172: 781a ldrb r2, [r3, #0]
8001174: 4b5e ldr r3, [pc, #376] @ (80012f0 <HAL_UART_RxCpltCallback+0x238>)
8001176: 781b ldrb r3, [r3, #0]
8001178: 429a cmp r2, r3
800117a: f040 80a8 bne.w 80012ce <HAL_UART_RxCpltCallback+0x216>
{
rx_counter++;
800117e: 4b5a ldr r3, [pc, #360] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001180: 781b ldrb r3, [r3, #0]
8001182: 3301 adds r3, #1
8001184: b2da uxtb r2, r3
8001186: 4b58 ldr r3, [pc, #352] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
8001188: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
800118a: 4b5a ldr r3, [pc, #360] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
800118c: 2200 movs r2, #0
800118e: 701a strb r2, [r3, #0]
}
break;
8001190: e09d b.n 80012ce <HAL_UART_RxCpltCallback+0x216>
case 0x04:
/* Store Rx checksum byte #1 */
rx_checksum_hold_1 = rx_hold_buffer[0];
8001192: 4b56 ldr r3, [pc, #344] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
8001194: 781a ldrb r2, [r3, #0]
8001196: 4b59 ldr r3, [pc, #356] @ (80012fc <HAL_UART_RxCpltCallback+0x244>)
8001198: 701a strb r2, [r3, #0]
rx_counter++;
800119a: 4b53 ldr r3, [pc, #332] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
800119c: 781b ldrb r3, [r3, #0]
800119e: 3301 adds r3, #1
80011a0: b2da uxtb r2, r3
80011a2: 4b51 ldr r3, [pc, #324] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
80011a4: 701a strb r2, [r3, #0]
break;
80011a6: e093 b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
case 0x05:
/* Store Rx checksum byte #2, reset and calculate checksum */
rx_checksum_hold_2 = rx_hold_buffer[0];
80011a8: 4b50 ldr r3, [pc, #320] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
80011aa: 781a ldrb r2, [r3, #0]
80011ac: 4b54 ldr r3, [pc, #336] @ (8001300 <HAL_UART_RxCpltCallback+0x248>)
80011ae: 701a strb r2, [r3, #0]
rx_checksum_hold = (rx_checksum_hold_1 << 8) | rx_checksum_hold_2;
80011b0: 4b52 ldr r3, [pc, #328] @ (80012fc <HAL_UART_RxCpltCallback+0x244>)
80011b2: 781b ldrb r3, [r3, #0]
80011b4: b21b sxth r3, r3
80011b6: 021b lsls r3, r3, #8
80011b8: b21a sxth r2, r3
80011ba: 4b51 ldr r3, [pc, #324] @ (8001300 <HAL_UART_RxCpltCallback+0x248>)
80011bc: 781b ldrb r3, [r3, #0]
80011be: b21b sxth r3, r3
80011c0: 4313 orrs r3, r2
80011c2: b21b sxth r3, r3
80011c4: b29a uxth r2, r3
80011c6: 4b4f ldr r3, [pc, #316] @ (8001304 <HAL_UART_RxCpltCallback+0x24c>)
80011c8: 801a strh r2, [r3, #0]
rx_checksum = 0;
80011ca: 4b4f ldr r3, [pc, #316] @ (8001308 <HAL_UART_RxCpltCallback+0x250>)
80011cc: 2200 movs r2, #0
80011ce: 801a strh r2, [r3, #0]
/* Need to apply to all data bits */
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
80011d0: 4b48 ldr r3, [pc, #288] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
80011d2: 2200 movs r2, #0
80011d4: 701a strb r2, [r3, #0]
80011d6: e011 b.n 80011fc <HAL_UART_RxCpltCallback+0x144>
{
rx_checksum += rx_buffer[rx_len_counter];
80011d8: 4b46 ldr r3, [pc, #280] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
80011da: 781b ldrb r3, [r3, #0]
80011dc: 461a mov r2, r3
80011de: 4b46 ldr r3, [pc, #280] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
80011e0: 5c9b ldrb r3, [r3, r2]
80011e2: 461a mov r2, r3
80011e4: 4b48 ldr r3, [pc, #288] @ (8001308 <HAL_UART_RxCpltCallback+0x250>)
80011e6: 881b ldrh r3, [r3, #0]
80011e8: 4413 add r3, r2
80011ea: b29a uxth r2, r3
80011ec: 4b46 ldr r3, [pc, #280] @ (8001308 <HAL_UART_RxCpltCallback+0x250>)
80011ee: 801a strh r2, [r3, #0]
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
80011f0: 4b40 ldr r3, [pc, #256] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
80011f2: 781b ldrb r3, [r3, #0]
80011f4: 3301 adds r3, #1
80011f6: b2da uxtb r2, r3
80011f8: 4b3e ldr r3, [pc, #248] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
80011fa: 701a strb r2, [r3, #0]
80011fc: 4b3d ldr r3, [pc, #244] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
80011fe: 781a ldrb r2, [r3, #0]
8001200: 4b3b ldr r3, [pc, #236] @ (80012f0 <HAL_UART_RxCpltCallback+0x238>)
8001202: 781b ldrb r3, [r3, #0]
8001204: 429a cmp r2, r3
8001206: d3e7 bcc.n 80011d8 <HAL_UART_RxCpltCallback+0x120>
}
rx_len = 0x00;
8001208: 4b39 ldr r3, [pc, #228] @ (80012f0 <HAL_UART_RxCpltCallback+0x238>)
800120a: 2200 movs r2, #0
800120c: 701a strb r2, [r3, #0]
rx_len_counter = 0x00;
800120e: 4b39 ldr r3, [pc, #228] @ (80012f4 <HAL_UART_RxCpltCallback+0x23c>)
8001210: 2200 movs r2, #0
8001212: 701a strb r2, [r3, #0]
rx_checksum = ~rx_checksum;
8001214: 4b3c ldr r3, [pc, #240] @ (8001308 <HAL_UART_RxCpltCallback+0x250>)
8001216: 881b ldrh r3, [r3, #0]
8001218: 43db mvns r3, r3
800121a: b29a uxth r2, r3
800121c: 4b3a ldr r3, [pc, #232] @ (8001308 <HAL_UART_RxCpltCallback+0x250>)
800121e: 801a strh r2, [r3, #0]
/* If checksum calculated equals the received checksum of packet then we got a good packet */
if (rx_checksum == rx_checksum_hold)
8001220: 4b39 ldr r3, [pc, #228] @ (8001308 <HAL_UART_RxCpltCallback+0x250>)
8001222: 881a ldrh r2, [r3, #0]
8001224: 4b37 ldr r3, [pc, #220] @ (8001304 <HAL_UART_RxCpltCallback+0x24c>)
8001226: 881b ldrh r3, [r3, #0]
8001228: 429a cmp r2, r3
800122a: d146 bne.n 80012ba <HAL_UART_RxCpltCallback+0x202>
{
/* Rx is finished, so reset count to wait for another first sync byte (also act on command/data)*/
rx_counter = 0x00;
800122c: 4b2e ldr r3, [pc, #184] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
800122e: 2200 movs r2, #0
8001230: 701a strb r2, [r3, #0]
command = rx_buffer[0];
8001232: 4b31 ldr r3, [pc, #196] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
8001234: 781a ldrb r2, [r3, #0]
8001236: 4b35 ldr r3, [pc, #212] @ (800130c <HAL_UART_RxCpltCallback+0x254>)
8001238: 701a strb r2, [r3, #0]
switch (command)
800123a: 4b34 ldr r3, [pc, #208] @ (800130c <HAL_UART_RxCpltCallback+0x254>)
800123c: 781b ldrb r3, [r3, #0]
800123e: 2b73 cmp r3, #115 @ 0x73
8001240: d026 beq.n 8001290 <HAL_UART_RxCpltCallback+0x1d8>
8001242: 2b73 cmp r3, #115 @ 0x73
8001244: dc3d bgt.n 80012c2 <HAL_UART_RxCpltCallback+0x20a>
8001246: 2b56 cmp r3, #86 @ 0x56
8001248: d02f beq.n 80012aa <HAL_UART_RxCpltCallback+0x1f2>
800124a: 2b56 cmp r3, #86 @ 0x56
800124c: dc39 bgt.n 80012c2 <HAL_UART_RxCpltCallback+0x20a>
800124e: 2b49 cmp r3, #73 @ 0x49
8001250: d02f beq.n 80012b2 <HAL_UART_RxCpltCallback+0x1fa>
8001252: 2b53 cmp r3, #83 @ 0x53
8001254: d135 bne.n 80012c2 <HAL_UART_RxCpltCallback+0x20a>
{
/* 'S' - Set power output state */
case 0x53:
solid_state_flag = 0x00;
8001256: 4b2e ldr r3, [pc, #184] @ (8001310 <HAL_UART_RxCpltCallback+0x258>)
8001258: 2200 movs r2, #0
800125a: 701a strb r2, [r3, #0]
power_state_value = rx_buffer[1];
800125c: 4b26 ldr r3, [pc, #152] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
800125e: 785a ldrb r2, [r3, #1]
8001260: 4b2c ldr r3, [pc, #176] @ (8001314 <HAL_UART_RxCpltCallback+0x25c>)
8001262: 701a strb r2, [r3, #0]
v_target = ((uint32_t)rx_buffer[2] << 24) | ((uint32_t)rx_buffer[3] << 16) | ((uint32_t)rx_buffer[4] << 8) | ((uint32_t)rx_buffer[5]);
8001264: 4b24 ldr r3, [pc, #144] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
8001266: 789b ldrb r3, [r3, #2]
8001268: 061a lsls r2, r3, #24
800126a: 4b23 ldr r3, [pc, #140] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
800126c: 78db ldrb r3, [r3, #3]
800126e: 041b lsls r3, r3, #16
8001270: 431a orrs r2, r3
8001272: 4b21 ldr r3, [pc, #132] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
8001274: 791b ldrb r3, [r3, #4]
8001276: 021b lsls r3, r3, #8
8001278: 4313 orrs r3, r2
800127a: 4a1f ldr r2, [pc, #124] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
800127c: 7952 ldrb r2, [r2, #5]
800127e: 4313 orrs r3, r2
8001280: 4a25 ldr r2, [pc, #148] @ (8001318 <HAL_UART_RxCpltCallback+0x260>)
8001282: 6013 str r3, [r2, #0]
power_switch(power_state_value);
8001284: 4b23 ldr r3, [pc, #140] @ (8001314 <HAL_UART_RxCpltCallback+0x25c>)
8001286: 781b ldrb r3, [r3, #0]
8001288: 4618 mov r0, r3
800128a: f7ff fe95 bl 8000fb8 <power_switch>
break;
800128e: e019 b.n 80012c4 <HAL_UART_RxCpltCallback+0x20c>
/* 's' - Set power output solid state */
case 0x73:
solid_state_flag = 0xff;
8001290: 4b1f ldr r3, [pc, #124] @ (8001310 <HAL_UART_RxCpltCallback+0x258>)
8001292: 22ff movs r2, #255 @ 0xff
8001294: 701a strb r2, [r3, #0]
power_state_value = rx_buffer[1];
8001296: 4b18 ldr r3, [pc, #96] @ (80012f8 <HAL_UART_RxCpltCallback+0x240>)
8001298: 785a ldrb r2, [r3, #1]
800129a: 4b1e ldr r3, [pc, #120] @ (8001314 <HAL_UART_RxCpltCallback+0x25c>)
800129c: 701a strb r2, [r3, #0]
power_switch_solid_state(power_state_value);
800129e: 4b1d ldr r3, [pc, #116] @ (8001314 <HAL_UART_RxCpltCallback+0x25c>)
80012a0: 781b ldrb r3, [r3, #0]
80012a2: 4618 mov r0, r3
80012a4: f7ff fed8 bl 8001058 <power_switch_solid_state>
break;
80012a8: e00c b.n 80012c4 <HAL_UART_RxCpltCallback+0x20c>
/* 'V' - Get voltages (both input and output) */
case 0x56:
adc_task_flag = 0xff;
80012aa: 4b1c ldr r3, [pc, #112] @ (800131c <HAL_UART_RxCpltCallback+0x264>)
80012ac: 22ff movs r2, #255 @ 0xff
80012ae: 701a strb r2, [r3, #0]
break;
80012b0: e008 b.n 80012c4 <HAL_UART_RxCpltCallback+0x20c>
/* 'I' - Get serial number information */
case 0x49:
serial_number_flag = 0xff;
80012b2: 4b1b ldr r3, [pc, #108] @ (8001320 <HAL_UART_RxCpltCallback+0x268>)
80012b4: 22ff movs r2, #255 @ 0xff
80012b6: 701a strb r2, [r3, #0]
break;
80012b8: e004 b.n 80012c4 <HAL_UART_RxCpltCallback+0x20c>
/* Bad packet received */
else
{
/* Rx is finished, so reset count to wait for another first sync byte (bad packet so no flag)*/
rx_counter = 0x00;
80012ba: 4b0b ldr r3, [pc, #44] @ (80012e8 <HAL_UART_RxCpltCallback+0x230>)
80012bc: 2200 movs r2, #0
80012be: 701a strb r2, [r3, #0]
}
break;
80012c0: e006 b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
break;
80012c2: bf00 nop
break;
80012c4: e004 b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
/* Default case - NOT USED!*/
default:
break;
80012c6: bf00 nop
80012c8: e002 b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
break;
80012ca: bf00 nop
80012cc: e000 b.n 80012d0 <HAL_UART_RxCpltCallback+0x218>
break;
80012ce: bf00 nop
}
/* Reset interrupts */
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
80012d0: 2201 movs r2, #1
80012d2: 4906 ldr r1, [pc, #24] @ (80012ec <HAL_UART_RxCpltCallback+0x234>)
80012d4: 4813 ldr r0, [pc, #76] @ (8001324 <HAL_UART_RxCpltCallback+0x26c>)
80012d6: f004 fe65 bl 8005fa4 <HAL_UART_Receive_IT>
}
}
80012da: bf00 nop
80012dc: 3708 adds r7, #8
80012de: 46bd mov sp, r7
80012e0: bd80 pop {r7, pc}
80012e2: bf00 nop
80012e4: 40004400 .word 0x40004400
80012e8: 20000292 .word 0x20000292
80012ec: 2000024c .word 0x2000024c
80012f0: 20000293 .word 0x20000293
80012f4: 20000294 .word 0x20000294
80012f8: 20000250 .word 0x20000250
80012fc: 2000029a .word 0x2000029a
8001300: 2000029b .word 0x2000029b
8001304: 2000029c .word 0x2000029c
8001308: 20000296 .word 0x20000296
800130c: 2000029f .word 0x2000029f
8001310: 200002d0 .word 0x200002d0
8001314: 2000029e .word 0x2000029e
8001318: 200002a8 .word 0x200002a8
800131c: 200002a0 .word 0x200002a0
8001320: 200002ad .word 0x200002ad
8001324: 200001b4 .word 0x200001b4
08001328 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001328: b480 push {r7}
800132a: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
800132c: b672 cpsid i
}
800132e: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001330: bf00 nop
8001332: e7fd b.n 8001330 <Error_Handler+0x8>
08001334 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001334: b580 push {r7, lr}
8001336: b082 sub sp, #8
8001338: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800133a: 4b0f ldr r3, [pc, #60] @ (8001378 <HAL_MspInit+0x44>)
800133c: 6e1b ldr r3, [r3, #96] @ 0x60
800133e: 4a0e ldr r2, [pc, #56] @ (8001378 <HAL_MspInit+0x44>)
8001340: f043 0301 orr.w r3, r3, #1
8001344: 6613 str r3, [r2, #96] @ 0x60
8001346: 4b0c ldr r3, [pc, #48] @ (8001378 <HAL_MspInit+0x44>)
8001348: 6e1b ldr r3, [r3, #96] @ 0x60
800134a: f003 0301 and.w r3, r3, #1
800134e: 607b str r3, [r7, #4]
8001350: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8001352: 4b09 ldr r3, [pc, #36] @ (8001378 <HAL_MspInit+0x44>)
8001354: 6d9b ldr r3, [r3, #88] @ 0x58
8001356: 4a08 ldr r2, [pc, #32] @ (8001378 <HAL_MspInit+0x44>)
8001358: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800135c: 6593 str r3, [r2, #88] @ 0x58
800135e: 4b06 ldr r3, [pc, #24] @ (8001378 <HAL_MspInit+0x44>)
8001360: 6d9b ldr r3, [r3, #88] @ 0x58
8001362: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001366: 603b str r3, [r7, #0]
8001368: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
*/
HAL_PWREx_DisableUCPDDeadBattery();
800136a: f002 fb1f bl 80039ac <HAL_PWREx_DisableUCPDDeadBattery>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800136e: bf00 nop
8001370: 3708 adds r7, #8
8001372: 46bd mov sp, r7
8001374: bd80 pop {r7, pc}
8001376: bf00 nop
8001378: 40021000 .word 0x40021000
0800137c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
800137c: b580 push {r7, lr}
800137e: b09c sub sp, #112 @ 0x70
8001380: af00 add r7, sp, #0
8001382: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001384: f107 035c add.w r3, r7, #92 @ 0x5c
8001388: 2200 movs r2, #0
800138a: 601a str r2, [r3, #0]
800138c: 605a str r2, [r3, #4]
800138e: 609a str r2, [r3, #8]
8001390: 60da str r2, [r3, #12]
8001392: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001394: f107 0318 add.w r3, r7, #24
8001398: 2244 movs r2, #68 @ 0x44
800139a: 2100 movs r1, #0
800139c: 4618 mov r0, r3
800139e: f006 fe33 bl 8008008 <memset>
if(hadc->Instance==ADC1)
80013a2: 687b ldr r3, [r7, #4]
80013a4: 681b ldr r3, [r3, #0]
80013a6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80013aa: d125 bne.n 80013f8 <HAL_ADC_MspInit+0x7c>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
80013ac: f44f 4300 mov.w r3, #32768 @ 0x8000
80013b0: 61bb str r3, [r7, #24]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
80013b2: f04f 5300 mov.w r3, #536870912 @ 0x20000000
80013b6: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80013b8: f107 0318 add.w r3, r7, #24
80013bc: 4618 mov r0, r3
80013be: f003 f833 bl 8004428 <HAL_RCCEx_PeriphCLKConfig>
80013c2: 4603 mov r3, r0
80013c4: 2b00 cmp r3, #0
80013c6: d001 beq.n 80013cc <HAL_ADC_MspInit+0x50>
{
Error_Handler();
80013c8: f7ff ffae bl 8001328 <Error_Handler>
}
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
80013cc: 4b2e ldr r3, [pc, #184] @ (8001488 <HAL_ADC_MspInit+0x10c>)
80013ce: 681b ldr r3, [r3, #0]
80013d0: 3301 adds r3, #1
80013d2: 4a2d ldr r2, [pc, #180] @ (8001488 <HAL_ADC_MspInit+0x10c>)
80013d4: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
80013d6: 4b2c ldr r3, [pc, #176] @ (8001488 <HAL_ADC_MspInit+0x10c>)
80013d8: 681b ldr r3, [r3, #0]
80013da: 2b01 cmp r3, #1
80013dc: d14f bne.n 800147e <HAL_ADC_MspInit+0x102>
__HAL_RCC_ADC12_CLK_ENABLE();
80013de: 4b2b ldr r3, [pc, #172] @ (800148c <HAL_ADC_MspInit+0x110>)
80013e0: 6cdb ldr r3, [r3, #76] @ 0x4c
80013e2: 4a2a ldr r2, [pc, #168] @ (800148c <HAL_ADC_MspInit+0x110>)
80013e4: f443 5300 orr.w r3, r3, #8192 @ 0x2000
80013e8: 64d3 str r3, [r2, #76] @ 0x4c
80013ea: 4b28 ldr r3, [pc, #160] @ (800148c <HAL_ADC_MspInit+0x110>)
80013ec: 6cdb ldr r3, [r3, #76] @ 0x4c
80013ee: f403 5300 and.w r3, r3, #8192 @ 0x2000
80013f2: 617b str r3, [r7, #20]
80013f4: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
80013f6: e042 b.n 800147e <HAL_ADC_MspInit+0x102>
else if(hadc->Instance==ADC2)
80013f8: 687b ldr r3, [r7, #4]
80013fa: 681b ldr r3, [r3, #0]
80013fc: 4a24 ldr r2, [pc, #144] @ (8001490 <HAL_ADC_MspInit+0x114>)
80013fe: 4293 cmp r3, r2
8001400: d13d bne.n 800147e <HAL_ADC_MspInit+0x102>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
8001402: f44f 4300 mov.w r3, #32768 @ 0x8000
8001406: 61bb str r3, [r7, #24]
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
8001408: f04f 5300 mov.w r3, #536870912 @ 0x20000000
800140c: 657b str r3, [r7, #84] @ 0x54
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800140e: f107 0318 add.w r3, r7, #24
8001412: 4618 mov r0, r3
8001414: f003 f808 bl 8004428 <HAL_RCCEx_PeriphCLKConfig>
8001418: 4603 mov r3, r0
800141a: 2b00 cmp r3, #0
800141c: d001 beq.n 8001422 <HAL_ADC_MspInit+0xa6>
Error_Handler();
800141e: f7ff ff83 bl 8001328 <Error_Handler>
HAL_RCC_ADC12_CLK_ENABLED++;
8001422: 4b19 ldr r3, [pc, #100] @ (8001488 <HAL_ADC_MspInit+0x10c>)
8001424: 681b ldr r3, [r3, #0]
8001426: 3301 adds r3, #1
8001428: 4a17 ldr r2, [pc, #92] @ (8001488 <HAL_ADC_MspInit+0x10c>)
800142a: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
800142c: 4b16 ldr r3, [pc, #88] @ (8001488 <HAL_ADC_MspInit+0x10c>)
800142e: 681b ldr r3, [r3, #0]
8001430: 2b01 cmp r3, #1
8001432: d10b bne.n 800144c <HAL_ADC_MspInit+0xd0>
__HAL_RCC_ADC12_CLK_ENABLE();
8001434: 4b15 ldr r3, [pc, #84] @ (800148c <HAL_ADC_MspInit+0x110>)
8001436: 6cdb ldr r3, [r3, #76] @ 0x4c
8001438: 4a14 ldr r2, [pc, #80] @ (800148c <HAL_ADC_MspInit+0x110>)
800143a: f443 5300 orr.w r3, r3, #8192 @ 0x2000
800143e: 64d3 str r3, [r2, #76] @ 0x4c
8001440: 4b12 ldr r3, [pc, #72] @ (800148c <HAL_ADC_MspInit+0x110>)
8001442: 6cdb ldr r3, [r3, #76] @ 0x4c
8001444: f403 5300 and.w r3, r3, #8192 @ 0x2000
8001448: 613b str r3, [r7, #16]
800144a: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800144c: 4b0f ldr r3, [pc, #60] @ (800148c <HAL_ADC_MspInit+0x110>)
800144e: 6cdb ldr r3, [r3, #76] @ 0x4c
8001450: 4a0e ldr r2, [pc, #56] @ (800148c <HAL_ADC_MspInit+0x110>)
8001452: f043 0301 orr.w r3, r3, #1
8001456: 64d3 str r3, [r2, #76] @ 0x4c
8001458: 4b0c ldr r3, [pc, #48] @ (800148c <HAL_ADC_MspInit+0x110>)
800145a: 6cdb ldr r3, [r3, #76] @ 0x4c
800145c: f003 0301 and.w r3, r3, #1
8001460: 60fb str r3, [r7, #12]
8001462: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = VOUT_Pin;
8001464: 2340 movs r3, #64 @ 0x40
8001466: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001468: 2303 movs r3, #3
800146a: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Pull = GPIO_NOPULL;
800146c: 2300 movs r3, #0
800146e: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(VOUT_GPIO_Port, &GPIO_InitStruct);
8001470: f107 035c add.w r3, r7, #92 @ 0x5c
8001474: 4619 mov r1, r3
8001476: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800147a: f002 f859 bl 8003530 <HAL_GPIO_Init>
}
800147e: bf00 nop
8001480: 3770 adds r7, #112 @ 0x70
8001482: 46bd mov sp, r7
8001484: bd80 pop {r7, pc}
8001486: bf00 nop
8001488: 2000035c .word 0x2000035c
800148c: 40021000 .word 0x40021000
8001490: 50000100 .word 0x50000100
08001494 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001494: b580 push {r7, lr}
8001496: b084 sub sp, #16
8001498: af00 add r7, sp, #0
800149a: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
800149c: 687b ldr r3, [r7, #4]
800149e: 681b ldr r3, [r3, #0]
80014a0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80014a4: d114 bne.n 80014d0 <HAL_TIM_Base_MspInit+0x3c>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
80014a6: 4b15 ldr r3, [pc, #84] @ (80014fc <HAL_TIM_Base_MspInit+0x68>)
80014a8: 6d9b ldr r3, [r3, #88] @ 0x58
80014aa: 4a14 ldr r2, [pc, #80] @ (80014fc <HAL_TIM_Base_MspInit+0x68>)
80014ac: f043 0301 orr.w r3, r3, #1
80014b0: 6593 str r3, [r2, #88] @ 0x58
80014b2: 4b12 ldr r3, [pc, #72] @ (80014fc <HAL_TIM_Base_MspInit+0x68>)
80014b4: 6d9b ldr r3, [r3, #88] @ 0x58
80014b6: f003 0301 and.w r3, r3, #1
80014ba: 60fb str r3, [r7, #12]
80014bc: 68fb ldr r3, [r7, #12]
/* TIM2 interrupt Init */
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
80014be: 2200 movs r2, #0
80014c0: 2100 movs r1, #0
80014c2: 201c movs r0, #28
80014c4: f001 ff3f bl 8003346 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM2_IRQn);
80014c8: 201c movs r0, #28
80014ca: f001 ff56 bl 800337a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM16_MspInit 1 */
/* USER CODE END TIM16_MspInit 1 */
}
}
80014ce: e010 b.n 80014f2 <HAL_TIM_Base_MspInit+0x5e>
else if(htim_base->Instance==TIM16)
80014d0: 687b ldr r3, [r7, #4]
80014d2: 681b ldr r3, [r3, #0]
80014d4: 4a0a ldr r2, [pc, #40] @ (8001500 <HAL_TIM_Base_MspInit+0x6c>)
80014d6: 4293 cmp r3, r2
80014d8: d10b bne.n 80014f2 <HAL_TIM_Base_MspInit+0x5e>
__HAL_RCC_TIM16_CLK_ENABLE();
80014da: 4b08 ldr r3, [pc, #32] @ (80014fc <HAL_TIM_Base_MspInit+0x68>)
80014dc: 6e1b ldr r3, [r3, #96] @ 0x60
80014de: 4a07 ldr r2, [pc, #28] @ (80014fc <HAL_TIM_Base_MspInit+0x68>)
80014e0: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80014e4: 6613 str r3, [r2, #96] @ 0x60
80014e6: 4b05 ldr r3, [pc, #20] @ (80014fc <HAL_TIM_Base_MspInit+0x68>)
80014e8: 6e1b ldr r3, [r3, #96] @ 0x60
80014ea: f403 3300 and.w r3, r3, #131072 @ 0x20000
80014ee: 60bb str r3, [r7, #8]
80014f0: 68bb ldr r3, [r7, #8]
}
80014f2: bf00 nop
80014f4: 3710 adds r7, #16
80014f6: 46bd mov sp, r7
80014f8: bd80 pop {r7, pc}
80014fa: bf00 nop
80014fc: 40021000 .word 0x40021000
8001500: 40014400 .word 0x40014400
08001504 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8001504: b580 push {r7, lr}
8001506: b088 sub sp, #32
8001508: af00 add r7, sp, #0
800150a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800150c: f107 030c add.w r3, r7, #12
8001510: 2200 movs r2, #0
8001512: 601a str r2, [r3, #0]
8001514: 605a str r2, [r3, #4]
8001516: 609a str r2, [r3, #8]
8001518: 60da str r2, [r3, #12]
800151a: 611a str r2, [r3, #16]
if(htim->Instance==TIM16)
800151c: 687b ldr r3, [r7, #4]
800151e: 681b ldr r3, [r3, #0]
8001520: 4a12 ldr r2, [pc, #72] @ (800156c <HAL_TIM_MspPostInit+0x68>)
8001522: 4293 cmp r3, r2
8001524: d11d bne.n 8001562 <HAL_TIM_MspPostInit+0x5e>
{
/* USER CODE BEGIN TIM16_MspPostInit 0 */
/* USER CODE END TIM16_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001526: 4b12 ldr r3, [pc, #72] @ (8001570 <HAL_TIM_MspPostInit+0x6c>)
8001528: 6cdb ldr r3, [r3, #76] @ 0x4c
800152a: 4a11 ldr r2, [pc, #68] @ (8001570 <HAL_TIM_MspPostInit+0x6c>)
800152c: f043 0301 orr.w r3, r3, #1
8001530: 64d3 str r3, [r2, #76] @ 0x4c
8001532: 4b0f ldr r3, [pc, #60] @ (8001570 <HAL_TIM_MspPostInit+0x6c>)
8001534: 6cdb ldr r3, [r3, #76] @ 0x4c
8001536: f003 0301 and.w r3, r3, #1
800153a: 60bb str r3, [r7, #8]
800153c: 68bb ldr r3, [r7, #8]
/**TIM16 GPIO Configuration
PA12 ------> TIM16_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_12;
800153e: f44f 5380 mov.w r3, #4096 @ 0x1000
8001542: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001544: 2302 movs r3, #2
8001546: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001548: 2300 movs r3, #0
800154a: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800154c: 2300 movs r3, #0
800154e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM16;
8001550: 2301 movs r3, #1
8001552: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001554: f107 030c add.w r3, r7, #12
8001558: 4619 mov r1, r3
800155a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800155e: f001 ffe7 bl 8003530 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM16_MspPostInit 1 */
/* USER CODE END TIM16_MspPostInit 1 */
}
}
8001562: bf00 nop
8001564: 3720 adds r7, #32
8001566: 46bd mov sp, r7
8001568: bd80 pop {r7, pc}
800156a: bf00 nop
800156c: 40014400 .word 0x40014400
8001570: 40021000 .word 0x40021000
08001574 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001574: b580 push {r7, lr}
8001576: b09a sub sp, #104 @ 0x68
8001578: af00 add r7, sp, #0
800157a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800157c: f107 0354 add.w r3, r7, #84 @ 0x54
8001580: 2200 movs r2, #0
8001582: 601a str r2, [r3, #0]
8001584: 605a str r2, [r3, #4]
8001586: 609a str r2, [r3, #8]
8001588: 60da str r2, [r3, #12]
800158a: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800158c: f107 0310 add.w r3, r7, #16
8001590: 2244 movs r2, #68 @ 0x44
8001592: 2100 movs r1, #0
8001594: 4618 mov r0, r3
8001596: f006 fd37 bl 8008008 <memset>
if(huart->Instance==USART2)
800159a: 687b ldr r3, [r7, #4]
800159c: 681b ldr r3, [r3, #0]
800159e: 4a23 ldr r2, [pc, #140] @ (800162c <HAL_UART_MspInit+0xb8>)
80015a0: 4293 cmp r3, r2
80015a2: d13e bne.n 8001622 <HAL_UART_MspInit+0xae>
/* USER CODE END USART2_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
80015a4: 2302 movs r3, #2
80015a6: 613b str r3, [r7, #16]
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
80015a8: 2300 movs r3, #0
80015aa: 61bb str r3, [r7, #24]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
80015ac: f107 0310 add.w r3, r7, #16
80015b0: 4618 mov r0, r3
80015b2: f002 ff39 bl 8004428 <HAL_RCCEx_PeriphCLKConfig>
80015b6: 4603 mov r3, r0
80015b8: 2b00 cmp r3, #0
80015ba: d001 beq.n 80015c0 <HAL_UART_MspInit+0x4c>
{
Error_Handler();
80015bc: f7ff feb4 bl 8001328 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
80015c0: 4b1b ldr r3, [pc, #108] @ (8001630 <HAL_UART_MspInit+0xbc>)
80015c2: 6d9b ldr r3, [r3, #88] @ 0x58
80015c4: 4a1a ldr r2, [pc, #104] @ (8001630 <HAL_UART_MspInit+0xbc>)
80015c6: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80015ca: 6593 str r3, [r2, #88] @ 0x58
80015cc: 4b18 ldr r3, [pc, #96] @ (8001630 <HAL_UART_MspInit+0xbc>)
80015ce: 6d9b ldr r3, [r3, #88] @ 0x58
80015d0: f403 3300 and.w r3, r3, #131072 @ 0x20000
80015d4: 60fb str r3, [r7, #12]
80015d6: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80015d8: 4b15 ldr r3, [pc, #84] @ (8001630 <HAL_UART_MspInit+0xbc>)
80015da: 6cdb ldr r3, [r3, #76] @ 0x4c
80015dc: 4a14 ldr r2, [pc, #80] @ (8001630 <HAL_UART_MspInit+0xbc>)
80015de: f043 0301 orr.w r3, r3, #1
80015e2: 64d3 str r3, [r2, #76] @ 0x4c
80015e4: 4b12 ldr r3, [pc, #72] @ (8001630 <HAL_UART_MspInit+0xbc>)
80015e6: 6cdb ldr r3, [r3, #76] @ 0x4c
80015e8: f003 0301 and.w r3, r3, #1
80015ec: 60bb str r3, [r7, #8]
80015ee: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin;
80015f0: 230c movs r3, #12
80015f2: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80015f4: 2302 movs r3, #2
80015f6: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
80015f8: 2300 movs r3, #0
80015fa: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80015fc: 2300 movs r3, #0
80015fe: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8001600: 2307 movs r3, #7
8001602: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001604: f107 0354 add.w r3, r7, #84 @ 0x54
8001608: 4619 mov r1, r3
800160a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
800160e: f001 ff8f bl 8003530 <HAL_GPIO_Init>
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
8001612: 2200 movs r2, #0
8001614: 2100 movs r1, #0
8001616: 2026 movs r0, #38 @ 0x26
8001618: f001 fe95 bl 8003346 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
800161c: 2026 movs r0, #38 @ 0x26
800161e: f001 feac bl 800337a <HAL_NVIC_EnableIRQ>
/* USER CODE END USART2_MspInit 1 */
}
}
8001622: bf00 nop
8001624: 3768 adds r7, #104 @ 0x68
8001626: 46bd mov sp, r7
8001628: bd80 pop {r7, pc}
800162a: bf00 nop
800162c: 40004400 .word 0x40004400
8001630: 40021000 .word 0x40021000
08001634 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001634: b480 push {r7}
8001636: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001638: bf00 nop
800163a: e7fd b.n 8001638 <NMI_Handler+0x4>
0800163c <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800163c: b480 push {r7}
800163e: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001640: bf00 nop
8001642: e7fd b.n 8001640 <HardFault_Handler+0x4>
08001644 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001644: b480 push {r7}
8001646: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001648: bf00 nop
800164a: e7fd b.n 8001648 <MemManage_Handler+0x4>
0800164c <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800164c: b480 push {r7}
800164e: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001650: bf00 nop
8001652: e7fd b.n 8001650 <BusFault_Handler+0x4>
08001654 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001654: b480 push {r7}
8001656: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001658: bf00 nop
800165a: e7fd b.n 8001658 <UsageFault_Handler+0x4>
0800165c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800165c: b480 push {r7}
800165e: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001660: bf00 nop
8001662: 46bd mov sp, r7
8001664: f85d 7b04 ldr.w r7, [sp], #4
8001668: 4770 bx lr
0800166a <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800166a: b480 push {r7}
800166c: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800166e: bf00 nop
8001670: 46bd mov sp, r7
8001672: f85d 7b04 ldr.w r7, [sp], #4
8001676: 4770 bx lr
08001678 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001678: b480 push {r7}
800167a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800167c: bf00 nop
800167e: 46bd mov sp, r7
8001680: f85d 7b04 ldr.w r7, [sp], #4
8001684: 4770 bx lr
08001686 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001686: b580 push {r7, lr}
8001688: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
800168a: f000 f8a5 bl 80017d8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800168e: bf00 nop
8001690: bd80 pop {r7, pc}
...
08001694 <TIM2_IRQHandler>:
/**
* @brief This function handles TIM2 global interrupt.
*/
void TIM2_IRQHandler(void)
{
8001694: b580 push {r7, lr}
8001696: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_IRQn 0 */
/* USER CODE END TIM2_IRQn 0 */
HAL_TIM_IRQHandler(&htim2);
8001698: 4802 ldr r0, [pc, #8] @ (80016a4 <TIM2_IRQHandler+0x10>)
800169a: f003 fa6d bl 8004b78 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM2_IRQn 1 */
/* USER CODE END TIM2_IRQn 1 */
}
800169e: bf00 nop
80016a0: bd80 pop {r7, pc}
80016a2: bf00 nop
80016a4: 2000011c .word 0x2000011c
080016a8 <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
*/
void USART2_IRQHandler(void)
{
80016a8: b580 push {r7, lr}
80016aa: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
80016ac: 4802 ldr r0, [pc, #8] @ (80016b8 <USART2_IRQHandler+0x10>)
80016ae: f004 fcc5 bl 800603c <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
80016b2: bf00 nop
80016b4: bd80 pop {r7, pc}
80016b6: bf00 nop
80016b8: 200001b4 .word 0x200001b4
080016bc <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
80016bc: b480 push {r7}
80016be: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
80016c0: 4b06 ldr r3, [pc, #24] @ (80016dc <SystemInit+0x20>)
80016c2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80016c6: 4a05 ldr r2, [pc, #20] @ (80016dc <SystemInit+0x20>)
80016c8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80016cc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80016d0: bf00 nop
80016d2: 46bd mov sp, r7
80016d4: f85d 7b04 ldr.w r7, [sp], #4
80016d8: 4770 bx lr
80016da: bf00 nop
80016dc: e000ed00 .word 0xe000ed00
080016e0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
80016e0: 480d ldr r0, [pc, #52] @ (8001718 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
80016e2: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
80016e4: f7ff ffea bl 80016bc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80016e8: 480c ldr r0, [pc, #48] @ (800171c <LoopForever+0x6>)
ldr r1, =_edata
80016ea: 490d ldr r1, [pc, #52] @ (8001720 <LoopForever+0xa>)
ldr r2, =_sidata
80016ec: 4a0d ldr r2, [pc, #52] @ (8001724 <LoopForever+0xe>)
movs r3, #0
80016ee: 2300 movs r3, #0
b LoopCopyDataInit
80016f0: e002 b.n 80016f8 <LoopCopyDataInit>
080016f2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80016f2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80016f4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80016f6: 3304 adds r3, #4
080016f8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80016f8: 18c4 adds r4, r0, r3
cmp r4, r1
80016fa: 428c cmp r4, r1
bcc CopyDataInit
80016fc: d3f9 bcc.n 80016f2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80016fe: 4a0a ldr r2, [pc, #40] @ (8001728 <LoopForever+0x12>)
ldr r4, =_ebss
8001700: 4c0a ldr r4, [pc, #40] @ (800172c <LoopForever+0x16>)
movs r3, #0
8001702: 2300 movs r3, #0
b LoopFillZerobss
8001704: e001 b.n 800170a <LoopFillZerobss>
08001706 <FillZerobss>:
FillZerobss:
str r3, [r2]
8001706: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001708: 3204 adds r2, #4
0800170a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800170a: 42a2 cmp r2, r4
bcc FillZerobss
800170c: d3fb bcc.n 8001706 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800170e: f006 fc83 bl 8008018 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001712: f7fe ff17 bl 8000544 <main>
08001716 <LoopForever>:
LoopForever:
b LoopForever
8001716: e7fe b.n 8001716 <LoopForever>
ldr r0, =_estack
8001718: 20008000 .word 0x20008000
ldr r0, =_sdata
800171c: 20000000 .word 0x20000000
ldr r1, =_edata
8001720: 20000028 .word 0x20000028
ldr r2, =_sidata
8001724: 080080fc .word 0x080080fc
ldr r2, =_sbss
8001728: 20000028 .word 0x20000028
ldr r4, =_ebss
800172c: 20000364 .word 0x20000364
08001730 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001730: e7fe b.n 8001730 <ADC1_2_IRQHandler>
08001732 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001732: b580 push {r7, lr}
8001734: b082 sub sp, #8
8001736: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001738: 2300 movs r3, #0
800173a: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800173c: 2003 movs r0, #3
800173e: f001 fdf7 bl 8003330 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001742: 2000 movs r0, #0
8001744: f000 f80e bl 8001764 <HAL_InitTick>
8001748: 4603 mov r3, r0
800174a: 2b00 cmp r3, #0
800174c: d002 beq.n 8001754 <HAL_Init+0x22>
{
status = HAL_ERROR;
800174e: 2301 movs r3, #1
8001750: 71fb strb r3, [r7, #7]
8001752: e001 b.n 8001758 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001754: f7ff fdee bl 8001334 <HAL_MspInit>
}
/* Return function status */
return status;
8001758: 79fb ldrb r3, [r7, #7]
}
800175a: 4618 mov r0, r3
800175c: 3708 adds r7, #8
800175e: 46bd mov sp, r7
8001760: bd80 pop {r7, pc}
...
08001764 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001764: b580 push {r7, lr}
8001766: b084 sub sp, #16
8001768: af00 add r7, sp, #0
800176a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800176c: 2300 movs r3, #0
800176e: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001770: 4b16 ldr r3, [pc, #88] @ (80017cc <HAL_InitTick+0x68>)
8001772: 681b ldr r3, [r3, #0]
8001774: 2b00 cmp r3, #0
8001776: d022 beq.n 80017be <HAL_InitTick+0x5a>
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8001778: 4b15 ldr r3, [pc, #84] @ (80017d0 <HAL_InitTick+0x6c>)
800177a: 681a ldr r2, [r3, #0]
800177c: 4b13 ldr r3, [pc, #76] @ (80017cc <HAL_InitTick+0x68>)
800177e: 681b ldr r3, [r3, #0]
8001780: f44f 717a mov.w r1, #1000 @ 0x3e8
8001784: fbb1 f3f3 udiv r3, r1, r3
8001788: fbb2 f3f3 udiv r3, r2, r3
800178c: 4618 mov r0, r3
800178e: f001 fe02 bl 8003396 <HAL_SYSTICK_Config>
8001792: 4603 mov r3, r0
8001794: 2b00 cmp r3, #0
8001796: d10f bne.n 80017b8 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001798: 687b ldr r3, [r7, #4]
800179a: 2b0f cmp r3, #15
800179c: d809 bhi.n 80017b2 <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800179e: 2200 movs r2, #0
80017a0: 6879 ldr r1, [r7, #4]
80017a2: f04f 30ff mov.w r0, #4294967295
80017a6: f001 fdce bl 8003346 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80017aa: 4a0a ldr r2, [pc, #40] @ (80017d4 <HAL_InitTick+0x70>)
80017ac: 687b ldr r3, [r7, #4]
80017ae: 6013 str r3, [r2, #0]
80017b0: e007 b.n 80017c2 <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
80017b2: 2301 movs r3, #1
80017b4: 73fb strb r3, [r7, #15]
80017b6: e004 b.n 80017c2 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
80017b8: 2301 movs r3, #1
80017ba: 73fb strb r3, [r7, #15]
80017bc: e001 b.n 80017c2 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
80017be: 2301 movs r3, #1
80017c0: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
80017c2: 7bfb ldrb r3, [r7, #15]
}
80017c4: 4618 mov r0, r3
80017c6: 3710 adds r7, #16
80017c8: 46bd mov sp, r7
80017ca: bd80 pop {r7, pc}
80017cc: 20000024 .word 0x20000024
80017d0: 2000001c .word 0x2000001c
80017d4: 20000020 .word 0x20000020
080017d8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80017d8: b480 push {r7}
80017da: af00 add r7, sp, #0
uwTick += uwTickFreq;
80017dc: 4b05 ldr r3, [pc, #20] @ (80017f4 <HAL_IncTick+0x1c>)
80017de: 681a ldr r2, [r3, #0]
80017e0: 4b05 ldr r3, [pc, #20] @ (80017f8 <HAL_IncTick+0x20>)
80017e2: 681b ldr r3, [r3, #0]
80017e4: 4413 add r3, r2
80017e6: 4a03 ldr r2, [pc, #12] @ (80017f4 <HAL_IncTick+0x1c>)
80017e8: 6013 str r3, [r2, #0]
}
80017ea: bf00 nop
80017ec: 46bd mov sp, r7
80017ee: f85d 7b04 ldr.w r7, [sp], #4
80017f2: 4770 bx lr
80017f4: 20000360 .word 0x20000360
80017f8: 20000024 .word 0x20000024
080017fc <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80017fc: b480 push {r7}
80017fe: af00 add r7, sp, #0
return uwTick;
8001800: 4b03 ldr r3, [pc, #12] @ (8001810 <HAL_GetTick+0x14>)
8001802: 681b ldr r3, [r3, #0]
}
8001804: 4618 mov r0, r3
8001806: 46bd mov sp, r7
8001808: f85d 7b04 ldr.w r7, [sp], #4
800180c: 4770 bx lr
800180e: bf00 nop
8001810: 20000360 .word 0x20000360
08001814 <LL_ADC_SetCommonClock>:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
8001814: b480 push {r7}
8001816: b083 sub sp, #12
8001818: af00 add r7, sp, #0
800181a: 6078 str r0, [r7, #4]
800181c: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
800181e: 687b ldr r3, [r7, #4]
8001820: 689b ldr r3, [r3, #8]
8001822: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000
8001826: 683b ldr r3, [r7, #0]
8001828: 431a orrs r2, r3
800182a: 687b ldr r3, [r7, #4]
800182c: 609a str r2, [r3, #8]
}
800182e: bf00 nop
8001830: 370c adds r7, #12
8001832: 46bd mov sp, r7
8001834: f85d 7b04 ldr.w r7, [sp], #4
8001838: 4770 bx lr
0800183a <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
800183a: b480 push {r7}
800183c: b083 sub sp, #12
800183e: af00 add r7, sp, #0
8001840: 6078 str r0, [r7, #4]
8001842: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
8001844: 687b ldr r3, [r7, #4]
8001846: 689b ldr r3, [r3, #8]
8001848: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000
800184c: 683b ldr r3, [r7, #0]
800184e: 431a orrs r2, r3
8001850: 687b ldr r3, [r7, #4]
8001852: 609a str r2, [r3, #8]
}
8001854: bf00 nop
8001856: 370c adds r7, #12
8001858: 46bd mov sp, r7
800185a: f85d 7b04 ldr.w r7, [sp], #4
800185e: 4770 bx lr
08001860 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001860: b480 push {r7}
8001862: b083 sub sp, #12
8001864: af00 add r7, sp, #0
8001866: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
8001868: 687b ldr r3, [r7, #4]
800186a: 689b ldr r3, [r3, #8]
800186c: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000
}
8001870: 4618 mov r0, r3
8001872: 370c adds r7, #12
8001874: 46bd mov sp, r7
8001876: f85d 7b04 ldr.w r7, [sp], #4
800187a: 4770 bx lr
0800187c <LL_ADC_SetOffset>:
* (fADC) to convert in 12-bit resolution.\n
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
800187c: b480 push {r7}
800187e: b087 sub sp, #28
8001880: af00 add r7, sp, #0
8001882: 60f8 str r0, [r7, #12]
8001884: 60b9 str r1, [r7, #8]
8001886: 607a str r2, [r7, #4]
8001888: 603b str r3, [r7, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
800188a: 68fb ldr r3, [r7, #12]
800188c: 3360 adds r3, #96 @ 0x60
800188e: 461a mov r2, r3
8001890: 68bb ldr r3, [r7, #8]
8001892: 009b lsls r3, r3, #2
8001894: 4413 add r3, r2
8001896: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001898: 697b ldr r3, [r7, #20]
800189a: 681a ldr r2, [r3, #0]
800189c: 4b08 ldr r3, [pc, #32] @ (80018c0 <LL_ADC_SetOffset+0x44>)
800189e: 4013 ands r3, r2
80018a0: 687a ldr r2, [r7, #4]
80018a2: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000
80018a6: 683a ldr r2, [r7, #0]
80018a8: 430a orrs r2, r1
80018aa: 4313 orrs r3, r2
80018ac: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
80018b0: 697b ldr r3, [r7, #20]
80018b2: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
80018b4: bf00 nop
80018b6: 371c adds r7, #28
80018b8: 46bd mov sp, r7
80018ba: f85d 7b04 ldr.w r7, [sp], #4
80018be: 4770 bx lr
80018c0: 03fff000 .word 0x03fff000
080018c4 <LL_ADC_GetOffsetChannel>:
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
80018c4: b480 push {r7}
80018c6: b085 sub sp, #20
80018c8: af00 add r7, sp, #0
80018ca: 6078 str r0, [r7, #4]
80018cc: 6039 str r1, [r7, #0]
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
80018ce: 687b ldr r3, [r7, #4]
80018d0: 3360 adds r3, #96 @ 0x60
80018d2: 461a mov r2, r3
80018d4: 683b ldr r3, [r7, #0]
80018d6: 009b lsls r3, r3, #2
80018d8: 4413 add r3, r2
80018da: 60fb str r3, [r7, #12]
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
80018dc: 68fb ldr r3, [r7, #12]
80018de: 681b ldr r3, [r3, #0]
80018e0: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
}
80018e4: 4618 mov r0, r3
80018e6: 3714 adds r7, #20
80018e8: 46bd mov sp, r7
80018ea: f85d 7b04 ldr.w r7, [sp], #4
80018ee: 4770 bx lr
080018f0 <LL_ADC_SetOffsetState>:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
80018f0: b480 push {r7}
80018f2: b087 sub sp, #28
80018f4: af00 add r7, sp, #0
80018f6: 60f8 str r0, [r7, #12]
80018f8: 60b9 str r1, [r7, #8]
80018fa: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
80018fc: 68fb ldr r3, [r7, #12]
80018fe: 3360 adds r3, #96 @ 0x60
8001900: 461a mov r2, r3
8001902: 68bb ldr r3, [r7, #8]
8001904: 009b lsls r3, r3, #2
8001906: 4413 add r3, r2
8001908: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
800190a: 697b ldr r3, [r7, #20]
800190c: 681b ldr r3, [r3, #0]
800190e: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001912: 687b ldr r3, [r7, #4]
8001914: 431a orrs r2, r3
8001916: 697b ldr r3, [r7, #20]
8001918: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
800191a: bf00 nop
800191c: 371c adds r7, #28
800191e: 46bd mov sp, r7
8001920: f85d 7b04 ldr.w r7, [sp], #4
8001924: 4770 bx lr
08001926 <LL_ADC_SetOffsetSign>:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
8001926: b480 push {r7}
8001928: b087 sub sp, #28
800192a: af00 add r7, sp, #0
800192c: 60f8 str r0, [r7, #12]
800192e: 60b9 str r1, [r7, #8]
8001930: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001932: 68fb ldr r3, [r7, #12]
8001934: 3360 adds r3, #96 @ 0x60
8001936: 461a mov r2, r3
8001938: 68bb ldr r3, [r7, #8]
800193a: 009b lsls r3, r3, #2
800193c: 4413 add r3, r2
800193e: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001940: 697b ldr r3, [r7, #20]
8001942: 681b ldr r3, [r3, #0]
8001944: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
8001948: 687b ldr r3, [r7, #4]
800194a: 431a orrs r2, r3
800194c: 697b ldr r3, [r7, #20]
800194e: 601a str r2, [r3, #0]
ADC_OFR1_OFFSETPOS,
OffsetSign);
}
8001950: bf00 nop
8001952: 371c adds r7, #28
8001954: 46bd mov sp, r7
8001956: f85d 7b04 ldr.w r7, [sp], #4
800195a: 4770 bx lr
0800195c <LL_ADC_SetOffsetSaturation>:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
800195c: b480 push {r7}
800195e: b087 sub sp, #28
8001960: af00 add r7, sp, #0
8001962: 60f8 str r0, [r7, #12]
8001964: 60b9 str r1, [r7, #8]
8001966: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001968: 68fb ldr r3, [r7, #12]
800196a: 3360 adds r3, #96 @ 0x60
800196c: 461a mov r2, r3
800196e: 68bb ldr r3, [r7, #8]
8001970: 009b lsls r3, r3, #2
8001972: 4413 add r3, r2
8001974: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001976: 697b ldr r3, [r7, #20]
8001978: 681b ldr r3, [r3, #0]
800197a: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
800197e: 687b ldr r3, [r7, #4]
8001980: 431a orrs r2, r3
8001982: 697b ldr r3, [r7, #20]
8001984: 601a str r2, [r3, #0]
ADC_OFR1_SATEN,
OffsetSaturation);
}
8001986: bf00 nop
8001988: 371c adds r7, #28
800198a: 46bd mov sp, r7
800198c: f85d 7b04 ldr.w r7, [sp], #4
8001990: 4770 bx lr
08001992 <LL_ADC_SetSamplingTimeCommonConfig>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
8001992: b480 push {r7}
8001994: b083 sub sp, #12
8001996: af00 add r7, sp, #0
8001998: 6078 str r0, [r7, #4]
800199a: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
800199c: 687b ldr r3, [r7, #4]
800199e: 695b ldr r3, [r3, #20]
80019a0: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
80019a4: 683b ldr r3, [r7, #0]
80019a6: 431a orrs r2, r3
80019a8: 687b ldr r3, [r7, #4]
80019aa: 615a str r2, [r3, #20]
}
80019ac: bf00 nop
80019ae: 370c adds r7, #12
80019b0: 46bd mov sp, r7
80019b2: f85d 7b04 ldr.w r7, [sp], #4
80019b6: 4770 bx lr
080019b8 <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
{
80019b8: b480 push {r7}
80019ba: b083 sub sp, #12
80019bc: af00 add r7, sp, #0
80019be: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
80019c0: 687b ldr r3, [r7, #4]
80019c2: 68db ldr r3, [r3, #12]
80019c4: f403 6340 and.w r3, r3, #3072 @ 0xc00
80019c8: 2b00 cmp r3, #0
80019ca: d101 bne.n 80019d0 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
80019cc: 2301 movs r3, #1
80019ce: e000 b.n 80019d2 <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
80019d0: 2300 movs r3, #0
}
80019d2: 4618 mov r0, r3
80019d4: 370c adds r7, #12
80019d6: 46bd mov sp, r7
80019d8: f85d 7b04 ldr.w r7, [sp], #4
80019dc: 4770 bx lr
080019de <LL_ADC_REG_SetSequencerRanks>:
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
* (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
80019de: b480 push {r7}
80019e0: b087 sub sp, #28
80019e2: af00 add r7, sp, #0
80019e4: 60f8 str r0, [r7, #12]
80019e6: 60b9 str r1, [r7, #8]
80019e8: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
80019ea: 68fb ldr r3, [r7, #12]
80019ec: 3330 adds r3, #48 @ 0x30
80019ee: 461a mov r2, r3
80019f0: 68bb ldr r3, [r7, #8]
80019f2: 0a1b lsrs r3, r3, #8
80019f4: 009b lsls r3, r3, #2
80019f6: f003 030c and.w r3, r3, #12
80019fa: 4413 add r3, r2
80019fc: 617b str r3, [r7, #20]
((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
80019fe: 697b ldr r3, [r7, #20]
8001a00: 681a ldr r2, [r3, #0]
8001a02: 68bb ldr r3, [r7, #8]
8001a04: f003 031f and.w r3, r3, #31
8001a08: 211f movs r1, #31
8001a0a: fa01 f303 lsl.w r3, r1, r3
8001a0e: 43db mvns r3, r3
8001a10: 401a ands r2, r3
8001a12: 687b ldr r3, [r7, #4]
8001a14: 0e9b lsrs r3, r3, #26
8001a16: f003 011f and.w r1, r3, #31
8001a1a: 68bb ldr r3, [r7, #8]
8001a1c: f003 031f and.w r3, r3, #31
8001a20: fa01 f303 lsl.w r3, r1, r3
8001a24: 431a orrs r2, r3
8001a26: 697b ldr r3, [r7, #20]
8001a28: 601a str r2, [r3, #0]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
8001a2a: bf00 nop
8001a2c: 371c adds r7, #28
8001a2e: 46bd mov sp, r7
8001a30: f85d 7b04 ldr.w r7, [sp], #4
8001a34: 4770 bx lr
08001a36 <LL_ADC_SetChannelSamplingTime>:
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
8001a36: b480 push {r7}
8001a38: b087 sub sp, #28
8001a3a: af00 add r7, sp, #0
8001a3c: 60f8 str r0, [r7, #12]
8001a3e: 60b9 str r1, [r7, #8]
8001a40: 607a str r2, [r7, #4]
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
8001a42: 68fb ldr r3, [r7, #12]
8001a44: 3314 adds r3, #20
8001a46: 461a mov r2, r3
8001a48: 68bb ldr r3, [r7, #8]
8001a4a: 0e5b lsrs r3, r3, #25
8001a4c: 009b lsls r3, r3, #2
8001a4e: f003 0304 and.w r3, r3, #4
8001a52: 4413 add r3, r2
8001a54: 617b str r3, [r7, #20]
((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
8001a56: 697b ldr r3, [r7, #20]
8001a58: 681a ldr r2, [r3, #0]
8001a5a: 68bb ldr r3, [r7, #8]
8001a5c: 0d1b lsrs r3, r3, #20
8001a5e: f003 031f and.w r3, r3, #31
8001a62: 2107 movs r1, #7
8001a64: fa01 f303 lsl.w r3, r1, r3
8001a68: 43db mvns r3, r3
8001a6a: 401a ands r2, r3
8001a6c: 68bb ldr r3, [r7, #8]
8001a6e: 0d1b lsrs r3, r3, #20
8001a70: f003 031f and.w r3, r3, #31
8001a74: 6879 ldr r1, [r7, #4]
8001a76: fa01 f303 lsl.w r3, r1, r3
8001a7a: 431a orrs r2, r3
8001a7c: 697b ldr r3, [r7, #20]
8001a7e: 601a str r2, [r3, #0]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
8001a80: bf00 nop
8001a82: 371c adds r7, #28
8001a84: 46bd mov sp, r7
8001a86: f85d 7b04 ldr.w r7, [sp], #4
8001a8a: 4770 bx lr
08001a8c <LL_ADC_SetChannelSingleDiff>:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
8001a8c: b480 push {r7}
8001a8e: b085 sub sp, #20
8001a90: af00 add r7, sp, #0
8001a92: 60f8 str r0, [r7, #12]
8001a94: 60b9 str r1, [r7, #8]
8001a96: 607a str r2, [r7, #4]
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
8001a98: 68fb ldr r3, [r7, #12]
8001a9a: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0
8001a9e: 68bb ldr r3, [r7, #8]
8001aa0: f3c3 0312 ubfx r3, r3, #0, #19
8001aa4: 43db mvns r3, r3
8001aa6: 401a ands r2, r3
8001aa8: 687b ldr r3, [r7, #4]
8001aaa: f003 0318 and.w r3, r3, #24
8001aae: 4908 ldr r1, [pc, #32] @ (8001ad0 <LL_ADC_SetChannelSingleDiff+0x44>)
8001ab0: 40d9 lsrs r1, r3
8001ab2: 68bb ldr r3, [r7, #8]
8001ab4: 400b ands r3, r1
8001ab6: f3c3 0312 ubfx r3, r3, #0, #19
8001aba: 431a orrs r2, r3
8001abc: 68fb ldr r3, [r7, #12]
8001abe: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
& (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
}
8001ac2: bf00 nop
8001ac4: 3714 adds r7, #20
8001ac6: 46bd mov sp, r7
8001ac8: f85d 7b04 ldr.w r7, [sp], #4
8001acc: 4770 bx lr
8001ace: bf00 nop
8001ad0: 0007ffff .word 0x0007ffff
08001ad4 <LL_ADC_GetMultimode>:
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001ad4: b480 push {r7}
8001ad6: b083 sub sp, #12
8001ad8: af00 add r7, sp, #0
8001ada: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
8001adc: 687b ldr r3, [r7, #4]
8001ade: 689b ldr r3, [r3, #8]
8001ae0: f003 031f and.w r3, r3, #31
}
8001ae4: 4618 mov r0, r3
8001ae6: 370c adds r7, #12
8001ae8: 46bd mov sp, r7
8001aea: f85d 7b04 ldr.w r7, [sp], #4
8001aee: 4770 bx lr
08001af0 <LL_ADC_GetMultiDMATransfer>:
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001af0: b480 push {r7}
8001af2: b083 sub sp, #12
8001af4: af00 add r7, sp, #0
8001af6: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
8001af8: 687b ldr r3, [r7, #4]
8001afa: 689b ldr r3, [r3, #8]
8001afc: f403 4360 and.w r3, r3, #57344 @ 0xe000
}
8001b00: 4618 mov r0, r3
8001b02: 370c adds r7, #12
8001b04: 46bd mov sp, r7
8001b06: f85d 7b04 ldr.w r7, [sp], #4
8001b0a: 4770 bx lr
08001b0c <LL_ADC_DisableDeepPowerDown>:
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
8001b0c: b480 push {r7}
8001b0e: b083 sub sp, #12
8001b10: af00 add r7, sp, #0
8001b12: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
8001b14: 687b ldr r3, [r7, #4]
8001b16: 689b ldr r3, [r3, #8]
8001b18: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000
8001b1c: f023 033f bic.w r3, r3, #63 @ 0x3f
8001b20: 687a ldr r2, [r7, #4]
8001b22: 6093 str r3, [r2, #8]
}
8001b24: bf00 nop
8001b26: 370c adds r7, #12
8001b28: 46bd mov sp, r7
8001b2a: f85d 7b04 ldr.w r7, [sp], #4
8001b2e: 4770 bx lr
08001b30 <LL_ADC_IsDeepPowerDownEnabled>:
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
{
8001b30: b480 push {r7}
8001b32: b083 sub sp, #12
8001b34: af00 add r7, sp, #0
8001b36: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 689b ldr r3, [r3, #8]
8001b3c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8001b40: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8001b44: d101 bne.n 8001b4a <LL_ADC_IsDeepPowerDownEnabled+0x1a>
8001b46: 2301 movs r3, #1
8001b48: e000 b.n 8001b4c <LL_ADC_IsDeepPowerDownEnabled+0x1c>
8001b4a: 2300 movs r3, #0
}
8001b4c: 4618 mov r0, r3
8001b4e: 370c adds r7, #12
8001b50: 46bd mov sp, r7
8001b52: f85d 7b04 ldr.w r7, [sp], #4
8001b56: 4770 bx lr
08001b58 <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
8001b58: b480 push {r7}
8001b5a: b083 sub sp, #12
8001b5c: af00 add r7, sp, #0
8001b5e: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001b60: 687b ldr r3, [r7, #4]
8001b62: 689b ldr r3, [r3, #8]
8001b64: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000
8001b68: f023 033f bic.w r3, r3, #63 @ 0x3f
8001b6c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000
8001b70: 687b ldr r3, [r7, #4]
8001b72: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
8001b74: bf00 nop
8001b76: 370c adds r7, #12
8001b78: 46bd mov sp, r7
8001b7a: f85d 7b04 ldr.w r7, [sp], #4
8001b7e: 4770 bx lr
08001b80 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
{
8001b80: b480 push {r7}
8001b82: b083 sub sp, #12
8001b84: af00 add r7, sp, #0
8001b86: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8001b88: 687b ldr r3, [r7, #4]
8001b8a: 689b ldr r3, [r3, #8]
8001b8c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001b90: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8001b94: d101 bne.n 8001b9a <LL_ADC_IsInternalRegulatorEnabled+0x1a>
8001b96: 2301 movs r3, #1
8001b98: e000 b.n 8001b9c <LL_ADC_IsInternalRegulatorEnabled+0x1c>
8001b9a: 2300 movs r3, #0
}
8001b9c: 4618 mov r0, r3
8001b9e: 370c adds r7, #12
8001ba0: 46bd mov sp, r7
8001ba2: f85d 7b04 ldr.w r7, [sp], #4
8001ba6: 4770 bx lr
08001ba8 <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
8001ba8: b480 push {r7}
8001baa: b083 sub sp, #12
8001bac: af00 add r7, sp, #0
8001bae: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001bb0: 687b ldr r3, [r7, #4]
8001bb2: 689b ldr r3, [r3, #8]
8001bb4: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001bb8: f023 033f bic.w r3, r3, #63 @ 0x3f
8001bbc: f043 0201 orr.w r2, r3, #1
8001bc0: 687b ldr r3, [r7, #4]
8001bc2: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
8001bc4: bf00 nop
8001bc6: 370c adds r7, #12
8001bc8: 46bd mov sp, r7
8001bca: f85d 7b04 ldr.w r7, [sp], #4
8001bce: 4770 bx lr
08001bd0 <LL_ADC_Disable>:
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
8001bd0: b480 push {r7}
8001bd2: b083 sub sp, #12
8001bd4: af00 add r7, sp, #0
8001bd6: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001bd8: 687b ldr r3, [r7, #4]
8001bda: 689b ldr r3, [r3, #8]
8001bdc: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001be0: f023 033f bic.w r3, r3, #63 @ 0x3f
8001be4: f043 0202 orr.w r2, r3, #2
8001be8: 687b ldr r3, [r7, #4]
8001bea: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
8001bec: bf00 nop
8001bee: 370c adds r7, #12
8001bf0: 46bd mov sp, r7
8001bf2: f85d 7b04 ldr.w r7, [sp], #4
8001bf6: 4770 bx lr
08001bf8 <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
{
8001bf8: b480 push {r7}
8001bfa: b083 sub sp, #12
8001bfc: af00 add r7, sp, #0
8001bfe: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8001c00: 687b ldr r3, [r7, #4]
8001c02: 689b ldr r3, [r3, #8]
8001c04: f003 0301 and.w r3, r3, #1
8001c08: 2b01 cmp r3, #1
8001c0a: d101 bne.n 8001c10 <LL_ADC_IsEnabled+0x18>
8001c0c: 2301 movs r3, #1
8001c0e: e000 b.n 8001c12 <LL_ADC_IsEnabled+0x1a>
8001c10: 2300 movs r3, #0
}
8001c12: 4618 mov r0, r3
8001c14: 370c adds r7, #12
8001c16: 46bd mov sp, r7
8001c18: f85d 7b04 ldr.w r7, [sp], #4
8001c1c: 4770 bx lr
08001c1e <LL_ADC_IsDisableOngoing>:
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
{
8001c1e: b480 push {r7}
8001c20: b083 sub sp, #12
8001c22: af00 add r7, sp, #0
8001c24: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
8001c26: 687b ldr r3, [r7, #4]
8001c28: 689b ldr r3, [r3, #8]
8001c2a: f003 0302 and.w r3, r3, #2
8001c2e: 2b02 cmp r3, #2
8001c30: d101 bne.n 8001c36 <LL_ADC_IsDisableOngoing+0x18>
8001c32: 2301 movs r3, #1
8001c34: e000 b.n 8001c38 <LL_ADC_IsDisableOngoing+0x1a>
8001c36: 2300 movs r3, #0
}
8001c38: 4618 mov r0, r3
8001c3a: 370c adds r7, #12
8001c3c: 46bd mov sp, r7
8001c3e: f85d 7b04 ldr.w r7, [sp], #4
8001c42: 4770 bx lr
08001c44 <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
8001c44: b480 push {r7}
8001c46: b083 sub sp, #12
8001c48: af00 add r7, sp, #0
8001c4a: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001c4c: 687b ldr r3, [r7, #4]
8001c4e: 689b ldr r3, [r3, #8]
8001c50: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001c54: f023 033f bic.w r3, r3, #63 @ 0x3f
8001c58: f043 0204 orr.w r2, r3, #4
8001c5c: 687b ldr r3, [r7, #4]
8001c5e: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
8001c60: bf00 nop
8001c62: 370c adds r7, #12
8001c64: 46bd mov sp, r7
8001c66: f85d 7b04 ldr.w r7, [sp], #4
8001c6a: 4770 bx lr
08001c6c <LL_ADC_REG_StopConversion>:
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
{
8001c6c: b480 push {r7}
8001c6e: b083 sub sp, #12
8001c70: af00 add r7, sp, #0
8001c72: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001c74: 687b ldr r3, [r7, #4]
8001c76: 689b ldr r3, [r3, #8]
8001c78: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001c7c: f023 033f bic.w r3, r3, #63 @ 0x3f
8001c80: f043 0210 orr.w r2, r3, #16
8001c84: 687b ldr r3, [r7, #4]
8001c86: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTP);
}
8001c88: bf00 nop
8001c8a: 370c adds r7, #12
8001c8c: 46bd mov sp, r7
8001c8e: f85d 7b04 ldr.w r7, [sp], #4
8001c92: 4770 bx lr
08001c94 <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
8001c94: b480 push {r7}
8001c96: b083 sub sp, #12
8001c98: af00 add r7, sp, #0
8001c9a: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001c9c: 687b ldr r3, [r7, #4]
8001c9e: 689b ldr r3, [r3, #8]
8001ca0: f003 0304 and.w r3, r3, #4
8001ca4: 2b04 cmp r3, #4
8001ca6: d101 bne.n 8001cac <LL_ADC_REG_IsConversionOngoing+0x18>
8001ca8: 2301 movs r3, #1
8001caa: e000 b.n 8001cae <LL_ADC_REG_IsConversionOngoing+0x1a>
8001cac: 2300 movs r3, #0
}
8001cae: 4618 mov r0, r3
8001cb0: 370c adds r7, #12
8001cb2: 46bd mov sp, r7
8001cb4: f85d 7b04 ldr.w r7, [sp], #4
8001cb8: 4770 bx lr
08001cba <LL_ADC_INJ_StopConversion>:
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
{
8001cba: b480 push {r7}
8001cbc: b083 sub sp, #12
8001cbe: af00 add r7, sp, #0
8001cc0: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001cc2: 687b ldr r3, [r7, #4]
8001cc4: 689b ldr r3, [r3, #8]
8001cc6: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001cca: f023 033f bic.w r3, r3, #63 @ 0x3f
8001cce: f043 0220 orr.w r2, r3, #32
8001cd2: 687b ldr r3, [r7, #4]
8001cd4: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_JADSTP);
}
8001cd6: bf00 nop
8001cd8: 370c adds r7, #12
8001cda: 46bd mov sp, r7
8001cdc: f85d 7b04 ldr.w r7, [sp], #4
8001ce0: 4770 bx lr
08001ce2 <LL_ADC_INJ_IsConversionOngoing>:
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
8001ce2: b480 push {r7}
8001ce4: b083 sub sp, #12
8001ce6: af00 add r7, sp, #0
8001ce8: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8001cea: 687b ldr r3, [r7, #4]
8001cec: 689b ldr r3, [r3, #8]
8001cee: f003 0308 and.w r3, r3, #8
8001cf2: 2b08 cmp r3, #8
8001cf4: d101 bne.n 8001cfa <LL_ADC_INJ_IsConversionOngoing+0x18>
8001cf6: 2301 movs r3, #1
8001cf8: e000 b.n 8001cfc <LL_ADC_INJ_IsConversionOngoing+0x1a>
8001cfa: 2300 movs r3, #0
}
8001cfc: 4618 mov r0, r3
8001cfe: 370c adds r7, #12
8001d00: 46bd mov sp, r7
8001d02: f85d 7b04 ldr.w r7, [sp], #4
8001d06: 4770 bx lr
08001d08 <HAL_ADC_Init>:
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
8001d08: b590 push {r4, r7, lr}
8001d0a: b089 sub sp, #36 @ 0x24
8001d0c: af00 add r7, sp, #0
8001d0e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001d10: 2300 movs r3, #0
8001d12: 77fb strb r3, [r7, #31]
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
8001d14: 2300 movs r3, #0
8001d16: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
8001d18: 687b ldr r3, [r7, #4]
8001d1a: 2b00 cmp r3, #0
8001d1c: d101 bne.n 8001d22 <HAL_ADC_Init+0x1a>
{
return HAL_ERROR;
8001d1e: 2301 movs r3, #1
8001d20: e167 b.n 8001ff2 <HAL_ADC_Init+0x2ea>
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8001d22: 687b ldr r3, [r7, #4]
8001d24: 695b ldr r3, [r3, #20]
8001d26: 2b00 cmp r3, #0
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8001d28: 687b ldr r3, [r7, #4]
8001d2a: 6ddb ldr r3, [r3, #92] @ 0x5c
8001d2c: 2b00 cmp r3, #0
8001d2e: d109 bne.n 8001d44 <HAL_ADC_Init+0x3c>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8001d30: 6878 ldr r0, [r7, #4]
8001d32: f7ff fb23 bl 800137c <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001d36: 687b ldr r3, [r7, #4]
8001d38: 2200 movs r2, #0
8001d3a: 661a str r2, [r3, #96] @ 0x60
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
8001d3c: 687b ldr r3, [r7, #4]
8001d3e: 2200 movs r2, #0
8001d40: f883 2058 strb.w r2, [r3, #88] @ 0x58
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
8001d44: 687b ldr r3, [r7, #4]
8001d46: 681b ldr r3, [r3, #0]
8001d48: 4618 mov r0, r3
8001d4a: f7ff fef1 bl 8001b30 <LL_ADC_IsDeepPowerDownEnabled>
8001d4e: 4603 mov r3, r0
8001d50: 2b00 cmp r3, #0
8001d52: d004 beq.n 8001d5e <HAL_ADC_Init+0x56>
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
8001d54: 687b ldr r3, [r7, #4]
8001d56: 681b ldr r3, [r3, #0]
8001d58: 4618 mov r0, r3
8001d5a: f7ff fed7 bl 8001b0c <LL_ADC_DisableDeepPowerDown>
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8001d5e: 687b ldr r3, [r7, #4]
8001d60: 681b ldr r3, [r3, #0]
8001d62: 4618 mov r0, r3
8001d64: f7ff ff0c bl 8001b80 <LL_ADC_IsInternalRegulatorEnabled>
8001d68: 4603 mov r3, r0
8001d6a: 2b00 cmp r3, #0
8001d6c: d115 bne.n 8001d9a <HAL_ADC_Init+0x92>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
8001d6e: 687b ldr r3, [r7, #4]
8001d70: 681b ldr r3, [r3, #0]
8001d72: 4618 mov r0, r3
8001d74: f7ff fef0 bl 8001b58 <LL_ADC_EnableInternalRegulator>
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8001d78: 4ba0 ldr r3, [pc, #640] @ (8001ffc <HAL_ADC_Init+0x2f4>)
8001d7a: 681b ldr r3, [r3, #0]
8001d7c: 099b lsrs r3, r3, #6
8001d7e: 4aa0 ldr r2, [pc, #640] @ (8002000 <HAL_ADC_Init+0x2f8>)
8001d80: fba2 2303 umull r2, r3, r2, r3
8001d84: 099b lsrs r3, r3, #6
8001d86: 3301 adds r3, #1
8001d88: 005b lsls r3, r3, #1
8001d8a: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8001d8c: e002 b.n 8001d94 <HAL_ADC_Init+0x8c>
{
wait_loop_index--;
8001d8e: 68fb ldr r3, [r7, #12]
8001d90: 3b01 subs r3, #1
8001d92: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8001d94: 68fb ldr r3, [r7, #12]
8001d96: 2b00 cmp r3, #0
8001d98: d1f9 bne.n 8001d8e <HAL_ADC_Init+0x86>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8001d9a: 687b ldr r3, [r7, #4]
8001d9c: 681b ldr r3, [r3, #0]
8001d9e: 4618 mov r0, r3
8001da0: f7ff feee bl 8001b80 <LL_ADC_IsInternalRegulatorEnabled>
8001da4: 4603 mov r3, r0
8001da6: 2b00 cmp r3, #0
8001da8: d10d bne.n 8001dc6 <HAL_ADC_Init+0xbe>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001daa: 687b ldr r3, [r7, #4]
8001dac: 6ddb ldr r3, [r3, #92] @ 0x5c
8001dae: f043 0210 orr.w r2, r3, #16
8001db2: 687b ldr r3, [r7, #4]
8001db4: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001db6: 687b ldr r3, [r7, #4]
8001db8: 6e1b ldr r3, [r3, #96] @ 0x60
8001dba: f043 0201 orr.w r2, r3, #1
8001dbe: 687b ldr r3, [r7, #4]
8001dc0: 661a str r2, [r3, #96] @ 0x60
tmp_hal_status = HAL_ERROR;
8001dc2: 2301 movs r3, #1
8001dc4: 77fb strb r3, [r7, #31]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8001dc6: 687b ldr r3, [r7, #4]
8001dc8: 681b ldr r3, [r3, #0]
8001dca: 4618 mov r0, r3
8001dcc: f7ff ff62 bl 8001c94 <LL_ADC_REG_IsConversionOngoing>
8001dd0: 6178 str r0, [r7, #20]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8001dd2: 687b ldr r3, [r7, #4]
8001dd4: 6ddb ldr r3, [r3, #92] @ 0x5c
8001dd6: f003 0310 and.w r3, r3, #16
8001dda: 2b00 cmp r3, #0
8001ddc: f040 8100 bne.w 8001fe0 <HAL_ADC_Init+0x2d8>
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
8001de0: 697b ldr r3, [r7, #20]
8001de2: 2b00 cmp r3, #0
8001de4: f040 80fc bne.w 8001fe0 <HAL_ADC_Init+0x2d8>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001de8: 687b ldr r3, [r7, #4]
8001dea: 6ddb ldr r3, [r3, #92] @ 0x5c
8001dec: f423 7381 bic.w r3, r3, #258 @ 0x102
8001df0: f043 0202 orr.w r2, r3, #2
8001df4: 687b ldr r3, [r7, #4]
8001df6: 65da str r2, [r3, #92] @ 0x5c
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8001df8: 687b ldr r3, [r7, #4]
8001dfa: 681b ldr r3, [r3, #0]
8001dfc: 4618 mov r0, r3
8001dfe: f7ff fefb bl 8001bf8 <LL_ADC_IsEnabled>
8001e02: 4603 mov r3, r0
8001e04: 2b00 cmp r3, #0
8001e06: d111 bne.n 8001e2c <HAL_ADC_Init+0x124>
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8001e08: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
8001e0c: f7ff fef4 bl 8001bf8 <LL_ADC_IsEnabled>
8001e10: 4604 mov r4, r0
8001e12: 487c ldr r0, [pc, #496] @ (8002004 <HAL_ADC_Init+0x2fc>)
8001e14: f7ff fef0 bl 8001bf8 <LL_ADC_IsEnabled>
8001e18: 4603 mov r3, r0
8001e1a: 4323 orrs r3, r4
8001e1c: 2b00 cmp r3, #0
8001e1e: d105 bne.n 8001e2c <HAL_ADC_Init+0x124>
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
8001e20: 687b ldr r3, [r7, #4]
8001e22: 685b ldr r3, [r3, #4]
8001e24: 4619 mov r1, r3
8001e26: 4878 ldr r0, [pc, #480] @ (8002008 <HAL_ADC_Init+0x300>)
8001e28: f7ff fcf4 bl 8001814 <LL_ADC_SetCommonClock>
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001e2c: 687b ldr r3, [r7, #4]
8001e2e: 7f5b ldrb r3, [r3, #29]
8001e30: 035a lsls r2, r3, #13
hadc->Init.Overrun |
8001e32: 687b ldr r3, [r7, #4]
8001e34: 6bdb ldr r3, [r3, #60] @ 0x3c
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001e36: 431a orrs r2, r3
hadc->Init.DataAlign |
8001e38: 687b ldr r3, [r7, #4]
8001e3a: 68db ldr r3, [r3, #12]
hadc->Init.Overrun |
8001e3c: 431a orrs r2, r3
hadc->Init.Resolution |
8001e3e: 687b ldr r3, [r7, #4]
8001e40: 689b ldr r3, [r3, #8]
hadc->Init.DataAlign |
8001e42: 431a orrs r2, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
8001e44: 687b ldr r3, [r7, #4]
8001e46: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8001e4a: 041b lsls r3, r3, #16
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001e4c: 4313 orrs r3, r2
8001e4e: 61bb str r3, [r7, #24]
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8001e50: 687b ldr r3, [r7, #4]
8001e52: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8001e56: 2b01 cmp r3, #1
8001e58: d106 bne.n 8001e68 <HAL_ADC_Init+0x160>
{
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 6a9b ldr r3, [r3, #40] @ 0x28
8001e5e: 3b01 subs r3, #1
8001e60: 045b lsls r3, r3, #17
8001e62: 69ba ldr r2, [r7, #24]
8001e64: 4313 orrs r3, r2
8001e66: 61bb str r3, [r7, #24]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8001e68: 687b ldr r3, [r7, #4]
8001e6a: 6adb ldr r3, [r3, #44] @ 0x2c
8001e6c: 2b00 cmp r3, #0
8001e6e: d009 beq.n 8001e84 <HAL_ADC_Init+0x17c>
{
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8001e70: 687b ldr r3, [r7, #4]
8001e72: 6adb ldr r3, [r3, #44] @ 0x2c
8001e74: f403 7278 and.w r2, r3, #992 @ 0x3e0
| hadc->Init.ExternalTrigConvEdge
8001e78: 687b ldr r3, [r7, #4]
8001e7a: 6b1b ldr r3, [r3, #48] @ 0x30
8001e7c: 4313 orrs r3, r2
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8001e7e: 69ba ldr r2, [r7, #24]
8001e80: 4313 orrs r3, r2
8001e82: 61bb str r3, [r7, #24]
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
8001e84: 687b ldr r3, [r7, #4]
8001e86: 681b ldr r3, [r3, #0]
8001e88: 68da ldr r2, [r3, #12]
8001e8a: 4b60 ldr r3, [pc, #384] @ (800200c <HAL_ADC_Init+0x304>)
8001e8c: 4013 ands r3, r2
8001e8e: 687a ldr r2, [r7, #4]
8001e90: 6812 ldr r2, [r2, #0]
8001e92: 69b9 ldr r1, [r7, #24]
8001e94: 430b orrs r3, r1
8001e96: 60d3 str r3, [r2, #12]
/* Configuration of sampling mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
8001e98: 687b ldr r3, [r7, #4]
8001e9a: 681b ldr r3, [r3, #0]
8001e9c: 691b ldr r3, [r3, #16]
8001e9e: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 6b5a ldr r2, [r3, #52] @ 0x34
8001ea6: 687b ldr r3, [r7, #4]
8001ea8: 681b ldr r3, [r3, #0]
8001eaa: 430a orrs r2, r1
8001eac: 611a str r2, [r3, #16]
/* conversion on going on regular and injected groups: */
/* - Gain Compensation Init.GainCompensation */
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 681b ldr r3, [r3, #0]
8001eb2: 4618 mov r0, r3
8001eb4: f7ff ff15 bl 8001ce2 <LL_ADC_INJ_IsConversionOngoing>
8001eb8: 6138 str r0, [r7, #16]
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8001eba: 697b ldr r3, [r7, #20]
8001ebc: 2b00 cmp r3, #0
8001ebe: d16d bne.n 8001f9c <HAL_ADC_Init+0x294>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8001ec0: 693b ldr r3, [r7, #16]
8001ec2: 2b00 cmp r3, #0
8001ec4: d16a bne.n 8001f9c <HAL_ADC_Init+0x294>
)
{
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: 7f1b ldrb r3, [r3, #28]
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
8001eca: 039a lsls r2, r3, #14
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
8001ecc: 687b ldr r3, [r7, #4]
8001ece: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8001ed2: 005b lsls r3, r3, #1
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
8001ed4: 4313 orrs r3, r2
8001ed6: 61bb str r3, [r7, #24]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
8001ed8: 687b ldr r3, [r7, #4]
8001eda: 681b ldr r3, [r3, #0]
8001edc: 68db ldr r3, [r3, #12]
8001ede: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8001ee2: f023 0302 bic.w r3, r3, #2
8001ee6: 687a ldr r2, [r7, #4]
8001ee8: 6812 ldr r2, [r2, #0]
8001eea: 69b9 ldr r1, [r7, #24]
8001eec: 430b orrs r3, r1
8001eee: 60d3 str r3, [r2, #12]
if (hadc->Init.GainCompensation != 0UL)
8001ef0: 687b ldr r3, [r7, #4]
8001ef2: 691b ldr r3, [r3, #16]
8001ef4: 2b00 cmp r3, #0
8001ef6: d017 beq.n 8001f28 <HAL_ADC_Init+0x220>
{
SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
8001ef8: 687b ldr r3, [r7, #4]
8001efa: 681b ldr r3, [r3, #0]
8001efc: 691a ldr r2, [r3, #16]
8001efe: 687b ldr r3, [r7, #4]
8001f00: 681b ldr r3, [r3, #0]
8001f02: f442 3280 orr.w r2, r2, #65536 @ 0x10000
8001f06: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
8001f08: 687b ldr r3, [r7, #4]
8001f0a: 681b ldr r3, [r3, #0]
8001f0c: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
8001f10: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8001f14: f023 033f bic.w r3, r3, #63 @ 0x3f
8001f18: 687a ldr r2, [r7, #4]
8001f1a: 6911 ldr r1, [r2, #16]
8001f1c: 687a ldr r2, [r7, #4]
8001f1e: 6812 ldr r2, [r2, #0]
8001f20: 430b orrs r3, r1
8001f22: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
8001f26: e013 b.n 8001f50 <HAL_ADC_Init+0x248>
}
else
{
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
8001f28: 687b ldr r3, [r7, #4]
8001f2a: 681b ldr r3, [r3, #0]
8001f2c: 691a ldr r2, [r3, #16]
8001f2e: 687b ldr r3, [r7, #4]
8001f30: 681b ldr r3, [r3, #0]
8001f32: f422 3280 bic.w r2, r2, #65536 @ 0x10000
8001f36: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
8001f38: 687b ldr r3, [r7, #4]
8001f3a: 681b ldr r3, [r3, #0]
8001f3c: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
8001f40: 687a ldr r2, [r7, #4]
8001f42: 6812 ldr r2, [r2, #0]
8001f44: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8001f48: f023 033f bic.w r3, r3, #63 @ 0x3f
8001f4c: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
}
if (hadc->Init.OversamplingMode == ENABLE)
8001f50: 687b ldr r3, [r7, #4]
8001f52: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8001f56: 2b01 cmp r3, #1
8001f58: d118 bne.n 8001f8c <HAL_ADC_Init+0x284>
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
8001f5a: 687b ldr r3, [r7, #4]
8001f5c: 681b ldr r3, [r3, #0]
8001f5e: 691b ldr r3, [r3, #16]
8001f60: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
8001f64: f023 0304 bic.w r3, r3, #4
8001f68: 687a ldr r2, [r7, #4]
8001f6a: 6c51 ldr r1, [r2, #68] @ 0x44
8001f6c: 687a ldr r2, [r7, #4]
8001f6e: 6c92 ldr r2, [r2, #72] @ 0x48
8001f70: 4311 orrs r1, r2
8001f72: 687a ldr r2, [r7, #4]
8001f74: 6cd2 ldr r2, [r2, #76] @ 0x4c
8001f76: 4311 orrs r1, r2
8001f78: 687a ldr r2, [r7, #4]
8001f7a: 6d12 ldr r2, [r2, #80] @ 0x50
8001f7c: 430a orrs r2, r1
8001f7e: 431a orrs r2, r3
8001f80: 687b ldr r3, [r7, #4]
8001f82: 681b ldr r3, [r3, #0]
8001f84: f042 0201 orr.w r2, r2, #1
8001f88: 611a str r2, [r3, #16]
8001f8a: e007 b.n 8001f9c <HAL_ADC_Init+0x294>
);
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8001f8c: 687b ldr r3, [r7, #4]
8001f8e: 681b ldr r3, [r3, #0]
8001f90: 691a ldr r2, [r3, #16]
8001f92: 687b ldr r3, [r7, #4]
8001f94: 681b ldr r3, [r3, #0]
8001f96: f022 0201 bic.w r2, r2, #1
8001f9a: 611a str r2, [r3, #16]
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8001f9c: 687b ldr r3, [r7, #4]
8001f9e: 695b ldr r3, [r3, #20]
8001fa0: 2b01 cmp r3, #1
8001fa2: d10c bne.n 8001fbe <HAL_ADC_Init+0x2b6>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 681b ldr r3, [r3, #0]
8001fa8: 6b1b ldr r3, [r3, #48] @ 0x30
8001faa: f023 010f bic.w r1, r3, #15
8001fae: 687b ldr r3, [r7, #4]
8001fb0: 6a1b ldr r3, [r3, #32]
8001fb2: 1e5a subs r2, r3, #1
8001fb4: 687b ldr r3, [r7, #4]
8001fb6: 681b ldr r3, [r3, #0]
8001fb8: 430a orrs r2, r1
8001fba: 631a str r2, [r3, #48] @ 0x30
8001fbc: e007 b.n 8001fce <HAL_ADC_Init+0x2c6>
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
8001fbe: 687b ldr r3, [r7, #4]
8001fc0: 681b ldr r3, [r3, #0]
8001fc2: 6b1a ldr r2, [r3, #48] @ 0x30
8001fc4: 687b ldr r3, [r7, #4]
8001fc6: 681b ldr r3, [r3, #0]
8001fc8: f022 020f bic.w r2, r2, #15
8001fcc: 631a str r2, [r3, #48] @ 0x30
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
8001fce: 687b ldr r3, [r7, #4]
8001fd0: 6ddb ldr r3, [r3, #92] @ 0x5c
8001fd2: f023 0303 bic.w r3, r3, #3
8001fd6: f043 0201 orr.w r2, r3, #1
8001fda: 687b ldr r3, [r7, #4]
8001fdc: 65da str r2, [r3, #92] @ 0x5c
8001fde: e007 b.n 8001ff0 <HAL_ADC_Init+0x2e8>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001fe0: 687b ldr r3, [r7, #4]
8001fe2: 6ddb ldr r3, [r3, #92] @ 0x5c
8001fe4: f043 0210 orr.w r2, r3, #16
8001fe8: 687b ldr r3, [r7, #4]
8001fea: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8001fec: 2301 movs r3, #1
8001fee: 77fb strb r3, [r7, #31]
}
/* Return function status */
return tmp_hal_status;
8001ff0: 7ffb ldrb r3, [r7, #31]
}
8001ff2: 4618 mov r0, r3
8001ff4: 3724 adds r7, #36 @ 0x24
8001ff6: 46bd mov sp, r7
8001ff8: bd90 pop {r4, r7, pc}
8001ffa: bf00 nop
8001ffc: 2000001c .word 0x2000001c
8002000: 053e2d63 .word 0x053e2d63
8002004: 50000100 .word 0x50000100
8002008: 50000300 .word 0x50000300
800200c: fff04007 .word 0xfff04007
08002010 <HAL_ADC_Start>:
* if ADC is master, ADC is enabled and multimode conversion is started.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
{
8002010: b580 push {r7, lr}
8002012: b086 sub sp, #24
8002014: af00 add r7, sp, #0
8002016: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8002018: 4859 ldr r0, [pc, #356] @ (8002180 <HAL_ADC_Start+0x170>)
800201a: f7ff fd5b bl 8001ad4 <LL_ADC_GetMultimode>
800201e: 6138 str r0, [r7, #16]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002020: 687b ldr r3, [r7, #4]
8002022: 681b ldr r3, [r3, #0]
8002024: 4618 mov r0, r3
8002026: f7ff fe35 bl 8001c94 <LL_ADC_REG_IsConversionOngoing>
800202a: 4603 mov r3, r0
800202c: 2b00 cmp r3, #0
800202e: f040 809f bne.w 8002170 <HAL_ADC_Start+0x160>
{
/* Process locked */
__HAL_LOCK(hadc);
8002032: 687b ldr r3, [r7, #4]
8002034: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8002038: 2b01 cmp r3, #1
800203a: d101 bne.n 8002040 <HAL_ADC_Start+0x30>
800203c: 2302 movs r3, #2
800203e: e09a b.n 8002176 <HAL_ADC_Start+0x166>
8002040: 687b ldr r3, [r7, #4]
8002042: 2201 movs r2, #1
8002044: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
8002048: 6878 ldr r0, [r7, #4]
800204a: f000 fe63 bl 8002d14 <ADC_Enable>
800204e: 4603 mov r3, r0
8002050: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
8002052: 7dfb ldrb r3, [r7, #23]
8002054: 2b00 cmp r3, #0
8002056: f040 8086 bne.w 8002166 <HAL_ADC_Start+0x156>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
800205a: 687b ldr r3, [r7, #4]
800205c: 6ddb ldr r3, [r3, #92] @ 0x5c
800205e: f423 6370 bic.w r3, r3, #3840 @ 0xf00
8002062: f023 0301 bic.w r3, r3, #1
8002066: f443 7280 orr.w r2, r3, #256 @ 0x100
800206a: 687b ldr r3, [r7, #4]
800206c: 65da str r2, [r3, #92] @ 0x5c
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
800206e: 687b ldr r3, [r7, #4]
8002070: 681b ldr r3, [r3, #0]
8002072: 4a44 ldr r2, [pc, #272] @ (8002184 <HAL_ADC_Start+0x174>)
8002074: 4293 cmp r3, r2
8002076: d002 beq.n 800207e <HAL_ADC_Start+0x6e>
8002078: 687b ldr r3, [r7, #4]
800207a: 681b ldr r3, [r3, #0]
800207c: e001 b.n 8002082 <HAL_ADC_Start+0x72>
800207e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002082: 687a ldr r2, [r7, #4]
8002084: 6812 ldr r2, [r2, #0]
8002086: 4293 cmp r3, r2
8002088: d002 beq.n 8002090 <HAL_ADC_Start+0x80>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
800208a: 693b ldr r3, [r7, #16]
800208c: 2b00 cmp r3, #0
800208e: d105 bne.n 800209c <HAL_ADC_Start+0x8c>
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002090: 687b ldr r3, [r7, #4]
8002092: 6ddb ldr r3, [r3, #92] @ 0x5c
8002094: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8002098: 687b ldr r3, [r7, #4]
800209a: 65da str r2, [r3, #92] @ 0x5c
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Set ADC error code */
/* Check if a conversion is on going on ADC group injected */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
800209c: 687b ldr r3, [r7, #4]
800209e: 6ddb ldr r3, [r3, #92] @ 0x5c
80020a0: f403 5380 and.w r3, r3, #4096 @ 0x1000
80020a4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80020a8: d106 bne.n 80020b8 <HAL_ADC_Start+0xa8>
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
80020aa: 687b ldr r3, [r7, #4]
80020ac: 6e1b ldr r3, [r3, #96] @ 0x60
80020ae: f023 0206 bic.w r2, r3, #6
80020b2: 687b ldr r3, [r7, #4]
80020b4: 661a str r2, [r3, #96] @ 0x60
80020b6: e002 b.n 80020be <HAL_ADC_Start+0xae>
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80020b8: 687b ldr r3, [r7, #4]
80020ba: 2200 movs r2, #0
80020bc: 661a str r2, [r3, #96] @ 0x60
}
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
80020be: 687b ldr r3, [r7, #4]
80020c0: 681b ldr r3, [r3, #0]
80020c2: 221c movs r2, #28
80020c4: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80020c6: 687b ldr r3, [r7, #4]
80020c8: 2200 movs r2, #0
80020ca: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Case of multimode enabled (when multimode feature is available): */
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
/* enabled only (conversion is not started), */
/* - if ADC is master, ADC is enabled and conversion is started. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
80020ce: 687b ldr r3, [r7, #4]
80020d0: 681b ldr r3, [r3, #0]
80020d2: 4a2c ldr r2, [pc, #176] @ (8002184 <HAL_ADC_Start+0x174>)
80020d4: 4293 cmp r3, r2
80020d6: d002 beq.n 80020de <HAL_ADC_Start+0xce>
80020d8: 687b ldr r3, [r7, #4]
80020da: 681b ldr r3, [r3, #0]
80020dc: e001 b.n 80020e2 <HAL_ADC_Start+0xd2>
80020de: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
80020e2: 687a ldr r2, [r7, #4]
80020e4: 6812 ldr r2, [r2, #0]
80020e6: 4293 cmp r3, r2
80020e8: d008 beq.n 80020fc <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
80020ea: 693b ldr r3, [r7, #16]
80020ec: 2b00 cmp r3, #0
80020ee: d005 beq.n 80020fc <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
80020f0: 693b ldr r3, [r7, #16]
80020f2: 2b05 cmp r3, #5
80020f4: d002 beq.n 80020fc <HAL_ADC_Start+0xec>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
80020f6: 693b ldr r3, [r7, #16]
80020f8: 2b09 cmp r3, #9
80020fa: d114 bne.n 8002126 <HAL_ADC_Start+0x116>
)
{
/* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
80020fc: 687b ldr r3, [r7, #4]
80020fe: 681b ldr r3, [r3, #0]
8002100: 68db ldr r3, [r3, #12]
8002102: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002106: 2b00 cmp r3, #0
8002108: d007 beq.n 800211a <HAL_ADC_Start+0x10a>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
800210a: 687b ldr r3, [r7, #4]
800210c: 6ddb ldr r3, [r3, #92] @ 0x5c
800210e: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8002112: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8002116: 687b ldr r3, [r7, #4]
8002118: 65da str r2, [r3, #92] @ 0x5c
}
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
800211a: 687b ldr r3, [r7, #4]
800211c: 681b ldr r3, [r3, #0]
800211e: 4618 mov r0, r3
8002120: f7ff fd90 bl 8001c44 <LL_ADC_REG_StartConversion>
8002124: e026 b.n 8002174 <HAL_ADC_Start+0x164>
}
else
{
/* ADC instance is a multimode slave instance with multimode regular conversions enabled */
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
8002126: 687b ldr r3, [r7, #4]
8002128: 6ddb ldr r3, [r3, #92] @ 0x5c
800212a: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
800212e: 687b ldr r3, [r7, #4]
8002130: 65da str r2, [r3, #92] @ 0x5c
/* if Master ADC JAUTO bit is set, update Slave State in setting
HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
8002132: 687b ldr r3, [r7, #4]
8002134: 681b ldr r3, [r3, #0]
8002136: 4a13 ldr r2, [pc, #76] @ (8002184 <HAL_ADC_Start+0x174>)
8002138: 4293 cmp r3, r2
800213a: d002 beq.n 8002142 <HAL_ADC_Start+0x132>
800213c: 687b ldr r3, [r7, #4]
800213e: 681b ldr r3, [r3, #0]
8002140: e001 b.n 8002146 <HAL_ADC_Start+0x136>
8002142: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002146: 60fb str r3, [r7, #12]
if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
8002148: 68fb ldr r3, [r7, #12]
800214a: 68db ldr r3, [r3, #12]
800214c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002150: 2b00 cmp r3, #0
8002152: d00f beq.n 8002174 <HAL_ADC_Start+0x164>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8002154: 687b ldr r3, [r7, #4]
8002156: 6ddb ldr r3, [r3, #92] @ 0x5c
8002158: f423 5340 bic.w r3, r3, #12288 @ 0x3000
800215c: f443 5280 orr.w r2, r3, #4096 @ 0x1000
8002160: 687b ldr r3, [r7, #4]
8002162: 65da str r2, [r3, #92] @ 0x5c
8002164: e006 b.n 8002174 <HAL_ADC_Start+0x164>
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002166: 687b ldr r3, [r7, #4]
8002168: 2200 movs r2, #0
800216a: f883 2058 strb.w r2, [r3, #88] @ 0x58
800216e: e001 b.n 8002174 <HAL_ADC_Start+0x164>
}
}
else
{
tmp_hal_status = HAL_BUSY;
8002170: 2302 movs r3, #2
8002172: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
8002174: 7dfb ldrb r3, [r7, #23]
}
8002176: 4618 mov r0, r3
8002178: 3718 adds r7, #24
800217a: 46bd mov sp, r7
800217c: bd80 pop {r7, pc}
800217e: bf00 nop
8002180: 50000300 .word 0x50000300
8002184: 50000100 .word 0x50000100
08002188 <HAL_ADC_Stop>:
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
{
8002188: b580 push {r7, lr}
800218a: b084 sub sp, #16
800218c: af00 add r7, sp, #0
800218e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Process locked */
__HAL_LOCK(hadc);
8002190: 687b ldr r3, [r7, #4]
8002192: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8002196: 2b01 cmp r3, #1
8002198: d101 bne.n 800219e <HAL_ADC_Stop+0x16>
800219a: 2302 movs r3, #2
800219c: e023 b.n 80021e6 <HAL_ADC_Stop+0x5e>
800219e: 687b ldr r3, [r7, #4]
80021a0: 2201 movs r2, #1
80021a2: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
80021a6: 2103 movs r1, #3
80021a8: 6878 ldr r0, [r7, #4]
80021aa: f000 fcf7 bl 8002b9c <ADC_ConversionStop>
80021ae: 4603 mov r3, r0
80021b0: 73fb strb r3, [r7, #15]
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
80021b2: 7bfb ldrb r3, [r7, #15]
80021b4: 2b00 cmp r3, #0
80021b6: d111 bne.n 80021dc <HAL_ADC_Stop+0x54>
{
/* 2. Disable the ADC peripheral */
tmp_hal_status = ADC_Disable(hadc);
80021b8: 6878 ldr r0, [r7, #4]
80021ba: f000 fe31 bl 8002e20 <ADC_Disable>
80021be: 4603 mov r3, r0
80021c0: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
80021c2: 7bfb ldrb r3, [r7, #15]
80021c4: 2b00 cmp r3, #0
80021c6: d109 bne.n 80021dc <HAL_ADC_Stop+0x54>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
80021c8: 687b ldr r3, [r7, #4]
80021ca: 6ddb ldr r3, [r3, #92] @ 0x5c
80021cc: f423 5388 bic.w r3, r3, #4352 @ 0x1100
80021d0: f023 0301 bic.w r3, r3, #1
80021d4: f043 0201 orr.w r2, r3, #1
80021d8: 687b ldr r3, [r7, #4]
80021da: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_READY);
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80021dc: 687b ldr r3, [r7, #4]
80021de: 2200 movs r2, #0
80021e0: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80021e4: 7bfb ldrb r3, [r7, #15]
}
80021e6: 4618 mov r0, r3
80021e8: 3710 adds r7, #16
80021ea: 46bd mov sp, r7
80021ec: bd80 pop {r7, pc}
...
080021f0 <HAL_ADC_PollForConversion>:
* @param hadc ADC handle
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
{
80021f0: b580 push {r7, lr}
80021f2: b088 sub sp, #32
80021f4: af00 add r7, sp, #0
80021f6: 6078 str r0, [r7, #4]
80021f8: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t tmp_Flag_End;
uint32_t tmp_cfgr;
#if defined(ADC_MULTIMODE_SUPPORT)
const ADC_TypeDef *tmpADC_Master;
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80021fa: 4867 ldr r0, [pc, #412] @ (8002398 <HAL_ADC_PollForConversion+0x1a8>)
80021fc: f7ff fc6a bl 8001ad4 <LL_ADC_GetMultimode>
8002200: 6178 str r0, [r7, #20]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* If end of conversion selected to end of sequence conversions */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
8002202: 687b ldr r3, [r7, #4]
8002204: 699b ldr r3, [r3, #24]
8002206: 2b08 cmp r3, #8
8002208: d102 bne.n 8002210 <HAL_ADC_PollForConversion+0x20>
{
tmp_Flag_End = ADC_FLAG_EOS;
800220a: 2308 movs r3, #8
800220c: 61fb str r3, [r7, #28]
800220e: e02a b.n 8002266 <HAL_ADC_PollForConversion+0x76>
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002210: 697b ldr r3, [r7, #20]
8002212: 2b00 cmp r3, #0
8002214: d005 beq.n 8002222 <HAL_ADC_PollForConversion+0x32>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
8002216: 697b ldr r3, [r7, #20]
8002218: 2b05 cmp r3, #5
800221a: d002 beq.n 8002222 <HAL_ADC_PollForConversion+0x32>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
800221c: 697b ldr r3, [r7, #20]
800221e: 2b09 cmp r3, #9
8002220: d111 bne.n 8002246 <HAL_ADC_PollForConversion+0x56>
)
{
/* Check ADC DMA mode in independent mode on ADC group regular */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
8002222: 687b ldr r3, [r7, #4]
8002224: 681b ldr r3, [r3, #0]
8002226: 68db ldr r3, [r3, #12]
8002228: f003 0301 and.w r3, r3, #1
800222c: 2b00 cmp r3, #0
800222e: d007 beq.n 8002240 <HAL_ADC_PollForConversion+0x50>
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002230: 687b ldr r3, [r7, #4]
8002232: 6ddb ldr r3, [r3, #92] @ 0x5c
8002234: f043 0220 orr.w r2, r3, #32
8002238: 687b ldr r3, [r7, #4]
800223a: 65da str r2, [r3, #92] @ 0x5c
return HAL_ERROR;
800223c: 2301 movs r3, #1
800223e: e0a6 b.n 800238e <HAL_ADC_PollForConversion+0x19e>
}
else
{
tmp_Flag_End = (ADC_FLAG_EOC);
8002240: 2304 movs r3, #4
8002242: 61fb str r3, [r7, #28]
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
8002244: e00f b.n 8002266 <HAL_ADC_PollForConversion+0x76>
}
}
else
{
/* Check ADC DMA mode in multimode on ADC group regular */
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
8002246: 4854 ldr r0, [pc, #336] @ (8002398 <HAL_ADC_PollForConversion+0x1a8>)
8002248: f7ff fc52 bl 8001af0 <LL_ADC_GetMultiDMATransfer>
800224c: 4603 mov r3, r0
800224e: 2b00 cmp r3, #0
8002250: d007 beq.n 8002262 <HAL_ADC_PollForConversion+0x72>
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002252: 687b ldr r3, [r7, #4]
8002254: 6ddb ldr r3, [r3, #92] @ 0x5c
8002256: f043 0220 orr.w r2, r3, #32
800225a: 687b ldr r3, [r7, #4]
800225c: 65da str r2, [r3, #92] @ 0x5c
return HAL_ERROR;
800225e: 2301 movs r3, #1
8002260: e095 b.n 800238e <HAL_ADC_PollForConversion+0x19e>
}
else
{
tmp_Flag_End = (ADC_FLAG_EOC);
8002262: 2304 movs r3, #4
8002264: 61fb str r3, [r7, #28]
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
/* Get tick count */
tickstart = HAL_GetTick();
8002266: f7ff fac9 bl 80017fc <HAL_GetTick>
800226a: 6138 str r0, [r7, #16]
/* Wait until End of unitary conversion or sequence conversions flag is raised */
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
800226c: e021 b.n 80022b2 <HAL_ADC_PollForConversion+0xc2>
{
/* Check if timeout is disabled (set to infinite wait) */
if (Timeout != HAL_MAX_DELAY)
800226e: 683b ldr r3, [r7, #0]
8002270: f1b3 3fff cmp.w r3, #4294967295
8002274: d01d beq.n 80022b2 <HAL_ADC_PollForConversion+0xc2>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
8002276: f7ff fac1 bl 80017fc <HAL_GetTick>
800227a: 4602 mov r2, r0
800227c: 693b ldr r3, [r7, #16]
800227e: 1ad3 subs r3, r2, r3
8002280: 683a ldr r2, [r7, #0]
8002282: 429a cmp r2, r3
8002284: d302 bcc.n 800228c <HAL_ADC_PollForConversion+0x9c>
8002286: 683b ldr r3, [r7, #0]
8002288: 2b00 cmp r3, #0
800228a: d112 bne.n 80022b2 <HAL_ADC_PollForConversion+0xc2>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
800228c: 687b ldr r3, [r7, #4]
800228e: 681b ldr r3, [r3, #0]
8002290: 681a ldr r2, [r3, #0]
8002292: 69fb ldr r3, [r7, #28]
8002294: 4013 ands r3, r2
8002296: 2b00 cmp r3, #0
8002298: d10b bne.n 80022b2 <HAL_ADC_PollForConversion+0xc2>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
800229a: 687b ldr r3, [r7, #4]
800229c: 6ddb ldr r3, [r3, #92] @ 0x5c
800229e: f043 0204 orr.w r2, r3, #4
80022a2: 687b ldr r3, [r7, #4]
80022a4: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
80022a6: 687b ldr r3, [r7, #4]
80022a8: 2200 movs r2, #0
80022aa: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_TIMEOUT;
80022ae: 2303 movs r3, #3
80022b0: e06d b.n 800238e <HAL_ADC_PollForConversion+0x19e>
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
80022b2: 687b ldr r3, [r7, #4]
80022b4: 681b ldr r3, [r3, #0]
80022b6: 681a ldr r2, [r3, #0]
80022b8: 69fb ldr r3, [r7, #28]
80022ba: 4013 ands r3, r2
80022bc: 2b00 cmp r3, #0
80022be: d0d6 beq.n 800226e <HAL_ADC_PollForConversion+0x7e>
}
}
}
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
80022c0: 687b ldr r3, [r7, #4]
80022c2: 6ddb ldr r3, [r3, #92] @ 0x5c
80022c4: f443 7200 orr.w r2, r3, #512 @ 0x200
80022c8: 687b ldr r3, [r7, #4]
80022ca: 65da str r2, [r3, #92] @ 0x5c
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
80022cc: 687b ldr r3, [r7, #4]
80022ce: 681b ldr r3, [r3, #0]
80022d0: 4618 mov r0, r3
80022d2: f7ff fb71 bl 80019b8 <LL_ADC_REG_IsTriggerSourceSWStart>
80022d6: 4603 mov r3, r0
80022d8: 2b00 cmp r3, #0
80022da: d01c beq.n 8002316 <HAL_ADC_PollForConversion+0x126>
&& (hadc->Init.ContinuousConvMode == DISABLE)
80022dc: 687b ldr r3, [r7, #4]
80022de: 7f5b ldrb r3, [r3, #29]
80022e0: 2b00 cmp r3, #0
80022e2: d118 bne.n 8002316 <HAL_ADC_PollForConversion+0x126>
)
{
/* Check whether end of sequence is reached */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
80022e4: 687b ldr r3, [r7, #4]
80022e6: 681b ldr r3, [r3, #0]
80022e8: 681b ldr r3, [r3, #0]
80022ea: f003 0308 and.w r3, r3, #8
80022ee: 2b08 cmp r3, #8
80022f0: d111 bne.n 8002316 <HAL_ADC_PollForConversion+0x126>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80022f2: 687b ldr r3, [r7, #4]
80022f4: 6ddb ldr r3, [r3, #92] @ 0x5c
80022f6: f423 7280 bic.w r2, r3, #256 @ 0x100
80022fa: 687b ldr r3, [r7, #4]
80022fc: 65da str r2, [r3, #92] @ 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
80022fe: 687b ldr r3, [r7, #4]
8002300: 6ddb ldr r3, [r3, #92] @ 0x5c
8002302: f403 5380 and.w r3, r3, #4096 @ 0x1000
8002306: 2b00 cmp r3, #0
8002308: d105 bne.n 8002316 <HAL_ADC_PollForConversion+0x126>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
800230a: 687b ldr r3, [r7, #4]
800230c: 6ddb ldr r3, [r3, #92] @ 0x5c
800230e: f043 0201 orr.w r2, r3, #1
8002312: 687b ldr r3, [r7, #4]
8002314: 65da str r2, [r3, #92] @ 0x5c
/* Get relevant register CFGR in ADC instance of ADC master or slave */
/* in function of multimode state (for devices with multimode */
/* available). */
#if defined(ADC_MULTIMODE_SUPPORT)
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002316: 687b ldr r3, [r7, #4]
8002318: 681b ldr r3, [r3, #0]
800231a: 4a20 ldr r2, [pc, #128] @ (800239c <HAL_ADC_PollForConversion+0x1ac>)
800231c: 4293 cmp r3, r2
800231e: d002 beq.n 8002326 <HAL_ADC_PollForConversion+0x136>
8002320: 687b ldr r3, [r7, #4]
8002322: 681b ldr r3, [r3, #0]
8002324: e001 b.n 800232a <HAL_ADC_PollForConversion+0x13a>
8002326: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
800232a: 687a ldr r2, [r7, #4]
800232c: 6812 ldr r2, [r2, #0]
800232e: 4293 cmp r3, r2
8002330: d008 beq.n 8002344 <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002332: 697b ldr r3, [r7, #20]
8002334: 2b00 cmp r3, #0
8002336: d005 beq.n 8002344 <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
8002338: 697b ldr r3, [r7, #20]
800233a: 2b05 cmp r3, #5
800233c: d002 beq.n 8002344 <HAL_ADC_PollForConversion+0x154>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
800233e: 697b ldr r3, [r7, #20]
8002340: 2b09 cmp r3, #9
8002342: d104 bne.n 800234e <HAL_ADC_PollForConversion+0x15e>
)
{
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
8002344: 687b ldr r3, [r7, #4]
8002346: 681b ldr r3, [r3, #0]
8002348: 68db ldr r3, [r3, #12]
800234a: 61bb str r3, [r7, #24]
800234c: e00d b.n 800236a <HAL_ADC_PollForConversion+0x17a>
}
else
{
/* Retrieve Master ADC CFGR register */
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
800234e: 687b ldr r3, [r7, #4]
8002350: 681b ldr r3, [r3, #0]
8002352: 4a12 ldr r2, [pc, #72] @ (800239c <HAL_ADC_PollForConversion+0x1ac>)
8002354: 4293 cmp r3, r2
8002356: d002 beq.n 800235e <HAL_ADC_PollForConversion+0x16e>
8002358: 687b ldr r3, [r7, #4]
800235a: 681b ldr r3, [r3, #0]
800235c: e001 b.n 8002362 <HAL_ADC_PollForConversion+0x172>
800235e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002362: 60fb str r3, [r7, #12]
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
8002364: 68fb ldr r3, [r7, #12]
8002366: 68db ldr r3, [r3, #12]
8002368: 61bb str r3, [r7, #24]
/* Retrieve handle ADC CFGR register */
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
#endif /* ADC_MULTIMODE_SUPPORT */
/* Clear polled flag */
if (tmp_Flag_End == ADC_FLAG_EOS)
800236a: 69fb ldr r3, [r7, #28]
800236c: 2b08 cmp r3, #8
800236e: d104 bne.n 800237a <HAL_ADC_PollForConversion+0x18a>
{
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
8002370: 687b ldr r3, [r7, #4]
8002372: 681b ldr r3, [r3, #0]
8002374: 2208 movs r2, #8
8002376: 601a str r2, [r3, #0]
8002378: e008 b.n 800238c <HAL_ADC_PollForConversion+0x19c>
else
{
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
800237a: 69bb ldr r3, [r7, #24]
800237c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8002380: 2b00 cmp r3, #0
8002382: d103 bne.n 800238c <HAL_ADC_PollForConversion+0x19c>
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
8002384: 687b ldr r3, [r7, #4]
8002386: 681b ldr r3, [r3, #0]
8002388: 220c movs r2, #12
800238a: 601a str r2, [r3, #0]
}
}
/* Return function status */
return HAL_OK;
800238c: 2300 movs r3, #0
}
800238e: 4618 mov r0, r3
8002390: 3720 adds r7, #32
8002392: 46bd mov sp, r7
8002394: bd80 pop {r7, pc}
8002396: bf00 nop
8002398: 50000300 .word 0x50000300
800239c: 50000100 .word 0x50000100
080023a0 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
{
80023a0: b480 push {r7}
80023a2: b083 sub sp, #12
80023a4: af00 add r7, sp, #0
80023a6: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
80023a8: 687b ldr r3, [r7, #4]
80023aa: 681b ldr r3, [r3, #0]
80023ac: 6c1b ldr r3, [r3, #64] @ 0x40
}
80023ae: 4618 mov r0, r3
80023b0: 370c adds r7, #12
80023b2: 46bd mov sp, r7
80023b4: f85d 7b04 ldr.w r7, [sp], #4
80023b8: 4770 bx lr
...
080023bc <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
80023bc: b580 push {r7, lr}
80023be: b0b6 sub sp, #216 @ 0xd8
80023c0: af00 add r7, sp, #0
80023c2: 6078 str r0, [r7, #4]
80023c4: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80023c6: 2300 movs r3, #0
80023c8: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
80023cc: 2300 movs r3, #0
80023ce: 60fb str r3, [r7, #12]
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
80023d0: 687b ldr r3, [r7, #4]
80023d2: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
80023d6: 2b01 cmp r3, #1
80023d8: d101 bne.n 80023de <HAL_ADC_ConfigChannel+0x22>
80023da: 2302 movs r3, #2
80023dc: e3c8 b.n 8002b70 <HAL_ADC_ConfigChannel+0x7b4>
80023de: 687b ldr r3, [r7, #4]
80023e0: 2201 movs r2, #1
80023e2: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80023e6: 687b ldr r3, [r7, #4]
80023e8: 681b ldr r3, [r3, #0]
80023ea: 4618 mov r0, r3
80023ec: f7ff fc52 bl 8001c94 <LL_ADC_REG_IsConversionOngoing>
80023f0: 4603 mov r3, r0
80023f2: 2b00 cmp r3, #0
80023f4: f040 83ad bne.w 8002b52 <HAL_ADC_ConfigChannel+0x796>
{
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
80023f8: 687b ldr r3, [r7, #4]
80023fa: 6818 ldr r0, [r3, #0]
80023fc: 683b ldr r3, [r7, #0]
80023fe: 6859 ldr r1, [r3, #4]
8002400: 683b ldr r3, [r7, #0]
8002402: 681b ldr r3, [r3, #0]
8002404: 461a mov r2, r3
8002406: f7ff faea bl 80019de <LL_ADC_REG_SetSequencerRanks>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
800240a: 687b ldr r3, [r7, #4]
800240c: 681b ldr r3, [r3, #0]
800240e: 4618 mov r0, r3
8002410: f7ff fc40 bl 8001c94 <LL_ADC_REG_IsConversionOngoing>
8002414: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002418: 687b ldr r3, [r7, #4]
800241a: 681b ldr r3, [r3, #0]
800241c: 4618 mov r0, r3
800241e: f7ff fc60 bl 8001ce2 <LL_ADC_INJ_IsConversionOngoing>
8002422: f8c7 00cc str.w r0, [r7, #204] @ 0xcc
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8002426: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
800242a: 2b00 cmp r3, #0
800242c: f040 81d9 bne.w 80027e2 <HAL_ADC_ConfigChannel+0x426>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002430: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
8002434: 2b00 cmp r3, #0
8002436: f040 81d4 bne.w 80027e2 <HAL_ADC_ConfigChannel+0x426>
)
{
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
800243a: 683b ldr r3, [r7, #0]
800243c: 689b ldr r3, [r3, #8]
800243e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8002442: d10f bne.n 8002464 <HAL_ADC_ConfigChannel+0xa8>
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
8002444: 687b ldr r3, [r7, #4]
8002446: 6818 ldr r0, [r3, #0]
8002448: 683b ldr r3, [r7, #0]
800244a: 681b ldr r3, [r3, #0]
800244c: 2200 movs r2, #0
800244e: 4619 mov r1, r3
8002450: f7ff faf1 bl 8001a36 <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
8002454: 687b ldr r3, [r7, #4]
8002456: 681b ldr r3, [r3, #0]
8002458: f04f 4100 mov.w r1, #2147483648 @ 0x80000000
800245c: 4618 mov r0, r3
800245e: f7ff fa98 bl 8001992 <LL_ADC_SetSamplingTimeCommonConfig>
8002462: e00e b.n 8002482 <HAL_ADC_ConfigChannel+0xc6>
}
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
8002464: 687b ldr r3, [r7, #4]
8002466: 6818 ldr r0, [r3, #0]
8002468: 683b ldr r3, [r7, #0]
800246a: 6819 ldr r1, [r3, #0]
800246c: 683b ldr r3, [r7, #0]
800246e: 689b ldr r3, [r3, #8]
8002470: 461a mov r2, r3
8002472: f7ff fae0 bl 8001a36 <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
8002476: 687b ldr r3, [r7, #4]
8002478: 681b ldr r3, [r3, #0]
800247a: 2100 movs r1, #0
800247c: 4618 mov r0, r3
800247e: f7ff fa88 bl 8001992 <LL_ADC_SetSamplingTimeCommonConfig>
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
8002482: 683b ldr r3, [r7, #0]
8002484: 695a ldr r2, [r3, #20]
8002486: 687b ldr r3, [r7, #4]
8002488: 681b ldr r3, [r3, #0]
800248a: 68db ldr r3, [r3, #12]
800248c: 08db lsrs r3, r3, #3
800248e: f003 0303 and.w r3, r3, #3
8002492: 005b lsls r3, r3, #1
8002494: fa02 f303 lsl.w r3, r2, r3
8002498: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
800249c: 683b ldr r3, [r7, #0]
800249e: 691b ldr r3, [r3, #16]
80024a0: 2b04 cmp r3, #4
80024a2: d022 beq.n 80024ea <HAL_ADC_ConfigChannel+0x12e>
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
80024a4: 687b ldr r3, [r7, #4]
80024a6: 6818 ldr r0, [r3, #0]
80024a8: 683b ldr r3, [r7, #0]
80024aa: 6919 ldr r1, [r3, #16]
80024ac: 683b ldr r3, [r7, #0]
80024ae: 681a ldr r2, [r3, #0]
80024b0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80024b4: f7ff f9e2 bl 800187c <LL_ADC_SetOffset>
assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
/* Set ADC selected offset sign & saturation */
LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
80024b8: 687b ldr r3, [r7, #4]
80024ba: 6818 ldr r0, [r3, #0]
80024bc: 683b ldr r3, [r7, #0]
80024be: 6919 ldr r1, [r3, #16]
80024c0: 683b ldr r3, [r7, #0]
80024c2: 699b ldr r3, [r3, #24]
80024c4: 461a mov r2, r3
80024c6: f7ff fa2e bl 8001926 <LL_ADC_SetOffsetSign>
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
80024ca: 687b ldr r3, [r7, #4]
80024cc: 6818 ldr r0, [r3, #0]
80024ce: 683b ldr r3, [r7, #0]
80024d0: 6919 ldr r1, [r3, #16]
(pConfig->OffsetSaturation == ENABLE) ?
80024d2: 683b ldr r3, [r7, #0]
80024d4: 7f1b ldrb r3, [r3, #28]
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
80024d6: 2b01 cmp r3, #1
80024d8: d102 bne.n 80024e0 <HAL_ADC_ConfigChannel+0x124>
80024da: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80024de: e000 b.n 80024e2 <HAL_ADC_ConfigChannel+0x126>
80024e0: 2300 movs r3, #0
80024e2: 461a mov r2, r3
80024e4: f7ff fa3a bl 800195c <LL_ADC_SetOffsetSaturation>
80024e8: e17b b.n 80027e2 <HAL_ADC_ConfigChannel+0x426>
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
80024ea: 687b ldr r3, [r7, #4]
80024ec: 681b ldr r3, [r3, #0]
80024ee: 2100 movs r1, #0
80024f0: 4618 mov r0, r3
80024f2: f7ff f9e7 bl 80018c4 <LL_ADC_GetOffsetChannel>
80024f6: 4603 mov r3, r0
80024f8: f3c3 0312 ubfx r3, r3, #0, #19
80024fc: 2b00 cmp r3, #0
80024fe: d10a bne.n 8002516 <HAL_ADC_ConfigChannel+0x15a>
8002500: 687b ldr r3, [r7, #4]
8002502: 681b ldr r3, [r3, #0]
8002504: 2100 movs r1, #0
8002506: 4618 mov r0, r3
8002508: f7ff f9dc bl 80018c4 <LL_ADC_GetOffsetChannel>
800250c: 4603 mov r3, r0
800250e: 0e9b lsrs r3, r3, #26
8002510: f003 021f and.w r2, r3, #31
8002514: e01e b.n 8002554 <HAL_ADC_ConfigChannel+0x198>
8002516: 687b ldr r3, [r7, #4]
8002518: 681b ldr r3, [r3, #0]
800251a: 2100 movs r1, #0
800251c: 4618 mov r0, r3
800251e: f7ff f9d1 bl 80018c4 <LL_ADC_GetOffsetChannel>
8002522: 4603 mov r3, r0
8002524: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002528: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
800252c: fa93 f3a3 rbit r3, r3
8002530: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8002534: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002538: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
800253c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002540: 2b00 cmp r3, #0
8002542: d101 bne.n 8002548 <HAL_ADC_ConfigChannel+0x18c>
{
return 32U;
8002544: 2320 movs r3, #32
8002546: e004 b.n 8002552 <HAL_ADC_ConfigChannel+0x196>
}
return __builtin_clz(value);
8002548: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
800254c: fab3 f383 clz r3, r3
8002550: b2db uxtb r3, r3
8002552: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002554: 683b ldr r3, [r7, #0]
8002556: 681b ldr r3, [r3, #0]
8002558: f3c3 0312 ubfx r3, r3, #0, #19
800255c: 2b00 cmp r3, #0
800255e: d105 bne.n 800256c <HAL_ADC_ConfigChannel+0x1b0>
8002560: 683b ldr r3, [r7, #0]
8002562: 681b ldr r3, [r3, #0]
8002564: 0e9b lsrs r3, r3, #26
8002566: f003 031f and.w r3, r3, #31
800256a: e018 b.n 800259e <HAL_ADC_ConfigChannel+0x1e2>
800256c: 683b ldr r3, [r7, #0]
800256e: 681b ldr r3, [r3, #0]
8002570: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002574: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
8002578: fa93 f3a3 rbit r3, r3
800257c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
return result;
8002580: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8002584: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
if (value == 0U)
8002588: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
800258c: 2b00 cmp r3, #0
800258e: d101 bne.n 8002594 <HAL_ADC_ConfigChannel+0x1d8>
return 32U;
8002590: 2320 movs r3, #32
8002592: e004 b.n 800259e <HAL_ADC_ConfigChannel+0x1e2>
return __builtin_clz(value);
8002594: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8002598: fab3 f383 clz r3, r3
800259c: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
800259e: 429a cmp r2, r3
80025a0: d106 bne.n 80025b0 <HAL_ADC_ConfigChannel+0x1f4>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
80025a2: 687b ldr r3, [r7, #4]
80025a4: 681b ldr r3, [r3, #0]
80025a6: 2200 movs r2, #0
80025a8: 2100 movs r1, #0
80025aa: 4618 mov r0, r3
80025ac: f7ff f9a0 bl 80018f0 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
80025b0: 687b ldr r3, [r7, #4]
80025b2: 681b ldr r3, [r3, #0]
80025b4: 2101 movs r1, #1
80025b6: 4618 mov r0, r3
80025b8: f7ff f984 bl 80018c4 <LL_ADC_GetOffsetChannel>
80025bc: 4603 mov r3, r0
80025be: f3c3 0312 ubfx r3, r3, #0, #19
80025c2: 2b00 cmp r3, #0
80025c4: d10a bne.n 80025dc <HAL_ADC_ConfigChannel+0x220>
80025c6: 687b ldr r3, [r7, #4]
80025c8: 681b ldr r3, [r3, #0]
80025ca: 2101 movs r1, #1
80025cc: 4618 mov r0, r3
80025ce: f7ff f979 bl 80018c4 <LL_ADC_GetOffsetChannel>
80025d2: 4603 mov r3, r0
80025d4: 0e9b lsrs r3, r3, #26
80025d6: f003 021f and.w r2, r3, #31
80025da: e01e b.n 800261a <HAL_ADC_ConfigChannel+0x25e>
80025dc: 687b ldr r3, [r7, #4]
80025de: 681b ldr r3, [r3, #0]
80025e0: 2101 movs r1, #1
80025e2: 4618 mov r0, r3
80025e4: f7ff f96e bl 80018c4 <LL_ADC_GetOffsetChannel>
80025e8: 4603 mov r3, r0
80025ea: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80025ee: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
80025f2: fa93 f3a3 rbit r3, r3
80025f6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return result;
80025fa: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
80025fe: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
if (value == 0U)
8002602: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002606: 2b00 cmp r3, #0
8002608: d101 bne.n 800260e <HAL_ADC_ConfigChannel+0x252>
return 32U;
800260a: 2320 movs r3, #32
800260c: e004 b.n 8002618 <HAL_ADC_ConfigChannel+0x25c>
return __builtin_clz(value);
800260e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002612: fab3 f383 clz r3, r3
8002616: b2db uxtb r3, r3
8002618: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
800261a: 683b ldr r3, [r7, #0]
800261c: 681b ldr r3, [r3, #0]
800261e: f3c3 0312 ubfx r3, r3, #0, #19
8002622: 2b00 cmp r3, #0
8002624: d105 bne.n 8002632 <HAL_ADC_ConfigChannel+0x276>
8002626: 683b ldr r3, [r7, #0]
8002628: 681b ldr r3, [r3, #0]
800262a: 0e9b lsrs r3, r3, #26
800262c: f003 031f and.w r3, r3, #31
8002630: e018 b.n 8002664 <HAL_ADC_ConfigChannel+0x2a8>
8002632: 683b ldr r3, [r7, #0]
8002634: 681b ldr r3, [r3, #0]
8002636: f8c7 3098 str.w r3, [r7, #152] @ 0x98
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800263a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
800263e: fa93 f3a3 rbit r3, r3
8002642: f8c7 3094 str.w r3, [r7, #148] @ 0x94
return result;
8002646: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
800264a: f8c7 309c str.w r3, [r7, #156] @ 0x9c
if (value == 0U)
800264e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002652: 2b00 cmp r3, #0
8002654: d101 bne.n 800265a <HAL_ADC_ConfigChannel+0x29e>
return 32U;
8002656: 2320 movs r3, #32
8002658: e004 b.n 8002664 <HAL_ADC_ConfigChannel+0x2a8>
return __builtin_clz(value);
800265a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800265e: fab3 f383 clz r3, r3
8002662: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
8002664: 429a cmp r2, r3
8002666: d106 bne.n 8002676 <HAL_ADC_ConfigChannel+0x2ba>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
8002668: 687b ldr r3, [r7, #4]
800266a: 681b ldr r3, [r3, #0]
800266c: 2200 movs r2, #0
800266e: 2101 movs r1, #1
8002670: 4618 mov r0, r3
8002672: f7ff f93d bl 80018f0 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002676: 687b ldr r3, [r7, #4]
8002678: 681b ldr r3, [r3, #0]
800267a: 2102 movs r1, #2
800267c: 4618 mov r0, r3
800267e: f7ff f921 bl 80018c4 <LL_ADC_GetOffsetChannel>
8002682: 4603 mov r3, r0
8002684: f3c3 0312 ubfx r3, r3, #0, #19
8002688: 2b00 cmp r3, #0
800268a: d10a bne.n 80026a2 <HAL_ADC_ConfigChannel+0x2e6>
800268c: 687b ldr r3, [r7, #4]
800268e: 681b ldr r3, [r3, #0]
8002690: 2102 movs r1, #2
8002692: 4618 mov r0, r3
8002694: f7ff f916 bl 80018c4 <LL_ADC_GetOffsetChannel>
8002698: 4603 mov r3, r0
800269a: 0e9b lsrs r3, r3, #26
800269c: f003 021f and.w r2, r3, #31
80026a0: e01e b.n 80026e0 <HAL_ADC_ConfigChannel+0x324>
80026a2: 687b ldr r3, [r7, #4]
80026a4: 681b ldr r3, [r3, #0]
80026a6: 2102 movs r1, #2
80026a8: 4618 mov r0, r3
80026aa: f7ff f90b bl 80018c4 <LL_ADC_GetOffsetChannel>
80026ae: 4603 mov r3, r0
80026b0: f8c7 308c str.w r3, [r7, #140] @ 0x8c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80026b4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80026b8: fa93 f3a3 rbit r3, r3
80026bc: f8c7 3088 str.w r3, [r7, #136] @ 0x88
return result;
80026c0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
80026c4: f8c7 3090 str.w r3, [r7, #144] @ 0x90
if (value == 0U)
80026c8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
80026cc: 2b00 cmp r3, #0
80026ce: d101 bne.n 80026d4 <HAL_ADC_ConfigChannel+0x318>
return 32U;
80026d0: 2320 movs r3, #32
80026d2: e004 b.n 80026de <HAL_ADC_ConfigChannel+0x322>
return __builtin_clz(value);
80026d4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
80026d8: fab3 f383 clz r3, r3
80026dc: b2db uxtb r3, r3
80026de: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
80026e0: 683b ldr r3, [r7, #0]
80026e2: 681b ldr r3, [r3, #0]
80026e4: f3c3 0312 ubfx r3, r3, #0, #19
80026e8: 2b00 cmp r3, #0
80026ea: d105 bne.n 80026f8 <HAL_ADC_ConfigChannel+0x33c>
80026ec: 683b ldr r3, [r7, #0]
80026ee: 681b ldr r3, [r3, #0]
80026f0: 0e9b lsrs r3, r3, #26
80026f2: f003 031f and.w r3, r3, #31
80026f6: e016 b.n 8002726 <HAL_ADC_ConfigChannel+0x36a>
80026f8: 683b ldr r3, [r7, #0]
80026fa: 681b ldr r3, [r3, #0]
80026fc: f8c7 3080 str.w r3, [r7, #128] @ 0x80
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002700: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8002704: fa93 f3a3 rbit r3, r3
8002708: 67fb str r3, [r7, #124] @ 0x7c
return result;
800270a: 6ffb ldr r3, [r7, #124] @ 0x7c
800270c: f8c7 3084 str.w r3, [r7, #132] @ 0x84
if (value == 0U)
8002710: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002714: 2b00 cmp r3, #0
8002716: d101 bne.n 800271c <HAL_ADC_ConfigChannel+0x360>
return 32U;
8002718: 2320 movs r3, #32
800271a: e004 b.n 8002726 <HAL_ADC_ConfigChannel+0x36a>
return __builtin_clz(value);
800271c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8002720: fab3 f383 clz r3, r3
8002724: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002726: 429a cmp r2, r3
8002728: d106 bne.n 8002738 <HAL_ADC_ConfigChannel+0x37c>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
800272a: 687b ldr r3, [r7, #4]
800272c: 681b ldr r3, [r3, #0]
800272e: 2200 movs r2, #0
8002730: 2102 movs r1, #2
8002732: 4618 mov r0, r3
8002734: f7ff f8dc bl 80018f0 <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002738: 687b ldr r3, [r7, #4]
800273a: 681b ldr r3, [r3, #0]
800273c: 2103 movs r1, #3
800273e: 4618 mov r0, r3
8002740: f7ff f8c0 bl 80018c4 <LL_ADC_GetOffsetChannel>
8002744: 4603 mov r3, r0
8002746: f3c3 0312 ubfx r3, r3, #0, #19
800274a: 2b00 cmp r3, #0
800274c: d10a bne.n 8002764 <HAL_ADC_ConfigChannel+0x3a8>
800274e: 687b ldr r3, [r7, #4]
8002750: 681b ldr r3, [r3, #0]
8002752: 2103 movs r1, #3
8002754: 4618 mov r0, r3
8002756: f7ff f8b5 bl 80018c4 <LL_ADC_GetOffsetChannel>
800275a: 4603 mov r3, r0
800275c: 0e9b lsrs r3, r3, #26
800275e: f003 021f and.w r2, r3, #31
8002762: e017 b.n 8002794 <HAL_ADC_ConfigChannel+0x3d8>
8002764: 687b ldr r3, [r7, #4]
8002766: 681b ldr r3, [r3, #0]
8002768: 2103 movs r1, #3
800276a: 4618 mov r0, r3
800276c: f7ff f8aa bl 80018c4 <LL_ADC_GetOffsetChannel>
8002770: 4603 mov r3, r0
8002772: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002774: 6f7b ldr r3, [r7, #116] @ 0x74
8002776: fa93 f3a3 rbit r3, r3
800277a: 673b str r3, [r7, #112] @ 0x70
return result;
800277c: 6f3b ldr r3, [r7, #112] @ 0x70
800277e: 67bb str r3, [r7, #120] @ 0x78
if (value == 0U)
8002780: 6fbb ldr r3, [r7, #120] @ 0x78
8002782: 2b00 cmp r3, #0
8002784: d101 bne.n 800278a <HAL_ADC_ConfigChannel+0x3ce>
return 32U;
8002786: 2320 movs r3, #32
8002788: e003 b.n 8002792 <HAL_ADC_ConfigChannel+0x3d6>
return __builtin_clz(value);
800278a: 6fbb ldr r3, [r7, #120] @ 0x78
800278c: fab3 f383 clz r3, r3
8002790: b2db uxtb r3, r3
8002792: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002794: 683b ldr r3, [r7, #0]
8002796: 681b ldr r3, [r3, #0]
8002798: f3c3 0312 ubfx r3, r3, #0, #19
800279c: 2b00 cmp r3, #0
800279e: d105 bne.n 80027ac <HAL_ADC_ConfigChannel+0x3f0>
80027a0: 683b ldr r3, [r7, #0]
80027a2: 681b ldr r3, [r3, #0]
80027a4: 0e9b lsrs r3, r3, #26
80027a6: f003 031f and.w r3, r3, #31
80027aa: e011 b.n 80027d0 <HAL_ADC_ConfigChannel+0x414>
80027ac: 683b ldr r3, [r7, #0]
80027ae: 681b ldr r3, [r3, #0]
80027b0: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80027b2: 6ebb ldr r3, [r7, #104] @ 0x68
80027b4: fa93 f3a3 rbit r3, r3
80027b8: 667b str r3, [r7, #100] @ 0x64
return result;
80027ba: 6e7b ldr r3, [r7, #100] @ 0x64
80027bc: 66fb str r3, [r7, #108] @ 0x6c
if (value == 0U)
80027be: 6efb ldr r3, [r7, #108] @ 0x6c
80027c0: 2b00 cmp r3, #0
80027c2: d101 bne.n 80027c8 <HAL_ADC_ConfigChannel+0x40c>
return 32U;
80027c4: 2320 movs r3, #32
80027c6: e003 b.n 80027d0 <HAL_ADC_ConfigChannel+0x414>
return __builtin_clz(value);
80027c8: 6efb ldr r3, [r7, #108] @ 0x6c
80027ca: fab3 f383 clz r3, r3
80027ce: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
80027d0: 429a cmp r2, r3
80027d2: d106 bne.n 80027e2 <HAL_ADC_ConfigChannel+0x426>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
80027d4: 687b ldr r3, [r7, #4]
80027d6: 681b ldr r3, [r3, #0]
80027d8: 2200 movs r2, #0
80027da: 2103 movs r1, #3
80027dc: 4618 mov r0, r3
80027de: f7ff f887 bl 80018f0 <LL_ADC_SetOffsetState>
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80027e2: 687b ldr r3, [r7, #4]
80027e4: 681b ldr r3, [r3, #0]
80027e6: 4618 mov r0, r3
80027e8: f7ff fa06 bl 8001bf8 <LL_ADC_IsEnabled>
80027ec: 4603 mov r3, r0
80027ee: 2b00 cmp r3, #0
80027f0: f040 8140 bne.w 8002a74 <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
80027f4: 687b ldr r3, [r7, #4]
80027f6: 6818 ldr r0, [r3, #0]
80027f8: 683b ldr r3, [r7, #0]
80027fa: 6819 ldr r1, [r3, #0]
80027fc: 683b ldr r3, [r7, #0]
80027fe: 68db ldr r3, [r3, #12]
8002800: 461a mov r2, r3
8002802: f7ff f943 bl 8001a8c <LL_ADC_SetChannelSingleDiff>
/* Configuration of differential mode */
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8002806: 683b ldr r3, [r7, #0]
8002808: 68db ldr r3, [r3, #12]
800280a: 4a8f ldr r2, [pc, #572] @ (8002a48 <HAL_ADC_ConfigChannel+0x68c>)
800280c: 4293 cmp r3, r2
800280e: f040 8131 bne.w 8002a74 <HAL_ADC_ConfigChannel+0x6b8>
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002812: 687b ldr r3, [r7, #4]
8002814: 6818 ldr r0, [r3, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002816: 683b ldr r3, [r7, #0]
8002818: 681b ldr r3, [r3, #0]
800281a: f3c3 0312 ubfx r3, r3, #0, #19
800281e: 2b00 cmp r3, #0
8002820: d10b bne.n 800283a <HAL_ADC_ConfigChannel+0x47e>
8002822: 683b ldr r3, [r7, #0]
8002824: 681b ldr r3, [r3, #0]
8002826: 0e9b lsrs r3, r3, #26
8002828: 3301 adds r3, #1
800282a: f003 031f and.w r3, r3, #31
800282e: 2b09 cmp r3, #9
8002830: bf94 ite ls
8002832: 2301 movls r3, #1
8002834: 2300 movhi r3, #0
8002836: b2db uxtb r3, r3
8002838: e019 b.n 800286e <HAL_ADC_ConfigChannel+0x4b2>
800283a: 683b ldr r3, [r7, #0]
800283c: 681b ldr r3, [r3, #0]
800283e: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002840: 6dfb ldr r3, [r7, #92] @ 0x5c
8002842: fa93 f3a3 rbit r3, r3
8002846: 65bb str r3, [r7, #88] @ 0x58
return result;
8002848: 6dbb ldr r3, [r7, #88] @ 0x58
800284a: 663b str r3, [r7, #96] @ 0x60
if (value == 0U)
800284c: 6e3b ldr r3, [r7, #96] @ 0x60
800284e: 2b00 cmp r3, #0
8002850: d101 bne.n 8002856 <HAL_ADC_ConfigChannel+0x49a>
return 32U;
8002852: 2320 movs r3, #32
8002854: e003 b.n 800285e <HAL_ADC_ConfigChannel+0x4a2>
return __builtin_clz(value);
8002856: 6e3b ldr r3, [r7, #96] @ 0x60
8002858: fab3 f383 clz r3, r3
800285c: b2db uxtb r3, r3
800285e: 3301 adds r3, #1
8002860: f003 031f and.w r3, r3, #31
8002864: 2b09 cmp r3, #9
8002866: bf94 ite ls
8002868: 2301 movls r3, #1
800286a: 2300 movhi r3, #0
800286c: b2db uxtb r3, r3
LL_ADC_SetChannelSamplingTime(hadc->Instance,
800286e: 2b00 cmp r3, #0
8002870: d079 beq.n 8002966 <HAL_ADC_ConfigChannel+0x5aa>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002872: 683b ldr r3, [r7, #0]
8002874: 681b ldr r3, [r3, #0]
8002876: f3c3 0312 ubfx r3, r3, #0, #19
800287a: 2b00 cmp r3, #0
800287c: d107 bne.n 800288e <HAL_ADC_ConfigChannel+0x4d2>
800287e: 683b ldr r3, [r7, #0]
8002880: 681b ldr r3, [r3, #0]
8002882: 0e9b lsrs r3, r3, #26
8002884: 3301 adds r3, #1
8002886: 069b lsls r3, r3, #26
8002888: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
800288c: e015 b.n 80028ba <HAL_ADC_ConfigChannel+0x4fe>
800288e: 683b ldr r3, [r7, #0]
8002890: 681b ldr r3, [r3, #0]
8002892: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002894: 6d3b ldr r3, [r7, #80] @ 0x50
8002896: fa93 f3a3 rbit r3, r3
800289a: 64fb str r3, [r7, #76] @ 0x4c
return result;
800289c: 6cfb ldr r3, [r7, #76] @ 0x4c
800289e: 657b str r3, [r7, #84] @ 0x54
if (value == 0U)
80028a0: 6d7b ldr r3, [r7, #84] @ 0x54
80028a2: 2b00 cmp r3, #0
80028a4: d101 bne.n 80028aa <HAL_ADC_ConfigChannel+0x4ee>
return 32U;
80028a6: 2320 movs r3, #32
80028a8: e003 b.n 80028b2 <HAL_ADC_ConfigChannel+0x4f6>
return __builtin_clz(value);
80028aa: 6d7b ldr r3, [r7, #84] @ 0x54
80028ac: fab3 f383 clz r3, r3
80028b0: b2db uxtb r3, r3
80028b2: 3301 adds r3, #1
80028b4: 069b lsls r3, r3, #26
80028b6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
80028ba: 683b ldr r3, [r7, #0]
80028bc: 681b ldr r3, [r3, #0]
80028be: f3c3 0312 ubfx r3, r3, #0, #19
80028c2: 2b00 cmp r3, #0
80028c4: d109 bne.n 80028da <HAL_ADC_ConfigChannel+0x51e>
80028c6: 683b ldr r3, [r7, #0]
80028c8: 681b ldr r3, [r3, #0]
80028ca: 0e9b lsrs r3, r3, #26
80028cc: 3301 adds r3, #1
80028ce: f003 031f and.w r3, r3, #31
80028d2: 2101 movs r1, #1
80028d4: fa01 f303 lsl.w r3, r1, r3
80028d8: e017 b.n 800290a <HAL_ADC_ConfigChannel+0x54e>
80028da: 683b ldr r3, [r7, #0]
80028dc: 681b ldr r3, [r3, #0]
80028de: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028e0: 6c7b ldr r3, [r7, #68] @ 0x44
80028e2: fa93 f3a3 rbit r3, r3
80028e6: 643b str r3, [r7, #64] @ 0x40
return result;
80028e8: 6c3b ldr r3, [r7, #64] @ 0x40
80028ea: 64bb str r3, [r7, #72] @ 0x48
if (value == 0U)
80028ec: 6cbb ldr r3, [r7, #72] @ 0x48
80028ee: 2b00 cmp r3, #0
80028f0: d101 bne.n 80028f6 <HAL_ADC_ConfigChannel+0x53a>
return 32U;
80028f2: 2320 movs r3, #32
80028f4: e003 b.n 80028fe <HAL_ADC_ConfigChannel+0x542>
return __builtin_clz(value);
80028f6: 6cbb ldr r3, [r7, #72] @ 0x48
80028f8: fab3 f383 clz r3, r3
80028fc: b2db uxtb r3, r3
80028fe: 3301 adds r3, #1
8002900: f003 031f and.w r3, r3, #31
8002904: 2101 movs r1, #1
8002906: fa01 f303 lsl.w r3, r1, r3
800290a: ea42 0103 orr.w r1, r2, r3
800290e: 683b ldr r3, [r7, #0]
8002910: 681b ldr r3, [r3, #0]
8002912: f3c3 0312 ubfx r3, r3, #0, #19
8002916: 2b00 cmp r3, #0
8002918: d10a bne.n 8002930 <HAL_ADC_ConfigChannel+0x574>
800291a: 683b ldr r3, [r7, #0]
800291c: 681b ldr r3, [r3, #0]
800291e: 0e9b lsrs r3, r3, #26
8002920: 3301 adds r3, #1
8002922: f003 021f and.w r2, r3, #31
8002926: 4613 mov r3, r2
8002928: 005b lsls r3, r3, #1
800292a: 4413 add r3, r2
800292c: 051b lsls r3, r3, #20
800292e: e018 b.n 8002962 <HAL_ADC_ConfigChannel+0x5a6>
8002930: 683b ldr r3, [r7, #0]
8002932: 681b ldr r3, [r3, #0]
8002934: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002936: 6bbb ldr r3, [r7, #56] @ 0x38
8002938: fa93 f3a3 rbit r3, r3
800293c: 637b str r3, [r7, #52] @ 0x34
return result;
800293e: 6b7b ldr r3, [r7, #52] @ 0x34
8002940: 63fb str r3, [r7, #60] @ 0x3c
if (value == 0U)
8002942: 6bfb ldr r3, [r7, #60] @ 0x3c
8002944: 2b00 cmp r3, #0
8002946: d101 bne.n 800294c <HAL_ADC_ConfigChannel+0x590>
return 32U;
8002948: 2320 movs r3, #32
800294a: e003 b.n 8002954 <HAL_ADC_ConfigChannel+0x598>
return __builtin_clz(value);
800294c: 6bfb ldr r3, [r7, #60] @ 0x3c
800294e: fab3 f383 clz r3, r3
8002952: b2db uxtb r3, r3
8002954: 3301 adds r3, #1
8002956: f003 021f and.w r2, r3, #31
800295a: 4613 mov r3, r2
800295c: 005b lsls r3, r3, #1
800295e: 4413 add r3, r2
8002960: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002962: 430b orrs r3, r1
8002964: e081 b.n 8002a6a <HAL_ADC_ConfigChannel+0x6ae>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002966: 683b ldr r3, [r7, #0]
8002968: 681b ldr r3, [r3, #0]
800296a: f3c3 0312 ubfx r3, r3, #0, #19
800296e: 2b00 cmp r3, #0
8002970: d107 bne.n 8002982 <HAL_ADC_ConfigChannel+0x5c6>
8002972: 683b ldr r3, [r7, #0]
8002974: 681b ldr r3, [r3, #0]
8002976: 0e9b lsrs r3, r3, #26
8002978: 3301 adds r3, #1
800297a: 069b lsls r3, r3, #26
800297c: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002980: e015 b.n 80029ae <HAL_ADC_ConfigChannel+0x5f2>
8002982: 683b ldr r3, [r7, #0]
8002984: 681b ldr r3, [r3, #0]
8002986: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002988: 6afb ldr r3, [r7, #44] @ 0x2c
800298a: fa93 f3a3 rbit r3, r3
800298e: 62bb str r3, [r7, #40] @ 0x28
return result;
8002990: 6abb ldr r3, [r7, #40] @ 0x28
8002992: 633b str r3, [r7, #48] @ 0x30
if (value == 0U)
8002994: 6b3b ldr r3, [r7, #48] @ 0x30
8002996: 2b00 cmp r3, #0
8002998: d101 bne.n 800299e <HAL_ADC_ConfigChannel+0x5e2>
return 32U;
800299a: 2320 movs r3, #32
800299c: e003 b.n 80029a6 <HAL_ADC_ConfigChannel+0x5ea>
return __builtin_clz(value);
800299e: 6b3b ldr r3, [r7, #48] @ 0x30
80029a0: fab3 f383 clz r3, r3
80029a4: b2db uxtb r3, r3
80029a6: 3301 adds r3, #1
80029a8: 069b lsls r3, r3, #26
80029aa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
80029ae: 683b ldr r3, [r7, #0]
80029b0: 681b ldr r3, [r3, #0]
80029b2: f3c3 0312 ubfx r3, r3, #0, #19
80029b6: 2b00 cmp r3, #0
80029b8: d109 bne.n 80029ce <HAL_ADC_ConfigChannel+0x612>
80029ba: 683b ldr r3, [r7, #0]
80029bc: 681b ldr r3, [r3, #0]
80029be: 0e9b lsrs r3, r3, #26
80029c0: 3301 adds r3, #1
80029c2: f003 031f and.w r3, r3, #31
80029c6: 2101 movs r1, #1
80029c8: fa01 f303 lsl.w r3, r1, r3
80029cc: e017 b.n 80029fe <HAL_ADC_ConfigChannel+0x642>
80029ce: 683b ldr r3, [r7, #0]
80029d0: 681b ldr r3, [r3, #0]
80029d2: 623b str r3, [r7, #32]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80029d4: 6a3b ldr r3, [r7, #32]
80029d6: fa93 f3a3 rbit r3, r3
80029da: 61fb str r3, [r7, #28]
return result;
80029dc: 69fb ldr r3, [r7, #28]
80029de: 627b str r3, [r7, #36] @ 0x24
if (value == 0U)
80029e0: 6a7b ldr r3, [r7, #36] @ 0x24
80029e2: 2b00 cmp r3, #0
80029e4: d101 bne.n 80029ea <HAL_ADC_ConfigChannel+0x62e>
return 32U;
80029e6: 2320 movs r3, #32
80029e8: e003 b.n 80029f2 <HAL_ADC_ConfigChannel+0x636>
return __builtin_clz(value);
80029ea: 6a7b ldr r3, [r7, #36] @ 0x24
80029ec: fab3 f383 clz r3, r3
80029f0: b2db uxtb r3, r3
80029f2: 3301 adds r3, #1
80029f4: f003 031f and.w r3, r3, #31
80029f8: 2101 movs r1, #1
80029fa: fa01 f303 lsl.w r3, r1, r3
80029fe: ea42 0103 orr.w r1, r2, r3
8002a02: 683b ldr r3, [r7, #0]
8002a04: 681b ldr r3, [r3, #0]
8002a06: f3c3 0312 ubfx r3, r3, #0, #19
8002a0a: 2b00 cmp r3, #0
8002a0c: d10d bne.n 8002a2a <HAL_ADC_ConfigChannel+0x66e>
8002a0e: 683b ldr r3, [r7, #0]
8002a10: 681b ldr r3, [r3, #0]
8002a12: 0e9b lsrs r3, r3, #26
8002a14: 3301 adds r3, #1
8002a16: f003 021f and.w r2, r3, #31
8002a1a: 4613 mov r3, r2
8002a1c: 005b lsls r3, r3, #1
8002a1e: 4413 add r3, r2
8002a20: 3b1e subs r3, #30
8002a22: 051b lsls r3, r3, #20
8002a24: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8002a28: e01e b.n 8002a68 <HAL_ADC_ConfigChannel+0x6ac>
8002a2a: 683b ldr r3, [r7, #0]
8002a2c: 681b ldr r3, [r3, #0]
8002a2e: 617b str r3, [r7, #20]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a30: 697b ldr r3, [r7, #20]
8002a32: fa93 f3a3 rbit r3, r3
8002a36: 613b str r3, [r7, #16]
return result;
8002a38: 693b ldr r3, [r7, #16]
8002a3a: 61bb str r3, [r7, #24]
if (value == 0U)
8002a3c: 69bb ldr r3, [r7, #24]
8002a3e: 2b00 cmp r3, #0
8002a40: d104 bne.n 8002a4c <HAL_ADC_ConfigChannel+0x690>
return 32U;
8002a42: 2320 movs r3, #32
8002a44: e006 b.n 8002a54 <HAL_ADC_ConfigChannel+0x698>
8002a46: bf00 nop
8002a48: 407f0000 .word 0x407f0000
return __builtin_clz(value);
8002a4c: 69bb ldr r3, [r7, #24]
8002a4e: fab3 f383 clz r3, r3
8002a52: b2db uxtb r3, r3
8002a54: 3301 adds r3, #1
8002a56: f003 021f and.w r2, r3, #31
8002a5a: 4613 mov r3, r2
8002a5c: 005b lsls r3, r3, #1
8002a5e: 4413 add r3, r2
8002a60: 3b1e subs r3, #30
8002a62: 051b lsls r3, r3, #20
8002a64: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002a68: 430b orrs r3, r1
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
8002a6a: 683a ldr r2, [r7, #0]
8002a6c: 6892 ldr r2, [r2, #8]
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002a6e: 4619 mov r1, r3
8002a70: f7fe ffe1 bl 8001a36 <LL_ADC_SetChannelSamplingTime>
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
8002a74: 683b ldr r3, [r7, #0]
8002a76: 681a ldr r2, [r3, #0]
8002a78: 4b3f ldr r3, [pc, #252] @ (8002b78 <HAL_ADC_ConfigChannel+0x7bc>)
8002a7a: 4013 ands r3, r2
8002a7c: 2b00 cmp r3, #0
8002a7e: d071 beq.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8002a80: 483e ldr r0, [pc, #248] @ (8002b7c <HAL_ADC_ConfigChannel+0x7c0>)
8002a82: f7fe feed bl 8001860 <LL_ADC_GetCommonPathInternalCh>
8002a86: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
8002a8a: 683b ldr r3, [r7, #0]
8002a8c: 681b ldr r3, [r3, #0]
8002a8e: 4a3c ldr r2, [pc, #240] @ (8002b80 <HAL_ADC_ConfigChannel+0x7c4>)
8002a90: 4293 cmp r3, r2
8002a92: d004 beq.n 8002a9e <HAL_ADC_ConfigChannel+0x6e2>
8002a94: 683b ldr r3, [r7, #0]
8002a96: 681b ldr r3, [r3, #0]
8002a98: 4a3a ldr r2, [pc, #232] @ (8002b84 <HAL_ADC_ConfigChannel+0x7c8>)
8002a9a: 4293 cmp r3, r2
8002a9c: d127 bne.n 8002aee <HAL_ADC_ConfigChannel+0x732>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8002a9e: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002aa2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002aa6: 2b00 cmp r3, #0
8002aa8: d121 bne.n 8002aee <HAL_ADC_ConfigChannel+0x732>
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002aaa: 687b ldr r3, [r7, #4]
8002aac: 681b ldr r3, [r3, #0]
8002aae: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002ab2: d157 bne.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002ab4: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002ab8: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8002abc: 4619 mov r1, r3
8002abe: 482f ldr r0, [pc, #188] @ (8002b7c <HAL_ADC_ConfigChannel+0x7c0>)
8002ac0: f7fe febb bl 800183a <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002ac4: 4b30 ldr r3, [pc, #192] @ (8002b88 <HAL_ADC_ConfigChannel+0x7cc>)
8002ac6: 681b ldr r3, [r3, #0]
8002ac8: 099b lsrs r3, r3, #6
8002aca: 4a30 ldr r2, [pc, #192] @ (8002b8c <HAL_ADC_ConfigChannel+0x7d0>)
8002acc: fba2 2303 umull r2, r3, r2, r3
8002ad0: 099b lsrs r3, r3, #6
8002ad2: 1c5a adds r2, r3, #1
8002ad4: 4613 mov r3, r2
8002ad6: 005b lsls r3, r3, #1
8002ad8: 4413 add r3, r2
8002ada: 009b lsls r3, r3, #2
8002adc: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002ade: e002 b.n 8002ae6 <HAL_ADC_ConfigChannel+0x72a>
{
wait_loop_index--;
8002ae0: 68fb ldr r3, [r7, #12]
8002ae2: 3b01 subs r3, #1
8002ae4: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002ae6: 68fb ldr r3, [r7, #12]
8002ae8: 2b00 cmp r3, #0
8002aea: d1f9 bne.n 8002ae0 <HAL_ADC_ConfigChannel+0x724>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002aec: e03a b.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
}
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
8002aee: 683b ldr r3, [r7, #0]
8002af0: 681b ldr r3, [r3, #0]
8002af2: 4a27 ldr r2, [pc, #156] @ (8002b90 <HAL_ADC_ConfigChannel+0x7d4>)
8002af4: 4293 cmp r3, r2
8002af6: d113 bne.n 8002b20 <HAL_ADC_ConfigChannel+0x764>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8002af8: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002afc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8002b00: 2b00 cmp r3, #0
8002b02: d10d bne.n 8002b20 <HAL_ADC_ConfigChannel+0x764>
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002b04: 687b ldr r3, [r7, #4]
8002b06: 681b ldr r3, [r3, #0]
8002b08: 4a22 ldr r2, [pc, #136] @ (8002b94 <HAL_ADC_ConfigChannel+0x7d8>)
8002b0a: 4293 cmp r3, r2
8002b0c: d02a beq.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002b0e: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002b12: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002b16: 4619 mov r1, r3
8002b18: 4818 ldr r0, [pc, #96] @ (8002b7c <HAL_ADC_ConfigChannel+0x7c0>)
8002b1a: f7fe fe8e bl 800183a <LL_ADC_SetCommonPathInternalCh>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002b1e: e021 b.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
8002b20: 683b ldr r3, [r7, #0]
8002b22: 681b ldr r3, [r3, #0]
8002b24: 4a1c ldr r2, [pc, #112] @ (8002b98 <HAL_ADC_ConfigChannel+0x7dc>)
8002b26: 4293 cmp r3, r2
8002b28: d11c bne.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8002b2a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002b2e: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8002b32: 2b00 cmp r3, #0
8002b34: d116 bne.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
{
if (ADC_VREFINT_INSTANCE(hadc))
8002b36: 687b ldr r3, [r7, #4]
8002b38: 681b ldr r3, [r3, #0]
8002b3a: 4a16 ldr r2, [pc, #88] @ (8002b94 <HAL_ADC_ConfigChannel+0x7d8>)
8002b3c: 4293 cmp r3, r2
8002b3e: d011 beq.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002b40: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002b44: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002b48: 4619 mov r1, r3
8002b4a: 480c ldr r0, [pc, #48] @ (8002b7c <HAL_ADC_ConfigChannel+0x7c0>)
8002b4c: f7fe fe75 bl 800183a <LL_ADC_SetCommonPathInternalCh>
8002b50: e008 b.n 8002b64 <HAL_ADC_ConfigChannel+0x7a8>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002b52: 687b ldr r3, [r7, #4]
8002b54: 6ddb ldr r3, [r3, #92] @ 0x5c
8002b56: f043 0220 orr.w r2, r3, #32
8002b5a: 687b ldr r3, [r7, #4]
8002b5c: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8002b5e: 2301 movs r3, #1
8002b60: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002b64: 687b ldr r3, [r7, #4]
8002b66: 2200 movs r2, #0
8002b68: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
8002b6c: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7
}
8002b70: 4618 mov r0, r3
8002b72: 37d8 adds r7, #216 @ 0xd8
8002b74: 46bd mov sp, r7
8002b76: bd80 pop {r7, pc}
8002b78: 80080000 .word 0x80080000
8002b7c: 50000300 .word 0x50000300
8002b80: c3210000 .word 0xc3210000
8002b84: 90c00010 .word 0x90c00010
8002b88: 2000001c .word 0x2000001c
8002b8c: 053e2d63 .word 0x053e2d63
8002b90: c7520000 .word 0xc7520000
8002b94: 50000100 .word 0x50000100
8002b98: cb840000 .word 0xcb840000
08002b9c <ADC_ConversionStop>:
* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
8002b9c: b580 push {r7, lr}
8002b9e: b088 sub sp, #32
8002ba0: af00 add r7, sp, #0
8002ba2: 6078 str r0, [r7, #4]
8002ba4: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
8002ba6: 2300 movs r3, #0
8002ba8: 61fb str r3, [r7, #28]
uint32_t conversion_group_reassigned = ConversionGroup;
8002baa: 683b ldr r3, [r7, #0]
8002bac: 61bb str r3, [r7, #24]
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
/* Verification if ADC is not already stopped (on regular and injected */
/* groups) to bypass this function if not needed. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8002bae: 687b ldr r3, [r7, #4]
8002bb0: 681b ldr r3, [r3, #0]
8002bb2: 4618 mov r0, r3
8002bb4: f7ff f86e bl 8001c94 <LL_ADC_REG_IsConversionOngoing>
8002bb8: 6138 str r0, [r7, #16]
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002bba: 687b ldr r3, [r7, #4]
8002bbc: 681b ldr r3, [r3, #0]
8002bbe: 4618 mov r0, r3
8002bc0: f7ff f88f bl 8001ce2 <LL_ADC_INJ_IsConversionOngoing>
8002bc4: 60f8 str r0, [r7, #12]
if ((tmp_adc_is_conversion_on_going_regular != 0UL)
8002bc6: 693b ldr r3, [r7, #16]
8002bc8: 2b00 cmp r3, #0
8002bca: d103 bne.n 8002bd4 <ADC_ConversionStop+0x38>
|| (tmp_adc_is_conversion_on_going_injected != 0UL)
8002bcc: 68fb ldr r3, [r7, #12]
8002bce: 2b00 cmp r3, #0
8002bd0: f000 8098 beq.w 8002d04 <ADC_ConversionStop+0x168>
/* auto-delay mode. */
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
/* injected group stop ADC_CR_JADSTP). */
/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
/* (see reference manual). */
if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
8002bd4: 687b ldr r3, [r7, #4]
8002bd6: 681b ldr r3, [r3, #0]
8002bd8: 68db ldr r3, [r3, #12]
8002bda: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8002bde: 2b00 cmp r3, #0
8002be0: d02a beq.n 8002c38 <ADC_ConversionStop+0x9c>
&& (hadc->Init.ContinuousConvMode == ENABLE)
8002be2: 687b ldr r3, [r7, #4]
8002be4: 7f5b ldrb r3, [r3, #29]
8002be6: 2b01 cmp r3, #1
8002be8: d126 bne.n 8002c38 <ADC_ConversionStop+0x9c>
&& (hadc->Init.LowPowerAutoWait == ENABLE)
8002bea: 687b ldr r3, [r7, #4]
8002bec: 7f1b ldrb r3, [r3, #28]
8002bee: 2b01 cmp r3, #1
8002bf0: d122 bne.n 8002c38 <ADC_ConversionStop+0x9c>
)
{
/* Use stop of regular group */
conversion_group_reassigned = ADC_REGULAR_GROUP;
8002bf2: 2301 movs r3, #1
8002bf4: 61bb str r3, [r7, #24]
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
8002bf6: e014 b.n 8002c22 <ADC_ConversionStop+0x86>
{
if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
8002bf8: 69fb ldr r3, [r7, #28]
8002bfa: 4a45 ldr r2, [pc, #276] @ (8002d10 <ADC_ConversionStop+0x174>)
8002bfc: 4293 cmp r3, r2
8002bfe: d90d bls.n 8002c1c <ADC_ConversionStop+0x80>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002c00: 687b ldr r3, [r7, #4]
8002c02: 6ddb ldr r3, [r3, #92] @ 0x5c
8002c04: f043 0210 orr.w r2, r3, #16
8002c08: 687b ldr r3, [r7, #4]
8002c0a: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002c0c: 687b ldr r3, [r7, #4]
8002c0e: 6e1b ldr r3, [r3, #96] @ 0x60
8002c10: f043 0201 orr.w r2, r3, #1
8002c14: 687b ldr r3, [r7, #4]
8002c16: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002c18: 2301 movs r3, #1
8002c1a: e074 b.n 8002d06 <ADC_ConversionStop+0x16a>
}
Conversion_Timeout_CPU_cycles ++;
8002c1c: 69fb ldr r3, [r7, #28]
8002c1e: 3301 adds r3, #1
8002c20: 61fb str r3, [r7, #28]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
8002c22: 687b ldr r3, [r7, #4]
8002c24: 681b ldr r3, [r3, #0]
8002c26: 681b ldr r3, [r3, #0]
8002c28: f003 0340 and.w r3, r3, #64 @ 0x40
8002c2c: 2b40 cmp r3, #64 @ 0x40
8002c2e: d1e3 bne.n 8002bf8 <ADC_ConversionStop+0x5c>
}
/* Clear JEOS */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
8002c30: 687b ldr r3, [r7, #4]
8002c32: 681b ldr r3, [r3, #0]
8002c34: 2240 movs r2, #64 @ 0x40
8002c36: 601a str r2, [r3, #0]
}
/* Stop potential conversion on going on ADC group regular */
if (conversion_group_reassigned != ADC_INJECTED_GROUP)
8002c38: 69bb ldr r3, [r7, #24]
8002c3a: 2b02 cmp r3, #2
8002c3c: d014 beq.n 8002c68 <ADC_ConversionStop+0xcc>
{
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
8002c3e: 687b ldr r3, [r7, #4]
8002c40: 681b ldr r3, [r3, #0]
8002c42: 4618 mov r0, r3
8002c44: f7ff f826 bl 8001c94 <LL_ADC_REG_IsConversionOngoing>
8002c48: 4603 mov r3, r0
8002c4a: 2b00 cmp r3, #0
8002c4c: d00c beq.n 8002c68 <ADC_ConversionStop+0xcc>
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
8002c4e: 687b ldr r3, [r7, #4]
8002c50: 681b ldr r3, [r3, #0]
8002c52: 4618 mov r0, r3
8002c54: f7fe ffe3 bl 8001c1e <LL_ADC_IsDisableOngoing>
8002c58: 4603 mov r3, r0
8002c5a: 2b00 cmp r3, #0
8002c5c: d104 bne.n 8002c68 <ADC_ConversionStop+0xcc>
{
/* Stop ADC group regular conversion */
LL_ADC_REG_StopConversion(hadc->Instance);
8002c5e: 687b ldr r3, [r7, #4]
8002c60: 681b ldr r3, [r3, #0]
8002c62: 4618 mov r0, r3
8002c64: f7ff f802 bl 8001c6c <LL_ADC_REG_StopConversion>
}
}
}
/* Stop potential conversion on going on ADC group injected */
if (conversion_group_reassigned != ADC_REGULAR_GROUP)
8002c68: 69bb ldr r3, [r7, #24]
8002c6a: 2b01 cmp r3, #1
8002c6c: d014 beq.n 8002c98 <ADC_ConversionStop+0xfc>
{
/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
8002c6e: 687b ldr r3, [r7, #4]
8002c70: 681b ldr r3, [r3, #0]
8002c72: 4618 mov r0, r3
8002c74: f7ff f835 bl 8001ce2 <LL_ADC_INJ_IsConversionOngoing>
8002c78: 4603 mov r3, r0
8002c7a: 2b00 cmp r3, #0
8002c7c: d00c beq.n 8002c98 <ADC_ConversionStop+0xfc>
{
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
8002c7e: 687b ldr r3, [r7, #4]
8002c80: 681b ldr r3, [r3, #0]
8002c82: 4618 mov r0, r3
8002c84: f7fe ffcb bl 8001c1e <LL_ADC_IsDisableOngoing>
8002c88: 4603 mov r3, r0
8002c8a: 2b00 cmp r3, #0
8002c8c: d104 bne.n 8002c98 <ADC_ConversionStop+0xfc>
{
/* Stop ADC group injected conversion */
LL_ADC_INJ_StopConversion(hadc->Instance);
8002c8e: 687b ldr r3, [r7, #4]
8002c90: 681b ldr r3, [r3, #0]
8002c92: 4618 mov r0, r3
8002c94: f7ff f811 bl 8001cba <LL_ADC_INJ_StopConversion>
}
}
}
/* Selection of start and stop bits with respect to the regular or injected group */
switch (conversion_group_reassigned)
8002c98: 69bb ldr r3, [r7, #24]
8002c9a: 2b02 cmp r3, #2
8002c9c: d005 beq.n 8002caa <ADC_ConversionStop+0x10e>
8002c9e: 69bb ldr r3, [r7, #24]
8002ca0: 2b03 cmp r3, #3
8002ca2: d105 bne.n 8002cb0 <ADC_ConversionStop+0x114>
{
case ADC_REGULAR_INJECTED_GROUP:
tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
8002ca4: 230c movs r3, #12
8002ca6: 617b str r3, [r7, #20]
break;
8002ca8: e005 b.n 8002cb6 <ADC_ConversionStop+0x11a>
case ADC_INJECTED_GROUP:
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
8002caa: 2308 movs r3, #8
8002cac: 617b str r3, [r7, #20]
break;
8002cae: e002 b.n 8002cb6 <ADC_ConversionStop+0x11a>
/* Case ADC_REGULAR_GROUP only*/
default:
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
8002cb0: 2304 movs r3, #4
8002cb2: 617b str r3, [r7, #20]
break;
8002cb4: bf00 nop
}
/* Wait for conversion effectively stopped */
tickstart = HAL_GetTick();
8002cb6: f7fe fda1 bl 80017fc <HAL_GetTick>
8002cba: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8002cbc: e01b b.n 8002cf6 <ADC_ConversionStop+0x15a>
{
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
8002cbe: f7fe fd9d bl 80017fc <HAL_GetTick>
8002cc2: 4602 mov r2, r0
8002cc4: 68bb ldr r3, [r7, #8]
8002cc6: 1ad3 subs r3, r2, r3
8002cc8: 2b05 cmp r3, #5
8002cca: d914 bls.n 8002cf6 <ADC_ConversionStop+0x15a>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8002ccc: 687b ldr r3, [r7, #4]
8002cce: 681b ldr r3, [r3, #0]
8002cd0: 689a ldr r2, [r3, #8]
8002cd2: 697b ldr r3, [r7, #20]
8002cd4: 4013 ands r3, r2
8002cd6: 2b00 cmp r3, #0
8002cd8: d00d beq.n 8002cf6 <ADC_ConversionStop+0x15a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002cda: 687b ldr r3, [r7, #4]
8002cdc: 6ddb ldr r3, [r3, #92] @ 0x5c
8002cde: f043 0210 orr.w r2, r3, #16
8002ce2: 687b ldr r3, [r7, #4]
8002ce4: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: 6e1b ldr r3, [r3, #96] @ 0x60
8002cea: f043 0201 orr.w r2, r3, #1
8002cee: 687b ldr r3, [r7, #4]
8002cf0: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002cf2: 2301 movs r3, #1
8002cf4: e007 b.n 8002d06 <ADC_ConversionStop+0x16a>
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
8002cf6: 687b ldr r3, [r7, #4]
8002cf8: 681b ldr r3, [r3, #0]
8002cfa: 689a ldr r2, [r3, #8]
8002cfc: 697b ldr r3, [r7, #20]
8002cfe: 4013 ands r3, r2
8002d00: 2b00 cmp r3, #0
8002d02: d1dc bne.n 8002cbe <ADC_ConversionStop+0x122>
}
}
/* Return HAL status */
return HAL_OK;
8002d04: 2300 movs r3, #0
}
8002d06: 4618 mov r0, r3
8002d08: 3720 adds r7, #32
8002d0a: 46bd mov sp, r7
8002d0c: bd80 pop {r7, pc}
8002d0e: bf00 nop
8002d10: a33fffff .word 0xa33fffff
08002d14 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
8002d14: b580 push {r7, lr}
8002d16: b084 sub sp, #16
8002d18: af00 add r7, sp, #0
8002d1a: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
8002d1c: 2300 movs r3, #0
8002d1e: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002d20: 687b ldr r3, [r7, #4]
8002d22: 681b ldr r3, [r3, #0]
8002d24: 4618 mov r0, r3
8002d26: f7fe ff67 bl 8001bf8 <LL_ADC_IsEnabled>
8002d2a: 4603 mov r3, r0
8002d2c: 2b00 cmp r3, #0
8002d2e: d169 bne.n 8002e04 <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
8002d30: 687b ldr r3, [r7, #4]
8002d32: 681b ldr r3, [r3, #0]
8002d34: 689a ldr r2, [r3, #8]
8002d36: 4b36 ldr r3, [pc, #216] @ (8002e10 <ADC_Enable+0xfc>)
8002d38: 4013 ands r3, r2
8002d3a: 2b00 cmp r3, #0
8002d3c: d00d beq.n 8002d5a <ADC_Enable+0x46>
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002d3e: 687b ldr r3, [r7, #4]
8002d40: 6ddb ldr r3, [r3, #92] @ 0x5c
8002d42: f043 0210 orr.w r2, r3, #16
8002d46: 687b ldr r3, [r7, #4]
8002d48: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002d4a: 687b ldr r3, [r7, #4]
8002d4c: 6e1b ldr r3, [r3, #96] @ 0x60
8002d4e: f043 0201 orr.w r2, r3, #1
8002d52: 687b ldr r3, [r7, #4]
8002d54: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002d56: 2301 movs r3, #1
8002d58: e055 b.n 8002e06 <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
8002d5a: 687b ldr r3, [r7, #4]
8002d5c: 681b ldr r3, [r3, #0]
8002d5e: 4618 mov r0, r3
8002d60: f7fe ff22 bl 8001ba8 <LL_ADC_Enable>
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
8002d64: 482b ldr r0, [pc, #172] @ (8002e14 <ADC_Enable+0x100>)
8002d66: f7fe fd7b bl 8001860 <LL_ADC_GetCommonPathInternalCh>
8002d6a: 4603 mov r3, r0
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
8002d6c: f403 0300 and.w r3, r3, #8388608 @ 0x800000
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
8002d70: 2b00 cmp r3, #0
8002d72: d013 beq.n 8002d9c <ADC_Enable+0x88>
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002d74: 4b28 ldr r3, [pc, #160] @ (8002e18 <ADC_Enable+0x104>)
8002d76: 681b ldr r3, [r3, #0]
8002d78: 099b lsrs r3, r3, #6
8002d7a: 4a28 ldr r2, [pc, #160] @ (8002e1c <ADC_Enable+0x108>)
8002d7c: fba2 2303 umull r2, r3, r2, r3
8002d80: 099b lsrs r3, r3, #6
8002d82: 1c5a adds r2, r3, #1
8002d84: 4613 mov r3, r2
8002d86: 005b lsls r3, r3, #1
8002d88: 4413 add r3, r2
8002d8a: 009b lsls r3, r3, #2
8002d8c: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002d8e: e002 b.n 8002d96 <ADC_Enable+0x82>
{
wait_loop_index--;
8002d90: 68bb ldr r3, [r7, #8]
8002d92: 3b01 subs r3, #1
8002d94: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002d96: 68bb ldr r3, [r7, #8]
8002d98: 2b00 cmp r3, #0
8002d9a: d1f9 bne.n 8002d90 <ADC_Enable+0x7c>
}
}
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
8002d9c: f7fe fd2e bl 80017fc <HAL_GetTick>
8002da0: 60f8 str r0, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002da2: e028 b.n 8002df6 <ADC_Enable+0xe2>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002da4: 687b ldr r3, [r7, #4]
8002da6: 681b ldr r3, [r3, #0]
8002da8: 4618 mov r0, r3
8002daa: f7fe ff25 bl 8001bf8 <LL_ADC_IsEnabled>
8002dae: 4603 mov r3, r0
8002db0: 2b00 cmp r3, #0
8002db2: d104 bne.n 8002dbe <ADC_Enable+0xaa>
{
LL_ADC_Enable(hadc->Instance);
8002db4: 687b ldr r3, [r7, #4]
8002db6: 681b ldr r3, [r3, #0]
8002db8: 4618 mov r0, r3
8002dba: f7fe fef5 bl 8001ba8 <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8002dbe: f7fe fd1d bl 80017fc <HAL_GetTick>
8002dc2: 4602 mov r2, r0
8002dc4: 68fb ldr r3, [r7, #12]
8002dc6: 1ad3 subs r3, r2, r3
8002dc8: 2b02 cmp r3, #2
8002dca: d914 bls.n 8002df6 <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002dcc: 687b ldr r3, [r7, #4]
8002dce: 681b ldr r3, [r3, #0]
8002dd0: 681b ldr r3, [r3, #0]
8002dd2: f003 0301 and.w r3, r3, #1
8002dd6: 2b01 cmp r3, #1
8002dd8: d00d beq.n 8002df6 <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002dda: 687b ldr r3, [r7, #4]
8002ddc: 6ddb ldr r3, [r3, #92] @ 0x5c
8002dde: f043 0210 orr.w r2, r3, #16
8002de2: 687b ldr r3, [r7, #4]
8002de4: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002de6: 687b ldr r3, [r7, #4]
8002de8: 6e1b ldr r3, [r3, #96] @ 0x60
8002dea: f043 0201 orr.w r2, r3, #1
8002dee: 687b ldr r3, [r7, #4]
8002df0: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002df2: 2301 movs r3, #1
8002df4: e007 b.n 8002e06 <ADC_Enable+0xf2>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002df6: 687b ldr r3, [r7, #4]
8002df8: 681b ldr r3, [r3, #0]
8002dfa: 681b ldr r3, [r3, #0]
8002dfc: f003 0301 and.w r3, r3, #1
8002e00: 2b01 cmp r3, #1
8002e02: d1cf bne.n 8002da4 <ADC_Enable+0x90>
}
}
}
/* Return HAL status */
return HAL_OK;
8002e04: 2300 movs r3, #0
}
8002e06: 4618 mov r0, r3
8002e08: 3710 adds r7, #16
8002e0a: 46bd mov sp, r7
8002e0c: bd80 pop {r7, pc}
8002e0e: bf00 nop
8002e10: 8000003f .word 0x8000003f
8002e14: 50000300 .word 0x50000300
8002e18: 2000001c .word 0x2000001c
8002e1c: 053e2d63 .word 0x053e2d63
08002e20 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
8002e20: b580 push {r7, lr}
8002e22: b084 sub sp, #16
8002e24: af00 add r7, sp, #0
8002e26: 6078 str r0, [r7, #4]
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
8002e28: 687b ldr r3, [r7, #4]
8002e2a: 681b ldr r3, [r3, #0]
8002e2c: 4618 mov r0, r3
8002e2e: f7fe fef6 bl 8001c1e <LL_ADC_IsDisableOngoing>
8002e32: 60f8 str r0, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002e34: 687b ldr r3, [r7, #4]
8002e36: 681b ldr r3, [r3, #0]
8002e38: 4618 mov r0, r3
8002e3a: f7fe fedd bl 8001bf8 <LL_ADC_IsEnabled>
8002e3e: 4603 mov r3, r0
8002e40: 2b00 cmp r3, #0
8002e42: d047 beq.n 8002ed4 <ADC_Disable+0xb4>
&& (tmp_adc_is_disable_on_going == 0UL)
8002e44: 68fb ldr r3, [r7, #12]
8002e46: 2b00 cmp r3, #0
8002e48: d144 bne.n 8002ed4 <ADC_Disable+0xb4>
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
8002e4a: 687b ldr r3, [r7, #4]
8002e4c: 681b ldr r3, [r3, #0]
8002e4e: 689b ldr r3, [r3, #8]
8002e50: f003 030d and.w r3, r3, #13
8002e54: 2b01 cmp r3, #1
8002e56: d10c bne.n 8002e72 <ADC_Disable+0x52>
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
8002e58: 687b ldr r3, [r7, #4]
8002e5a: 681b ldr r3, [r3, #0]
8002e5c: 4618 mov r0, r3
8002e5e: f7fe feb7 bl 8001bd0 <LL_ADC_Disable>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
8002e62: 687b ldr r3, [r7, #4]
8002e64: 681b ldr r3, [r3, #0]
8002e66: 2203 movs r2, #3
8002e68: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
8002e6a: f7fe fcc7 bl 80017fc <HAL_GetTick>
8002e6e: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002e70: e029 b.n 8002ec6 <ADC_Disable+0xa6>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002e72: 687b ldr r3, [r7, #4]
8002e74: 6ddb ldr r3, [r3, #92] @ 0x5c
8002e76: f043 0210 orr.w r2, r3, #16
8002e7a: 687b ldr r3, [r7, #4]
8002e7c: 65da str r2, [r3, #92] @ 0x5c
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002e7e: 687b ldr r3, [r7, #4]
8002e80: 6e1b ldr r3, [r3, #96] @ 0x60
8002e82: f043 0201 orr.w r2, r3, #1
8002e86: 687b ldr r3, [r7, #4]
8002e88: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002e8a: 2301 movs r3, #1
8002e8c: e023 b.n 8002ed6 <ADC_Disable+0xb6>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002e8e: f7fe fcb5 bl 80017fc <HAL_GetTick>
8002e92: 4602 mov r2, r0
8002e94: 68bb ldr r3, [r7, #8]
8002e96: 1ad3 subs r3, r2, r3
8002e98: 2b02 cmp r3, #2
8002e9a: d914 bls.n 8002ec6 <ADC_Disable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002e9c: 687b ldr r3, [r7, #4]
8002e9e: 681b ldr r3, [r3, #0]
8002ea0: 689b ldr r3, [r3, #8]
8002ea2: f003 0301 and.w r3, r3, #1
8002ea6: 2b00 cmp r3, #0
8002ea8: d00d beq.n 8002ec6 <ADC_Disable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002eaa: 687b ldr r3, [r7, #4]
8002eac: 6ddb ldr r3, [r3, #92] @ 0x5c
8002eae: f043 0210 orr.w r2, r3, #16
8002eb2: 687b ldr r3, [r7, #4]
8002eb4: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002eb6: 687b ldr r3, [r7, #4]
8002eb8: 6e1b ldr r3, [r3, #96] @ 0x60
8002eba: f043 0201 orr.w r2, r3, #1
8002ebe: 687b ldr r3, [r7, #4]
8002ec0: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002ec2: 2301 movs r3, #1
8002ec4: e007 b.n 8002ed6 <ADC_Disable+0xb6>
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002ec6: 687b ldr r3, [r7, #4]
8002ec8: 681b ldr r3, [r3, #0]
8002eca: 689b ldr r3, [r3, #8]
8002ecc: f003 0301 and.w r3, r3, #1
8002ed0: 2b00 cmp r3, #0
8002ed2: d1dc bne.n 8002e8e <ADC_Disable+0x6e>
}
}
}
/* Return HAL status */
return HAL_OK;
8002ed4: 2300 movs r3, #0
}
8002ed6: 4618 mov r0, r3
8002ed8: 3710 adds r7, #16
8002eda: 46bd mov sp, r7
8002edc: bd80 pop {r7, pc}
08002ede <LL_ADC_IsEnabled>:
{
8002ede: b480 push {r7}
8002ee0: b083 sub sp, #12
8002ee2: af00 add r7, sp, #0
8002ee4: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002ee6: 687b ldr r3, [r7, #4]
8002ee8: 689b ldr r3, [r3, #8]
8002eea: f003 0301 and.w r3, r3, #1
8002eee: 2b01 cmp r3, #1
8002ef0: d101 bne.n 8002ef6 <LL_ADC_IsEnabled+0x18>
8002ef2: 2301 movs r3, #1
8002ef4: e000 b.n 8002ef8 <LL_ADC_IsEnabled+0x1a>
8002ef6: 2300 movs r3, #0
}
8002ef8: 4618 mov r0, r3
8002efa: 370c adds r7, #12
8002efc: 46bd mov sp, r7
8002efe: f85d 7b04 ldr.w r7, [sp], #4
8002f02: 4770 bx lr
08002f04 <LL_ADC_StartCalibration>:
{
8002f04: b480 push {r7}
8002f06: b083 sub sp, #12
8002f08: af00 add r7, sp, #0
8002f0a: 6078 str r0, [r7, #4]
8002f0c: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->CR,
8002f0e: 687b ldr r3, [r7, #4]
8002f10: 689b ldr r3, [r3, #8]
8002f12: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000
8002f16: f023 033f bic.w r3, r3, #63 @ 0x3f
8002f1a: 683a ldr r2, [r7, #0]
8002f1c: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
8002f20: 4313 orrs r3, r2
8002f22: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
8002f26: 687b ldr r3, [r7, #4]
8002f28: 609a str r2, [r3, #8]
}
8002f2a: bf00 nop
8002f2c: 370c adds r7, #12
8002f2e: 46bd mov sp, r7
8002f30: f85d 7b04 ldr.w r7, [sp], #4
8002f34: 4770 bx lr
08002f36 <LL_ADC_IsCalibrationOnGoing>:
{
8002f36: b480 push {r7}
8002f38: b083 sub sp, #12
8002f3a: af00 add r7, sp, #0
8002f3c: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
8002f3e: 687b ldr r3, [r7, #4]
8002f40: 689b ldr r3, [r3, #8]
8002f42: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8002f46: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8002f4a: d101 bne.n 8002f50 <LL_ADC_IsCalibrationOnGoing+0x1a>
8002f4c: 2301 movs r3, #1
8002f4e: e000 b.n 8002f52 <LL_ADC_IsCalibrationOnGoing+0x1c>
8002f50: 2300 movs r3, #0
}
8002f52: 4618 mov r0, r3
8002f54: 370c adds r7, #12
8002f56: 46bd mov sp, r7
8002f58: f85d 7b04 ldr.w r7, [sp], #4
8002f5c: 4770 bx lr
08002f5e <LL_ADC_REG_IsConversionOngoing>:
{
8002f5e: b480 push {r7}
8002f60: b083 sub sp, #12
8002f62: af00 add r7, sp, #0
8002f64: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002f66: 687b ldr r3, [r7, #4]
8002f68: 689b ldr r3, [r3, #8]
8002f6a: f003 0304 and.w r3, r3, #4
8002f6e: 2b04 cmp r3, #4
8002f70: d101 bne.n 8002f76 <LL_ADC_REG_IsConversionOngoing+0x18>
8002f72: 2301 movs r3, #1
8002f74: e000 b.n 8002f78 <LL_ADC_REG_IsConversionOngoing+0x1a>
8002f76: 2300 movs r3, #0
}
8002f78: 4618 mov r0, r3
8002f7a: 370c adds r7, #12
8002f7c: 46bd mov sp, r7
8002f7e: f85d 7b04 ldr.w r7, [sp], #4
8002f82: 4770 bx lr
08002f84 <HAL_ADCEx_Calibration_Start>:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
8002f84: b580 push {r7, lr}
8002f86: b084 sub sp, #16
8002f88: af00 add r7, sp, #0
8002f8a: 6078 str r0, [r7, #4]
8002f8c: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
8002f8e: 2300 movs r3, #0
8002f90: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Process locked */
__HAL_LOCK(hadc);
8002f92: 687b ldr r3, [r7, #4]
8002f94: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8002f98: 2b01 cmp r3, #1
8002f9a: d101 bne.n 8002fa0 <HAL_ADCEx_Calibration_Start+0x1c>
8002f9c: 2302 movs r3, #2
8002f9e: e04d b.n 800303c <HAL_ADCEx_Calibration_Start+0xb8>
8002fa0: 687b ldr r3, [r7, #4]
8002fa2: 2201 movs r2, #1
8002fa4: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
8002fa8: 6878 ldr r0, [r7, #4]
8002faa: f7ff ff39 bl 8002e20 <ADC_Disable>
8002fae: 4603 mov r3, r0
8002fb0: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
8002fb2: 7bfb ldrb r3, [r7, #15]
8002fb4: 2b00 cmp r3, #0
8002fb6: d136 bne.n 8003026 <HAL_ADCEx_Calibration_Start+0xa2>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002fb8: 687b ldr r3, [r7, #4]
8002fba: 6ddb ldr r3, [r3, #92] @ 0x5c
8002fbc: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8002fc0: f023 0302 bic.w r3, r3, #2
8002fc4: f043 0202 orr.w r2, r3, #2
8002fc8: 687b ldr r3, [r7, #4]
8002fca: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
8002fcc: 687b ldr r3, [r7, #4]
8002fce: 681b ldr r3, [r3, #0]
8002fd0: 6839 ldr r1, [r7, #0]
8002fd2: 4618 mov r0, r3
8002fd4: f7ff ff96 bl 8002f04 <LL_ADC_StartCalibration>
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8002fd8: e014 b.n 8003004 <HAL_ADCEx_Calibration_Start+0x80>
{
wait_loop_index++;
8002fda: 68bb ldr r3, [r7, #8]
8002fdc: 3301 adds r3, #1
8002fde: 60bb str r3, [r7, #8]
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
8002fe0: 68bb ldr r3, [r7, #8]
8002fe2: 4a18 ldr r2, [pc, #96] @ (8003044 <HAL_ADCEx_Calibration_Start+0xc0>)
8002fe4: 4293 cmp r3, r2
8002fe6: d90d bls.n 8003004 <HAL_ADCEx_Calibration_Start+0x80>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8002fe8: 687b ldr r3, [r7, #4]
8002fea: 6ddb ldr r3, [r3, #92] @ 0x5c
8002fec: f023 0312 bic.w r3, r3, #18
8002ff0: f043 0210 orr.w r2, r3, #16
8002ff4: 687b ldr r3, [r7, #4]
8002ff6: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002ff8: 687b ldr r3, [r7, #4]
8002ffa: 2200 movs r2, #0
8002ffc: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
8003000: 2301 movs r3, #1
8003002: e01b b.n 800303c <HAL_ADCEx_Calibration_Start+0xb8>
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8003004: 687b ldr r3, [r7, #4]
8003006: 681b ldr r3, [r3, #0]
8003008: 4618 mov r0, r3
800300a: f7ff ff94 bl 8002f36 <LL_ADC_IsCalibrationOnGoing>
800300e: 4603 mov r3, r0
8003010: 2b00 cmp r3, #0
8003012: d1e2 bne.n 8002fda <HAL_ADCEx_Calibration_Start+0x56>
}
}
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8003014: 687b ldr r3, [r7, #4]
8003016: 6ddb ldr r3, [r3, #92] @ 0x5c
8003018: f023 0303 bic.w r3, r3, #3
800301c: f043 0201 orr.w r2, r3, #1
8003020: 687b ldr r3, [r7, #4]
8003022: 65da str r2, [r3, #92] @ 0x5c
8003024: e005 b.n 8003032 <HAL_ADCEx_Calibration_Start+0xae>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8003026: 687b ldr r3, [r7, #4]
8003028: 6ddb ldr r3, [r3, #92] @ 0x5c
800302a: f043 0210 orr.w r2, r3, #16
800302e: 687b ldr r3, [r7, #4]
8003030: 65da str r2, [r3, #92] @ 0x5c
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003032: 687b ldr r3, [r7, #4]
8003034: 2200 movs r2, #0
8003036: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
800303a: 7bfb ldrb r3, [r7, #15]
}
800303c: 4618 mov r0, r3
800303e: 3710 adds r7, #16
8003040: 46bd mov sp, r7
8003042: bd80 pop {r7, pc}
8003044: 0004de01 .word 0x0004de01
08003048 <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc Master ADC handle
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
8003048: b590 push {r4, r7, lr}
800304a: b0a1 sub sp, #132 @ 0x84
800304c: af00 add r7, sp, #0
800304e: 6078 str r0, [r7, #4]
8003050: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8003052: 2300 movs r3, #0
8003054: f887 307f strb.w r3, [r7, #127] @ 0x7f
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
8003058: 687b ldr r3, [r7, #4]
800305a: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
800305e: 2b01 cmp r3, #1
8003060: d101 bne.n 8003066 <HAL_ADCEx_MultiModeConfigChannel+0x1e>
8003062: 2302 movs r3, #2
8003064: e08b b.n 800317e <HAL_ADCEx_MultiModeConfigChannel+0x136>
8003066: 687b ldr r3, [r7, #4]
8003068: 2201 movs r2, #1
800306a: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
800306e: 2300 movs r3, #0
8003070: 667b str r3, [r7, #100] @ 0x64
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
8003072: 2300 movs r3, #0
8003074: 66bb str r3, [r7, #104] @ 0x68
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
8003076: 687b ldr r3, [r7, #4]
8003078: 681b ldr r3, [r3, #0]
800307a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800307e: d102 bne.n 8003086 <HAL_ADCEx_MultiModeConfigChannel+0x3e>
8003080: 4b41 ldr r3, [pc, #260] @ (8003188 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
8003082: 60bb str r3, [r7, #8]
8003084: e001 b.n 800308a <HAL_ADCEx_MultiModeConfigChannel+0x42>
8003086: 2300 movs r3, #0
8003088: 60bb str r3, [r7, #8]
if (tmp_hadc_slave.Instance == NULL)
800308a: 68bb ldr r3, [r7, #8]
800308c: 2b00 cmp r3, #0
800308e: d10b bne.n 80030a8 <HAL_ADCEx_MultiModeConfigChannel+0x60>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003090: 687b ldr r3, [r7, #4]
8003092: 6ddb ldr r3, [r3, #92] @ 0x5c
8003094: f043 0220 orr.w r2, r3, #32
8003098: 687b ldr r3, [r7, #4]
800309a: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
800309c: 687b ldr r3, [r7, #4]
800309e: 2200 movs r2, #0
80030a0: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
80030a4: 2301 movs r3, #1
80030a6: e06a b.n 800317e <HAL_ADCEx_MultiModeConfigChannel+0x136>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
80030a8: 68bb ldr r3, [r7, #8]
80030aa: 4618 mov r0, r3
80030ac: f7ff ff57 bl 8002f5e <LL_ADC_REG_IsConversionOngoing>
80030b0: 67b8 str r0, [r7, #120] @ 0x78
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80030b2: 687b ldr r3, [r7, #4]
80030b4: 681b ldr r3, [r3, #0]
80030b6: 4618 mov r0, r3
80030b8: f7ff ff51 bl 8002f5e <LL_ADC_REG_IsConversionOngoing>
80030bc: 4603 mov r3, r0
80030be: 2b00 cmp r3, #0
80030c0: d14c bne.n 800315c <HAL_ADCEx_MultiModeConfigChannel+0x114>
&& (tmp_hadc_slave_conversion_on_going == 0UL))
80030c2: 6fbb ldr r3, [r7, #120] @ 0x78
80030c4: 2b00 cmp r3, #0
80030c6: d149 bne.n 800315c <HAL_ADCEx_MultiModeConfigChannel+0x114>
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
80030c8: 4b30 ldr r3, [pc, #192] @ (800318c <HAL_ADCEx_MultiModeConfigChannel+0x144>)
80030ca: 677b str r3, [r7, #116] @ 0x74
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
80030cc: 683b ldr r3, [r7, #0]
80030ce: 681b ldr r3, [r3, #0]
80030d0: 2b00 cmp r3, #0
80030d2: d028 beq.n 8003126 <HAL_ADCEx_MultiModeConfigChannel+0xde>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
80030d4: 6f7b ldr r3, [r7, #116] @ 0x74
80030d6: 689b ldr r3, [r3, #8]
80030d8: f423 4260 bic.w r2, r3, #57344 @ 0xe000
80030dc: 683b ldr r3, [r7, #0]
80030de: 6859 ldr r1, [r3, #4]
80030e0: 687b ldr r3, [r7, #4]
80030e2: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
80030e6: 035b lsls r3, r3, #13
80030e8: 430b orrs r3, r1
80030ea: 431a orrs r2, r3
80030ec: 6f7b ldr r3, [r7, #116] @ 0x74
80030ee: 609a str r2, [r3, #8]
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80030f0: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
80030f4: f7ff fef3 bl 8002ede <LL_ADC_IsEnabled>
80030f8: 4604 mov r4, r0
80030fa: 4823 ldr r0, [pc, #140] @ (8003188 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
80030fc: f7ff feef bl 8002ede <LL_ADC_IsEnabled>
8003100: 4603 mov r3, r0
8003102: 4323 orrs r3, r4
8003104: 2b00 cmp r3, #0
8003106: d133 bne.n 8003170 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
MODIFY_REG(tmpADC_Common->CCR,
8003108: 6f7b ldr r3, [r7, #116] @ 0x74
800310a: 689b ldr r3, [r3, #8]
800310c: f423 6371 bic.w r3, r3, #3856 @ 0xf10
8003110: f023 030f bic.w r3, r3, #15
8003114: 683a ldr r2, [r7, #0]
8003116: 6811 ldr r1, [r2, #0]
8003118: 683a ldr r2, [r7, #0]
800311a: 6892 ldr r2, [r2, #8]
800311c: 430a orrs r2, r1
800311e: 431a orrs r2, r3
8003120: 6f7b ldr r3, [r7, #116] @ 0x74
8003122: 609a str r2, [r3, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003124: e024 b.n 8003170 <HAL_ADCEx_MultiModeConfigChannel+0x128>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
8003126: 6f7b ldr r3, [r7, #116] @ 0x74
8003128: 689b ldr r3, [r3, #8]
800312a: f423 4260 bic.w r2, r3, #57344 @ 0xe000
800312e: 6f7b ldr r3, [r7, #116] @ 0x74
8003130: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8003132: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
8003136: f7ff fed2 bl 8002ede <LL_ADC_IsEnabled>
800313a: 4604 mov r4, r0
800313c: 4812 ldr r0, [pc, #72] @ (8003188 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
800313e: f7ff fece bl 8002ede <LL_ADC_IsEnabled>
8003142: 4603 mov r3, r0
8003144: 4323 orrs r3, r4
8003146: 2b00 cmp r3, #0
8003148: d112 bne.n 8003170 <HAL_ADCEx_MultiModeConfigChannel+0x128>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
800314a: 6f7b ldr r3, [r7, #116] @ 0x74
800314c: 689b ldr r3, [r3, #8]
800314e: f423 6371 bic.w r3, r3, #3856 @ 0xf10
8003152: f023 030f bic.w r3, r3, #15
8003156: 6f7a ldr r2, [r7, #116] @ 0x74
8003158: 6093 str r3, [r2, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
800315a: e009 b.n 8003170 <HAL_ADCEx_MultiModeConfigChannel+0x128>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800315c: 687b ldr r3, [r7, #4]
800315e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003160: f043 0220 orr.w r2, r3, #32
8003164: 687b ldr r3, [r7, #4]
8003166: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8003168: 2301 movs r3, #1
800316a: f887 307f strb.w r3, [r7, #127] @ 0x7f
800316e: e000 b.n 8003172 <HAL_ADCEx_MultiModeConfigChannel+0x12a>
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003170: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003172: 687b ldr r3, [r7, #4]
8003174: 2200 movs r2, #0
8003176: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
800317a: f897 307f ldrb.w r3, [r7, #127] @ 0x7f
}
800317e: 4618 mov r0, r3
8003180: 3784 adds r7, #132 @ 0x84
8003182: 46bd mov sp, r7
8003184: bd90 pop {r4, r7, pc}
8003186: bf00 nop
8003188: 50000100 .word 0x50000100
800318c: 50000300 .word 0x50000300
08003190 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003190: b480 push {r7}
8003192: b085 sub sp, #20
8003194: af00 add r7, sp, #0
8003196: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003198: 687b ldr r3, [r7, #4]
800319a: f003 0307 and.w r3, r3, #7
800319e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80031a0: 4b0c ldr r3, [pc, #48] @ (80031d4 <__NVIC_SetPriorityGrouping+0x44>)
80031a2: 68db ldr r3, [r3, #12]
80031a4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80031a6: 68ba ldr r2, [r7, #8]
80031a8: f64f 03ff movw r3, #63743 @ 0xf8ff
80031ac: 4013 ands r3, r2
80031ae: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80031b0: 68fb ldr r3, [r7, #12]
80031b2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80031b4: 68bb ldr r3, [r7, #8]
80031b6: 4313 orrs r3, r2
reg_value = (reg_value |
80031b8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80031bc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80031c0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80031c2: 4a04 ldr r2, [pc, #16] @ (80031d4 <__NVIC_SetPriorityGrouping+0x44>)
80031c4: 68bb ldr r3, [r7, #8]
80031c6: 60d3 str r3, [r2, #12]
}
80031c8: bf00 nop
80031ca: 3714 adds r7, #20
80031cc: 46bd mov sp, r7
80031ce: f85d 7b04 ldr.w r7, [sp], #4
80031d2: 4770 bx lr
80031d4: e000ed00 .word 0xe000ed00
080031d8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80031d8: b480 push {r7}
80031da: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80031dc: 4b04 ldr r3, [pc, #16] @ (80031f0 <__NVIC_GetPriorityGrouping+0x18>)
80031de: 68db ldr r3, [r3, #12]
80031e0: 0a1b lsrs r3, r3, #8
80031e2: f003 0307 and.w r3, r3, #7
}
80031e6: 4618 mov r0, r3
80031e8: 46bd mov sp, r7
80031ea: f85d 7b04 ldr.w r7, [sp], #4
80031ee: 4770 bx lr
80031f0: e000ed00 .word 0xe000ed00
080031f4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80031f4: b480 push {r7}
80031f6: b083 sub sp, #12
80031f8: af00 add r7, sp, #0
80031fa: 4603 mov r3, r0
80031fc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80031fe: f997 3007 ldrsb.w r3, [r7, #7]
8003202: 2b00 cmp r3, #0
8003204: db0b blt.n 800321e <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8003206: 79fb ldrb r3, [r7, #7]
8003208: f003 021f and.w r2, r3, #31
800320c: 4907 ldr r1, [pc, #28] @ (800322c <__NVIC_EnableIRQ+0x38>)
800320e: f997 3007 ldrsb.w r3, [r7, #7]
8003212: 095b lsrs r3, r3, #5
8003214: 2001 movs r0, #1
8003216: fa00 f202 lsl.w r2, r0, r2
800321a: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
800321e: bf00 nop
8003220: 370c adds r7, #12
8003222: 46bd mov sp, r7
8003224: f85d 7b04 ldr.w r7, [sp], #4
8003228: 4770 bx lr
800322a: bf00 nop
800322c: e000e100 .word 0xe000e100
08003230 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003230: b480 push {r7}
8003232: b083 sub sp, #12
8003234: af00 add r7, sp, #0
8003236: 4603 mov r3, r0
8003238: 6039 str r1, [r7, #0]
800323a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800323c: f997 3007 ldrsb.w r3, [r7, #7]
8003240: 2b00 cmp r3, #0
8003242: db0a blt.n 800325a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003244: 683b ldr r3, [r7, #0]
8003246: b2da uxtb r2, r3
8003248: 490c ldr r1, [pc, #48] @ (800327c <__NVIC_SetPriority+0x4c>)
800324a: f997 3007 ldrsb.w r3, [r7, #7]
800324e: 0112 lsls r2, r2, #4
8003250: b2d2 uxtb r2, r2
8003252: 440b add r3, r1
8003254: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003258: e00a b.n 8003270 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800325a: 683b ldr r3, [r7, #0]
800325c: b2da uxtb r2, r3
800325e: 4908 ldr r1, [pc, #32] @ (8003280 <__NVIC_SetPriority+0x50>)
8003260: 79fb ldrb r3, [r7, #7]
8003262: f003 030f and.w r3, r3, #15
8003266: 3b04 subs r3, #4
8003268: 0112 lsls r2, r2, #4
800326a: b2d2 uxtb r2, r2
800326c: 440b add r3, r1
800326e: 761a strb r2, [r3, #24]
}
8003270: bf00 nop
8003272: 370c adds r7, #12
8003274: 46bd mov sp, r7
8003276: f85d 7b04 ldr.w r7, [sp], #4
800327a: 4770 bx lr
800327c: e000e100 .word 0xe000e100
8003280: e000ed00 .word 0xe000ed00
08003284 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003284: b480 push {r7}
8003286: b089 sub sp, #36 @ 0x24
8003288: af00 add r7, sp, #0
800328a: 60f8 str r0, [r7, #12]
800328c: 60b9 str r1, [r7, #8]
800328e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003290: 68fb ldr r3, [r7, #12]
8003292: f003 0307 and.w r3, r3, #7
8003296: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8003298: 69fb ldr r3, [r7, #28]
800329a: f1c3 0307 rsb r3, r3, #7
800329e: 2b04 cmp r3, #4
80032a0: bf28 it cs
80032a2: 2304 movcs r3, #4
80032a4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80032a6: 69fb ldr r3, [r7, #28]
80032a8: 3304 adds r3, #4
80032aa: 2b06 cmp r3, #6
80032ac: d902 bls.n 80032b4 <NVIC_EncodePriority+0x30>
80032ae: 69fb ldr r3, [r7, #28]
80032b0: 3b03 subs r3, #3
80032b2: e000 b.n 80032b6 <NVIC_EncodePriority+0x32>
80032b4: 2300 movs r3, #0
80032b6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80032b8: f04f 32ff mov.w r2, #4294967295
80032bc: 69bb ldr r3, [r7, #24]
80032be: fa02 f303 lsl.w r3, r2, r3
80032c2: 43da mvns r2, r3
80032c4: 68bb ldr r3, [r7, #8]
80032c6: 401a ands r2, r3
80032c8: 697b ldr r3, [r7, #20]
80032ca: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80032cc: f04f 31ff mov.w r1, #4294967295
80032d0: 697b ldr r3, [r7, #20]
80032d2: fa01 f303 lsl.w r3, r1, r3
80032d6: 43d9 mvns r1, r3
80032d8: 687b ldr r3, [r7, #4]
80032da: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80032dc: 4313 orrs r3, r2
);
}
80032de: 4618 mov r0, r3
80032e0: 3724 adds r7, #36 @ 0x24
80032e2: 46bd mov sp, r7
80032e4: f85d 7b04 ldr.w r7, [sp], #4
80032e8: 4770 bx lr
...
080032ec <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80032ec: b580 push {r7, lr}
80032ee: b082 sub sp, #8
80032f0: af00 add r7, sp, #0
80032f2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80032f4: 687b ldr r3, [r7, #4]
80032f6: 3b01 subs r3, #1
80032f8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
80032fc: d301 bcc.n 8003302 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80032fe: 2301 movs r3, #1
8003300: e00f b.n 8003322 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003302: 4a0a ldr r2, [pc, #40] @ (800332c <SysTick_Config+0x40>)
8003304: 687b ldr r3, [r7, #4]
8003306: 3b01 subs r3, #1
8003308: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800330a: 210f movs r1, #15
800330c: f04f 30ff mov.w r0, #4294967295
8003310: f7ff ff8e bl 8003230 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003314: 4b05 ldr r3, [pc, #20] @ (800332c <SysTick_Config+0x40>)
8003316: 2200 movs r2, #0
8003318: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800331a: 4b04 ldr r3, [pc, #16] @ (800332c <SysTick_Config+0x40>)
800331c: 2207 movs r2, #7
800331e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003320: 2300 movs r3, #0
}
8003322: 4618 mov r0, r3
8003324: 3708 adds r7, #8
8003326: 46bd mov sp, r7
8003328: bd80 pop {r7, pc}
800332a: bf00 nop
800332c: e000e010 .word 0xe000e010
08003330 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003330: b580 push {r7, lr}
8003332: b082 sub sp, #8
8003334: af00 add r7, sp, #0
8003336: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003338: 6878 ldr r0, [r7, #4]
800333a: f7ff ff29 bl 8003190 <__NVIC_SetPriorityGrouping>
}
800333e: bf00 nop
8003340: 3708 adds r7, #8
8003342: 46bd mov sp, r7
8003344: bd80 pop {r7, pc}
08003346 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003346: b580 push {r7, lr}
8003348: b086 sub sp, #24
800334a: af00 add r7, sp, #0
800334c: 4603 mov r3, r0
800334e: 60b9 str r1, [r7, #8]
8003350: 607a str r2, [r7, #4]
8003352: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003354: f7ff ff40 bl 80031d8 <__NVIC_GetPriorityGrouping>
8003358: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800335a: 687a ldr r2, [r7, #4]
800335c: 68b9 ldr r1, [r7, #8]
800335e: 6978 ldr r0, [r7, #20]
8003360: f7ff ff90 bl 8003284 <NVIC_EncodePriority>
8003364: 4602 mov r2, r0
8003366: f997 300f ldrsb.w r3, [r7, #15]
800336a: 4611 mov r1, r2
800336c: 4618 mov r0, r3
800336e: f7ff ff5f bl 8003230 <__NVIC_SetPriority>
}
8003372: bf00 nop
8003374: 3718 adds r7, #24
8003376: 46bd mov sp, r7
8003378: bd80 pop {r7, pc}
0800337a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800337a: b580 push {r7, lr}
800337c: b082 sub sp, #8
800337e: af00 add r7, sp, #0
8003380: 4603 mov r3, r0
8003382: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003384: f997 3007 ldrsb.w r3, [r7, #7]
8003388: 4618 mov r0, r3
800338a: f7ff ff33 bl 80031f4 <__NVIC_EnableIRQ>
}
800338e: bf00 nop
8003390: 3708 adds r7, #8
8003392: 46bd mov sp, r7
8003394: bd80 pop {r7, pc}
08003396 <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8003396: b580 push {r7, lr}
8003398: b082 sub sp, #8
800339a: af00 add r7, sp, #0
800339c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
800339e: 6878 ldr r0, [r7, #4]
80033a0: f7ff ffa4 bl 80032ec <SysTick_Config>
80033a4: 4603 mov r3, r0
}
80033a6: 4618 mov r0, r3
80033a8: 3708 adds r7, #8
80033aa: 46bd mov sp, r7
80033ac: bd80 pop {r7, pc}
080033ae <HAL_DMA_Abort>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
80033ae: b480 push {r7}
80033b0: b085 sub sp, #20
80033b2: af00 add r7, sp, #0
80033b4: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80033b6: 2300 movs r3, #0
80033b8: 73fb strb r3, [r7, #15]
if(hdma->State != HAL_DMA_STATE_BUSY)
80033ba: 687b ldr r3, [r7, #4]
80033bc: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
80033c0: b2db uxtb r3, r3
80033c2: 2b02 cmp r3, #2
80033c4: d005 beq.n 80033d2 <HAL_DMA_Abort+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
80033c6: 687b ldr r3, [r7, #4]
80033c8: 2204 movs r2, #4
80033ca: 63da str r2, [r3, #60] @ 0x3c
status = HAL_ERROR;
80033cc: 2301 movs r3, #1
80033ce: 73fb strb r3, [r7, #15]
80033d0: e037 b.n 8003442 <HAL_DMA_Abort+0x94>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80033d2: 687b ldr r3, [r7, #4]
80033d4: 681b ldr r3, [r3, #0]
80033d6: 681a ldr r2, [r3, #0]
80033d8: 687b ldr r3, [r7, #4]
80033da: 681b ldr r3, [r3, #0]
80033dc: f022 020e bic.w r2, r2, #14
80033e0: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
80033e2: 687b ldr r3, [r7, #4]
80033e4: 6c9b ldr r3, [r3, #72] @ 0x48
80033e6: 681a ldr r2, [r3, #0]
80033e8: 687b ldr r3, [r7, #4]
80033ea: 6c9b ldr r3, [r3, #72] @ 0x48
80033ec: f422 7280 bic.w r2, r2, #256 @ 0x100
80033f0: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80033f2: 687b ldr r3, [r7, #4]
80033f4: 681b ldr r3, [r3, #0]
80033f6: 681a ldr r2, [r3, #0]
80033f8: 687b ldr r3, [r7, #4]
80033fa: 681b ldr r3, [r3, #0]
80033fc: f022 0201 bic.w r2, r2, #1
8003400: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8003402: 687b ldr r3, [r7, #4]
8003404: 6c5b ldr r3, [r3, #68] @ 0x44
8003406: f003 021f and.w r2, r3, #31
800340a: 687b ldr r3, [r7, #4]
800340c: 6c1b ldr r3, [r3, #64] @ 0x40
800340e: 2101 movs r1, #1
8003410: fa01 f202 lsl.w r2, r1, r2
8003414: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003416: 687b ldr r3, [r7, #4]
8003418: 6cdb ldr r3, [r3, #76] @ 0x4c
800341a: 687a ldr r2, [r7, #4]
800341c: 6d12 ldr r2, [r2, #80] @ 0x50
800341e: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003420: 687b ldr r3, [r7, #4]
8003422: 6d5b ldr r3, [r3, #84] @ 0x54
8003424: 2b00 cmp r3, #0
8003426: d00c beq.n 8003442 <HAL_DMA_Abort+0x94>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003428: 687b ldr r3, [r7, #4]
800342a: 6d5b ldr r3, [r3, #84] @ 0x54
800342c: 681a ldr r2, [r3, #0]
800342e: 687b ldr r3, [r7, #4]
8003430: 6d5b ldr r3, [r3, #84] @ 0x54
8003432: f422 7280 bic.w r2, r2, #256 @ 0x100
8003436: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003438: 687b ldr r3, [r7, #4]
800343a: 6d9b ldr r3, [r3, #88] @ 0x58
800343c: 687a ldr r2, [r7, #4]
800343e: 6dd2 ldr r2, [r2, #92] @ 0x5c
8003440: 605a str r2, [r3, #4]
}
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003442: 687b ldr r3, [r7, #4]
8003444: 2201 movs r2, #1
8003446: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800344a: 687b ldr r3, [r7, #4]
800344c: 2200 movs r2, #0
800344e: f883 2024 strb.w r2, [r3, #36] @ 0x24
return status;
8003452: 7bfb ldrb r3, [r7, #15]
}
8003454: 4618 mov r0, r3
8003456: 3714 adds r7, #20
8003458: 46bd mov sp, r7
800345a: f85d 7b04 ldr.w r7, [sp], #4
800345e: 4770 bx lr
08003460 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8003460: b580 push {r7, lr}
8003462: b084 sub sp, #16
8003464: af00 add r7, sp, #0
8003466: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8003468: 2300 movs r3, #0
800346a: 73fb strb r3, [r7, #15]
if (HAL_DMA_STATE_BUSY != hdma->State)
800346c: 687b ldr r3, [r7, #4]
800346e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8003472: b2db uxtb r3, r3
8003474: 2b02 cmp r3, #2
8003476: d00d beq.n 8003494 <HAL_DMA_Abort_IT+0x34>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003478: 687b ldr r3, [r7, #4]
800347a: 2204 movs r2, #4
800347c: 63da str r2, [r3, #60] @ 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800347e: 687b ldr r3, [r7, #4]
8003480: 2201 movs r2, #1
8003482: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003486: 687b ldr r3, [r7, #4]
8003488: 2200 movs r2, #0
800348a: f883 2024 strb.w r2, [r3, #36] @ 0x24
status = HAL_ERROR;
800348e: 2301 movs r3, #1
8003490: 73fb strb r3, [r7, #15]
8003492: e047 b.n 8003524 <HAL_DMA_Abort_IT+0xc4>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003494: 687b ldr r3, [r7, #4]
8003496: 681b ldr r3, [r3, #0]
8003498: 681a ldr r2, [r3, #0]
800349a: 687b ldr r3, [r7, #4]
800349c: 681b ldr r3, [r3, #0]
800349e: f022 020e bic.w r2, r2, #14
80034a2: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
80034a4: 687b ldr r3, [r7, #4]
80034a6: 681b ldr r3, [r3, #0]
80034a8: 681a ldr r2, [r3, #0]
80034aa: 687b ldr r3, [r7, #4]
80034ac: 681b ldr r3, [r3, #0]
80034ae: f022 0201 bic.w r2, r2, #1
80034b2: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
80034b4: 687b ldr r3, [r7, #4]
80034b6: 6c9b ldr r3, [r3, #72] @ 0x48
80034b8: 681a ldr r2, [r3, #0]
80034ba: 687b ldr r3, [r7, #4]
80034bc: 6c9b ldr r3, [r3, #72] @ 0x48
80034be: f422 7280 bic.w r2, r2, #256 @ 0x100
80034c2: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
80034c4: 687b ldr r3, [r7, #4]
80034c6: 6c5b ldr r3, [r3, #68] @ 0x44
80034c8: f003 021f and.w r2, r3, #31
80034cc: 687b ldr r3, [r7, #4]
80034ce: 6c1b ldr r3, [r3, #64] @ 0x40
80034d0: 2101 movs r1, #1
80034d2: fa01 f202 lsl.w r2, r1, r2
80034d6: 605a str r2, [r3, #4]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
80034d8: 687b ldr r3, [r7, #4]
80034da: 6cdb ldr r3, [r3, #76] @ 0x4c
80034dc: 687a ldr r2, [r7, #4]
80034de: 6d12 ldr r2, [r2, #80] @ 0x50
80034e0: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
80034e2: 687b ldr r3, [r7, #4]
80034e4: 6d5b ldr r3, [r3, #84] @ 0x54
80034e6: 2b00 cmp r3, #0
80034e8: d00c beq.n 8003504 <HAL_DMA_Abort_IT+0xa4>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
80034ea: 687b ldr r3, [r7, #4]
80034ec: 6d5b ldr r3, [r3, #84] @ 0x54
80034ee: 681a ldr r2, [r3, #0]
80034f0: 687b ldr r3, [r7, #4]
80034f2: 6d5b ldr r3, [r3, #84] @ 0x54
80034f4: f422 7280 bic.w r2, r2, #256 @ 0x100
80034f8: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80034fa: 687b ldr r3, [r7, #4]
80034fc: 6d9b ldr r3, [r3, #88] @ 0x58
80034fe: 687a ldr r2, [r7, #4]
8003500: 6dd2 ldr r2, [r2, #92] @ 0x5c
8003502: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003504: 687b ldr r3, [r7, #4]
8003506: 2201 movs r2, #1
8003508: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800350c: 687b ldr r3, [r7, #4]
800350e: 2200 movs r2, #0
8003510: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
8003514: 687b ldr r3, [r7, #4]
8003516: 6b9b ldr r3, [r3, #56] @ 0x38
8003518: 2b00 cmp r3, #0
800351a: d003 beq.n 8003524 <HAL_DMA_Abort_IT+0xc4>
{
hdma->XferAbortCallback(hdma);
800351c: 687b ldr r3, [r7, #4]
800351e: 6b9b ldr r3, [r3, #56] @ 0x38
8003520: 6878 ldr r0, [r7, #4]
8003522: 4798 blx r3
}
}
return status;
8003524: 7bfb ldrb r3, [r7, #15]
}
8003526: 4618 mov r0, r3
8003528: 3710 adds r7, #16
800352a: 46bd mov sp, r7
800352c: bd80 pop {r7, pc}
...
08003530 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003530: b480 push {r7}
8003532: b087 sub sp, #28
8003534: af00 add r7, sp, #0
8003536: 6078 str r0, [r7, #4]
8003538: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
800353a: 2300 movs r3, #0
800353c: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
800353e: e15a b.n 80037f6 <HAL_GPIO_Init+0x2c6>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8003540: 683b ldr r3, [r7, #0]
8003542: 681a ldr r2, [r3, #0]
8003544: 2101 movs r1, #1
8003546: 697b ldr r3, [r7, #20]
8003548: fa01 f303 lsl.w r3, r1, r3
800354c: 4013 ands r3, r2
800354e: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8003550: 68fb ldr r3, [r7, #12]
8003552: 2b00 cmp r3, #0
8003554: f000 814c beq.w 80037f0 <HAL_GPIO_Init+0x2c0>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8003558: 683b ldr r3, [r7, #0]
800355a: 685b ldr r3, [r3, #4]
800355c: f003 0303 and.w r3, r3, #3
8003560: 2b01 cmp r3, #1
8003562: d005 beq.n 8003570 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8003564: 683b ldr r3, [r7, #0]
8003566: 685b ldr r3, [r3, #4]
8003568: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
800356c: 2b02 cmp r3, #2
800356e: d130 bne.n 80035d2 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8003570: 687b ldr r3, [r7, #4]
8003572: 689b ldr r3, [r3, #8]
8003574: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8003576: 697b ldr r3, [r7, #20]
8003578: 005b lsls r3, r3, #1
800357a: 2203 movs r2, #3
800357c: fa02 f303 lsl.w r3, r2, r3
8003580: 43db mvns r3, r3
8003582: 693a ldr r2, [r7, #16]
8003584: 4013 ands r3, r2
8003586: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
8003588: 683b ldr r3, [r7, #0]
800358a: 68da ldr r2, [r3, #12]
800358c: 697b ldr r3, [r7, #20]
800358e: 005b lsls r3, r3, #1
8003590: fa02 f303 lsl.w r3, r2, r3
8003594: 693a ldr r2, [r7, #16]
8003596: 4313 orrs r3, r2
8003598: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800359a: 687b ldr r3, [r7, #4]
800359c: 693a ldr r2, [r7, #16]
800359e: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80035a0: 687b ldr r3, [r7, #4]
80035a2: 685b ldr r3, [r3, #4]
80035a4: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
80035a6: 2201 movs r2, #1
80035a8: 697b ldr r3, [r7, #20]
80035aa: fa02 f303 lsl.w r3, r2, r3
80035ae: 43db mvns r3, r3
80035b0: 693a ldr r2, [r7, #16]
80035b2: 4013 ands r3, r2
80035b4: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80035b6: 683b ldr r3, [r7, #0]
80035b8: 685b ldr r3, [r3, #4]
80035ba: 091b lsrs r3, r3, #4
80035bc: f003 0201 and.w r2, r3, #1
80035c0: 697b ldr r3, [r7, #20]
80035c2: fa02 f303 lsl.w r3, r2, r3
80035c6: 693a ldr r2, [r7, #16]
80035c8: 4313 orrs r3, r2
80035ca: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80035cc: 687b ldr r3, [r7, #4]
80035ce: 693a ldr r2, [r7, #16]
80035d0: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80035d2: 683b ldr r3, [r7, #0]
80035d4: 685b ldr r3, [r3, #4]
80035d6: f003 0303 and.w r3, r3, #3
80035da: 2b03 cmp r3, #3
80035dc: d017 beq.n 800360e <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80035de: 687b ldr r3, [r7, #4]
80035e0: 68db ldr r3, [r3, #12]
80035e2: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
80035e4: 697b ldr r3, [r7, #20]
80035e6: 005b lsls r3, r3, #1
80035e8: 2203 movs r2, #3
80035ea: fa02 f303 lsl.w r3, r2, r3
80035ee: 43db mvns r3, r3
80035f0: 693a ldr r2, [r7, #16]
80035f2: 4013 ands r3, r2
80035f4: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80035f6: 683b ldr r3, [r7, #0]
80035f8: 689a ldr r2, [r3, #8]
80035fa: 697b ldr r3, [r7, #20]
80035fc: 005b lsls r3, r3, #1
80035fe: fa02 f303 lsl.w r3, r2, r3
8003602: 693a ldr r2, [r7, #16]
8003604: 4313 orrs r3, r2
8003606: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8003608: 687b ldr r3, [r7, #4]
800360a: 693a ldr r2, [r7, #16]
800360c: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800360e: 683b ldr r3, [r7, #0]
8003610: 685b ldr r3, [r3, #4]
8003612: f003 0303 and.w r3, r3, #3
8003616: 2b02 cmp r3, #2
8003618: d123 bne.n 8003662 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
800361a: 697b ldr r3, [r7, #20]
800361c: 08da lsrs r2, r3, #3
800361e: 687b ldr r3, [r7, #4]
8003620: 3208 adds r2, #8
8003622: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8003626: 613b str r3, [r7, #16]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8003628: 697b ldr r3, [r7, #20]
800362a: f003 0307 and.w r3, r3, #7
800362e: 009b lsls r3, r3, #2
8003630: 220f movs r2, #15
8003632: fa02 f303 lsl.w r3, r2, r3
8003636: 43db mvns r3, r3
8003638: 693a ldr r2, [r7, #16]
800363a: 4013 ands r3, r2
800363c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
800363e: 683b ldr r3, [r7, #0]
8003640: 691a ldr r2, [r3, #16]
8003642: 697b ldr r3, [r7, #20]
8003644: f003 0307 and.w r3, r3, #7
8003648: 009b lsls r3, r3, #2
800364a: fa02 f303 lsl.w r3, r2, r3
800364e: 693a ldr r2, [r7, #16]
8003650: 4313 orrs r3, r2
8003652: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
8003654: 697b ldr r3, [r7, #20]
8003656: 08da lsrs r2, r3, #3
8003658: 687b ldr r3, [r7, #4]
800365a: 3208 adds r2, #8
800365c: 6939 ldr r1, [r7, #16]
800365e: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003662: 687b ldr r3, [r7, #4]
8003664: 681b ldr r3, [r3, #0]
8003666: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8003668: 697b ldr r3, [r7, #20]
800366a: 005b lsls r3, r3, #1
800366c: 2203 movs r2, #3
800366e: fa02 f303 lsl.w r3, r2, r3
8003672: 43db mvns r3, r3
8003674: 693a ldr r2, [r7, #16]
8003676: 4013 ands r3, r2
8003678: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
800367a: 683b ldr r3, [r7, #0]
800367c: 685b ldr r3, [r3, #4]
800367e: f003 0203 and.w r2, r3, #3
8003682: 697b ldr r3, [r7, #20]
8003684: 005b lsls r3, r3, #1
8003686: fa02 f303 lsl.w r3, r2, r3
800368a: 693a ldr r2, [r7, #16]
800368c: 4313 orrs r3, r2
800368e: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8003690: 687b ldr r3, [r7, #4]
8003692: 693a ldr r2, [r7, #16]
8003694: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8003696: 683b ldr r3, [r7, #0]
8003698: 685b ldr r3, [r3, #4]
800369a: f403 3340 and.w r3, r3, #196608 @ 0x30000
800369e: 2b00 cmp r3, #0
80036a0: f000 80a6 beq.w 80037f0 <HAL_GPIO_Init+0x2c0>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80036a4: 4b5b ldr r3, [pc, #364] @ (8003814 <HAL_GPIO_Init+0x2e4>)
80036a6: 6e1b ldr r3, [r3, #96] @ 0x60
80036a8: 4a5a ldr r2, [pc, #360] @ (8003814 <HAL_GPIO_Init+0x2e4>)
80036aa: f043 0301 orr.w r3, r3, #1
80036ae: 6613 str r3, [r2, #96] @ 0x60
80036b0: 4b58 ldr r3, [pc, #352] @ (8003814 <HAL_GPIO_Init+0x2e4>)
80036b2: 6e1b ldr r3, [r3, #96] @ 0x60
80036b4: f003 0301 and.w r3, r3, #1
80036b8: 60bb str r3, [r7, #8]
80036ba: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2U];
80036bc: 4a56 ldr r2, [pc, #344] @ (8003818 <HAL_GPIO_Init+0x2e8>)
80036be: 697b ldr r3, [r7, #20]
80036c0: 089b lsrs r3, r3, #2
80036c2: 3302 adds r3, #2
80036c4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80036c8: 613b str r3, [r7, #16]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
80036ca: 697b ldr r3, [r7, #20]
80036cc: f003 0303 and.w r3, r3, #3
80036d0: 009b lsls r3, r3, #2
80036d2: 220f movs r2, #15
80036d4: fa02 f303 lsl.w r3, r2, r3
80036d8: 43db mvns r3, r3
80036da: 693a ldr r2, [r7, #16]
80036dc: 4013 ands r3, r2
80036de: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
80036e0: 687b ldr r3, [r7, #4]
80036e2: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
80036e6: d01f beq.n 8003728 <HAL_GPIO_Init+0x1f8>
80036e8: 687b ldr r3, [r7, #4]
80036ea: 4a4c ldr r2, [pc, #304] @ (800381c <HAL_GPIO_Init+0x2ec>)
80036ec: 4293 cmp r3, r2
80036ee: d019 beq.n 8003724 <HAL_GPIO_Init+0x1f4>
80036f0: 687b ldr r3, [r7, #4]
80036f2: 4a4b ldr r2, [pc, #300] @ (8003820 <HAL_GPIO_Init+0x2f0>)
80036f4: 4293 cmp r3, r2
80036f6: d013 beq.n 8003720 <HAL_GPIO_Init+0x1f0>
80036f8: 687b ldr r3, [r7, #4]
80036fa: 4a4a ldr r2, [pc, #296] @ (8003824 <HAL_GPIO_Init+0x2f4>)
80036fc: 4293 cmp r3, r2
80036fe: d00d beq.n 800371c <HAL_GPIO_Init+0x1ec>
8003700: 687b ldr r3, [r7, #4]
8003702: 4a49 ldr r2, [pc, #292] @ (8003828 <HAL_GPIO_Init+0x2f8>)
8003704: 4293 cmp r3, r2
8003706: d007 beq.n 8003718 <HAL_GPIO_Init+0x1e8>
8003708: 687b ldr r3, [r7, #4]
800370a: 4a48 ldr r2, [pc, #288] @ (800382c <HAL_GPIO_Init+0x2fc>)
800370c: 4293 cmp r3, r2
800370e: d101 bne.n 8003714 <HAL_GPIO_Init+0x1e4>
8003710: 2305 movs r3, #5
8003712: e00a b.n 800372a <HAL_GPIO_Init+0x1fa>
8003714: 2306 movs r3, #6
8003716: e008 b.n 800372a <HAL_GPIO_Init+0x1fa>
8003718: 2304 movs r3, #4
800371a: e006 b.n 800372a <HAL_GPIO_Init+0x1fa>
800371c: 2303 movs r3, #3
800371e: e004 b.n 800372a <HAL_GPIO_Init+0x1fa>
8003720: 2302 movs r3, #2
8003722: e002 b.n 800372a <HAL_GPIO_Init+0x1fa>
8003724: 2301 movs r3, #1
8003726: e000 b.n 800372a <HAL_GPIO_Init+0x1fa>
8003728: 2300 movs r3, #0
800372a: 697a ldr r2, [r7, #20]
800372c: f002 0203 and.w r2, r2, #3
8003730: 0092 lsls r2, r2, #2
8003732: 4093 lsls r3, r2
8003734: 693a ldr r2, [r7, #16]
8003736: 4313 orrs r3, r2
8003738: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2U] = temp;
800373a: 4937 ldr r1, [pc, #220] @ (8003818 <HAL_GPIO_Init+0x2e8>)
800373c: 697b ldr r3, [r7, #20]
800373e: 089b lsrs r3, r3, #2
8003740: 3302 adds r3, #2
8003742: 693a ldr r2, [r7, #16]
8003744: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8003748: 4b39 ldr r3, [pc, #228] @ (8003830 <HAL_GPIO_Init+0x300>)
800374a: 689b ldr r3, [r3, #8]
800374c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800374e: 68fb ldr r3, [r7, #12]
8003750: 43db mvns r3, r3
8003752: 693a ldr r2, [r7, #16]
8003754: 4013 ands r3, r2
8003756: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8003758: 683b ldr r3, [r7, #0]
800375a: 685b ldr r3, [r3, #4]
800375c: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8003760: 2b00 cmp r3, #0
8003762: d003 beq.n 800376c <HAL_GPIO_Init+0x23c>
{
temp |= iocurrent;
8003764: 693a ldr r2, [r7, #16]
8003766: 68fb ldr r3, [r7, #12]
8003768: 4313 orrs r3, r2
800376a: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
800376c: 4a30 ldr r2, [pc, #192] @ (8003830 <HAL_GPIO_Init+0x300>)
800376e: 693b ldr r3, [r7, #16]
8003770: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8003772: 4b2f ldr r3, [pc, #188] @ (8003830 <HAL_GPIO_Init+0x300>)
8003774: 68db ldr r3, [r3, #12]
8003776: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003778: 68fb ldr r3, [r7, #12]
800377a: 43db mvns r3, r3
800377c: 693a ldr r2, [r7, #16]
800377e: 4013 ands r3, r2
8003780: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8003782: 683b ldr r3, [r7, #0]
8003784: 685b ldr r3, [r3, #4]
8003786: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800378a: 2b00 cmp r3, #0
800378c: d003 beq.n 8003796 <HAL_GPIO_Init+0x266>
{
temp |= iocurrent;
800378e: 693a ldr r2, [r7, #16]
8003790: 68fb ldr r3, [r7, #12]
8003792: 4313 orrs r3, r2
8003794: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8003796: 4a26 ldr r2, [pc, #152] @ (8003830 <HAL_GPIO_Init+0x300>)
8003798: 693b ldr r3, [r7, #16]
800379a: 60d3 str r3, [r2, #12]
temp = EXTI->EMR1;
800379c: 4b24 ldr r3, [pc, #144] @ (8003830 <HAL_GPIO_Init+0x300>)
800379e: 685b ldr r3, [r3, #4]
80037a0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80037a2: 68fb ldr r3, [r7, #12]
80037a4: 43db mvns r3, r3
80037a6: 693a ldr r2, [r7, #16]
80037a8: 4013 ands r3, r2
80037aa: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
80037ac: 683b ldr r3, [r7, #0]
80037ae: 685b ldr r3, [r3, #4]
80037b0: f403 3300 and.w r3, r3, #131072 @ 0x20000
80037b4: 2b00 cmp r3, #0
80037b6: d003 beq.n 80037c0 <HAL_GPIO_Init+0x290>
{
temp |= iocurrent;
80037b8: 693a ldr r2, [r7, #16]
80037ba: 68fb ldr r3, [r7, #12]
80037bc: 4313 orrs r3, r2
80037be: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
80037c0: 4a1b ldr r2, [pc, #108] @ (8003830 <HAL_GPIO_Init+0x300>)
80037c2: 693b ldr r3, [r7, #16]
80037c4: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
80037c6: 4b1a ldr r3, [pc, #104] @ (8003830 <HAL_GPIO_Init+0x300>)
80037c8: 681b ldr r3, [r3, #0]
80037ca: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80037cc: 68fb ldr r3, [r7, #12]
80037ce: 43db mvns r3, r3
80037d0: 693a ldr r2, [r7, #16]
80037d2: 4013 ands r3, r2
80037d4: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80037d6: 683b ldr r3, [r7, #0]
80037d8: 685b ldr r3, [r3, #4]
80037da: f403 3380 and.w r3, r3, #65536 @ 0x10000
80037de: 2b00 cmp r3, #0
80037e0: d003 beq.n 80037ea <HAL_GPIO_Init+0x2ba>
{
temp |= iocurrent;
80037e2: 693a ldr r2, [r7, #16]
80037e4: 68fb ldr r3, [r7, #12]
80037e6: 4313 orrs r3, r2
80037e8: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
80037ea: 4a11 ldr r2, [pc, #68] @ (8003830 <HAL_GPIO_Init+0x300>)
80037ec: 693b ldr r3, [r7, #16]
80037ee: 6013 str r3, [r2, #0]
}
}
position++;
80037f0: 697b ldr r3, [r7, #20]
80037f2: 3301 adds r3, #1
80037f4: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0U)
80037f6: 683b ldr r3, [r7, #0]
80037f8: 681a ldr r2, [r3, #0]
80037fa: 697b ldr r3, [r7, #20]
80037fc: fa22 f303 lsr.w r3, r2, r3
8003800: 2b00 cmp r3, #0
8003802: f47f ae9d bne.w 8003540 <HAL_GPIO_Init+0x10>
}
}
8003806: bf00 nop
8003808: bf00 nop
800380a: 371c adds r7, #28
800380c: 46bd mov sp, r7
800380e: f85d 7b04 ldr.w r7, [sp], #4
8003812: 4770 bx lr
8003814: 40021000 .word 0x40021000
8003818: 40010000 .word 0x40010000
800381c: 48000400 .word 0x48000400
8003820: 48000800 .word 0x48000800
8003824: 48000c00 .word 0x48000c00
8003828: 48001000 .word 0x48001000
800382c: 48001400 .word 0x48001400
8003830: 40010400 .word 0x40010400
08003834 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8003834: b480 push {r7}
8003836: b083 sub sp, #12
8003838: af00 add r7, sp, #0
800383a: 6078 str r0, [r7, #4]
800383c: 460b mov r3, r1
800383e: 807b strh r3, [r7, #2]
8003840: 4613 mov r3, r2
8003842: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003844: 787b ldrb r3, [r7, #1]
8003846: 2b00 cmp r3, #0
8003848: d003 beq.n 8003852 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
800384a: 887a ldrh r2, [r7, #2]
800384c: 687b ldr r3, [r7, #4]
800384e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8003850: e002 b.n 8003858 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8003852: 887a ldrh r2, [r7, #2]
8003854: 687b ldr r3, [r7, #4]
8003856: 629a str r2, [r3, #40] @ 0x28
}
8003858: bf00 nop
800385a: 370c adds r7, #12
800385c: 46bd mov sp, r7
800385e: f85d 7b04 ldr.w r7, [sp], #4
8003862: 4770 bx lr
08003864 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8003864: b480 push {r7}
8003866: b085 sub sp, #20
8003868: af00 add r7, sp, #0
800386a: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
800386c: 687b ldr r3, [r7, #4]
800386e: 2b00 cmp r3, #0
8003870: d141 bne.n 80038f6 <HAL_PWREx_ControlVoltageScaling+0x92>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8003872: 4b4b ldr r3, [pc, #300] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003874: 681b ldr r3, [r3, #0]
8003876: f403 63c0 and.w r3, r3, #1536 @ 0x600
800387a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800387e: d131 bne.n 80038e4 <HAL_PWREx_ControlVoltageScaling+0x80>
{
/* Make sure Range 1 Boost is enabled */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003880: 4b47 ldr r3, [pc, #284] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003882: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003886: 4a46 ldr r2, [pc, #280] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003888: f423 7380 bic.w r3, r3, #256 @ 0x100
800388c: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8003890: 4b43 ldr r3, [pc, #268] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003892: 681b ldr r3, [r3, #0]
8003894: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003898: 4a41 ldr r2, [pc, #260] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800389a: f443 7300 orr.w r3, r3, #512 @ 0x200
800389e: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
80038a0: 4b40 ldr r3, [pc, #256] @ (80039a4 <HAL_PWREx_ControlVoltageScaling+0x140>)
80038a2: 681b ldr r3, [r3, #0]
80038a4: 2232 movs r2, #50 @ 0x32
80038a6: fb02 f303 mul.w r3, r2, r3
80038aa: 4a3f ldr r2, [pc, #252] @ (80039a8 <HAL_PWREx_ControlVoltageScaling+0x144>)
80038ac: fba2 2303 umull r2, r3, r2, r3
80038b0: 0c9b lsrs r3, r3, #18
80038b2: 3301 adds r3, #1
80038b4: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80038b6: e002 b.n 80038be <HAL_PWREx_ControlVoltageScaling+0x5a>
{
wait_loop_index--;
80038b8: 68fb ldr r3, [r7, #12]
80038ba: 3b01 subs r3, #1
80038bc: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80038be: 4b38 ldr r3, [pc, #224] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80038c0: 695b ldr r3, [r3, #20]
80038c2: f403 6380 and.w r3, r3, #1024 @ 0x400
80038c6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80038ca: d102 bne.n 80038d2 <HAL_PWREx_ControlVoltageScaling+0x6e>
80038cc: 68fb ldr r3, [r7, #12]
80038ce: 2b00 cmp r3, #0
80038d0: d1f2 bne.n 80038b8 <HAL_PWREx_ControlVoltageScaling+0x54>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80038d2: 4b33 ldr r3, [pc, #204] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80038d4: 695b ldr r3, [r3, #20]
80038d6: f403 6380 and.w r3, r3, #1024 @ 0x400
80038da: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80038de: d158 bne.n 8003992 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
80038e0: 2303 movs r3, #3
80038e2: e057 b.n 8003994 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Enable Range 1 Boost (no issue if bit already reset) */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
80038e4: 4b2e ldr r3, [pc, #184] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80038e6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80038ea: 4a2d ldr r2, [pc, #180] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80038ec: f423 7380 bic.w r3, r3, #256 @ 0x100
80038f0: f8c2 3080 str.w r3, [r2, #128] @ 0x80
80038f4: e04d b.n 8003992 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
80038f6: 687b ldr r3, [r7, #4]
80038f8: f5b3 7f00 cmp.w r3, #512 @ 0x200
80038fc: d141 bne.n 8003982 <HAL_PWREx_ControlVoltageScaling+0x11e>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
80038fe: 4b28 ldr r3, [pc, #160] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003900: 681b ldr r3, [r3, #0]
8003902: f403 63c0 and.w r3, r3, #1536 @ 0x600
8003906: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800390a: d131 bne.n 8003970 <HAL_PWREx_ControlVoltageScaling+0x10c>
{
/* Make sure Range 1 Boost is disabled */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
800390c: 4b24 ldr r3, [pc, #144] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800390e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003912: 4a23 ldr r2, [pc, #140] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003914: f443 7380 orr.w r3, r3, #256 @ 0x100
8003918: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
800391c: 4b20 ldr r3, [pc, #128] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800391e: 681b ldr r3, [r3, #0]
8003920: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8003924: 4a1e ldr r2, [pc, #120] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003926: f443 7300 orr.w r3, r3, #512 @ 0x200
800392a: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
800392c: 4b1d ldr r3, [pc, #116] @ (80039a4 <HAL_PWREx_ControlVoltageScaling+0x140>)
800392e: 681b ldr r3, [r3, #0]
8003930: 2232 movs r2, #50 @ 0x32
8003932: fb02 f303 mul.w r3, r2, r3
8003936: 4a1c ldr r2, [pc, #112] @ (80039a8 <HAL_PWREx_ControlVoltageScaling+0x144>)
8003938: fba2 2303 umull r2, r3, r2, r3
800393c: 0c9b lsrs r3, r3, #18
800393e: 3301 adds r3, #1
8003940: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8003942: e002 b.n 800394a <HAL_PWREx_ControlVoltageScaling+0xe6>
{
wait_loop_index--;
8003944: 68fb ldr r3, [r7, #12]
8003946: 3b01 subs r3, #1
8003948: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
800394a: 4b15 ldr r3, [pc, #84] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800394c: 695b ldr r3, [r3, #20]
800394e: f403 6380 and.w r3, r3, #1024 @ 0x400
8003952: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003956: d102 bne.n 800395e <HAL_PWREx_ControlVoltageScaling+0xfa>
8003958: 68fb ldr r3, [r7, #12]
800395a: 2b00 cmp r3, #0
800395c: d1f2 bne.n 8003944 <HAL_PWREx_ControlVoltageScaling+0xe0>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
800395e: 4b10 ldr r3, [pc, #64] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003960: 695b ldr r3, [r3, #20]
8003962: f403 6380 and.w r3, r3, #1024 @ 0x400
8003966: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800396a: d112 bne.n 8003992 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
800396c: 2303 movs r3, #3
800396e: e011 b.n 8003994 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Disable Range 1 Boost (no issue if bit already set) */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8003970: 4b0b ldr r3, [pc, #44] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003972: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8003976: 4a0a ldr r2, [pc, #40] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003978: f443 7380 orr.w r3, r3, #256 @ 0x100
800397c: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8003980: e007 b.n 8003992 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8003982: 4b07 ldr r3, [pc, #28] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8003984: 681b ldr r3, [r3, #0]
8003986: f423 63c0 bic.w r3, r3, #1536 @ 0x600
800398a: 4a05 ldr r2, [pc, #20] @ (80039a0 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800398c: f443 6380 orr.w r3, r3, #1024 @ 0x400
8003990: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
}
return HAL_OK;
8003992: 2300 movs r3, #0
}
8003994: 4618 mov r0, r3
8003996: 3714 adds r7, #20
8003998: 46bd mov sp, r7
800399a: f85d 7b04 ldr.w r7, [sp], #4
800399e: 4770 bx lr
80039a0: 40007000 .word 0x40007000
80039a4: 2000001c .word 0x2000001c
80039a8: 431bde83 .word 0x431bde83
080039ac <HAL_PWREx_DisableUCPDDeadBattery>:
* or to hand over control to the UCPD (which should therefore be
* initialized before doing the disable).
* @retval None
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
80039ac: b480 push {r7}
80039ae: af00 add r7, sp, #0
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
80039b0: 4b05 ldr r3, [pc, #20] @ (80039c8 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
80039b2: 689b ldr r3, [r3, #8]
80039b4: 4a04 ldr r2, [pc, #16] @ (80039c8 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
80039b6: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80039ba: 6093 str r3, [r2, #8]
}
80039bc: bf00 nop
80039be: 46bd mov sp, r7
80039c0: f85d 7b04 ldr.w r7, [sp], #4
80039c4: 4770 bx lr
80039c6: bf00 nop
80039c8: 40007000 .word 0x40007000
080039cc <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80039cc: b580 push {r7, lr}
80039ce: b088 sub sp, #32
80039d0: af00 add r7, sp, #0
80039d2: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80039d4: 687b ldr r3, [r7, #4]
80039d6: 2b00 cmp r3, #0
80039d8: d101 bne.n 80039de <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80039da: 2301 movs r3, #1
80039dc: e2fe b.n 8003fdc <HAL_RCC_OscConfig+0x610>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80039de: 687b ldr r3, [r7, #4]
80039e0: 681b ldr r3, [r3, #0]
80039e2: f003 0301 and.w r3, r3, #1
80039e6: 2b00 cmp r3, #0
80039e8: d075 beq.n 8003ad6 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80039ea: 4b97 ldr r3, [pc, #604] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
80039ec: 689b ldr r3, [r3, #8]
80039ee: f003 030c and.w r3, r3, #12
80039f2: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
80039f4: 4b94 ldr r3, [pc, #592] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
80039f6: 68db ldr r3, [r3, #12]
80039f8: f003 0303 and.w r3, r3, #3
80039fc: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
80039fe: 69bb ldr r3, [r7, #24]
8003a00: 2b0c cmp r3, #12
8003a02: d102 bne.n 8003a0a <HAL_RCC_OscConfig+0x3e>
8003a04: 697b ldr r3, [r7, #20]
8003a06: 2b03 cmp r3, #3
8003a08: d002 beq.n 8003a10 <HAL_RCC_OscConfig+0x44>
8003a0a: 69bb ldr r3, [r7, #24]
8003a0c: 2b08 cmp r3, #8
8003a0e: d10b bne.n 8003a28 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003a10: 4b8d ldr r3, [pc, #564] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a12: 681b ldr r3, [r3, #0]
8003a14: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003a18: 2b00 cmp r3, #0
8003a1a: d05b beq.n 8003ad4 <HAL_RCC_OscConfig+0x108>
8003a1c: 687b ldr r3, [r7, #4]
8003a1e: 685b ldr r3, [r3, #4]
8003a20: 2b00 cmp r3, #0
8003a22: d157 bne.n 8003ad4 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8003a24: 2301 movs r3, #1
8003a26: e2d9 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 685b ldr r3, [r3, #4]
8003a2c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003a30: d106 bne.n 8003a40 <HAL_RCC_OscConfig+0x74>
8003a32: 4b85 ldr r3, [pc, #532] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a34: 681b ldr r3, [r3, #0]
8003a36: 4a84 ldr r2, [pc, #528] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a38: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003a3c: 6013 str r3, [r2, #0]
8003a3e: e01d b.n 8003a7c <HAL_RCC_OscConfig+0xb0>
8003a40: 687b ldr r3, [r7, #4]
8003a42: 685b ldr r3, [r3, #4]
8003a44: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8003a48: d10c bne.n 8003a64 <HAL_RCC_OscConfig+0x98>
8003a4a: 4b7f ldr r3, [pc, #508] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a4c: 681b ldr r3, [r3, #0]
8003a4e: 4a7e ldr r2, [pc, #504] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a50: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8003a54: 6013 str r3, [r2, #0]
8003a56: 4b7c ldr r3, [pc, #496] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a58: 681b ldr r3, [r3, #0]
8003a5a: 4a7b ldr r2, [pc, #492] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a5c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003a60: 6013 str r3, [r2, #0]
8003a62: e00b b.n 8003a7c <HAL_RCC_OscConfig+0xb0>
8003a64: 4b78 ldr r3, [pc, #480] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a66: 681b ldr r3, [r3, #0]
8003a68: 4a77 ldr r2, [pc, #476] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a6a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003a6e: 6013 str r3, [r2, #0]
8003a70: 4b75 ldr r3, [pc, #468] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a72: 681b ldr r3, [r3, #0]
8003a74: 4a74 ldr r2, [pc, #464] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003a76: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8003a7a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8003a7c: 687b ldr r3, [r7, #4]
8003a7e: 685b ldr r3, [r3, #4]
8003a80: 2b00 cmp r3, #0
8003a82: d013 beq.n 8003aac <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003a84: f7fd feba bl 80017fc <HAL_GetTick>
8003a88: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003a8a: e008 b.n 8003a9e <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8003a8c: f7fd feb6 bl 80017fc <HAL_GetTick>
8003a90: 4602 mov r2, r0
8003a92: 693b ldr r3, [r7, #16]
8003a94: 1ad3 subs r3, r2, r3
8003a96: 2b64 cmp r3, #100 @ 0x64
8003a98: d901 bls.n 8003a9e <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8003a9a: 2303 movs r3, #3
8003a9c: e29e b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003a9e: 4b6a ldr r3, [pc, #424] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003aa0: 681b ldr r3, [r3, #0]
8003aa2: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003aa6: 2b00 cmp r3, #0
8003aa8: d0f0 beq.n 8003a8c <HAL_RCC_OscConfig+0xc0>
8003aaa: e014 b.n 8003ad6 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003aac: f7fd fea6 bl 80017fc <HAL_GetTick>
8003ab0: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8003ab2: e008 b.n 8003ac6 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8003ab4: f7fd fea2 bl 80017fc <HAL_GetTick>
8003ab8: 4602 mov r2, r0
8003aba: 693b ldr r3, [r7, #16]
8003abc: 1ad3 subs r3, r2, r3
8003abe: 2b64 cmp r3, #100 @ 0x64
8003ac0: d901 bls.n 8003ac6 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8003ac2: 2303 movs r3, #3
8003ac4: e28a b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8003ac6: 4b60 ldr r3, [pc, #384] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003ac8: 681b ldr r3, [r3, #0]
8003aca: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003ace: 2b00 cmp r3, #0
8003ad0: d1f0 bne.n 8003ab4 <HAL_RCC_OscConfig+0xe8>
8003ad2: e000 b.n 8003ad6 <HAL_RCC_OscConfig+0x10a>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003ad4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003ad6: 687b ldr r3, [r7, #4]
8003ad8: 681b ldr r3, [r3, #0]
8003ada: f003 0302 and.w r3, r3, #2
8003ade: 2b00 cmp r3, #0
8003ae0: d075 beq.n 8003bce <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003ae2: 4b59 ldr r3, [pc, #356] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003ae4: 689b ldr r3, [r3, #8]
8003ae6: f003 030c and.w r3, r3, #12
8003aea: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8003aec: 4b56 ldr r3, [pc, #344] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003aee: 68db ldr r3, [r3, #12]
8003af0: f003 0303 and.w r3, r3, #3
8003af4: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
8003af6: 69bb ldr r3, [r7, #24]
8003af8: 2b0c cmp r3, #12
8003afa: d102 bne.n 8003b02 <HAL_RCC_OscConfig+0x136>
8003afc: 697b ldr r3, [r7, #20]
8003afe: 2b02 cmp r3, #2
8003b00: d002 beq.n 8003b08 <HAL_RCC_OscConfig+0x13c>
8003b02: 69bb ldr r3, [r7, #24]
8003b04: 2b04 cmp r3, #4
8003b06: d11f bne.n 8003b48 <HAL_RCC_OscConfig+0x17c>
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003b08: 4b4f ldr r3, [pc, #316] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b0a: 681b ldr r3, [r3, #0]
8003b0c: f403 6380 and.w r3, r3, #1024 @ 0x400
8003b10: 2b00 cmp r3, #0
8003b12: d005 beq.n 8003b20 <HAL_RCC_OscConfig+0x154>
8003b14: 687b ldr r3, [r7, #4]
8003b16: 68db ldr r3, [r3, #12]
8003b18: 2b00 cmp r3, #0
8003b1a: d101 bne.n 8003b20 <HAL_RCC_OscConfig+0x154>
{
return HAL_ERROR;
8003b1c: 2301 movs r3, #1
8003b1e: e25d b.n 8003fdc <HAL_RCC_OscConfig+0x610>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003b20: 4b49 ldr r3, [pc, #292] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b22: 685b ldr r3, [r3, #4]
8003b24: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
8003b28: 687b ldr r3, [r7, #4]
8003b2a: 691b ldr r3, [r3, #16]
8003b2c: 061b lsls r3, r3, #24
8003b2e: 4946 ldr r1, [pc, #280] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b30: 4313 orrs r3, r2
8003b32: 604b str r3, [r1, #4]
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8003b34: 4b45 ldr r3, [pc, #276] @ (8003c4c <HAL_RCC_OscConfig+0x280>)
8003b36: 681b ldr r3, [r3, #0]
8003b38: 4618 mov r0, r3
8003b3a: f7fd fe13 bl 8001764 <HAL_InitTick>
8003b3e: 4603 mov r3, r0
8003b40: 2b00 cmp r3, #0
8003b42: d043 beq.n 8003bcc <HAL_RCC_OscConfig+0x200>
{
return HAL_ERROR;
8003b44: 2301 movs r3, #1
8003b46: e249 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 68db ldr r3, [r3, #12]
8003b4c: 2b00 cmp r3, #0
8003b4e: d023 beq.n 8003b98 <HAL_RCC_OscConfig+0x1cc>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8003b50: 4b3d ldr r3, [pc, #244] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b52: 681b ldr r3, [r3, #0]
8003b54: 4a3c ldr r2, [pc, #240] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b56: f443 7380 orr.w r3, r3, #256 @ 0x100
8003b5a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b5c: f7fd fe4e bl 80017fc <HAL_GetTick>
8003b60: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003b62: e008 b.n 8003b76 <HAL_RCC_OscConfig+0x1aa>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003b64: f7fd fe4a bl 80017fc <HAL_GetTick>
8003b68: 4602 mov r2, r0
8003b6a: 693b ldr r3, [r7, #16]
8003b6c: 1ad3 subs r3, r2, r3
8003b6e: 2b02 cmp r3, #2
8003b70: d901 bls.n 8003b76 <HAL_RCC_OscConfig+0x1aa>
{
return HAL_TIMEOUT;
8003b72: 2303 movs r3, #3
8003b74: e232 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003b76: 4b34 ldr r3, [pc, #208] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b78: 681b ldr r3, [r3, #0]
8003b7a: f403 6380 and.w r3, r3, #1024 @ 0x400
8003b7e: 2b00 cmp r3, #0
8003b80: d0f0 beq.n 8003b64 <HAL_RCC_OscConfig+0x198>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003b82: 4b31 ldr r3, [pc, #196] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b84: 685b ldr r3, [r3, #4]
8003b86: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
8003b8a: 687b ldr r3, [r7, #4]
8003b8c: 691b ldr r3, [r3, #16]
8003b8e: 061b lsls r3, r3, #24
8003b90: 492d ldr r1, [pc, #180] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b92: 4313 orrs r3, r2
8003b94: 604b str r3, [r1, #4]
8003b96: e01a b.n 8003bce <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8003b98: 4b2b ldr r3, [pc, #172] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b9a: 681b ldr r3, [r3, #0]
8003b9c: 4a2a ldr r2, [pc, #168] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003b9e: f423 7380 bic.w r3, r3, #256 @ 0x100
8003ba2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ba4: f7fd fe2a bl 80017fc <HAL_GetTick>
8003ba8: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003baa: e008 b.n 8003bbe <HAL_RCC_OscConfig+0x1f2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003bac: f7fd fe26 bl 80017fc <HAL_GetTick>
8003bb0: 4602 mov r2, r0
8003bb2: 693b ldr r3, [r7, #16]
8003bb4: 1ad3 subs r3, r2, r3
8003bb6: 2b02 cmp r3, #2
8003bb8: d901 bls.n 8003bbe <HAL_RCC_OscConfig+0x1f2>
{
return HAL_TIMEOUT;
8003bba: 2303 movs r3, #3
8003bbc: e20e b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003bbe: 4b22 ldr r3, [pc, #136] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003bc0: 681b ldr r3, [r3, #0]
8003bc2: f403 6380 and.w r3, r3, #1024 @ 0x400
8003bc6: 2b00 cmp r3, #0
8003bc8: d1f0 bne.n 8003bac <HAL_RCC_OscConfig+0x1e0>
8003bca: e000 b.n 8003bce <HAL_RCC_OscConfig+0x202>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003bcc: bf00 nop
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003bce: 687b ldr r3, [r7, #4]
8003bd0: 681b ldr r3, [r3, #0]
8003bd2: f003 0308 and.w r3, r3, #8
8003bd6: 2b00 cmp r3, #0
8003bd8: d041 beq.n 8003c5e <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8003bda: 687b ldr r3, [r7, #4]
8003bdc: 695b ldr r3, [r3, #20]
8003bde: 2b00 cmp r3, #0
8003be0: d01c beq.n 8003c1c <HAL_RCC_OscConfig+0x250>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8003be2: 4b19 ldr r3, [pc, #100] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003be4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8003be8: 4a17 ldr r2, [pc, #92] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003bea: f043 0301 orr.w r3, r3, #1
8003bee: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003bf2: f7fd fe03 bl 80017fc <HAL_GetTick>
8003bf6: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003bf8: e008 b.n 8003c0c <HAL_RCC_OscConfig+0x240>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003bfa: f7fd fdff bl 80017fc <HAL_GetTick>
8003bfe: 4602 mov r2, r0
8003c00: 693b ldr r3, [r7, #16]
8003c02: 1ad3 subs r3, r2, r3
8003c04: 2b02 cmp r3, #2
8003c06: d901 bls.n 8003c0c <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
8003c08: 2303 movs r3, #3
8003c0a: e1e7 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003c0c: 4b0e ldr r3, [pc, #56] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003c0e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8003c12: f003 0302 and.w r3, r3, #2
8003c16: 2b00 cmp r3, #0
8003c18: d0ef beq.n 8003bfa <HAL_RCC_OscConfig+0x22e>
8003c1a: e020 b.n 8003c5e <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003c1c: 4b0a ldr r3, [pc, #40] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003c1e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8003c22: 4a09 ldr r2, [pc, #36] @ (8003c48 <HAL_RCC_OscConfig+0x27c>)
8003c24: f023 0301 bic.w r3, r3, #1
8003c28: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003c2c: f7fd fde6 bl 80017fc <HAL_GetTick>
8003c30: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003c32: e00d b.n 8003c50 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003c34: f7fd fde2 bl 80017fc <HAL_GetTick>
8003c38: 4602 mov r2, r0
8003c3a: 693b ldr r3, [r7, #16]
8003c3c: 1ad3 subs r3, r2, r3
8003c3e: 2b02 cmp r3, #2
8003c40: d906 bls.n 8003c50 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8003c42: 2303 movs r3, #3
8003c44: e1ca b.n 8003fdc <HAL_RCC_OscConfig+0x610>
8003c46: bf00 nop
8003c48: 40021000 .word 0x40021000
8003c4c: 20000020 .word 0x20000020
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003c50: 4b8c ldr r3, [pc, #560] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003c52: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8003c56: f003 0302 and.w r3, r3, #2
8003c5a: 2b00 cmp r3, #0
8003c5c: d1ea bne.n 8003c34 <HAL_RCC_OscConfig+0x268>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8003c5e: 687b ldr r3, [r7, #4]
8003c60: 681b ldr r3, [r3, #0]
8003c62: f003 0304 and.w r3, r3, #4
8003c66: 2b00 cmp r3, #0
8003c68: f000 80a6 beq.w 8003db8 <HAL_RCC_OscConfig+0x3ec>
{
FlagStatus pwrclkchanged = RESET;
8003c6c: 2300 movs r3, #0
8003c6e: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain if necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8003c70: 4b84 ldr r3, [pc, #528] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003c72: 6d9b ldr r3, [r3, #88] @ 0x58
8003c74: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003c78: 2b00 cmp r3, #0
8003c7a: d101 bne.n 8003c80 <HAL_RCC_OscConfig+0x2b4>
8003c7c: 2301 movs r3, #1
8003c7e: e000 b.n 8003c82 <HAL_RCC_OscConfig+0x2b6>
8003c80: 2300 movs r3, #0
8003c82: 2b00 cmp r3, #0
8003c84: d00d beq.n 8003ca2 <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003c86: 4b7f ldr r3, [pc, #508] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003c88: 6d9b ldr r3, [r3, #88] @ 0x58
8003c8a: 4a7e ldr r2, [pc, #504] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003c8c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003c90: 6593 str r3, [r2, #88] @ 0x58
8003c92: 4b7c ldr r3, [pc, #496] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003c94: 6d9b ldr r3, [r3, #88] @ 0x58
8003c96: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003c9a: 60fb str r3, [r7, #12]
8003c9c: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8003c9e: 2301 movs r3, #1
8003ca0: 77fb strb r3, [r7, #31]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003ca2: 4b79 ldr r3, [pc, #484] @ (8003e88 <HAL_RCC_OscConfig+0x4bc>)
8003ca4: 681b ldr r3, [r3, #0]
8003ca6: f403 7380 and.w r3, r3, #256 @ 0x100
8003caa: 2b00 cmp r3, #0
8003cac: d118 bne.n 8003ce0 <HAL_RCC_OscConfig+0x314>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003cae: 4b76 ldr r3, [pc, #472] @ (8003e88 <HAL_RCC_OscConfig+0x4bc>)
8003cb0: 681b ldr r3, [r3, #0]
8003cb2: 4a75 ldr r2, [pc, #468] @ (8003e88 <HAL_RCC_OscConfig+0x4bc>)
8003cb4: f443 7380 orr.w r3, r3, #256 @ 0x100
8003cb8: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003cba: f7fd fd9f bl 80017fc <HAL_GetTick>
8003cbe: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003cc0: e008 b.n 8003cd4 <HAL_RCC_OscConfig+0x308>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003cc2: f7fd fd9b bl 80017fc <HAL_GetTick>
8003cc6: 4602 mov r2, r0
8003cc8: 693b ldr r3, [r7, #16]
8003cca: 1ad3 subs r3, r2, r3
8003ccc: 2b02 cmp r3, #2
8003cce: d901 bls.n 8003cd4 <HAL_RCC_OscConfig+0x308>
{
return HAL_TIMEOUT;
8003cd0: 2303 movs r3, #3
8003cd2: e183 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003cd4: 4b6c ldr r3, [pc, #432] @ (8003e88 <HAL_RCC_OscConfig+0x4bc>)
8003cd6: 681b ldr r3, [r3, #0]
8003cd8: f403 7380 and.w r3, r3, #256 @ 0x100
8003cdc: 2b00 cmp r3, #0
8003cde: d0f0 beq.n 8003cc2 <HAL_RCC_OscConfig+0x2f6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003ce0: 687b ldr r3, [r7, #4]
8003ce2: 689b ldr r3, [r3, #8]
8003ce4: 2b01 cmp r3, #1
8003ce6: d108 bne.n 8003cfa <HAL_RCC_OscConfig+0x32e>
8003ce8: 4b66 ldr r3, [pc, #408] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003cea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003cee: 4a65 ldr r2, [pc, #404] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003cf0: f043 0301 orr.w r3, r3, #1
8003cf4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8003cf8: e024 b.n 8003d44 <HAL_RCC_OscConfig+0x378>
8003cfa: 687b ldr r3, [r7, #4]
8003cfc: 689b ldr r3, [r3, #8]
8003cfe: 2b05 cmp r3, #5
8003d00: d110 bne.n 8003d24 <HAL_RCC_OscConfig+0x358>
8003d02: 4b60 ldr r3, [pc, #384] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d04: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d08: 4a5e ldr r2, [pc, #376] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d0a: f043 0304 orr.w r3, r3, #4
8003d0e: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8003d12: 4b5c ldr r3, [pc, #368] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d14: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d18: 4a5a ldr r2, [pc, #360] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d1a: f043 0301 orr.w r3, r3, #1
8003d1e: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8003d22: e00f b.n 8003d44 <HAL_RCC_OscConfig+0x378>
8003d24: 4b57 ldr r3, [pc, #348] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d26: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d2a: 4a56 ldr r2, [pc, #344] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d2c: f023 0301 bic.w r3, r3, #1
8003d30: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8003d34: 4b53 ldr r3, [pc, #332] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d36: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d3a: 4a52 ldr r2, [pc, #328] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d3c: f023 0304 bic.w r3, r3, #4
8003d40: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8003d44: 687b ldr r3, [r7, #4]
8003d46: 689b ldr r3, [r3, #8]
8003d48: 2b00 cmp r3, #0
8003d4a: d016 beq.n 8003d7a <HAL_RCC_OscConfig+0x3ae>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d4c: f7fd fd56 bl 80017fc <HAL_GetTick>
8003d50: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003d52: e00a b.n 8003d6a <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003d54: f7fd fd52 bl 80017fc <HAL_GetTick>
8003d58: 4602 mov r2, r0
8003d5a: 693b ldr r3, [r7, #16]
8003d5c: 1ad3 subs r3, r2, r3
8003d5e: f241 3288 movw r2, #5000 @ 0x1388
8003d62: 4293 cmp r3, r2
8003d64: d901 bls.n 8003d6a <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
8003d66: 2303 movs r3, #3
8003d68: e138 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003d6a: 4b46 ldr r3, [pc, #280] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d6c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d70: f003 0302 and.w r3, r3, #2
8003d74: 2b00 cmp r3, #0
8003d76: d0ed beq.n 8003d54 <HAL_RCC_OscConfig+0x388>
8003d78: e015 b.n 8003da6 <HAL_RCC_OscConfig+0x3da>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d7a: f7fd fd3f bl 80017fc <HAL_GetTick>
8003d7e: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003d80: e00a b.n 8003d98 <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003d82: f7fd fd3b bl 80017fc <HAL_GetTick>
8003d86: 4602 mov r2, r0
8003d88: 693b ldr r3, [r7, #16]
8003d8a: 1ad3 subs r3, r2, r3
8003d8c: f241 3288 movw r2, #5000 @ 0x1388
8003d90: 4293 cmp r3, r2
8003d92: d901 bls.n 8003d98 <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
8003d94: 2303 movs r3, #3
8003d96: e121 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003d98: 4b3a ldr r3, [pc, #232] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003d9a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8003d9e: f003 0302 and.w r3, r3, #2
8003da2: 2b00 cmp r3, #0
8003da4: d1ed bne.n 8003d82 <HAL_RCC_OscConfig+0x3b6>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8003da6: 7ffb ldrb r3, [r7, #31]
8003da8: 2b01 cmp r3, #1
8003daa: d105 bne.n 8003db8 <HAL_RCC_OscConfig+0x3ec>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003dac: 4b35 ldr r3, [pc, #212] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003dae: 6d9b ldr r3, [r3, #88] @ 0x58
8003db0: 4a34 ldr r2, [pc, #208] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003db2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8003db6: 6593 str r3, [r2, #88] @ 0x58
}
}
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
8003db8: 687b ldr r3, [r7, #4]
8003dba: 681b ldr r3, [r3, #0]
8003dbc: f003 0320 and.w r3, r3, #32
8003dc0: 2b00 cmp r3, #0
8003dc2: d03c beq.n 8003e3e <HAL_RCC_OscConfig+0x472>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
8003dc4: 687b ldr r3, [r7, #4]
8003dc6: 699b ldr r3, [r3, #24]
8003dc8: 2b00 cmp r3, #0
8003dca: d01c beq.n 8003e06 <HAL_RCC_OscConfig+0x43a>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8003dcc: 4b2d ldr r3, [pc, #180] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003dce: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8003dd2: 4a2c ldr r2, [pc, #176] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003dd4: f043 0301 orr.w r3, r3, #1
8003dd8: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ddc: f7fd fd0e bl 80017fc <HAL_GetTick>
8003de0: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8003de2: e008 b.n 8003df6 <HAL_RCC_OscConfig+0x42a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8003de4: f7fd fd0a bl 80017fc <HAL_GetTick>
8003de8: 4602 mov r2, r0
8003dea: 693b ldr r3, [r7, #16]
8003dec: 1ad3 subs r3, r2, r3
8003dee: 2b02 cmp r3, #2
8003df0: d901 bls.n 8003df6 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8003df2: 2303 movs r3, #3
8003df4: e0f2 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
8003df6: 4b23 ldr r3, [pc, #140] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003df8: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8003dfc: f003 0302 and.w r3, r3, #2
8003e00: 2b00 cmp r3, #0
8003e02: d0ef beq.n 8003de4 <HAL_RCC_OscConfig+0x418>
8003e04: e01b b.n 8003e3e <HAL_RCC_OscConfig+0x472>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
8003e06: 4b1f ldr r3, [pc, #124] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003e08: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8003e0c: 4a1d ldr r2, [pc, #116] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003e0e: f023 0301 bic.w r3, r3, #1
8003e12: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e16: f7fd fcf1 bl 80017fc <HAL_GetTick>
8003e1a: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8003e1c: e008 b.n 8003e30 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8003e1e: f7fd fced bl 80017fc <HAL_GetTick>
8003e22: 4602 mov r2, r0
8003e24: 693b ldr r3, [r7, #16]
8003e26: 1ad3 subs r3, r2, r3
8003e28: 2b02 cmp r3, #2
8003e2a: d901 bls.n 8003e30 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
8003e2c: 2303 movs r3, #3
8003e2e: e0d5 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8003e30: 4b14 ldr r3, [pc, #80] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003e32: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8003e36: f003 0302 and.w r3, r3, #2
8003e3a: 2b00 cmp r3, #0
8003e3c: d1ef bne.n 8003e1e <HAL_RCC_OscConfig+0x452>
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8003e3e: 687b ldr r3, [r7, #4]
8003e40: 69db ldr r3, [r3, #28]
8003e42: 2b00 cmp r3, #0
8003e44: f000 80c9 beq.w 8003fda <HAL_RCC_OscConfig+0x60e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8003e48: 4b0e ldr r3, [pc, #56] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003e4a: 689b ldr r3, [r3, #8]
8003e4c: f003 030c and.w r3, r3, #12
8003e50: 2b0c cmp r3, #12
8003e52: f000 8083 beq.w 8003f5c <HAL_RCC_OscConfig+0x590>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8003e56: 687b ldr r3, [r7, #4]
8003e58: 69db ldr r3, [r3, #28]
8003e5a: 2b02 cmp r3, #2
8003e5c: d15e bne.n 8003f1c <HAL_RCC_OscConfig+0x550>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003e5e: 4b09 ldr r3, [pc, #36] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003e60: 681b ldr r3, [r3, #0]
8003e62: 4a08 ldr r2, [pc, #32] @ (8003e84 <HAL_RCC_OscConfig+0x4b8>)
8003e64: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8003e68: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e6a: f7fd fcc7 bl 80017fc <HAL_GetTick>
8003e6e: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003e70: e00c b.n 8003e8c <HAL_RCC_OscConfig+0x4c0>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003e72: f7fd fcc3 bl 80017fc <HAL_GetTick>
8003e76: 4602 mov r2, r0
8003e78: 693b ldr r3, [r7, #16]
8003e7a: 1ad3 subs r3, r2, r3
8003e7c: 2b02 cmp r3, #2
8003e7e: d905 bls.n 8003e8c <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
8003e80: 2303 movs r3, #3
8003e82: e0ab b.n 8003fdc <HAL_RCC_OscConfig+0x610>
8003e84: 40021000 .word 0x40021000
8003e88: 40007000 .word 0x40007000
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003e8c: 4b55 ldr r3, [pc, #340] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003e8e: 681b ldr r3, [r3, #0]
8003e90: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003e94: 2b00 cmp r3, #0
8003e96: d1ec bne.n 8003e72 <HAL_RCC_OscConfig+0x4a6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8003e98: 4b52 ldr r3, [pc, #328] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003e9a: 68da ldr r2, [r3, #12]
8003e9c: 4b52 ldr r3, [pc, #328] @ (8003fe8 <HAL_RCC_OscConfig+0x61c>)
8003e9e: 4013 ands r3, r2
8003ea0: 687a ldr r2, [r7, #4]
8003ea2: 6a11 ldr r1, [r2, #32]
8003ea4: 687a ldr r2, [r7, #4]
8003ea6: 6a52 ldr r2, [r2, #36] @ 0x24
8003ea8: 3a01 subs r2, #1
8003eaa: 0112 lsls r2, r2, #4
8003eac: 4311 orrs r1, r2
8003eae: 687a ldr r2, [r7, #4]
8003eb0: 6a92 ldr r2, [r2, #40] @ 0x28
8003eb2: 0212 lsls r2, r2, #8
8003eb4: 4311 orrs r1, r2
8003eb6: 687a ldr r2, [r7, #4]
8003eb8: 6b12 ldr r2, [r2, #48] @ 0x30
8003eba: 0852 lsrs r2, r2, #1
8003ebc: 3a01 subs r2, #1
8003ebe: 0552 lsls r2, r2, #21
8003ec0: 4311 orrs r1, r2
8003ec2: 687a ldr r2, [r7, #4]
8003ec4: 6b52 ldr r2, [r2, #52] @ 0x34
8003ec6: 0852 lsrs r2, r2, #1
8003ec8: 3a01 subs r2, #1
8003eca: 0652 lsls r2, r2, #25
8003ecc: 4311 orrs r1, r2
8003ece: 687a ldr r2, [r7, #4]
8003ed0: 6ad2 ldr r2, [r2, #44] @ 0x2c
8003ed2: 06d2 lsls r2, r2, #27
8003ed4: 430a orrs r2, r1
8003ed6: 4943 ldr r1, [pc, #268] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003ed8: 4313 orrs r3, r2
8003eda: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8003edc: 4b41 ldr r3, [pc, #260] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003ede: 681b ldr r3, [r3, #0]
8003ee0: 4a40 ldr r2, [pc, #256] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003ee2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8003ee6: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
8003ee8: 4b3e ldr r3, [pc, #248] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003eea: 68db ldr r3, [r3, #12]
8003eec: 4a3d ldr r2, [pc, #244] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003eee: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8003ef2: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ef4: f7fd fc82 bl 80017fc <HAL_GetTick>
8003ef8: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003efa: e008 b.n 8003f0e <HAL_RCC_OscConfig+0x542>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003efc: f7fd fc7e bl 80017fc <HAL_GetTick>
8003f00: 4602 mov r2, r0
8003f02: 693b ldr r3, [r7, #16]
8003f04: 1ad3 subs r3, r2, r3
8003f06: 2b02 cmp r3, #2
8003f08: d901 bls.n 8003f0e <HAL_RCC_OscConfig+0x542>
{
return HAL_TIMEOUT;
8003f0a: 2303 movs r3, #3
8003f0c: e066 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003f0e: 4b35 ldr r3, [pc, #212] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f10: 681b ldr r3, [r3, #0]
8003f12: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003f16: 2b00 cmp r3, #0
8003f18: d0f0 beq.n 8003efc <HAL_RCC_OscConfig+0x530>
8003f1a: e05e b.n 8003fda <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003f1c: 4b31 ldr r3, [pc, #196] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f1e: 681b ldr r3, [r3, #0]
8003f20: 4a30 ldr r2, [pc, #192] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f22: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8003f26: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003f28: f7fd fc68 bl 80017fc <HAL_GetTick>
8003f2c: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003f2e: e008 b.n 8003f42 <HAL_RCC_OscConfig+0x576>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003f30: f7fd fc64 bl 80017fc <HAL_GetTick>
8003f34: 4602 mov r2, r0
8003f36: 693b ldr r3, [r7, #16]
8003f38: 1ad3 subs r3, r2, r3
8003f3a: 2b02 cmp r3, #2
8003f3c: d901 bls.n 8003f42 <HAL_RCC_OscConfig+0x576>
{
return HAL_TIMEOUT;
8003f3e: 2303 movs r3, #3
8003f40: e04c b.n 8003fdc <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003f42: 4b28 ldr r3, [pc, #160] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f44: 681b ldr r3, [r3, #0]
8003f46: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003f4a: 2b00 cmp r3, #0
8003f4c: d1f0 bne.n 8003f30 <HAL_RCC_OscConfig+0x564>
}
}
/* Unselect PLL clock source and disable outputs to save power */
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
8003f4e: 4b25 ldr r3, [pc, #148] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f50: 68da ldr r2, [r3, #12]
8003f52: 4924 ldr r1, [pc, #144] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f54: 4b25 ldr r3, [pc, #148] @ (8003fec <HAL_RCC_OscConfig+0x620>)
8003f56: 4013 ands r3, r2
8003f58: 60cb str r3, [r1, #12]
8003f5a: e03e b.n 8003fda <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003f5c: 687b ldr r3, [r7, #4]
8003f5e: 69db ldr r3, [r3, #28]
8003f60: 2b01 cmp r3, #1
8003f62: d101 bne.n 8003f68 <HAL_RCC_OscConfig+0x59c>
{
return HAL_ERROR;
8003f64: 2301 movs r3, #1
8003f66: e039 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8003f68: 4b1e ldr r3, [pc, #120] @ (8003fe4 <HAL_RCC_OscConfig+0x618>)
8003f6a: 68db ldr r3, [r3, #12]
8003f6c: 617b str r3, [r7, #20]
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003f6e: 697b ldr r3, [r7, #20]
8003f70: f003 0203 and.w r2, r3, #3
8003f74: 687b ldr r3, [r7, #4]
8003f76: 6a1b ldr r3, [r3, #32]
8003f78: 429a cmp r2, r3
8003f7a: d12c bne.n 8003fd6 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8003f7c: 697b ldr r3, [r7, #20]
8003f7e: f003 02f0 and.w r2, r3, #240 @ 0xf0
8003f82: 687b ldr r3, [r7, #4]
8003f84: 6a5b ldr r3, [r3, #36] @ 0x24
8003f86: 3b01 subs r3, #1
8003f88: 011b lsls r3, r3, #4
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003f8a: 429a cmp r2, r3
8003f8c: d123 bne.n 8003fd6 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8003f8e: 697b ldr r3, [r7, #20]
8003f90: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8003f94: 687b ldr r3, [r7, #4]
8003f96: 6a9b ldr r3, [r3, #40] @ 0x28
8003f98: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8003f9a: 429a cmp r2, r3
8003f9c: d11b bne.n 8003fd6 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8003f9e: 697b ldr r3, [r7, #20]
8003fa0: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
8003fa4: 687b ldr r3, [r7, #4]
8003fa6: 6adb ldr r3, [r3, #44] @ 0x2c
8003fa8: 06db lsls r3, r3, #27
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8003faa: 429a cmp r2, r3
8003fac: d113 bne.n 8003fd6 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8003fae: 697b ldr r3, [r7, #20]
8003fb0: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 6b1b ldr r3, [r3, #48] @ 0x30
8003fb8: 085b lsrs r3, r3, #1
8003fba: 3b01 subs r3, #1
8003fbc: 055b lsls r3, r3, #21
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8003fbe: 429a cmp r2, r3
8003fc0: d109 bne.n 8003fd6 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8003fc2: 697b ldr r3, [r7, #20]
8003fc4: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
8003fc8: 687b ldr r3, [r7, #4]
8003fca: 6b5b ldr r3, [r3, #52] @ 0x34
8003fcc: 085b lsrs r3, r3, #1
8003fce: 3b01 subs r3, #1
8003fd0: 065b lsls r3, r3, #25
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8003fd2: 429a cmp r2, r3
8003fd4: d001 beq.n 8003fda <HAL_RCC_OscConfig+0x60e>
{
return HAL_ERROR;
8003fd6: 2301 movs r3, #1
8003fd8: e000 b.n 8003fdc <HAL_RCC_OscConfig+0x610>
}
}
}
}
return HAL_OK;
8003fda: 2300 movs r3, #0
}
8003fdc: 4618 mov r0, r3
8003fde: 3720 adds r7, #32
8003fe0: 46bd mov sp, r7
8003fe2: bd80 pop {r7, pc}
8003fe4: 40021000 .word 0x40021000
8003fe8: 019f800c .word 0x019f800c
8003fec: feeefffc .word 0xfeeefffc
08003ff0 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003ff0: b580 push {r7, lr}
8003ff2: b086 sub sp, #24
8003ff4: af00 add r7, sp, #0
8003ff6: 6078 str r0, [r7, #4]
8003ff8: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
8003ffa: 2300 movs r3, #0
8003ffc: 617b str r3, [r7, #20]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8003ffe: 687b ldr r3, [r7, #4]
8004000: 2b00 cmp r3, #0
8004002: d101 bne.n 8004008 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8004004: 2301 movs r3, #1
8004006: e11e b.n 8004246 <HAL_RCC_ClockConfig+0x256>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8004008: 4b91 ldr r3, [pc, #580] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
800400a: 681b ldr r3, [r3, #0]
800400c: f003 030f and.w r3, r3, #15
8004010: 683a ldr r2, [r7, #0]
8004012: 429a cmp r2, r3
8004014: d910 bls.n 8004038 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004016: 4b8e ldr r3, [pc, #568] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
8004018: 681b ldr r3, [r3, #0]
800401a: f023 020f bic.w r2, r3, #15
800401e: 498c ldr r1, [pc, #560] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
8004020: 683b ldr r3, [r7, #0]
8004022: 4313 orrs r3, r2
8004024: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8004026: 4b8a ldr r3, [pc, #552] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
8004028: 681b ldr r3, [r3, #0]
800402a: f003 030f and.w r3, r3, #15
800402e: 683a ldr r2, [r7, #0]
8004030: 429a cmp r2, r3
8004032: d001 beq.n 8004038 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8004034: 2301 movs r3, #1
8004036: e106 b.n 8004246 <HAL_RCC_ClockConfig+0x256>
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8004038: 687b ldr r3, [r7, #4]
800403a: 681b ldr r3, [r3, #0]
800403c: f003 0301 and.w r3, r3, #1
8004040: 2b00 cmp r3, #0
8004042: d073 beq.n 800412c <HAL_RCC_ClockConfig+0x13c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8004044: 687b ldr r3, [r7, #4]
8004046: 685b ldr r3, [r3, #4]
8004048: 2b03 cmp r3, #3
800404a: d129 bne.n 80040a0 <HAL_RCC_ClockConfig+0xb0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800404c: 4b81 ldr r3, [pc, #516] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800404e: 681b ldr r3, [r3, #0]
8004050: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004054: 2b00 cmp r3, #0
8004056: d101 bne.n 800405c <HAL_RCC_ClockConfig+0x6c>
{
return HAL_ERROR;
8004058: 2301 movs r3, #1
800405a: e0f4 b.n 8004246 <HAL_RCC_ClockConfig+0x256>
}
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
/* Compute target PLL output frequency */
pllfreq = RCC_GetSysClockFreqFromPLLSource();
800405c: f000 f99e bl 800439c <RCC_GetSysClockFreqFromPLLSource>
8004060: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(pllfreq > 80000000U)
8004062: 693b ldr r3, [r7, #16]
8004064: 4a7c ldr r2, [pc, #496] @ (8004258 <HAL_RCC_ClockConfig+0x268>)
8004066: 4293 cmp r3, r2
8004068: d93f bls.n 80040ea <HAL_RCC_ClockConfig+0xfa>
{
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
800406a: 4b7a ldr r3, [pc, #488] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800406c: 689b ldr r3, [r3, #8]
800406e: f003 03f0 and.w r3, r3, #240 @ 0xf0
8004072: 2b00 cmp r3, #0
8004074: d009 beq.n 800408a <HAL_RCC_ClockConfig+0x9a>
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8004076: 687b ldr r3, [r7, #4]
8004078: 681b ldr r3, [r3, #0]
800407a: f003 0302 and.w r3, r3, #2
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
800407e: 2b00 cmp r3, #0
8004080: d033 beq.n 80040ea <HAL_RCC_ClockConfig+0xfa>
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
8004082: 687b ldr r3, [r7, #4]
8004084: 689b ldr r3, [r3, #8]
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8004086: 2b00 cmp r3, #0
8004088: d12f bne.n 80040ea <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
800408a: 4b72 ldr r3, [pc, #456] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800408c: 689b ldr r3, [r3, #8]
800408e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8004092: 4a70 ldr r2, [pc, #448] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004094: f043 0380 orr.w r3, r3, #128 @ 0x80
8004098: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
800409a: 2380 movs r3, #128 @ 0x80
800409c: 617b str r3, [r7, #20]
800409e: e024 b.n 80040ea <HAL_RCC_ClockConfig+0xfa>
}
}
else
{
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80040a0: 687b ldr r3, [r7, #4]
80040a2: 685b ldr r3, [r3, #4]
80040a4: 2b02 cmp r3, #2
80040a6: d107 bne.n 80040b8 <HAL_RCC_ClockConfig+0xc8>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80040a8: 4b6a ldr r3, [pc, #424] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80040aa: 681b ldr r3, [r3, #0]
80040ac: f403 3300 and.w r3, r3, #131072 @ 0x20000
80040b0: 2b00 cmp r3, #0
80040b2: d109 bne.n 80040c8 <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
80040b4: 2301 movs r3, #1
80040b6: e0c6 b.n 8004246 <HAL_RCC_ClockConfig+0x256>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
80040b8: 4b66 ldr r3, [pc, #408] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80040ba: 681b ldr r3, [r3, #0]
80040bc: f403 6380 and.w r3, r3, #1024 @ 0x400
80040c0: 2b00 cmp r3, #0
80040c2: d101 bne.n 80040c8 <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
80040c4: 2301 movs r3, #1
80040c6: e0be b.n 8004246 <HAL_RCC_ClockConfig+0x256>
}
}
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
pllfreq = HAL_RCC_GetSysClockFreq();
80040c8: f000 f8ce bl 8004268 <HAL_RCC_GetSysClockFreq>
80040cc: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(pllfreq > 80000000U)
80040ce: 693b ldr r3, [r7, #16]
80040d0: 4a61 ldr r2, [pc, #388] @ (8004258 <HAL_RCC_ClockConfig+0x268>)
80040d2: 4293 cmp r3, r2
80040d4: d909 bls.n 80040ea <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
80040d6: 4b5f ldr r3, [pc, #380] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80040d8: 689b ldr r3, [r3, #8]
80040da: f023 03f0 bic.w r3, r3, #240 @ 0xf0
80040de: 4a5d ldr r2, [pc, #372] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80040e0: f043 0380 orr.w r3, r3, #128 @ 0x80
80040e4: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
80040e6: 2380 movs r3, #128 @ 0x80
80040e8: 617b str r3, [r7, #20]
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80040ea: 4b5a ldr r3, [pc, #360] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80040ec: 689b ldr r3, [r3, #8]
80040ee: f023 0203 bic.w r2, r3, #3
80040f2: 687b ldr r3, [r7, #4]
80040f4: 685b ldr r3, [r3, #4]
80040f6: 4957 ldr r1, [pc, #348] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80040f8: 4313 orrs r3, r2
80040fa: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80040fc: f7fd fb7e bl 80017fc <HAL_GetTick>
8004100: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004102: e00a b.n 800411a <HAL_RCC_ClockConfig+0x12a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004104: f7fd fb7a bl 80017fc <HAL_GetTick>
8004108: 4602 mov r2, r0
800410a: 68fb ldr r3, [r7, #12]
800410c: 1ad3 subs r3, r2, r3
800410e: f241 3288 movw r2, #5000 @ 0x1388
8004112: 4293 cmp r3, r2
8004114: d901 bls.n 800411a <HAL_RCC_ClockConfig+0x12a>
{
return HAL_TIMEOUT;
8004116: 2303 movs r3, #3
8004118: e095 b.n 8004246 <HAL_RCC_ClockConfig+0x256>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800411a: 4b4e ldr r3, [pc, #312] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800411c: 689b ldr r3, [r3, #8]
800411e: f003 020c and.w r2, r3, #12
8004122: 687b ldr r3, [r7, #4]
8004124: 685b ldr r3, [r3, #4]
8004126: 009b lsls r3, r3, #2
8004128: 429a cmp r2, r3
800412a: d1eb bne.n 8004104 <HAL_RCC_ClockConfig+0x114>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800412c: 687b ldr r3, [r7, #4]
800412e: 681b ldr r3, [r3, #0]
8004130: f003 0302 and.w r3, r3, #2
8004134: 2b00 cmp r3, #0
8004136: d023 beq.n 8004180 <HAL_RCC_ClockConfig+0x190>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004138: 687b ldr r3, [r7, #4]
800413a: 681b ldr r3, [r3, #0]
800413c: f003 0304 and.w r3, r3, #4
8004140: 2b00 cmp r3, #0
8004142: d005 beq.n 8004150 <HAL_RCC_ClockConfig+0x160>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8004144: 4b43 ldr r3, [pc, #268] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004146: 689b ldr r3, [r3, #8]
8004148: 4a42 ldr r2, [pc, #264] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800414a: f443 63e0 orr.w r3, r3, #1792 @ 0x700
800414e: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004150: 687b ldr r3, [r7, #4]
8004152: 681b ldr r3, [r3, #0]
8004154: f003 0308 and.w r3, r3, #8
8004158: 2b00 cmp r3, #0
800415a: d007 beq.n 800416c <HAL_RCC_ClockConfig+0x17c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
800415c: 4b3d ldr r3, [pc, #244] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800415e: 689b ldr r3, [r3, #8]
8004160: f423 537c bic.w r3, r3, #16128 @ 0x3f00
8004164: 4a3b ldr r2, [pc, #236] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004166: f443 63e0 orr.w r3, r3, #1792 @ 0x700
800416a: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
800416c: 4b39 ldr r3, [pc, #228] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800416e: 689b ldr r3, [r3, #8]
8004170: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8004174: 687b ldr r3, [r7, #4]
8004176: 689b ldr r3, [r3, #8]
8004178: 4936 ldr r1, [pc, #216] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800417a: 4313 orrs r3, r2
800417c: 608b str r3, [r1, #8]
800417e: e008 b.n 8004192 <HAL_RCC_ClockConfig+0x1a2>
}
else
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
8004180: 697b ldr r3, [r7, #20]
8004182: 2b80 cmp r3, #128 @ 0x80
8004184: d105 bne.n 8004192 <HAL_RCC_ClockConfig+0x1a2>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
8004186: 4b33 ldr r3, [pc, #204] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004188: 689b ldr r3, [r3, #8]
800418a: 4a32 ldr r2, [pc, #200] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
800418c: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8004190: 6093 str r3, [r2, #8]
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8004192: 4b2f ldr r3, [pc, #188] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
8004194: 681b ldr r3, [r3, #0]
8004196: f003 030f and.w r3, r3, #15
800419a: 683a ldr r2, [r7, #0]
800419c: 429a cmp r2, r3
800419e: d21d bcs.n 80041dc <HAL_RCC_ClockConfig+0x1ec>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80041a0: 4b2b ldr r3, [pc, #172] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
80041a2: 681b ldr r3, [r3, #0]
80041a4: f023 020f bic.w r2, r3, #15
80041a8: 4929 ldr r1, [pc, #164] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
80041aa: 683b ldr r3, [r7, #0]
80041ac: 4313 orrs r3, r2
80041ae: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
80041b0: f7fd fb24 bl 80017fc <HAL_GetTick>
80041b4: 60f8 str r0, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
80041b6: e00a b.n 80041ce <HAL_RCC_ClockConfig+0x1de>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80041b8: f7fd fb20 bl 80017fc <HAL_GetTick>
80041bc: 4602 mov r2, r0
80041be: 68fb ldr r3, [r7, #12]
80041c0: 1ad3 subs r3, r2, r3
80041c2: f241 3288 movw r2, #5000 @ 0x1388
80041c6: 4293 cmp r3, r2
80041c8: d901 bls.n 80041ce <HAL_RCC_ClockConfig+0x1de>
{
return HAL_TIMEOUT;
80041ca: 2303 movs r3, #3
80041cc: e03b b.n 8004246 <HAL_RCC_ClockConfig+0x256>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
80041ce: 4b20 ldr r3, [pc, #128] @ (8004250 <HAL_RCC_ClockConfig+0x260>)
80041d0: 681b ldr r3, [r3, #0]
80041d2: f003 030f and.w r3, r3, #15
80041d6: 683a ldr r2, [r7, #0]
80041d8: 429a cmp r2, r3
80041da: d1ed bne.n 80041b8 <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80041dc: 687b ldr r3, [r7, #4]
80041de: 681b ldr r3, [r3, #0]
80041e0: f003 0304 and.w r3, r3, #4
80041e4: 2b00 cmp r3, #0
80041e6: d008 beq.n 80041fa <HAL_RCC_ClockConfig+0x20a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80041e8: 4b1a ldr r3, [pc, #104] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80041ea: 689b ldr r3, [r3, #8]
80041ec: f423 62e0 bic.w r2, r3, #1792 @ 0x700
80041f0: 687b ldr r3, [r7, #4]
80041f2: 68db ldr r3, [r3, #12]
80041f4: 4917 ldr r1, [pc, #92] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
80041f6: 4313 orrs r3, r2
80041f8: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80041fa: 687b ldr r3, [r7, #4]
80041fc: 681b ldr r3, [r3, #0]
80041fe: f003 0308 and.w r3, r3, #8
8004202: 2b00 cmp r3, #0
8004204: d009 beq.n 800421a <HAL_RCC_ClockConfig+0x22a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8004206: 4b13 ldr r3, [pc, #76] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004208: 689b ldr r3, [r3, #8]
800420a: f423 5260 bic.w r2, r3, #14336 @ 0x3800
800420e: 687b ldr r3, [r7, #4]
8004210: 691b ldr r3, [r3, #16]
8004212: 00db lsls r3, r3, #3
8004214: 490f ldr r1, [pc, #60] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004216: 4313 orrs r3, r2
8004218: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
800421a: f000 f825 bl 8004268 <HAL_RCC_GetSysClockFreq>
800421e: 4602 mov r2, r0
8004220: 4b0c ldr r3, [pc, #48] @ (8004254 <HAL_RCC_ClockConfig+0x264>)
8004222: 689b ldr r3, [r3, #8]
8004224: 091b lsrs r3, r3, #4
8004226: f003 030f and.w r3, r3, #15
800422a: 490c ldr r1, [pc, #48] @ (800425c <HAL_RCC_ClockConfig+0x26c>)
800422c: 5ccb ldrb r3, [r1, r3]
800422e: f003 031f and.w r3, r3, #31
8004232: fa22 f303 lsr.w r3, r2, r3
8004236: 4a0a ldr r2, [pc, #40] @ (8004260 <HAL_RCC_ClockConfig+0x270>)
8004238: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
800423a: 4b0a ldr r3, [pc, #40] @ (8004264 <HAL_RCC_ClockConfig+0x274>)
800423c: 681b ldr r3, [r3, #0]
800423e: 4618 mov r0, r3
8004240: f7fd fa90 bl 8001764 <HAL_InitTick>
8004244: 4603 mov r3, r0
}
8004246: 4618 mov r0, r3
8004248: 3718 adds r7, #24
800424a: 46bd mov sp, r7
800424c: bd80 pop {r7, pc}
800424e: bf00 nop
8004250: 40022000 .word 0x40022000
8004254: 40021000 .word 0x40021000
8004258: 04c4b400 .word 0x04c4b400
800425c: 080080ac .word 0x080080ac
8004260: 2000001c .word 0x2000001c
8004264: 20000020 .word 0x20000020
08004268 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8004268: b480 push {r7}
800426a: b087 sub sp, #28
800426c: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
800426e: 4b2c ldr r3, [pc, #176] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
8004270: 689b ldr r3, [r3, #8]
8004272: f003 030c and.w r3, r3, #12
8004276: 2b04 cmp r3, #4
8004278: d102 bne.n 8004280 <HAL_RCC_GetSysClockFreq+0x18>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
800427a: 4b2a ldr r3, [pc, #168] @ (8004324 <HAL_RCC_GetSysClockFreq+0xbc>)
800427c: 613b str r3, [r7, #16]
800427e: e047 b.n 8004310 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
8004280: 4b27 ldr r3, [pc, #156] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
8004282: 689b ldr r3, [r3, #8]
8004284: f003 030c and.w r3, r3, #12
8004288: 2b08 cmp r3, #8
800428a: d102 bne.n 8004292 <HAL_RCC_GetSysClockFreq+0x2a>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
800428c: 4b26 ldr r3, [pc, #152] @ (8004328 <HAL_RCC_GetSysClockFreq+0xc0>)
800428e: 613b str r3, [r7, #16]
8004290: e03e b.n 8004310 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
8004292: 4b23 ldr r3, [pc, #140] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
8004294: 689b ldr r3, [r3, #8]
8004296: f003 030c and.w r3, r3, #12
800429a: 2b0c cmp r3, #12
800429c: d136 bne.n 800430c <HAL_RCC_GetSysClockFreq+0xa4>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
800429e: 4b20 ldr r3, [pc, #128] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
80042a0: 68db ldr r3, [r3, #12]
80042a2: f003 0303 and.w r3, r3, #3
80042a6: 60fb str r3, [r7, #12]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
80042a8: 4b1d ldr r3, [pc, #116] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
80042aa: 68db ldr r3, [r3, #12]
80042ac: 091b lsrs r3, r3, #4
80042ae: f003 030f and.w r3, r3, #15
80042b2: 3301 adds r3, #1
80042b4: 60bb str r3, [r7, #8]
switch (pllsource)
80042b6: 68fb ldr r3, [r7, #12]
80042b8: 2b03 cmp r3, #3
80042ba: d10c bne.n 80042d6 <HAL_RCC_GetSysClockFreq+0x6e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80042bc: 4a1a ldr r2, [pc, #104] @ (8004328 <HAL_RCC_GetSysClockFreq+0xc0>)
80042be: 68bb ldr r3, [r7, #8]
80042c0: fbb2 f3f3 udiv r3, r2, r3
80042c4: 4a16 ldr r2, [pc, #88] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
80042c6: 68d2 ldr r2, [r2, #12]
80042c8: 0a12 lsrs r2, r2, #8
80042ca: f002 027f and.w r2, r2, #127 @ 0x7f
80042ce: fb02 f303 mul.w r3, r2, r3
80042d2: 617b str r3, [r7, #20]
break;
80042d4: e00c b.n 80042f0 <HAL_RCC_GetSysClockFreq+0x88>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80042d6: 4a13 ldr r2, [pc, #76] @ (8004324 <HAL_RCC_GetSysClockFreq+0xbc>)
80042d8: 68bb ldr r3, [r7, #8]
80042da: fbb2 f3f3 udiv r3, r2, r3
80042de: 4a10 ldr r2, [pc, #64] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
80042e0: 68d2 ldr r2, [r2, #12]
80042e2: 0a12 lsrs r2, r2, #8
80042e4: f002 027f and.w r2, r2, #127 @ 0x7f
80042e8: fb02 f303 mul.w r3, r2, r3
80042ec: 617b str r3, [r7, #20]
break;
80042ee: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
80042f0: 4b0b ldr r3, [pc, #44] @ (8004320 <HAL_RCC_GetSysClockFreq+0xb8>)
80042f2: 68db ldr r3, [r3, #12]
80042f4: 0e5b lsrs r3, r3, #25
80042f6: f003 0303 and.w r3, r3, #3
80042fa: 3301 adds r3, #1
80042fc: 005b lsls r3, r3, #1
80042fe: 607b str r3, [r7, #4]
sysclockfreq = pllvco/pllr;
8004300: 697a ldr r2, [r7, #20]
8004302: 687b ldr r3, [r7, #4]
8004304: fbb2 f3f3 udiv r3, r2, r3
8004308: 613b str r3, [r7, #16]
800430a: e001 b.n 8004310 <HAL_RCC_GetSysClockFreq+0xa8>
}
else
{
sysclockfreq = 0U;
800430c: 2300 movs r3, #0
800430e: 613b str r3, [r7, #16]
}
return sysclockfreq;
8004310: 693b ldr r3, [r7, #16]
}
8004312: 4618 mov r0, r3
8004314: 371c adds r7, #28
8004316: 46bd mov sp, r7
8004318: f85d 7b04 ldr.w r7, [sp], #4
800431c: 4770 bx lr
800431e: bf00 nop
8004320: 40021000 .word 0x40021000
8004324: 00f42400 .word 0x00f42400
8004328: 007a1200 .word 0x007a1200
0800432c <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800432c: b480 push {r7}
800432e: af00 add r7, sp, #0
return SystemCoreClock;
8004330: 4b03 ldr r3, [pc, #12] @ (8004340 <HAL_RCC_GetHCLKFreq+0x14>)
8004332: 681b ldr r3, [r3, #0]
}
8004334: 4618 mov r0, r3
8004336: 46bd mov sp, r7
8004338: f85d 7b04 ldr.w r7, [sp], #4
800433c: 4770 bx lr
800433e: bf00 nop
8004340: 2000001c .word 0x2000001c
08004344 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8004344: b580 push {r7, lr}
8004346: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8004348: f7ff fff0 bl 800432c <HAL_RCC_GetHCLKFreq>
800434c: 4602 mov r2, r0
800434e: 4b06 ldr r3, [pc, #24] @ (8004368 <HAL_RCC_GetPCLK1Freq+0x24>)
8004350: 689b ldr r3, [r3, #8]
8004352: 0a1b lsrs r3, r3, #8
8004354: f003 0307 and.w r3, r3, #7
8004358: 4904 ldr r1, [pc, #16] @ (800436c <HAL_RCC_GetPCLK1Freq+0x28>)
800435a: 5ccb ldrb r3, [r1, r3]
800435c: f003 031f and.w r3, r3, #31
8004360: fa22 f303 lsr.w r3, r2, r3
}
8004364: 4618 mov r0, r3
8004366: bd80 pop {r7, pc}
8004368: 40021000 .word 0x40021000
800436c: 080080bc .word 0x080080bc
08004370 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8004370: b580 push {r7, lr}
8004372: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
8004374: f7ff ffda bl 800432c <HAL_RCC_GetHCLKFreq>
8004378: 4602 mov r2, r0
800437a: 4b06 ldr r3, [pc, #24] @ (8004394 <HAL_RCC_GetPCLK2Freq+0x24>)
800437c: 689b ldr r3, [r3, #8]
800437e: 0adb lsrs r3, r3, #11
8004380: f003 0307 and.w r3, r3, #7
8004384: 4904 ldr r1, [pc, #16] @ (8004398 <HAL_RCC_GetPCLK2Freq+0x28>)
8004386: 5ccb ldrb r3, [r1, r3]
8004388: f003 031f and.w r3, r3, #31
800438c: fa22 f303 lsr.w r3, r2, r3
}
8004390: 4618 mov r0, r3
8004392: bd80 pop {r7, pc}
8004394: 40021000 .word 0x40021000
8004398: 080080bc .word 0x080080bc
0800439c <RCC_GetSysClockFreqFromPLLSource>:
/**
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
* @retval SYSCLK frequency
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
800439c: b480 push {r7}
800439e: b087 sub sp, #28
80043a0: af00 add r7, sp, #0
uint32_t sysclockfreq;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
80043a2: 4b1e ldr r3, [pc, #120] @ (800441c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80043a4: 68db ldr r3, [r3, #12]
80043a6: f003 0303 and.w r3, r3, #3
80043aa: 613b str r3, [r7, #16]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
80043ac: 4b1b ldr r3, [pc, #108] @ (800441c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80043ae: 68db ldr r3, [r3, #12]
80043b0: 091b lsrs r3, r3, #4
80043b2: f003 030f and.w r3, r3, #15
80043b6: 3301 adds r3, #1
80043b8: 60fb str r3, [r7, #12]
switch (pllsource)
80043ba: 693b ldr r3, [r7, #16]
80043bc: 2b03 cmp r3, #3
80043be: d10c bne.n 80043da <RCC_GetSysClockFreqFromPLLSource+0x3e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80043c0: 4a17 ldr r2, [pc, #92] @ (8004420 <RCC_GetSysClockFreqFromPLLSource+0x84>)
80043c2: 68fb ldr r3, [r7, #12]
80043c4: fbb2 f3f3 udiv r3, r2, r3
80043c8: 4a14 ldr r2, [pc, #80] @ (800441c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80043ca: 68d2 ldr r2, [r2, #12]
80043cc: 0a12 lsrs r2, r2, #8
80043ce: f002 027f and.w r2, r2, #127 @ 0x7f
80043d2: fb02 f303 mul.w r3, r2, r3
80043d6: 617b str r3, [r7, #20]
break;
80043d8: e00c b.n 80043f4 <RCC_GetSysClockFreqFromPLLSource+0x58>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
80043da: 4a12 ldr r2, [pc, #72] @ (8004424 <RCC_GetSysClockFreqFromPLLSource+0x88>)
80043dc: 68fb ldr r3, [r7, #12]
80043de: fbb2 f3f3 udiv r3, r2, r3
80043e2: 4a0e ldr r2, [pc, #56] @ (800441c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80043e4: 68d2 ldr r2, [r2, #12]
80043e6: 0a12 lsrs r2, r2, #8
80043e8: f002 027f and.w r2, r2, #127 @ 0x7f
80043ec: fb02 f303 mul.w r3, r2, r3
80043f0: 617b str r3, [r7, #20]
break;
80043f2: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
80043f4: 4b09 ldr r3, [pc, #36] @ (800441c <RCC_GetSysClockFreqFromPLLSource+0x80>)
80043f6: 68db ldr r3, [r3, #12]
80043f8: 0e5b lsrs r3, r3, #25
80043fa: f003 0303 and.w r3, r3, #3
80043fe: 3301 adds r3, #1
8004400: 005b lsls r3, r3, #1
8004402: 60bb str r3, [r7, #8]
sysclockfreq = pllvco/pllr;
8004404: 697a ldr r2, [r7, #20]
8004406: 68bb ldr r3, [r7, #8]
8004408: fbb2 f3f3 udiv r3, r2, r3
800440c: 607b str r3, [r7, #4]
return sysclockfreq;
800440e: 687b ldr r3, [r7, #4]
}
8004410: 4618 mov r0, r3
8004412: 371c adds r7, #28
8004414: 46bd mov sp, r7
8004416: f85d 7b04 ldr.w r7, [sp], #4
800441a: 4770 bx lr
800441c: 40021000 .word 0x40021000
8004420: 007a1200 .word 0x007a1200
8004424: 00f42400 .word 0x00f42400
08004428 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004428: b580 push {r7, lr}
800442a: b086 sub sp, #24
800442c: af00 add r7, sp, #0
800442e: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8004430: 2300 movs r3, #0
8004432: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8004434: 2300 movs r3, #0
8004436: 74bb strb r3, [r7, #18]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8004438: 687b ldr r3, [r7, #4]
800443a: 681b ldr r3, [r3, #0]
800443c: f403 2300 and.w r3, r3, #524288 @ 0x80000
8004440: 2b00 cmp r3, #0
8004442: f000 8098 beq.w 8004576 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
FlagStatus pwrclkchanged = RESET;
8004446: 2300 movs r3, #0
8004448: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800444a: 4b43 ldr r3, [pc, #268] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
800444c: 6d9b ldr r3, [r3, #88] @ 0x58
800444e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004452: 2b00 cmp r3, #0
8004454: d10d bne.n 8004472 <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004456: 4b40 ldr r3, [pc, #256] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004458: 6d9b ldr r3, [r3, #88] @ 0x58
800445a: 4a3f ldr r2, [pc, #252] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
800445c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8004460: 6593 str r3, [r2, #88] @ 0x58
8004462: 4b3d ldr r3, [pc, #244] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004464: 6d9b ldr r3, [r3, #88] @ 0x58
8004466: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800446a: 60bb str r3, [r7, #8]
800446c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800446e: 2301 movs r3, #1
8004470: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8004472: 4b3a ldr r3, [pc, #232] @ (800455c <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004474: 681b ldr r3, [r3, #0]
8004476: 4a39 ldr r2, [pc, #228] @ (800455c <HAL_RCCEx_PeriphCLKConfig+0x134>)
8004478: f443 7380 orr.w r3, r3, #256 @ 0x100
800447c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800447e: f7fd f9bd bl 80017fc <HAL_GetTick>
8004482: 60f8 str r0, [r7, #12]
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8004484: e009 b.n 800449a <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8004486: f7fd f9b9 bl 80017fc <HAL_GetTick>
800448a: 4602 mov r2, r0
800448c: 68fb ldr r3, [r7, #12]
800448e: 1ad3 subs r3, r2, r3
8004490: 2b02 cmp r3, #2
8004492: d902 bls.n 800449a <HAL_RCCEx_PeriphCLKConfig+0x72>
{
ret = HAL_TIMEOUT;
8004494: 2303 movs r3, #3
8004496: 74fb strb r3, [r7, #19]
break;
8004498: e005 b.n 80044a6 <HAL_RCCEx_PeriphCLKConfig+0x7e>
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
800449a: 4b30 ldr r3, [pc, #192] @ (800455c <HAL_RCCEx_PeriphCLKConfig+0x134>)
800449c: 681b ldr r3, [r3, #0]
800449e: f403 7380 and.w r3, r3, #256 @ 0x100
80044a2: 2b00 cmp r3, #0
80044a4: d0ef beq.n 8004486 <HAL_RCCEx_PeriphCLKConfig+0x5e>
}
}
if(ret == HAL_OK)
80044a6: 7cfb ldrb r3, [r7, #19]
80044a8: 2b00 cmp r3, #0
80044aa: d159 bne.n 8004560 <HAL_RCCEx_PeriphCLKConfig+0x138>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
80044ac: 4b2a ldr r3, [pc, #168] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044ae: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80044b2: f403 7340 and.w r3, r3, #768 @ 0x300
80044b6: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
80044b8: 697b ldr r3, [r7, #20]
80044ba: 2b00 cmp r3, #0
80044bc: d01e beq.n 80044fc <HAL_RCCEx_PeriphCLKConfig+0xd4>
80044be: 687b ldr r3, [r7, #4]
80044c0: 6c1b ldr r3, [r3, #64] @ 0x40
80044c2: 697a ldr r2, [r7, #20]
80044c4: 429a cmp r2, r3
80044c6: d019 beq.n 80044fc <HAL_RCCEx_PeriphCLKConfig+0xd4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
80044c8: 4b23 ldr r3, [pc, #140] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044ca: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80044ce: f423 7340 bic.w r3, r3, #768 @ 0x300
80044d2: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80044d4: 4b20 ldr r3, [pc, #128] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044d6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80044da: 4a1f ldr r2, [pc, #124] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80044e0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
80044e4: 4b1c ldr r3, [pc, #112] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044e6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80044ea: 4a1b ldr r2, [pc, #108] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044ec: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80044f0: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
80044f4: 4a18 ldr r2, [pc, #96] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
80044f6: 697b ldr r3, [r7, #20]
80044f8: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
80044fc: 697b ldr r3, [r7, #20]
80044fe: f003 0301 and.w r3, r3, #1
8004502: 2b00 cmp r3, #0
8004504: d016 beq.n 8004534 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004506: f7fd f979 bl 80017fc <HAL_GetTick>
800450a: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800450c: e00b b.n 8004526 <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800450e: f7fd f975 bl 80017fc <HAL_GetTick>
8004512: 4602 mov r2, r0
8004514: 68fb ldr r3, [r7, #12]
8004516: 1ad3 subs r3, r2, r3
8004518: f241 3288 movw r2, #5000 @ 0x1388
800451c: 4293 cmp r3, r2
800451e: d902 bls.n 8004526 <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
ret = HAL_TIMEOUT;
8004520: 2303 movs r3, #3
8004522: 74fb strb r3, [r7, #19]
break;
8004524: e006 b.n 8004534 <HAL_RCCEx_PeriphCLKConfig+0x10c>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004526: 4b0c ldr r3, [pc, #48] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
8004528: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800452c: f003 0302 and.w r3, r3, #2
8004530: 2b00 cmp r3, #0
8004532: d0ec beq.n 800450e <HAL_RCCEx_PeriphCLKConfig+0xe6>
}
}
}
if(ret == HAL_OK)
8004534: 7cfb ldrb r3, [r7, #19]
8004536: 2b00 cmp r3, #0
8004538: d10b bne.n 8004552 <HAL_RCCEx_PeriphCLKConfig+0x12a>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800453a: 4b07 ldr r3, [pc, #28] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
800453c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8004540: f423 7240 bic.w r2, r3, #768 @ 0x300
8004544: 687b ldr r3, [r7, #4]
8004546: 6c1b ldr r3, [r3, #64] @ 0x40
8004548: 4903 ldr r1, [pc, #12] @ (8004558 <HAL_RCCEx_PeriphCLKConfig+0x130>)
800454a: 4313 orrs r3, r2
800454c: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8004550: e008 b.n 8004564 <HAL_RCCEx_PeriphCLKConfig+0x13c>
}
else
{
/* set overall return value */
status = ret;
8004552: 7cfb ldrb r3, [r7, #19]
8004554: 74bb strb r3, [r7, #18]
8004556: e005 b.n 8004564 <HAL_RCCEx_PeriphCLKConfig+0x13c>
8004558: 40021000 .word 0x40021000
800455c: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8004560: 7cfb ldrb r3, [r7, #19]
8004562: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8004564: 7c7b ldrb r3, [r7, #17]
8004566: 2b01 cmp r3, #1
8004568: d105 bne.n 8004576 <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
__HAL_RCC_PWR_CLK_DISABLE();
800456a: 4ba6 ldr r3, [pc, #664] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800456c: 6d9b ldr r3, [r3, #88] @ 0x58
800456e: 4aa5 ldr r2, [pc, #660] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004570: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8004574: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8004576: 687b ldr r3, [r7, #4]
8004578: 681b ldr r3, [r3, #0]
800457a: f003 0301 and.w r3, r3, #1
800457e: 2b00 cmp r3, #0
8004580: d00a beq.n 8004598 <HAL_RCCEx_PeriphCLKConfig+0x170>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8004582: 4ba0 ldr r3, [pc, #640] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004584: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004588: f023 0203 bic.w r2, r3, #3
800458c: 687b ldr r3, [r7, #4]
800458e: 685b ldr r3, [r3, #4]
8004590: 499c ldr r1, [pc, #624] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004592: 4313 orrs r3, r2
8004594: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8004598: 687b ldr r3, [r7, #4]
800459a: 681b ldr r3, [r3, #0]
800459c: f003 0302 and.w r3, r3, #2
80045a0: 2b00 cmp r3, #0
80045a2: d00a beq.n 80045ba <HAL_RCCEx_PeriphCLKConfig+0x192>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
80045a4: 4b97 ldr r3, [pc, #604] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80045a6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80045aa: f023 020c bic.w r2, r3, #12
80045ae: 687b ldr r3, [r7, #4]
80045b0: 689b ldr r3, [r3, #8]
80045b2: 4994 ldr r1, [pc, #592] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80045b4: 4313 orrs r3, r2
80045b6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
80045ba: 687b ldr r3, [r7, #4]
80045bc: 681b ldr r3, [r3, #0]
80045be: f003 0304 and.w r3, r3, #4
80045c2: 2b00 cmp r3, #0
80045c4: d00a beq.n 80045dc <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
80045c6: 4b8f ldr r3, [pc, #572] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80045c8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80045cc: f023 0230 bic.w r2, r3, #48 @ 0x30
80045d0: 687b ldr r3, [r7, #4]
80045d2: 68db ldr r3, [r3, #12]
80045d4: 498b ldr r1, [pc, #556] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80045d6: 4313 orrs r3, r2
80045d8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
80045dc: 687b ldr r3, [r7, #4]
80045de: 681b ldr r3, [r3, #0]
80045e0: f003 0308 and.w r3, r3, #8
80045e4: 2b00 cmp r3, #0
80045e6: d00a beq.n 80045fe <HAL_RCCEx_PeriphCLKConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
80045e8: 4b86 ldr r3, [pc, #536] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80045ea: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80045ee: f023 02c0 bic.w r2, r3, #192 @ 0xc0
80045f2: 687b ldr r3, [r7, #4]
80045f4: 691b ldr r3, [r3, #16]
80045f6: 4983 ldr r1, [pc, #524] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80045f8: 4313 orrs r3, r2
80045fa: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
80045fe: 687b ldr r3, [r7, #4]
8004600: 681b ldr r3, [r3, #0]
8004602: f003 0320 and.w r3, r3, #32
8004606: 2b00 cmp r3, #0
8004608: d00a beq.n 8004620 <HAL_RCCEx_PeriphCLKConfig+0x1f8>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
800460a: 4b7e ldr r3, [pc, #504] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800460c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004610: f423 6240 bic.w r2, r3, #3072 @ 0xc00
8004614: 687b ldr r3, [r7, #4]
8004616: 695b ldr r3, [r3, #20]
8004618: 497a ldr r1, [pc, #488] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800461a: 4313 orrs r3, r2
800461c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8004620: 687b ldr r3, [r7, #4]
8004622: 681b ldr r3, [r3, #0]
8004624: f003 0340 and.w r3, r3, #64 @ 0x40
8004628: 2b00 cmp r3, #0
800462a: d00a beq.n 8004642 <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
800462c: 4b75 ldr r3, [pc, #468] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800462e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004632: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8004636: 687b ldr r3, [r7, #4]
8004638: 699b ldr r3, [r3, #24]
800463a: 4972 ldr r1, [pc, #456] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800463c: 4313 orrs r3, r2
800463e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8004642: 687b ldr r3, [r7, #4]
8004644: 681b ldr r3, [r3, #0]
8004646: f003 0380 and.w r3, r3, #128 @ 0x80
800464a: 2b00 cmp r3, #0
800464c: d00a beq.n 8004664 <HAL_RCCEx_PeriphCLKConfig+0x23c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
800464e: 4b6d ldr r3, [pc, #436] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004650: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004654: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8004658: 687b ldr r3, [r7, #4]
800465a: 69db ldr r3, [r3, #28]
800465c: 4969 ldr r1, [pc, #420] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800465e: 4313 orrs r3, r2
8004660: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8004664: 687b ldr r3, [r7, #4]
8004666: 681b ldr r3, [r3, #0]
8004668: f403 7380 and.w r3, r3, #256 @ 0x100
800466c: 2b00 cmp r3, #0
800466e: d00a beq.n 8004686 <HAL_RCCEx_PeriphCLKConfig+0x25e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8004670: 4b64 ldr r3, [pc, #400] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004672: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004676: f423 3240 bic.w r2, r3, #196608 @ 0x30000
800467a: 687b ldr r3, [r7, #4]
800467c: 6a1b ldr r3, [r3, #32]
800467e: 4961 ldr r1, [pc, #388] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004680: 4313 orrs r3, r2
8004682: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* I2C4 */
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8004686: 687b ldr r3, [r7, #4]
8004688: 681b ldr r3, [r3, #0]
800468a: f403 7300 and.w r3, r3, #512 @ 0x200
800468e: 2b00 cmp r3, #0
8004690: d00a beq.n 80046a8 <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8004692: 4b5c ldr r3, [pc, #368] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004694: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004698: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
800469c: 687b ldr r3, [r7, #4]
800469e: 6a5b ldr r3, [r3, #36] @ 0x24
80046a0: 4958 ldr r1, [pc, #352] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046a2: 4313 orrs r3, r2
80046a4: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
80046a8: 687b ldr r3, [r7, #4]
80046aa: 681b ldr r3, [r3, #0]
80046ac: f403 6380 and.w r3, r3, #1024 @ 0x400
80046b0: 2b00 cmp r3, #0
80046b2: d015 beq.n 80046e0 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure the SAI1 interface clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80046b4: 4b53 ldr r3, [pc, #332] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046b6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80046ba: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80046be: 687b ldr r3, [r7, #4]
80046c0: 6a9b ldr r3, [r3, #40] @ 0x28
80046c2: 4950 ldr r1, [pc, #320] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046c4: 4313 orrs r3, r2
80046c6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
80046ca: 687b ldr r3, [r7, #4]
80046cc: 6a9b ldr r3, [r3, #40] @ 0x28
80046ce: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80046d2: d105 bne.n 80046e0 <HAL_RCCEx_PeriphCLKConfig+0x2b8>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80046d4: 4b4b ldr r3, [pc, #300] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046d6: 68db ldr r3, [r3, #12]
80046d8: 4a4a ldr r2, [pc, #296] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046da: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80046de: 60d3 str r3, [r2, #12]
#endif /* SAI1 */
#if defined(SPI_I2S_SUPPORT)
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
80046e0: 687b ldr r3, [r7, #4]
80046e2: 681b ldr r3, [r3, #0]
80046e4: f403 6300 and.w r3, r3, #2048 @ 0x800
80046e8: 2b00 cmp r3, #0
80046ea: d015 beq.n 8004718 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S interface clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80046ec: 4b45 ldr r3, [pc, #276] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046ee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80046f2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
80046f6: 687b ldr r3, [r7, #4]
80046f8: 6adb ldr r3, [r3, #44] @ 0x2c
80046fa: 4942 ldr r1, [pc, #264] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80046fc: 4313 orrs r3, r2
80046fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
8004702: 687b ldr r3, [r7, #4]
8004704: 6adb ldr r3, [r3, #44] @ 0x2c
8004706: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
800470a: d105 bne.n 8004718 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800470c: 4b3d ldr r3, [pc, #244] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800470e: 68db ldr r3, [r3, #12]
8004710: 4a3c ldr r2, [pc, #240] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004712: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004716: 60d3 str r3, [r2, #12]
#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8004718: 687b ldr r3, [r7, #4]
800471a: 681b ldr r3, [r3, #0]
800471c: f403 5380 and.w r3, r3, #4096 @ 0x1000
8004720: 2b00 cmp r3, #0
8004722: d015 beq.n 8004750 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Check the parameters */
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
/* Configure the FDCAN interface clock source */
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8004724: 4b37 ldr r3, [pc, #220] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004726: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800472a: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
800472e: 687b ldr r3, [r7, #4]
8004730: 6b1b ldr r3, [r3, #48] @ 0x30
8004732: 4934 ldr r1, [pc, #208] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004734: 4313 orrs r3, r2
8004736: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
800473a: 687b ldr r3, [r7, #4]
800473c: 6b1b ldr r3, [r3, #48] @ 0x30
800473e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8004742: d105 bne.n 8004750 <HAL_RCCEx_PeriphCLKConfig+0x328>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8004744: 4b2f ldr r3, [pc, #188] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004746: 68db ldr r3, [r3, #12]
8004748: 4a2e ldr r2, [pc, #184] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800474a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800474e: 60d3 str r3, [r2, #12]
#endif /* FDCAN1 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
8004750: 687b ldr r3, [r7, #4]
8004752: 681b ldr r3, [r3, #0]
8004754: f403 5300 and.w r3, r3, #8192 @ 0x2000
8004758: 2b00 cmp r3, #0
800475a: d015 beq.n 8004788 <HAL_RCCEx_PeriphCLKConfig+0x360>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
800475c: 4b29 ldr r3, [pc, #164] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800475e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8004762: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
8004766: 687b ldr r3, [r7, #4]
8004768: 6b5b ldr r3, [r3, #52] @ 0x34
800476a: 4926 ldr r1, [pc, #152] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800476c: 4313 orrs r3, r2
800476e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
8004772: 687b ldr r3, [r7, #4]
8004774: 6b5b ldr r3, [r3, #52] @ 0x34
8004776: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800477a: d105 bne.n 8004788 <HAL_RCCEx_PeriphCLKConfig+0x360>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800477c: 4b21 ldr r3, [pc, #132] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
800477e: 68db ldr r3, [r3, #12]
8004780: 4a20 ldr r2, [pc, #128] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004782: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8004786: 60d3 str r3, [r2, #12]
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
8004788: 687b ldr r3, [r7, #4]
800478a: 681b ldr r3, [r3, #0]
800478c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8004790: 2b00 cmp r3, #0
8004792: d015 beq.n 80047c0 <HAL_RCCEx_PeriphCLKConfig+0x398>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
8004794: 4b1b ldr r3, [pc, #108] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
8004796: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800479a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
800479e: 687b ldr r3, [r7, #4]
80047a0: 6b9b ldr r3, [r3, #56] @ 0x38
80047a2: 4918 ldr r1, [pc, #96] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047a4: 4313 orrs r3, r2
80047a6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
80047aa: 687b ldr r3, [r7, #4]
80047ac: 6b9b ldr r3, [r3, #56] @ 0x38
80047ae: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80047b2: d105 bne.n 80047c0 <HAL_RCCEx_PeriphCLKConfig+0x398>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80047b4: 4b13 ldr r3, [pc, #76] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047b6: 68db ldr r3, [r3, #12]
80047b8: 4a12 ldr r2, [pc, #72] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047ba: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80047be: 60d3 str r3, [r2, #12]
}
}
/*-------------------------- ADC12 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
80047c0: 687b ldr r3, [r7, #4]
80047c2: 681b ldr r3, [r3, #0]
80047c4: f403 4300 and.w r3, r3, #32768 @ 0x8000
80047c8: 2b00 cmp r3, #0
80047ca: d015 beq.n 80047f8 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 interface clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
80047cc: 4b0d ldr r3, [pc, #52] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047ce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80047d2: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
80047d6: 687b ldr r3, [r7, #4]
80047d8: 6bdb ldr r3, [r3, #60] @ 0x3c
80047da: 490a ldr r1, [pc, #40] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047dc: 4313 orrs r3, r2
80047de: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
80047e2: 687b ldr r3, [r7, #4]
80047e4: 6bdb ldr r3, [r3, #60] @ 0x3c
80047e6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
80047ea: d105 bne.n 80047f8 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
80047ec: 4b05 ldr r3, [pc, #20] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047ee: 68db ldr r3, [r3, #12]
80047f0: 4a04 ldr r2, [pc, #16] @ (8004804 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
80047f2: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80047f6: 60d3 str r3, [r2, #12]
}
}
#endif /* QUADSPI */
return status;
80047f8: 7cbb ldrb r3, [r7, #18]
}
80047fa: 4618 mov r0, r3
80047fc: 3718 adds r7, #24
80047fe: 46bd mov sp, r7
8004800: bd80 pop {r7, pc}
8004802: bf00 nop
8004804: 40021000 .word 0x40021000
08004808 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8004808: b580 push {r7, lr}
800480a: b082 sub sp, #8
800480c: af00 add r7, sp, #0
800480e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004810: 687b ldr r3, [r7, #4]
8004812: 2b00 cmp r3, #0
8004814: d101 bne.n 800481a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8004816: 2301 movs r3, #1
8004818: e049 b.n 80048ae <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800481a: 687b ldr r3, [r7, #4]
800481c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004820: b2db uxtb r3, r3
8004822: 2b00 cmp r3, #0
8004824: d106 bne.n 8004834 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004826: 687b ldr r3, [r7, #4]
8004828: 2200 movs r2, #0
800482a: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800482e: 6878 ldr r0, [r7, #4]
8004830: f7fc fe30 bl 8001494 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004834: 687b ldr r3, [r7, #4]
8004836: 2202 movs r2, #2
8004838: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800483c: 687b ldr r3, [r7, #4]
800483e: 681a ldr r2, [r3, #0]
8004840: 687b ldr r3, [r7, #4]
8004842: 3304 adds r3, #4
8004844: 4619 mov r1, r3
8004846: 4610 mov r0, r2
8004848: f000 fd26 bl 8005298 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800484c: 687b ldr r3, [r7, #4]
800484e: 2201 movs r2, #1
8004850: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004854: 687b ldr r3, [r7, #4]
8004856: 2201 movs r2, #1
8004858: f883 203e strb.w r2, [r3, #62] @ 0x3e
800485c: 687b ldr r3, [r7, #4]
800485e: 2201 movs r2, #1
8004860: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004864: 687b ldr r3, [r7, #4]
8004866: 2201 movs r2, #1
8004868: f883 2040 strb.w r2, [r3, #64] @ 0x40
800486c: 687b ldr r3, [r7, #4]
800486e: 2201 movs r2, #1
8004870: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004874: 687b ldr r3, [r7, #4]
8004876: 2201 movs r2, #1
8004878: f883 2042 strb.w r2, [r3, #66] @ 0x42
800487c: 687b ldr r3, [r7, #4]
800487e: 2201 movs r2, #1
8004880: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004884: 687b ldr r3, [r7, #4]
8004886: 2201 movs r2, #1
8004888: f883 2044 strb.w r2, [r3, #68] @ 0x44
800488c: 687b ldr r3, [r7, #4]
800488e: 2201 movs r2, #1
8004890: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004894: 687b ldr r3, [r7, #4]
8004896: 2201 movs r2, #1
8004898: f883 2046 strb.w r2, [r3, #70] @ 0x46
800489c: 687b ldr r3, [r7, #4]
800489e: 2201 movs r2, #1
80048a0: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80048a4: 687b ldr r3, [r7, #4]
80048a6: 2201 movs r2, #1
80048a8: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
80048ac: 2300 movs r3, #0
}
80048ae: 4618 mov r0, r3
80048b0: 3708 adds r7, #8
80048b2: 46bd mov sp, r7
80048b4: bd80 pop {r7, pc}
080048b6 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
80048b6: b580 push {r7, lr}
80048b8: b082 sub sp, #8
80048ba: af00 add r7, sp, #0
80048bc: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80048be: 687b ldr r3, [r7, #4]
80048c0: 2b00 cmp r3, #0
80048c2: d101 bne.n 80048c8 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
80048c4: 2301 movs r3, #1
80048c6: e049 b.n 800495c <HAL_TIM_PWM_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80048c8: 687b ldr r3, [r7, #4]
80048ca: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80048ce: b2db uxtb r3, r3
80048d0: 2b00 cmp r3, #0
80048d2: d106 bne.n 80048e2 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80048d4: 687b ldr r3, [r7, #4]
80048d6: 2200 movs r2, #0
80048d8: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
80048dc: 6878 ldr r0, [r7, #4]
80048de: f000 f841 bl 8004964 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80048e2: 687b ldr r3, [r7, #4]
80048e4: 2202 movs r2, #2
80048e6: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80048ea: 687b ldr r3, [r7, #4]
80048ec: 681a ldr r2, [r3, #0]
80048ee: 687b ldr r3, [r7, #4]
80048f0: 3304 adds r3, #4
80048f2: 4619 mov r1, r3
80048f4: 4610 mov r0, r2
80048f6: f000 fccf bl 8005298 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80048fa: 687b ldr r3, [r7, #4]
80048fc: 2201 movs r2, #1
80048fe: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004902: 687b ldr r3, [r7, #4]
8004904: 2201 movs r2, #1
8004906: f883 203e strb.w r2, [r3, #62] @ 0x3e
800490a: 687b ldr r3, [r7, #4]
800490c: 2201 movs r2, #1
800490e: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004912: 687b ldr r3, [r7, #4]
8004914: 2201 movs r2, #1
8004916: f883 2040 strb.w r2, [r3, #64] @ 0x40
800491a: 687b ldr r3, [r7, #4]
800491c: 2201 movs r2, #1
800491e: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004922: 687b ldr r3, [r7, #4]
8004924: 2201 movs r2, #1
8004926: f883 2042 strb.w r2, [r3, #66] @ 0x42
800492a: 687b ldr r3, [r7, #4]
800492c: 2201 movs r2, #1
800492e: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004932: 687b ldr r3, [r7, #4]
8004934: 2201 movs r2, #1
8004936: f883 2044 strb.w r2, [r3, #68] @ 0x44
800493a: 687b ldr r3, [r7, #4]
800493c: 2201 movs r2, #1
800493e: f883 2045 strb.w r2, [r3, #69] @ 0x45
8004942: 687b ldr r3, [r7, #4]
8004944: 2201 movs r2, #1
8004946: f883 2046 strb.w r2, [r3, #70] @ 0x46
800494a: 687b ldr r3, [r7, #4]
800494c: 2201 movs r2, #1
800494e: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004952: 687b ldr r3, [r7, #4]
8004954: 2201 movs r2, #1
8004956: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800495a: 2300 movs r3, #0
}
800495c: 4618 mov r0, r3
800495e: 3708 adds r7, #8
8004960: 46bd mov sp, r7
8004962: bd80 pop {r7, pc}
08004964 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8004964: b480 push {r7}
8004966: b083 sub sp, #12
8004968: af00 add r7, sp, #0
800496a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
800496c: bf00 nop
800496e: 370c adds r7, #12
8004970: 46bd mov sp, r7
8004972: f85d 7b04 ldr.w r7, [sp], #4
8004976: 4770 bx lr
08004978 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8004978: b580 push {r7, lr}
800497a: b084 sub sp, #16
800497c: af00 add r7, sp, #0
800497e: 6078 str r0, [r7, #4]
8004980: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8004982: 683b ldr r3, [r7, #0]
8004984: 2b00 cmp r3, #0
8004986: d109 bne.n 800499c <HAL_TIM_PWM_Start+0x24>
8004988: 687b ldr r3, [r7, #4]
800498a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
800498e: b2db uxtb r3, r3
8004990: 2b01 cmp r3, #1
8004992: bf14 ite ne
8004994: 2301 movne r3, #1
8004996: 2300 moveq r3, #0
8004998: b2db uxtb r3, r3
800499a: e03c b.n 8004a16 <HAL_TIM_PWM_Start+0x9e>
800499c: 683b ldr r3, [r7, #0]
800499e: 2b04 cmp r3, #4
80049a0: d109 bne.n 80049b6 <HAL_TIM_PWM_Start+0x3e>
80049a2: 687b ldr r3, [r7, #4]
80049a4: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
80049a8: b2db uxtb r3, r3
80049aa: 2b01 cmp r3, #1
80049ac: bf14 ite ne
80049ae: 2301 movne r3, #1
80049b0: 2300 moveq r3, #0
80049b2: b2db uxtb r3, r3
80049b4: e02f b.n 8004a16 <HAL_TIM_PWM_Start+0x9e>
80049b6: 683b ldr r3, [r7, #0]
80049b8: 2b08 cmp r3, #8
80049ba: d109 bne.n 80049d0 <HAL_TIM_PWM_Start+0x58>
80049bc: 687b ldr r3, [r7, #4]
80049be: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80049c2: b2db uxtb r3, r3
80049c4: 2b01 cmp r3, #1
80049c6: bf14 ite ne
80049c8: 2301 movne r3, #1
80049ca: 2300 moveq r3, #0
80049cc: b2db uxtb r3, r3
80049ce: e022 b.n 8004a16 <HAL_TIM_PWM_Start+0x9e>
80049d0: 683b ldr r3, [r7, #0]
80049d2: 2b0c cmp r3, #12
80049d4: d109 bne.n 80049ea <HAL_TIM_PWM_Start+0x72>
80049d6: 687b ldr r3, [r7, #4]
80049d8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
80049dc: b2db uxtb r3, r3
80049de: 2b01 cmp r3, #1
80049e0: bf14 ite ne
80049e2: 2301 movne r3, #1
80049e4: 2300 moveq r3, #0
80049e6: b2db uxtb r3, r3
80049e8: e015 b.n 8004a16 <HAL_TIM_PWM_Start+0x9e>
80049ea: 683b ldr r3, [r7, #0]
80049ec: 2b10 cmp r3, #16
80049ee: d109 bne.n 8004a04 <HAL_TIM_PWM_Start+0x8c>
80049f0: 687b ldr r3, [r7, #4]
80049f2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
80049f6: b2db uxtb r3, r3
80049f8: 2b01 cmp r3, #1
80049fa: bf14 ite ne
80049fc: 2301 movne r3, #1
80049fe: 2300 moveq r3, #0
8004a00: b2db uxtb r3, r3
8004a02: e008 b.n 8004a16 <HAL_TIM_PWM_Start+0x9e>
8004a04: 687b ldr r3, [r7, #4]
8004a06: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
8004a0a: b2db uxtb r3, r3
8004a0c: 2b01 cmp r3, #1
8004a0e: bf14 ite ne
8004a10: 2301 movne r3, #1
8004a12: 2300 moveq r3, #0
8004a14: b2db uxtb r3, r3
8004a16: 2b00 cmp r3, #0
8004a18: d001 beq.n 8004a1e <HAL_TIM_PWM_Start+0xa6>
{
return HAL_ERROR;
8004a1a: 2301 movs r3, #1
8004a1c: e097 b.n 8004b4e <HAL_TIM_PWM_Start+0x1d6>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8004a1e: 683b ldr r3, [r7, #0]
8004a20: 2b00 cmp r3, #0
8004a22: d104 bne.n 8004a2e <HAL_TIM_PWM_Start+0xb6>
8004a24: 687b ldr r3, [r7, #4]
8004a26: 2202 movs r2, #2
8004a28: f883 203e strb.w r2, [r3, #62] @ 0x3e
8004a2c: e023 b.n 8004a76 <HAL_TIM_PWM_Start+0xfe>
8004a2e: 683b ldr r3, [r7, #0]
8004a30: 2b04 cmp r3, #4
8004a32: d104 bne.n 8004a3e <HAL_TIM_PWM_Start+0xc6>
8004a34: 687b ldr r3, [r7, #4]
8004a36: 2202 movs r2, #2
8004a38: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004a3c: e01b b.n 8004a76 <HAL_TIM_PWM_Start+0xfe>
8004a3e: 683b ldr r3, [r7, #0]
8004a40: 2b08 cmp r3, #8
8004a42: d104 bne.n 8004a4e <HAL_TIM_PWM_Start+0xd6>
8004a44: 687b ldr r3, [r7, #4]
8004a46: 2202 movs r2, #2
8004a48: f883 2040 strb.w r2, [r3, #64] @ 0x40
8004a4c: e013 b.n 8004a76 <HAL_TIM_PWM_Start+0xfe>
8004a4e: 683b ldr r3, [r7, #0]
8004a50: 2b0c cmp r3, #12
8004a52: d104 bne.n 8004a5e <HAL_TIM_PWM_Start+0xe6>
8004a54: 687b ldr r3, [r7, #4]
8004a56: 2202 movs r2, #2
8004a58: f883 2041 strb.w r2, [r3, #65] @ 0x41
8004a5c: e00b b.n 8004a76 <HAL_TIM_PWM_Start+0xfe>
8004a5e: 683b ldr r3, [r7, #0]
8004a60: 2b10 cmp r3, #16
8004a62: d104 bne.n 8004a6e <HAL_TIM_PWM_Start+0xf6>
8004a64: 687b ldr r3, [r7, #4]
8004a66: 2202 movs r2, #2
8004a68: f883 2042 strb.w r2, [r3, #66] @ 0x42
8004a6c: e003 b.n 8004a76 <HAL_TIM_PWM_Start+0xfe>
8004a6e: 687b ldr r3, [r7, #4]
8004a70: 2202 movs r2, #2
8004a72: f883 2043 strb.w r2, [r3, #67] @ 0x43
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8004a76: 687b ldr r3, [r7, #4]
8004a78: 681b ldr r3, [r3, #0]
8004a7a: 2201 movs r2, #1
8004a7c: 6839 ldr r1, [r7, #0]
8004a7e: 4618 mov r0, r3
8004a80: f001 f838 bl 8005af4 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
8004a84: 687b ldr r3, [r7, #4]
8004a86: 681b ldr r3, [r3, #0]
8004a88: 4a33 ldr r2, [pc, #204] @ (8004b58 <HAL_TIM_PWM_Start+0x1e0>)
8004a8a: 4293 cmp r3, r2
8004a8c: d013 beq.n 8004ab6 <HAL_TIM_PWM_Start+0x13e>
8004a8e: 687b ldr r3, [r7, #4]
8004a90: 681b ldr r3, [r3, #0]
8004a92: 4a32 ldr r2, [pc, #200] @ (8004b5c <HAL_TIM_PWM_Start+0x1e4>)
8004a94: 4293 cmp r3, r2
8004a96: d00e beq.n 8004ab6 <HAL_TIM_PWM_Start+0x13e>
8004a98: 687b ldr r3, [r7, #4]
8004a9a: 681b ldr r3, [r3, #0]
8004a9c: 4a30 ldr r2, [pc, #192] @ (8004b60 <HAL_TIM_PWM_Start+0x1e8>)
8004a9e: 4293 cmp r3, r2
8004aa0: d009 beq.n 8004ab6 <HAL_TIM_PWM_Start+0x13e>
8004aa2: 687b ldr r3, [r7, #4]
8004aa4: 681b ldr r3, [r3, #0]
8004aa6: 4a2f ldr r2, [pc, #188] @ (8004b64 <HAL_TIM_PWM_Start+0x1ec>)
8004aa8: 4293 cmp r3, r2
8004aaa: d004 beq.n 8004ab6 <HAL_TIM_PWM_Start+0x13e>
8004aac: 687b ldr r3, [r7, #4]
8004aae: 681b ldr r3, [r3, #0]
8004ab0: 4a2d ldr r2, [pc, #180] @ (8004b68 <HAL_TIM_PWM_Start+0x1f0>)
8004ab2: 4293 cmp r3, r2
8004ab4: d101 bne.n 8004aba <HAL_TIM_PWM_Start+0x142>
8004ab6: 2301 movs r3, #1
8004ab8: e000 b.n 8004abc <HAL_TIM_PWM_Start+0x144>
8004aba: 2300 movs r3, #0
8004abc: 2b00 cmp r3, #0
8004abe: d007 beq.n 8004ad0 <HAL_TIM_PWM_Start+0x158>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8004ac0: 687b ldr r3, [r7, #4]
8004ac2: 681b ldr r3, [r3, #0]
8004ac4: 6c5a ldr r2, [r3, #68] @ 0x44
8004ac6: 687b ldr r3, [r7, #4]
8004ac8: 681b ldr r3, [r3, #0]
8004aca: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8004ace: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004ad0: 687b ldr r3, [r7, #4]
8004ad2: 681b ldr r3, [r3, #0]
8004ad4: 4a20 ldr r2, [pc, #128] @ (8004b58 <HAL_TIM_PWM_Start+0x1e0>)
8004ad6: 4293 cmp r3, r2
8004ad8: d018 beq.n 8004b0c <HAL_TIM_PWM_Start+0x194>
8004ada: 687b ldr r3, [r7, #4]
8004adc: 681b ldr r3, [r3, #0]
8004ade: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004ae2: d013 beq.n 8004b0c <HAL_TIM_PWM_Start+0x194>
8004ae4: 687b ldr r3, [r7, #4]
8004ae6: 681b ldr r3, [r3, #0]
8004ae8: 4a20 ldr r2, [pc, #128] @ (8004b6c <HAL_TIM_PWM_Start+0x1f4>)
8004aea: 4293 cmp r3, r2
8004aec: d00e beq.n 8004b0c <HAL_TIM_PWM_Start+0x194>
8004aee: 687b ldr r3, [r7, #4]
8004af0: 681b ldr r3, [r3, #0]
8004af2: 4a1f ldr r2, [pc, #124] @ (8004b70 <HAL_TIM_PWM_Start+0x1f8>)
8004af4: 4293 cmp r3, r2
8004af6: d009 beq.n 8004b0c <HAL_TIM_PWM_Start+0x194>
8004af8: 687b ldr r3, [r7, #4]
8004afa: 681b ldr r3, [r3, #0]
8004afc: 4a17 ldr r2, [pc, #92] @ (8004b5c <HAL_TIM_PWM_Start+0x1e4>)
8004afe: 4293 cmp r3, r2
8004b00: d004 beq.n 8004b0c <HAL_TIM_PWM_Start+0x194>
8004b02: 687b ldr r3, [r7, #4]
8004b04: 681b ldr r3, [r3, #0]
8004b06: 4a16 ldr r2, [pc, #88] @ (8004b60 <HAL_TIM_PWM_Start+0x1e8>)
8004b08: 4293 cmp r3, r2
8004b0a: d115 bne.n 8004b38 <HAL_TIM_PWM_Start+0x1c0>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8004b0c: 687b ldr r3, [r7, #4]
8004b0e: 681b ldr r3, [r3, #0]
8004b10: 689a ldr r2, [r3, #8]
8004b12: 4b18 ldr r3, [pc, #96] @ (8004b74 <HAL_TIM_PWM_Start+0x1fc>)
8004b14: 4013 ands r3, r2
8004b16: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004b18: 68fb ldr r3, [r7, #12]
8004b1a: 2b06 cmp r3, #6
8004b1c: d015 beq.n 8004b4a <HAL_TIM_PWM_Start+0x1d2>
8004b1e: 68fb ldr r3, [r7, #12]
8004b20: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004b24: d011 beq.n 8004b4a <HAL_TIM_PWM_Start+0x1d2>
{
__HAL_TIM_ENABLE(htim);
8004b26: 687b ldr r3, [r7, #4]
8004b28: 681b ldr r3, [r3, #0]
8004b2a: 681a ldr r2, [r3, #0]
8004b2c: 687b ldr r3, [r7, #4]
8004b2e: 681b ldr r3, [r3, #0]
8004b30: f042 0201 orr.w r2, r2, #1
8004b34: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004b36: e008 b.n 8004b4a <HAL_TIM_PWM_Start+0x1d2>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8004b38: 687b ldr r3, [r7, #4]
8004b3a: 681b ldr r3, [r3, #0]
8004b3c: 681a ldr r2, [r3, #0]
8004b3e: 687b ldr r3, [r7, #4]
8004b40: 681b ldr r3, [r3, #0]
8004b42: f042 0201 orr.w r2, r2, #1
8004b46: 601a str r2, [r3, #0]
8004b48: e000 b.n 8004b4c <HAL_TIM_PWM_Start+0x1d4>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004b4a: bf00 nop
}
/* Return function status */
return HAL_OK;
8004b4c: 2300 movs r3, #0
}
8004b4e: 4618 mov r0, r3
8004b50: 3710 adds r7, #16
8004b52: 46bd mov sp, r7
8004b54: bd80 pop {r7, pc}
8004b56: bf00 nop
8004b58: 40012c00 .word 0x40012c00
8004b5c: 40013400 .word 0x40013400
8004b60: 40014000 .word 0x40014000
8004b64: 40014400 .word 0x40014400
8004b68: 40014800 .word 0x40014800
8004b6c: 40000400 .word 0x40000400
8004b70: 40000800 .word 0x40000800
8004b74: 00010007 .word 0x00010007
08004b78 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8004b78: b580 push {r7, lr}
8004b7a: b084 sub sp, #16
8004b7c: af00 add r7, sp, #0
8004b7e: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8004b80: 687b ldr r3, [r7, #4]
8004b82: 681b ldr r3, [r3, #0]
8004b84: 68db ldr r3, [r3, #12]
8004b86: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8004b88: 687b ldr r3, [r7, #4]
8004b8a: 681b ldr r3, [r3, #0]
8004b8c: 691b ldr r3, [r3, #16]
8004b8e: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8004b90: 68bb ldr r3, [r7, #8]
8004b92: f003 0302 and.w r3, r3, #2
8004b96: 2b00 cmp r3, #0
8004b98: d020 beq.n 8004bdc <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8004b9a: 68fb ldr r3, [r7, #12]
8004b9c: f003 0302 and.w r3, r3, #2
8004ba0: 2b00 cmp r3, #0
8004ba2: d01b beq.n 8004bdc <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8004ba4: 687b ldr r3, [r7, #4]
8004ba6: 681b ldr r3, [r3, #0]
8004ba8: f06f 0202 mvn.w r2, #2
8004bac: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8004bae: 687b ldr r3, [r7, #4]
8004bb0: 2201 movs r2, #1
8004bb2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8004bb4: 687b ldr r3, [r7, #4]
8004bb6: 681b ldr r3, [r3, #0]
8004bb8: 699b ldr r3, [r3, #24]
8004bba: f003 0303 and.w r3, r3, #3
8004bbe: 2b00 cmp r3, #0
8004bc0: d003 beq.n 8004bca <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004bc2: 6878 ldr r0, [r7, #4]
8004bc4: f000 fb4a bl 800525c <HAL_TIM_IC_CaptureCallback>
8004bc8: e005 b.n 8004bd6 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004bca: 6878 ldr r0, [r7, #4]
8004bcc: f000 fb3c bl 8005248 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004bd0: 6878 ldr r0, [r7, #4]
8004bd2: f000 fb4d bl 8005270 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004bd6: 687b ldr r3, [r7, #4]
8004bd8: 2200 movs r2, #0
8004bda: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8004bdc: 68bb ldr r3, [r7, #8]
8004bde: f003 0304 and.w r3, r3, #4
8004be2: 2b00 cmp r3, #0
8004be4: d020 beq.n 8004c28 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8004be6: 68fb ldr r3, [r7, #12]
8004be8: f003 0304 and.w r3, r3, #4
8004bec: 2b00 cmp r3, #0
8004bee: d01b beq.n 8004c28 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8004bf0: 687b ldr r3, [r7, #4]
8004bf2: 681b ldr r3, [r3, #0]
8004bf4: f06f 0204 mvn.w r2, #4
8004bf8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8004bfa: 687b ldr r3, [r7, #4]
8004bfc: 2202 movs r2, #2
8004bfe: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8004c00: 687b ldr r3, [r7, #4]
8004c02: 681b ldr r3, [r3, #0]
8004c04: 699b ldr r3, [r3, #24]
8004c06: f403 7340 and.w r3, r3, #768 @ 0x300
8004c0a: 2b00 cmp r3, #0
8004c0c: d003 beq.n 8004c16 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004c0e: 6878 ldr r0, [r7, #4]
8004c10: f000 fb24 bl 800525c <HAL_TIM_IC_CaptureCallback>
8004c14: e005 b.n 8004c22 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004c16: 6878 ldr r0, [r7, #4]
8004c18: f000 fb16 bl 8005248 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004c1c: 6878 ldr r0, [r7, #4]
8004c1e: f000 fb27 bl 8005270 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004c22: 687b ldr r3, [r7, #4]
8004c24: 2200 movs r2, #0
8004c26: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8004c28: 68bb ldr r3, [r7, #8]
8004c2a: f003 0308 and.w r3, r3, #8
8004c2e: 2b00 cmp r3, #0
8004c30: d020 beq.n 8004c74 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8004c32: 68fb ldr r3, [r7, #12]
8004c34: f003 0308 and.w r3, r3, #8
8004c38: 2b00 cmp r3, #0
8004c3a: d01b beq.n 8004c74 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8004c3c: 687b ldr r3, [r7, #4]
8004c3e: 681b ldr r3, [r3, #0]
8004c40: f06f 0208 mvn.w r2, #8
8004c44: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8004c46: 687b ldr r3, [r7, #4]
8004c48: 2204 movs r2, #4
8004c4a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8004c4c: 687b ldr r3, [r7, #4]
8004c4e: 681b ldr r3, [r3, #0]
8004c50: 69db ldr r3, [r3, #28]
8004c52: f003 0303 and.w r3, r3, #3
8004c56: 2b00 cmp r3, #0
8004c58: d003 beq.n 8004c62 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004c5a: 6878 ldr r0, [r7, #4]
8004c5c: f000 fafe bl 800525c <HAL_TIM_IC_CaptureCallback>
8004c60: e005 b.n 8004c6e <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004c62: 6878 ldr r0, [r7, #4]
8004c64: f000 faf0 bl 8005248 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004c68: 6878 ldr r0, [r7, #4]
8004c6a: f000 fb01 bl 8005270 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004c6e: 687b ldr r3, [r7, #4]
8004c70: 2200 movs r2, #0
8004c72: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8004c74: 68bb ldr r3, [r7, #8]
8004c76: f003 0310 and.w r3, r3, #16
8004c7a: 2b00 cmp r3, #0
8004c7c: d020 beq.n 8004cc0 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8004c7e: 68fb ldr r3, [r7, #12]
8004c80: f003 0310 and.w r3, r3, #16
8004c84: 2b00 cmp r3, #0
8004c86: d01b beq.n 8004cc0 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8004c88: 687b ldr r3, [r7, #4]
8004c8a: 681b ldr r3, [r3, #0]
8004c8c: f06f 0210 mvn.w r2, #16
8004c90: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8004c92: 687b ldr r3, [r7, #4]
8004c94: 2208 movs r2, #8
8004c96: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8004c98: 687b ldr r3, [r7, #4]
8004c9a: 681b ldr r3, [r3, #0]
8004c9c: 69db ldr r3, [r3, #28]
8004c9e: f403 7340 and.w r3, r3, #768 @ 0x300
8004ca2: 2b00 cmp r3, #0
8004ca4: d003 beq.n 8004cae <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004ca6: 6878 ldr r0, [r7, #4]
8004ca8: f000 fad8 bl 800525c <HAL_TIM_IC_CaptureCallback>
8004cac: e005 b.n 8004cba <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004cae: 6878 ldr r0, [r7, #4]
8004cb0: f000 faca bl 8005248 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004cb4: 6878 ldr r0, [r7, #4]
8004cb6: f000 fadb bl 8005270 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004cba: 687b ldr r3, [r7, #4]
8004cbc: 2200 movs r2, #0
8004cbe: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8004cc0: 68bb ldr r3, [r7, #8]
8004cc2: f003 0301 and.w r3, r3, #1
8004cc6: 2b00 cmp r3, #0
8004cc8: d00c beq.n 8004ce4 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8004cca: 68fb ldr r3, [r7, #12]
8004ccc: f003 0301 and.w r3, r3, #1
8004cd0: 2b00 cmp r3, #0
8004cd2: d007 beq.n 8004ce4 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8004cd4: 687b ldr r3, [r7, #4]
8004cd6: 681b ldr r3, [r3, #0]
8004cd8: f06f 0201 mvn.w r2, #1
8004cdc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8004cde: 6878 ldr r0, [r7, #4]
8004ce0: f000 faa8 bl 8005234 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8004ce4: 68bb ldr r3, [r7, #8]
8004ce6: f003 0380 and.w r3, r3, #128 @ 0x80
8004cea: 2b00 cmp r3, #0
8004cec: d104 bne.n 8004cf8 <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
8004cee: 68bb ldr r3, [r7, #8]
8004cf0: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8004cf4: 2b00 cmp r3, #0
8004cf6: d00c beq.n 8004d12 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8004cf8: 68fb ldr r3, [r7, #12]
8004cfa: f003 0380 and.w r3, r3, #128 @ 0x80
8004cfe: 2b00 cmp r3, #0
8004d00: d007 beq.n 8004d12 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8004d02: 687b ldr r3, [r7, #4]
8004d04: 681b ldr r3, [r3, #0]
8004d06: f46f 5202 mvn.w r2, #8320 @ 0x2080
8004d0a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8004d0c: 6878 ldr r0, [r7, #4]
8004d0e: f001 f82f bl 8005d70 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8004d12: 68bb ldr r3, [r7, #8]
8004d14: f403 7380 and.w r3, r3, #256 @ 0x100
8004d18: 2b00 cmp r3, #0
8004d1a: d00c beq.n 8004d36 <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8004d1c: 68fb ldr r3, [r7, #12]
8004d1e: f003 0380 and.w r3, r3, #128 @ 0x80
8004d22: 2b00 cmp r3, #0
8004d24: d007 beq.n 8004d36 <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8004d26: 687b ldr r3, [r7, #4]
8004d28: 681b ldr r3, [r3, #0]
8004d2a: f46f 7280 mvn.w r2, #256 @ 0x100
8004d2e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8004d30: 6878 ldr r0, [r7, #4]
8004d32: f001 f827 bl 8005d84 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8004d36: 68bb ldr r3, [r7, #8]
8004d38: f003 0340 and.w r3, r3, #64 @ 0x40
8004d3c: 2b00 cmp r3, #0
8004d3e: d00c beq.n 8004d5a <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8004d40: 68fb ldr r3, [r7, #12]
8004d42: f003 0340 and.w r3, r3, #64 @ 0x40
8004d46: 2b00 cmp r3, #0
8004d48: d007 beq.n 8004d5a <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8004d4a: 687b ldr r3, [r7, #4]
8004d4c: 681b ldr r3, [r3, #0]
8004d4e: f06f 0240 mvn.w r2, #64 @ 0x40
8004d52: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8004d54: 6878 ldr r0, [r7, #4]
8004d56: f000 fa95 bl 8005284 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8004d5a: 68bb ldr r3, [r7, #8]
8004d5c: f003 0320 and.w r3, r3, #32
8004d60: 2b00 cmp r3, #0
8004d62: d00c beq.n 8004d7e <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8004d64: 68fb ldr r3, [r7, #12]
8004d66: f003 0320 and.w r3, r3, #32
8004d6a: 2b00 cmp r3, #0
8004d6c: d007 beq.n 8004d7e <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8004d6e: 687b ldr r3, [r7, #4]
8004d70: 681b ldr r3, [r3, #0]
8004d72: f06f 0220 mvn.w r2, #32
8004d76: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8004d78: 6878 ldr r0, [r7, #4]
8004d7a: f000 ffef bl 8005d5c <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Encoder index event */
if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
8004d7e: 68bb ldr r3, [r7, #8]
8004d80: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8004d84: 2b00 cmp r3, #0
8004d86: d00c beq.n 8004da2 <HAL_TIM_IRQHandler+0x22a>
{
if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
8004d88: 68fb ldr r3, [r7, #12]
8004d8a: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8004d8e: 2b00 cmp r3, #0
8004d90: d007 beq.n 8004da2 <HAL_TIM_IRQHandler+0x22a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
8004d92: 687b ldr r3, [r7, #4]
8004d94: 681b ldr r3, [r3, #0]
8004d96: f46f 1280 mvn.w r2, #1048576 @ 0x100000
8004d9a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->EncoderIndexCallback(htim);
#else
HAL_TIMEx_EncoderIndexCallback(htim);
8004d9c: 6878 ldr r0, [r7, #4]
8004d9e: f000 fffb bl 8005d98 <HAL_TIMEx_EncoderIndexCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Direction change event */
if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
8004da2: 68bb ldr r3, [r7, #8]
8004da4: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8004da8: 2b00 cmp r3, #0
8004daa: d00c beq.n 8004dc6 <HAL_TIM_IRQHandler+0x24e>
{
if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
8004dac: 68fb ldr r3, [r7, #12]
8004dae: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8004db2: 2b00 cmp r3, #0
8004db4: d007 beq.n 8004dc6 <HAL_TIM_IRQHandler+0x24e>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
8004db6: 687b ldr r3, [r7, #4]
8004db8: 681b ldr r3, [r3, #0]
8004dba: f46f 1200 mvn.w r2, #2097152 @ 0x200000
8004dbe: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->DirectionChangeCallback(htim);
#else
HAL_TIMEx_DirectionChangeCallback(htim);
8004dc0: 6878 ldr r0, [r7, #4]
8004dc2: f000 fff3 bl 8005dac <HAL_TIMEx_DirectionChangeCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Index error event */
if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
8004dc6: 68bb ldr r3, [r7, #8]
8004dc8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8004dcc: 2b00 cmp r3, #0
8004dce: d00c beq.n 8004dea <HAL_TIM_IRQHandler+0x272>
{
if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
8004dd0: 68fb ldr r3, [r7, #12]
8004dd2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8004dd6: 2b00 cmp r3, #0
8004dd8: d007 beq.n 8004dea <HAL_TIM_IRQHandler+0x272>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
8004dda: 687b ldr r3, [r7, #4]
8004ddc: 681b ldr r3, [r3, #0]
8004dde: f46f 0280 mvn.w r2, #4194304 @ 0x400000
8004de2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IndexErrorCallback(htim);
#else
HAL_TIMEx_IndexErrorCallback(htim);
8004de4: 6878 ldr r0, [r7, #4]
8004de6: f000 ffeb bl 8005dc0 <HAL_TIMEx_IndexErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Transition error event */
if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
8004dea: 68bb ldr r3, [r7, #8]
8004dec: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8004df0: 2b00 cmp r3, #0
8004df2: d00c beq.n 8004e0e <HAL_TIM_IRQHandler+0x296>
{
if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
8004df4: 68fb ldr r3, [r7, #12]
8004df6: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8004dfa: 2b00 cmp r3, #0
8004dfc: d007 beq.n 8004e0e <HAL_TIM_IRQHandler+0x296>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
8004dfe: 687b ldr r3, [r7, #4]
8004e00: 681b ldr r3, [r3, #0]
8004e02: f46f 0200 mvn.w r2, #8388608 @ 0x800000
8004e06: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TransitionErrorCallback(htim);
#else
HAL_TIMEx_TransitionErrorCallback(htim);
8004e08: 6878 ldr r0, [r7, #4]
8004e0a: f000 ffe3 bl 8005dd4 <HAL_TIMEx_TransitionErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8004e0e: bf00 nop
8004e10: 3710 adds r7, #16
8004e12: 46bd mov sp, r7
8004e14: bd80 pop {r7, pc}
...
08004e18 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8004e18: b580 push {r7, lr}
8004e1a: b086 sub sp, #24
8004e1c: af00 add r7, sp, #0
8004e1e: 60f8 str r0, [r7, #12]
8004e20: 60b9 str r1, [r7, #8]
8004e22: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8004e24: 2300 movs r3, #0
8004e26: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8004e28: 68fb ldr r3, [r7, #12]
8004e2a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004e2e: 2b01 cmp r3, #1
8004e30: d101 bne.n 8004e36 <HAL_TIM_PWM_ConfigChannel+0x1e>
8004e32: 2302 movs r3, #2
8004e34: e0ff b.n 8005036 <HAL_TIM_PWM_ConfigChannel+0x21e>
8004e36: 68fb ldr r3, [r7, #12]
8004e38: 2201 movs r2, #1
8004e3a: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8004e3e: 687b ldr r3, [r7, #4]
8004e40: 2b14 cmp r3, #20
8004e42: f200 80f0 bhi.w 8005026 <HAL_TIM_PWM_ConfigChannel+0x20e>
8004e46: a201 add r2, pc, #4 @ (adr r2, 8004e4c <HAL_TIM_PWM_ConfigChannel+0x34>)
8004e48: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004e4c: 08004ea1 .word 0x08004ea1
8004e50: 08005027 .word 0x08005027
8004e54: 08005027 .word 0x08005027
8004e58: 08005027 .word 0x08005027
8004e5c: 08004ee1 .word 0x08004ee1
8004e60: 08005027 .word 0x08005027
8004e64: 08005027 .word 0x08005027
8004e68: 08005027 .word 0x08005027
8004e6c: 08004f23 .word 0x08004f23
8004e70: 08005027 .word 0x08005027
8004e74: 08005027 .word 0x08005027
8004e78: 08005027 .word 0x08005027
8004e7c: 08004f63 .word 0x08004f63
8004e80: 08005027 .word 0x08005027
8004e84: 08005027 .word 0x08005027
8004e88: 08005027 .word 0x08005027
8004e8c: 08004fa5 .word 0x08004fa5
8004e90: 08005027 .word 0x08005027
8004e94: 08005027 .word 0x08005027
8004e98: 08005027 .word 0x08005027
8004e9c: 08004fe5 .word 0x08004fe5
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8004ea0: 68fb ldr r3, [r7, #12]
8004ea2: 681b ldr r3, [r3, #0]
8004ea4: 68b9 ldr r1, [r7, #8]
8004ea6: 4618 mov r0, r3
8004ea8: f000 fa92 bl 80053d0 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8004eac: 68fb ldr r3, [r7, #12]
8004eae: 681b ldr r3, [r3, #0]
8004eb0: 699a ldr r2, [r3, #24]
8004eb2: 68fb ldr r3, [r7, #12]
8004eb4: 681b ldr r3, [r3, #0]
8004eb6: f042 0208 orr.w r2, r2, #8
8004eba: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8004ebc: 68fb ldr r3, [r7, #12]
8004ebe: 681b ldr r3, [r3, #0]
8004ec0: 699a ldr r2, [r3, #24]
8004ec2: 68fb ldr r3, [r7, #12]
8004ec4: 681b ldr r3, [r3, #0]
8004ec6: f022 0204 bic.w r2, r2, #4
8004eca: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8004ecc: 68fb ldr r3, [r7, #12]
8004ece: 681b ldr r3, [r3, #0]
8004ed0: 6999 ldr r1, [r3, #24]
8004ed2: 68bb ldr r3, [r7, #8]
8004ed4: 691a ldr r2, [r3, #16]
8004ed6: 68fb ldr r3, [r7, #12]
8004ed8: 681b ldr r3, [r3, #0]
8004eda: 430a orrs r2, r1
8004edc: 619a str r2, [r3, #24]
break;
8004ede: e0a5 b.n 800502c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8004ee0: 68fb ldr r3, [r7, #12]
8004ee2: 681b ldr r3, [r3, #0]
8004ee4: 68b9 ldr r1, [r7, #8]
8004ee6: 4618 mov r0, r3
8004ee8: f000 fb02 bl 80054f0 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8004eec: 68fb ldr r3, [r7, #12]
8004eee: 681b ldr r3, [r3, #0]
8004ef0: 699a ldr r2, [r3, #24]
8004ef2: 68fb ldr r3, [r7, #12]
8004ef4: 681b ldr r3, [r3, #0]
8004ef6: f442 6200 orr.w r2, r2, #2048 @ 0x800
8004efa: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8004efc: 68fb ldr r3, [r7, #12]
8004efe: 681b ldr r3, [r3, #0]
8004f00: 699a ldr r2, [r3, #24]
8004f02: 68fb ldr r3, [r7, #12]
8004f04: 681b ldr r3, [r3, #0]
8004f06: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004f0a: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8004f0c: 68fb ldr r3, [r7, #12]
8004f0e: 681b ldr r3, [r3, #0]
8004f10: 6999 ldr r1, [r3, #24]
8004f12: 68bb ldr r3, [r7, #8]
8004f14: 691b ldr r3, [r3, #16]
8004f16: 021a lsls r2, r3, #8
8004f18: 68fb ldr r3, [r7, #12]
8004f1a: 681b ldr r3, [r3, #0]
8004f1c: 430a orrs r2, r1
8004f1e: 619a str r2, [r3, #24]
break;
8004f20: e084 b.n 800502c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8004f22: 68fb ldr r3, [r7, #12]
8004f24: 681b ldr r3, [r3, #0]
8004f26: 68b9 ldr r1, [r7, #8]
8004f28: 4618 mov r0, r3
8004f2a: f000 fb6b bl 8005604 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8004f2e: 68fb ldr r3, [r7, #12]
8004f30: 681b ldr r3, [r3, #0]
8004f32: 69da ldr r2, [r3, #28]
8004f34: 68fb ldr r3, [r7, #12]
8004f36: 681b ldr r3, [r3, #0]
8004f38: f042 0208 orr.w r2, r2, #8
8004f3c: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8004f3e: 68fb ldr r3, [r7, #12]
8004f40: 681b ldr r3, [r3, #0]
8004f42: 69da ldr r2, [r3, #28]
8004f44: 68fb ldr r3, [r7, #12]
8004f46: 681b ldr r3, [r3, #0]
8004f48: f022 0204 bic.w r2, r2, #4
8004f4c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8004f4e: 68fb ldr r3, [r7, #12]
8004f50: 681b ldr r3, [r3, #0]
8004f52: 69d9 ldr r1, [r3, #28]
8004f54: 68bb ldr r3, [r7, #8]
8004f56: 691a ldr r2, [r3, #16]
8004f58: 68fb ldr r3, [r7, #12]
8004f5a: 681b ldr r3, [r3, #0]
8004f5c: 430a orrs r2, r1
8004f5e: 61da str r2, [r3, #28]
break;
8004f60: e064 b.n 800502c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8004f62: 68fb ldr r3, [r7, #12]
8004f64: 681b ldr r3, [r3, #0]
8004f66: 68b9 ldr r1, [r7, #8]
8004f68: 4618 mov r0, r3
8004f6a: f000 fbd3 bl 8005714 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8004f6e: 68fb ldr r3, [r7, #12]
8004f70: 681b ldr r3, [r3, #0]
8004f72: 69da ldr r2, [r3, #28]
8004f74: 68fb ldr r3, [r7, #12]
8004f76: 681b ldr r3, [r3, #0]
8004f78: f442 6200 orr.w r2, r2, #2048 @ 0x800
8004f7c: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8004f7e: 68fb ldr r3, [r7, #12]
8004f80: 681b ldr r3, [r3, #0]
8004f82: 69da ldr r2, [r3, #28]
8004f84: 68fb ldr r3, [r7, #12]
8004f86: 681b ldr r3, [r3, #0]
8004f88: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004f8c: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8004f8e: 68fb ldr r3, [r7, #12]
8004f90: 681b ldr r3, [r3, #0]
8004f92: 69d9 ldr r1, [r3, #28]
8004f94: 68bb ldr r3, [r7, #8]
8004f96: 691b ldr r3, [r3, #16]
8004f98: 021a lsls r2, r3, #8
8004f9a: 68fb ldr r3, [r7, #12]
8004f9c: 681b ldr r3, [r3, #0]
8004f9e: 430a orrs r2, r1
8004fa0: 61da str r2, [r3, #28]
break;
8004fa2: e043 b.n 800502c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8004fa4: 68fb ldr r3, [r7, #12]
8004fa6: 681b ldr r3, [r3, #0]
8004fa8: 68b9 ldr r1, [r7, #8]
8004faa: 4618 mov r0, r3
8004fac: f000 fc3c bl 8005828 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8004fb0: 68fb ldr r3, [r7, #12]
8004fb2: 681b ldr r3, [r3, #0]
8004fb4: 6d1a ldr r2, [r3, #80] @ 0x50
8004fb6: 68fb ldr r3, [r7, #12]
8004fb8: 681b ldr r3, [r3, #0]
8004fba: f042 0208 orr.w r2, r2, #8
8004fbe: 651a str r2, [r3, #80] @ 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8004fc0: 68fb ldr r3, [r7, #12]
8004fc2: 681b ldr r3, [r3, #0]
8004fc4: 6d1a ldr r2, [r3, #80] @ 0x50
8004fc6: 68fb ldr r3, [r7, #12]
8004fc8: 681b ldr r3, [r3, #0]
8004fca: f022 0204 bic.w r2, r2, #4
8004fce: 651a str r2, [r3, #80] @ 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8004fd0: 68fb ldr r3, [r7, #12]
8004fd2: 681b ldr r3, [r3, #0]
8004fd4: 6d19 ldr r1, [r3, #80] @ 0x50
8004fd6: 68bb ldr r3, [r7, #8]
8004fd8: 691a ldr r2, [r3, #16]
8004fda: 68fb ldr r3, [r7, #12]
8004fdc: 681b ldr r3, [r3, #0]
8004fde: 430a orrs r2, r1
8004fe0: 651a str r2, [r3, #80] @ 0x50
break;
8004fe2: e023 b.n 800502c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8004fe4: 68fb ldr r3, [r7, #12]
8004fe6: 681b ldr r3, [r3, #0]
8004fe8: 68b9 ldr r1, [r7, #8]
8004fea: 4618 mov r0, r3
8004fec: f000 fc80 bl 80058f0 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8004ff0: 68fb ldr r3, [r7, #12]
8004ff2: 681b ldr r3, [r3, #0]
8004ff4: 6d1a ldr r2, [r3, #80] @ 0x50
8004ff6: 68fb ldr r3, [r7, #12]
8004ff8: 681b ldr r3, [r3, #0]
8004ffa: f442 6200 orr.w r2, r2, #2048 @ 0x800
8004ffe: 651a str r2, [r3, #80] @ 0x50
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8005000: 68fb ldr r3, [r7, #12]
8005002: 681b ldr r3, [r3, #0]
8005004: 6d1a ldr r2, [r3, #80] @ 0x50
8005006: 68fb ldr r3, [r7, #12]
8005008: 681b ldr r3, [r3, #0]
800500a: f422 6280 bic.w r2, r2, #1024 @ 0x400
800500e: 651a str r2, [r3, #80] @ 0x50
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8005010: 68fb ldr r3, [r7, #12]
8005012: 681b ldr r3, [r3, #0]
8005014: 6d19 ldr r1, [r3, #80] @ 0x50
8005016: 68bb ldr r3, [r7, #8]
8005018: 691b ldr r3, [r3, #16]
800501a: 021a lsls r2, r3, #8
800501c: 68fb ldr r3, [r7, #12]
800501e: 681b ldr r3, [r3, #0]
8005020: 430a orrs r2, r1
8005022: 651a str r2, [r3, #80] @ 0x50
break;
8005024: e002 b.n 800502c <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
status = HAL_ERROR;
8005026: 2301 movs r3, #1
8005028: 75fb strb r3, [r7, #23]
break;
800502a: bf00 nop
}
__HAL_UNLOCK(htim);
800502c: 68fb ldr r3, [r7, #12]
800502e: 2200 movs r2, #0
8005030: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8005034: 7dfb ldrb r3, [r7, #23]
}
8005036: 4618 mov r0, r3
8005038: 3718 adds r7, #24
800503a: 46bd mov sp, r7
800503c: bd80 pop {r7, pc}
800503e: bf00 nop
08005040 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8005040: b580 push {r7, lr}
8005042: b084 sub sp, #16
8005044: af00 add r7, sp, #0
8005046: 6078 str r0, [r7, #4]
8005048: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
800504a: 2300 movs r3, #0
800504c: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800504e: 687b ldr r3, [r7, #4]
8005050: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005054: 2b01 cmp r3, #1
8005056: d101 bne.n 800505c <HAL_TIM_ConfigClockSource+0x1c>
8005058: 2302 movs r3, #2
800505a: e0de b.n 800521a <HAL_TIM_ConfigClockSource+0x1da>
800505c: 687b ldr r3, [r7, #4]
800505e: 2201 movs r2, #1
8005060: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8005064: 687b ldr r3, [r7, #4]
8005066: 2202 movs r2, #2
8005068: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800506c: 687b ldr r3, [r7, #4]
800506e: 681b ldr r3, [r3, #0]
8005070: 689b ldr r3, [r3, #8]
8005072: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8005074: 68bb ldr r3, [r7, #8]
8005076: f423 1344 bic.w r3, r3, #3211264 @ 0x310000
800507a: f023 0377 bic.w r3, r3, #119 @ 0x77
800507e: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005080: 68bb ldr r3, [r7, #8]
8005082: f423 437f bic.w r3, r3, #65280 @ 0xff00
8005086: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8005088: 687b ldr r3, [r7, #4]
800508a: 681b ldr r3, [r3, #0]
800508c: 68ba ldr r2, [r7, #8]
800508e: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8005090: 683b ldr r3, [r7, #0]
8005092: 681b ldr r3, [r3, #0]
8005094: 4a63 ldr r2, [pc, #396] @ (8005224 <HAL_TIM_ConfigClockSource+0x1e4>)
8005096: 4293 cmp r3, r2
8005098: f000 80a9 beq.w 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
800509c: 4a61 ldr r2, [pc, #388] @ (8005224 <HAL_TIM_ConfigClockSource+0x1e4>)
800509e: 4293 cmp r3, r2
80050a0: f200 80ae bhi.w 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
80050a4: 4a60 ldr r2, [pc, #384] @ (8005228 <HAL_TIM_ConfigClockSource+0x1e8>)
80050a6: 4293 cmp r3, r2
80050a8: f000 80a1 beq.w 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
80050ac: 4a5e ldr r2, [pc, #376] @ (8005228 <HAL_TIM_ConfigClockSource+0x1e8>)
80050ae: 4293 cmp r3, r2
80050b0: f200 80a6 bhi.w 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
80050b4: 4a5d ldr r2, [pc, #372] @ (800522c <HAL_TIM_ConfigClockSource+0x1ec>)
80050b6: 4293 cmp r3, r2
80050b8: f000 8099 beq.w 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
80050bc: 4a5b ldr r2, [pc, #364] @ (800522c <HAL_TIM_ConfigClockSource+0x1ec>)
80050be: 4293 cmp r3, r2
80050c0: f200 809e bhi.w 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
80050c4: 4a5a ldr r2, [pc, #360] @ (8005230 <HAL_TIM_ConfigClockSource+0x1f0>)
80050c6: 4293 cmp r3, r2
80050c8: f000 8091 beq.w 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
80050cc: 4a58 ldr r2, [pc, #352] @ (8005230 <HAL_TIM_ConfigClockSource+0x1f0>)
80050ce: 4293 cmp r3, r2
80050d0: f200 8096 bhi.w 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
80050d4: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
80050d8: f000 8089 beq.w 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
80050dc: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
80050e0: f200 808e bhi.w 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
80050e4: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80050e8: d03e beq.n 8005168 <HAL_TIM_ConfigClockSource+0x128>
80050ea: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80050ee: f200 8087 bhi.w 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
80050f2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80050f6: f000 8086 beq.w 8005206 <HAL_TIM_ConfigClockSource+0x1c6>
80050fa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80050fe: d87f bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005100: 2b70 cmp r3, #112 @ 0x70
8005102: d01a beq.n 800513a <HAL_TIM_ConfigClockSource+0xfa>
8005104: 2b70 cmp r3, #112 @ 0x70
8005106: d87b bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005108: 2b60 cmp r3, #96 @ 0x60
800510a: d050 beq.n 80051ae <HAL_TIM_ConfigClockSource+0x16e>
800510c: 2b60 cmp r3, #96 @ 0x60
800510e: d877 bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005110: 2b50 cmp r3, #80 @ 0x50
8005112: d03c beq.n 800518e <HAL_TIM_ConfigClockSource+0x14e>
8005114: 2b50 cmp r3, #80 @ 0x50
8005116: d873 bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005118: 2b40 cmp r3, #64 @ 0x40
800511a: d058 beq.n 80051ce <HAL_TIM_ConfigClockSource+0x18e>
800511c: 2b40 cmp r3, #64 @ 0x40
800511e: d86f bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005120: 2b30 cmp r3, #48 @ 0x30
8005122: d064 beq.n 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
8005124: 2b30 cmp r3, #48 @ 0x30
8005126: d86b bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005128: 2b20 cmp r3, #32
800512a: d060 beq.n 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
800512c: 2b20 cmp r3, #32
800512e: d867 bhi.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
8005130: 2b00 cmp r3, #0
8005132: d05c beq.n 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
8005134: 2b10 cmp r3, #16
8005136: d05a beq.n 80051ee <HAL_TIM_ConfigClockSource+0x1ae>
8005138: e062 b.n 8005200 <HAL_TIM_ConfigClockSource+0x1c0>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
800513a: 687b ldr r3, [r7, #4]
800513c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
800513e: 683b ldr r3, [r7, #0]
8005140: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8005142: 683b ldr r3, [r7, #0]
8005144: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8005146: 683b ldr r3, [r7, #0]
8005148: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
800514a: f000 fcb3 bl 8005ab4 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
800514e: 687b ldr r3, [r7, #4]
8005150: 681b ldr r3, [r3, #0]
8005152: 689b ldr r3, [r3, #8]
8005154: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8005156: 68bb ldr r3, [r7, #8]
8005158: f043 0377 orr.w r3, r3, #119 @ 0x77
800515c: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800515e: 687b ldr r3, [r7, #4]
8005160: 681b ldr r3, [r3, #0]
8005162: 68ba ldr r2, [r7, #8]
8005164: 609a str r2, [r3, #8]
break;
8005166: e04f b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8005168: 687b ldr r3, [r7, #4]
800516a: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
800516c: 683b ldr r3, [r7, #0]
800516e: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8005170: 683b ldr r3, [r7, #0]
8005172: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8005174: 683b ldr r3, [r7, #0]
8005176: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8005178: f000 fc9c bl 8005ab4 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
800517c: 687b ldr r3, [r7, #4]
800517e: 681b ldr r3, [r3, #0]
8005180: 689a ldr r2, [r3, #8]
8005182: 687b ldr r3, [r7, #4]
8005184: 681b ldr r3, [r3, #0]
8005186: f442 4280 orr.w r2, r2, #16384 @ 0x4000
800518a: 609a str r2, [r3, #8]
break;
800518c: e03c b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
800518e: 687b ldr r3, [r7, #4]
8005190: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8005192: 683b ldr r3, [r7, #0]
8005194: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8005196: 683b ldr r3, [r7, #0]
8005198: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
800519a: 461a mov r2, r3
800519c: f000 fc0e bl 80059bc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
80051a0: 687b ldr r3, [r7, #4]
80051a2: 681b ldr r3, [r3, #0]
80051a4: 2150 movs r1, #80 @ 0x50
80051a6: 4618 mov r0, r3
80051a8: f000 fc67 bl 8005a7a <TIM_ITRx_SetConfig>
break;
80051ac: e02c b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
80051ae: 687b ldr r3, [r7, #4]
80051b0: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80051b2: 683b ldr r3, [r7, #0]
80051b4: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80051b6: 683b ldr r3, [r7, #0]
80051b8: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
80051ba: 461a mov r2, r3
80051bc: f000 fc2d bl 8005a1a <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
80051c0: 687b ldr r3, [r7, #4]
80051c2: 681b ldr r3, [r3, #0]
80051c4: 2160 movs r1, #96 @ 0x60
80051c6: 4618 mov r0, r3
80051c8: f000 fc57 bl 8005a7a <TIM_ITRx_SetConfig>
break;
80051cc: e01c b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
80051ce: 687b ldr r3, [r7, #4]
80051d0: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
80051d2: 683b ldr r3, [r7, #0]
80051d4: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
80051d6: 683b ldr r3, [r7, #0]
80051d8: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
80051da: 461a mov r2, r3
80051dc: f000 fbee bl 80059bc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
80051e0: 687b ldr r3, [r7, #4]
80051e2: 681b ldr r3, [r3, #0]
80051e4: 2140 movs r1, #64 @ 0x40
80051e6: 4618 mov r0, r3
80051e8: f000 fc47 bl 8005a7a <TIM_ITRx_SetConfig>
break;
80051ec: e00c b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
case TIM_CLOCKSOURCE_ITR11:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
80051ee: 687b ldr r3, [r7, #4]
80051f0: 681a ldr r2, [r3, #0]
80051f2: 683b ldr r3, [r7, #0]
80051f4: 681b ldr r3, [r3, #0]
80051f6: 4619 mov r1, r3
80051f8: 4610 mov r0, r2
80051fa: f000 fc3e bl 8005a7a <TIM_ITRx_SetConfig>
break;
80051fe: e003 b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
}
default:
status = HAL_ERROR;
8005200: 2301 movs r3, #1
8005202: 73fb strb r3, [r7, #15]
break;
8005204: e000 b.n 8005208 <HAL_TIM_ConfigClockSource+0x1c8>
break;
8005206: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8005208: 687b ldr r3, [r7, #4]
800520a: 2201 movs r2, #1
800520c: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005210: 687b ldr r3, [r7, #4]
8005212: 2200 movs r2, #0
8005214: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8005218: 7bfb ldrb r3, [r7, #15]
}
800521a: 4618 mov r0, r3
800521c: 3710 adds r7, #16
800521e: 46bd mov sp, r7
8005220: bd80 pop {r7, pc}
8005222: bf00 nop
8005224: 00100070 .word 0x00100070
8005228: 00100040 .word 0x00100040
800522c: 00100030 .word 0x00100030
8005230: 00100020 .word 0x00100020
08005234 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8005234: b480 push {r7}
8005236: b083 sub sp, #12
8005238: af00 add r7, sp, #0
800523a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
800523c: bf00 nop
800523e: 370c adds r7, #12
8005240: 46bd mov sp, r7
8005242: f85d 7b04 ldr.w r7, [sp], #4
8005246: 4770 bx lr
08005248 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8005248: b480 push {r7}
800524a: b083 sub sp, #12
800524c: af00 add r7, sp, #0
800524e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8005250: bf00 nop
8005252: 370c adds r7, #12
8005254: 46bd mov sp, r7
8005256: f85d 7b04 ldr.w r7, [sp], #4
800525a: 4770 bx lr
0800525c <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800525c: b480 push {r7}
800525e: b083 sub sp, #12
8005260: af00 add r7, sp, #0
8005262: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8005264: bf00 nop
8005266: 370c adds r7, #12
8005268: 46bd mov sp, r7
800526a: f85d 7b04 ldr.w r7, [sp], #4
800526e: 4770 bx lr
08005270 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8005270: b480 push {r7}
8005272: b083 sub sp, #12
8005274: af00 add r7, sp, #0
8005276: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8005278: bf00 nop
800527a: 370c adds r7, #12
800527c: 46bd mov sp, r7
800527e: f85d 7b04 ldr.w r7, [sp], #4
8005282: 4770 bx lr
08005284 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8005284: b480 push {r7}
8005286: b083 sub sp, #12
8005288: af00 add r7, sp, #0
800528a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800528c: bf00 nop
800528e: 370c adds r7, #12
8005290: 46bd mov sp, r7
8005292: f85d 7b04 ldr.w r7, [sp], #4
8005296: 4770 bx lr
08005298 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8005298: b480 push {r7}
800529a: b085 sub sp, #20
800529c: af00 add r7, sp, #0
800529e: 6078 str r0, [r7, #4]
80052a0: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80052a2: 687b ldr r3, [r7, #4]
80052a4: 681b ldr r3, [r3, #0]
80052a6: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80052a8: 687b ldr r3, [r7, #4]
80052aa: 4a42 ldr r2, [pc, #264] @ (80053b4 <TIM_Base_SetConfig+0x11c>)
80052ac: 4293 cmp r3, r2
80052ae: d00f beq.n 80052d0 <TIM_Base_SetConfig+0x38>
80052b0: 687b ldr r3, [r7, #4]
80052b2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80052b6: d00b beq.n 80052d0 <TIM_Base_SetConfig+0x38>
80052b8: 687b ldr r3, [r7, #4]
80052ba: 4a3f ldr r2, [pc, #252] @ (80053b8 <TIM_Base_SetConfig+0x120>)
80052bc: 4293 cmp r3, r2
80052be: d007 beq.n 80052d0 <TIM_Base_SetConfig+0x38>
80052c0: 687b ldr r3, [r7, #4]
80052c2: 4a3e ldr r2, [pc, #248] @ (80053bc <TIM_Base_SetConfig+0x124>)
80052c4: 4293 cmp r3, r2
80052c6: d003 beq.n 80052d0 <TIM_Base_SetConfig+0x38>
80052c8: 687b ldr r3, [r7, #4]
80052ca: 4a3d ldr r2, [pc, #244] @ (80053c0 <TIM_Base_SetConfig+0x128>)
80052cc: 4293 cmp r3, r2
80052ce: d108 bne.n 80052e2 <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80052d0: 68fb ldr r3, [r7, #12]
80052d2: f023 0370 bic.w r3, r3, #112 @ 0x70
80052d6: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80052d8: 683b ldr r3, [r7, #0]
80052da: 685b ldr r3, [r3, #4]
80052dc: 68fa ldr r2, [r7, #12]
80052de: 4313 orrs r3, r2
80052e0: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80052e2: 687b ldr r3, [r7, #4]
80052e4: 4a33 ldr r2, [pc, #204] @ (80053b4 <TIM_Base_SetConfig+0x11c>)
80052e6: 4293 cmp r3, r2
80052e8: d01b beq.n 8005322 <TIM_Base_SetConfig+0x8a>
80052ea: 687b ldr r3, [r7, #4]
80052ec: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80052f0: d017 beq.n 8005322 <TIM_Base_SetConfig+0x8a>
80052f2: 687b ldr r3, [r7, #4]
80052f4: 4a30 ldr r2, [pc, #192] @ (80053b8 <TIM_Base_SetConfig+0x120>)
80052f6: 4293 cmp r3, r2
80052f8: d013 beq.n 8005322 <TIM_Base_SetConfig+0x8a>
80052fa: 687b ldr r3, [r7, #4]
80052fc: 4a2f ldr r2, [pc, #188] @ (80053bc <TIM_Base_SetConfig+0x124>)
80052fe: 4293 cmp r3, r2
8005300: d00f beq.n 8005322 <TIM_Base_SetConfig+0x8a>
8005302: 687b ldr r3, [r7, #4]
8005304: 4a2e ldr r2, [pc, #184] @ (80053c0 <TIM_Base_SetConfig+0x128>)
8005306: 4293 cmp r3, r2
8005308: d00b beq.n 8005322 <TIM_Base_SetConfig+0x8a>
800530a: 687b ldr r3, [r7, #4]
800530c: 4a2d ldr r2, [pc, #180] @ (80053c4 <TIM_Base_SetConfig+0x12c>)
800530e: 4293 cmp r3, r2
8005310: d007 beq.n 8005322 <TIM_Base_SetConfig+0x8a>
8005312: 687b ldr r3, [r7, #4]
8005314: 4a2c ldr r2, [pc, #176] @ (80053c8 <TIM_Base_SetConfig+0x130>)
8005316: 4293 cmp r3, r2
8005318: d003 beq.n 8005322 <TIM_Base_SetConfig+0x8a>
800531a: 687b ldr r3, [r7, #4]
800531c: 4a2b ldr r2, [pc, #172] @ (80053cc <TIM_Base_SetConfig+0x134>)
800531e: 4293 cmp r3, r2
8005320: d108 bne.n 8005334 <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8005322: 68fb ldr r3, [r7, #12]
8005324: f423 7340 bic.w r3, r3, #768 @ 0x300
8005328: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800532a: 683b ldr r3, [r7, #0]
800532c: 68db ldr r3, [r3, #12]
800532e: 68fa ldr r2, [r7, #12]
8005330: 4313 orrs r3, r2
8005332: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8005334: 68fb ldr r3, [r7, #12]
8005336: f023 0280 bic.w r2, r3, #128 @ 0x80
800533a: 683b ldr r3, [r7, #0]
800533c: 695b ldr r3, [r3, #20]
800533e: 4313 orrs r3, r2
8005340: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8005342: 687b ldr r3, [r7, #4]
8005344: 68fa ldr r2, [r7, #12]
8005346: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8005348: 683b ldr r3, [r7, #0]
800534a: 689a ldr r2, [r3, #8]
800534c: 687b ldr r3, [r7, #4]
800534e: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8005350: 683b ldr r3, [r7, #0]
8005352: 681a ldr r2, [r3, #0]
8005354: 687b ldr r3, [r7, #4]
8005356: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8005358: 687b ldr r3, [r7, #4]
800535a: 4a16 ldr r2, [pc, #88] @ (80053b4 <TIM_Base_SetConfig+0x11c>)
800535c: 4293 cmp r3, r2
800535e: d00f beq.n 8005380 <TIM_Base_SetConfig+0xe8>
8005360: 687b ldr r3, [r7, #4]
8005362: 4a17 ldr r2, [pc, #92] @ (80053c0 <TIM_Base_SetConfig+0x128>)
8005364: 4293 cmp r3, r2
8005366: d00b beq.n 8005380 <TIM_Base_SetConfig+0xe8>
8005368: 687b ldr r3, [r7, #4]
800536a: 4a16 ldr r2, [pc, #88] @ (80053c4 <TIM_Base_SetConfig+0x12c>)
800536c: 4293 cmp r3, r2
800536e: d007 beq.n 8005380 <TIM_Base_SetConfig+0xe8>
8005370: 687b ldr r3, [r7, #4]
8005372: 4a15 ldr r2, [pc, #84] @ (80053c8 <TIM_Base_SetConfig+0x130>)
8005374: 4293 cmp r3, r2
8005376: d003 beq.n 8005380 <TIM_Base_SetConfig+0xe8>
8005378: 687b ldr r3, [r7, #4]
800537a: 4a14 ldr r2, [pc, #80] @ (80053cc <TIM_Base_SetConfig+0x134>)
800537c: 4293 cmp r3, r2
800537e: d103 bne.n 8005388 <TIM_Base_SetConfig+0xf0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8005380: 683b ldr r3, [r7, #0]
8005382: 691a ldr r2, [r3, #16]
8005384: 687b ldr r3, [r7, #4]
8005386: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8005388: 687b ldr r3, [r7, #4]
800538a: 2201 movs r2, #1
800538c: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
800538e: 687b ldr r3, [r7, #4]
8005390: 691b ldr r3, [r3, #16]
8005392: f003 0301 and.w r3, r3, #1
8005396: 2b01 cmp r3, #1
8005398: d105 bne.n 80053a6 <TIM_Base_SetConfig+0x10e>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
800539a: 687b ldr r3, [r7, #4]
800539c: 691b ldr r3, [r3, #16]
800539e: f023 0201 bic.w r2, r3, #1
80053a2: 687b ldr r3, [r7, #4]
80053a4: 611a str r2, [r3, #16]
}
}
80053a6: bf00 nop
80053a8: 3714 adds r7, #20
80053aa: 46bd mov sp, r7
80053ac: f85d 7b04 ldr.w r7, [sp], #4
80053b0: 4770 bx lr
80053b2: bf00 nop
80053b4: 40012c00 .word 0x40012c00
80053b8: 40000400 .word 0x40000400
80053bc: 40000800 .word 0x40000800
80053c0: 40013400 .word 0x40013400
80053c4: 40014000 .word 0x40014000
80053c8: 40014400 .word 0x40014400
80053cc: 40014800 .word 0x40014800
080053d0 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80053d0: b480 push {r7}
80053d2: b087 sub sp, #28
80053d4: af00 add r7, sp, #0
80053d6: 6078 str r0, [r7, #4]
80053d8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80053da: 687b ldr r3, [r7, #4]
80053dc: 6a1b ldr r3, [r3, #32]
80053de: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80053e0: 687b ldr r3, [r7, #4]
80053e2: 6a1b ldr r3, [r3, #32]
80053e4: f023 0201 bic.w r2, r3, #1
80053e8: 687b ldr r3, [r7, #4]
80053ea: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80053ec: 687b ldr r3, [r7, #4]
80053ee: 685b ldr r3, [r3, #4]
80053f0: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80053f2: 687b ldr r3, [r7, #4]
80053f4: 699b ldr r3, [r3, #24]
80053f6: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
80053f8: 68fb ldr r3, [r7, #12]
80053fa: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80053fe: f023 0370 bic.w r3, r3, #112 @ 0x70
8005402: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8005404: 68fb ldr r3, [r7, #12]
8005406: f023 0303 bic.w r3, r3, #3
800540a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800540c: 683b ldr r3, [r7, #0]
800540e: 681b ldr r3, [r3, #0]
8005410: 68fa ldr r2, [r7, #12]
8005412: 4313 orrs r3, r2
8005414: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8005416: 697b ldr r3, [r7, #20]
8005418: f023 0302 bic.w r3, r3, #2
800541c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800541e: 683b ldr r3, [r7, #0]
8005420: 689b ldr r3, [r3, #8]
8005422: 697a ldr r2, [r7, #20]
8005424: 4313 orrs r3, r2
8005426: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8005428: 687b ldr r3, [r7, #4]
800542a: 4a2c ldr r2, [pc, #176] @ (80054dc <TIM_OC1_SetConfig+0x10c>)
800542c: 4293 cmp r3, r2
800542e: d00f beq.n 8005450 <TIM_OC1_SetConfig+0x80>
8005430: 687b ldr r3, [r7, #4]
8005432: 4a2b ldr r2, [pc, #172] @ (80054e0 <TIM_OC1_SetConfig+0x110>)
8005434: 4293 cmp r3, r2
8005436: d00b beq.n 8005450 <TIM_OC1_SetConfig+0x80>
8005438: 687b ldr r3, [r7, #4]
800543a: 4a2a ldr r2, [pc, #168] @ (80054e4 <TIM_OC1_SetConfig+0x114>)
800543c: 4293 cmp r3, r2
800543e: d007 beq.n 8005450 <TIM_OC1_SetConfig+0x80>
8005440: 687b ldr r3, [r7, #4]
8005442: 4a29 ldr r2, [pc, #164] @ (80054e8 <TIM_OC1_SetConfig+0x118>)
8005444: 4293 cmp r3, r2
8005446: d003 beq.n 8005450 <TIM_OC1_SetConfig+0x80>
8005448: 687b ldr r3, [r7, #4]
800544a: 4a28 ldr r2, [pc, #160] @ (80054ec <TIM_OC1_SetConfig+0x11c>)
800544c: 4293 cmp r3, r2
800544e: d10c bne.n 800546a <TIM_OC1_SetConfig+0x9a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8005450: 697b ldr r3, [r7, #20]
8005452: f023 0308 bic.w r3, r3, #8
8005456: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8005458: 683b ldr r3, [r7, #0]
800545a: 68db ldr r3, [r3, #12]
800545c: 697a ldr r2, [r7, #20]
800545e: 4313 orrs r3, r2
8005460: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8005462: 697b ldr r3, [r7, #20]
8005464: f023 0304 bic.w r3, r3, #4
8005468: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800546a: 687b ldr r3, [r7, #4]
800546c: 4a1b ldr r2, [pc, #108] @ (80054dc <TIM_OC1_SetConfig+0x10c>)
800546e: 4293 cmp r3, r2
8005470: d00f beq.n 8005492 <TIM_OC1_SetConfig+0xc2>
8005472: 687b ldr r3, [r7, #4]
8005474: 4a1a ldr r2, [pc, #104] @ (80054e0 <TIM_OC1_SetConfig+0x110>)
8005476: 4293 cmp r3, r2
8005478: d00b beq.n 8005492 <TIM_OC1_SetConfig+0xc2>
800547a: 687b ldr r3, [r7, #4]
800547c: 4a19 ldr r2, [pc, #100] @ (80054e4 <TIM_OC1_SetConfig+0x114>)
800547e: 4293 cmp r3, r2
8005480: d007 beq.n 8005492 <TIM_OC1_SetConfig+0xc2>
8005482: 687b ldr r3, [r7, #4]
8005484: 4a18 ldr r2, [pc, #96] @ (80054e8 <TIM_OC1_SetConfig+0x118>)
8005486: 4293 cmp r3, r2
8005488: d003 beq.n 8005492 <TIM_OC1_SetConfig+0xc2>
800548a: 687b ldr r3, [r7, #4]
800548c: 4a17 ldr r2, [pc, #92] @ (80054ec <TIM_OC1_SetConfig+0x11c>)
800548e: 4293 cmp r3, r2
8005490: d111 bne.n 80054b6 <TIM_OC1_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8005492: 693b ldr r3, [r7, #16]
8005494: f423 7380 bic.w r3, r3, #256 @ 0x100
8005498: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800549a: 693b ldr r3, [r7, #16]
800549c: f423 7300 bic.w r3, r3, #512 @ 0x200
80054a0: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
80054a2: 683b ldr r3, [r7, #0]
80054a4: 695b ldr r3, [r3, #20]
80054a6: 693a ldr r2, [r7, #16]
80054a8: 4313 orrs r3, r2
80054aa: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
80054ac: 683b ldr r3, [r7, #0]
80054ae: 699b ldr r3, [r3, #24]
80054b0: 693a ldr r2, [r7, #16]
80054b2: 4313 orrs r3, r2
80054b4: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80054b6: 687b ldr r3, [r7, #4]
80054b8: 693a ldr r2, [r7, #16]
80054ba: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80054bc: 687b ldr r3, [r7, #4]
80054be: 68fa ldr r2, [r7, #12]
80054c0: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80054c2: 683b ldr r3, [r7, #0]
80054c4: 685a ldr r2, [r3, #4]
80054c6: 687b ldr r3, [r7, #4]
80054c8: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80054ca: 687b ldr r3, [r7, #4]
80054cc: 697a ldr r2, [r7, #20]
80054ce: 621a str r2, [r3, #32]
}
80054d0: bf00 nop
80054d2: 371c adds r7, #28
80054d4: 46bd mov sp, r7
80054d6: f85d 7b04 ldr.w r7, [sp], #4
80054da: 4770 bx lr
80054dc: 40012c00 .word 0x40012c00
80054e0: 40013400 .word 0x40013400
80054e4: 40014000 .word 0x40014000
80054e8: 40014400 .word 0x40014400
80054ec: 40014800 .word 0x40014800
080054f0 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80054f0: b480 push {r7}
80054f2: b087 sub sp, #28
80054f4: af00 add r7, sp, #0
80054f6: 6078 str r0, [r7, #4]
80054f8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80054fa: 687b ldr r3, [r7, #4]
80054fc: 6a1b ldr r3, [r3, #32]
80054fe: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8005500: 687b ldr r3, [r7, #4]
8005502: 6a1b ldr r3, [r3, #32]
8005504: f023 0210 bic.w r2, r3, #16
8005508: 687b ldr r3, [r7, #4]
800550a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800550c: 687b ldr r3, [r7, #4]
800550e: 685b ldr r3, [r3, #4]
8005510: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8005512: 687b ldr r3, [r7, #4]
8005514: 699b ldr r3, [r3, #24]
8005516: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8005518: 68fb ldr r3, [r7, #12]
800551a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800551e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005522: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8005524: 68fb ldr r3, [r7, #12]
8005526: f423 7340 bic.w r3, r3, #768 @ 0x300
800552a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800552c: 683b ldr r3, [r7, #0]
800552e: 681b ldr r3, [r3, #0]
8005530: 021b lsls r3, r3, #8
8005532: 68fa ldr r2, [r7, #12]
8005534: 4313 orrs r3, r2
8005536: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8005538: 697b ldr r3, [r7, #20]
800553a: f023 0320 bic.w r3, r3, #32
800553e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8005540: 683b ldr r3, [r7, #0]
8005542: 689b ldr r3, [r3, #8]
8005544: 011b lsls r3, r3, #4
8005546: 697a ldr r2, [r7, #20]
8005548: 4313 orrs r3, r2
800554a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800554c: 687b ldr r3, [r7, #4]
800554e: 4a28 ldr r2, [pc, #160] @ (80055f0 <TIM_OC2_SetConfig+0x100>)
8005550: 4293 cmp r3, r2
8005552: d003 beq.n 800555c <TIM_OC2_SetConfig+0x6c>
8005554: 687b ldr r3, [r7, #4]
8005556: 4a27 ldr r2, [pc, #156] @ (80055f4 <TIM_OC2_SetConfig+0x104>)
8005558: 4293 cmp r3, r2
800555a: d10d bne.n 8005578 <TIM_OC2_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800555c: 697b ldr r3, [r7, #20]
800555e: f023 0380 bic.w r3, r3, #128 @ 0x80
8005562: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8005564: 683b ldr r3, [r7, #0]
8005566: 68db ldr r3, [r3, #12]
8005568: 011b lsls r3, r3, #4
800556a: 697a ldr r2, [r7, #20]
800556c: 4313 orrs r3, r2
800556e: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8005570: 697b ldr r3, [r7, #20]
8005572: f023 0340 bic.w r3, r3, #64 @ 0x40
8005576: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005578: 687b ldr r3, [r7, #4]
800557a: 4a1d ldr r2, [pc, #116] @ (80055f0 <TIM_OC2_SetConfig+0x100>)
800557c: 4293 cmp r3, r2
800557e: d00f beq.n 80055a0 <TIM_OC2_SetConfig+0xb0>
8005580: 687b ldr r3, [r7, #4]
8005582: 4a1c ldr r2, [pc, #112] @ (80055f4 <TIM_OC2_SetConfig+0x104>)
8005584: 4293 cmp r3, r2
8005586: d00b beq.n 80055a0 <TIM_OC2_SetConfig+0xb0>
8005588: 687b ldr r3, [r7, #4]
800558a: 4a1b ldr r2, [pc, #108] @ (80055f8 <TIM_OC2_SetConfig+0x108>)
800558c: 4293 cmp r3, r2
800558e: d007 beq.n 80055a0 <TIM_OC2_SetConfig+0xb0>
8005590: 687b ldr r3, [r7, #4]
8005592: 4a1a ldr r2, [pc, #104] @ (80055fc <TIM_OC2_SetConfig+0x10c>)
8005594: 4293 cmp r3, r2
8005596: d003 beq.n 80055a0 <TIM_OC2_SetConfig+0xb0>
8005598: 687b ldr r3, [r7, #4]
800559a: 4a19 ldr r2, [pc, #100] @ (8005600 <TIM_OC2_SetConfig+0x110>)
800559c: 4293 cmp r3, r2
800559e: d113 bne.n 80055c8 <TIM_OC2_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
80055a0: 693b ldr r3, [r7, #16]
80055a2: f423 6380 bic.w r3, r3, #1024 @ 0x400
80055a6: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
80055a8: 693b ldr r3, [r7, #16]
80055aa: f423 6300 bic.w r3, r3, #2048 @ 0x800
80055ae: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
80055b0: 683b ldr r3, [r7, #0]
80055b2: 695b ldr r3, [r3, #20]
80055b4: 009b lsls r3, r3, #2
80055b6: 693a ldr r2, [r7, #16]
80055b8: 4313 orrs r3, r2
80055ba: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
80055bc: 683b ldr r3, [r7, #0]
80055be: 699b ldr r3, [r3, #24]
80055c0: 009b lsls r3, r3, #2
80055c2: 693a ldr r2, [r7, #16]
80055c4: 4313 orrs r3, r2
80055c6: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80055c8: 687b ldr r3, [r7, #4]
80055ca: 693a ldr r2, [r7, #16]
80055cc: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80055ce: 687b ldr r3, [r7, #4]
80055d0: 68fa ldr r2, [r7, #12]
80055d2: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
80055d4: 683b ldr r3, [r7, #0]
80055d6: 685a ldr r2, [r3, #4]
80055d8: 687b ldr r3, [r7, #4]
80055da: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80055dc: 687b ldr r3, [r7, #4]
80055de: 697a ldr r2, [r7, #20]
80055e0: 621a str r2, [r3, #32]
}
80055e2: bf00 nop
80055e4: 371c adds r7, #28
80055e6: 46bd mov sp, r7
80055e8: f85d 7b04 ldr.w r7, [sp], #4
80055ec: 4770 bx lr
80055ee: bf00 nop
80055f0: 40012c00 .word 0x40012c00
80055f4: 40013400 .word 0x40013400
80055f8: 40014000 .word 0x40014000
80055fc: 40014400 .word 0x40014400
8005600: 40014800 .word 0x40014800
08005604 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005604: b480 push {r7}
8005606: b087 sub sp, #28
8005608: af00 add r7, sp, #0
800560a: 6078 str r0, [r7, #4]
800560c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800560e: 687b ldr r3, [r7, #4]
8005610: 6a1b ldr r3, [r3, #32]
8005612: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8005614: 687b ldr r3, [r7, #4]
8005616: 6a1b ldr r3, [r3, #32]
8005618: f423 7280 bic.w r2, r3, #256 @ 0x100
800561c: 687b ldr r3, [r7, #4]
800561e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005620: 687b ldr r3, [r7, #4]
8005622: 685b ldr r3, [r3, #4]
8005624: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005626: 687b ldr r3, [r7, #4]
8005628: 69db ldr r3, [r3, #28]
800562a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800562c: 68fb ldr r3, [r7, #12]
800562e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005632: f023 0370 bic.w r3, r3, #112 @ 0x70
8005636: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8005638: 68fb ldr r3, [r7, #12]
800563a: f023 0303 bic.w r3, r3, #3
800563e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005640: 683b ldr r3, [r7, #0]
8005642: 681b ldr r3, [r3, #0]
8005644: 68fa ldr r2, [r7, #12]
8005646: 4313 orrs r3, r2
8005648: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800564a: 697b ldr r3, [r7, #20]
800564c: f423 7300 bic.w r3, r3, #512 @ 0x200
8005650: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8005652: 683b ldr r3, [r7, #0]
8005654: 689b ldr r3, [r3, #8]
8005656: 021b lsls r3, r3, #8
8005658: 697a ldr r2, [r7, #20]
800565a: 4313 orrs r3, r2
800565c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800565e: 687b ldr r3, [r7, #4]
8005660: 4a27 ldr r2, [pc, #156] @ (8005700 <TIM_OC3_SetConfig+0xfc>)
8005662: 4293 cmp r3, r2
8005664: d003 beq.n 800566e <TIM_OC3_SetConfig+0x6a>
8005666: 687b ldr r3, [r7, #4]
8005668: 4a26 ldr r2, [pc, #152] @ (8005704 <TIM_OC3_SetConfig+0x100>)
800566a: 4293 cmp r3, r2
800566c: d10d bne.n 800568a <TIM_OC3_SetConfig+0x86>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800566e: 697b ldr r3, [r7, #20]
8005670: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005674: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8005676: 683b ldr r3, [r7, #0]
8005678: 68db ldr r3, [r3, #12]
800567a: 021b lsls r3, r3, #8
800567c: 697a ldr r2, [r7, #20]
800567e: 4313 orrs r3, r2
8005680: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8005682: 697b ldr r3, [r7, #20]
8005684: f423 6380 bic.w r3, r3, #1024 @ 0x400
8005688: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800568a: 687b ldr r3, [r7, #4]
800568c: 4a1c ldr r2, [pc, #112] @ (8005700 <TIM_OC3_SetConfig+0xfc>)
800568e: 4293 cmp r3, r2
8005690: d00f beq.n 80056b2 <TIM_OC3_SetConfig+0xae>
8005692: 687b ldr r3, [r7, #4]
8005694: 4a1b ldr r2, [pc, #108] @ (8005704 <TIM_OC3_SetConfig+0x100>)
8005696: 4293 cmp r3, r2
8005698: d00b beq.n 80056b2 <TIM_OC3_SetConfig+0xae>
800569a: 687b ldr r3, [r7, #4]
800569c: 4a1a ldr r2, [pc, #104] @ (8005708 <TIM_OC3_SetConfig+0x104>)
800569e: 4293 cmp r3, r2
80056a0: d007 beq.n 80056b2 <TIM_OC3_SetConfig+0xae>
80056a2: 687b ldr r3, [r7, #4]
80056a4: 4a19 ldr r2, [pc, #100] @ (800570c <TIM_OC3_SetConfig+0x108>)
80056a6: 4293 cmp r3, r2
80056a8: d003 beq.n 80056b2 <TIM_OC3_SetConfig+0xae>
80056aa: 687b ldr r3, [r7, #4]
80056ac: 4a18 ldr r2, [pc, #96] @ (8005710 <TIM_OC3_SetConfig+0x10c>)
80056ae: 4293 cmp r3, r2
80056b0: d113 bne.n 80056da <TIM_OC3_SetConfig+0xd6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
80056b2: 693b ldr r3, [r7, #16]
80056b4: f423 5380 bic.w r3, r3, #4096 @ 0x1000
80056b8: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
80056ba: 693b ldr r3, [r7, #16]
80056bc: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80056c0: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
80056c2: 683b ldr r3, [r7, #0]
80056c4: 695b ldr r3, [r3, #20]
80056c6: 011b lsls r3, r3, #4
80056c8: 693a ldr r2, [r7, #16]
80056ca: 4313 orrs r3, r2
80056cc: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
80056ce: 683b ldr r3, [r7, #0]
80056d0: 699b ldr r3, [r3, #24]
80056d2: 011b lsls r3, r3, #4
80056d4: 693a ldr r2, [r7, #16]
80056d6: 4313 orrs r3, r2
80056d8: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80056da: 687b ldr r3, [r7, #4]
80056dc: 693a ldr r2, [r7, #16]
80056de: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80056e0: 687b ldr r3, [r7, #4]
80056e2: 68fa ldr r2, [r7, #12]
80056e4: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
80056e6: 683b ldr r3, [r7, #0]
80056e8: 685a ldr r2, [r3, #4]
80056ea: 687b ldr r3, [r7, #4]
80056ec: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80056ee: 687b ldr r3, [r7, #4]
80056f0: 697a ldr r2, [r7, #20]
80056f2: 621a str r2, [r3, #32]
}
80056f4: bf00 nop
80056f6: 371c adds r7, #28
80056f8: 46bd mov sp, r7
80056fa: f85d 7b04 ldr.w r7, [sp], #4
80056fe: 4770 bx lr
8005700: 40012c00 .word 0x40012c00
8005704: 40013400 .word 0x40013400
8005708: 40014000 .word 0x40014000
800570c: 40014400 .word 0x40014400
8005710: 40014800 .word 0x40014800
08005714 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005714: b480 push {r7}
8005716: b087 sub sp, #28
8005718: af00 add r7, sp, #0
800571a: 6078 str r0, [r7, #4]
800571c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800571e: 687b ldr r3, [r7, #4]
8005720: 6a1b ldr r3, [r3, #32]
8005722: 617b str r3, [r7, #20]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8005724: 687b ldr r3, [r7, #4]
8005726: 6a1b ldr r3, [r3, #32]
8005728: f423 5280 bic.w r2, r3, #4096 @ 0x1000
800572c: 687b ldr r3, [r7, #4]
800572e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005730: 687b ldr r3, [r7, #4]
8005732: 685b ldr r3, [r3, #4]
8005734: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005736: 687b ldr r3, [r7, #4]
8005738: 69db ldr r3, [r3, #28]
800573a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800573c: 68fb ldr r3, [r7, #12]
800573e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8005742: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005746: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8005748: 68fb ldr r3, [r7, #12]
800574a: f423 7340 bic.w r3, r3, #768 @ 0x300
800574e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005750: 683b ldr r3, [r7, #0]
8005752: 681b ldr r3, [r3, #0]
8005754: 021b lsls r3, r3, #8
8005756: 68fa ldr r2, [r7, #12]
8005758: 4313 orrs r3, r2
800575a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800575c: 697b ldr r3, [r7, #20]
800575e: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8005762: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8005764: 683b ldr r3, [r7, #0]
8005766: 689b ldr r3, [r3, #8]
8005768: 031b lsls r3, r3, #12
800576a: 697a ldr r2, [r7, #20]
800576c: 4313 orrs r3, r2
800576e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
8005770: 687b ldr r3, [r7, #4]
8005772: 4a28 ldr r2, [pc, #160] @ (8005814 <TIM_OC4_SetConfig+0x100>)
8005774: 4293 cmp r3, r2
8005776: d003 beq.n 8005780 <TIM_OC4_SetConfig+0x6c>
8005778: 687b ldr r3, [r7, #4]
800577a: 4a27 ldr r2, [pc, #156] @ (8005818 <TIM_OC4_SetConfig+0x104>)
800577c: 4293 cmp r3, r2
800577e: d10d bne.n 800579c <TIM_OC4_SetConfig+0x88>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC4NP;
8005780: 697b ldr r3, [r7, #20]
8005782: f423 4300 bic.w r3, r3, #32768 @ 0x8000
8005786: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 12U);
8005788: 683b ldr r3, [r7, #0]
800578a: 68db ldr r3, [r3, #12]
800578c: 031b lsls r3, r3, #12
800578e: 697a ldr r2, [r7, #20]
8005790: 4313 orrs r3, r2
8005792: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC4NE;
8005794: 697b ldr r3, [r7, #20]
8005796: f423 4380 bic.w r3, r3, #16384 @ 0x4000
800579a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800579c: 687b ldr r3, [r7, #4]
800579e: 4a1d ldr r2, [pc, #116] @ (8005814 <TIM_OC4_SetConfig+0x100>)
80057a0: 4293 cmp r3, r2
80057a2: d00f beq.n 80057c4 <TIM_OC4_SetConfig+0xb0>
80057a4: 687b ldr r3, [r7, #4]
80057a6: 4a1c ldr r2, [pc, #112] @ (8005818 <TIM_OC4_SetConfig+0x104>)
80057a8: 4293 cmp r3, r2
80057aa: d00b beq.n 80057c4 <TIM_OC4_SetConfig+0xb0>
80057ac: 687b ldr r3, [r7, #4]
80057ae: 4a1b ldr r2, [pc, #108] @ (800581c <TIM_OC4_SetConfig+0x108>)
80057b0: 4293 cmp r3, r2
80057b2: d007 beq.n 80057c4 <TIM_OC4_SetConfig+0xb0>
80057b4: 687b ldr r3, [r7, #4]
80057b6: 4a1a ldr r2, [pc, #104] @ (8005820 <TIM_OC4_SetConfig+0x10c>)
80057b8: 4293 cmp r3, r2
80057ba: d003 beq.n 80057c4 <TIM_OC4_SetConfig+0xb0>
80057bc: 687b ldr r3, [r7, #4]
80057be: 4a19 ldr r2, [pc, #100] @ (8005824 <TIM_OC4_SetConfig+0x110>)
80057c0: 4293 cmp r3, r2
80057c2: d113 bne.n 80057ec <TIM_OC4_SetConfig+0xd8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80057c4: 693b ldr r3, [r7, #16]
80057c6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80057ca: 613b str r3, [r7, #16]
/* Reset the Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4N;
80057cc: 693b ldr r3, [r7, #16]
80057ce: f423 4300 bic.w r3, r3, #32768 @ 0x8000
80057d2: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80057d4: 683b ldr r3, [r7, #0]
80057d6: 695b ldr r3, [r3, #20]
80057d8: 019b lsls r3, r3, #6
80057da: 693a ldr r2, [r7, #16]
80057dc: 4313 orrs r3, r2
80057de: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 6U);
80057e0: 683b ldr r3, [r7, #0]
80057e2: 699b ldr r3, [r3, #24]
80057e4: 019b lsls r3, r3, #6
80057e6: 693a ldr r2, [r7, #16]
80057e8: 4313 orrs r3, r2
80057ea: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80057ec: 687b ldr r3, [r7, #4]
80057ee: 693a ldr r2, [r7, #16]
80057f0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80057f2: 687b ldr r3, [r7, #4]
80057f4: 68fa ldr r2, [r7, #12]
80057f6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80057f8: 683b ldr r3, [r7, #0]
80057fa: 685a ldr r2, [r3, #4]
80057fc: 687b ldr r3, [r7, #4]
80057fe: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005800: 687b ldr r3, [r7, #4]
8005802: 697a ldr r2, [r7, #20]
8005804: 621a str r2, [r3, #32]
}
8005806: bf00 nop
8005808: 371c adds r7, #28
800580a: 46bd mov sp, r7
800580c: f85d 7b04 ldr.w r7, [sp], #4
8005810: 4770 bx lr
8005812: bf00 nop
8005814: 40012c00 .word 0x40012c00
8005818: 40013400 .word 0x40013400
800581c: 40014000 .word 0x40014000
8005820: 40014400 .word 0x40014400
8005824: 40014800 .word 0x40014800
08005828 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8005828: b480 push {r7}
800582a: b087 sub sp, #28
800582c: af00 add r7, sp, #0
800582e: 6078 str r0, [r7, #4]
8005830: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005832: 687b ldr r3, [r7, #4]
8005834: 6a1b ldr r3, [r3, #32]
8005836: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8005838: 687b ldr r3, [r7, #4]
800583a: 6a1b ldr r3, [r3, #32]
800583c: f423 3280 bic.w r2, r3, #65536 @ 0x10000
8005840: 687b ldr r3, [r7, #4]
8005842: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005844: 687b ldr r3, [r7, #4]
8005846: 685b ldr r3, [r3, #4]
8005848: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800584a: 687b ldr r3, [r7, #4]
800584c: 6d1b ldr r3, [r3, #80] @ 0x50
800584e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8005850: 68fb ldr r3, [r7, #12]
8005852: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005856: f023 0370 bic.w r3, r3, #112 @ 0x70
800585a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800585c: 683b ldr r3, [r7, #0]
800585e: 681b ldr r3, [r3, #0]
8005860: 68fa ldr r2, [r7, #12]
8005862: 4313 orrs r3, r2
8005864: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8005866: 693b ldr r3, [r7, #16]
8005868: f423 3300 bic.w r3, r3, #131072 @ 0x20000
800586c: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800586e: 683b ldr r3, [r7, #0]
8005870: 689b ldr r3, [r3, #8]
8005872: 041b lsls r3, r3, #16
8005874: 693a ldr r2, [r7, #16]
8005876: 4313 orrs r3, r2
8005878: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800587a: 687b ldr r3, [r7, #4]
800587c: 4a17 ldr r2, [pc, #92] @ (80058dc <TIM_OC5_SetConfig+0xb4>)
800587e: 4293 cmp r3, r2
8005880: d00f beq.n 80058a2 <TIM_OC5_SetConfig+0x7a>
8005882: 687b ldr r3, [r7, #4]
8005884: 4a16 ldr r2, [pc, #88] @ (80058e0 <TIM_OC5_SetConfig+0xb8>)
8005886: 4293 cmp r3, r2
8005888: d00b beq.n 80058a2 <TIM_OC5_SetConfig+0x7a>
800588a: 687b ldr r3, [r7, #4]
800588c: 4a15 ldr r2, [pc, #84] @ (80058e4 <TIM_OC5_SetConfig+0xbc>)
800588e: 4293 cmp r3, r2
8005890: d007 beq.n 80058a2 <TIM_OC5_SetConfig+0x7a>
8005892: 687b ldr r3, [r7, #4]
8005894: 4a14 ldr r2, [pc, #80] @ (80058e8 <TIM_OC5_SetConfig+0xc0>)
8005896: 4293 cmp r3, r2
8005898: d003 beq.n 80058a2 <TIM_OC5_SetConfig+0x7a>
800589a: 687b ldr r3, [r7, #4]
800589c: 4a13 ldr r2, [pc, #76] @ (80058ec <TIM_OC5_SetConfig+0xc4>)
800589e: 4293 cmp r3, r2
80058a0: d109 bne.n 80058b6 <TIM_OC5_SetConfig+0x8e>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
80058a2: 697b ldr r3, [r7, #20]
80058a4: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80058a8: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
80058aa: 683b ldr r3, [r7, #0]
80058ac: 695b ldr r3, [r3, #20]
80058ae: 021b lsls r3, r3, #8
80058b0: 697a ldr r2, [r7, #20]
80058b2: 4313 orrs r3, r2
80058b4: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80058b6: 687b ldr r3, [r7, #4]
80058b8: 697a ldr r2, [r7, #20]
80058ba: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
80058bc: 687b ldr r3, [r7, #4]
80058be: 68fa ldr r2, [r7, #12]
80058c0: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
80058c2: 683b ldr r3, [r7, #0]
80058c4: 685a ldr r2, [r3, #4]
80058c6: 687b ldr r3, [r7, #4]
80058c8: 649a str r2, [r3, #72] @ 0x48
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80058ca: 687b ldr r3, [r7, #4]
80058cc: 693a ldr r2, [r7, #16]
80058ce: 621a str r2, [r3, #32]
}
80058d0: bf00 nop
80058d2: 371c adds r7, #28
80058d4: 46bd mov sp, r7
80058d6: f85d 7b04 ldr.w r7, [sp], #4
80058da: 4770 bx lr
80058dc: 40012c00 .word 0x40012c00
80058e0: 40013400 .word 0x40013400
80058e4: 40014000 .word 0x40014000
80058e8: 40014400 .word 0x40014400
80058ec: 40014800 .word 0x40014800
080058f0 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80058f0: b480 push {r7}
80058f2: b087 sub sp, #28
80058f4: af00 add r7, sp, #0
80058f6: 6078 str r0, [r7, #4]
80058f8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80058fa: 687b ldr r3, [r7, #4]
80058fc: 6a1b ldr r3, [r3, #32]
80058fe: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8005900: 687b ldr r3, [r7, #4]
8005902: 6a1b ldr r3, [r3, #32]
8005904: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8005908: 687b ldr r3, [r7, #4]
800590a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800590c: 687b ldr r3, [r7, #4]
800590e: 685b ldr r3, [r3, #4]
8005910: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8005912: 687b ldr r3, [r7, #4]
8005914: 6d1b ldr r3, [r3, #80] @ 0x50
8005916: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8005918: 68fb ldr r3, [r7, #12]
800591a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800591e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8005922: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005924: 683b ldr r3, [r7, #0]
8005926: 681b ldr r3, [r3, #0]
8005928: 021b lsls r3, r3, #8
800592a: 68fa ldr r2, [r7, #12]
800592c: 4313 orrs r3, r2
800592e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8005930: 693b ldr r3, [r7, #16]
8005932: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8005936: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8005938: 683b ldr r3, [r7, #0]
800593a: 689b ldr r3, [r3, #8]
800593c: 051b lsls r3, r3, #20
800593e: 693a ldr r2, [r7, #16]
8005940: 4313 orrs r3, r2
8005942: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005944: 687b ldr r3, [r7, #4]
8005946: 4a18 ldr r2, [pc, #96] @ (80059a8 <TIM_OC6_SetConfig+0xb8>)
8005948: 4293 cmp r3, r2
800594a: d00f beq.n 800596c <TIM_OC6_SetConfig+0x7c>
800594c: 687b ldr r3, [r7, #4]
800594e: 4a17 ldr r2, [pc, #92] @ (80059ac <TIM_OC6_SetConfig+0xbc>)
8005950: 4293 cmp r3, r2
8005952: d00b beq.n 800596c <TIM_OC6_SetConfig+0x7c>
8005954: 687b ldr r3, [r7, #4]
8005956: 4a16 ldr r2, [pc, #88] @ (80059b0 <TIM_OC6_SetConfig+0xc0>)
8005958: 4293 cmp r3, r2
800595a: d007 beq.n 800596c <TIM_OC6_SetConfig+0x7c>
800595c: 687b ldr r3, [r7, #4]
800595e: 4a15 ldr r2, [pc, #84] @ (80059b4 <TIM_OC6_SetConfig+0xc4>)
8005960: 4293 cmp r3, r2
8005962: d003 beq.n 800596c <TIM_OC6_SetConfig+0x7c>
8005964: 687b ldr r3, [r7, #4]
8005966: 4a14 ldr r2, [pc, #80] @ (80059b8 <TIM_OC6_SetConfig+0xc8>)
8005968: 4293 cmp r3, r2
800596a: d109 bne.n 8005980 <TIM_OC6_SetConfig+0x90>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
800596c: 697b ldr r3, [r7, #20]
800596e: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005972: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8005974: 683b ldr r3, [r7, #0]
8005976: 695b ldr r3, [r3, #20]
8005978: 029b lsls r3, r3, #10
800597a: 697a ldr r2, [r7, #20]
800597c: 4313 orrs r3, r2
800597e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005980: 687b ldr r3, [r7, #4]
8005982: 697a ldr r2, [r7, #20]
8005984: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8005986: 687b ldr r3, [r7, #4]
8005988: 68fa ldr r2, [r7, #12]
800598a: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
800598c: 683b ldr r3, [r7, #0]
800598e: 685a ldr r2, [r3, #4]
8005990: 687b ldr r3, [r7, #4]
8005992: 64da str r2, [r3, #76] @ 0x4c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005994: 687b ldr r3, [r7, #4]
8005996: 693a ldr r2, [r7, #16]
8005998: 621a str r2, [r3, #32]
}
800599a: bf00 nop
800599c: 371c adds r7, #28
800599e: 46bd mov sp, r7
80059a0: f85d 7b04 ldr.w r7, [sp], #4
80059a4: 4770 bx lr
80059a6: bf00 nop
80059a8: 40012c00 .word 0x40012c00
80059ac: 40013400 .word 0x40013400
80059b0: 40014000 .word 0x40014000
80059b4: 40014400 .word 0x40014400
80059b8: 40014800 .word 0x40014800
080059bc <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80059bc: b480 push {r7}
80059be: b087 sub sp, #28
80059c0: af00 add r7, sp, #0
80059c2: 60f8 str r0, [r7, #12]
80059c4: 60b9 str r1, [r7, #8]
80059c6: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
80059c8: 68fb ldr r3, [r7, #12]
80059ca: 6a1b ldr r3, [r3, #32]
80059cc: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
80059ce: 68fb ldr r3, [r7, #12]
80059d0: 6a1b ldr r3, [r3, #32]
80059d2: f023 0201 bic.w r2, r3, #1
80059d6: 68fb ldr r3, [r7, #12]
80059d8: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80059da: 68fb ldr r3, [r7, #12]
80059dc: 699b ldr r3, [r3, #24]
80059de: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
80059e0: 693b ldr r3, [r7, #16]
80059e2: f023 03f0 bic.w r3, r3, #240 @ 0xf0
80059e6: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
80059e8: 687b ldr r3, [r7, #4]
80059ea: 011b lsls r3, r3, #4
80059ec: 693a ldr r2, [r7, #16]
80059ee: 4313 orrs r3, r2
80059f0: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
80059f2: 697b ldr r3, [r7, #20]
80059f4: f023 030a bic.w r3, r3, #10
80059f8: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
80059fa: 697a ldr r2, [r7, #20]
80059fc: 68bb ldr r3, [r7, #8]
80059fe: 4313 orrs r3, r2
8005a00: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8005a02: 68fb ldr r3, [r7, #12]
8005a04: 693a ldr r2, [r7, #16]
8005a06: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005a08: 68fb ldr r3, [r7, #12]
8005a0a: 697a ldr r2, [r7, #20]
8005a0c: 621a str r2, [r3, #32]
}
8005a0e: bf00 nop
8005a10: 371c adds r7, #28
8005a12: 46bd mov sp, r7
8005a14: f85d 7b04 ldr.w r7, [sp], #4
8005a18: 4770 bx lr
08005a1a <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005a1a: b480 push {r7}
8005a1c: b087 sub sp, #28
8005a1e: af00 add r7, sp, #0
8005a20: 60f8 str r0, [r7, #12]
8005a22: 60b9 str r1, [r7, #8]
8005a24: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8005a26: 68fb ldr r3, [r7, #12]
8005a28: 6a1b ldr r3, [r3, #32]
8005a2a: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8005a2c: 68fb ldr r3, [r7, #12]
8005a2e: 6a1b ldr r3, [r3, #32]
8005a30: f023 0210 bic.w r2, r3, #16
8005a34: 68fb ldr r3, [r7, #12]
8005a36: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005a38: 68fb ldr r3, [r7, #12]
8005a3a: 699b ldr r3, [r3, #24]
8005a3c: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8005a3e: 693b ldr r3, [r7, #16]
8005a40: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8005a44: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8005a46: 687b ldr r3, [r7, #4]
8005a48: 031b lsls r3, r3, #12
8005a4a: 693a ldr r2, [r7, #16]
8005a4c: 4313 orrs r3, r2
8005a4e: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8005a50: 697b ldr r3, [r7, #20]
8005a52: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8005a56: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8005a58: 68bb ldr r3, [r7, #8]
8005a5a: 011b lsls r3, r3, #4
8005a5c: 697a ldr r2, [r7, #20]
8005a5e: 4313 orrs r3, r2
8005a60: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8005a62: 68fb ldr r3, [r7, #12]
8005a64: 693a ldr r2, [r7, #16]
8005a66: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005a68: 68fb ldr r3, [r7, #12]
8005a6a: 697a ldr r2, [r7, #20]
8005a6c: 621a str r2, [r3, #32]
}
8005a6e: bf00 nop
8005a70: 371c adds r7, #28
8005a72: 46bd mov sp, r7
8005a74: f85d 7b04 ldr.w r7, [sp], #4
8005a78: 4770 bx lr
08005a7a <TIM_ITRx_SetConfig>:
* (*) Value not defined in all devices.
*
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8005a7a: b480 push {r7}
8005a7c: b085 sub sp, #20
8005a7e: af00 add r7, sp, #0
8005a80: 6078 str r0, [r7, #4]
8005a82: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8005a84: 687b ldr r3, [r7, #4]
8005a86: 689b ldr r3, [r3, #8]
8005a88: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8005a8a: 68fb ldr r3, [r7, #12]
8005a8c: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
8005a90: f023 0370 bic.w r3, r3, #112 @ 0x70
8005a94: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8005a96: 683a ldr r2, [r7, #0]
8005a98: 68fb ldr r3, [r7, #12]
8005a9a: 4313 orrs r3, r2
8005a9c: f043 0307 orr.w r3, r3, #7
8005aa0: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8005aa2: 687b ldr r3, [r7, #4]
8005aa4: 68fa ldr r2, [r7, #12]
8005aa6: 609a str r2, [r3, #8]
}
8005aa8: bf00 nop
8005aaa: 3714 adds r7, #20
8005aac: 46bd mov sp, r7
8005aae: f85d 7b04 ldr.w r7, [sp], #4
8005ab2: 4770 bx lr
08005ab4 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8005ab4: b480 push {r7}
8005ab6: b087 sub sp, #28
8005ab8: af00 add r7, sp, #0
8005aba: 60f8 str r0, [r7, #12]
8005abc: 60b9 str r1, [r7, #8]
8005abe: 607a str r2, [r7, #4]
8005ac0: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8005ac2: 68fb ldr r3, [r7, #12]
8005ac4: 689b ldr r3, [r3, #8]
8005ac6: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005ac8: 697b ldr r3, [r7, #20]
8005aca: f423 437f bic.w r3, r3, #65280 @ 0xff00
8005ace: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8005ad0: 683b ldr r3, [r7, #0]
8005ad2: 021a lsls r2, r3, #8
8005ad4: 687b ldr r3, [r7, #4]
8005ad6: 431a orrs r2, r3
8005ad8: 68bb ldr r3, [r7, #8]
8005ada: 4313 orrs r3, r2
8005adc: 697a ldr r2, [r7, #20]
8005ade: 4313 orrs r3, r2
8005ae0: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8005ae2: 68fb ldr r3, [r7, #12]
8005ae4: 697a ldr r2, [r7, #20]
8005ae6: 609a str r2, [r3, #8]
}
8005ae8: bf00 nop
8005aea: 371c adds r7, #28
8005aec: 46bd mov sp, r7
8005aee: f85d 7b04 ldr.w r7, [sp], #4
8005af2: 4770 bx lr
08005af4 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8005af4: b480 push {r7}
8005af6: b087 sub sp, #28
8005af8: af00 add r7, sp, #0
8005afa: 60f8 str r0, [r7, #12]
8005afc: 60b9 str r1, [r7, #8]
8005afe: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8005b00: 68bb ldr r3, [r7, #8]
8005b02: f003 031f and.w r3, r3, #31
8005b06: 2201 movs r2, #1
8005b08: fa02 f303 lsl.w r3, r2, r3
8005b0c: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8005b0e: 68fb ldr r3, [r7, #12]
8005b10: 6a1a ldr r2, [r3, #32]
8005b12: 697b ldr r3, [r7, #20]
8005b14: 43db mvns r3, r3
8005b16: 401a ands r2, r3
8005b18: 68fb ldr r3, [r7, #12]
8005b1a: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8005b1c: 68fb ldr r3, [r7, #12]
8005b1e: 6a1a ldr r2, [r3, #32]
8005b20: 68bb ldr r3, [r7, #8]
8005b22: f003 031f and.w r3, r3, #31
8005b26: 6879 ldr r1, [r7, #4]
8005b28: fa01 f303 lsl.w r3, r1, r3
8005b2c: 431a orrs r2, r3
8005b2e: 68fb ldr r3, [r7, #12]
8005b30: 621a str r2, [r3, #32]
}
8005b32: bf00 nop
8005b34: 371c adds r7, #28
8005b36: 46bd mov sp, r7
8005b38: f85d 7b04 ldr.w r7, [sp], #4
8005b3c: 4770 bx lr
...
08005b40 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8005b40: b480 push {r7}
8005b42: b085 sub sp, #20
8005b44: af00 add r7, sp, #0
8005b46: 6078 str r0, [r7, #4]
8005b48: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8005b4a: 687b ldr r3, [r7, #4]
8005b4c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005b50: 2b01 cmp r3, #1
8005b52: d101 bne.n 8005b58 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8005b54: 2302 movs r3, #2
8005b56: e065 b.n 8005c24 <HAL_TIMEx_MasterConfigSynchronization+0xe4>
8005b58: 687b ldr r3, [r7, #4]
8005b5a: 2201 movs r2, #1
8005b5c: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8005b60: 687b ldr r3, [r7, #4]
8005b62: 2202 movs r2, #2
8005b64: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8005b68: 687b ldr r3, [r7, #4]
8005b6a: 681b ldr r3, [r3, #0]
8005b6c: 685b ldr r3, [r3, #4]
8005b6e: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8005b70: 687b ldr r3, [r7, #4]
8005b72: 681b ldr r3, [r3, #0]
8005b74: 689b ldr r3, [r3, #8]
8005b76: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8005b78: 687b ldr r3, [r7, #4]
8005b7a: 681b ldr r3, [r3, #0]
8005b7c: 4a2c ldr r2, [pc, #176] @ (8005c30 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8005b7e: 4293 cmp r3, r2
8005b80: d004 beq.n 8005b8c <HAL_TIMEx_MasterConfigSynchronization+0x4c>
8005b82: 687b ldr r3, [r7, #4]
8005b84: 681b ldr r3, [r3, #0]
8005b86: 4a2b ldr r2, [pc, #172] @ (8005c34 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8005b88: 4293 cmp r3, r2
8005b8a: d108 bne.n 8005b9e <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8005b8c: 68fb ldr r3, [r7, #12]
8005b8e: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
8005b92: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8005b94: 683b ldr r3, [r7, #0]
8005b96: 685b ldr r3, [r3, #4]
8005b98: 68fa ldr r2, [r7, #12]
8005b9a: 4313 orrs r3, r2
8005b9c: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8005b9e: 68fb ldr r3, [r7, #12]
8005ba0: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000
8005ba4: f023 0370 bic.w r3, r3, #112 @ 0x70
8005ba8: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8005baa: 683b ldr r3, [r7, #0]
8005bac: 681b ldr r3, [r3, #0]
8005bae: 68fa ldr r2, [r7, #12]
8005bb0: 4313 orrs r3, r2
8005bb2: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8005bb4: 687b ldr r3, [r7, #4]
8005bb6: 681b ldr r3, [r3, #0]
8005bb8: 68fa ldr r2, [r7, #12]
8005bba: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005bbc: 687b ldr r3, [r7, #4]
8005bbe: 681b ldr r3, [r3, #0]
8005bc0: 4a1b ldr r2, [pc, #108] @ (8005c30 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8005bc2: 4293 cmp r3, r2
8005bc4: d018 beq.n 8005bf8 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8005bc6: 687b ldr r3, [r7, #4]
8005bc8: 681b ldr r3, [r3, #0]
8005bca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005bce: d013 beq.n 8005bf8 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8005bd0: 687b ldr r3, [r7, #4]
8005bd2: 681b ldr r3, [r3, #0]
8005bd4: 4a18 ldr r2, [pc, #96] @ (8005c38 <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
8005bd6: 4293 cmp r3, r2
8005bd8: d00e beq.n 8005bf8 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8005bda: 687b ldr r3, [r7, #4]
8005bdc: 681b ldr r3, [r3, #0]
8005bde: 4a17 ldr r2, [pc, #92] @ (8005c3c <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
8005be0: 4293 cmp r3, r2
8005be2: d009 beq.n 8005bf8 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8005be4: 687b ldr r3, [r7, #4]
8005be6: 681b ldr r3, [r3, #0]
8005be8: 4a12 ldr r2, [pc, #72] @ (8005c34 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8005bea: 4293 cmp r3, r2
8005bec: d004 beq.n 8005bf8 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
8005bee: 687b ldr r3, [r7, #4]
8005bf0: 681b ldr r3, [r3, #0]
8005bf2: 4a13 ldr r2, [pc, #76] @ (8005c40 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8005bf4: 4293 cmp r3, r2
8005bf6: d10c bne.n 8005c12 <HAL_TIMEx_MasterConfigSynchronization+0xd2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8005bf8: 68bb ldr r3, [r7, #8]
8005bfa: f023 0380 bic.w r3, r3, #128 @ 0x80
8005bfe: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8005c00: 683b ldr r3, [r7, #0]
8005c02: 689b ldr r3, [r3, #8]
8005c04: 68ba ldr r2, [r7, #8]
8005c06: 4313 orrs r3, r2
8005c08: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005c0a: 687b ldr r3, [r7, #4]
8005c0c: 681b ldr r3, [r3, #0]
8005c0e: 68ba ldr r2, [r7, #8]
8005c10: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005c12: 687b ldr r3, [r7, #4]
8005c14: 2201 movs r2, #1
8005c16: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005c1a: 687b ldr r3, [r7, #4]
8005c1c: 2200 movs r2, #0
8005c1e: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8005c22: 2300 movs r3, #0
}
8005c24: 4618 mov r0, r3
8005c26: 3714 adds r7, #20
8005c28: 46bd mov sp, r7
8005c2a: f85d 7b04 ldr.w r7, [sp], #4
8005c2e: 4770 bx lr
8005c30: 40012c00 .word 0x40012c00
8005c34: 40013400 .word 0x40013400
8005c38: 40000400 .word 0x40000400
8005c3c: 40000800 .word 0x40000800
8005c40: 40014000 .word 0x40014000
08005c44 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8005c44: b480 push {r7}
8005c46: b085 sub sp, #20
8005c48: af00 add r7, sp, #0
8005c4a: 6078 str r0, [r7, #4]
8005c4c: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8005c4e: 2300 movs r3, #0
8005c50: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
8005c52: 687b ldr r3, [r7, #4]
8005c54: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005c58: 2b01 cmp r3, #1
8005c5a: d101 bne.n 8005c60 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8005c5c: 2302 movs r3, #2
8005c5e: e073 b.n 8005d48 <HAL_TIMEx_ConfigBreakDeadTime+0x104>
8005c60: 687b ldr r3, [r7, #4]
8005c62: 2201 movs r2, #1
8005c64: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8005c68: 68fb ldr r3, [r7, #12]
8005c6a: f023 02ff bic.w r2, r3, #255 @ 0xff
8005c6e: 683b ldr r3, [r7, #0]
8005c70: 68db ldr r3, [r3, #12]
8005c72: 4313 orrs r3, r2
8005c74: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8005c76: 68fb ldr r3, [r7, #12]
8005c78: f423 7240 bic.w r2, r3, #768 @ 0x300
8005c7c: 683b ldr r3, [r7, #0]
8005c7e: 689b ldr r3, [r3, #8]
8005c80: 4313 orrs r3, r2
8005c82: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8005c84: 68fb ldr r3, [r7, #12]
8005c86: f423 6280 bic.w r2, r3, #1024 @ 0x400
8005c8a: 683b ldr r3, [r7, #0]
8005c8c: 685b ldr r3, [r3, #4]
8005c8e: 4313 orrs r3, r2
8005c90: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8005c92: 68fb ldr r3, [r7, #12]
8005c94: f423 6200 bic.w r2, r3, #2048 @ 0x800
8005c98: 683b ldr r3, [r7, #0]
8005c9a: 681b ldr r3, [r3, #0]
8005c9c: 4313 orrs r3, r2
8005c9e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8005ca0: 68fb ldr r3, [r7, #12]
8005ca2: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8005ca6: 683b ldr r3, [r7, #0]
8005ca8: 691b ldr r3, [r3, #16]
8005caa: 4313 orrs r3, r2
8005cac: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8005cae: 68fb ldr r3, [r7, #12]
8005cb0: f423 5200 bic.w r2, r3, #8192 @ 0x2000
8005cb4: 683b ldr r3, [r7, #0]
8005cb6: 695b ldr r3, [r3, #20]
8005cb8: 4313 orrs r3, r2
8005cba: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8005cbc: 68fb ldr r3, [r7, #12]
8005cbe: f423 4280 bic.w r2, r3, #16384 @ 0x4000
8005cc2: 683b ldr r3, [r7, #0]
8005cc4: 6b1b ldr r3, [r3, #48] @ 0x30
8005cc6: 4313 orrs r3, r2
8005cc8: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
8005cca: 68fb ldr r3, [r7, #12]
8005ccc: f423 2270 bic.w r2, r3, #983040 @ 0xf0000
8005cd0: 683b ldr r3, [r7, #0]
8005cd2: 699b ldr r3, [r3, #24]
8005cd4: 041b lsls r3, r3, #16
8005cd6: 4313 orrs r3, r2
8005cd8: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
8005cda: 68fb ldr r3, [r7, #12]
8005cdc: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
8005ce0: 683b ldr r3, [r7, #0]
8005ce2: 69db ldr r3, [r3, #28]
8005ce4: 4313 orrs r3, r2
8005ce6: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
8005ce8: 687b ldr r3, [r7, #4]
8005cea: 681b ldr r3, [r3, #0]
8005cec: 4a19 ldr r2, [pc, #100] @ (8005d54 <HAL_TIMEx_ConfigBreakDeadTime+0x110>)
8005cee: 4293 cmp r3, r2
8005cf0: d004 beq.n 8005cfc <HAL_TIMEx_ConfigBreakDeadTime+0xb8>
8005cf2: 687b ldr r3, [r7, #4]
8005cf4: 681b ldr r3, [r3, #0]
8005cf6: 4a18 ldr r2, [pc, #96] @ (8005d58 <HAL_TIMEx_ConfigBreakDeadTime+0x114>)
8005cf8: 4293 cmp r3, r2
8005cfa: d11c bne.n 8005d36 <HAL_TIMEx_ConfigBreakDeadTime+0xf2>
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
8005cfc: 68fb ldr r3, [r7, #12]
8005cfe: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000
8005d02: 683b ldr r3, [r7, #0]
8005d04: 6a9b ldr r3, [r3, #40] @ 0x28
8005d06: 051b lsls r3, r3, #20
8005d08: 4313 orrs r3, r2
8005d0a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
8005d0c: 68fb ldr r3, [r7, #12]
8005d0e: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
8005d12: 683b ldr r3, [r7, #0]
8005d14: 6a1b ldr r3, [r3, #32]
8005d16: 4313 orrs r3, r2
8005d18: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
8005d1a: 68fb ldr r3, [r7, #12]
8005d1c: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
8005d20: 683b ldr r3, [r7, #0]
8005d22: 6a5b ldr r3, [r3, #36] @ 0x24
8005d24: 4313 orrs r3, r2
8005d26: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
8005d28: 68fb ldr r3, [r7, #12]
8005d2a: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
8005d2e: 683b ldr r3, [r7, #0]
8005d30: 6adb ldr r3, [r3, #44] @ 0x2c
8005d32: 4313 orrs r3, r2
8005d34: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8005d36: 687b ldr r3, [r7, #4]
8005d38: 681b ldr r3, [r3, #0]
8005d3a: 68fa ldr r2, [r7, #12]
8005d3c: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
8005d3e: 687b ldr r3, [r7, #4]
8005d40: 2200 movs r2, #0
8005d42: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8005d46: 2300 movs r3, #0
}
8005d48: 4618 mov r0, r3
8005d4a: 3714 adds r7, #20
8005d4c: 46bd mov sp, r7
8005d4e: f85d 7b04 ldr.w r7, [sp], #4
8005d52: 4770 bx lr
8005d54: 40012c00 .word 0x40012c00
8005d58: 40013400 .word 0x40013400
08005d5c <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8005d5c: b480 push {r7}
8005d5e: b083 sub sp, #12
8005d60: af00 add r7, sp, #0
8005d62: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8005d64: bf00 nop
8005d66: 370c adds r7, #12
8005d68: 46bd mov sp, r7
8005d6a: f85d 7b04 ldr.w r7, [sp], #4
8005d6e: 4770 bx lr
08005d70 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8005d70: b480 push {r7}
8005d72: b083 sub sp, #12
8005d74: af00 add r7, sp, #0
8005d76: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8005d78: bf00 nop
8005d7a: 370c adds r7, #12
8005d7c: 46bd mov sp, r7
8005d7e: f85d 7b04 ldr.w r7, [sp], #4
8005d82: 4770 bx lr
08005d84 <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8005d84: b480 push {r7}
8005d86: b083 sub sp, #12
8005d88: af00 add r7, sp, #0
8005d8a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8005d8c: bf00 nop
8005d8e: 370c adds r7, #12
8005d90: 46bd mov sp, r7
8005d92: f85d 7b04 ldr.w r7, [sp], #4
8005d96: 4770 bx lr
08005d98 <HAL_TIMEx_EncoderIndexCallback>:
* @brief Encoder index callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
{
8005d98: b480 push {r7}
8005d9a: b083 sub sp, #12
8005d9c: af00 add r7, sp, #0
8005d9e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
*/
}
8005da0: bf00 nop
8005da2: 370c adds r7, #12
8005da4: 46bd mov sp, r7
8005da6: f85d 7b04 ldr.w r7, [sp], #4
8005daa: 4770 bx lr
08005dac <HAL_TIMEx_DirectionChangeCallback>:
* @brief Direction change callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
{
8005dac: b480 push {r7}
8005dae: b083 sub sp, #12
8005db0: af00 add r7, sp, #0
8005db2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
*/
}
8005db4: bf00 nop
8005db6: 370c adds r7, #12
8005db8: 46bd mov sp, r7
8005dba: f85d 7b04 ldr.w r7, [sp], #4
8005dbe: 4770 bx lr
08005dc0 <HAL_TIMEx_IndexErrorCallback>:
* @brief Index error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
{
8005dc0: b480 push {r7}
8005dc2: b083 sub sp, #12
8005dc4: af00 add r7, sp, #0
8005dc6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
*/
}
8005dc8: bf00 nop
8005dca: 370c adds r7, #12
8005dcc: 46bd mov sp, r7
8005dce: f85d 7b04 ldr.w r7, [sp], #4
8005dd2: 4770 bx lr
08005dd4 <HAL_TIMEx_TransitionErrorCallback>:
* @brief Transition error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
{
8005dd4: b480 push {r7}
8005dd6: b083 sub sp, #12
8005dd8: af00 add r7, sp, #0
8005dda: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
*/
}
8005ddc: bf00 nop
8005dde: 370c adds r7, #12
8005de0: 46bd mov sp, r7
8005de2: f85d 7b04 ldr.w r7, [sp], #4
8005de6: 4770 bx lr
08005de8 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8005de8: b580 push {r7, lr}
8005dea: b082 sub sp, #8
8005dec: af00 add r7, sp, #0
8005dee: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005df0: 687b ldr r3, [r7, #4]
8005df2: 2b00 cmp r3, #0
8005df4: d101 bne.n 8005dfa <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8005df6: 2301 movs r3, #1
8005df8: e042 b.n 8005e80 <HAL_UART_Init+0x98>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
8005dfa: 687b ldr r3, [r7, #4]
8005dfc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005e00: 2b00 cmp r3, #0
8005e02: d106 bne.n 8005e12 <HAL_UART_Init+0x2a>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8005e04: 687b ldr r3, [r7, #4]
8005e06: 2200 movs r2, #0
8005e08: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8005e0c: 6878 ldr r0, [r7, #4]
8005e0e: f7fb fbb1 bl 8001574 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8005e12: 687b ldr r3, [r7, #4]
8005e14: 2224 movs r2, #36 @ 0x24
8005e16: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UART_DISABLE(huart);
8005e1a: 687b ldr r3, [r7, #4]
8005e1c: 681b ldr r3, [r3, #0]
8005e1e: 681a ldr r2, [r3, #0]
8005e20: 687b ldr r3, [r7, #4]
8005e22: 681b ldr r3, [r3, #0]
8005e24: f022 0201 bic.w r2, r2, #1
8005e28: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8005e2a: 687b ldr r3, [r7, #4]
8005e2c: 6a9b ldr r3, [r3, #40] @ 0x28
8005e2e: 2b00 cmp r3, #0
8005e30: d002 beq.n 8005e38 <HAL_UART_Init+0x50>
{
UART_AdvFeatureConfig(huart);
8005e32: 6878 ldr r0, [r7, #4]
8005e34: f000 ff26 bl 8006c84 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8005e38: 6878 ldr r0, [r7, #4]
8005e3a: f000 fc57 bl 80066ec <UART_SetConfig>
8005e3e: 4603 mov r3, r0
8005e40: 2b01 cmp r3, #1
8005e42: d101 bne.n 8005e48 <HAL_UART_Init+0x60>
{
return HAL_ERROR;
8005e44: 2301 movs r3, #1
8005e46: e01b b.n 8005e80 <HAL_UART_Init+0x98>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8005e48: 687b ldr r3, [r7, #4]
8005e4a: 681b ldr r3, [r3, #0]
8005e4c: 685a ldr r2, [r3, #4]
8005e4e: 687b ldr r3, [r7, #4]
8005e50: 681b ldr r3, [r3, #0]
8005e52: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005e56: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005e58: 687b ldr r3, [r7, #4]
8005e5a: 681b ldr r3, [r3, #0]
8005e5c: 689a ldr r2, [r3, #8]
8005e5e: 687b ldr r3, [r7, #4]
8005e60: 681b ldr r3, [r3, #0]
8005e62: f022 022a bic.w r2, r2, #42 @ 0x2a
8005e66: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8005e68: 687b ldr r3, [r7, #4]
8005e6a: 681b ldr r3, [r3, #0]
8005e6c: 681a ldr r2, [r3, #0]
8005e6e: 687b ldr r3, [r7, #4]
8005e70: 681b ldr r3, [r3, #0]
8005e72: f042 0201 orr.w r2, r2, #1
8005e76: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8005e78: 6878 ldr r0, [r7, #4]
8005e7a: f000 ffa5 bl 8006dc8 <UART_CheckIdleState>
8005e7e: 4603 mov r3, r0
}
8005e80: 4618 mov r0, r3
8005e82: 3708 adds r7, #8
8005e84: 46bd mov sp, r7
8005e86: bd80 pop {r7, pc}
08005e88 <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8005e88: b580 push {r7, lr}
8005e8a: b08a sub sp, #40 @ 0x28
8005e8c: af02 add r7, sp, #8
8005e8e: 60f8 str r0, [r7, #12]
8005e90: 60b9 str r1, [r7, #8]
8005e92: 603b str r3, [r7, #0]
8005e94: 4613 mov r3, r2
8005e96: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8005e98: 68fb ldr r3, [r7, #12]
8005e9a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8005e9e: 2b20 cmp r3, #32
8005ea0: d17b bne.n 8005f9a <HAL_UART_Transmit+0x112>
{
if ((pData == NULL) || (Size == 0U))
8005ea2: 68bb ldr r3, [r7, #8]
8005ea4: 2b00 cmp r3, #0
8005ea6: d002 beq.n 8005eae <HAL_UART_Transmit+0x26>
8005ea8: 88fb ldrh r3, [r7, #6]
8005eaa: 2b00 cmp r3, #0
8005eac: d101 bne.n 8005eb2 <HAL_UART_Transmit+0x2a>
{
return HAL_ERROR;
8005eae: 2301 movs r3, #1
8005eb0: e074 b.n 8005f9c <HAL_UART_Transmit+0x114>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005eb2: 68fb ldr r3, [r7, #12]
8005eb4: 2200 movs r2, #0
8005eb6: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->gState = HAL_UART_STATE_BUSY_TX;
8005eba: 68fb ldr r3, [r7, #12]
8005ebc: 2221 movs r2, #33 @ 0x21
8005ebe: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8005ec2: f7fb fc9b bl 80017fc <HAL_GetTick>
8005ec6: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8005ec8: 68fb ldr r3, [r7, #12]
8005eca: 88fa ldrh r2, [r7, #6]
8005ecc: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
huart->TxXferCount = Size;
8005ed0: 68fb ldr r3, [r7, #12]
8005ed2: 88fa ldrh r2, [r7, #6]
8005ed4: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005ed8: 68fb ldr r3, [r7, #12]
8005eda: 689b ldr r3, [r3, #8]
8005edc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005ee0: d108 bne.n 8005ef4 <HAL_UART_Transmit+0x6c>
8005ee2: 68fb ldr r3, [r7, #12]
8005ee4: 691b ldr r3, [r3, #16]
8005ee6: 2b00 cmp r3, #0
8005ee8: d104 bne.n 8005ef4 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
8005eea: 2300 movs r3, #0
8005eec: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8005eee: 68bb ldr r3, [r7, #8]
8005ef0: 61bb str r3, [r7, #24]
8005ef2: e003 b.n 8005efc <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8005ef4: 68bb ldr r3, [r7, #8]
8005ef6: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8005ef8: 2300 movs r3, #0
8005efa: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8005efc: e030 b.n 8005f60 <HAL_UART_Transmit+0xd8>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8005efe: 683b ldr r3, [r7, #0]
8005f00: 9300 str r3, [sp, #0]
8005f02: 697b ldr r3, [r7, #20]
8005f04: 2200 movs r2, #0
8005f06: 2180 movs r1, #128 @ 0x80
8005f08: 68f8 ldr r0, [r7, #12]
8005f0a: f001 f807 bl 8006f1c <UART_WaitOnFlagUntilTimeout>
8005f0e: 4603 mov r3, r0
8005f10: 2b00 cmp r3, #0
8005f12: d005 beq.n 8005f20 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8005f14: 68fb ldr r3, [r7, #12]
8005f16: 2220 movs r2, #32
8005f18: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
8005f1c: 2303 movs r3, #3
8005f1e: e03d b.n 8005f9c <HAL_UART_Transmit+0x114>
}
if (pdata8bits == NULL)
8005f20: 69fb ldr r3, [r7, #28]
8005f22: 2b00 cmp r3, #0
8005f24: d10b bne.n 8005f3e <HAL_UART_Transmit+0xb6>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8005f26: 69bb ldr r3, [r7, #24]
8005f28: 881b ldrh r3, [r3, #0]
8005f2a: 461a mov r2, r3
8005f2c: 68fb ldr r3, [r7, #12]
8005f2e: 681b ldr r3, [r3, #0]
8005f30: f3c2 0208 ubfx r2, r2, #0, #9
8005f34: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
8005f36: 69bb ldr r3, [r7, #24]
8005f38: 3302 adds r3, #2
8005f3a: 61bb str r3, [r7, #24]
8005f3c: e007 b.n 8005f4e <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8005f3e: 69fb ldr r3, [r7, #28]
8005f40: 781a ldrb r2, [r3, #0]
8005f42: 68fb ldr r3, [r7, #12]
8005f44: 681b ldr r3, [r3, #0]
8005f46: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
8005f48: 69fb ldr r3, [r7, #28]
8005f4a: 3301 adds r3, #1
8005f4c: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8005f4e: 68fb ldr r3, [r7, #12]
8005f50: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
8005f54: b29b uxth r3, r3
8005f56: 3b01 subs r3, #1
8005f58: b29a uxth r2, r3
8005f5a: 68fb ldr r3, [r7, #12]
8005f5c: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
while (huart->TxXferCount > 0U)
8005f60: 68fb ldr r3, [r7, #12]
8005f62: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
8005f66: b29b uxth r3, r3
8005f68: 2b00 cmp r3, #0
8005f6a: d1c8 bne.n 8005efe <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8005f6c: 683b ldr r3, [r7, #0]
8005f6e: 9300 str r3, [sp, #0]
8005f70: 697b ldr r3, [r7, #20]
8005f72: 2200 movs r2, #0
8005f74: 2140 movs r1, #64 @ 0x40
8005f76: 68f8 ldr r0, [r7, #12]
8005f78: f000 ffd0 bl 8006f1c <UART_WaitOnFlagUntilTimeout>
8005f7c: 4603 mov r3, r0
8005f7e: 2b00 cmp r3, #0
8005f80: d005 beq.n 8005f8e <HAL_UART_Transmit+0x106>
{
huart->gState = HAL_UART_STATE_READY;
8005f82: 68fb ldr r3, [r7, #12]
8005f84: 2220 movs r2, #32
8005f86: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
8005f8a: 2303 movs r3, #3
8005f8c: e006 b.n 8005f9c <HAL_UART_Transmit+0x114>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8005f8e: 68fb ldr r3, [r7, #12]
8005f90: 2220 movs r2, #32
8005f92: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_OK;
8005f96: 2300 movs r3, #0
8005f98: e000 b.n 8005f9c <HAL_UART_Transmit+0x114>
}
else
{
return HAL_BUSY;
8005f9a: 2302 movs r3, #2
}
}
8005f9c: 4618 mov r0, r3
8005f9e: 3720 adds r7, #32
8005fa0: 46bd mov sp, r7
8005fa2: bd80 pop {r7, pc}
08005fa4 <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8005fa4: b580 push {r7, lr}
8005fa6: b08a sub sp, #40 @ 0x28
8005fa8: af00 add r7, sp, #0
8005faa: 60f8 str r0, [r7, #12]
8005fac: 60b9 str r1, [r7, #8]
8005fae: 4613 mov r3, r2
8005fb0: 80fb strh r3, [r7, #6]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8005fb2: 68fb ldr r3, [r7, #12]
8005fb4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8005fb8: 2b20 cmp r3, #32
8005fba: d137 bne.n 800602c <HAL_UART_Receive_IT+0x88>
{
if ((pData == NULL) || (Size == 0U))
8005fbc: 68bb ldr r3, [r7, #8]
8005fbe: 2b00 cmp r3, #0
8005fc0: d002 beq.n 8005fc8 <HAL_UART_Receive_IT+0x24>
8005fc2: 88fb ldrh r3, [r7, #6]
8005fc4: 2b00 cmp r3, #0
8005fc6: d101 bne.n 8005fcc <HAL_UART_Receive_IT+0x28>
{
return HAL_ERROR;
8005fc8: 2301 movs r3, #1
8005fca: e030 b.n 800602e <HAL_UART_Receive_IT+0x8a>
}
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005fcc: 68fb ldr r3, [r7, #12]
8005fce: 2200 movs r2, #0
8005fd0: 66da str r2, [r3, #108] @ 0x6c
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8005fd2: 68fb ldr r3, [r7, #12]
8005fd4: 681b ldr r3, [r3, #0]
8005fd6: 4a18 ldr r2, [pc, #96] @ (8006038 <HAL_UART_Receive_IT+0x94>)
8005fd8: 4293 cmp r3, r2
8005fda: d01f beq.n 800601c <HAL_UART_Receive_IT+0x78>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8005fdc: 68fb ldr r3, [r7, #12]
8005fde: 681b ldr r3, [r3, #0]
8005fe0: 685b ldr r3, [r3, #4]
8005fe2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8005fe6: 2b00 cmp r3, #0
8005fe8: d018 beq.n 800601c <HAL_UART_Receive_IT+0x78>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8005fea: 68fb ldr r3, [r7, #12]
8005fec: 681b ldr r3, [r3, #0]
8005fee: 617b str r3, [r7, #20]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8005ff0: 697b ldr r3, [r7, #20]
8005ff2: e853 3f00 ldrex r3, [r3]
8005ff6: 613b str r3, [r7, #16]
return(result);
8005ff8: 693b ldr r3, [r7, #16]
8005ffa: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8005ffe: 627b str r3, [r7, #36] @ 0x24
8006000: 68fb ldr r3, [r7, #12]
8006002: 681b ldr r3, [r3, #0]
8006004: 461a mov r2, r3
8006006: 6a7b ldr r3, [r7, #36] @ 0x24
8006008: 623b str r3, [r7, #32]
800600a: 61fa str r2, [r7, #28]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800600c: 69f9 ldr r1, [r7, #28]
800600e: 6a3a ldr r2, [r7, #32]
8006010: e841 2300 strex r3, r2, [r1]
8006014: 61bb str r3, [r7, #24]
return(result);
8006016: 69bb ldr r3, [r7, #24]
8006018: 2b00 cmp r3, #0
800601a: d1e6 bne.n 8005fea <HAL_UART_Receive_IT+0x46>
}
}
return (UART_Start_Receive_IT(huart, pData, Size));
800601c: 88fb ldrh r3, [r7, #6]
800601e: 461a mov r2, r3
8006020: 68b9 ldr r1, [r7, #8]
8006022: 68f8 ldr r0, [r7, #12]
8006024: f000 ffe8 bl 8006ff8 <UART_Start_Receive_IT>
8006028: 4603 mov r3, r0
800602a: e000 b.n 800602e <HAL_UART_Receive_IT+0x8a>
}
else
{
return HAL_BUSY;
800602c: 2302 movs r3, #2
}
}
800602e: 4618 mov r0, r3
8006030: 3728 adds r7, #40 @ 0x28
8006032: 46bd mov sp, r7
8006034: bd80 pop {r7, pc}
8006036: bf00 nop
8006038: 40008000 .word 0x40008000
0800603c <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
800603c: b580 push {r7, lr}
800603e: b0ba sub sp, #232 @ 0xe8
8006040: af00 add r7, sp, #0
8006042: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8006044: 687b ldr r3, [r7, #4]
8006046: 681b ldr r3, [r3, #0]
8006048: 69db ldr r3, [r3, #28]
800604a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
800604e: 687b ldr r3, [r7, #4]
8006050: 681b ldr r3, [r3, #0]
8006052: 681b ldr r3, [r3, #0]
8006054: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8006058: 687b ldr r3, [r7, #4]
800605a: 681b ldr r3, [r3, #0]
800605c: 689b ldr r3, [r3, #8]
800605e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
8006062: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
8006066: f640 030f movw r3, #2063 @ 0x80f
800606a: 4013 ands r3, r2
800606c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (errorflags == 0U)
8006070: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
8006074: 2b00 cmp r3, #0
8006076: d11b bne.n 80060b0 <HAL_UART_IRQHandler+0x74>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8006078: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800607c: f003 0320 and.w r3, r3, #32
8006080: 2b00 cmp r3, #0
8006082: d015 beq.n 80060b0 <HAL_UART_IRQHandler+0x74>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
8006084: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006088: f003 0320 and.w r3, r3, #32
800608c: 2b00 cmp r3, #0
800608e: d105 bne.n 800609c <HAL_UART_IRQHandler+0x60>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8006090: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006094: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006098: 2b00 cmp r3, #0
800609a: d009 beq.n 80060b0 <HAL_UART_IRQHandler+0x74>
{
if (huart->RxISR != NULL)
800609c: 687b ldr r3, [r7, #4]
800609e: 6f5b ldr r3, [r3, #116] @ 0x74
80060a0: 2b00 cmp r3, #0
80060a2: f000 8300 beq.w 80066a6 <HAL_UART_IRQHandler+0x66a>
{
huart->RxISR(huart);
80060a6: 687b ldr r3, [r7, #4]
80060a8: 6f5b ldr r3, [r3, #116] @ 0x74
80060aa: 6878 ldr r0, [r7, #4]
80060ac: 4798 blx r3
}
return;
80060ae: e2fa b.n 80066a6 <HAL_UART_IRQHandler+0x66a>
}
}
/* If some errors occur */
if ((errorflags != 0U)
80060b0: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
80060b4: 2b00 cmp r3, #0
80060b6: f000 8123 beq.w 8006300 <HAL_UART_IRQHandler+0x2c4>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
80060ba: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
80060be: 4b8d ldr r3, [pc, #564] @ (80062f4 <HAL_UART_IRQHandler+0x2b8>)
80060c0: 4013 ands r3, r2
80060c2: 2b00 cmp r3, #0
80060c4: d106 bne.n 80060d4 <HAL_UART_IRQHandler+0x98>
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
80060c6: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
80060ca: 4b8b ldr r3, [pc, #556] @ (80062f8 <HAL_UART_IRQHandler+0x2bc>)
80060cc: 4013 ands r3, r2
80060ce: 2b00 cmp r3, #0
80060d0: f000 8116 beq.w 8006300 <HAL_UART_IRQHandler+0x2c4>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
80060d4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80060d8: f003 0301 and.w r3, r3, #1
80060dc: 2b00 cmp r3, #0
80060de: d011 beq.n 8006104 <HAL_UART_IRQHandler+0xc8>
80060e0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80060e4: f403 7380 and.w r3, r3, #256 @ 0x100
80060e8: 2b00 cmp r3, #0
80060ea: d00b beq.n 8006104 <HAL_UART_IRQHandler+0xc8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
80060ec: 687b ldr r3, [r7, #4]
80060ee: 681b ldr r3, [r3, #0]
80060f0: 2201 movs r2, #1
80060f2: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
80060f4: 687b ldr r3, [r7, #4]
80060f6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80060fa: f043 0201 orr.w r2, r3, #1
80060fe: 687b ldr r3, [r7, #4]
8006100: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006104: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006108: f003 0302 and.w r3, r3, #2
800610c: 2b00 cmp r3, #0
800610e: d011 beq.n 8006134 <HAL_UART_IRQHandler+0xf8>
8006110: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006114: f003 0301 and.w r3, r3, #1
8006118: 2b00 cmp r3, #0
800611a: d00b beq.n 8006134 <HAL_UART_IRQHandler+0xf8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
800611c: 687b ldr r3, [r7, #4]
800611e: 681b ldr r3, [r3, #0]
8006120: 2202 movs r2, #2
8006122: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8006124: 687b ldr r3, [r7, #4]
8006126: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800612a: f043 0204 orr.w r2, r3, #4
800612e: 687b ldr r3, [r7, #4]
8006130: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006134: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006138: f003 0304 and.w r3, r3, #4
800613c: 2b00 cmp r3, #0
800613e: d011 beq.n 8006164 <HAL_UART_IRQHandler+0x128>
8006140: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006144: f003 0301 and.w r3, r3, #1
8006148: 2b00 cmp r3, #0
800614a: d00b beq.n 8006164 <HAL_UART_IRQHandler+0x128>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
800614c: 687b ldr r3, [r7, #4]
800614e: 681b ldr r3, [r3, #0]
8006150: 2204 movs r2, #4
8006152: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8006154: 687b ldr r3, [r7, #4]
8006156: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800615a: f043 0202 orr.w r2, r3, #2
800615e: 687b ldr r3, [r7, #4]
8006160: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
8006164: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006168: f003 0308 and.w r3, r3, #8
800616c: 2b00 cmp r3, #0
800616e: d017 beq.n 80061a0 <HAL_UART_IRQHandler+0x164>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
8006170: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006174: f003 0320 and.w r3, r3, #32
8006178: 2b00 cmp r3, #0
800617a: d105 bne.n 8006188 <HAL_UART_IRQHandler+0x14c>
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
800617c: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
8006180: 4b5c ldr r3, [pc, #368] @ (80062f4 <HAL_UART_IRQHandler+0x2b8>)
8006182: 4013 ands r3, r2
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
8006184: 2b00 cmp r3, #0
8006186: d00b beq.n 80061a0 <HAL_UART_IRQHandler+0x164>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8006188: 687b ldr r3, [r7, #4]
800618a: 681b ldr r3, [r3, #0]
800618c: 2208 movs r2, #8
800618e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8006190: 687b ldr r3, [r7, #4]
8006192: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006196: f043 0208 orr.w r2, r3, #8
800619a: 687b ldr r3, [r7, #4]
800619c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
80061a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80061a4: f403 6300 and.w r3, r3, #2048 @ 0x800
80061a8: 2b00 cmp r3, #0
80061aa: d012 beq.n 80061d2 <HAL_UART_IRQHandler+0x196>
80061ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80061b0: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80061b4: 2b00 cmp r3, #0
80061b6: d00c beq.n 80061d2 <HAL_UART_IRQHandler+0x196>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80061b8: 687b ldr r3, [r7, #4]
80061ba: 681b ldr r3, [r3, #0]
80061bc: f44f 6200 mov.w r2, #2048 @ 0x800
80061c0: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
80061c2: 687b ldr r3, [r7, #4]
80061c4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80061c8: f043 0220 orr.w r2, r3, #32
80061cc: 687b ldr r3, [r7, #4]
80061ce: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
80061d2: 687b ldr r3, [r7, #4]
80061d4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80061d8: 2b00 cmp r3, #0
80061da: f000 8266 beq.w 80066aa <HAL_UART_IRQHandler+0x66e>
{
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
80061de: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80061e2: f003 0320 and.w r3, r3, #32
80061e6: 2b00 cmp r3, #0
80061e8: d013 beq.n 8006212 <HAL_UART_IRQHandler+0x1d6>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
80061ea: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
80061ee: f003 0320 and.w r3, r3, #32
80061f2: 2b00 cmp r3, #0
80061f4: d105 bne.n 8006202 <HAL_UART_IRQHandler+0x1c6>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80061f6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80061fa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80061fe: 2b00 cmp r3, #0
8006200: d007 beq.n 8006212 <HAL_UART_IRQHandler+0x1d6>
{
if (huart->RxISR != NULL)
8006202: 687b ldr r3, [r7, #4]
8006204: 6f5b ldr r3, [r3, #116] @ 0x74
8006206: 2b00 cmp r3, #0
8006208: d003 beq.n 8006212 <HAL_UART_IRQHandler+0x1d6>
{
huart->RxISR(huart);
800620a: 687b ldr r3, [r7, #4]
800620c: 6f5b ldr r3, [r3, #116] @ 0x74
800620e: 6878 ldr r0, [r7, #4]
8006210: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
8006212: 687b ldr r3, [r7, #4]
8006214: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006218: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
800621c: 687b ldr r3, [r7, #4]
800621e: 681b ldr r3, [r3, #0]
8006220: 689b ldr r3, [r3, #8]
8006222: f003 0340 and.w r3, r3, #64 @ 0x40
8006226: 2b40 cmp r3, #64 @ 0x40
8006228: d005 beq.n 8006236 <HAL_UART_IRQHandler+0x1fa>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
800622a: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
800622e: f003 0328 and.w r3, r3, #40 @ 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8006232: 2b00 cmp r3, #0
8006234: d054 beq.n 80062e0 <HAL_UART_IRQHandler+0x2a4>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
8006236: 6878 ldr r0, [r7, #4]
8006238: f001 f800 bl 800723c <UART_EndRxTransfer>
/* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800623c: 687b ldr r3, [r7, #4]
800623e: 681b ldr r3, [r3, #0]
8006240: 689b ldr r3, [r3, #8]
8006242: f003 0340 and.w r3, r3, #64 @ 0x40
8006246: 2b40 cmp r3, #64 @ 0x40
8006248: d146 bne.n 80062d8 <HAL_UART_IRQHandler+0x29c>
{
/* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800624a: 687b ldr r3, [r7, #4]
800624c: 681b ldr r3, [r3, #0]
800624e: 3308 adds r3, #8
8006250: f8c7 309c str.w r3, [r7, #156] @ 0x9c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006254: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8006258: e853 3f00 ldrex r3, [r3]
800625c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
return(result);
8006260: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8006264: f023 0340 bic.w r3, r3, #64 @ 0x40
8006268: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
800626c: 687b ldr r3, [r7, #4]
800626e: 681b ldr r3, [r3, #0]
8006270: 3308 adds r3, #8
8006272: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
8006276: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
800627a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800627e: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
8006282: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
8006286: e841 2300 strex r3, r2, [r1]
800628a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return(result);
800628e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8006292: 2b00 cmp r3, #0
8006294: d1d9 bne.n 800624a <HAL_UART_IRQHandler+0x20e>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8006296: 687b ldr r3, [r7, #4]
8006298: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800629c: 2b00 cmp r3, #0
800629e: d017 beq.n 80062d0 <HAL_UART_IRQHandler+0x294>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
80062a0: 687b ldr r3, [r7, #4]
80062a2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80062a6: 4a15 ldr r2, [pc, #84] @ (80062fc <HAL_UART_IRQHandler+0x2c0>)
80062a8: 639a str r2, [r3, #56] @ 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
80062aa: 687b ldr r3, [r7, #4]
80062ac: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80062b0: 4618 mov r0, r3
80062b2: f7fd f8d5 bl 8003460 <HAL_DMA_Abort_IT>
80062b6: 4603 mov r3, r0
80062b8: 2b00 cmp r3, #0
80062ba: d019 beq.n 80062f0 <HAL_UART_IRQHandler+0x2b4>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80062bc: 687b ldr r3, [r7, #4]
80062be: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80062c2: 6b9b ldr r3, [r3, #56] @ 0x38
80062c4: 687a ldr r2, [r7, #4]
80062c6: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80
80062ca: 4610 mov r0, r2
80062cc: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80062ce: e00f b.n 80062f0 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80062d0: 6878 ldr r0, [r7, #4]
80062d2: f000 f9f5 bl 80066c0 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80062d6: e00b b.n 80062f0 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80062d8: 6878 ldr r0, [r7, #4]
80062da: f000 f9f1 bl 80066c0 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80062de: e007 b.n 80062f0 <HAL_UART_IRQHandler+0x2b4>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80062e0: 6878 ldr r0, [r7, #4]
80062e2: f000 f9ed bl 80066c0 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80062e6: 687b ldr r3, [r7, #4]
80062e8: 2200 movs r2, #0
80062ea: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
return;
80062ee: e1dc b.n 80066aa <HAL_UART_IRQHandler+0x66e>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80062f0: bf00 nop
return;
80062f2: e1da b.n 80066aa <HAL_UART_IRQHandler+0x66e>
80062f4: 10000001 .word 0x10000001
80062f8: 04000120 .word 0x04000120
80062fc: 08007309 .word 0x08007309
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006300: 687b ldr r3, [r7, #4]
8006302: 6edb ldr r3, [r3, #108] @ 0x6c
8006304: 2b01 cmp r3, #1
8006306: f040 8170 bne.w 80065ea <HAL_UART_IRQHandler+0x5ae>
&& ((isrflags & USART_ISR_IDLE) != 0U)
800630a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800630e: f003 0310 and.w r3, r3, #16
8006312: 2b00 cmp r3, #0
8006314: f000 8169 beq.w 80065ea <HAL_UART_IRQHandler+0x5ae>
&& ((cr1its & USART_ISR_IDLE) != 0U))
8006318: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800631c: f003 0310 and.w r3, r3, #16
8006320: 2b00 cmp r3, #0
8006322: f000 8162 beq.w 80065ea <HAL_UART_IRQHandler+0x5ae>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006326: 687b ldr r3, [r7, #4]
8006328: 681b ldr r3, [r3, #0]
800632a: 2210 movs r2, #16
800632c: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800632e: 687b ldr r3, [r7, #4]
8006330: 681b ldr r3, [r3, #0]
8006332: 689b ldr r3, [r3, #8]
8006334: f003 0340 and.w r3, r3, #64 @ 0x40
8006338: 2b40 cmp r3, #64 @ 0x40
800633a: f040 80d8 bne.w 80064ee <HAL_UART_IRQHandler+0x4b2>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
800633e: 687b ldr r3, [r7, #4]
8006340: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006344: 681b ldr r3, [r3, #0]
8006346: 685b ldr r3, [r3, #4]
8006348: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
if ((nb_remaining_rx_data > 0U)
800634c: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
8006350: 2b00 cmp r3, #0
8006352: f000 80af beq.w 80064b4 <HAL_UART_IRQHandler+0x478>
&& (nb_remaining_rx_data < huart->RxXferSize))
8006356: 687b ldr r3, [r7, #4]
8006358: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
800635c: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
8006360: 429a cmp r2, r3
8006362: f080 80a7 bcs.w 80064b4 <HAL_UART_IRQHandler+0x478>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8006366: 687b ldr r3, [r7, #4]
8006368: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
800636c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
8006370: 687b ldr r3, [r7, #4]
8006372: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006376: 681b ldr r3, [r3, #0]
8006378: 681b ldr r3, [r3, #0]
800637a: f003 0320 and.w r3, r3, #32
800637e: 2b00 cmp r3, #0
8006380: f040 8087 bne.w 8006492 <HAL_UART_IRQHandler+0x456>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006384: 687b ldr r3, [r7, #4]
8006386: 681b ldr r3, [r3, #0]
8006388: f8c7 3088 str.w r3, [r7, #136] @ 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800638c: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
8006390: e853 3f00 ldrex r3, [r3]
8006394: f8c7 3084 str.w r3, [r7, #132] @ 0x84
return(result);
8006398: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800639c: f423 7380 bic.w r3, r3, #256 @ 0x100
80063a0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
80063a4: 687b ldr r3, [r7, #4]
80063a6: 681b ldr r3, [r3, #0]
80063a8: 461a mov r2, r3
80063aa: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
80063ae: f8c7 3094 str.w r3, [r7, #148] @ 0x94
80063b2: f8c7 2090 str.w r2, [r7, #144] @ 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80063b6: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
80063ba: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
80063be: e841 2300 strex r3, r2, [r1]
80063c2: f8c7 308c str.w r3, [r7, #140] @ 0x8c
return(result);
80063c6: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80063ca: 2b00 cmp r3, #0
80063cc: d1da bne.n 8006384 <HAL_UART_IRQHandler+0x348>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80063ce: 687b ldr r3, [r7, #4]
80063d0: 681b ldr r3, [r3, #0]
80063d2: 3308 adds r3, #8
80063d4: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80063d6: 6f7b ldr r3, [r7, #116] @ 0x74
80063d8: e853 3f00 ldrex r3, [r3]
80063dc: 673b str r3, [r7, #112] @ 0x70
return(result);
80063de: 6f3b ldr r3, [r7, #112] @ 0x70
80063e0: f023 0301 bic.w r3, r3, #1
80063e4: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80063e8: 687b ldr r3, [r7, #4]
80063ea: 681b ldr r3, [r3, #0]
80063ec: 3308 adds r3, #8
80063ee: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
80063f2: f8c7 2080 str.w r2, [r7, #128] @ 0x80
80063f6: 67fb str r3, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80063f8: 6ff9 ldr r1, [r7, #124] @ 0x7c
80063fa: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
80063fe: e841 2300 strex r3, r2, [r1]
8006402: 67bb str r3, [r7, #120] @ 0x78
return(result);
8006404: 6fbb ldr r3, [r7, #120] @ 0x78
8006406: 2b00 cmp r3, #0
8006408: d1e1 bne.n 80063ce <HAL_UART_IRQHandler+0x392>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800640a: 687b ldr r3, [r7, #4]
800640c: 681b ldr r3, [r3, #0]
800640e: 3308 adds r3, #8
8006410: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006412: 6e3b ldr r3, [r7, #96] @ 0x60
8006414: e853 3f00 ldrex r3, [r3]
8006418: 65fb str r3, [r7, #92] @ 0x5c
return(result);
800641a: 6dfb ldr r3, [r7, #92] @ 0x5c
800641c: f023 0340 bic.w r3, r3, #64 @ 0x40
8006420: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8006424: 687b ldr r3, [r7, #4]
8006426: 681b ldr r3, [r3, #0]
8006428: 3308 adds r3, #8
800642a: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
800642e: 66fa str r2, [r7, #108] @ 0x6c
8006430: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006432: 6eb9 ldr r1, [r7, #104] @ 0x68
8006434: 6efa ldr r2, [r7, #108] @ 0x6c
8006436: e841 2300 strex r3, r2, [r1]
800643a: 667b str r3, [r7, #100] @ 0x64
return(result);
800643c: 6e7b ldr r3, [r7, #100] @ 0x64
800643e: 2b00 cmp r3, #0
8006440: d1e3 bne.n 800640a <HAL_UART_IRQHandler+0x3ce>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006442: 687b ldr r3, [r7, #4]
8006444: 2220 movs r2, #32
8006446: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800644a: 687b ldr r3, [r7, #4]
800644c: 2200 movs r2, #0
800644e: 66da str r2, [r3, #108] @ 0x6c
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006450: 687b ldr r3, [r7, #4]
8006452: 681b ldr r3, [r3, #0]
8006454: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006456: 6cfb ldr r3, [r7, #76] @ 0x4c
8006458: e853 3f00 ldrex r3, [r3]
800645c: 64bb str r3, [r7, #72] @ 0x48
return(result);
800645e: 6cbb ldr r3, [r7, #72] @ 0x48
8006460: f023 0310 bic.w r3, r3, #16
8006464: f8c7 30ac str.w r3, [r7, #172] @ 0xac
8006468: 687b ldr r3, [r7, #4]
800646a: 681b ldr r3, [r3, #0]
800646c: 461a mov r2, r3
800646e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8006472: 65bb str r3, [r7, #88] @ 0x58
8006474: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006476: 6d79 ldr r1, [r7, #84] @ 0x54
8006478: 6dba ldr r2, [r7, #88] @ 0x58
800647a: e841 2300 strex r3, r2, [r1]
800647e: 653b str r3, [r7, #80] @ 0x50
return(result);
8006480: 6d3b ldr r3, [r7, #80] @ 0x50
8006482: 2b00 cmp r3, #0
8006484: d1e4 bne.n 8006450 <HAL_UART_IRQHandler+0x414>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8006486: 687b ldr r3, [r7, #4]
8006488: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800648c: 4618 mov r0, r3
800648e: f7fc ff8e bl 80033ae <HAL_DMA_Abort>
}
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
8006492: 687b ldr r3, [r7, #4]
8006494: 2202 movs r2, #2
8006496: 671a str r2, [r3, #112] @ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8006498: 687b ldr r3, [r7, #4]
800649a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
800649e: 687b ldr r3, [r7, #4]
80064a0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80064a4: b29b uxth r3, r3
80064a6: 1ad3 subs r3, r2, r3
80064a8: b29b uxth r3, r3
80064aa: 4619 mov r1, r3
80064ac: 6878 ldr r0, [r7, #4]
80064ae: f000 f911 bl 80066d4 <HAL_UARTEx_RxEventCallback>
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
}
}
return;
80064b2: e0fc b.n 80066ae <HAL_UART_IRQHandler+0x672>
if (nb_remaining_rx_data == huart->RxXferSize)
80064b4: 687b ldr r3, [r7, #4]
80064b6: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
80064ba: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
80064be: 429a cmp r2, r3
80064c0: f040 80f5 bne.w 80066ae <HAL_UART_IRQHandler+0x672>
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
80064c4: 687b ldr r3, [r7, #4]
80064c6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80064ca: 681b ldr r3, [r3, #0]
80064cc: 681b ldr r3, [r3, #0]
80064ce: f003 0320 and.w r3, r3, #32
80064d2: 2b20 cmp r3, #32
80064d4: f040 80eb bne.w 80066ae <HAL_UART_IRQHandler+0x672>
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
80064d8: 687b ldr r3, [r7, #4]
80064da: 2202 movs r2, #2
80064dc: 671a str r2, [r3, #112] @ 0x70
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80064de: 687b ldr r3, [r7, #4]
80064e0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
80064e4: 4619 mov r1, r3
80064e6: 6878 ldr r0, [r7, #4]
80064e8: f000 f8f4 bl 80066d4 <HAL_UARTEx_RxEventCallback>
return;
80064ec: e0df b.n 80066ae <HAL_UART_IRQHandler+0x672>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
80064ee: 687b ldr r3, [r7, #4]
80064f0: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
80064f4: 687b ldr r3, [r7, #4]
80064f6: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80064fa: b29b uxth r3, r3
80064fc: 1ad3 subs r3, r2, r3
80064fe: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
if ((huart->RxXferCount > 0U)
8006502: 687b ldr r3, [r7, #4]
8006504: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8006508: b29b uxth r3, r3
800650a: 2b00 cmp r3, #0
800650c: f000 80d1 beq.w 80066b2 <HAL_UART_IRQHandler+0x676>
&& (nb_rx_data > 0U))
8006510: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
8006514: 2b00 cmp r3, #0
8006516: f000 80cc beq.w 80066b2 <HAL_UART_IRQHandler+0x676>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
800651a: 687b ldr r3, [r7, #4]
800651c: 681b ldr r3, [r3, #0]
800651e: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006520: 6bbb ldr r3, [r7, #56] @ 0x38
8006522: e853 3f00 ldrex r3, [r3]
8006526: 637b str r3, [r7, #52] @ 0x34
return(result);
8006528: 6b7b ldr r3, [r7, #52] @ 0x34
800652a: f423 7390 bic.w r3, r3, #288 @ 0x120
800652e: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8006532: 687b ldr r3, [r7, #4]
8006534: 681b ldr r3, [r3, #0]
8006536: 461a mov r2, r3
8006538: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
800653c: 647b str r3, [r7, #68] @ 0x44
800653e: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006540: 6c39 ldr r1, [r7, #64] @ 0x40
8006542: 6c7a ldr r2, [r7, #68] @ 0x44
8006544: e841 2300 strex r3, r2, [r1]
8006548: 63fb str r3, [r7, #60] @ 0x3c
return(result);
800654a: 6bfb ldr r3, [r7, #60] @ 0x3c
800654c: 2b00 cmp r3, #0
800654e: d1e4 bne.n 800651a <HAL_UART_IRQHandler+0x4de>
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8006550: 687b ldr r3, [r7, #4]
8006552: 681b ldr r3, [r3, #0]
8006554: 3308 adds r3, #8
8006556: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006558: 6a7b ldr r3, [r7, #36] @ 0x24
800655a: e853 3f00 ldrex r3, [r3]
800655e: 623b str r3, [r7, #32]
return(result);
8006560: 6a3b ldr r3, [r7, #32]
8006562: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8006566: f023 0301 bic.w r3, r3, #1
800656a: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
800656e: 687b ldr r3, [r7, #4]
8006570: 681b ldr r3, [r3, #0]
8006572: 3308 adds r3, #8
8006574: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
8006578: 633a str r2, [r7, #48] @ 0x30
800657a: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800657c: 6af9 ldr r1, [r7, #44] @ 0x2c
800657e: 6b3a ldr r2, [r7, #48] @ 0x30
8006580: e841 2300 strex r3, r2, [r1]
8006584: 62bb str r3, [r7, #40] @ 0x28
return(result);
8006586: 6abb ldr r3, [r7, #40] @ 0x28
8006588: 2b00 cmp r3, #0
800658a: d1e1 bne.n 8006550 <HAL_UART_IRQHandler+0x514>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800658c: 687b ldr r3, [r7, #4]
800658e: 2220 movs r2, #32
8006590: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006594: 687b ldr r3, [r7, #4]
8006596: 2200 movs r2, #0
8006598: 66da str r2, [r3, #108] @ 0x6c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
800659a: 687b ldr r3, [r7, #4]
800659c: 2200 movs r2, #0
800659e: 675a str r2, [r3, #116] @ 0x74
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80065a0: 687b ldr r3, [r7, #4]
80065a2: 681b ldr r3, [r3, #0]
80065a4: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80065a6: 693b ldr r3, [r7, #16]
80065a8: e853 3f00 ldrex r3, [r3]
80065ac: 60fb str r3, [r7, #12]
return(result);
80065ae: 68fb ldr r3, [r7, #12]
80065b0: f023 0310 bic.w r3, r3, #16
80065b4: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
80065b8: 687b ldr r3, [r7, #4]
80065ba: 681b ldr r3, [r3, #0]
80065bc: 461a mov r2, r3
80065be: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
80065c2: 61fb str r3, [r7, #28]
80065c4: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80065c6: 69b9 ldr r1, [r7, #24]
80065c8: 69fa ldr r2, [r7, #28]
80065ca: e841 2300 strex r3, r2, [r1]
80065ce: 617b str r3, [r7, #20]
return(result);
80065d0: 697b ldr r3, [r7, #20]
80065d2: 2b00 cmp r3, #0
80065d4: d1e4 bne.n 80065a0 <HAL_UART_IRQHandler+0x564>
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
In this case, Rx Event type is Idle Event */
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
80065d6: 687b ldr r3, [r7, #4]
80065d8: 2202 movs r2, #2
80065da: 671a str r2, [r3, #112] @ 0x70
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
80065dc: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
80065e0: 4619 mov r1, r3
80065e2: 6878 ldr r0, [r7, #4]
80065e4: f000 f876 bl 80066d4 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
80065e8: e063 b.n 80066b2 <HAL_UART_IRQHandler+0x676>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
80065ea: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
80065ee: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80065f2: 2b00 cmp r3, #0
80065f4: d00e beq.n 8006614 <HAL_UART_IRQHandler+0x5d8>
80065f6: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
80065fa: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80065fe: 2b00 cmp r3, #0
8006600: d008 beq.n 8006614 <HAL_UART_IRQHandler+0x5d8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8006602: 687b ldr r3, [r7, #4]
8006604: 681b ldr r3, [r3, #0]
8006606: f44f 1280 mov.w r2, #1048576 @ 0x100000
800660a: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
800660c: 6878 ldr r0, [r7, #4]
800660e: f001 fbd9 bl 8007dc4 <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006612: e051 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
8006614: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
8006618: f003 0380 and.w r3, r3, #128 @ 0x80
800661c: 2b00 cmp r3, #0
800661e: d014 beq.n 800664a <HAL_UART_IRQHandler+0x60e>
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
8006620: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
8006624: f003 0380 and.w r3, r3, #128 @ 0x80
8006628: 2b00 cmp r3, #0
800662a: d105 bne.n 8006638 <HAL_UART_IRQHandler+0x5fc>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
800662c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
8006630: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8006634: 2b00 cmp r3, #0
8006636: d008 beq.n 800664a <HAL_UART_IRQHandler+0x60e>
{
if (huart->TxISR != NULL)
8006638: 687b ldr r3, [r7, #4]
800663a: 6f9b ldr r3, [r3, #120] @ 0x78
800663c: 2b00 cmp r3, #0
800663e: d03a beq.n 80066b6 <HAL_UART_IRQHandler+0x67a>
{
huart->TxISR(huart);
8006640: 687b ldr r3, [r7, #4]
8006642: 6f9b ldr r3, [r3, #120] @ 0x78
8006644: 6878 ldr r0, [r7, #4]
8006646: 4798 blx r3
}
return;
8006648: e035 b.n 80066b6 <HAL_UART_IRQHandler+0x67a>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
800664a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800664e: f003 0340 and.w r3, r3, #64 @ 0x40
8006652: 2b00 cmp r3, #0
8006654: d009 beq.n 800666a <HAL_UART_IRQHandler+0x62e>
8006656: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800665a: f003 0340 and.w r3, r3, #64 @ 0x40
800665e: 2b00 cmp r3, #0
8006660: d003 beq.n 800666a <HAL_UART_IRQHandler+0x62e>
{
UART_EndTransmit_IT(huart);
8006662: 6878 ldr r0, [r7, #4]
8006664: f000 fe62 bl 800732c <UART_EndTransmit_IT>
return;
8006668: e026 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
}
/* UART TX Fifo Empty occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
800666a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800666e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8006672: 2b00 cmp r3, #0
8006674: d009 beq.n 800668a <HAL_UART_IRQHandler+0x64e>
8006676: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800667a: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
800667e: 2b00 cmp r3, #0
8006680: d003 beq.n 800668a <HAL_UART_IRQHandler+0x64e>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Tx Fifo Empty Callback */
huart->TxFifoEmptyCallback(huart);
#else
/* Call legacy weak Tx Fifo Empty Callback */
HAL_UARTEx_TxFifoEmptyCallback(huart);
8006682: 6878 ldr r0, [r7, #4]
8006684: f001 fbb2 bl 8007dec <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8006688: e016 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
}
/* UART RX Fifo Full occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
800668a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
800668e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8006692: 2b00 cmp r3, #0
8006694: d010 beq.n 80066b8 <HAL_UART_IRQHandler+0x67c>
8006696: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
800669a: 2b00 cmp r3, #0
800669c: da0c bge.n 80066b8 <HAL_UART_IRQHandler+0x67c>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Rx Fifo Full Callback */
huart->RxFifoFullCallback(huart);
#else
/* Call legacy weak Rx Fifo Full Callback */
HAL_UARTEx_RxFifoFullCallback(huart);
800669e: 6878 ldr r0, [r7, #4]
80066a0: f001 fb9a bl 8007dd8 <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
80066a4: e008 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
return;
80066a6: bf00 nop
80066a8: e006 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
return;
80066aa: bf00 nop
80066ac: e004 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
return;
80066ae: bf00 nop
80066b0: e002 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
return;
80066b2: bf00 nop
80066b4: e000 b.n 80066b8 <HAL_UART_IRQHandler+0x67c>
return;
80066b6: bf00 nop
}
}
80066b8: 37e8 adds r7, #232 @ 0xe8
80066ba: 46bd mov sp, r7
80066bc: bd80 pop {r7, pc}
80066be: bf00 nop
080066c0 <HAL_UART_ErrorCallback>:
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
80066c0: b480 push {r7}
80066c2: b083 sub sp, #12
80066c4: af00 add r7, sp, #0
80066c6: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
80066c8: bf00 nop
80066ca: 370c adds r7, #12
80066cc: 46bd mov sp, r7
80066ce: f85d 7b04 ldr.w r7, [sp], #4
80066d2: 4770 bx lr
080066d4 <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
80066d4: b480 push {r7}
80066d6: b083 sub sp, #12
80066d8: af00 add r7, sp, #0
80066da: 6078 str r0, [r7, #4]
80066dc: 460b mov r3, r1
80066de: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
80066e0: bf00 nop
80066e2: 370c adds r7, #12
80066e4: 46bd mov sp, r7
80066e6: f85d 7b04 ldr.w r7, [sp], #4
80066ea: 4770 bx lr
080066ec <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
80066ec: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
80066f0: b08c sub sp, #48 @ 0x30
80066f2: af00 add r7, sp, #0
80066f4: 6178 str r0, [r7, #20]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
80066f6: 2300 movs r3, #0
80066f8: f887 302a strb.w r3, [r7, #42] @ 0x2a
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
80066fc: 697b ldr r3, [r7, #20]
80066fe: 689a ldr r2, [r3, #8]
8006700: 697b ldr r3, [r7, #20]
8006702: 691b ldr r3, [r3, #16]
8006704: 431a orrs r2, r3
8006706: 697b ldr r3, [r7, #20]
8006708: 695b ldr r3, [r3, #20]
800670a: 431a orrs r2, r3
800670c: 697b ldr r3, [r7, #20]
800670e: 69db ldr r3, [r3, #28]
8006710: 4313 orrs r3, r2
8006712: 62fb str r3, [r7, #44] @ 0x2c
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8006714: 697b ldr r3, [r7, #20]
8006716: 681b ldr r3, [r3, #0]
8006718: 681a ldr r2, [r3, #0]
800671a: 4bab ldr r3, [pc, #684] @ (80069c8 <UART_SetConfig+0x2dc>)
800671c: 4013 ands r3, r2
800671e: 697a ldr r2, [r7, #20]
8006720: 6812 ldr r2, [r2, #0]
8006722: 6af9 ldr r1, [r7, #44] @ 0x2c
8006724: 430b orrs r3, r1
8006726: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8006728: 697b ldr r3, [r7, #20]
800672a: 681b ldr r3, [r3, #0]
800672c: 685b ldr r3, [r3, #4]
800672e: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8006732: 697b ldr r3, [r7, #20]
8006734: 68da ldr r2, [r3, #12]
8006736: 697b ldr r3, [r7, #20]
8006738: 681b ldr r3, [r3, #0]
800673a: 430a orrs r2, r1
800673c: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
800673e: 697b ldr r3, [r7, #20]
8006740: 699b ldr r3, [r3, #24]
8006742: 62fb str r3, [r7, #44] @ 0x2c
if (!(UART_INSTANCE_LOWPOWER(huart)))
8006744: 697b ldr r3, [r7, #20]
8006746: 681b ldr r3, [r3, #0]
8006748: 4aa0 ldr r2, [pc, #640] @ (80069cc <UART_SetConfig+0x2e0>)
800674a: 4293 cmp r3, r2
800674c: d004 beq.n 8006758 <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
800674e: 697b ldr r3, [r7, #20]
8006750: 6a1b ldr r3, [r3, #32]
8006752: 6afa ldr r2, [r7, #44] @ 0x2c
8006754: 4313 orrs r3, r2
8006756: 62fb str r3, [r7, #44] @ 0x2c
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8006758: 697b ldr r3, [r7, #20]
800675a: 681b ldr r3, [r3, #0]
800675c: 689b ldr r3, [r3, #8]
800675e: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
8006762: f423 6330 bic.w r3, r3, #2816 @ 0xb00
8006766: 697a ldr r2, [r7, #20]
8006768: 6812 ldr r2, [r2, #0]
800676a: 6af9 ldr r1, [r7, #44] @ 0x2c
800676c: 430b orrs r3, r1
800676e: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8006770: 697b ldr r3, [r7, #20]
8006772: 681b ldr r3, [r3, #0]
8006774: 6adb ldr r3, [r3, #44] @ 0x2c
8006776: f023 010f bic.w r1, r3, #15
800677a: 697b ldr r3, [r7, #20]
800677c: 6a5a ldr r2, [r3, #36] @ 0x24
800677e: 697b ldr r3, [r7, #20]
8006780: 681b ldr r3, [r3, #0]
8006782: 430a orrs r2, r1
8006784: 62da str r2, [r3, #44] @ 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8006786: 697b ldr r3, [r7, #20]
8006788: 681b ldr r3, [r3, #0]
800678a: 4a91 ldr r2, [pc, #580] @ (80069d0 <UART_SetConfig+0x2e4>)
800678c: 4293 cmp r3, r2
800678e: d125 bne.n 80067dc <UART_SetConfig+0xf0>
8006790: 4b90 ldr r3, [pc, #576] @ (80069d4 <UART_SetConfig+0x2e8>)
8006792: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006796: f003 0303 and.w r3, r3, #3
800679a: 2b03 cmp r3, #3
800679c: d81a bhi.n 80067d4 <UART_SetConfig+0xe8>
800679e: a201 add r2, pc, #4 @ (adr r2, 80067a4 <UART_SetConfig+0xb8>)
80067a0: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80067a4: 080067b5 .word 0x080067b5
80067a8: 080067c5 .word 0x080067c5
80067ac: 080067bd .word 0x080067bd
80067b0: 080067cd .word 0x080067cd
80067b4: 2301 movs r3, #1
80067b6: f887 302b strb.w r3, [r7, #43] @ 0x2b
80067ba: e0d6 b.n 800696a <UART_SetConfig+0x27e>
80067bc: 2302 movs r3, #2
80067be: f887 302b strb.w r3, [r7, #43] @ 0x2b
80067c2: e0d2 b.n 800696a <UART_SetConfig+0x27e>
80067c4: 2304 movs r3, #4
80067c6: f887 302b strb.w r3, [r7, #43] @ 0x2b
80067ca: e0ce b.n 800696a <UART_SetConfig+0x27e>
80067cc: 2308 movs r3, #8
80067ce: f887 302b strb.w r3, [r7, #43] @ 0x2b
80067d2: e0ca b.n 800696a <UART_SetConfig+0x27e>
80067d4: 2310 movs r3, #16
80067d6: f887 302b strb.w r3, [r7, #43] @ 0x2b
80067da: e0c6 b.n 800696a <UART_SetConfig+0x27e>
80067dc: 697b ldr r3, [r7, #20]
80067de: 681b ldr r3, [r3, #0]
80067e0: 4a7d ldr r2, [pc, #500] @ (80069d8 <UART_SetConfig+0x2ec>)
80067e2: 4293 cmp r3, r2
80067e4: d138 bne.n 8006858 <UART_SetConfig+0x16c>
80067e6: 4b7b ldr r3, [pc, #492] @ (80069d4 <UART_SetConfig+0x2e8>)
80067e8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80067ec: f003 030c and.w r3, r3, #12
80067f0: 2b0c cmp r3, #12
80067f2: d82d bhi.n 8006850 <UART_SetConfig+0x164>
80067f4: a201 add r2, pc, #4 @ (adr r2, 80067fc <UART_SetConfig+0x110>)
80067f6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80067fa: bf00 nop
80067fc: 08006831 .word 0x08006831
8006800: 08006851 .word 0x08006851
8006804: 08006851 .word 0x08006851
8006808: 08006851 .word 0x08006851
800680c: 08006841 .word 0x08006841
8006810: 08006851 .word 0x08006851
8006814: 08006851 .word 0x08006851
8006818: 08006851 .word 0x08006851
800681c: 08006839 .word 0x08006839
8006820: 08006851 .word 0x08006851
8006824: 08006851 .word 0x08006851
8006828: 08006851 .word 0x08006851
800682c: 08006849 .word 0x08006849
8006830: 2300 movs r3, #0
8006832: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006836: e098 b.n 800696a <UART_SetConfig+0x27e>
8006838: 2302 movs r3, #2
800683a: f887 302b strb.w r3, [r7, #43] @ 0x2b
800683e: e094 b.n 800696a <UART_SetConfig+0x27e>
8006840: 2304 movs r3, #4
8006842: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006846: e090 b.n 800696a <UART_SetConfig+0x27e>
8006848: 2308 movs r3, #8
800684a: f887 302b strb.w r3, [r7, #43] @ 0x2b
800684e: e08c b.n 800696a <UART_SetConfig+0x27e>
8006850: 2310 movs r3, #16
8006852: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006856: e088 b.n 800696a <UART_SetConfig+0x27e>
8006858: 697b ldr r3, [r7, #20]
800685a: 681b ldr r3, [r3, #0]
800685c: 4a5f ldr r2, [pc, #380] @ (80069dc <UART_SetConfig+0x2f0>)
800685e: 4293 cmp r3, r2
8006860: d125 bne.n 80068ae <UART_SetConfig+0x1c2>
8006862: 4b5c ldr r3, [pc, #368] @ (80069d4 <UART_SetConfig+0x2e8>)
8006864: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006868: f003 0330 and.w r3, r3, #48 @ 0x30
800686c: 2b30 cmp r3, #48 @ 0x30
800686e: d016 beq.n 800689e <UART_SetConfig+0x1b2>
8006870: 2b30 cmp r3, #48 @ 0x30
8006872: d818 bhi.n 80068a6 <UART_SetConfig+0x1ba>
8006874: 2b20 cmp r3, #32
8006876: d00a beq.n 800688e <UART_SetConfig+0x1a2>
8006878: 2b20 cmp r3, #32
800687a: d814 bhi.n 80068a6 <UART_SetConfig+0x1ba>
800687c: 2b00 cmp r3, #0
800687e: d002 beq.n 8006886 <UART_SetConfig+0x19a>
8006880: 2b10 cmp r3, #16
8006882: d008 beq.n 8006896 <UART_SetConfig+0x1aa>
8006884: e00f b.n 80068a6 <UART_SetConfig+0x1ba>
8006886: 2300 movs r3, #0
8006888: f887 302b strb.w r3, [r7, #43] @ 0x2b
800688c: e06d b.n 800696a <UART_SetConfig+0x27e>
800688e: 2302 movs r3, #2
8006890: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006894: e069 b.n 800696a <UART_SetConfig+0x27e>
8006896: 2304 movs r3, #4
8006898: f887 302b strb.w r3, [r7, #43] @ 0x2b
800689c: e065 b.n 800696a <UART_SetConfig+0x27e>
800689e: 2308 movs r3, #8
80068a0: f887 302b strb.w r3, [r7, #43] @ 0x2b
80068a4: e061 b.n 800696a <UART_SetConfig+0x27e>
80068a6: 2310 movs r3, #16
80068a8: f887 302b strb.w r3, [r7, #43] @ 0x2b
80068ac: e05d b.n 800696a <UART_SetConfig+0x27e>
80068ae: 697b ldr r3, [r7, #20]
80068b0: 681b ldr r3, [r3, #0]
80068b2: 4a4b ldr r2, [pc, #300] @ (80069e0 <UART_SetConfig+0x2f4>)
80068b4: 4293 cmp r3, r2
80068b6: d125 bne.n 8006904 <UART_SetConfig+0x218>
80068b8: 4b46 ldr r3, [pc, #280] @ (80069d4 <UART_SetConfig+0x2e8>)
80068ba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80068be: f003 03c0 and.w r3, r3, #192 @ 0xc0
80068c2: 2bc0 cmp r3, #192 @ 0xc0
80068c4: d016 beq.n 80068f4 <UART_SetConfig+0x208>
80068c6: 2bc0 cmp r3, #192 @ 0xc0
80068c8: d818 bhi.n 80068fc <UART_SetConfig+0x210>
80068ca: 2b80 cmp r3, #128 @ 0x80
80068cc: d00a beq.n 80068e4 <UART_SetConfig+0x1f8>
80068ce: 2b80 cmp r3, #128 @ 0x80
80068d0: d814 bhi.n 80068fc <UART_SetConfig+0x210>
80068d2: 2b00 cmp r3, #0
80068d4: d002 beq.n 80068dc <UART_SetConfig+0x1f0>
80068d6: 2b40 cmp r3, #64 @ 0x40
80068d8: d008 beq.n 80068ec <UART_SetConfig+0x200>
80068da: e00f b.n 80068fc <UART_SetConfig+0x210>
80068dc: 2300 movs r3, #0
80068de: f887 302b strb.w r3, [r7, #43] @ 0x2b
80068e2: e042 b.n 800696a <UART_SetConfig+0x27e>
80068e4: 2302 movs r3, #2
80068e6: f887 302b strb.w r3, [r7, #43] @ 0x2b
80068ea: e03e b.n 800696a <UART_SetConfig+0x27e>
80068ec: 2304 movs r3, #4
80068ee: f887 302b strb.w r3, [r7, #43] @ 0x2b
80068f2: e03a b.n 800696a <UART_SetConfig+0x27e>
80068f4: 2308 movs r3, #8
80068f6: f887 302b strb.w r3, [r7, #43] @ 0x2b
80068fa: e036 b.n 800696a <UART_SetConfig+0x27e>
80068fc: 2310 movs r3, #16
80068fe: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006902: e032 b.n 800696a <UART_SetConfig+0x27e>
8006904: 697b ldr r3, [r7, #20]
8006906: 681b ldr r3, [r3, #0]
8006908: 4a30 ldr r2, [pc, #192] @ (80069cc <UART_SetConfig+0x2e0>)
800690a: 4293 cmp r3, r2
800690c: d12a bne.n 8006964 <UART_SetConfig+0x278>
800690e: 4b31 ldr r3, [pc, #196] @ (80069d4 <UART_SetConfig+0x2e8>)
8006910: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8006914: f403 6340 and.w r3, r3, #3072 @ 0xc00
8006918: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
800691c: d01a beq.n 8006954 <UART_SetConfig+0x268>
800691e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8006922: d81b bhi.n 800695c <UART_SetConfig+0x270>
8006924: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8006928: d00c beq.n 8006944 <UART_SetConfig+0x258>
800692a: f5b3 6f00 cmp.w r3, #2048 @ 0x800
800692e: d815 bhi.n 800695c <UART_SetConfig+0x270>
8006930: 2b00 cmp r3, #0
8006932: d003 beq.n 800693c <UART_SetConfig+0x250>
8006934: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8006938: d008 beq.n 800694c <UART_SetConfig+0x260>
800693a: e00f b.n 800695c <UART_SetConfig+0x270>
800693c: 2300 movs r3, #0
800693e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006942: e012 b.n 800696a <UART_SetConfig+0x27e>
8006944: 2302 movs r3, #2
8006946: f887 302b strb.w r3, [r7, #43] @ 0x2b
800694a: e00e b.n 800696a <UART_SetConfig+0x27e>
800694c: 2304 movs r3, #4
800694e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006952: e00a b.n 800696a <UART_SetConfig+0x27e>
8006954: 2308 movs r3, #8
8006956: f887 302b strb.w r3, [r7, #43] @ 0x2b
800695a: e006 b.n 800696a <UART_SetConfig+0x27e>
800695c: 2310 movs r3, #16
800695e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8006962: e002 b.n 800696a <UART_SetConfig+0x27e>
8006964: 2310 movs r3, #16
8006966: f887 302b strb.w r3, [r7, #43] @ 0x2b
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
800696a: 697b ldr r3, [r7, #20]
800696c: 681b ldr r3, [r3, #0]
800696e: 4a17 ldr r2, [pc, #92] @ (80069cc <UART_SetConfig+0x2e0>)
8006970: 4293 cmp r3, r2
8006972: f040 80a8 bne.w 8006ac6 <UART_SetConfig+0x3da>
{
/* Retrieve frequency clock */
switch (clocksource)
8006976: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
800697a: 2b08 cmp r3, #8
800697c: d834 bhi.n 80069e8 <UART_SetConfig+0x2fc>
800697e: a201 add r2, pc, #4 @ (adr r2, 8006984 <UART_SetConfig+0x298>)
8006980: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006984: 080069a9 .word 0x080069a9
8006988: 080069e9 .word 0x080069e9
800698c: 080069b1 .word 0x080069b1
8006990: 080069e9 .word 0x080069e9
8006994: 080069b7 .word 0x080069b7
8006998: 080069e9 .word 0x080069e9
800699c: 080069e9 .word 0x080069e9
80069a0: 080069e9 .word 0x080069e9
80069a4: 080069bf .word 0x080069bf
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80069a8: f7fd fccc bl 8004344 <HAL_RCC_GetPCLK1Freq>
80069ac: 6278 str r0, [r7, #36] @ 0x24
break;
80069ae: e021 b.n 80069f4 <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80069b0: 4b0c ldr r3, [pc, #48] @ (80069e4 <UART_SetConfig+0x2f8>)
80069b2: 627b str r3, [r7, #36] @ 0x24
break;
80069b4: e01e b.n 80069f4 <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80069b6: f7fd fc57 bl 8004268 <HAL_RCC_GetSysClockFreq>
80069ba: 6278 str r0, [r7, #36] @ 0x24
break;
80069bc: e01a b.n 80069f4 <UART_SetConfig+0x308>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80069be: f44f 4300 mov.w r3, #32768 @ 0x8000
80069c2: 627b str r3, [r7, #36] @ 0x24
break;
80069c4: e016 b.n 80069f4 <UART_SetConfig+0x308>
80069c6: bf00 nop
80069c8: cfff69f3 .word 0xcfff69f3
80069cc: 40008000 .word 0x40008000
80069d0: 40013800 .word 0x40013800
80069d4: 40021000 .word 0x40021000
80069d8: 40004400 .word 0x40004400
80069dc: 40004800 .word 0x40004800
80069e0: 40004c00 .word 0x40004c00
80069e4: 00f42400 .word 0x00f42400
default:
pclk = 0U;
80069e8: 2300 movs r3, #0
80069ea: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
80069ec: 2301 movs r3, #1
80069ee: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
80069f2: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
80069f4: 6a7b ldr r3, [r7, #36] @ 0x24
80069f6: 2b00 cmp r3, #0
80069f8: f000 812a beq.w 8006c50 <UART_SetConfig+0x564>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
80069fc: 697b ldr r3, [r7, #20]
80069fe: 6a5b ldr r3, [r3, #36] @ 0x24
8006a00: 4a9e ldr r2, [pc, #632] @ (8006c7c <UART_SetConfig+0x590>)
8006a02: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8006a06: 461a mov r2, r3
8006a08: 6a7b ldr r3, [r7, #36] @ 0x24
8006a0a: fbb3 f3f2 udiv r3, r3, r2
8006a0e: 61bb str r3, [r7, #24]
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8006a10: 697b ldr r3, [r7, #20]
8006a12: 685a ldr r2, [r3, #4]
8006a14: 4613 mov r3, r2
8006a16: 005b lsls r3, r3, #1
8006a18: 4413 add r3, r2
8006a1a: 69ba ldr r2, [r7, #24]
8006a1c: 429a cmp r2, r3
8006a1e: d305 bcc.n 8006a2c <UART_SetConfig+0x340>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
8006a20: 697b ldr r3, [r7, #20]
8006a22: 685b ldr r3, [r3, #4]
8006a24: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8006a26: 69ba ldr r2, [r7, #24]
8006a28: 429a cmp r2, r3
8006a2a: d903 bls.n 8006a34 <UART_SetConfig+0x348>
{
ret = HAL_ERROR;
8006a2c: 2301 movs r3, #1
8006a2e: f887 302a strb.w r3, [r7, #42] @ 0x2a
8006a32: e10d b.n 8006c50 <UART_SetConfig+0x564>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8006a34: 6a7b ldr r3, [r7, #36] @ 0x24
8006a36: 2200 movs r2, #0
8006a38: 60bb str r3, [r7, #8]
8006a3a: 60fa str r2, [r7, #12]
8006a3c: 697b ldr r3, [r7, #20]
8006a3e: 6a5b ldr r3, [r3, #36] @ 0x24
8006a40: 4a8e ldr r2, [pc, #568] @ (8006c7c <UART_SetConfig+0x590>)
8006a42: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8006a46: b29b uxth r3, r3
8006a48: 2200 movs r2, #0
8006a4a: 603b str r3, [r7, #0]
8006a4c: 607a str r2, [r7, #4]
8006a4e: e9d7 2300 ldrd r2, r3, [r7]
8006a52: e9d7 0102 ldrd r0, r1, [r7, #8]
8006a56: f7f9 fbdf bl 8000218 <__aeabi_uldivmod>
8006a5a: 4602 mov r2, r0
8006a5c: 460b mov r3, r1
8006a5e: 4610 mov r0, r2
8006a60: 4619 mov r1, r3
8006a62: f04f 0200 mov.w r2, #0
8006a66: f04f 0300 mov.w r3, #0
8006a6a: 020b lsls r3, r1, #8
8006a6c: ea43 6310 orr.w r3, r3, r0, lsr #24
8006a70: 0202 lsls r2, r0, #8
8006a72: 6979 ldr r1, [r7, #20]
8006a74: 6849 ldr r1, [r1, #4]
8006a76: 0849 lsrs r1, r1, #1
8006a78: 2000 movs r0, #0
8006a7a: 460c mov r4, r1
8006a7c: 4605 mov r5, r0
8006a7e: eb12 0804 adds.w r8, r2, r4
8006a82: eb43 0905 adc.w r9, r3, r5
8006a86: 697b ldr r3, [r7, #20]
8006a88: 685b ldr r3, [r3, #4]
8006a8a: 2200 movs r2, #0
8006a8c: 469a mov sl, r3
8006a8e: 4693 mov fp, r2
8006a90: 4652 mov r2, sl
8006a92: 465b mov r3, fp
8006a94: 4640 mov r0, r8
8006a96: 4649 mov r1, r9
8006a98: f7f9 fbbe bl 8000218 <__aeabi_uldivmod>
8006a9c: 4602 mov r2, r0
8006a9e: 460b mov r3, r1
8006aa0: 4613 mov r3, r2
8006aa2: 623b str r3, [r7, #32]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8006aa4: 6a3b ldr r3, [r7, #32]
8006aa6: f5b3 7f40 cmp.w r3, #768 @ 0x300
8006aaa: d308 bcc.n 8006abe <UART_SetConfig+0x3d2>
8006aac: 6a3b ldr r3, [r7, #32]
8006aae: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8006ab2: d204 bcs.n 8006abe <UART_SetConfig+0x3d2>
{
huart->Instance->BRR = usartdiv;
8006ab4: 697b ldr r3, [r7, #20]
8006ab6: 681b ldr r3, [r3, #0]
8006ab8: 6a3a ldr r2, [r7, #32]
8006aba: 60da str r2, [r3, #12]
8006abc: e0c8 b.n 8006c50 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8006abe: 2301 movs r3, #1
8006ac0: f887 302a strb.w r3, [r7, #42] @ 0x2a
8006ac4: e0c4 b.n 8006c50 <UART_SetConfig+0x564>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8006ac6: 697b ldr r3, [r7, #20]
8006ac8: 69db ldr r3, [r3, #28]
8006aca: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8006ace: d167 bne.n 8006ba0 <UART_SetConfig+0x4b4>
{
switch (clocksource)
8006ad0: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8006ad4: 2b08 cmp r3, #8
8006ad6: d828 bhi.n 8006b2a <UART_SetConfig+0x43e>
8006ad8: a201 add r2, pc, #4 @ (adr r2, 8006ae0 <UART_SetConfig+0x3f4>)
8006ada: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006ade: bf00 nop
8006ae0: 08006b05 .word 0x08006b05
8006ae4: 08006b0d .word 0x08006b0d
8006ae8: 08006b15 .word 0x08006b15
8006aec: 08006b2b .word 0x08006b2b
8006af0: 08006b1b .word 0x08006b1b
8006af4: 08006b2b .word 0x08006b2b
8006af8: 08006b2b .word 0x08006b2b
8006afc: 08006b2b .word 0x08006b2b
8006b00: 08006b23 .word 0x08006b23
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8006b04: f7fd fc1e bl 8004344 <HAL_RCC_GetPCLK1Freq>
8006b08: 6278 str r0, [r7, #36] @ 0x24
break;
8006b0a: e014 b.n 8006b36 <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8006b0c: f7fd fc30 bl 8004370 <HAL_RCC_GetPCLK2Freq>
8006b10: 6278 str r0, [r7, #36] @ 0x24
break;
8006b12: e010 b.n 8006b36 <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8006b14: 4b5a ldr r3, [pc, #360] @ (8006c80 <UART_SetConfig+0x594>)
8006b16: 627b str r3, [r7, #36] @ 0x24
break;
8006b18: e00d b.n 8006b36 <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8006b1a: f7fd fba5 bl 8004268 <HAL_RCC_GetSysClockFreq>
8006b1e: 6278 str r0, [r7, #36] @ 0x24
break;
8006b20: e009 b.n 8006b36 <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8006b22: f44f 4300 mov.w r3, #32768 @ 0x8000
8006b26: 627b str r3, [r7, #36] @ 0x24
break;
8006b28: e005 b.n 8006b36 <UART_SetConfig+0x44a>
default:
pclk = 0U;
8006b2a: 2300 movs r3, #0
8006b2c: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8006b2e: 2301 movs r3, #1
8006b30: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8006b34: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8006b36: 6a7b ldr r3, [r7, #36] @ 0x24
8006b38: 2b00 cmp r3, #0
8006b3a: f000 8089 beq.w 8006c50 <UART_SetConfig+0x564>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8006b3e: 697b ldr r3, [r7, #20]
8006b40: 6a5b ldr r3, [r3, #36] @ 0x24
8006b42: 4a4e ldr r2, [pc, #312] @ (8006c7c <UART_SetConfig+0x590>)
8006b44: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8006b48: 461a mov r2, r3
8006b4a: 6a7b ldr r3, [r7, #36] @ 0x24
8006b4c: fbb3 f3f2 udiv r3, r3, r2
8006b50: 005a lsls r2, r3, #1
8006b52: 697b ldr r3, [r7, #20]
8006b54: 685b ldr r3, [r3, #4]
8006b56: 085b lsrs r3, r3, #1
8006b58: 441a add r2, r3
8006b5a: 697b ldr r3, [r7, #20]
8006b5c: 685b ldr r3, [r3, #4]
8006b5e: fbb2 f3f3 udiv r3, r2, r3
8006b62: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8006b64: 6a3b ldr r3, [r7, #32]
8006b66: 2b0f cmp r3, #15
8006b68: d916 bls.n 8006b98 <UART_SetConfig+0x4ac>
8006b6a: 6a3b ldr r3, [r7, #32]
8006b6c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8006b70: d212 bcs.n 8006b98 <UART_SetConfig+0x4ac>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8006b72: 6a3b ldr r3, [r7, #32]
8006b74: b29b uxth r3, r3
8006b76: f023 030f bic.w r3, r3, #15
8006b7a: 83fb strh r3, [r7, #30]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8006b7c: 6a3b ldr r3, [r7, #32]
8006b7e: 085b lsrs r3, r3, #1
8006b80: b29b uxth r3, r3
8006b82: f003 0307 and.w r3, r3, #7
8006b86: b29a uxth r2, r3
8006b88: 8bfb ldrh r3, [r7, #30]
8006b8a: 4313 orrs r3, r2
8006b8c: 83fb strh r3, [r7, #30]
huart->Instance->BRR = brrtemp;
8006b8e: 697b ldr r3, [r7, #20]
8006b90: 681b ldr r3, [r3, #0]
8006b92: 8bfa ldrh r2, [r7, #30]
8006b94: 60da str r2, [r3, #12]
8006b96: e05b b.n 8006c50 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8006b98: 2301 movs r3, #1
8006b9a: f887 302a strb.w r3, [r7, #42] @ 0x2a
8006b9e: e057 b.n 8006c50 <UART_SetConfig+0x564>
}
}
}
else
{
switch (clocksource)
8006ba0: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8006ba4: 2b08 cmp r3, #8
8006ba6: d828 bhi.n 8006bfa <UART_SetConfig+0x50e>
8006ba8: a201 add r2, pc, #4 @ (adr r2, 8006bb0 <UART_SetConfig+0x4c4>)
8006baa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8006bae: bf00 nop
8006bb0: 08006bd5 .word 0x08006bd5
8006bb4: 08006bdd .word 0x08006bdd
8006bb8: 08006be5 .word 0x08006be5
8006bbc: 08006bfb .word 0x08006bfb
8006bc0: 08006beb .word 0x08006beb
8006bc4: 08006bfb .word 0x08006bfb
8006bc8: 08006bfb .word 0x08006bfb
8006bcc: 08006bfb .word 0x08006bfb
8006bd0: 08006bf3 .word 0x08006bf3
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8006bd4: f7fd fbb6 bl 8004344 <HAL_RCC_GetPCLK1Freq>
8006bd8: 6278 str r0, [r7, #36] @ 0x24
break;
8006bda: e014 b.n 8006c06 <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8006bdc: f7fd fbc8 bl 8004370 <HAL_RCC_GetPCLK2Freq>
8006be0: 6278 str r0, [r7, #36] @ 0x24
break;
8006be2: e010 b.n 8006c06 <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8006be4: 4b26 ldr r3, [pc, #152] @ (8006c80 <UART_SetConfig+0x594>)
8006be6: 627b str r3, [r7, #36] @ 0x24
break;
8006be8: e00d b.n 8006c06 <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8006bea: f7fd fb3d bl 8004268 <HAL_RCC_GetSysClockFreq>
8006bee: 6278 str r0, [r7, #36] @ 0x24
break;
8006bf0: e009 b.n 8006c06 <UART_SetConfig+0x51a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8006bf2: f44f 4300 mov.w r3, #32768 @ 0x8000
8006bf6: 627b str r3, [r7, #36] @ 0x24
break;
8006bf8: e005 b.n 8006c06 <UART_SetConfig+0x51a>
default:
pclk = 0U;
8006bfa: 2300 movs r3, #0
8006bfc: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8006bfe: 2301 movs r3, #1
8006c00: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8006c04: bf00 nop
}
if (pclk != 0U)
8006c06: 6a7b ldr r3, [r7, #36] @ 0x24
8006c08: 2b00 cmp r3, #0
8006c0a: d021 beq.n 8006c50 <UART_SetConfig+0x564>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8006c0c: 697b ldr r3, [r7, #20]
8006c0e: 6a5b ldr r3, [r3, #36] @ 0x24
8006c10: 4a1a ldr r2, [pc, #104] @ (8006c7c <UART_SetConfig+0x590>)
8006c12: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8006c16: 461a mov r2, r3
8006c18: 6a7b ldr r3, [r7, #36] @ 0x24
8006c1a: fbb3 f2f2 udiv r2, r3, r2
8006c1e: 697b ldr r3, [r7, #20]
8006c20: 685b ldr r3, [r3, #4]
8006c22: 085b lsrs r3, r3, #1
8006c24: 441a add r2, r3
8006c26: 697b ldr r3, [r7, #20]
8006c28: 685b ldr r3, [r3, #4]
8006c2a: fbb2 f3f3 udiv r3, r2, r3
8006c2e: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8006c30: 6a3b ldr r3, [r7, #32]
8006c32: 2b0f cmp r3, #15
8006c34: d909 bls.n 8006c4a <UART_SetConfig+0x55e>
8006c36: 6a3b ldr r3, [r7, #32]
8006c38: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8006c3c: d205 bcs.n 8006c4a <UART_SetConfig+0x55e>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8006c3e: 6a3b ldr r3, [r7, #32]
8006c40: b29a uxth r2, r3
8006c42: 697b ldr r3, [r7, #20]
8006c44: 681b ldr r3, [r3, #0]
8006c46: 60da str r2, [r3, #12]
8006c48: e002 b.n 8006c50 <UART_SetConfig+0x564>
}
else
{
ret = HAL_ERROR;
8006c4a: 2301 movs r3, #1
8006c4c: f887 302a strb.w r3, [r7, #42] @ 0x2a
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
8006c50: 697b ldr r3, [r7, #20]
8006c52: 2201 movs r2, #1
8006c54: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1;
8006c58: 697b ldr r3, [r7, #20]
8006c5a: 2201 movs r2, #1
8006c5c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
/* Clear ISR function pointers */
huart->RxISR = NULL;
8006c60: 697b ldr r3, [r7, #20]
8006c62: 2200 movs r2, #0
8006c64: 675a str r2, [r3, #116] @ 0x74
huart->TxISR = NULL;
8006c66: 697b ldr r3, [r7, #20]
8006c68: 2200 movs r2, #0
8006c6a: 679a str r2, [r3, #120] @ 0x78
return ret;
8006c6c: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
}
8006c70: 4618 mov r0, r3
8006c72: 3730 adds r7, #48 @ 0x30
8006c74: 46bd mov sp, r7
8006c76: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8006c7a: bf00 nop
8006c7c: 080080c4 .word 0x080080c4
8006c80: 00f42400 .word 0x00f42400
08006c84 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8006c84: b480 push {r7}
8006c86: b083 sub sp, #12
8006c88: af00 add r7, sp, #0
8006c8a: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8006c8c: 687b ldr r3, [r7, #4]
8006c8e: 6a9b ldr r3, [r3, #40] @ 0x28
8006c90: f003 0308 and.w r3, r3, #8
8006c94: 2b00 cmp r3, #0
8006c96: d00a beq.n 8006cae <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8006c98: 687b ldr r3, [r7, #4]
8006c9a: 681b ldr r3, [r3, #0]
8006c9c: 685b ldr r3, [r3, #4]
8006c9e: f423 4100 bic.w r1, r3, #32768 @ 0x8000
8006ca2: 687b ldr r3, [r7, #4]
8006ca4: 6b9a ldr r2, [r3, #56] @ 0x38
8006ca6: 687b ldr r3, [r7, #4]
8006ca8: 681b ldr r3, [r3, #0]
8006caa: 430a orrs r2, r1
8006cac: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8006cae: 687b ldr r3, [r7, #4]
8006cb0: 6a9b ldr r3, [r3, #40] @ 0x28
8006cb2: f003 0301 and.w r3, r3, #1
8006cb6: 2b00 cmp r3, #0
8006cb8: d00a beq.n 8006cd0 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8006cba: 687b ldr r3, [r7, #4]
8006cbc: 681b ldr r3, [r3, #0]
8006cbe: 685b ldr r3, [r3, #4]
8006cc0: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8006cc4: 687b ldr r3, [r7, #4]
8006cc6: 6ada ldr r2, [r3, #44] @ 0x2c
8006cc8: 687b ldr r3, [r7, #4]
8006cca: 681b ldr r3, [r3, #0]
8006ccc: 430a orrs r2, r1
8006cce: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8006cd0: 687b ldr r3, [r7, #4]
8006cd2: 6a9b ldr r3, [r3, #40] @ 0x28
8006cd4: f003 0302 and.w r3, r3, #2
8006cd8: 2b00 cmp r3, #0
8006cda: d00a beq.n 8006cf2 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8006cdc: 687b ldr r3, [r7, #4]
8006cde: 681b ldr r3, [r3, #0]
8006ce0: 685b ldr r3, [r3, #4]
8006ce2: f423 3180 bic.w r1, r3, #65536 @ 0x10000
8006ce6: 687b ldr r3, [r7, #4]
8006ce8: 6b1a ldr r2, [r3, #48] @ 0x30
8006cea: 687b ldr r3, [r7, #4]
8006cec: 681b ldr r3, [r3, #0]
8006cee: 430a orrs r2, r1
8006cf0: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8006cf2: 687b ldr r3, [r7, #4]
8006cf4: 6a9b ldr r3, [r3, #40] @ 0x28
8006cf6: f003 0304 and.w r3, r3, #4
8006cfa: 2b00 cmp r3, #0
8006cfc: d00a beq.n 8006d14 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8006cfe: 687b ldr r3, [r7, #4]
8006d00: 681b ldr r3, [r3, #0]
8006d02: 685b ldr r3, [r3, #4]
8006d04: f423 2180 bic.w r1, r3, #262144 @ 0x40000
8006d08: 687b ldr r3, [r7, #4]
8006d0a: 6b5a ldr r2, [r3, #52] @ 0x34
8006d0c: 687b ldr r3, [r7, #4]
8006d0e: 681b ldr r3, [r3, #0]
8006d10: 430a orrs r2, r1
8006d12: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8006d14: 687b ldr r3, [r7, #4]
8006d16: 6a9b ldr r3, [r3, #40] @ 0x28
8006d18: f003 0310 and.w r3, r3, #16
8006d1c: 2b00 cmp r3, #0
8006d1e: d00a beq.n 8006d36 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8006d20: 687b ldr r3, [r7, #4]
8006d22: 681b ldr r3, [r3, #0]
8006d24: 689b ldr r3, [r3, #8]
8006d26: f423 5180 bic.w r1, r3, #4096 @ 0x1000
8006d2a: 687b ldr r3, [r7, #4]
8006d2c: 6bda ldr r2, [r3, #60] @ 0x3c
8006d2e: 687b ldr r3, [r7, #4]
8006d30: 681b ldr r3, [r3, #0]
8006d32: 430a orrs r2, r1
8006d34: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8006d36: 687b ldr r3, [r7, #4]
8006d38: 6a9b ldr r3, [r3, #40] @ 0x28
8006d3a: f003 0320 and.w r3, r3, #32
8006d3e: 2b00 cmp r3, #0
8006d40: d00a beq.n 8006d58 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8006d42: 687b ldr r3, [r7, #4]
8006d44: 681b ldr r3, [r3, #0]
8006d46: 689b ldr r3, [r3, #8]
8006d48: f423 5100 bic.w r1, r3, #8192 @ 0x2000
8006d4c: 687b ldr r3, [r7, #4]
8006d4e: 6c1a ldr r2, [r3, #64] @ 0x40
8006d50: 687b ldr r3, [r7, #4]
8006d52: 681b ldr r3, [r3, #0]
8006d54: 430a orrs r2, r1
8006d56: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8006d58: 687b ldr r3, [r7, #4]
8006d5a: 6a9b ldr r3, [r3, #40] @ 0x28
8006d5c: f003 0340 and.w r3, r3, #64 @ 0x40
8006d60: 2b00 cmp r3, #0
8006d62: d01a beq.n 8006d9a <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8006d64: 687b ldr r3, [r7, #4]
8006d66: 681b ldr r3, [r3, #0]
8006d68: 685b ldr r3, [r3, #4]
8006d6a: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
8006d6e: 687b ldr r3, [r7, #4]
8006d70: 6c5a ldr r2, [r3, #68] @ 0x44
8006d72: 687b ldr r3, [r7, #4]
8006d74: 681b ldr r3, [r3, #0]
8006d76: 430a orrs r2, r1
8006d78: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8006d7a: 687b ldr r3, [r7, #4]
8006d7c: 6c5b ldr r3, [r3, #68] @ 0x44
8006d7e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8006d82: d10a bne.n 8006d9a <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8006d84: 687b ldr r3, [r7, #4]
8006d86: 681b ldr r3, [r3, #0]
8006d88: 685b ldr r3, [r3, #4]
8006d8a: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
8006d8e: 687b ldr r3, [r7, #4]
8006d90: 6c9a ldr r2, [r3, #72] @ 0x48
8006d92: 687b ldr r3, [r7, #4]
8006d94: 681b ldr r3, [r3, #0]
8006d96: 430a orrs r2, r1
8006d98: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8006d9a: 687b ldr r3, [r7, #4]
8006d9c: 6a9b ldr r3, [r3, #40] @ 0x28
8006d9e: f003 0380 and.w r3, r3, #128 @ 0x80
8006da2: 2b00 cmp r3, #0
8006da4: d00a beq.n 8006dbc <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8006da6: 687b ldr r3, [r7, #4]
8006da8: 681b ldr r3, [r3, #0]
8006daa: 685b ldr r3, [r3, #4]
8006dac: f423 2100 bic.w r1, r3, #524288 @ 0x80000
8006db0: 687b ldr r3, [r7, #4]
8006db2: 6cda ldr r2, [r3, #76] @ 0x4c
8006db4: 687b ldr r3, [r7, #4]
8006db6: 681b ldr r3, [r3, #0]
8006db8: 430a orrs r2, r1
8006dba: 605a str r2, [r3, #4]
}
}
8006dbc: bf00 nop
8006dbe: 370c adds r7, #12
8006dc0: 46bd mov sp, r7
8006dc2: f85d 7b04 ldr.w r7, [sp], #4
8006dc6: 4770 bx lr
08006dc8 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8006dc8: b580 push {r7, lr}
8006dca: b098 sub sp, #96 @ 0x60
8006dcc: af02 add r7, sp, #8
8006dce: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8006dd0: 687b ldr r3, [r7, #4]
8006dd2: 2200 movs r2, #0
8006dd4: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8006dd8: f7fa fd10 bl 80017fc <HAL_GetTick>
8006ddc: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8006dde: 687b ldr r3, [r7, #4]
8006de0: 681b ldr r3, [r3, #0]
8006de2: 681b ldr r3, [r3, #0]
8006de4: f003 0308 and.w r3, r3, #8
8006de8: 2b08 cmp r3, #8
8006dea: d12f bne.n 8006e4c <UART_CheckIdleState+0x84>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8006dec: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8006df0: 9300 str r3, [sp, #0]
8006df2: 6d7b ldr r3, [r7, #84] @ 0x54
8006df4: 2200 movs r2, #0
8006df6: f44f 1100 mov.w r1, #2097152 @ 0x200000
8006dfa: 6878 ldr r0, [r7, #4]
8006dfc: f000 f88e bl 8006f1c <UART_WaitOnFlagUntilTimeout>
8006e00: 4603 mov r3, r0
8006e02: 2b00 cmp r3, #0
8006e04: d022 beq.n 8006e4c <UART_CheckIdleState+0x84>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
8006e06: 687b ldr r3, [r7, #4]
8006e08: 681b ldr r3, [r3, #0]
8006e0a: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006e0c: 6bbb ldr r3, [r7, #56] @ 0x38
8006e0e: e853 3f00 ldrex r3, [r3]
8006e12: 637b str r3, [r7, #52] @ 0x34
return(result);
8006e14: 6b7b ldr r3, [r7, #52] @ 0x34
8006e16: f023 0380 bic.w r3, r3, #128 @ 0x80
8006e1a: 653b str r3, [r7, #80] @ 0x50
8006e1c: 687b ldr r3, [r7, #4]
8006e1e: 681b ldr r3, [r3, #0]
8006e20: 461a mov r2, r3
8006e22: 6d3b ldr r3, [r7, #80] @ 0x50
8006e24: 647b str r3, [r7, #68] @ 0x44
8006e26: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006e28: 6c39 ldr r1, [r7, #64] @ 0x40
8006e2a: 6c7a ldr r2, [r7, #68] @ 0x44
8006e2c: e841 2300 strex r3, r2, [r1]
8006e30: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8006e32: 6bfb ldr r3, [r7, #60] @ 0x3c
8006e34: 2b00 cmp r3, #0
8006e36: d1e6 bne.n 8006e06 <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
8006e38: 687b ldr r3, [r7, #4]
8006e3a: 2220 movs r2, #32
8006e3c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
8006e40: 687b ldr r3, [r7, #4]
8006e42: 2200 movs r2, #0
8006e44: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
8006e48: 2303 movs r3, #3
8006e4a: e063 b.n 8006f14 <UART_CheckIdleState+0x14c>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8006e4c: 687b ldr r3, [r7, #4]
8006e4e: 681b ldr r3, [r3, #0]
8006e50: 681b ldr r3, [r3, #0]
8006e52: f003 0304 and.w r3, r3, #4
8006e56: 2b04 cmp r3, #4
8006e58: d149 bne.n 8006eee <UART_CheckIdleState+0x126>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8006e5a: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
8006e5e: 9300 str r3, [sp, #0]
8006e60: 6d7b ldr r3, [r7, #84] @ 0x54
8006e62: 2200 movs r2, #0
8006e64: f44f 0180 mov.w r1, #4194304 @ 0x400000
8006e68: 6878 ldr r0, [r7, #4]
8006e6a: f000 f857 bl 8006f1c <UART_WaitOnFlagUntilTimeout>
8006e6e: 4603 mov r3, r0
8006e70: 2b00 cmp r3, #0
8006e72: d03c beq.n 8006eee <UART_CheckIdleState+0x126>
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006e74: 687b ldr r3, [r7, #4]
8006e76: 681b ldr r3, [r3, #0]
8006e78: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006e7a: 6a7b ldr r3, [r7, #36] @ 0x24
8006e7c: e853 3f00 ldrex r3, [r3]
8006e80: 623b str r3, [r7, #32]
return(result);
8006e82: 6a3b ldr r3, [r7, #32]
8006e84: f423 7390 bic.w r3, r3, #288 @ 0x120
8006e88: 64fb str r3, [r7, #76] @ 0x4c
8006e8a: 687b ldr r3, [r7, #4]
8006e8c: 681b ldr r3, [r3, #0]
8006e8e: 461a mov r2, r3
8006e90: 6cfb ldr r3, [r7, #76] @ 0x4c
8006e92: 633b str r3, [r7, #48] @ 0x30
8006e94: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006e96: 6af9 ldr r1, [r7, #44] @ 0x2c
8006e98: 6b3a ldr r2, [r7, #48] @ 0x30
8006e9a: e841 2300 strex r3, r2, [r1]
8006e9e: 62bb str r3, [r7, #40] @ 0x28
return(result);
8006ea0: 6abb ldr r3, [r7, #40] @ 0x28
8006ea2: 2b00 cmp r3, #0
8006ea4: d1e6 bne.n 8006e74 <UART_CheckIdleState+0xac>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006ea6: 687b ldr r3, [r7, #4]
8006ea8: 681b ldr r3, [r3, #0]
8006eaa: 3308 adds r3, #8
8006eac: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8006eae: 693b ldr r3, [r7, #16]
8006eb0: e853 3f00 ldrex r3, [r3]
8006eb4: 60fb str r3, [r7, #12]
return(result);
8006eb6: 68fb ldr r3, [r7, #12]
8006eb8: f023 0301 bic.w r3, r3, #1
8006ebc: 64bb str r3, [r7, #72] @ 0x48
8006ebe: 687b ldr r3, [r7, #4]
8006ec0: 681b ldr r3, [r3, #0]
8006ec2: 3308 adds r3, #8
8006ec4: 6cba ldr r2, [r7, #72] @ 0x48
8006ec6: 61fa str r2, [r7, #28]
8006ec8: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8006eca: 69b9 ldr r1, [r7, #24]
8006ecc: 69fa ldr r2, [r7, #28]
8006ece: e841 2300 strex r3, r2, [r1]
8006ed2: 617b str r3, [r7, #20]
return(result);
8006ed4: 697b ldr r3, [r7, #20]
8006ed6: 2b00 cmp r3, #0
8006ed8: d1e5 bne.n 8006ea6 <UART_CheckIdleState+0xde>
huart->RxState = HAL_UART_STATE_READY;
8006eda: 687b ldr r3, [r7, #4]
8006edc: 2220 movs r2, #32
8006ede: f8c3 208c str.w r2, [r3, #140] @ 0x8c
__HAL_UNLOCK(huart);
8006ee2: 687b ldr r3, [r7, #4]
8006ee4: 2200 movs r2, #0
8006ee6: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
8006eea: 2303 movs r3, #3
8006eec: e012 b.n 8006f14 <UART_CheckIdleState+0x14c>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8006eee: 687b ldr r3, [r7, #4]
8006ef0: 2220 movs r2, #32
8006ef2: f8c3 2088 str.w r2, [r3, #136] @ 0x88
huart->RxState = HAL_UART_STATE_READY;
8006ef6: 687b ldr r3, [r7, #4]
8006ef8: 2220 movs r2, #32
8006efa: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006efe: 687b ldr r3, [r7, #4]
8006f00: 2200 movs r2, #0
8006f02: 66da str r2, [r3, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8006f04: 687b ldr r3, [r7, #4]
8006f06: 2200 movs r2, #0
8006f08: 671a str r2, [r3, #112] @ 0x70
__HAL_UNLOCK(huart);
8006f0a: 687b ldr r3, [r7, #4]
8006f0c: 2200 movs r2, #0
8006f0e: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8006f12: 2300 movs r3, #0
}
8006f14: 4618 mov r0, r3
8006f16: 3758 adds r7, #88 @ 0x58
8006f18: 46bd mov sp, r7
8006f1a: bd80 pop {r7, pc}
08006f1c <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8006f1c: b580 push {r7, lr}
8006f1e: b084 sub sp, #16
8006f20: af00 add r7, sp, #0
8006f22: 60f8 str r0, [r7, #12]
8006f24: 60b9 str r1, [r7, #8]
8006f26: 603b str r3, [r7, #0]
8006f28: 4613 mov r3, r2
8006f2a: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8006f2c: e04f b.n 8006fce <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8006f2e: 69bb ldr r3, [r7, #24]
8006f30: f1b3 3fff cmp.w r3, #4294967295
8006f34: d04b beq.n 8006fce <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8006f36: f7fa fc61 bl 80017fc <HAL_GetTick>
8006f3a: 4602 mov r2, r0
8006f3c: 683b ldr r3, [r7, #0]
8006f3e: 1ad3 subs r3, r2, r3
8006f40: 69ba ldr r2, [r7, #24]
8006f42: 429a cmp r2, r3
8006f44: d302 bcc.n 8006f4c <UART_WaitOnFlagUntilTimeout+0x30>
8006f46: 69bb ldr r3, [r7, #24]
8006f48: 2b00 cmp r3, #0
8006f4a: d101 bne.n 8006f50 <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
8006f4c: 2303 movs r3, #3
8006f4e: e04e b.n 8006fee <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8006f50: 68fb ldr r3, [r7, #12]
8006f52: 681b ldr r3, [r3, #0]
8006f54: 681b ldr r3, [r3, #0]
8006f56: f003 0304 and.w r3, r3, #4
8006f5a: 2b00 cmp r3, #0
8006f5c: d037 beq.n 8006fce <UART_WaitOnFlagUntilTimeout+0xb2>
8006f5e: 68bb ldr r3, [r7, #8]
8006f60: 2b80 cmp r3, #128 @ 0x80
8006f62: d034 beq.n 8006fce <UART_WaitOnFlagUntilTimeout+0xb2>
8006f64: 68bb ldr r3, [r7, #8]
8006f66: 2b40 cmp r3, #64 @ 0x40
8006f68: d031 beq.n 8006fce <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8006f6a: 68fb ldr r3, [r7, #12]
8006f6c: 681b ldr r3, [r3, #0]
8006f6e: 69db ldr r3, [r3, #28]
8006f70: f003 0308 and.w r3, r3, #8
8006f74: 2b08 cmp r3, #8
8006f76: d110 bne.n 8006f9a <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8006f78: 68fb ldr r3, [r7, #12]
8006f7a: 681b ldr r3, [r3, #0]
8006f7c: 2208 movs r2, #8
8006f7e: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8006f80: 68f8 ldr r0, [r7, #12]
8006f82: f000 f95b bl 800723c <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8006f86: 68fb ldr r3, [r7, #12]
8006f88: 2208 movs r2, #8
8006f8a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
8006f8e: 68fb ldr r3, [r7, #12]
8006f90: 2200 movs r2, #0
8006f92: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_ERROR;
8006f96: 2301 movs r3, #1
8006f98: e029 b.n 8006fee <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8006f9a: 68fb ldr r3, [r7, #12]
8006f9c: 681b ldr r3, [r3, #0]
8006f9e: 69db ldr r3, [r3, #28]
8006fa0: f403 6300 and.w r3, r3, #2048 @ 0x800
8006fa4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8006fa8: d111 bne.n 8006fce <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8006faa: 68fb ldr r3, [r7, #12]
8006fac: 681b ldr r3, [r3, #0]
8006fae: f44f 6200 mov.w r2, #2048 @ 0x800
8006fb2: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8006fb4: 68f8 ldr r0, [r7, #12]
8006fb6: f000 f941 bl 800723c <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8006fba: 68fb ldr r3, [r7, #12]
8006fbc: 2220 movs r2, #32
8006fbe: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
8006fc2: 68fb ldr r3, [r7, #12]
8006fc4: 2200 movs r2, #0
8006fc6: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_TIMEOUT;
8006fca: 2303 movs r3, #3
8006fcc: e00f b.n 8006fee <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8006fce: 68fb ldr r3, [r7, #12]
8006fd0: 681b ldr r3, [r3, #0]
8006fd2: 69da ldr r2, [r3, #28]
8006fd4: 68bb ldr r3, [r7, #8]
8006fd6: 4013 ands r3, r2
8006fd8: 68ba ldr r2, [r7, #8]
8006fda: 429a cmp r2, r3
8006fdc: bf0c ite eq
8006fde: 2301 moveq r3, #1
8006fe0: 2300 movne r3, #0
8006fe2: b2db uxtb r3, r3
8006fe4: 461a mov r2, r3
8006fe6: 79fb ldrb r3, [r7, #7]
8006fe8: 429a cmp r2, r3
8006fea: d0a0 beq.n 8006f2e <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8006fec: 2300 movs r3, #0
}
8006fee: 4618 mov r0, r3
8006ff0: 3710 adds r7, #16
8006ff2: 46bd mov sp, r7
8006ff4: bd80 pop {r7, pc}
...
08006ff8 <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8006ff8: b480 push {r7}
8006ffa: b0a3 sub sp, #140 @ 0x8c
8006ffc: af00 add r7, sp, #0
8006ffe: 60f8 str r0, [r7, #12]
8007000: 60b9 str r1, [r7, #8]
8007002: 4613 mov r3, r2
8007004: 80fb strh r3, [r7, #6]
huart->pRxBuffPtr = pData;
8007006: 68fb ldr r3, [r7, #12]
8007008: 68ba ldr r2, [r7, #8]
800700a: 659a str r2, [r3, #88] @ 0x58
huart->RxXferSize = Size;
800700c: 68fb ldr r3, [r7, #12]
800700e: 88fa ldrh r2, [r7, #6]
8007010: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
huart->RxXferCount = Size;
8007014: 68fb ldr r3, [r7, #12]
8007016: 88fa ldrh r2, [r7, #6]
8007018: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
huart->RxISR = NULL;
800701c: 68fb ldr r3, [r7, #12]
800701e: 2200 movs r2, #0
8007020: 675a str r2, [r3, #116] @ 0x74
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
8007022: 68fb ldr r3, [r7, #12]
8007024: 689b ldr r3, [r3, #8]
8007026: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800702a: d10e bne.n 800704a <UART_Start_Receive_IT+0x52>
800702c: 68fb ldr r3, [r7, #12]
800702e: 691b ldr r3, [r3, #16]
8007030: 2b00 cmp r3, #0
8007032: d105 bne.n 8007040 <UART_Start_Receive_IT+0x48>
8007034: 68fb ldr r3, [r7, #12]
8007036: f240 12ff movw r2, #511 @ 0x1ff
800703a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
800703e: e02d b.n 800709c <UART_Start_Receive_IT+0xa4>
8007040: 68fb ldr r3, [r7, #12]
8007042: 22ff movs r2, #255 @ 0xff
8007044: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007048: e028 b.n 800709c <UART_Start_Receive_IT+0xa4>
800704a: 68fb ldr r3, [r7, #12]
800704c: 689b ldr r3, [r3, #8]
800704e: 2b00 cmp r3, #0
8007050: d10d bne.n 800706e <UART_Start_Receive_IT+0x76>
8007052: 68fb ldr r3, [r7, #12]
8007054: 691b ldr r3, [r3, #16]
8007056: 2b00 cmp r3, #0
8007058: d104 bne.n 8007064 <UART_Start_Receive_IT+0x6c>
800705a: 68fb ldr r3, [r7, #12]
800705c: 22ff movs r2, #255 @ 0xff
800705e: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007062: e01b b.n 800709c <UART_Start_Receive_IT+0xa4>
8007064: 68fb ldr r3, [r7, #12]
8007066: 227f movs r2, #127 @ 0x7f
8007068: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
800706c: e016 b.n 800709c <UART_Start_Receive_IT+0xa4>
800706e: 68fb ldr r3, [r7, #12]
8007070: 689b ldr r3, [r3, #8]
8007072: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8007076: d10d bne.n 8007094 <UART_Start_Receive_IT+0x9c>
8007078: 68fb ldr r3, [r7, #12]
800707a: 691b ldr r3, [r3, #16]
800707c: 2b00 cmp r3, #0
800707e: d104 bne.n 800708a <UART_Start_Receive_IT+0x92>
8007080: 68fb ldr r3, [r7, #12]
8007082: 227f movs r2, #127 @ 0x7f
8007084: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007088: e008 b.n 800709c <UART_Start_Receive_IT+0xa4>
800708a: 68fb ldr r3, [r7, #12]
800708c: 223f movs r2, #63 @ 0x3f
800708e: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
8007092: e003 b.n 800709c <UART_Start_Receive_IT+0xa4>
8007094: 68fb ldr r3, [r7, #12]
8007096: 2200 movs r2, #0
8007098: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
huart->ErrorCode = HAL_UART_ERROR_NONE;
800709c: 68fb ldr r3, [r7, #12]
800709e: 2200 movs r2, #0
80070a0: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->RxState = HAL_UART_STATE_BUSY_RX;
80070a4: 68fb ldr r3, [r7, #12]
80070a6: 2222 movs r2, #34 @ 0x22
80070a8: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
80070ac: 68fb ldr r3, [r7, #12]
80070ae: 681b ldr r3, [r3, #0]
80070b0: 3308 adds r3, #8
80070b2: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80070b4: 6e7b ldr r3, [r7, #100] @ 0x64
80070b6: e853 3f00 ldrex r3, [r3]
80070ba: 663b str r3, [r7, #96] @ 0x60
return(result);
80070bc: 6e3b ldr r3, [r7, #96] @ 0x60
80070be: f043 0301 orr.w r3, r3, #1
80070c2: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80070c6: 68fb ldr r3, [r7, #12]
80070c8: 681b ldr r3, [r3, #0]
80070ca: 3308 adds r3, #8
80070cc: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
80070d0: 673a str r2, [r7, #112] @ 0x70
80070d2: 66fb str r3, [r7, #108] @ 0x6c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80070d4: 6ef9 ldr r1, [r7, #108] @ 0x6c
80070d6: 6f3a ldr r2, [r7, #112] @ 0x70
80070d8: e841 2300 strex r3, r2, [r1]
80070dc: 66bb str r3, [r7, #104] @ 0x68
return(result);
80070de: 6ebb ldr r3, [r7, #104] @ 0x68
80070e0: 2b00 cmp r3, #0
80070e2: d1e3 bne.n 80070ac <UART_Start_Receive_IT+0xb4>
/* Configure Rx interrupt processing */
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
80070e4: 68fb ldr r3, [r7, #12]
80070e6: 6e5b ldr r3, [r3, #100] @ 0x64
80070e8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80070ec: d14f bne.n 800718e <UART_Start_Receive_IT+0x196>
80070ee: 68fb ldr r3, [r7, #12]
80070f0: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
80070f4: 88fa ldrh r2, [r7, #6]
80070f6: 429a cmp r2, r3
80070f8: d349 bcc.n 800718e <UART_Start_Receive_IT+0x196>
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80070fa: 68fb ldr r3, [r7, #12]
80070fc: 689b ldr r3, [r3, #8]
80070fe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8007102: d107 bne.n 8007114 <UART_Start_Receive_IT+0x11c>
8007104: 68fb ldr r3, [r7, #12]
8007106: 691b ldr r3, [r3, #16]
8007108: 2b00 cmp r3, #0
800710a: d103 bne.n 8007114 <UART_Start_Receive_IT+0x11c>
{
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
800710c: 68fb ldr r3, [r7, #12]
800710e: 4a47 ldr r2, [pc, #284] @ (800722c <UART_Start_Receive_IT+0x234>)
8007110: 675a str r2, [r3, #116] @ 0x74
8007112: e002 b.n 800711a <UART_Start_Receive_IT+0x122>
}
else
{
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
8007114: 68fb ldr r3, [r7, #12]
8007116: 4a46 ldr r2, [pc, #280] @ (8007230 <UART_Start_Receive_IT+0x238>)
8007118: 675a str r2, [r3, #116] @ 0x74
}
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
800711a: 68fb ldr r3, [r7, #12]
800711c: 691b ldr r3, [r3, #16]
800711e: 2b00 cmp r3, #0
8007120: d01a beq.n 8007158 <UART_Start_Receive_IT+0x160>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8007122: 68fb ldr r3, [r7, #12]
8007124: 681b ldr r3, [r3, #0]
8007126: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007128: 6d3b ldr r3, [r7, #80] @ 0x50
800712a: e853 3f00 ldrex r3, [r3]
800712e: 64fb str r3, [r7, #76] @ 0x4c
return(result);
8007130: 6cfb ldr r3, [r7, #76] @ 0x4c
8007132: f443 7380 orr.w r3, r3, #256 @ 0x100
8007136: f8c7 3080 str.w r3, [r7, #128] @ 0x80
800713a: 68fb ldr r3, [r7, #12]
800713c: 681b ldr r3, [r3, #0]
800713e: 461a mov r2, r3
8007140: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8007144: 65fb str r3, [r7, #92] @ 0x5c
8007146: 65ba str r2, [r7, #88] @ 0x58
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007148: 6db9 ldr r1, [r7, #88] @ 0x58
800714a: 6dfa ldr r2, [r7, #92] @ 0x5c
800714c: e841 2300 strex r3, r2, [r1]
8007150: 657b str r3, [r7, #84] @ 0x54
return(result);
8007152: 6d7b ldr r3, [r7, #84] @ 0x54
8007154: 2b00 cmp r3, #0
8007156: d1e4 bne.n 8007122 <UART_Start_Receive_IT+0x12a>
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8007158: 68fb ldr r3, [r7, #12]
800715a: 681b ldr r3, [r3, #0]
800715c: 3308 adds r3, #8
800715e: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007160: 6bfb ldr r3, [r7, #60] @ 0x3c
8007162: e853 3f00 ldrex r3, [r3]
8007166: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007168: 6bbb ldr r3, [r7, #56] @ 0x38
800716a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
800716e: 67fb str r3, [r7, #124] @ 0x7c
8007170: 68fb ldr r3, [r7, #12]
8007172: 681b ldr r3, [r3, #0]
8007174: 3308 adds r3, #8
8007176: 6ffa ldr r2, [r7, #124] @ 0x7c
8007178: 64ba str r2, [r7, #72] @ 0x48
800717a: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800717c: 6c79 ldr r1, [r7, #68] @ 0x44
800717e: 6cba ldr r2, [r7, #72] @ 0x48
8007180: e841 2300 strex r3, r2, [r1]
8007184: 643b str r3, [r7, #64] @ 0x40
return(result);
8007186: 6c3b ldr r3, [r7, #64] @ 0x40
8007188: 2b00 cmp r3, #0
800718a: d1e5 bne.n 8007158 <UART_Start_Receive_IT+0x160>
800718c: e046 b.n 800721c <UART_Start_Receive_IT+0x224>
}
else
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
800718e: 68fb ldr r3, [r7, #12]
8007190: 689b ldr r3, [r3, #8]
8007192: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8007196: d107 bne.n 80071a8 <UART_Start_Receive_IT+0x1b0>
8007198: 68fb ldr r3, [r7, #12]
800719a: 691b ldr r3, [r3, #16]
800719c: 2b00 cmp r3, #0
800719e: d103 bne.n 80071a8 <UART_Start_Receive_IT+0x1b0>
{
huart->RxISR = UART_RxISR_16BIT;
80071a0: 68fb ldr r3, [r7, #12]
80071a2: 4a24 ldr r2, [pc, #144] @ (8007234 <UART_Start_Receive_IT+0x23c>)
80071a4: 675a str r2, [r3, #116] @ 0x74
80071a6: e002 b.n 80071ae <UART_Start_Receive_IT+0x1b6>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
80071a8: 68fb ldr r3, [r7, #12]
80071aa: 4a23 ldr r2, [pc, #140] @ (8007238 <UART_Start_Receive_IT+0x240>)
80071ac: 675a str r2, [r3, #116] @ 0x74
}
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
80071ae: 68fb ldr r3, [r7, #12]
80071b0: 691b ldr r3, [r3, #16]
80071b2: 2b00 cmp r3, #0
80071b4: d019 beq.n 80071ea <UART_Start_Receive_IT+0x1f2>
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
80071b6: 68fb ldr r3, [r7, #12]
80071b8: 681b ldr r3, [r3, #0]
80071ba: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80071bc: 6abb ldr r3, [r7, #40] @ 0x28
80071be: e853 3f00 ldrex r3, [r3]
80071c2: 627b str r3, [r7, #36] @ 0x24
return(result);
80071c4: 6a7b ldr r3, [r7, #36] @ 0x24
80071c6: f443 7390 orr.w r3, r3, #288 @ 0x120
80071ca: 677b str r3, [r7, #116] @ 0x74
80071cc: 68fb ldr r3, [r7, #12]
80071ce: 681b ldr r3, [r3, #0]
80071d0: 461a mov r2, r3
80071d2: 6f7b ldr r3, [r7, #116] @ 0x74
80071d4: 637b str r3, [r7, #52] @ 0x34
80071d6: 633a str r2, [r7, #48] @ 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80071d8: 6b39 ldr r1, [r7, #48] @ 0x30
80071da: 6b7a ldr r2, [r7, #52] @ 0x34
80071dc: e841 2300 strex r3, r2, [r1]
80071e0: 62fb str r3, [r7, #44] @ 0x2c
return(result);
80071e2: 6afb ldr r3, [r7, #44] @ 0x2c
80071e4: 2b00 cmp r3, #0
80071e6: d1e6 bne.n 80071b6 <UART_Start_Receive_IT+0x1be>
80071e8: e018 b.n 800721c <UART_Start_Receive_IT+0x224>
}
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
80071ea: 68fb ldr r3, [r7, #12]
80071ec: 681b ldr r3, [r3, #0]
80071ee: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80071f0: 697b ldr r3, [r7, #20]
80071f2: e853 3f00 ldrex r3, [r3]
80071f6: 613b str r3, [r7, #16]
return(result);
80071f8: 693b ldr r3, [r7, #16]
80071fa: f043 0320 orr.w r3, r3, #32
80071fe: 67bb str r3, [r7, #120] @ 0x78
8007200: 68fb ldr r3, [r7, #12]
8007202: 681b ldr r3, [r3, #0]
8007204: 461a mov r2, r3
8007206: 6fbb ldr r3, [r7, #120] @ 0x78
8007208: 623b str r3, [r7, #32]
800720a: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800720c: 69f9 ldr r1, [r7, #28]
800720e: 6a3a ldr r2, [r7, #32]
8007210: e841 2300 strex r3, r2, [r1]
8007214: 61bb str r3, [r7, #24]
return(result);
8007216: 69bb ldr r3, [r7, #24]
8007218: 2b00 cmp r3, #0
800721a: d1e6 bne.n 80071ea <UART_Start_Receive_IT+0x1f2>
}
}
return HAL_OK;
800721c: 2300 movs r3, #0
}
800721e: 4618 mov r0, r3
8007220: 378c adds r7, #140 @ 0x8c
8007222: 46bd mov sp, r7
8007224: f85d 7b04 ldr.w r7, [sp], #4
8007228: 4770 bx lr
800722a: bf00 nop
800722c: 08007a59 .word 0x08007a59
8007230: 080076f5 .word 0x080076f5
8007234: 0800753d .word 0x0800753d
8007238: 08007385 .word 0x08007385
0800723c <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
800723c: b480 push {r7}
800723e: b095 sub sp, #84 @ 0x54
8007240: af00 add r7, sp, #0
8007242: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8007244: 687b ldr r3, [r7, #4]
8007246: 681b ldr r3, [r3, #0]
8007248: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800724a: 6b7b ldr r3, [r7, #52] @ 0x34
800724c: e853 3f00 ldrex r3, [r3]
8007250: 633b str r3, [r7, #48] @ 0x30
return(result);
8007252: 6b3b ldr r3, [r7, #48] @ 0x30
8007254: f423 7390 bic.w r3, r3, #288 @ 0x120
8007258: 64fb str r3, [r7, #76] @ 0x4c
800725a: 687b ldr r3, [r7, #4]
800725c: 681b ldr r3, [r3, #0]
800725e: 461a mov r2, r3
8007260: 6cfb ldr r3, [r7, #76] @ 0x4c
8007262: 643b str r3, [r7, #64] @ 0x40
8007264: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007266: 6bf9 ldr r1, [r7, #60] @ 0x3c
8007268: 6c3a ldr r2, [r7, #64] @ 0x40
800726a: e841 2300 strex r3, r2, [r1]
800726e: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007270: 6bbb ldr r3, [r7, #56] @ 0x38
8007272: 2b00 cmp r3, #0
8007274: d1e6 bne.n 8007244 <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8007276: 687b ldr r3, [r7, #4]
8007278: 681b ldr r3, [r3, #0]
800727a: 3308 adds r3, #8
800727c: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800727e: 6a3b ldr r3, [r7, #32]
8007280: e853 3f00 ldrex r3, [r3]
8007284: 61fb str r3, [r7, #28]
return(result);
8007286: 69fb ldr r3, [r7, #28]
8007288: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800728c: f023 0301 bic.w r3, r3, #1
8007290: 64bb str r3, [r7, #72] @ 0x48
8007292: 687b ldr r3, [r7, #4]
8007294: 681b ldr r3, [r3, #0]
8007296: 3308 adds r3, #8
8007298: 6cba ldr r2, [r7, #72] @ 0x48
800729a: 62fa str r2, [r7, #44] @ 0x2c
800729c: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800729e: 6ab9 ldr r1, [r7, #40] @ 0x28
80072a0: 6afa ldr r2, [r7, #44] @ 0x2c
80072a2: e841 2300 strex r3, r2, [r1]
80072a6: 627b str r3, [r7, #36] @ 0x24
return(result);
80072a8: 6a7b ldr r3, [r7, #36] @ 0x24
80072aa: 2b00 cmp r3, #0
80072ac: d1e3 bne.n 8007276 <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80072ae: 687b ldr r3, [r7, #4]
80072b0: 6edb ldr r3, [r3, #108] @ 0x6c
80072b2: 2b01 cmp r3, #1
80072b4: d118 bne.n 80072e8 <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80072b6: 687b ldr r3, [r7, #4]
80072b8: 681b ldr r3, [r3, #0]
80072ba: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80072bc: 68fb ldr r3, [r7, #12]
80072be: e853 3f00 ldrex r3, [r3]
80072c2: 60bb str r3, [r7, #8]
return(result);
80072c4: 68bb ldr r3, [r7, #8]
80072c6: f023 0310 bic.w r3, r3, #16
80072ca: 647b str r3, [r7, #68] @ 0x44
80072cc: 687b ldr r3, [r7, #4]
80072ce: 681b ldr r3, [r3, #0]
80072d0: 461a mov r2, r3
80072d2: 6c7b ldr r3, [r7, #68] @ 0x44
80072d4: 61bb str r3, [r7, #24]
80072d6: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80072d8: 6979 ldr r1, [r7, #20]
80072da: 69ba ldr r2, [r7, #24]
80072dc: e841 2300 strex r3, r2, [r1]
80072e0: 613b str r3, [r7, #16]
return(result);
80072e2: 693b ldr r3, [r7, #16]
80072e4: 2b00 cmp r3, #0
80072e6: d1e6 bne.n 80072b6 <UART_EndRxTransfer+0x7a>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80072e8: 687b ldr r3, [r7, #4]
80072ea: 2220 movs r2, #32
80072ec: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80072f0: 687b ldr r3, [r7, #4]
80072f2: 2200 movs r2, #0
80072f4: 66da str r2, [r3, #108] @ 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80072f6: 687b ldr r3, [r7, #4]
80072f8: 2200 movs r2, #0
80072fa: 675a str r2, [r3, #116] @ 0x74
}
80072fc: bf00 nop
80072fe: 3754 adds r7, #84 @ 0x54
8007300: 46bd mov sp, r7
8007302: f85d 7b04 ldr.w r7, [sp], #4
8007306: 4770 bx lr
08007308 <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8007308: b580 push {r7, lr}
800730a: b084 sub sp, #16
800730c: af00 add r7, sp, #0
800730e: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8007310: 687b ldr r3, [r7, #4]
8007312: 6a9b ldr r3, [r3, #40] @ 0x28
8007314: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
8007316: 68fb ldr r3, [r7, #12]
8007318: 2200 movs r2, #0
800731a: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800731e: 68f8 ldr r0, [r7, #12]
8007320: f7ff f9ce bl 80066c0 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8007324: bf00 nop
8007326: 3710 adds r7, #16
8007328: 46bd mov sp, r7
800732a: bd80 pop {r7, pc}
0800732c <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
800732c: b580 push {r7, lr}
800732e: b088 sub sp, #32
8007330: af00 add r7, sp, #0
8007332: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8007334: 687b ldr r3, [r7, #4]
8007336: 681b ldr r3, [r3, #0]
8007338: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800733a: 68fb ldr r3, [r7, #12]
800733c: e853 3f00 ldrex r3, [r3]
8007340: 60bb str r3, [r7, #8]
return(result);
8007342: 68bb ldr r3, [r7, #8]
8007344: f023 0340 bic.w r3, r3, #64 @ 0x40
8007348: 61fb str r3, [r7, #28]
800734a: 687b ldr r3, [r7, #4]
800734c: 681b ldr r3, [r3, #0]
800734e: 461a mov r2, r3
8007350: 69fb ldr r3, [r7, #28]
8007352: 61bb str r3, [r7, #24]
8007354: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007356: 6979 ldr r1, [r7, #20]
8007358: 69ba ldr r2, [r7, #24]
800735a: e841 2300 strex r3, r2, [r1]
800735e: 613b str r3, [r7, #16]
return(result);
8007360: 693b ldr r3, [r7, #16]
8007362: 2b00 cmp r3, #0
8007364: d1e6 bne.n 8007334 <UART_EndTransmit_IT+0x8>
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8007366: 687b ldr r3, [r7, #4]
8007368: 2220 movs r2, #32
800736a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
800736e: 687b ldr r3, [r7, #4]
8007370: 2200 movs r2, #0
8007372: 679a str r2, [r3, #120] @ 0x78
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8007374: 6878 ldr r0, [r7, #4]
8007376: f7f9 fe95 bl 80010a4 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800737a: bf00 nop
800737c: 3720 adds r7, #32
800737e: 46bd mov sp, r7
8007380: bd80 pop {r7, pc}
...
08007384 <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
8007384: b580 push {r7, lr}
8007386: b09c sub sp, #112 @ 0x70
8007388: af00 add r7, sp, #0
800738a: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
800738c: 687b ldr r3, [r7, #4]
800738e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007392: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007396: 687b ldr r3, [r7, #4]
8007398: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800739c: 2b22 cmp r3, #34 @ 0x22
800739e: f040 80be bne.w 800751e <UART_RxISR_8BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
80073a2: 687b ldr r3, [r7, #4]
80073a4: 681b ldr r3, [r3, #0]
80073a6: 6a5b ldr r3, [r3, #36] @ 0x24
80073a8: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
80073ac: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
80073b0: b2d9 uxtb r1, r3
80073b2: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
80073b6: b2da uxtb r2, r3
80073b8: 687b ldr r3, [r7, #4]
80073ba: 6d9b ldr r3, [r3, #88] @ 0x58
80073bc: 400a ands r2, r1
80073be: b2d2 uxtb r2, r2
80073c0: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
80073c2: 687b ldr r3, [r7, #4]
80073c4: 6d9b ldr r3, [r3, #88] @ 0x58
80073c6: 1c5a adds r2, r3, #1
80073c8: 687b ldr r3, [r7, #4]
80073ca: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
80073cc: 687b ldr r3, [r7, #4]
80073ce: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80073d2: b29b uxth r3, r3
80073d4: 3b01 subs r3, #1
80073d6: b29a uxth r2, r3
80073d8: 687b ldr r3, [r7, #4]
80073da: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
if (huart->RxXferCount == 0U)
80073de: 687b ldr r3, [r7, #4]
80073e0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80073e4: b29b uxth r3, r3
80073e6: 2b00 cmp r3, #0
80073e8: f040 80a1 bne.w 800752e <UART_RxISR_8BIT+0x1aa>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80073ec: 687b ldr r3, [r7, #4]
80073ee: 681b ldr r3, [r3, #0]
80073f0: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80073f2: 6cfb ldr r3, [r7, #76] @ 0x4c
80073f4: e853 3f00 ldrex r3, [r3]
80073f8: 64bb str r3, [r7, #72] @ 0x48
return(result);
80073fa: 6cbb ldr r3, [r7, #72] @ 0x48
80073fc: f423 7390 bic.w r3, r3, #288 @ 0x120
8007400: 66bb str r3, [r7, #104] @ 0x68
8007402: 687b ldr r3, [r7, #4]
8007404: 681b ldr r3, [r3, #0]
8007406: 461a mov r2, r3
8007408: 6ebb ldr r3, [r7, #104] @ 0x68
800740a: 65bb str r3, [r7, #88] @ 0x58
800740c: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800740e: 6d79 ldr r1, [r7, #84] @ 0x54
8007410: 6dba ldr r2, [r7, #88] @ 0x58
8007412: e841 2300 strex r3, r2, [r1]
8007416: 653b str r3, [r7, #80] @ 0x50
return(result);
8007418: 6d3b ldr r3, [r7, #80] @ 0x50
800741a: 2b00 cmp r3, #0
800741c: d1e6 bne.n 80073ec <UART_RxISR_8BIT+0x68>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800741e: 687b ldr r3, [r7, #4]
8007420: 681b ldr r3, [r3, #0]
8007422: 3308 adds r3, #8
8007424: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007426: 6bbb ldr r3, [r7, #56] @ 0x38
8007428: e853 3f00 ldrex r3, [r3]
800742c: 637b str r3, [r7, #52] @ 0x34
return(result);
800742e: 6b7b ldr r3, [r7, #52] @ 0x34
8007430: f023 0301 bic.w r3, r3, #1
8007434: 667b str r3, [r7, #100] @ 0x64
8007436: 687b ldr r3, [r7, #4]
8007438: 681b ldr r3, [r3, #0]
800743a: 3308 adds r3, #8
800743c: 6e7a ldr r2, [r7, #100] @ 0x64
800743e: 647a str r2, [r7, #68] @ 0x44
8007440: 643b str r3, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007442: 6c39 ldr r1, [r7, #64] @ 0x40
8007444: 6c7a ldr r2, [r7, #68] @ 0x44
8007446: e841 2300 strex r3, r2, [r1]
800744a: 63fb str r3, [r7, #60] @ 0x3c
return(result);
800744c: 6bfb ldr r3, [r7, #60] @ 0x3c
800744e: 2b00 cmp r3, #0
8007450: d1e5 bne.n 800741e <UART_RxISR_8BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007452: 687b ldr r3, [r7, #4]
8007454: 2220 movs r2, #32
8007456: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
800745a: 687b ldr r3, [r7, #4]
800745c: 2200 movs r2, #0
800745e: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007460: 687b ldr r3, [r7, #4]
8007462: 2200 movs r2, #0
8007464: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007466: 687b ldr r3, [r7, #4]
8007468: 681b ldr r3, [r3, #0]
800746a: 4a33 ldr r2, [pc, #204] @ (8007538 <UART_RxISR_8BIT+0x1b4>)
800746c: 4293 cmp r3, r2
800746e: d01f beq.n 80074b0 <UART_RxISR_8BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007470: 687b ldr r3, [r7, #4]
8007472: 681b ldr r3, [r3, #0]
8007474: 685b ldr r3, [r3, #4]
8007476: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800747a: 2b00 cmp r3, #0
800747c: d018 beq.n 80074b0 <UART_RxISR_8BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
800747e: 687b ldr r3, [r7, #4]
8007480: 681b ldr r3, [r3, #0]
8007482: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007484: 6a7b ldr r3, [r7, #36] @ 0x24
8007486: e853 3f00 ldrex r3, [r3]
800748a: 623b str r3, [r7, #32]
return(result);
800748c: 6a3b ldr r3, [r7, #32]
800748e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007492: 663b str r3, [r7, #96] @ 0x60
8007494: 687b ldr r3, [r7, #4]
8007496: 681b ldr r3, [r3, #0]
8007498: 461a mov r2, r3
800749a: 6e3b ldr r3, [r7, #96] @ 0x60
800749c: 633b str r3, [r7, #48] @ 0x30
800749e: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80074a0: 6af9 ldr r1, [r7, #44] @ 0x2c
80074a2: 6b3a ldr r2, [r7, #48] @ 0x30
80074a4: e841 2300 strex r3, r2, [r1]
80074a8: 62bb str r3, [r7, #40] @ 0x28
return(result);
80074aa: 6abb ldr r3, [r7, #40] @ 0x28
80074ac: 2b00 cmp r3, #0
80074ae: d1e6 bne.n 800747e <UART_RxISR_8BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80074b0: 687b ldr r3, [r7, #4]
80074b2: 6edb ldr r3, [r3, #108] @ 0x6c
80074b4: 2b01 cmp r3, #1
80074b6: d12e bne.n 8007516 <UART_RxISR_8BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80074b8: 687b ldr r3, [r7, #4]
80074ba: 2200 movs r2, #0
80074bc: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80074be: 687b ldr r3, [r7, #4]
80074c0: 681b ldr r3, [r3, #0]
80074c2: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80074c4: 693b ldr r3, [r7, #16]
80074c6: e853 3f00 ldrex r3, [r3]
80074ca: 60fb str r3, [r7, #12]
return(result);
80074cc: 68fb ldr r3, [r7, #12]
80074ce: f023 0310 bic.w r3, r3, #16
80074d2: 65fb str r3, [r7, #92] @ 0x5c
80074d4: 687b ldr r3, [r7, #4]
80074d6: 681b ldr r3, [r3, #0]
80074d8: 461a mov r2, r3
80074da: 6dfb ldr r3, [r7, #92] @ 0x5c
80074dc: 61fb str r3, [r7, #28]
80074de: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80074e0: 69b9 ldr r1, [r7, #24]
80074e2: 69fa ldr r2, [r7, #28]
80074e4: e841 2300 strex r3, r2, [r1]
80074e8: 617b str r3, [r7, #20]
return(result);
80074ea: 697b ldr r3, [r7, #20]
80074ec: 2b00 cmp r3, #0
80074ee: d1e6 bne.n 80074be <UART_RxISR_8BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
80074f0: 687b ldr r3, [r7, #4]
80074f2: 681b ldr r3, [r3, #0]
80074f4: 69db ldr r3, [r3, #28]
80074f6: f003 0310 and.w r3, r3, #16
80074fa: 2b10 cmp r3, #16
80074fc: d103 bne.n 8007506 <UART_RxISR_8BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
80074fe: 687b ldr r3, [r7, #4]
8007500: 681b ldr r3, [r3, #0]
8007502: 2210 movs r2, #16
8007504: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007506: 687b ldr r3, [r7, #4]
8007508: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
800750c: 4619 mov r1, r3
800750e: 6878 ldr r0, [r7, #4]
8007510: f7ff f8e0 bl 80066d4 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007514: e00b b.n 800752e <UART_RxISR_8BIT+0x1aa>
HAL_UART_RxCpltCallback(huart);
8007516: 6878 ldr r0, [r7, #4]
8007518: f7f9 fdce bl 80010b8 <HAL_UART_RxCpltCallback>
}
800751c: e007 b.n 800752e <UART_RxISR_8BIT+0x1aa>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
800751e: 687b ldr r3, [r7, #4]
8007520: 681b ldr r3, [r3, #0]
8007522: 699a ldr r2, [r3, #24]
8007524: 687b ldr r3, [r7, #4]
8007526: 681b ldr r3, [r3, #0]
8007528: f042 0208 orr.w r2, r2, #8
800752c: 619a str r2, [r3, #24]
}
800752e: bf00 nop
8007530: 3770 adds r7, #112 @ 0x70
8007532: 46bd mov sp, r7
8007534: bd80 pop {r7, pc}
8007536: bf00 nop
8007538: 40008000 .word 0x40008000
0800753c <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
800753c: b580 push {r7, lr}
800753e: b09c sub sp, #112 @ 0x70
8007540: af00 add r7, sp, #0
8007542: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8007544: 687b ldr r3, [r7, #4]
8007546: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
800754a: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
800754e: 687b ldr r3, [r7, #4]
8007550: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007554: 2b22 cmp r3, #34 @ 0x22
8007556: f040 80be bne.w 80076d6 <UART_RxISR_16BIT+0x19a>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
800755a: 687b ldr r3, [r7, #4]
800755c: 681b ldr r3, [r3, #0]
800755e: 6a5b ldr r3, [r3, #36] @ 0x24
8007560: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
tmp = (uint16_t *) huart->pRxBuffPtr ;
8007564: 687b ldr r3, [r7, #4]
8007566: 6d9b ldr r3, [r3, #88] @ 0x58
8007568: 66bb str r3, [r7, #104] @ 0x68
*tmp = (uint16_t)(uhdata & uhMask);
800756a: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
800756e: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
8007572: 4013 ands r3, r2
8007574: b29a uxth r2, r3
8007576: 6ebb ldr r3, [r7, #104] @ 0x68
8007578: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
800757a: 687b ldr r3, [r7, #4]
800757c: 6d9b ldr r3, [r3, #88] @ 0x58
800757e: 1c9a adds r2, r3, #2
8007580: 687b ldr r3, [r7, #4]
8007582: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007584: 687b ldr r3, [r7, #4]
8007586: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800758a: b29b uxth r3, r3
800758c: 3b01 subs r3, #1
800758e: b29a uxth r2, r3
8007590: 687b ldr r3, [r7, #4]
8007592: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
if (huart->RxXferCount == 0U)
8007596: 687b ldr r3, [r7, #4]
8007598: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800759c: b29b uxth r3, r3
800759e: 2b00 cmp r3, #0
80075a0: f040 80a1 bne.w 80076e6 <UART_RxISR_16BIT+0x1aa>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80075a4: 687b ldr r3, [r7, #4]
80075a6: 681b ldr r3, [r3, #0]
80075a8: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80075aa: 6cbb ldr r3, [r7, #72] @ 0x48
80075ac: e853 3f00 ldrex r3, [r3]
80075b0: 647b str r3, [r7, #68] @ 0x44
return(result);
80075b2: 6c7b ldr r3, [r7, #68] @ 0x44
80075b4: f423 7390 bic.w r3, r3, #288 @ 0x120
80075b8: 667b str r3, [r7, #100] @ 0x64
80075ba: 687b ldr r3, [r7, #4]
80075bc: 681b ldr r3, [r3, #0]
80075be: 461a mov r2, r3
80075c0: 6e7b ldr r3, [r7, #100] @ 0x64
80075c2: 657b str r3, [r7, #84] @ 0x54
80075c4: 653a str r2, [r7, #80] @ 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80075c6: 6d39 ldr r1, [r7, #80] @ 0x50
80075c8: 6d7a ldr r2, [r7, #84] @ 0x54
80075ca: e841 2300 strex r3, r2, [r1]
80075ce: 64fb str r3, [r7, #76] @ 0x4c
return(result);
80075d0: 6cfb ldr r3, [r7, #76] @ 0x4c
80075d2: 2b00 cmp r3, #0
80075d4: d1e6 bne.n 80075a4 <UART_RxISR_16BIT+0x68>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80075d6: 687b ldr r3, [r7, #4]
80075d8: 681b ldr r3, [r3, #0]
80075da: 3308 adds r3, #8
80075dc: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80075de: 6b7b ldr r3, [r7, #52] @ 0x34
80075e0: e853 3f00 ldrex r3, [r3]
80075e4: 633b str r3, [r7, #48] @ 0x30
return(result);
80075e6: 6b3b ldr r3, [r7, #48] @ 0x30
80075e8: f023 0301 bic.w r3, r3, #1
80075ec: 663b str r3, [r7, #96] @ 0x60
80075ee: 687b ldr r3, [r7, #4]
80075f0: 681b ldr r3, [r3, #0]
80075f2: 3308 adds r3, #8
80075f4: 6e3a ldr r2, [r7, #96] @ 0x60
80075f6: 643a str r2, [r7, #64] @ 0x40
80075f8: 63fb str r3, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80075fa: 6bf9 ldr r1, [r7, #60] @ 0x3c
80075fc: 6c3a ldr r2, [r7, #64] @ 0x40
80075fe: e841 2300 strex r3, r2, [r1]
8007602: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007604: 6bbb ldr r3, [r7, #56] @ 0x38
8007606: 2b00 cmp r3, #0
8007608: d1e5 bne.n 80075d6 <UART_RxISR_16BIT+0x9a>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800760a: 687b ldr r3, [r7, #4]
800760c: 2220 movs r2, #32
800760e: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007612: 687b ldr r3, [r7, #4]
8007614: 2200 movs r2, #0
8007616: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007618: 687b ldr r3, [r7, #4]
800761a: 2200 movs r2, #0
800761c: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
800761e: 687b ldr r3, [r7, #4]
8007620: 681b ldr r3, [r3, #0]
8007622: 4a33 ldr r2, [pc, #204] @ (80076f0 <UART_RxISR_16BIT+0x1b4>)
8007624: 4293 cmp r3, r2
8007626: d01f beq.n 8007668 <UART_RxISR_16BIT+0x12c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007628: 687b ldr r3, [r7, #4]
800762a: 681b ldr r3, [r3, #0]
800762c: 685b ldr r3, [r3, #4]
800762e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007632: 2b00 cmp r3, #0
8007634: d018 beq.n 8007668 <UART_RxISR_16BIT+0x12c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007636: 687b ldr r3, [r7, #4]
8007638: 681b ldr r3, [r3, #0]
800763a: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800763c: 6a3b ldr r3, [r7, #32]
800763e: e853 3f00 ldrex r3, [r3]
8007642: 61fb str r3, [r7, #28]
return(result);
8007644: 69fb ldr r3, [r7, #28]
8007646: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
800764a: 65fb str r3, [r7, #92] @ 0x5c
800764c: 687b ldr r3, [r7, #4]
800764e: 681b ldr r3, [r3, #0]
8007650: 461a mov r2, r3
8007652: 6dfb ldr r3, [r7, #92] @ 0x5c
8007654: 62fb str r3, [r7, #44] @ 0x2c
8007656: 62ba str r2, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007658: 6ab9 ldr r1, [r7, #40] @ 0x28
800765a: 6afa ldr r2, [r7, #44] @ 0x2c
800765c: e841 2300 strex r3, r2, [r1]
8007660: 627b str r3, [r7, #36] @ 0x24
return(result);
8007662: 6a7b ldr r3, [r7, #36] @ 0x24
8007664: 2b00 cmp r3, #0
8007666: d1e6 bne.n 8007636 <UART_RxISR_16BIT+0xfa>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007668: 687b ldr r3, [r7, #4]
800766a: 6edb ldr r3, [r3, #108] @ 0x6c
800766c: 2b01 cmp r3, #1
800766e: d12e bne.n 80076ce <UART_RxISR_16BIT+0x192>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007670: 687b ldr r3, [r7, #4]
8007672: 2200 movs r2, #0
8007674: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007676: 687b ldr r3, [r7, #4]
8007678: 681b ldr r3, [r3, #0]
800767a: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800767c: 68fb ldr r3, [r7, #12]
800767e: e853 3f00 ldrex r3, [r3]
8007682: 60bb str r3, [r7, #8]
return(result);
8007684: 68bb ldr r3, [r7, #8]
8007686: f023 0310 bic.w r3, r3, #16
800768a: 65bb str r3, [r7, #88] @ 0x58
800768c: 687b ldr r3, [r7, #4]
800768e: 681b ldr r3, [r3, #0]
8007690: 461a mov r2, r3
8007692: 6dbb ldr r3, [r7, #88] @ 0x58
8007694: 61bb str r3, [r7, #24]
8007696: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007698: 6979 ldr r1, [r7, #20]
800769a: 69ba ldr r2, [r7, #24]
800769c: e841 2300 strex r3, r2, [r1]
80076a0: 613b str r3, [r7, #16]
return(result);
80076a2: 693b ldr r3, [r7, #16]
80076a4: 2b00 cmp r3, #0
80076a6: d1e6 bne.n 8007676 <UART_RxISR_16BIT+0x13a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
80076a8: 687b ldr r3, [r7, #4]
80076aa: 681b ldr r3, [r3, #0]
80076ac: 69db ldr r3, [r3, #28]
80076ae: f003 0310 and.w r3, r3, #16
80076b2: 2b10 cmp r3, #16
80076b4: d103 bne.n 80076be <UART_RxISR_16BIT+0x182>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
80076b6: 687b ldr r3, [r7, #4]
80076b8: 681b ldr r3, [r3, #0]
80076ba: 2210 movs r2, #16
80076bc: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80076be: 687b ldr r3, [r7, #4]
80076c0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
80076c4: 4619 mov r1, r3
80076c6: 6878 ldr r0, [r7, #4]
80076c8: f7ff f804 bl 80066d4 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
80076cc: e00b b.n 80076e6 <UART_RxISR_16BIT+0x1aa>
HAL_UART_RxCpltCallback(huart);
80076ce: 6878 ldr r0, [r7, #4]
80076d0: f7f9 fcf2 bl 80010b8 <HAL_UART_RxCpltCallback>
}
80076d4: e007 b.n 80076e6 <UART_RxISR_16BIT+0x1aa>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
80076d6: 687b ldr r3, [r7, #4]
80076d8: 681b ldr r3, [r3, #0]
80076da: 699a ldr r2, [r3, #24]
80076dc: 687b ldr r3, [r7, #4]
80076de: 681b ldr r3, [r3, #0]
80076e0: f042 0208 orr.w r2, r2, #8
80076e4: 619a str r2, [r3, #24]
}
80076e6: bf00 nop
80076e8: 3770 adds r7, #112 @ 0x70
80076ea: 46bd mov sp, r7
80076ec: bd80 pop {r7, pc}
80076ee: bf00 nop
80076f0: 40008000 .word 0x40008000
080076f4 <UART_RxISR_8BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
80076f4: b580 push {r7, lr}
80076f6: b0ac sub sp, #176 @ 0xb0
80076f8: af00 add r7, sp, #0
80076fa: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
80076fc: 687b ldr r3, [r7, #4]
80076fe: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007702: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8007706: 687b ldr r3, [r7, #4]
8007708: 681b ldr r3, [r3, #0]
800770a: 69db ldr r3, [r3, #28]
800770c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8007710: 687b ldr r3, [r7, #4]
8007712: 681b ldr r3, [r3, #0]
8007714: 681b ldr r3, [r3, #0]
8007716: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
uint32_t cr3its = READ_REG(huart->Instance->CR3);
800771a: 687b ldr r3, [r7, #4]
800771c: 681b ldr r3, [r3, #0]
800771e: 689b ldr r3, [r3, #8]
8007720: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007724: 687b ldr r3, [r7, #4]
8007726: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
800772a: 2b22 cmp r3, #34 @ 0x22
800772c: f040 8183 bne.w 8007a36 <UART_RxISR_8BIT_FIFOEN+0x342>
{
nb_rx_data = huart->NbRxDataToProcess;
8007730: 687b ldr r3, [r7, #4]
8007732: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007736: f8a7 309e strh.w r3, [r7, #158] @ 0x9e
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
800773a: e126 b.n 800798a <UART_RxISR_8BIT_FIFOEN+0x296>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
800773c: 687b ldr r3, [r7, #4]
800773e: 681b ldr r3, [r3, #0]
8007740: 6a5b ldr r3, [r3, #36] @ 0x24
8007742: f8a7 309c strh.w r3, [r7, #156] @ 0x9c
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8007746: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c
800774a: b2d9 uxtb r1, r3
800774c: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa
8007750: b2da uxtb r2, r3
8007752: 687b ldr r3, [r7, #4]
8007754: 6d9b ldr r3, [r3, #88] @ 0x58
8007756: 400a ands r2, r1
8007758: b2d2 uxtb r2, r2
800775a: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
800775c: 687b ldr r3, [r7, #4]
800775e: 6d9b ldr r3, [r3, #88] @ 0x58
8007760: 1c5a adds r2, r3, #1
8007762: 687b ldr r3, [r7, #4]
8007764: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007766: 687b ldr r3, [r7, #4]
8007768: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800776c: b29b uxth r3, r3
800776e: 3b01 subs r3, #1
8007770: b29a uxth r2, r3
8007772: 687b ldr r3, [r7, #4]
8007774: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
isrflags = READ_REG(huart->Instance->ISR);
8007778: 687b ldr r3, [r7, #4]
800777a: 681b ldr r3, [r3, #0]
800777c: 69db ldr r3, [r3, #28]
800777e: f8c7 30ac str.w r3, [r7, #172] @ 0xac
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
8007782: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007786: f003 0307 and.w r3, r3, #7
800778a: 2b00 cmp r3, #0
800778c: d053 beq.n 8007836 <UART_RxISR_8BIT_FIFOEN+0x142>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
800778e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007792: f003 0301 and.w r3, r3, #1
8007796: 2b00 cmp r3, #0
8007798: d011 beq.n 80077be <UART_RxISR_8BIT_FIFOEN+0xca>
800779a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
800779e: f403 7380 and.w r3, r3, #256 @ 0x100
80077a2: 2b00 cmp r3, #0
80077a4: d00b beq.n 80077be <UART_RxISR_8BIT_FIFOEN+0xca>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
80077a6: 687b ldr r3, [r7, #4]
80077a8: 681b ldr r3, [r3, #0]
80077aa: 2201 movs r2, #1
80077ac: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
80077ae: 687b ldr r3, [r7, #4]
80077b0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80077b4: f043 0201 orr.w r2, r3, #1
80077b8: 687b ldr r3, [r7, #4]
80077ba: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80077be: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80077c2: f003 0302 and.w r3, r3, #2
80077c6: 2b00 cmp r3, #0
80077c8: d011 beq.n 80077ee <UART_RxISR_8BIT_FIFOEN+0xfa>
80077ca: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
80077ce: f003 0301 and.w r3, r3, #1
80077d2: 2b00 cmp r3, #0
80077d4: d00b beq.n 80077ee <UART_RxISR_8BIT_FIFOEN+0xfa>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
80077d6: 687b ldr r3, [r7, #4]
80077d8: 681b ldr r3, [r3, #0]
80077da: 2202 movs r2, #2
80077dc: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
80077de: 687b ldr r3, [r7, #4]
80077e0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80077e4: f043 0204 orr.w r2, r3, #4
80077e8: 687b ldr r3, [r7, #4]
80077ea: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80077ee: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
80077f2: f003 0304 and.w r3, r3, #4
80077f6: 2b00 cmp r3, #0
80077f8: d011 beq.n 800781e <UART_RxISR_8BIT_FIFOEN+0x12a>
80077fa: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
80077fe: f003 0301 and.w r3, r3, #1
8007802: 2b00 cmp r3, #0
8007804: d00b beq.n 800781e <UART_RxISR_8BIT_FIFOEN+0x12a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8007806: 687b ldr r3, [r7, #4]
8007808: 681b ldr r3, [r3, #0]
800780a: 2204 movs r2, #4
800780c: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
800780e: 687b ldr r3, [r7, #4]
8007810: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007814: f043 0202 orr.w r2, r3, #2
8007818: 687b ldr r3, [r7, #4]
800781a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800781e: 687b ldr r3, [r7, #4]
8007820: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007824: 2b00 cmp r3, #0
8007826: d006 beq.n 8007836 <UART_RxISR_8BIT_FIFOEN+0x142>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8007828: 6878 ldr r0, [r7, #4]
800782a: f7fe ff49 bl 80066c0 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800782e: 687b ldr r3, [r7, #4]
8007830: 2200 movs r2, #0
8007832: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
if (huart->RxXferCount == 0U)
8007836: 687b ldr r3, [r7, #4]
8007838: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
800783c: b29b uxth r3, r3
800783e: 2b00 cmp r3, #0
8007840: f040 80a3 bne.w 800798a <UART_RxISR_8BIT_FIFOEN+0x296>
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8007844: 687b ldr r3, [r7, #4]
8007846: 681b ldr r3, [r3, #0]
8007848: 673b str r3, [r7, #112] @ 0x70
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800784a: 6f3b ldr r3, [r7, #112] @ 0x70
800784c: e853 3f00 ldrex r3, [r3]
8007850: 66fb str r3, [r7, #108] @ 0x6c
return(result);
8007852: 6efb ldr r3, [r7, #108] @ 0x6c
8007854: f423 7380 bic.w r3, r3, #256 @ 0x100
8007858: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800785c: 687b ldr r3, [r7, #4]
800785e: 681b ldr r3, [r3, #0]
8007860: 461a mov r2, r3
8007862: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8007866: 67fb str r3, [r7, #124] @ 0x7c
8007868: 67ba str r2, [r7, #120] @ 0x78
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800786a: 6fb9 ldr r1, [r7, #120] @ 0x78
800786c: 6ffa ldr r2, [r7, #124] @ 0x7c
800786e: e841 2300 strex r3, r2, [r1]
8007872: 677b str r3, [r7, #116] @ 0x74
return(result);
8007874: 6f7b ldr r3, [r7, #116] @ 0x74
8007876: 2b00 cmp r3, #0
8007878: d1e4 bne.n 8007844 <UART_RxISR_8BIT_FIFOEN+0x150>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
800787a: 687b ldr r3, [r7, #4]
800787c: 681b ldr r3, [r3, #0]
800787e: 3308 adds r3, #8
8007880: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007882: 6dfb ldr r3, [r7, #92] @ 0x5c
8007884: e853 3f00 ldrex r3, [r3]
8007888: 65bb str r3, [r7, #88] @ 0x58
return(result);
800788a: 6dbb ldr r3, [r7, #88] @ 0x58
800788c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007890: f023 0301 bic.w r3, r3, #1
8007894: f8c7 3094 str.w r3, [r7, #148] @ 0x94
8007898: 687b ldr r3, [r7, #4]
800789a: 681b ldr r3, [r3, #0]
800789c: 3308 adds r3, #8
800789e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
80078a2: 66ba str r2, [r7, #104] @ 0x68
80078a4: 667b str r3, [r7, #100] @ 0x64
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80078a6: 6e79 ldr r1, [r7, #100] @ 0x64
80078a8: 6eba ldr r2, [r7, #104] @ 0x68
80078aa: e841 2300 strex r3, r2, [r1]
80078ae: 663b str r3, [r7, #96] @ 0x60
return(result);
80078b0: 6e3b ldr r3, [r7, #96] @ 0x60
80078b2: 2b00 cmp r3, #0
80078b4: d1e1 bne.n 800787a <UART_RxISR_8BIT_FIFOEN+0x186>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80078b6: 687b ldr r3, [r7, #4]
80078b8: 2220 movs r2, #32
80078ba: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
80078be: 687b ldr r3, [r7, #4]
80078c0: 2200 movs r2, #0
80078c2: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
80078c4: 687b ldr r3, [r7, #4]
80078c6: 2200 movs r2, #0
80078c8: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
80078ca: 687b ldr r3, [r7, #4]
80078cc: 681b ldr r3, [r3, #0]
80078ce: 4a60 ldr r2, [pc, #384] @ (8007a50 <UART_RxISR_8BIT_FIFOEN+0x35c>)
80078d0: 4293 cmp r3, r2
80078d2: d021 beq.n 8007918 <UART_RxISR_8BIT_FIFOEN+0x224>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
80078d4: 687b ldr r3, [r7, #4]
80078d6: 681b ldr r3, [r3, #0]
80078d8: 685b ldr r3, [r3, #4]
80078da: f403 0300 and.w r3, r3, #8388608 @ 0x800000
80078de: 2b00 cmp r3, #0
80078e0: d01a beq.n 8007918 <UART_RxISR_8BIT_FIFOEN+0x224>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
80078e2: 687b ldr r3, [r7, #4]
80078e4: 681b ldr r3, [r3, #0]
80078e6: 64bb str r3, [r7, #72] @ 0x48
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80078e8: 6cbb ldr r3, [r7, #72] @ 0x48
80078ea: e853 3f00 ldrex r3, [r3]
80078ee: 647b str r3, [r7, #68] @ 0x44
return(result);
80078f0: 6c7b ldr r3, [r7, #68] @ 0x44
80078f2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
80078f6: f8c7 3090 str.w r3, [r7, #144] @ 0x90
80078fa: 687b ldr r3, [r7, #4]
80078fc: 681b ldr r3, [r3, #0]
80078fe: 461a mov r2, r3
8007900: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8007904: 657b str r3, [r7, #84] @ 0x54
8007906: 653a str r2, [r7, #80] @ 0x50
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007908: 6d39 ldr r1, [r7, #80] @ 0x50
800790a: 6d7a ldr r2, [r7, #84] @ 0x54
800790c: e841 2300 strex r3, r2, [r1]
8007910: 64fb str r3, [r7, #76] @ 0x4c
return(result);
8007912: 6cfb ldr r3, [r7, #76] @ 0x4c
8007914: 2b00 cmp r3, #0
8007916: d1e4 bne.n 80078e2 <UART_RxISR_8BIT_FIFOEN+0x1ee>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007918: 687b ldr r3, [r7, #4]
800791a: 6edb ldr r3, [r3, #108] @ 0x6c
800791c: 2b01 cmp r3, #1
800791e: d130 bne.n 8007982 <UART_RxISR_8BIT_FIFOEN+0x28e>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007920: 687b ldr r3, [r7, #4]
8007922: 2200 movs r2, #0
8007924: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007926: 687b ldr r3, [r7, #4]
8007928: 681b ldr r3, [r3, #0]
800792a: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800792c: 6b7b ldr r3, [r7, #52] @ 0x34
800792e: e853 3f00 ldrex r3, [r3]
8007932: 633b str r3, [r7, #48] @ 0x30
return(result);
8007934: 6b3b ldr r3, [r7, #48] @ 0x30
8007936: f023 0310 bic.w r3, r3, #16
800793a: f8c7 308c str.w r3, [r7, #140] @ 0x8c
800793e: 687b ldr r3, [r7, #4]
8007940: 681b ldr r3, [r3, #0]
8007942: 461a mov r2, r3
8007944: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
8007948: 643b str r3, [r7, #64] @ 0x40
800794a: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800794c: 6bf9 ldr r1, [r7, #60] @ 0x3c
800794e: 6c3a ldr r2, [r7, #64] @ 0x40
8007950: e841 2300 strex r3, r2, [r1]
8007954: 63bb str r3, [r7, #56] @ 0x38
return(result);
8007956: 6bbb ldr r3, [r7, #56] @ 0x38
8007958: 2b00 cmp r3, #0
800795a: d1e4 bne.n 8007926 <UART_RxISR_8BIT_FIFOEN+0x232>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
800795c: 687b ldr r3, [r7, #4]
800795e: 681b ldr r3, [r3, #0]
8007960: 69db ldr r3, [r3, #28]
8007962: f003 0310 and.w r3, r3, #16
8007966: 2b10 cmp r3, #16
8007968: d103 bne.n 8007972 <UART_RxISR_8BIT_FIFOEN+0x27e>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800796a: 687b ldr r3, [r7, #4]
800796c: 681b ldr r3, [r3, #0]
800796e: 2210 movs r2, #16
8007970: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007972: 687b ldr r3, [r7, #4]
8007974: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007978: 4619 mov r1, r3
800797a: 6878 ldr r0, [r7, #4]
800797c: f7fe feaa bl 80066d4 <HAL_UARTEx_RxEventCallback>
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
break;
8007980: e00e b.n 80079a0 <UART_RxISR_8BIT_FIFOEN+0x2ac>
HAL_UART_RxCpltCallback(huart);
8007982: 6878 ldr r0, [r7, #4]
8007984: f7f9 fb98 bl 80010b8 <HAL_UART_RxCpltCallback>
break;
8007988: e00a b.n 80079a0 <UART_RxISR_8BIT_FIFOEN+0x2ac>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
800798a: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e
800798e: 2b00 cmp r3, #0
8007990: d006 beq.n 80079a0 <UART_RxISR_8BIT_FIFOEN+0x2ac>
8007992: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007996: f003 0320 and.w r3, r3, #32
800799a: 2b00 cmp r3, #0
800799c: f47f aece bne.w 800773c <UART_RxISR_8BIT_FIFOEN+0x48>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
80079a0: 687b ldr r3, [r7, #4]
80079a2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
80079a6: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
80079aa: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
80079ae: 2b00 cmp r3, #0
80079b0: d049 beq.n 8007a46 <UART_RxISR_8BIT_FIFOEN+0x352>
80079b2: 687b ldr r3, [r7, #4]
80079b4: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
80079b8: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a
80079bc: 429a cmp r2, r3
80079be: d242 bcs.n 8007a46 <UART_RxISR_8BIT_FIFOEN+0x352>
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80079c0: 687b ldr r3, [r7, #4]
80079c2: 681b ldr r3, [r3, #0]
80079c4: 3308 adds r3, #8
80079c6: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80079c8: 6a3b ldr r3, [r7, #32]
80079ca: e853 3f00 ldrex r3, [r3]
80079ce: 61fb str r3, [r7, #28]
return(result);
80079d0: 69fb ldr r3, [r7, #28]
80079d2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80079d6: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80079da: 687b ldr r3, [r7, #4]
80079dc: 681b ldr r3, [r3, #0]
80079de: 3308 adds r3, #8
80079e0: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
80079e4: 62fa str r2, [r7, #44] @ 0x2c
80079e6: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80079e8: 6ab9 ldr r1, [r7, #40] @ 0x28
80079ea: 6afa ldr r2, [r7, #44] @ 0x2c
80079ec: e841 2300 strex r3, r2, [r1]
80079f0: 627b str r3, [r7, #36] @ 0x24
return(result);
80079f2: 6a7b ldr r3, [r7, #36] @ 0x24
80079f4: 2b00 cmp r3, #0
80079f6: d1e3 bne.n 80079c0 <UART_RxISR_8BIT_FIFOEN+0x2cc>
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
80079f8: 687b ldr r3, [r7, #4]
80079fa: 4a16 ldr r2, [pc, #88] @ (8007a54 <UART_RxISR_8BIT_FIFOEN+0x360>)
80079fc: 675a str r2, [r3, #116] @ 0x74
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
80079fe: 687b ldr r3, [r7, #4]
8007a00: 681b ldr r3, [r3, #0]
8007a02: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007a04: 68fb ldr r3, [r7, #12]
8007a06: e853 3f00 ldrex r3, [r3]
8007a0a: 60bb str r3, [r7, #8]
return(result);
8007a0c: 68bb ldr r3, [r7, #8]
8007a0e: f043 0320 orr.w r3, r3, #32
8007a12: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8007a16: 687b ldr r3, [r7, #4]
8007a18: 681b ldr r3, [r3, #0]
8007a1a: 461a mov r2, r3
8007a1c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
8007a20: 61bb str r3, [r7, #24]
8007a22: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007a24: 6979 ldr r1, [r7, #20]
8007a26: 69ba ldr r2, [r7, #24]
8007a28: e841 2300 strex r3, r2, [r1]
8007a2c: 613b str r3, [r7, #16]
return(result);
8007a2e: 693b ldr r3, [r7, #16]
8007a30: 2b00 cmp r3, #0
8007a32: d1e4 bne.n 80079fe <UART_RxISR_8BIT_FIFOEN+0x30a>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007a34: e007 b.n 8007a46 <UART_RxISR_8BIT_FIFOEN+0x352>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007a36: 687b ldr r3, [r7, #4]
8007a38: 681b ldr r3, [r3, #0]
8007a3a: 699a ldr r2, [r3, #24]
8007a3c: 687b ldr r3, [r7, #4]
8007a3e: 681b ldr r3, [r3, #0]
8007a40: f042 0208 orr.w r2, r2, #8
8007a44: 619a str r2, [r3, #24]
}
8007a46: bf00 nop
8007a48: 37b0 adds r7, #176 @ 0xb0
8007a4a: 46bd mov sp, r7
8007a4c: bd80 pop {r7, pc}
8007a4e: bf00 nop
8007a50: 40008000 .word 0x40008000
8007a54: 08007385 .word 0x08007385
08007a58 <UART_RxISR_16BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8007a58: b580 push {r7, lr}
8007a5a: b0ae sub sp, #184 @ 0xb8
8007a5c: af00 add r7, sp, #0
8007a5e: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8007a60: 687b ldr r3, [r7, #4]
8007a62: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
8007a66: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8007a6a: 687b ldr r3, [r7, #4]
8007a6c: 681b ldr r3, [r3, #0]
8007a6e: 69db ldr r3, [r3, #28]
8007a70: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8007a74: 687b ldr r3, [r7, #4]
8007a76: 681b ldr r3, [r3, #0]
8007a78: 681b ldr r3, [r3, #0]
8007a7a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8007a7e: 687b ldr r3, [r7, #4]
8007a80: 681b ldr r3, [r3, #0]
8007a82: 689b ldr r3, [r3, #8]
8007a84: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007a88: 687b ldr r3, [r7, #4]
8007a8a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8007a8e: 2b22 cmp r3, #34 @ 0x22
8007a90: f040 8187 bne.w 8007da2 <UART_RxISR_16BIT_FIFOEN+0x34a>
{
nb_rx_data = huart->NbRxDataToProcess;
8007a94: 687b ldr r3, [r7, #4]
8007a96: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007a9a: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007a9e: e12a b.n 8007cf6 <UART_RxISR_16BIT_FIFOEN+0x29e>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007aa0: 687b ldr r3, [r7, #4]
8007aa2: 681b ldr r3, [r3, #0]
8007aa4: 6a5b ldr r3, [r3, #36] @ 0x24
8007aa6: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4
tmp = (uint16_t *) huart->pRxBuffPtr ;
8007aaa: 687b ldr r3, [r7, #4]
8007aac: 6d9b ldr r3, [r3, #88] @ 0x58
8007aae: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
*tmp = (uint16_t)(uhdata & uhMask);
8007ab2: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4
8007ab6: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2
8007aba: 4013 ands r3, r2
8007abc: b29a uxth r2, r3
8007abe: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8007ac2: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8007ac4: 687b ldr r3, [r7, #4]
8007ac6: 6d9b ldr r3, [r3, #88] @ 0x58
8007ac8: 1c9a adds r2, r3, #2
8007aca: 687b ldr r3, [r7, #4]
8007acc: 659a str r2, [r3, #88] @ 0x58
huart->RxXferCount--;
8007ace: 687b ldr r3, [r7, #4]
8007ad0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007ad4: b29b uxth r3, r3
8007ad6: 3b01 subs r3, #1
8007ad8: b29a uxth r2, r3
8007ada: 687b ldr r3, [r7, #4]
8007adc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
isrflags = READ_REG(huart->Instance->ISR);
8007ae0: 687b ldr r3, [r7, #4]
8007ae2: 681b ldr r3, [r3, #0]
8007ae4: 69db ldr r3, [r3, #28]
8007ae6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
8007aea: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8007aee: f003 0307 and.w r3, r3, #7
8007af2: 2b00 cmp r3, #0
8007af4: d053 beq.n 8007b9e <UART_RxISR_16BIT_FIFOEN+0x146>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8007af6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8007afa: f003 0301 and.w r3, r3, #1
8007afe: 2b00 cmp r3, #0
8007b00: d011 beq.n 8007b26 <UART_RxISR_16BIT_FIFOEN+0xce>
8007b02: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8007b06: f403 7380 and.w r3, r3, #256 @ 0x100
8007b0a: 2b00 cmp r3, #0
8007b0c: d00b beq.n 8007b26 <UART_RxISR_16BIT_FIFOEN+0xce>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8007b0e: 687b ldr r3, [r7, #4]
8007b10: 681b ldr r3, [r3, #0]
8007b12: 2201 movs r2, #1
8007b14: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8007b16: 687b ldr r3, [r7, #4]
8007b18: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007b1c: f043 0201 orr.w r2, r3, #1
8007b20: 687b ldr r3, [r7, #4]
8007b22: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007b26: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8007b2a: f003 0302 and.w r3, r3, #2
8007b2e: 2b00 cmp r3, #0
8007b30: d011 beq.n 8007b56 <UART_RxISR_16BIT_FIFOEN+0xfe>
8007b32: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8007b36: f003 0301 and.w r3, r3, #1
8007b3a: 2b00 cmp r3, #0
8007b3c: d00b beq.n 8007b56 <UART_RxISR_16BIT_FIFOEN+0xfe>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8007b3e: 687b ldr r3, [r7, #4]
8007b40: 681b ldr r3, [r3, #0]
8007b42: 2202 movs r2, #2
8007b44: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8007b46: 687b ldr r3, [r7, #4]
8007b48: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007b4c: f043 0204 orr.w r2, r3, #4
8007b50: 687b ldr r3, [r7, #4]
8007b52: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007b56: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8007b5a: f003 0304 and.w r3, r3, #4
8007b5e: 2b00 cmp r3, #0
8007b60: d011 beq.n 8007b86 <UART_RxISR_16BIT_FIFOEN+0x12e>
8007b62: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8007b66: f003 0301 and.w r3, r3, #1
8007b6a: 2b00 cmp r3, #0
8007b6c: d00b beq.n 8007b86 <UART_RxISR_16BIT_FIFOEN+0x12e>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8007b6e: 687b ldr r3, [r7, #4]
8007b70: 681b ldr r3, [r3, #0]
8007b72: 2204 movs r2, #4
8007b74: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8007b76: 687b ldr r3, [r7, #4]
8007b78: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007b7c: f043 0202 orr.w r2, r3, #2
8007b80: 687b ldr r3, [r7, #4]
8007b82: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8007b86: 687b ldr r3, [r7, #4]
8007b88: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007b8c: 2b00 cmp r3, #0
8007b8e: d006 beq.n 8007b9e <UART_RxISR_16BIT_FIFOEN+0x146>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8007b90: 6878 ldr r0, [r7, #4]
8007b92: f7fe fd95 bl 80066c0 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007b96: 687b ldr r3, [r7, #4]
8007b98: 2200 movs r2, #0
8007b9a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
}
}
if (huart->RxXferCount == 0U)
8007b9e: 687b ldr r3, [r7, #4]
8007ba0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007ba4: b29b uxth r3, r3
8007ba6: 2b00 cmp r3, #0
8007ba8: f040 80a5 bne.w 8007cf6 <UART_RxISR_16BIT_FIFOEN+0x29e>
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8007bac: 687b ldr r3, [r7, #4]
8007bae: 681b ldr r3, [r3, #0]
8007bb0: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007bb2: 6f7b ldr r3, [r7, #116] @ 0x74
8007bb4: e853 3f00 ldrex r3, [r3]
8007bb8: 673b str r3, [r7, #112] @ 0x70
return(result);
8007bba: 6f3b ldr r3, [r7, #112] @ 0x70
8007bbc: f423 7380 bic.w r3, r3, #256 @ 0x100
8007bc0: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8007bc4: 687b ldr r3, [r7, #4]
8007bc6: 681b ldr r3, [r3, #0]
8007bc8: 461a mov r2, r3
8007bca: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8007bce: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8007bd2: 67fa str r2, [r7, #124] @ 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007bd4: 6ff9 ldr r1, [r7, #124] @ 0x7c
8007bd6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
8007bda: e841 2300 strex r3, r2, [r1]
8007bde: 67bb str r3, [r7, #120] @ 0x78
return(result);
8007be0: 6fbb ldr r3, [r7, #120] @ 0x78
8007be2: 2b00 cmp r3, #0
8007be4: d1e2 bne.n 8007bac <UART_RxISR_16BIT_FIFOEN+0x154>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8007be6: 687b ldr r3, [r7, #4]
8007be8: 681b ldr r3, [r3, #0]
8007bea: 3308 adds r3, #8
8007bec: 663b str r3, [r7, #96] @ 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007bee: 6e3b ldr r3, [r7, #96] @ 0x60
8007bf0: e853 3f00 ldrex r3, [r3]
8007bf4: 65fb str r3, [r7, #92] @ 0x5c
return(result);
8007bf6: 6dfb ldr r3, [r7, #92] @ 0x5c
8007bf8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007bfc: f023 0301 bic.w r3, r3, #1
8007c00: f8c7 3098 str.w r3, [r7, #152] @ 0x98
8007c04: 687b ldr r3, [r7, #4]
8007c06: 681b ldr r3, [r3, #0]
8007c08: 3308 adds r3, #8
8007c0a: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98
8007c0e: 66fa str r2, [r7, #108] @ 0x6c
8007c10: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007c12: 6eb9 ldr r1, [r7, #104] @ 0x68
8007c14: 6efa ldr r2, [r7, #108] @ 0x6c
8007c16: e841 2300 strex r3, r2, [r1]
8007c1a: 667b str r3, [r7, #100] @ 0x64
return(result);
8007c1c: 6e7b ldr r3, [r7, #100] @ 0x64
8007c1e: 2b00 cmp r3, #0
8007c20: d1e1 bne.n 8007be6 <UART_RxISR_16BIT_FIFOEN+0x18e>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8007c22: 687b ldr r3, [r7, #4]
8007c24: 2220 movs r2, #32
8007c26: f8c3 208c str.w r2, [r3, #140] @ 0x8c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007c2a: 687b ldr r3, [r7, #4]
8007c2c: 2200 movs r2, #0
8007c2e: 675a str r2, [r3, #116] @ 0x74
/* Initialize type of RxEvent to Transfer Complete */
huart->RxEventType = HAL_UART_RXEVENT_TC;
8007c30: 687b ldr r3, [r7, #4]
8007c32: 2200 movs r2, #0
8007c34: 671a str r2, [r3, #112] @ 0x70
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8007c36: 687b ldr r3, [r7, #4]
8007c38: 681b ldr r3, [r3, #0]
8007c3a: 4a60 ldr r2, [pc, #384] @ (8007dbc <UART_RxISR_16BIT_FIFOEN+0x364>)
8007c3c: 4293 cmp r3, r2
8007c3e: d021 beq.n 8007c84 <UART_RxISR_16BIT_FIFOEN+0x22c>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
8007c40: 687b ldr r3, [r7, #4]
8007c42: 681b ldr r3, [r3, #0]
8007c44: 685b ldr r3, [r3, #4]
8007c46: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007c4a: 2b00 cmp r3, #0
8007c4c: d01a beq.n 8007c84 <UART_RxISR_16BIT_FIFOEN+0x22c>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8007c4e: 687b ldr r3, [r7, #4]
8007c50: 681b ldr r3, [r3, #0]
8007c52: 64fb str r3, [r7, #76] @ 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007c54: 6cfb ldr r3, [r7, #76] @ 0x4c
8007c56: e853 3f00 ldrex r3, [r3]
8007c5a: 64bb str r3, [r7, #72] @ 0x48
return(result);
8007c5c: 6cbb ldr r3, [r7, #72] @ 0x48
8007c5e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8007c62: f8c7 3094 str.w r3, [r7, #148] @ 0x94
8007c66: 687b ldr r3, [r7, #4]
8007c68: 681b ldr r3, [r3, #0]
8007c6a: 461a mov r2, r3
8007c6c: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
8007c70: 65bb str r3, [r7, #88] @ 0x58
8007c72: 657a str r2, [r7, #84] @ 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007c74: 6d79 ldr r1, [r7, #84] @ 0x54
8007c76: 6dba ldr r2, [r7, #88] @ 0x58
8007c78: e841 2300 strex r3, r2, [r1]
8007c7c: 653b str r3, [r7, #80] @ 0x50
return(result);
8007c7e: 6d3b ldr r3, [r7, #80] @ 0x50
8007c80: 2b00 cmp r3, #0
8007c82: d1e4 bne.n 8007c4e <UART_RxISR_16BIT_FIFOEN+0x1f6>
}
}
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8007c84: 687b ldr r3, [r7, #4]
8007c86: 6edb ldr r3, [r3, #108] @ 0x6c
8007c88: 2b01 cmp r3, #1
8007c8a: d130 bne.n 8007cee <UART_RxISR_16BIT_FIFOEN+0x296>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007c8c: 687b ldr r3, [r7, #4]
8007c8e: 2200 movs r2, #0
8007c90: 66da str r2, [r3, #108] @ 0x6c
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007c92: 687b ldr r3, [r7, #4]
8007c94: 681b ldr r3, [r3, #0]
8007c96: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007c98: 6bbb ldr r3, [r7, #56] @ 0x38
8007c9a: e853 3f00 ldrex r3, [r3]
8007c9e: 637b str r3, [r7, #52] @ 0x34
return(result);
8007ca0: 6b7b ldr r3, [r7, #52] @ 0x34
8007ca2: f023 0310 bic.w r3, r3, #16
8007ca6: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8007caa: 687b ldr r3, [r7, #4]
8007cac: 681b ldr r3, [r3, #0]
8007cae: 461a mov r2, r3
8007cb0: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
8007cb4: 647b str r3, [r7, #68] @ 0x44
8007cb6: 643a str r2, [r7, #64] @ 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007cb8: 6c39 ldr r1, [r7, #64] @ 0x40
8007cba: 6c7a ldr r2, [r7, #68] @ 0x44
8007cbc: e841 2300 strex r3, r2, [r1]
8007cc0: 63fb str r3, [r7, #60] @ 0x3c
return(result);
8007cc2: 6bfb ldr r3, [r7, #60] @ 0x3c
8007cc4: 2b00 cmp r3, #0
8007cc6: d1e4 bne.n 8007c92 <UART_RxISR_16BIT_FIFOEN+0x23a>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007cc8: 687b ldr r3, [r7, #4]
8007cca: 681b ldr r3, [r3, #0]
8007ccc: 69db ldr r3, [r3, #28]
8007cce: f003 0310 and.w r3, r3, #16
8007cd2: 2b10 cmp r3, #16
8007cd4: d103 bne.n 8007cde <UART_RxISR_16BIT_FIFOEN+0x286>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007cd6: 687b ldr r3, [r7, #4]
8007cd8: 681b ldr r3, [r3, #0]
8007cda: 2210 movs r2, #16
8007cdc: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007cde: 687b ldr r3, [r7, #4]
8007ce0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
8007ce4: 4619 mov r1, r3
8007ce6: 6878 ldr r0, [r7, #4]
8007ce8: f7fe fcf4 bl 80066d4 <HAL_UARTEx_RxEventCallback>
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
break;
8007cec: e00e b.n 8007d0c <UART_RxISR_16BIT_FIFOEN+0x2b4>
HAL_UART_RxCpltCallback(huart);
8007cee: 6878 ldr r0, [r7, #4]
8007cf0: f7f9 f9e2 bl 80010b8 <HAL_UART_RxCpltCallback>
break;
8007cf4: e00a b.n 8007d0c <UART_RxISR_16BIT_FIFOEN+0x2b4>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007cf6: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6
8007cfa: 2b00 cmp r3, #0
8007cfc: d006 beq.n 8007d0c <UART_RxISR_16BIT_FIFOEN+0x2b4>
8007cfe: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8007d02: f003 0320 and.w r3, r3, #32
8007d06: 2b00 cmp r3, #0
8007d08: f47f aeca bne.w 8007aa0 <UART_RxISR_16BIT_FIFOEN+0x48>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8007d0c: 687b ldr r3, [r7, #4]
8007d0e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
8007d12: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
8007d16: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
8007d1a: 2b00 cmp r3, #0
8007d1c: d049 beq.n 8007db2 <UART_RxISR_16BIT_FIFOEN+0x35a>
8007d1e: 687b ldr r3, [r7, #4]
8007d20: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
8007d24: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e
8007d28: 429a cmp r2, r3
8007d2a: d242 bcs.n 8007db2 <UART_RxISR_16BIT_FIFOEN+0x35a>
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8007d2c: 687b ldr r3, [r7, #4]
8007d2e: 681b ldr r3, [r3, #0]
8007d30: 3308 adds r3, #8
8007d32: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007d34: 6a7b ldr r3, [r7, #36] @ 0x24
8007d36: e853 3f00 ldrex r3, [r3]
8007d3a: 623b str r3, [r7, #32]
return(result);
8007d3c: 6a3b ldr r3, [r7, #32]
8007d3e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007d42: f8c7 3088 str.w r3, [r7, #136] @ 0x88
8007d46: 687b ldr r3, [r7, #4]
8007d48: 681b ldr r3, [r3, #0]
8007d4a: 3308 adds r3, #8
8007d4c: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88
8007d50: 633a str r2, [r7, #48] @ 0x30
8007d52: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007d54: 6af9 ldr r1, [r7, #44] @ 0x2c
8007d56: 6b3a ldr r2, [r7, #48] @ 0x30
8007d58: e841 2300 strex r3, r2, [r1]
8007d5c: 62bb str r3, [r7, #40] @ 0x28
return(result);
8007d5e: 6abb ldr r3, [r7, #40] @ 0x28
8007d60: 2b00 cmp r3, #0
8007d62: d1e3 bne.n 8007d2c <UART_RxISR_16BIT_FIFOEN+0x2d4>
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
8007d64: 687b ldr r3, [r7, #4]
8007d66: 4a16 ldr r2, [pc, #88] @ (8007dc0 <UART_RxISR_16BIT_FIFOEN+0x368>)
8007d68: 675a str r2, [r3, #116] @ 0x74
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8007d6a: 687b ldr r3, [r7, #4]
8007d6c: 681b ldr r3, [r3, #0]
8007d6e: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8007d70: 693b ldr r3, [r7, #16]
8007d72: e853 3f00 ldrex r3, [r3]
8007d76: 60fb str r3, [r7, #12]
return(result);
8007d78: 68fb ldr r3, [r7, #12]
8007d7a: f043 0320 orr.w r3, r3, #32
8007d7e: f8c7 3084 str.w r3, [r7, #132] @ 0x84
8007d82: 687b ldr r3, [r7, #4]
8007d84: 681b ldr r3, [r3, #0]
8007d86: 461a mov r2, r3
8007d88: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
8007d8c: 61fb str r3, [r7, #28]
8007d8e: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8007d90: 69b9 ldr r1, [r7, #24]
8007d92: 69fa ldr r2, [r7, #28]
8007d94: e841 2300 strex r3, r2, [r1]
8007d98: 617b str r3, [r7, #20]
return(result);
8007d9a: 697b ldr r3, [r7, #20]
8007d9c: 2b00 cmp r3, #0
8007d9e: d1e4 bne.n 8007d6a <UART_RxISR_16BIT_FIFOEN+0x312>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007da0: e007 b.n 8007db2 <UART_RxISR_16BIT_FIFOEN+0x35a>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007da2: 687b ldr r3, [r7, #4]
8007da4: 681b ldr r3, [r3, #0]
8007da6: 699a ldr r2, [r3, #24]
8007da8: 687b ldr r3, [r7, #4]
8007daa: 681b ldr r3, [r3, #0]
8007dac: f042 0208 orr.w r2, r2, #8
8007db0: 619a str r2, [r3, #24]
}
8007db2: bf00 nop
8007db4: 37b8 adds r7, #184 @ 0xb8
8007db6: 46bd mov sp, r7
8007db8: bd80 pop {r7, pc}
8007dba: bf00 nop
8007dbc: 40008000 .word 0x40008000
8007dc0: 0800753d .word 0x0800753d
08007dc4 <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
8007dc4: b480 push {r7}
8007dc6: b083 sub sp, #12
8007dc8: af00 add r7, sp, #0
8007dca: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8007dcc: bf00 nop
8007dce: 370c adds r7, #12
8007dd0: 46bd mov sp, r7
8007dd2: f85d 7b04 ldr.w r7, [sp], #4
8007dd6: 4770 bx lr
08007dd8 <HAL_UARTEx_RxFifoFullCallback>:
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
8007dd8: b480 push {r7}
8007dda: b083 sub sp, #12
8007ddc: af00 add r7, sp, #0
8007dde: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
8007de0: bf00 nop
8007de2: 370c adds r7, #12
8007de4: 46bd mov sp, r7
8007de6: f85d 7b04 ldr.w r7, [sp], #4
8007dea: 4770 bx lr
08007dec <HAL_UARTEx_TxFifoEmptyCallback>:
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
8007dec: b480 push {r7}
8007dee: b083 sub sp, #12
8007df0: af00 add r7, sp, #0
8007df2: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
8007df4: bf00 nop
8007df6: 370c adds r7, #12
8007df8: 46bd mov sp, r7
8007dfa: f85d 7b04 ldr.w r7, [sp], #4
8007dfe: 4770 bx lr
08007e00 <HAL_UARTEx_DisableFifoMode>:
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
8007e00: b480 push {r7}
8007e02: b085 sub sp, #20
8007e04: af00 add r7, sp, #0
8007e06: 6078 str r0, [r7, #4]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
8007e08: 687b ldr r3, [r7, #4]
8007e0a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
8007e0e: 2b01 cmp r3, #1
8007e10: d101 bne.n 8007e16 <HAL_UARTEx_DisableFifoMode+0x16>
8007e12: 2302 movs r3, #2
8007e14: e027 b.n 8007e66 <HAL_UARTEx_DisableFifoMode+0x66>
8007e16: 687b ldr r3, [r7, #4]
8007e18: 2201 movs r2, #1
8007e1a: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
8007e1e: 687b ldr r3, [r7, #4]
8007e20: 2224 movs r2, #36 @ 0x24
8007e22: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8007e26: 687b ldr r3, [r7, #4]
8007e28: 681b ldr r3, [r3, #0]
8007e2a: 681b ldr r3, [r3, #0]
8007e2c: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8007e2e: 687b ldr r3, [r7, #4]
8007e30: 681b ldr r3, [r3, #0]
8007e32: 681a ldr r2, [r3, #0]
8007e34: 687b ldr r3, [r7, #4]
8007e36: 681b ldr r3, [r3, #0]
8007e38: f022 0201 bic.w r2, r2, #1
8007e3c: 601a str r2, [r3, #0]
/* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
8007e3e: 68fb ldr r3, [r7, #12]
8007e40: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
8007e44: 60fb str r3, [r7, #12]
huart->FifoMode = UART_FIFOMODE_DISABLE;
8007e46: 687b ldr r3, [r7, #4]
8007e48: 2200 movs r2, #0
8007e4a: 665a str r2, [r3, #100] @ 0x64
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8007e4c: 687b ldr r3, [r7, #4]
8007e4e: 681b ldr r3, [r3, #0]
8007e50: 68fa ldr r2, [r7, #12]
8007e52: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8007e54: 687b ldr r3, [r7, #4]
8007e56: 2220 movs r2, #32
8007e58: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007e5c: 687b ldr r3, [r7, #4]
8007e5e: 2200 movs r2, #0
8007e60: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8007e64: 2300 movs r3, #0
}
8007e66: 4618 mov r0, r3
8007e68: 3714 adds r7, #20
8007e6a: 46bd mov sp, r7
8007e6c: f85d 7b04 ldr.w r7, [sp], #4
8007e70: 4770 bx lr
08007e72 <HAL_UARTEx_SetTxFifoThreshold>:
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
8007e72: b580 push {r7, lr}
8007e74: b084 sub sp, #16
8007e76: af00 add r7, sp, #0
8007e78: 6078 str r0, [r7, #4]
8007e7a: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8007e7c: 687b ldr r3, [r7, #4]
8007e7e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
8007e82: 2b01 cmp r3, #1
8007e84: d101 bne.n 8007e8a <HAL_UARTEx_SetTxFifoThreshold+0x18>
8007e86: 2302 movs r3, #2
8007e88: e02d b.n 8007ee6 <HAL_UARTEx_SetTxFifoThreshold+0x74>
8007e8a: 687b ldr r3, [r7, #4]
8007e8c: 2201 movs r2, #1
8007e8e: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
8007e92: 687b ldr r3, [r7, #4]
8007e94: 2224 movs r2, #36 @ 0x24
8007e96: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8007e9a: 687b ldr r3, [r7, #4]
8007e9c: 681b ldr r3, [r3, #0]
8007e9e: 681b ldr r3, [r3, #0]
8007ea0: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8007ea2: 687b ldr r3, [r7, #4]
8007ea4: 681b ldr r3, [r3, #0]
8007ea6: 681a ldr r2, [r3, #0]
8007ea8: 687b ldr r3, [r7, #4]
8007eaa: 681b ldr r3, [r3, #0]
8007eac: f022 0201 bic.w r2, r2, #1
8007eb0: 601a str r2, [r3, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
8007eb2: 687b ldr r3, [r7, #4]
8007eb4: 681b ldr r3, [r3, #0]
8007eb6: 689b ldr r3, [r3, #8]
8007eb8: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
8007ebc: 687b ldr r3, [r7, #4]
8007ebe: 681b ldr r3, [r3, #0]
8007ec0: 683a ldr r2, [r7, #0]
8007ec2: 430a orrs r2, r1
8007ec4: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
8007ec6: 6878 ldr r0, [r7, #4]
8007ec8: f000 f850 bl 8007f6c <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8007ecc: 687b ldr r3, [r7, #4]
8007ece: 681b ldr r3, [r3, #0]
8007ed0: 68fa ldr r2, [r7, #12]
8007ed2: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8007ed4: 687b ldr r3, [r7, #4]
8007ed6: 2220 movs r2, #32
8007ed8: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007edc: 687b ldr r3, [r7, #4]
8007ede: 2200 movs r2, #0
8007ee0: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8007ee4: 2300 movs r3, #0
}
8007ee6: 4618 mov r0, r3
8007ee8: 3710 adds r7, #16
8007eea: 46bd mov sp, r7
8007eec: bd80 pop {r7, pc}
08007eee <HAL_UARTEx_SetRxFifoThreshold>:
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
8007eee: b580 push {r7, lr}
8007ef0: b084 sub sp, #16
8007ef2: af00 add r7, sp, #0
8007ef4: 6078 str r0, [r7, #4]
8007ef6: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8007ef8: 687b ldr r3, [r7, #4]
8007efa: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
8007efe: 2b01 cmp r3, #1
8007f00: d101 bne.n 8007f06 <HAL_UARTEx_SetRxFifoThreshold+0x18>
8007f02: 2302 movs r3, #2
8007f04: e02d b.n 8007f62 <HAL_UARTEx_SetRxFifoThreshold+0x74>
8007f06: 687b ldr r3, [r7, #4]
8007f08: 2201 movs r2, #1
8007f0a: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
8007f0e: 687b ldr r3, [r7, #4]
8007f10: 2224 movs r2, #36 @ 0x24
8007f12: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8007f16: 687b ldr r3, [r7, #4]
8007f18: 681b ldr r3, [r3, #0]
8007f1a: 681b ldr r3, [r3, #0]
8007f1c: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8007f1e: 687b ldr r3, [r7, #4]
8007f20: 681b ldr r3, [r3, #0]
8007f22: 681a ldr r2, [r3, #0]
8007f24: 687b ldr r3, [r7, #4]
8007f26: 681b ldr r3, [r3, #0]
8007f28: f022 0201 bic.w r2, r2, #1
8007f2c: 601a str r2, [r3, #0]
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
8007f2e: 687b ldr r3, [r7, #4]
8007f30: 681b ldr r3, [r3, #0]
8007f32: 689b ldr r3, [r3, #8]
8007f34: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
8007f38: 687b ldr r3, [r7, #4]
8007f3a: 681b ldr r3, [r3, #0]
8007f3c: 683a ldr r2, [r7, #0]
8007f3e: 430a orrs r2, r1
8007f40: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
8007f42: 6878 ldr r0, [r7, #4]
8007f44: f000 f812 bl 8007f6c <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8007f48: 687b ldr r3, [r7, #4]
8007f4a: 681b ldr r3, [r3, #0]
8007f4c: 68fa ldr r2, [r7, #12]
8007f4e: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8007f50: 687b ldr r3, [r7, #4]
8007f52: 2220 movs r2, #32
8007f54: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
8007f58: 687b ldr r3, [r7, #4]
8007f5a: 2200 movs r2, #0
8007f5c: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8007f60: 2300 movs r3, #0
}
8007f62: 4618 mov r0, r3
8007f64: 3710 adds r7, #16
8007f66: 46bd mov sp, r7
8007f68: bd80 pop {r7, pc}
...
08007f6c <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
8007f6c: b480 push {r7}
8007f6e: b085 sub sp, #20
8007f70: af00 add r7, sp, #0
8007f72: 6078 str r0, [r7, #4]
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
8007f74: 687b ldr r3, [r7, #4]
8007f76: 6e5b ldr r3, [r3, #100] @ 0x64
8007f78: 2b00 cmp r3, #0
8007f7a: d108 bne.n 8007f8e <UARTEx_SetNbDataToProcess+0x22>
{
huart->NbTxDataToProcess = 1U;
8007f7c: 687b ldr r3, [r7, #4]
8007f7e: 2201 movs r2, #1
8007f80: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1U;
8007f84: 687b ldr r3, [r7, #4]
8007f86: 2201 movs r2, #1
8007f88: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
8007f8c: e031 b.n 8007ff2 <UARTEx_SetNbDataToProcess+0x86>
rx_fifo_depth = RX_FIFO_DEPTH;
8007f8e: 2308 movs r3, #8
8007f90: 73fb strb r3, [r7, #15]
tx_fifo_depth = TX_FIFO_DEPTH;
8007f92: 2308 movs r3, #8
8007f94: 73bb strb r3, [r7, #14]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8007f96: 687b ldr r3, [r7, #4]
8007f98: 681b ldr r3, [r3, #0]
8007f9a: 689b ldr r3, [r3, #8]
8007f9c: 0e5b lsrs r3, r3, #25
8007f9e: b2db uxtb r3, r3
8007fa0: f003 0307 and.w r3, r3, #7
8007fa4: 737b strb r3, [r7, #13]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
8007fa6: 687b ldr r3, [r7, #4]
8007fa8: 681b ldr r3, [r3, #0]
8007faa: 689b ldr r3, [r3, #8]
8007fac: 0f5b lsrs r3, r3, #29
8007fae: b2db uxtb r3, r3
8007fb0: f003 0307 and.w r3, r3, #7
8007fb4: 733b strb r3, [r7, #12]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8007fb6: 7bbb ldrb r3, [r7, #14]
8007fb8: 7b3a ldrb r2, [r7, #12]
8007fba: 4911 ldr r1, [pc, #68] @ (8008000 <UARTEx_SetNbDataToProcess+0x94>)
8007fbc: 5c8a ldrb r2, [r1, r2]
8007fbe: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[tx_fifo_threshold];
8007fc2: 7b3a ldrb r2, [r7, #12]
8007fc4: 490f ldr r1, [pc, #60] @ (8008004 <UARTEx_SetNbDataToProcess+0x98>)
8007fc6: 5c8a ldrb r2, [r1, r2]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8007fc8: fb93 f3f2 sdiv r3, r3, r2
8007fcc: b29a uxth r2, r3
8007fce: 687b ldr r3, [r7, #4]
8007fd0: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8007fd4: 7bfb ldrb r3, [r7, #15]
8007fd6: 7b7a ldrb r2, [r7, #13]
8007fd8: 4909 ldr r1, [pc, #36] @ (8008000 <UARTEx_SetNbDataToProcess+0x94>)
8007fda: 5c8a ldrb r2, [r1, r2]
8007fdc: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[rx_fifo_threshold];
8007fe0: 7b7a ldrb r2, [r7, #13]
8007fe2: 4908 ldr r1, [pc, #32] @ (8008004 <UARTEx_SetNbDataToProcess+0x98>)
8007fe4: 5c8a ldrb r2, [r1, r2]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8007fe6: fb93 f3f2 sdiv r3, r3, r2
8007fea: b29a uxth r2, r3
8007fec: 687b ldr r3, [r7, #4]
8007fee: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
}
8007ff2: bf00 nop
8007ff4: 3714 adds r7, #20
8007ff6: 46bd mov sp, r7
8007ff8: f85d 7b04 ldr.w r7, [sp], #4
8007ffc: 4770 bx lr
8007ffe: bf00 nop
8008000: 080080dc .word 0x080080dc
8008004: 080080e4 .word 0x080080e4
08008008 <memset>:
8008008: 4402 add r2, r0
800800a: 4603 mov r3, r0
800800c: 4293 cmp r3, r2
800800e: d100 bne.n 8008012 <memset+0xa>
8008010: 4770 bx lr
8008012: f803 1b01 strb.w r1, [r3], #1
8008016: e7f9 b.n 800800c <memset+0x4>
08008018 <__libc_init_array>:
8008018: b570 push {r4, r5, r6, lr}
800801a: 4d0d ldr r5, [pc, #52] @ (8008050 <__libc_init_array+0x38>)
800801c: 4c0d ldr r4, [pc, #52] @ (8008054 <__libc_init_array+0x3c>)
800801e: 1b64 subs r4, r4, r5
8008020: 10a4 asrs r4, r4, #2
8008022: 2600 movs r6, #0
8008024: 42a6 cmp r6, r4
8008026: d109 bne.n 800803c <__libc_init_array+0x24>
8008028: 4d0b ldr r5, [pc, #44] @ (8008058 <__libc_init_array+0x40>)
800802a: 4c0c ldr r4, [pc, #48] @ (800805c <__libc_init_array+0x44>)
800802c: f000 f818 bl 8008060 <_init>
8008030: 1b64 subs r4, r4, r5
8008032: 10a4 asrs r4, r4, #2
8008034: 2600 movs r6, #0
8008036: 42a6 cmp r6, r4
8008038: d105 bne.n 8008046 <__libc_init_array+0x2e>
800803a: bd70 pop {r4, r5, r6, pc}
800803c: f855 3b04 ldr.w r3, [r5], #4
8008040: 4798 blx r3
8008042: 3601 adds r6, #1
8008044: e7ee b.n 8008024 <__libc_init_array+0xc>
8008046: f855 3b04 ldr.w r3, [r5], #4
800804a: 4798 blx r3
800804c: 3601 adds r6, #1
800804e: e7f2 b.n 8008036 <__libc_init_array+0x1e>
8008050: 080080f4 .word 0x080080f4
8008054: 080080f4 .word 0x080080f4
8008058: 080080f4 .word 0x080080f4
800805c: 080080f8 .word 0x080080f8
08008060 <_init>:
8008060: b5f8 push {r3, r4, r5, r6, r7, lr}
8008062: bf00 nop
8008064: bcf8 pop {r3, r4, r5, r6, r7}
8008066: bc08 pop {r3}
8008068: 469e mov lr, r3
800806a: 4770 bx lr
0800806c <_fini>:
800806c: b5f8 push {r3, r4, r5, r6, r7, lr}
800806e: bf00 nop
8008070: bcf8 pop {r3, r4, r5, r6, r7}
8008072: bc08 pop {r3}
8008074: 469e mov lr, r3
8008076: 4770 bx lr
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