21344 lines
820 KiB
Plaintext
21344 lines
820 KiB
Plaintext
|
|
POWER_SWITCH.elf: file format elf32-littlearm
|
|
|
|
Sections:
|
|
Idx Name Size VMA LMA File off Algn
|
|
0 .isr_vector 000001d8 08000000 08000000 00001000 2**0
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
1 .text 00007e1c 080001d8 080001d8 000011d8 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
|
2 .rodata 00000074 08007ff4 08007ff4 00008ff4 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
3 .ARM.extab 00000000 08008068 08008068 0000a028 2**0
|
|
CONTENTS, READONLY
|
|
4 .ARM 00000008 08008068 08008068 00009068 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
5 .preinit_array 00000000 08008070 08008070 0000a028 2**0
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
6 .init_array 00000004 08008070 08008070 00009070 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
7 .fini_array 00000004 08008074 08008074 00009074 2**2
|
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
|
8 .data 00000028 20000000 08008078 0000a000 2**2
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
9 .bss 00000338 20000028 080080a0 0000a028 2**2
|
|
ALLOC
|
|
10 ._user_heap_stack 00000600 20000360 080080a0 0000a360 2**0
|
|
ALLOC
|
|
11 .ARM.attributes 00000030 00000000 00000000 0000a028 2**0
|
|
CONTENTS, READONLY
|
|
12 .debug_info 000174f0 00000000 00000000 0000a058 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
13 .debug_abbrev 00002a3a 00000000 00000000 00021548 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
14 .debug_aranges 000014b8 00000000 00000000 00023f88 2**3
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
15 .debug_rnglists 00001033 00000000 00000000 00025440 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
16 .debug_macro 00020283 00000000 00000000 00026473 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
17 .debug_line 00016a69 00000000 00000000 000466f6 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
18 .debug_str 000db12d 00000000 00000000 0005d15f 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
19 .comment 00000043 00000000 00000000 0013828c 2**0
|
|
CONTENTS, READONLY
|
|
20 .debug_frame 00005a0c 00000000 00000000 001382d0 2**2
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
21 .debug_line_str 0000006d 00000000 00000000 0013dcdc 2**0
|
|
CONTENTS, READONLY, DEBUGGING, OCTETS
|
|
|
|
Disassembly of section .text:
|
|
|
|
080001d8 <__do_global_dtors_aux>:
|
|
80001d8: b510 push {r4, lr}
|
|
80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
|
|
80001dc: 7823 ldrb r3, [r4, #0]
|
|
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
|
|
80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
|
|
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
|
|
80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
|
|
80001e6: f3af 8000 nop.w
|
|
80001ea: 2301 movs r3, #1
|
|
80001ec: 7023 strb r3, [r4, #0]
|
|
80001ee: bd10 pop {r4, pc}
|
|
80001f0: 20000028 .word 0x20000028
|
|
80001f4: 00000000 .word 0x00000000
|
|
80001f8: 08007fdc .word 0x08007fdc
|
|
|
|
080001fc <frame_dummy>:
|
|
80001fc: b508 push {r3, lr}
|
|
80001fe: 4b03 ldr r3, [pc, #12] @ (800020c <frame_dummy+0x10>)
|
|
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
|
|
8000202: 4903 ldr r1, [pc, #12] @ (8000210 <frame_dummy+0x14>)
|
|
8000204: 4803 ldr r0, [pc, #12] @ (8000214 <frame_dummy+0x18>)
|
|
8000206: f3af 8000 nop.w
|
|
800020a: bd08 pop {r3, pc}
|
|
800020c: 00000000 .word 0x00000000
|
|
8000210: 2000002c .word 0x2000002c
|
|
8000214: 08007fdc .word 0x08007fdc
|
|
|
|
08000218 <__aeabi_uldivmod>:
|
|
8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18>
|
|
800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18>
|
|
800021c: 2900 cmp r1, #0
|
|
800021e: bf08 it eq
|
|
8000220: 2800 cmpeq r0, #0
|
|
8000222: bf1c itt ne
|
|
8000224: f04f 31ff movne.w r1, #4294967295
|
|
8000228: f04f 30ff movne.w r0, #4294967295
|
|
800022c: f000 b988 b.w 8000540 <__aeabi_idiv0>
|
|
8000230: f1ad 0c08 sub.w ip, sp, #8
|
|
8000234: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000238: f000 f806 bl 8000248 <__udivmoddi4>
|
|
800023c: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000240: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000244: b004 add sp, #16
|
|
8000246: 4770 bx lr
|
|
|
|
08000248 <__udivmoddi4>:
|
|
8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800024c: 9d08 ldr r5, [sp, #32]
|
|
800024e: 468e mov lr, r1
|
|
8000250: 4604 mov r4, r0
|
|
8000252: 4688 mov r8, r1
|
|
8000254: 2b00 cmp r3, #0
|
|
8000256: d14a bne.n 80002ee <__udivmoddi4+0xa6>
|
|
8000258: 428a cmp r2, r1
|
|
800025a: 4617 mov r7, r2
|
|
800025c: d962 bls.n 8000324 <__udivmoddi4+0xdc>
|
|
800025e: fab2 f682 clz r6, r2
|
|
8000262: b14e cbz r6, 8000278 <__udivmoddi4+0x30>
|
|
8000264: f1c6 0320 rsb r3, r6, #32
|
|
8000268: fa01 f806 lsl.w r8, r1, r6
|
|
800026c: fa20 f303 lsr.w r3, r0, r3
|
|
8000270: 40b7 lsls r7, r6
|
|
8000272: ea43 0808 orr.w r8, r3, r8
|
|
8000276: 40b4 lsls r4, r6
|
|
8000278: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
800027c: fa1f fc87 uxth.w ip, r7
|
|
8000280: fbb8 f1fe udiv r1, r8, lr
|
|
8000284: 0c23 lsrs r3, r4, #16
|
|
8000286: fb0e 8811 mls r8, lr, r1, r8
|
|
800028a: ea43 4308 orr.w r3, r3, r8, lsl #16
|
|
800028e: fb01 f20c mul.w r2, r1, ip
|
|
8000292: 429a cmp r2, r3
|
|
8000294: d909 bls.n 80002aa <__udivmoddi4+0x62>
|
|
8000296: 18fb adds r3, r7, r3
|
|
8000298: f101 30ff add.w r0, r1, #4294967295
|
|
800029c: f080 80ea bcs.w 8000474 <__udivmoddi4+0x22c>
|
|
80002a0: 429a cmp r2, r3
|
|
80002a2: f240 80e7 bls.w 8000474 <__udivmoddi4+0x22c>
|
|
80002a6: 3902 subs r1, #2
|
|
80002a8: 443b add r3, r7
|
|
80002aa: 1a9a subs r2, r3, r2
|
|
80002ac: b2a3 uxth r3, r4
|
|
80002ae: fbb2 f0fe udiv r0, r2, lr
|
|
80002b2: fb0e 2210 mls r2, lr, r0, r2
|
|
80002b6: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
80002ba: fb00 fc0c mul.w ip, r0, ip
|
|
80002be: 459c cmp ip, r3
|
|
80002c0: d909 bls.n 80002d6 <__udivmoddi4+0x8e>
|
|
80002c2: 18fb adds r3, r7, r3
|
|
80002c4: f100 32ff add.w r2, r0, #4294967295
|
|
80002c8: f080 80d6 bcs.w 8000478 <__udivmoddi4+0x230>
|
|
80002cc: 459c cmp ip, r3
|
|
80002ce: f240 80d3 bls.w 8000478 <__udivmoddi4+0x230>
|
|
80002d2: 443b add r3, r7
|
|
80002d4: 3802 subs r0, #2
|
|
80002d6: ea40 4001 orr.w r0, r0, r1, lsl #16
|
|
80002da: eba3 030c sub.w r3, r3, ip
|
|
80002de: 2100 movs r1, #0
|
|
80002e0: b11d cbz r5, 80002ea <__udivmoddi4+0xa2>
|
|
80002e2: 40f3 lsrs r3, r6
|
|
80002e4: 2200 movs r2, #0
|
|
80002e6: e9c5 3200 strd r3, r2, [r5]
|
|
80002ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
80002ee: 428b cmp r3, r1
|
|
80002f0: d905 bls.n 80002fe <__udivmoddi4+0xb6>
|
|
80002f2: b10d cbz r5, 80002f8 <__udivmoddi4+0xb0>
|
|
80002f4: e9c5 0100 strd r0, r1, [r5]
|
|
80002f8: 2100 movs r1, #0
|
|
80002fa: 4608 mov r0, r1
|
|
80002fc: e7f5 b.n 80002ea <__udivmoddi4+0xa2>
|
|
80002fe: fab3 f183 clz r1, r3
|
|
8000302: 2900 cmp r1, #0
|
|
8000304: d146 bne.n 8000394 <__udivmoddi4+0x14c>
|
|
8000306: 4573 cmp r3, lr
|
|
8000308: d302 bcc.n 8000310 <__udivmoddi4+0xc8>
|
|
800030a: 4282 cmp r2, r0
|
|
800030c: f200 8105 bhi.w 800051a <__udivmoddi4+0x2d2>
|
|
8000310: 1a84 subs r4, r0, r2
|
|
8000312: eb6e 0203 sbc.w r2, lr, r3
|
|
8000316: 2001 movs r0, #1
|
|
8000318: 4690 mov r8, r2
|
|
800031a: 2d00 cmp r5, #0
|
|
800031c: d0e5 beq.n 80002ea <__udivmoddi4+0xa2>
|
|
800031e: e9c5 4800 strd r4, r8, [r5]
|
|
8000322: e7e2 b.n 80002ea <__udivmoddi4+0xa2>
|
|
8000324: 2a00 cmp r2, #0
|
|
8000326: f000 8090 beq.w 800044a <__udivmoddi4+0x202>
|
|
800032a: fab2 f682 clz r6, r2
|
|
800032e: 2e00 cmp r6, #0
|
|
8000330: f040 80a4 bne.w 800047c <__udivmoddi4+0x234>
|
|
8000334: 1a8a subs r2, r1, r2
|
|
8000336: 0c03 lsrs r3, r0, #16
|
|
8000338: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
800033c: b280 uxth r0, r0
|
|
800033e: b2bc uxth r4, r7
|
|
8000340: 2101 movs r1, #1
|
|
8000342: fbb2 fcfe udiv ip, r2, lr
|
|
8000346: fb0e 221c mls r2, lr, ip, r2
|
|
800034a: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
800034e: fb04 f20c mul.w r2, r4, ip
|
|
8000352: 429a cmp r2, r3
|
|
8000354: d907 bls.n 8000366 <__udivmoddi4+0x11e>
|
|
8000356: 18fb adds r3, r7, r3
|
|
8000358: f10c 38ff add.w r8, ip, #4294967295
|
|
800035c: d202 bcs.n 8000364 <__udivmoddi4+0x11c>
|
|
800035e: 429a cmp r2, r3
|
|
8000360: f200 80e0 bhi.w 8000524 <__udivmoddi4+0x2dc>
|
|
8000364: 46c4 mov ip, r8
|
|
8000366: 1a9b subs r3, r3, r2
|
|
8000368: fbb3 f2fe udiv r2, r3, lr
|
|
800036c: fb0e 3312 mls r3, lr, r2, r3
|
|
8000370: ea40 4303 orr.w r3, r0, r3, lsl #16
|
|
8000374: fb02 f404 mul.w r4, r2, r4
|
|
8000378: 429c cmp r4, r3
|
|
800037a: d907 bls.n 800038c <__udivmoddi4+0x144>
|
|
800037c: 18fb adds r3, r7, r3
|
|
800037e: f102 30ff add.w r0, r2, #4294967295
|
|
8000382: d202 bcs.n 800038a <__udivmoddi4+0x142>
|
|
8000384: 429c cmp r4, r3
|
|
8000386: f200 80ca bhi.w 800051e <__udivmoddi4+0x2d6>
|
|
800038a: 4602 mov r2, r0
|
|
800038c: 1b1b subs r3, r3, r4
|
|
800038e: ea42 400c orr.w r0, r2, ip, lsl #16
|
|
8000392: e7a5 b.n 80002e0 <__udivmoddi4+0x98>
|
|
8000394: f1c1 0620 rsb r6, r1, #32
|
|
8000398: 408b lsls r3, r1
|
|
800039a: fa22 f706 lsr.w r7, r2, r6
|
|
800039e: 431f orrs r7, r3
|
|
80003a0: fa0e f401 lsl.w r4, lr, r1
|
|
80003a4: fa20 f306 lsr.w r3, r0, r6
|
|
80003a8: fa2e fe06 lsr.w lr, lr, r6
|
|
80003ac: ea4f 4917 mov.w r9, r7, lsr #16
|
|
80003b0: 4323 orrs r3, r4
|
|
80003b2: fa00 f801 lsl.w r8, r0, r1
|
|
80003b6: fa1f fc87 uxth.w ip, r7
|
|
80003ba: fbbe f0f9 udiv r0, lr, r9
|
|
80003be: 0c1c lsrs r4, r3, #16
|
|
80003c0: fb09 ee10 mls lr, r9, r0, lr
|
|
80003c4: ea44 440e orr.w r4, r4, lr, lsl #16
|
|
80003c8: fb00 fe0c mul.w lr, r0, ip
|
|
80003cc: 45a6 cmp lr, r4
|
|
80003ce: fa02 f201 lsl.w r2, r2, r1
|
|
80003d2: d909 bls.n 80003e8 <__udivmoddi4+0x1a0>
|
|
80003d4: 193c adds r4, r7, r4
|
|
80003d6: f100 3aff add.w sl, r0, #4294967295
|
|
80003da: f080 809c bcs.w 8000516 <__udivmoddi4+0x2ce>
|
|
80003de: 45a6 cmp lr, r4
|
|
80003e0: f240 8099 bls.w 8000516 <__udivmoddi4+0x2ce>
|
|
80003e4: 3802 subs r0, #2
|
|
80003e6: 443c add r4, r7
|
|
80003e8: eba4 040e sub.w r4, r4, lr
|
|
80003ec: fa1f fe83 uxth.w lr, r3
|
|
80003f0: fbb4 f3f9 udiv r3, r4, r9
|
|
80003f4: fb09 4413 mls r4, r9, r3, r4
|
|
80003f8: ea4e 4404 orr.w r4, lr, r4, lsl #16
|
|
80003fc: fb03 fc0c mul.w ip, r3, ip
|
|
8000400: 45a4 cmp ip, r4
|
|
8000402: d908 bls.n 8000416 <__udivmoddi4+0x1ce>
|
|
8000404: 193c adds r4, r7, r4
|
|
8000406: f103 3eff add.w lr, r3, #4294967295
|
|
800040a: f080 8082 bcs.w 8000512 <__udivmoddi4+0x2ca>
|
|
800040e: 45a4 cmp ip, r4
|
|
8000410: d97f bls.n 8000512 <__udivmoddi4+0x2ca>
|
|
8000412: 3b02 subs r3, #2
|
|
8000414: 443c add r4, r7
|
|
8000416: ea43 4000 orr.w r0, r3, r0, lsl #16
|
|
800041a: eba4 040c sub.w r4, r4, ip
|
|
800041e: fba0 ec02 umull lr, ip, r0, r2
|
|
8000422: 4564 cmp r4, ip
|
|
8000424: 4673 mov r3, lr
|
|
8000426: 46e1 mov r9, ip
|
|
8000428: d362 bcc.n 80004f0 <__udivmoddi4+0x2a8>
|
|
800042a: d05f beq.n 80004ec <__udivmoddi4+0x2a4>
|
|
800042c: b15d cbz r5, 8000446 <__udivmoddi4+0x1fe>
|
|
800042e: ebb8 0203 subs.w r2, r8, r3
|
|
8000432: eb64 0409 sbc.w r4, r4, r9
|
|
8000436: fa04 f606 lsl.w r6, r4, r6
|
|
800043a: fa22 f301 lsr.w r3, r2, r1
|
|
800043e: 431e orrs r6, r3
|
|
8000440: 40cc lsrs r4, r1
|
|
8000442: e9c5 6400 strd r6, r4, [r5]
|
|
8000446: 2100 movs r1, #0
|
|
8000448: e74f b.n 80002ea <__udivmoddi4+0xa2>
|
|
800044a: fbb1 fcf2 udiv ip, r1, r2
|
|
800044e: 0c01 lsrs r1, r0, #16
|
|
8000450: ea41 410e orr.w r1, r1, lr, lsl #16
|
|
8000454: b280 uxth r0, r0
|
|
8000456: ea40 4201 orr.w r2, r0, r1, lsl #16
|
|
800045a: 463b mov r3, r7
|
|
800045c: 4638 mov r0, r7
|
|
800045e: 463c mov r4, r7
|
|
8000460: 46b8 mov r8, r7
|
|
8000462: 46be mov lr, r7
|
|
8000464: 2620 movs r6, #32
|
|
8000466: fbb1 f1f7 udiv r1, r1, r7
|
|
800046a: eba2 0208 sub.w r2, r2, r8
|
|
800046e: ea41 410c orr.w r1, r1, ip, lsl #16
|
|
8000472: e766 b.n 8000342 <__udivmoddi4+0xfa>
|
|
8000474: 4601 mov r1, r0
|
|
8000476: e718 b.n 80002aa <__udivmoddi4+0x62>
|
|
8000478: 4610 mov r0, r2
|
|
800047a: e72c b.n 80002d6 <__udivmoddi4+0x8e>
|
|
800047c: f1c6 0220 rsb r2, r6, #32
|
|
8000480: fa2e f302 lsr.w r3, lr, r2
|
|
8000484: 40b7 lsls r7, r6
|
|
8000486: 40b1 lsls r1, r6
|
|
8000488: fa20 f202 lsr.w r2, r0, r2
|
|
800048c: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000490: 430a orrs r2, r1
|
|
8000492: fbb3 f8fe udiv r8, r3, lr
|
|
8000496: b2bc uxth r4, r7
|
|
8000498: fb0e 3318 mls r3, lr, r8, r3
|
|
800049c: 0c11 lsrs r1, r2, #16
|
|
800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
80004a2: fb08 f904 mul.w r9, r8, r4
|
|
80004a6: 40b0 lsls r0, r6
|
|
80004a8: 4589 cmp r9, r1
|
|
80004aa: ea4f 4310 mov.w r3, r0, lsr #16
|
|
80004ae: b280 uxth r0, r0
|
|
80004b0: d93e bls.n 8000530 <__udivmoddi4+0x2e8>
|
|
80004b2: 1879 adds r1, r7, r1
|
|
80004b4: f108 3cff add.w ip, r8, #4294967295
|
|
80004b8: d201 bcs.n 80004be <__udivmoddi4+0x276>
|
|
80004ba: 4589 cmp r9, r1
|
|
80004bc: d81f bhi.n 80004fe <__udivmoddi4+0x2b6>
|
|
80004be: eba1 0109 sub.w r1, r1, r9
|
|
80004c2: fbb1 f9fe udiv r9, r1, lr
|
|
80004c6: fb09 f804 mul.w r8, r9, r4
|
|
80004ca: fb0e 1119 mls r1, lr, r9, r1
|
|
80004ce: b292 uxth r2, r2
|
|
80004d0: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004d4: 4542 cmp r2, r8
|
|
80004d6: d229 bcs.n 800052c <__udivmoddi4+0x2e4>
|
|
80004d8: 18ba adds r2, r7, r2
|
|
80004da: f109 31ff add.w r1, r9, #4294967295
|
|
80004de: d2c4 bcs.n 800046a <__udivmoddi4+0x222>
|
|
80004e0: 4542 cmp r2, r8
|
|
80004e2: d2c2 bcs.n 800046a <__udivmoddi4+0x222>
|
|
80004e4: f1a9 0102 sub.w r1, r9, #2
|
|
80004e8: 443a add r2, r7
|
|
80004ea: e7be b.n 800046a <__udivmoddi4+0x222>
|
|
80004ec: 45f0 cmp r8, lr
|
|
80004ee: d29d bcs.n 800042c <__udivmoddi4+0x1e4>
|
|
80004f0: ebbe 0302 subs.w r3, lr, r2
|
|
80004f4: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004f8: 3801 subs r0, #1
|
|
80004fa: 46e1 mov r9, ip
|
|
80004fc: e796 b.n 800042c <__udivmoddi4+0x1e4>
|
|
80004fe: eba7 0909 sub.w r9, r7, r9
|
|
8000502: 4449 add r1, r9
|
|
8000504: f1a8 0c02 sub.w ip, r8, #2
|
|
8000508: fbb1 f9fe udiv r9, r1, lr
|
|
800050c: fb09 f804 mul.w r8, r9, r4
|
|
8000510: e7db b.n 80004ca <__udivmoddi4+0x282>
|
|
8000512: 4673 mov r3, lr
|
|
8000514: e77f b.n 8000416 <__udivmoddi4+0x1ce>
|
|
8000516: 4650 mov r0, sl
|
|
8000518: e766 b.n 80003e8 <__udivmoddi4+0x1a0>
|
|
800051a: 4608 mov r0, r1
|
|
800051c: e6fd b.n 800031a <__udivmoddi4+0xd2>
|
|
800051e: 443b add r3, r7
|
|
8000520: 3a02 subs r2, #2
|
|
8000522: e733 b.n 800038c <__udivmoddi4+0x144>
|
|
8000524: f1ac 0c02 sub.w ip, ip, #2
|
|
8000528: 443b add r3, r7
|
|
800052a: e71c b.n 8000366 <__udivmoddi4+0x11e>
|
|
800052c: 4649 mov r1, r9
|
|
800052e: e79c b.n 800046a <__udivmoddi4+0x222>
|
|
8000530: eba1 0109 sub.w r1, r1, r9
|
|
8000534: 46c4 mov ip, r8
|
|
8000536: fbb1 f9fe udiv r9, r1, lr
|
|
800053a: fb09 f804 mul.w r8, r9, r4
|
|
800053e: e7c4 b.n 80004ca <__udivmoddi4+0x282>
|
|
|
|
08000540 <__aeabi_idiv0>:
|
|
8000540: 4770 bx lr
|
|
8000542: bf00 nop
|
|
|
|
08000544 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000544: b580 push {r7, lr}
|
|
8000546: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000548: f001 f8b1 bl 80016ae <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800054c: f000 f932 bl 80007b4 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000550: f000 fb6e bl 8000c30 <MX_GPIO_Init>
|
|
MX_USART2_UART_Init();
|
|
8000554: f000 fb20 bl 8000b98 <MX_USART2_UART_Init>
|
|
MX_ADC2_Init();
|
|
8000558: f000 f9f0 bl 800093c <MX_ADC2_Init>
|
|
MX_TIM2_Init();
|
|
800055c: f000 fa54 bl 8000a08 <MX_TIM2_Init>
|
|
MX_ADC1_Init();
|
|
8000560: f000 f974 bl 800084c <MX_ADC1_Init>
|
|
MX_TIM16_Init();
|
|
8000564: f000 fa9e bl 8000aa4 <MX_TIM16_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
/*Configure GPIO pin output Level */
|
|
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
|
|
8000568: 2200 movs r2, #0
|
|
800056a: f44f 7180 mov.w r1, #256 @ 0x100
|
|
800056e: 4876 ldr r0, [pc, #472] @ (8000748 <main+0x204>)
|
|
8000570: f003 f91e bl 80037b0 <HAL_GPIO_WritePin>
|
|
|
|
/* Run ADC calibration */
|
|
HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
|
|
8000574: 217f movs r1, #127 @ 0x7f
|
|
8000576: 4875 ldr r0, [pc, #468] @ (800074c <main+0x208>)
|
|
8000578: f002 fcc2 bl 8002f00 <HAL_ADCEx_Calibration_Start>
|
|
HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED);
|
|
800057c: 217f movs r1, #127 @ 0x7f
|
|
800057e: 4874 ldr r0, [pc, #464] @ (8000750 <main+0x20c>)
|
|
8000580: f002 fcbe bl 8002f00 <HAL_ADCEx_Calibration_Start>
|
|
|
|
/* Setup UART interrupts */
|
|
/* Make sure UART Rx counters and flags are reset */
|
|
rx_counter = 0x00;
|
|
8000584: 4b73 ldr r3, [pc, #460] @ (8000754 <main+0x210>)
|
|
8000586: 2200 movs r2, #0
|
|
8000588: 701a strb r2, [r3, #0]
|
|
rx_len = 0x00;
|
|
800058a: 4b73 ldr r3, [pc, #460] @ (8000758 <main+0x214>)
|
|
800058c: 2200 movs r2, #0
|
|
800058e: 701a strb r2, [r3, #0]
|
|
rx_len_counter = 0x00;
|
|
8000590: 4b72 ldr r3, [pc, #456] @ (800075c <main+0x218>)
|
|
8000592: 2200 movs r2, #0
|
|
8000594: 701a strb r2, [r3, #0]
|
|
adc_task_flag = 0x00;
|
|
8000596: 4b72 ldr r3, [pc, #456] @ (8000760 <main+0x21c>)
|
|
8000598: 2200 movs r2, #0
|
|
800059a: 701a strb r2, [r3, #0]
|
|
pwm_value = 0x0000;
|
|
800059c: 4b71 ldr r3, [pc, #452] @ (8000764 <main+0x220>)
|
|
800059e: 2200 movs r2, #0
|
|
80005a0: 801a strh r2, [r3, #0]
|
|
|
|
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
|
|
80005a2: 2201 movs r2, #1
|
|
80005a4: 4970 ldr r1, [pc, #448] @ (8000768 <main+0x224>)
|
|
80005a6: 4871 ldr r0, [pc, #452] @ (800076c <main+0x228>)
|
|
80005a8: f005 fcba bl 8005f20 <HAL_UART_Receive_IT>
|
|
|
|
/* Get real VDDA value */
|
|
vdd_ref = get_actual_vdda(&hadc1);
|
|
80005ac: 4867 ldr r0, [pc, #412] @ (800074c <main+0x208>)
|
|
80005ae: f000 fc0f bl 8000dd0 <get_actual_vdda>
|
|
80005b2: eef0 7a40 vmov.f32 s15, s0
|
|
80005b6: 4b6e ldr r3, [pc, #440] @ (8000770 <main+0x22c>)
|
|
80005b8: edc3 7a00 vstr s15, [r3]
|
|
|
|
/* Start output PWM at zero */
|
|
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
|
|
80005bc: 4b6d ldr r3, [pc, #436] @ (8000774 <main+0x230>)
|
|
80005be: 681b ldr r3, [r3, #0]
|
|
80005c0: 2200 movs r2, #0
|
|
80005c2: 635a str r2, [r3, #52] @ 0x34
|
|
HAL_TIM_PWM_Start(&htim16, TIM_CHANNEL_1);
|
|
80005c4: 2100 movs r1, #0
|
|
80005c6: 486b ldr r0, [pc, #428] @ (8000774 <main+0x230>)
|
|
80005c8: f004 f994 bl 80048f4 <HAL_TIM_PWM_Start>
|
|
|
|
ADC_Filter_Init(&v_out_filter);
|
|
80005cc: 486a ldr r0, [pc, #424] @ (8000778 <main+0x234>)
|
|
80005ce: f000 fb6f bl 8000cb0 <ADC_Filter_Init>
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
|
|
while (1)
|
|
{
|
|
if (adc_task_flag == 0xff)
|
|
80005d2: 4b63 ldr r3, [pc, #396] @ (8000760 <main+0x21c>)
|
|
80005d4: 781b ldrb r3, [r3, #0]
|
|
80005d6: 2bff cmp r3, #255 @ 0xff
|
|
80005d8: d15f bne.n 800069a <main+0x156>
|
|
{
|
|
adc_task_flag = 0x00;
|
|
80005da: 4b61 ldr r3, [pc, #388] @ (8000760 <main+0x21c>)
|
|
80005dc: 2200 movs r2, #0
|
|
80005de: 701a strb r2, [r3, #0]
|
|
|
|
tx_len = 0x04;
|
|
80005e0: 4b66 ldr r3, [pc, #408] @ (800077c <main+0x238>)
|
|
80005e2: 2204 movs r2, #4
|
|
80005e4: 701a strb r2, [r3, #0]
|
|
|
|
tx_buffer[0] = IN_SYNC_BYTE_1;
|
|
80005e6: 4b66 ldr r3, [pc, #408] @ (8000780 <main+0x23c>)
|
|
80005e8: 2241 movs r2, #65 @ 0x41
|
|
80005ea: 701a strb r2, [r3, #0]
|
|
tx_buffer[1] = IN_SYNC_BYTE_2;
|
|
80005ec: 4b64 ldr r3, [pc, #400] @ (8000780 <main+0x23c>)
|
|
80005ee: 2252 movs r2, #82 @ 0x52
|
|
80005f0: 705a strb r2, [r3, #1]
|
|
tx_buffer[2] = tx_len;
|
|
80005f2: 4b62 ldr r3, [pc, #392] @ (800077c <main+0x238>)
|
|
80005f4: 781a ldrb r2, [r3, #0]
|
|
80005f6: 4b62 ldr r3, [pc, #392] @ (8000780 <main+0x23c>)
|
|
80005f8: 709a strb r2, [r3, #2]
|
|
tx_buffer[3] = (uint8_t)((vout_adj_uint >> 24) & 0xFF);
|
|
80005fa: 4b62 ldr r3, [pc, #392] @ (8000784 <main+0x240>)
|
|
80005fc: 681b ldr r3, [r3, #0]
|
|
80005fe: 0e1b lsrs r3, r3, #24
|
|
8000600: b2da uxtb r2, r3
|
|
8000602: 4b5f ldr r3, [pc, #380] @ (8000780 <main+0x23c>)
|
|
8000604: 70da strb r2, [r3, #3]
|
|
tx_buffer[4] = (uint8_t)((vout_adj_uint >> 16) & 0xFF);
|
|
8000606: 4b5f ldr r3, [pc, #380] @ (8000784 <main+0x240>)
|
|
8000608: 681b ldr r3, [r3, #0]
|
|
800060a: 0c1b lsrs r3, r3, #16
|
|
800060c: b2da uxtb r2, r3
|
|
800060e: 4b5c ldr r3, [pc, #368] @ (8000780 <main+0x23c>)
|
|
8000610: 711a strb r2, [r3, #4]
|
|
tx_buffer[5] = (uint8_t)((vout_adj_uint >> 8) & 0xFF);
|
|
8000612: 4b5c ldr r3, [pc, #368] @ (8000784 <main+0x240>)
|
|
8000614: 681b ldr r3, [r3, #0]
|
|
8000616: 0a1b lsrs r3, r3, #8
|
|
8000618: b2da uxtb r2, r3
|
|
800061a: 4b59 ldr r3, [pc, #356] @ (8000780 <main+0x23c>)
|
|
800061c: 715a strb r2, [r3, #5]
|
|
tx_buffer[6] = (uint8_t)(vout_adj_uint & 0xFF);
|
|
800061e: 4b59 ldr r3, [pc, #356] @ (8000784 <main+0x240>)
|
|
8000620: 681b ldr r3, [r3, #0]
|
|
8000622: b2da uxtb r2, r3
|
|
8000624: 4b56 ldr r3, [pc, #344] @ (8000780 <main+0x23c>)
|
|
8000626: 719a strb r2, [r3, #6]
|
|
|
|
/* Need to apply checksum to all data bits */
|
|
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
|
|
8000628: 4b57 ldr r3, [pc, #348] @ (8000788 <main+0x244>)
|
|
800062a: 2200 movs r2, #0
|
|
800062c: 701a strb r2, [r3, #0]
|
|
800062e: e011 b.n 8000654 <main+0x110>
|
|
{
|
|
tx_checksum += tx_buffer[tx_len_counter + 3];
|
|
8000630: 4b55 ldr r3, [pc, #340] @ (8000788 <main+0x244>)
|
|
8000632: 781b ldrb r3, [r3, #0]
|
|
8000634: 3303 adds r3, #3
|
|
8000636: 4a52 ldr r2, [pc, #328] @ (8000780 <main+0x23c>)
|
|
8000638: 5cd3 ldrb r3, [r2, r3]
|
|
800063a: 461a mov r2, r3
|
|
800063c: 4b53 ldr r3, [pc, #332] @ (800078c <main+0x248>)
|
|
800063e: 881b ldrh r3, [r3, #0]
|
|
8000640: 4413 add r3, r2
|
|
8000642: b29a uxth r2, r3
|
|
8000644: 4b51 ldr r3, [pc, #324] @ (800078c <main+0x248>)
|
|
8000646: 801a strh r2, [r3, #0]
|
|
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
|
|
8000648: 4b4f ldr r3, [pc, #316] @ (8000788 <main+0x244>)
|
|
800064a: 781b ldrb r3, [r3, #0]
|
|
800064c: 3301 adds r3, #1
|
|
800064e: b2da uxtb r2, r3
|
|
8000650: 4b4d ldr r3, [pc, #308] @ (8000788 <main+0x244>)
|
|
8000652: 701a strb r2, [r3, #0]
|
|
8000654: 4b4c ldr r3, [pc, #304] @ (8000788 <main+0x244>)
|
|
8000656: 781a ldrb r2, [r3, #0]
|
|
8000658: 4b48 ldr r3, [pc, #288] @ (800077c <main+0x238>)
|
|
800065a: 781b ldrb r3, [r3, #0]
|
|
800065c: 429a cmp r2, r3
|
|
800065e: d3e7 bcc.n 8000630 <main+0xec>
|
|
}
|
|
|
|
tx_checksum = ~tx_checksum;
|
|
8000660: 4b4a ldr r3, [pc, #296] @ (800078c <main+0x248>)
|
|
8000662: 881b ldrh r3, [r3, #0]
|
|
8000664: 43db mvns r3, r3
|
|
8000666: b29a uxth r2, r3
|
|
8000668: 4b48 ldr r3, [pc, #288] @ (800078c <main+0x248>)
|
|
800066a: 801a strh r2, [r3, #0]
|
|
|
|
tx_buffer[7] = (uint8_t)((tx_checksum >> 8) & 0xFF);
|
|
800066c: 4b47 ldr r3, [pc, #284] @ (800078c <main+0x248>)
|
|
800066e: 881b ldrh r3, [r3, #0]
|
|
8000670: 0a1b lsrs r3, r3, #8
|
|
8000672: b29b uxth r3, r3
|
|
8000674: b2da uxtb r2, r3
|
|
8000676: 4b42 ldr r3, [pc, #264] @ (8000780 <main+0x23c>)
|
|
8000678: 71da strb r2, [r3, #7]
|
|
tx_buffer[8] = (uint8_t)(tx_checksum & 0xFF);
|
|
800067a: 4b44 ldr r3, [pc, #272] @ (800078c <main+0x248>)
|
|
800067c: 881b ldrh r3, [r3, #0]
|
|
800067e: b2da uxtb r2, r3
|
|
8000680: 4b3f ldr r3, [pc, #252] @ (8000780 <main+0x23c>)
|
|
8000682: 721a strb r2, [r3, #8]
|
|
|
|
tx_len = 0x13;
|
|
8000684: 4b3d ldr r3, [pc, #244] @ (800077c <main+0x238>)
|
|
8000686: 2213 movs r2, #19
|
|
8000688: 701a strb r2, [r3, #0]
|
|
|
|
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
|
|
800068a: 4b3c ldr r3, [pc, #240] @ (800077c <main+0x238>)
|
|
800068c: 781b ldrb r3, [r3, #0]
|
|
800068e: 461a mov r2, r3
|
|
8000690: 2364 movs r3, #100 @ 0x64
|
|
8000692: 493b ldr r1, [pc, #236] @ (8000780 <main+0x23c>)
|
|
8000694: 4835 ldr r0, [pc, #212] @ (800076c <main+0x228>)
|
|
8000696: f005 fbb5 bl 8005e04 <HAL_UART_Transmit>
|
|
}
|
|
|
|
if (serial_number_flag == 0xff)
|
|
800069a: 4b3d ldr r3, [pc, #244] @ (8000790 <main+0x24c>)
|
|
800069c: 781b ldrb r3, [r3, #0]
|
|
800069e: 2bff cmp r3, #255 @ 0xff
|
|
80006a0: d104 bne.n 80006ac <main+0x168>
|
|
{
|
|
serial_number_flag = 0x00;
|
|
80006a2: 4b3b ldr r3, [pc, #236] @ (8000790 <main+0x24c>)
|
|
80006a4: 2200 movs r2, #0
|
|
80006a6: 701a strb r2, [r3, #0]
|
|
serial_number_task ();
|
|
80006a8: f000 fbce bl 8000e48 <serial_number_task>
|
|
}
|
|
|
|
if (vset_task_flag == 0xff)
|
|
80006ac: 4b39 ldr r3, [pc, #228] @ (8000794 <main+0x250>)
|
|
80006ae: 781b ldrb r3, [r3, #0]
|
|
80006b0: 2bff cmp r3, #255 @ 0xff
|
|
80006b2: d143 bne.n 800073c <main+0x1f8>
|
|
{
|
|
adc_task();
|
|
80006b4: f000 fc60 bl 8000f78 <adc_task>
|
|
|
|
filtered_adc = ADC_Filter_Update(&v_out_filter, vout_adc_val);
|
|
80006b8: 4b37 ldr r3, [pc, #220] @ (8000798 <main+0x254>)
|
|
80006ba: 681b ldr r3, [r3, #0]
|
|
80006bc: 4619 mov r1, r3
|
|
80006be: 482e ldr r0, [pc, #184] @ (8000778 <main+0x234>)
|
|
80006c0: f000 fb0c bl 8000cdc <ADC_Filter_Update>
|
|
80006c4: 4603 mov r3, r0
|
|
80006c6: 4a35 ldr r2, [pc, #212] @ (800079c <main+0x258>)
|
|
80006c8: 6013 str r3, [r2, #0]
|
|
|
|
vout = ((float)filtered_adc / 4095.0f) * vdd_ref;
|
|
80006ca: 4b34 ldr r3, [pc, #208] @ (800079c <main+0x258>)
|
|
80006cc: 681b ldr r3, [r3, #0]
|
|
80006ce: ee07 3a90 vmov s15, r3
|
|
80006d2: eef8 7a67 vcvt.f32.u32 s15, s15
|
|
80006d6: eddf 6a32 vldr s13, [pc, #200] @ 80007a0 <main+0x25c>
|
|
80006da: ee87 7aa6 vdiv.f32 s14, s15, s13
|
|
80006de: 4b24 ldr r3, [pc, #144] @ (8000770 <main+0x22c>)
|
|
80006e0: edd3 7a00 vldr s15, [r3]
|
|
80006e4: ee67 7a27 vmul.f32 s15, s14, s15
|
|
80006e8: 4b2e ldr r3, [pc, #184] @ (80007a4 <main+0x260>)
|
|
80006ea: edc3 7a00 vstr s15, [r3]
|
|
|
|
vout_adj = vout * 10.9f;
|
|
80006ee: 4b2d ldr r3, [pc, #180] @ (80007a4 <main+0x260>)
|
|
80006f0: edd3 7a00 vldr s15, [r3]
|
|
80006f4: ed9f 7a2c vldr s14, [pc, #176] @ 80007a8 <main+0x264>
|
|
80006f8: ee67 7a87 vmul.f32 s15, s15, s14
|
|
80006fc: 4b2b ldr r3, [pc, #172] @ (80007ac <main+0x268>)
|
|
80006fe: edc3 7a00 vstr s15, [r3]
|
|
|
|
vout_adj_uint = (uint32_t)vout_adj;
|
|
8000702: 4b2a ldr r3, [pc, #168] @ (80007ac <main+0x268>)
|
|
8000704: edd3 7a00 vldr s15, [r3]
|
|
8000708: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
800070c: ee17 2a90 vmov r2, s15
|
|
8000710: 4b1c ldr r3, [pc, #112] @ (8000784 <main+0x240>)
|
|
8000712: 601a str r2, [r3, #0]
|
|
|
|
pwm_value_store = update_pwm(vout_adj_uint);
|
|
8000714: 4b1b ldr r3, [pc, #108] @ (8000784 <main+0x240>)
|
|
8000716: 681b ldr r3, [r3, #0]
|
|
8000718: 4618 mov r0, r3
|
|
800071a: f000 fb1d bl 8000d58 <update_pwm>
|
|
800071e: 4603 mov r3, r0
|
|
8000720: 461a mov r2, r3
|
|
8000722: 4b23 ldr r3, [pc, #140] @ (80007b0 <main+0x26c>)
|
|
8000724: 601a str r2, [r3, #0]
|
|
|
|
pwm_value = (uint16_t)pwm_value_store;
|
|
8000726: 4b22 ldr r3, [pc, #136] @ (80007b0 <main+0x26c>)
|
|
8000728: 681b ldr r3, [r3, #0]
|
|
800072a: b29a uxth r2, r3
|
|
800072c: 4b0d ldr r3, [pc, #52] @ (8000764 <main+0x220>)
|
|
800072e: 801a strh r2, [r3, #0]
|
|
|
|
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, pwm_value);
|
|
8000730: 4b0c ldr r3, [pc, #48] @ (8000764 <main+0x220>)
|
|
8000732: 881a ldrh r2, [r3, #0]
|
|
8000734: 4b0f ldr r3, [pc, #60] @ (8000774 <main+0x230>)
|
|
8000736: 681b ldr r3, [r3, #0]
|
|
8000738: 635a str r2, [r3, #52] @ 0x34
|
|
800073a: e74a b.n 80005d2 <main+0x8e>
|
|
}
|
|
|
|
|
|
else
|
|
{
|
|
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
|
|
800073c: 4b0d ldr r3, [pc, #52] @ (8000774 <main+0x230>)
|
|
800073e: 681b ldr r3, [r3, #0]
|
|
8000740: 2200 movs r2, #0
|
|
8000742: 635a str r2, [r3, #52] @ 0x34
|
|
if (adc_task_flag == 0xff)
|
|
8000744: e745 b.n 80005d2 <main+0x8e>
|
|
8000746: bf00 nop
|
|
8000748: 48000400 .word 0x48000400
|
|
800074c: 20000044 .word 0x20000044
|
|
8000750: 200000b0 .word 0x200000b0
|
|
8000754: 20000292 .word 0x20000292
|
|
8000758: 20000293 .word 0x20000293
|
|
800075c: 20000294 .word 0x20000294
|
|
8000760: 200002a0 .word 0x200002a0
|
|
8000764: 200002ae .word 0x200002ae
|
|
8000768: 2000024c .word 0x2000024c
|
|
800076c: 200001b4 .word 0x200001b4
|
|
8000770: 200002a4 .word 0x200002a4
|
|
8000774: 20000168 .word 0x20000168
|
|
8000778: 200002d0 .word 0x200002d0
|
|
800077c: 20000290 .word 0x20000290
|
|
8000780: 20000270 .word 0x20000270
|
|
8000784: 200002c4 .word 0x200002c4
|
|
8000788: 20000291 .word 0x20000291
|
|
800078c: 20000298 .word 0x20000298
|
|
8000790: 200002ad .word 0x200002ad
|
|
8000794: 200002ac .word 0x200002ac
|
|
8000798: 200002b4 .word 0x200002b4
|
|
800079c: 200002b8 .word 0x200002b8
|
|
80007a0: 457ff000 .word 0x457ff000
|
|
80007a4: 200002bc .word 0x200002bc
|
|
80007a8: 412e6666 .word 0x412e6666
|
|
80007ac: 200002c0 .word 0x200002c0
|
|
80007b0: 200002b0 .word 0x200002b0
|
|
|
|
080007b4 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
80007b4: b580 push {r7, lr}
|
|
80007b6: b094 sub sp, #80 @ 0x50
|
|
80007b8: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
80007ba: f107 0318 add.w r3, r7, #24
|
|
80007be: 2238 movs r2, #56 @ 0x38
|
|
80007c0: 2100 movs r1, #0
|
|
80007c2: 4618 mov r0, r3
|
|
80007c4: f007 fbde bl 8007f84 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80007c8: 1d3b adds r3, r7, #4
|
|
80007ca: 2200 movs r2, #0
|
|
80007cc: 601a str r2, [r3, #0]
|
|
80007ce: 605a str r2, [r3, #4]
|
|
80007d0: 609a str r2, [r3, #8]
|
|
80007d2: 60da str r2, [r3, #12]
|
|
80007d4: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
80007d6: f44f 7000 mov.w r0, #512 @ 0x200
|
|
80007da: f003 f801 bl 80037e0 <HAL_PWREx_ControlVoltageScaling>
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
80007de: 2302 movs r3, #2
|
|
80007e0: 61bb str r3, [r7, #24]
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80007e2: f44f 7380 mov.w r3, #256 @ 0x100
|
|
80007e6: 627b str r3, [r7, #36] @ 0x24
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
80007e8: 2340 movs r3, #64 @ 0x40
|
|
80007ea: 62bb str r3, [r7, #40] @ 0x28
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80007ec: 2302 movs r3, #2
|
|
80007ee: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
|
80007f0: 2302 movs r3, #2
|
|
80007f2: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
|
|
80007f4: 2301 movs r3, #1
|
|
80007f6: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLN = 16;
|
|
80007f8: 2310 movs r3, #16
|
|
80007fa: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
80007fc: 2302 movs r3, #2
|
|
80007fe: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
8000800: 2302 movs r3, #2
|
|
8000802: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
8000804: 2302 movs r3, #2
|
|
8000806: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000808: f107 0318 add.w r3, r7, #24
|
|
800080c: 4618 mov r0, r3
|
|
800080e: f003 f89b bl 8003948 <HAL_RCC_OscConfig>
|
|
8000812: 4603 mov r3, r0
|
|
8000814: 2b00 cmp r3, #0
|
|
8000816: d001 beq.n 800081c <SystemClock_Config+0x68>
|
|
{
|
|
Error_Handler();
|
|
8000818: f000 fd44 bl 80012a4 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
800081c: 230f movs r3, #15
|
|
800081e: 607b str r3, [r7, #4]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8000820: 2303 movs r3, #3
|
|
8000822: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8000824: 2300 movs r3, #0
|
|
8000826: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8000828: 2300 movs r3, #0
|
|
800082a: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
800082c: 2300 movs r3, #0
|
|
800082e: 617b str r3, [r7, #20]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
8000830: 1d3b adds r3, r7, #4
|
|
8000832: 2104 movs r1, #4
|
|
8000834: 4618 mov r0, r3
|
|
8000836: f003 fb99 bl 8003f6c <HAL_RCC_ClockConfig>
|
|
800083a: 4603 mov r3, r0
|
|
800083c: 2b00 cmp r3, #0
|
|
800083e: d001 beq.n 8000844 <SystemClock_Config+0x90>
|
|
{
|
|
Error_Handler();
|
|
8000840: f000 fd30 bl 80012a4 <Error_Handler>
|
|
}
|
|
}
|
|
8000844: bf00 nop
|
|
8000846: 3750 adds r7, #80 @ 0x50
|
|
8000848: 46bd mov sp, r7
|
|
800084a: bd80 pop {r7, pc}
|
|
|
|
0800084c <MX_ADC1_Init>:
|
|
* @brief ADC1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC1_Init(void)
|
|
{
|
|
800084c: b580 push {r7, lr}
|
|
800084e: b08c sub sp, #48 @ 0x30
|
|
8000850: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC1_Init 0 */
|
|
|
|
/* USER CODE END ADC1_Init 0 */
|
|
|
|
ADC_MultiModeTypeDef multimode = {0};
|
|
8000852: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000856: 2200 movs r2, #0
|
|
8000858: 601a str r2, [r3, #0]
|
|
800085a: 605a str r2, [r3, #4]
|
|
800085c: 609a str r2, [r3, #8]
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
800085e: 1d3b adds r3, r7, #4
|
|
8000860: 2220 movs r2, #32
|
|
8000862: 2100 movs r1, #0
|
|
8000864: 4618 mov r0, r3
|
|
8000866: f007 fb8d bl 8007f84 <memset>
|
|
|
|
/* USER CODE END ADC1_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc1.Instance = ADC1;
|
|
800086a: 4b32 ldr r3, [pc, #200] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
800086c: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000
|
|
8000870: 601a str r2, [r3, #0]
|
|
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
|
|
8000872: 4b30 ldr r3, [pc, #192] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
8000874: f44f 1200 mov.w r2, #2097152 @ 0x200000
|
|
8000878: 605a str r2, [r3, #4]
|
|
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
|
|
800087a: 4b2e ldr r3, [pc, #184] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
800087c: 2200 movs r2, #0
|
|
800087e: 609a str r2, [r3, #8]
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8000880: 4b2c ldr r3, [pc, #176] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
8000882: 2200 movs r2, #0
|
|
8000884: 60da str r2, [r3, #12]
|
|
hadc1.Init.GainCompensation = 0;
|
|
8000886: 4b2b ldr r3, [pc, #172] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
8000888: 2200 movs r2, #0
|
|
800088a: 611a str r2, [r3, #16]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
800088c: 4b29 ldr r3, [pc, #164] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
800088e: 2200 movs r2, #0
|
|
8000890: 615a str r2, [r3, #20]
|
|
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
|
|
8000892: 4b28 ldr r3, [pc, #160] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
8000894: 2204 movs r2, #4
|
|
8000896: 619a str r2, [r3, #24]
|
|
hadc1.Init.LowPowerAutoWait = DISABLE;
|
|
8000898: 4b26 ldr r3, [pc, #152] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
800089a: 2200 movs r2, #0
|
|
800089c: 771a strb r2, [r3, #28]
|
|
hadc1.Init.ContinuousConvMode = DISABLE;
|
|
800089e: 4b25 ldr r3, [pc, #148] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008a0: 2200 movs r2, #0
|
|
80008a2: 775a strb r2, [r3, #29]
|
|
hadc1.Init.NbrOfConversion = 1;
|
|
80008a4: 4b23 ldr r3, [pc, #140] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008a6: 2201 movs r2, #1
|
|
80008a8: 621a str r2, [r3, #32]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
80008aa: 4b22 ldr r3, [pc, #136] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008ac: 2200 movs r2, #0
|
|
80008ae: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
80008b2: 4b20 ldr r3, [pc, #128] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008b4: 2200 movs r2, #0
|
|
80008b6: 62da str r2, [r3, #44] @ 0x2c
|
|
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
80008b8: 4b1e ldr r3, [pc, #120] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008ba: 2200 movs r2, #0
|
|
80008bc: 631a str r2, [r3, #48] @ 0x30
|
|
hadc1.Init.DMAContinuousRequests = DISABLE;
|
|
80008be: 4b1d ldr r3, [pc, #116] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008c0: 2200 movs r2, #0
|
|
80008c2: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
|
|
80008c6: 4b1b ldr r3, [pc, #108] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008c8: 2200 movs r2, #0
|
|
80008ca: 63da str r2, [r3, #60] @ 0x3c
|
|
hadc1.Init.OversamplingMode = DISABLE;
|
|
80008cc: 4b19 ldr r3, [pc, #100] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008ce: 2200 movs r2, #0
|
|
80008d0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
80008d4: 4817 ldr r0, [pc, #92] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008d6: f001 f9d5 bl 8001c84 <HAL_ADC_Init>
|
|
80008da: 4603 mov r3, r0
|
|
80008dc: 2b00 cmp r3, #0
|
|
80008de: d001 beq.n 80008e4 <MX_ADC1_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
80008e0: f000 fce0 bl 80012a4 <Error_Handler>
|
|
}
|
|
|
|
/** Configure the ADC multi-mode
|
|
*/
|
|
multimode.Mode = ADC_MODE_INDEPENDENT;
|
|
80008e4: 2300 movs r3, #0
|
|
80008e6: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
|
|
80008e8: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
80008ec: 4619 mov r1, r3
|
|
80008ee: 4811 ldr r0, [pc, #68] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
80008f0: f002 fb68 bl 8002fc4 <HAL_ADCEx_MultiModeConfigChannel>
|
|
80008f4: 4603 mov r3, r0
|
|
80008f6: 2b00 cmp r3, #0
|
|
80008f8: d001 beq.n 80008fe <MX_ADC1_Init+0xb2>
|
|
{
|
|
Error_Handler();
|
|
80008fa: f000 fcd3 bl 80012a4 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_VREFINT;
|
|
80008fe: 4b0e ldr r3, [pc, #56] @ (8000938 <MX_ADC1_Init+0xec>)
|
|
8000900: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
8000902: 2306 movs r3, #6
|
|
8000904: 60bb str r3, [r7, #8]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
|
|
8000906: 2307 movs r3, #7
|
|
8000908: 60fb str r3, [r7, #12]
|
|
sConfig.SingleDiff = ADC_SINGLE_ENDED;
|
|
800090a: 237f movs r3, #127 @ 0x7f
|
|
800090c: 613b str r3, [r7, #16]
|
|
sConfig.OffsetNumber = ADC_OFFSET_NONE;
|
|
800090e: 2304 movs r3, #4
|
|
8000910: 617b str r3, [r7, #20]
|
|
sConfig.Offset = 0;
|
|
8000912: 2300 movs r3, #0
|
|
8000914: 61bb str r3, [r7, #24]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8000916: 1d3b adds r3, r7, #4
|
|
8000918: 4619 mov r1, r3
|
|
800091a: 4806 ldr r0, [pc, #24] @ (8000934 <MX_ADC1_Init+0xe8>)
|
|
800091c: f001 fd0c bl 8002338 <HAL_ADC_ConfigChannel>
|
|
8000920: 4603 mov r3, r0
|
|
8000922: 2b00 cmp r3, #0
|
|
8000924: d001 beq.n 800092a <MX_ADC1_Init+0xde>
|
|
{
|
|
Error_Handler();
|
|
8000926: f000 fcbd bl 80012a4 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC1_Init 2 */
|
|
|
|
/* USER CODE END ADC1_Init 2 */
|
|
|
|
}
|
|
800092a: bf00 nop
|
|
800092c: 3730 adds r7, #48 @ 0x30
|
|
800092e: 46bd mov sp, r7
|
|
8000930: bd80 pop {r7, pc}
|
|
8000932: bf00 nop
|
|
8000934: 20000044 .word 0x20000044
|
|
8000938: cb840000 .word 0xcb840000
|
|
|
|
0800093c <MX_ADC2_Init>:
|
|
* @brief ADC2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC2_Init(void)
|
|
{
|
|
800093c: b580 push {r7, lr}
|
|
800093e: b088 sub sp, #32
|
|
8000940: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC2_Init 0 */
|
|
|
|
/* USER CODE END ADC2_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8000942: 463b mov r3, r7
|
|
8000944: 2220 movs r2, #32
|
|
8000946: 2100 movs r1, #0
|
|
8000948: 4618 mov r0, r3
|
|
800094a: f007 fb1b bl 8007f84 <memset>
|
|
|
|
/* USER CODE END ADC2_Init 1 */
|
|
|
|
/** Common config
|
|
*/
|
|
hadc2.Instance = ADC2;
|
|
800094e: 4b2b ldr r3, [pc, #172] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000950: 4a2b ldr r2, [pc, #172] @ (8000a00 <MX_ADC2_Init+0xc4>)
|
|
8000952: 601a str r2, [r3, #0]
|
|
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
|
|
8000954: 4b29 ldr r3, [pc, #164] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000956: f44f 1200 mov.w r2, #2097152 @ 0x200000
|
|
800095a: 605a str r2, [r3, #4]
|
|
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
|
|
800095c: 4b27 ldr r3, [pc, #156] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
800095e: 2200 movs r2, #0
|
|
8000960: 609a str r2, [r3, #8]
|
|
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8000962: 4b26 ldr r3, [pc, #152] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000964: 2200 movs r2, #0
|
|
8000966: 60da str r2, [r3, #12]
|
|
hadc2.Init.GainCompensation = 0;
|
|
8000968: 4b24 ldr r3, [pc, #144] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
800096a: 2200 movs r2, #0
|
|
800096c: 611a str r2, [r3, #16]
|
|
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
800096e: 4b23 ldr r3, [pc, #140] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000970: 2200 movs r2, #0
|
|
8000972: 615a str r2, [r3, #20]
|
|
hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
|
|
8000974: 4b21 ldr r3, [pc, #132] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000976: 2204 movs r2, #4
|
|
8000978: 619a str r2, [r3, #24]
|
|
hadc2.Init.LowPowerAutoWait = DISABLE;
|
|
800097a: 4b20 ldr r3, [pc, #128] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
800097c: 2200 movs r2, #0
|
|
800097e: 771a strb r2, [r3, #28]
|
|
hadc2.Init.ContinuousConvMode = DISABLE;
|
|
8000980: 4b1e ldr r3, [pc, #120] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000982: 2200 movs r2, #0
|
|
8000984: 775a strb r2, [r3, #29]
|
|
hadc2.Init.NbrOfConversion = 1;
|
|
8000986: 4b1d ldr r3, [pc, #116] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000988: 2201 movs r2, #1
|
|
800098a: 621a str r2, [r3, #32]
|
|
hadc2.Init.DiscontinuousConvMode = DISABLE;
|
|
800098c: 4b1b ldr r3, [pc, #108] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
800098e: 2200 movs r2, #0
|
|
8000990: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
8000994: 4b19 ldr r3, [pc, #100] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
8000996: 2200 movs r2, #0
|
|
8000998: 62da str r2, [r3, #44] @ 0x2c
|
|
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
800099a: 4b18 ldr r3, [pc, #96] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
800099c: 2200 movs r2, #0
|
|
800099e: 631a str r2, [r3, #48] @ 0x30
|
|
hadc2.Init.DMAContinuousRequests = DISABLE;
|
|
80009a0: 4b16 ldr r3, [pc, #88] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
80009a2: 2200 movs r2, #0
|
|
80009a4: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
|
|
80009a8: 4b14 ldr r3, [pc, #80] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
80009aa: 2200 movs r2, #0
|
|
80009ac: 63da str r2, [r3, #60] @ 0x3c
|
|
hadc2.Init.OversamplingMode = DISABLE;
|
|
80009ae: 4b13 ldr r3, [pc, #76] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
80009b0: 2200 movs r2, #0
|
|
80009b2: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
if (HAL_ADC_Init(&hadc2) != HAL_OK)
|
|
80009b6: 4811 ldr r0, [pc, #68] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
80009b8: f001 f964 bl 8001c84 <HAL_ADC_Init>
|
|
80009bc: 4603 mov r3, r0
|
|
80009be: 2b00 cmp r3, #0
|
|
80009c0: d001 beq.n 80009c6 <MX_ADC2_Init+0x8a>
|
|
{
|
|
Error_Handler();
|
|
80009c2: f000 fc6f bl 80012a4 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_3;
|
|
80009c6: 4b0f ldr r3, [pc, #60] @ (8000a04 <MX_ADC2_Init+0xc8>)
|
|
80009c8: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
80009ca: 2306 movs r3, #6
|
|
80009cc: 607b str r3, [r7, #4]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
|
|
80009ce: 2307 movs r3, #7
|
|
80009d0: 60bb str r3, [r7, #8]
|
|
sConfig.SingleDiff = ADC_SINGLE_ENDED;
|
|
80009d2: 237f movs r3, #127 @ 0x7f
|
|
80009d4: 60fb str r3, [r7, #12]
|
|
sConfig.OffsetNumber = ADC_OFFSET_NONE;
|
|
80009d6: 2304 movs r3, #4
|
|
80009d8: 613b str r3, [r7, #16]
|
|
sConfig.Offset = 0;
|
|
80009da: 2300 movs r3, #0
|
|
80009dc: 617b str r3, [r7, #20]
|
|
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
|
80009de: 463b mov r3, r7
|
|
80009e0: 4619 mov r1, r3
|
|
80009e2: 4806 ldr r0, [pc, #24] @ (80009fc <MX_ADC2_Init+0xc0>)
|
|
80009e4: f001 fca8 bl 8002338 <HAL_ADC_ConfigChannel>
|
|
80009e8: 4603 mov r3, r0
|
|
80009ea: 2b00 cmp r3, #0
|
|
80009ec: d001 beq.n 80009f2 <MX_ADC2_Init+0xb6>
|
|
{
|
|
Error_Handler();
|
|
80009ee: f000 fc59 bl 80012a4 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC2_Init 2 */
|
|
|
|
/* USER CODE END ADC2_Init 2 */
|
|
|
|
}
|
|
80009f2: bf00 nop
|
|
80009f4: 3720 adds r7, #32
|
|
80009f6: 46bd mov sp, r7
|
|
80009f8: bd80 pop {r7, pc}
|
|
80009fa: bf00 nop
|
|
80009fc: 200000b0 .word 0x200000b0
|
|
8000a00: 50000100 .word 0x50000100
|
|
8000a04: 0c900008 .word 0x0c900008
|
|
|
|
08000a08 <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
8000a08: b580 push {r7, lr}
|
|
8000a0a: b088 sub sp, #32
|
|
8000a0c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
8000a0e: f107 0310 add.w r3, r7, #16
|
|
8000a12: 2200 movs r2, #0
|
|
8000a14: 601a str r2, [r3, #0]
|
|
8000a16: 605a str r2, [r3, #4]
|
|
8000a18: 609a str r2, [r3, #8]
|
|
8000a1a: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8000a1c: 1d3b adds r3, r7, #4
|
|
8000a1e: 2200 movs r2, #0
|
|
8000a20: 601a str r2, [r3, #0]
|
|
8000a22: 605a str r2, [r3, #4]
|
|
8000a24: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
8000a26: 4b1e ldr r3, [pc, #120] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a28: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
|
|
8000a2c: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 12800-1;
|
|
8000a2e: 4b1c ldr r3, [pc, #112] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a30: f243 12ff movw r2, #12799 @ 0x31ff
|
|
8000a34: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000a36: 4b1a ldr r3, [pc, #104] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a38: 2200 movs r2, #0
|
|
8000a3a: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 99;
|
|
8000a3c: 4b18 ldr r3, [pc, #96] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a3e: 2263 movs r2, #99 @ 0x63
|
|
8000a40: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000a42: 4b17 ldr r3, [pc, #92] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a44: 2200 movs r2, #0
|
|
8000a46: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000a48: 4b15 ldr r3, [pc, #84] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a4a: 2200 movs r2, #0
|
|
8000a4c: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
|
|
8000a4e: 4814 ldr r0, [pc, #80] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a50: f003 fe98 bl 8004784 <HAL_TIM_Base_Init>
|
|
8000a54: 4603 mov r3, r0
|
|
8000a56: 2b00 cmp r3, #0
|
|
8000a58: d001 beq.n 8000a5e <MX_TIM2_Init+0x56>
|
|
{
|
|
Error_Handler();
|
|
8000a5a: f000 fc23 bl 80012a4 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8000a5e: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000a62: 613b str r3, [r7, #16]
|
|
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
|
|
8000a64: f107 0310 add.w r3, r7, #16
|
|
8000a68: 4619 mov r1, r3
|
|
8000a6a: 480d ldr r0, [pc, #52] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a6c: f004 faa6 bl 8004fbc <HAL_TIM_ConfigClockSource>
|
|
8000a70: 4603 mov r3, r0
|
|
8000a72: 2b00 cmp r3, #0
|
|
8000a74: d001 beq.n 8000a7a <MX_TIM2_Init+0x72>
|
|
{
|
|
Error_Handler();
|
|
8000a76: f000 fc15 bl 80012a4 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8000a7a: 2300 movs r3, #0
|
|
8000a7c: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8000a7e: 2300 movs r3, #0
|
|
8000a80: 60fb str r3, [r7, #12]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
8000a82: 1d3b adds r3, r7, #4
|
|
8000a84: 4619 mov r1, r3
|
|
8000a86: 4806 ldr r0, [pc, #24] @ (8000aa0 <MX_TIM2_Init+0x98>)
|
|
8000a88: f005 f818 bl 8005abc <HAL_TIMEx_MasterConfigSynchronization>
|
|
8000a8c: 4603 mov r3, r0
|
|
8000a8e: 2b00 cmp r3, #0
|
|
8000a90: d001 beq.n 8000a96 <MX_TIM2_Init+0x8e>
|
|
{
|
|
Error_Handler();
|
|
8000a92: f000 fc07 bl 80012a4 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
|
|
}
|
|
8000a96: bf00 nop
|
|
8000a98: 3720 adds r7, #32
|
|
8000a9a: 46bd mov sp, r7
|
|
8000a9c: bd80 pop {r7, pc}
|
|
8000a9e: bf00 nop
|
|
8000aa0: 2000011c .word 0x2000011c
|
|
|
|
08000aa4 <MX_TIM16_Init>:
|
|
* @brief TIM16 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM16_Init(void)
|
|
{
|
|
8000aa4: b580 push {r7, lr}
|
|
8000aa6: b094 sub sp, #80 @ 0x50
|
|
8000aa8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM16_Init 0 */
|
|
|
|
/* USER CODE END TIM16_Init 0 */
|
|
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8000aaa: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000aae: 2200 movs r2, #0
|
|
8000ab0: 601a str r2, [r3, #0]
|
|
8000ab2: 605a str r2, [r3, #4]
|
|
8000ab4: 609a str r2, [r3, #8]
|
|
8000ab6: 60da str r2, [r3, #12]
|
|
8000ab8: 611a str r2, [r3, #16]
|
|
8000aba: 615a str r2, [r3, #20]
|
|
8000abc: 619a str r2, [r3, #24]
|
|
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
|
|
8000abe: 463b mov r3, r7
|
|
8000ac0: 2234 movs r2, #52 @ 0x34
|
|
8000ac2: 2100 movs r1, #0
|
|
8000ac4: 4618 mov r0, r3
|
|
8000ac6: f007 fa5d bl 8007f84 <memset>
|
|
|
|
/* USER CODE BEGIN TIM16_Init 1 */
|
|
|
|
/* USER CODE END TIM16_Init 1 */
|
|
htim16.Instance = TIM16;
|
|
8000aca: 4b31 ldr r3, [pc, #196] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000acc: 4a31 ldr r2, [pc, #196] @ (8000b94 <MX_TIM16_Init+0xf0>)
|
|
8000ace: 601a str r2, [r3, #0]
|
|
htim16.Init.Prescaler = 1;
|
|
8000ad0: 4b2f ldr r3, [pc, #188] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000ad2: 2201 movs r2, #1
|
|
8000ad4: 605a str r2, [r3, #4]
|
|
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000ad6: 4b2e ldr r3, [pc, #184] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000ad8: 2200 movs r2, #0
|
|
8000ada: 609a str r2, [r3, #8]
|
|
htim16.Init.Period = 63999;
|
|
8000adc: 4b2c ldr r3, [pc, #176] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000ade: f64f 12ff movw r2, #63999 @ 0xf9ff
|
|
8000ae2: 60da str r2, [r3, #12]
|
|
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8000ae4: 4b2a ldr r3, [pc, #168] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000ae6: 2200 movs r2, #0
|
|
8000ae8: 611a str r2, [r3, #16]
|
|
htim16.Init.RepetitionCounter = 0;
|
|
8000aea: 4b29 ldr r3, [pc, #164] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000aec: 2200 movs r2, #0
|
|
8000aee: 615a str r2, [r3, #20]
|
|
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8000af0: 4b27 ldr r3, [pc, #156] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000af2: 2200 movs r2, #0
|
|
8000af4: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
|
|
8000af6: 4826 ldr r0, [pc, #152] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000af8: f003 fe44 bl 8004784 <HAL_TIM_Base_Init>
|
|
8000afc: 4603 mov r3, r0
|
|
8000afe: 2b00 cmp r3, #0
|
|
8000b00: d001 beq.n 8000b06 <MX_TIM16_Init+0x62>
|
|
{
|
|
Error_Handler();
|
|
8000b02: f000 fbcf bl 80012a4 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim16) != HAL_OK)
|
|
8000b06: 4822 ldr r0, [pc, #136] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000b08: f003 fe93 bl 8004832 <HAL_TIM_PWM_Init>
|
|
8000b0c: 4603 mov r3, r0
|
|
8000b0e: 2b00 cmp r3, #0
|
|
8000b10: d001 beq.n 8000b16 <MX_TIM16_Init+0x72>
|
|
{
|
|
Error_Handler();
|
|
8000b12: f000 fbc7 bl 80012a4 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
8000b16: 2360 movs r3, #96 @ 0x60
|
|
8000b18: 637b str r3, [r7, #52] @ 0x34
|
|
sConfigOC.Pulse = 0;
|
|
8000b1a: 2300 movs r3, #0
|
|
8000b1c: 63bb str r3, [r7, #56] @ 0x38
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
8000b1e: 2300 movs r3, #0
|
|
8000b20: 63fb str r3, [r7, #60] @ 0x3c
|
|
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
|
8000b22: 2300 movs r3, #0
|
|
8000b24: 643b str r3, [r7, #64] @ 0x40
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8000b26: 2300 movs r3, #0
|
|
8000b28: 647b str r3, [r7, #68] @ 0x44
|
|
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
|
|
8000b2a: 2300 movs r3, #0
|
|
8000b2c: 64bb str r3, [r7, #72] @ 0x48
|
|
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
|
8000b2e: 2300 movs r3, #0
|
|
8000b30: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim16, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8000b32: f107 0334 add.w r3, r7, #52 @ 0x34
|
|
8000b36: 2200 movs r2, #0
|
|
8000b38: 4619 mov r1, r3
|
|
8000b3a: 4815 ldr r0, [pc, #84] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000b3c: f004 f92a bl 8004d94 <HAL_TIM_PWM_ConfigChannel>
|
|
8000b40: 4603 mov r3, r0
|
|
8000b42: 2b00 cmp r3, #0
|
|
8000b44: d001 beq.n 8000b4a <MX_TIM16_Init+0xa6>
|
|
{
|
|
Error_Handler();
|
|
8000b46: f000 fbad bl 80012a4 <Error_Handler>
|
|
}
|
|
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
|
|
8000b4a: 2300 movs r3, #0
|
|
8000b4c: 603b str r3, [r7, #0]
|
|
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
|
|
8000b4e: 2300 movs r3, #0
|
|
8000b50: 607b str r3, [r7, #4]
|
|
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
|
|
8000b52: 2300 movs r3, #0
|
|
8000b54: 60bb str r3, [r7, #8]
|
|
sBreakDeadTimeConfig.DeadTime = 0;
|
|
8000b56: 2300 movs r3, #0
|
|
8000b58: 60fb str r3, [r7, #12]
|
|
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
|
|
8000b5a: 2300 movs r3, #0
|
|
8000b5c: 613b str r3, [r7, #16]
|
|
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
|
|
8000b5e: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
8000b62: 617b str r3, [r7, #20]
|
|
sBreakDeadTimeConfig.BreakFilter = 0;
|
|
8000b64: 2300 movs r3, #0
|
|
8000b66: 61bb str r3, [r7, #24]
|
|
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
|
|
8000b68: 2300 movs r3, #0
|
|
8000b6a: 633b str r3, [r7, #48] @ 0x30
|
|
if (HAL_TIMEx_ConfigBreakDeadTime(&htim16, &sBreakDeadTimeConfig) != HAL_OK)
|
|
8000b6c: 463b mov r3, r7
|
|
8000b6e: 4619 mov r1, r3
|
|
8000b70: 4807 ldr r0, [pc, #28] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000b72: f005 f825 bl 8005bc0 <HAL_TIMEx_ConfigBreakDeadTime>
|
|
8000b76: 4603 mov r3, r0
|
|
8000b78: 2b00 cmp r3, #0
|
|
8000b7a: d001 beq.n 8000b80 <MX_TIM16_Init+0xdc>
|
|
{
|
|
Error_Handler();
|
|
8000b7c: f000 fb92 bl 80012a4 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM16_Init 2 */
|
|
|
|
/* USER CODE END TIM16_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim16);
|
|
8000b80: 4803 ldr r0, [pc, #12] @ (8000b90 <MX_TIM16_Init+0xec>)
|
|
8000b82: f000 fc7d bl 8001480 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8000b86: bf00 nop
|
|
8000b88: 3750 adds r7, #80 @ 0x50
|
|
8000b8a: 46bd mov sp, r7
|
|
8000b8c: bd80 pop {r7, pc}
|
|
8000b8e: bf00 nop
|
|
8000b90: 20000168 .word 0x20000168
|
|
8000b94: 40014400 .word 0x40014400
|
|
|
|
08000b98 <MX_USART2_UART_Init>:
|
|
* @brief USART2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART2_UART_Init(void)
|
|
{
|
|
8000b98: b580 push {r7, lr}
|
|
8000b9a: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
8000b9c: 4b22 ldr r3, [pc, #136] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000b9e: 4a23 ldr r2, [pc, #140] @ (8000c2c <MX_USART2_UART_Init+0x94>)
|
|
8000ba0: 601a str r2, [r3, #0]
|
|
huart2.Init.BaudRate = 115200;
|
|
8000ba2: 4b21 ldr r3, [pc, #132] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000ba4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000ba8: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000baa: 4b1f ldr r3, [pc, #124] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bac: 2200 movs r2, #0
|
|
8000bae: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
8000bb0: 4b1d ldr r3, [pc, #116] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bb2: 2200 movs r2, #0
|
|
8000bb4: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
8000bb6: 4b1c ldr r3, [pc, #112] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bb8: 2200 movs r2, #0
|
|
8000bba: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8000bbc: 4b1a ldr r3, [pc, #104] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bbe: 220c movs r2, #12
|
|
8000bc0: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000bc2: 4b19 ldr r3, [pc, #100] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bc4: 2200 movs r2, #0
|
|
8000bc6: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000bc8: 4b17 ldr r3, [pc, #92] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bca: 2200 movs r2, #0
|
|
8000bcc: 61da str r2, [r3, #28]
|
|
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8000bce: 4b16 ldr r3, [pc, #88] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bd0: 2200 movs r2, #0
|
|
8000bd2: 621a str r2, [r3, #32]
|
|
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
|
8000bd4: 4b14 ldr r3, [pc, #80] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bd6: 2200 movs r2, #0
|
|
8000bd8: 625a str r2, [r3, #36] @ 0x24
|
|
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8000bda: 4b13 ldr r3, [pc, #76] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bdc: 2200 movs r2, #0
|
|
8000bde: 629a str r2, [r3, #40] @ 0x28
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
8000be0: 4811 ldr r0, [pc, #68] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000be2: f005 f8bf bl 8005d64 <HAL_UART_Init>
|
|
8000be6: 4603 mov r3, r0
|
|
8000be8: 2b00 cmp r3, #0
|
|
8000bea: d001 beq.n 8000bf0 <MX_USART2_UART_Init+0x58>
|
|
{
|
|
Error_Handler();
|
|
8000bec: f000 fb5a bl 80012a4 <Error_Handler>
|
|
}
|
|
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
|
8000bf0: 2100 movs r1, #0
|
|
8000bf2: 480d ldr r0, [pc, #52] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000bf4: f007 f8fb bl 8007dee <HAL_UARTEx_SetTxFifoThreshold>
|
|
8000bf8: 4603 mov r3, r0
|
|
8000bfa: 2b00 cmp r3, #0
|
|
8000bfc: d001 beq.n 8000c02 <MX_USART2_UART_Init+0x6a>
|
|
{
|
|
Error_Handler();
|
|
8000bfe: f000 fb51 bl 80012a4 <Error_Handler>
|
|
}
|
|
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
|
8000c02: 2100 movs r1, #0
|
|
8000c04: 4808 ldr r0, [pc, #32] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000c06: f007 f930 bl 8007e6a <HAL_UARTEx_SetRxFifoThreshold>
|
|
8000c0a: 4603 mov r3, r0
|
|
8000c0c: 2b00 cmp r3, #0
|
|
8000c0e: d001 beq.n 8000c14 <MX_USART2_UART_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
8000c10: f000 fb48 bl 80012a4 <Error_Handler>
|
|
}
|
|
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
|
|
8000c14: 4804 ldr r0, [pc, #16] @ (8000c28 <MX_USART2_UART_Init+0x90>)
|
|
8000c16: f007 f8b1 bl 8007d7c <HAL_UARTEx_DisableFifoMode>
|
|
8000c1a: 4603 mov r3, r0
|
|
8000c1c: 2b00 cmp r3, #0
|
|
8000c1e: d001 beq.n 8000c24 <MX_USART2_UART_Init+0x8c>
|
|
{
|
|
Error_Handler();
|
|
8000c20: f000 fb40 bl 80012a4 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
8000c24: bf00 nop
|
|
8000c26: bd80 pop {r7, pc}
|
|
8000c28: 200001b4 .word 0x200001b4
|
|
8000c2c: 40004400 .word 0x40004400
|
|
|
|
08000c30 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000c30: b580 push {r7, lr}
|
|
8000c32: b088 sub sp, #32
|
|
8000c34: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000c36: f107 030c add.w r3, r7, #12
|
|
8000c3a: 2200 movs r2, #0
|
|
8000c3c: 601a str r2, [r3, #0]
|
|
8000c3e: 605a str r2, [r3, #4]
|
|
8000c40: 609a str r2, [r3, #8]
|
|
8000c42: 60da str r2, [r3, #12]
|
|
8000c44: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000c46: 4b18 ldr r3, [pc, #96] @ (8000ca8 <MX_GPIO_Init+0x78>)
|
|
8000c48: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8000c4a: 4a17 ldr r2, [pc, #92] @ (8000ca8 <MX_GPIO_Init+0x78>)
|
|
8000c4c: f043 0301 orr.w r3, r3, #1
|
|
8000c50: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8000c52: 4b15 ldr r3, [pc, #84] @ (8000ca8 <MX_GPIO_Init+0x78>)
|
|
8000c54: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8000c56: f003 0301 and.w r3, r3, #1
|
|
8000c5a: 60bb str r3, [r7, #8]
|
|
8000c5c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000c5e: 4b12 ldr r3, [pc, #72] @ (8000ca8 <MX_GPIO_Init+0x78>)
|
|
8000c60: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8000c62: 4a11 ldr r2, [pc, #68] @ (8000ca8 <MX_GPIO_Init+0x78>)
|
|
8000c64: f043 0302 orr.w r3, r3, #2
|
|
8000c68: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8000c6a: 4b0f ldr r3, [pc, #60] @ (8000ca8 <MX_GPIO_Init+0x78>)
|
|
8000c6c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8000c6e: f003 0302 and.w r3, r3, #2
|
|
8000c72: 607b str r3, [r7, #4]
|
|
8000c74: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
|
|
8000c76: 2200 movs r2, #0
|
|
8000c78: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000c7c: 480b ldr r0, [pc, #44] @ (8000cac <MX_GPIO_Init+0x7c>)
|
|
8000c7e: f002 fd97 bl 80037b0 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : LD2_Pin */
|
|
GPIO_InitStruct.Pin = LD2_Pin;
|
|
8000c82: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000c86: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c88: 2301 movs r3, #1
|
|
8000c8a: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c8c: 2300 movs r3, #0
|
|
8000c8e: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c90: 2300 movs r3, #0
|
|
8000c92: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
|
|
8000c94: f107 030c add.w r3, r7, #12
|
|
8000c98: 4619 mov r1, r3
|
|
8000c9a: 4804 ldr r0, [pc, #16] @ (8000cac <MX_GPIO_Init+0x7c>)
|
|
8000c9c: f002 fc06 bl 80034ac <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000ca0: bf00 nop
|
|
8000ca2: 3720 adds r7, #32
|
|
8000ca4: 46bd mov sp, r7
|
|
8000ca6: bd80 pop {r7, pc}
|
|
8000ca8: 40021000 .word 0x40021000
|
|
8000cac: 48000400 .word 0x48000400
|
|
|
|
08000cb0 <ADC_Filter_Init>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
void ADC_Filter_Init(ADC_Filter *f)
|
|
{
|
|
8000cb0: b580 push {r7, lr}
|
|
8000cb2: b082 sub sp, #8
|
|
8000cb4: af00 add r7, sp, #0
|
|
8000cb6: 6078 str r0, [r7, #4]
|
|
memset(f->buffer, 0, sizeof(f->buffer));
|
|
8000cb8: 687b ldr r3, [r7, #4]
|
|
8000cba: 2280 movs r2, #128 @ 0x80
|
|
8000cbc: 2100 movs r1, #0
|
|
8000cbe: 4618 mov r0, r3
|
|
8000cc0: f007 f960 bl 8007f84 <memset>
|
|
f->sum = 0;
|
|
8000cc4: 687b ldr r3, [r7, #4]
|
|
8000cc6: 2200 movs r2, #0
|
|
8000cc8: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
f->index = 0;
|
|
8000ccc: 687b ldr r3, [r7, #4]
|
|
8000cce: 2200 movs r2, #0
|
|
8000cd0: f883 2080 strb.w r2, [r3, #128] @ 0x80
|
|
}
|
|
8000cd4: bf00 nop
|
|
8000cd6: 3708 adds r7, #8
|
|
8000cd8: 46bd mov sp, r7
|
|
8000cda: bd80 pop {r7, pc}
|
|
|
|
08000cdc <ADC_Filter_Update>:
|
|
|
|
uint32_t ADC_Filter_Update(ADC_Filter *f, uint32_t new_sample)
|
|
{
|
|
8000cdc: b480 push {r7}
|
|
8000cde: b083 sub sp, #12
|
|
8000ce0: af00 add r7, sp, #0
|
|
8000ce2: 6078 str r0, [r7, #4]
|
|
8000ce4: 6039 str r1, [r7, #0]
|
|
/* Remove the oldest sample from the running sum */
|
|
f->sum -= f->buffer[f->index];
|
|
8000ce6: 687b ldr r3, [r7, #4]
|
|
8000ce8: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
|
|
8000cec: 687b ldr r3, [r7, #4]
|
|
8000cee: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
|
|
8000cf2: 4619 mov r1, r3
|
|
8000cf4: 687b ldr r3, [r7, #4]
|
|
8000cf6: f853 3021 ldr.w r3, [r3, r1, lsl #2]
|
|
8000cfa: 1ad2 subs r2, r2, r3
|
|
8000cfc: 687b ldr r3, [r7, #4]
|
|
8000cfe: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Store the new sample in the buffer */
|
|
f->buffer[f->index] = new_sample;
|
|
8000d02: 687b ldr r3, [r7, #4]
|
|
8000d04: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
|
|
8000d08: 4619 mov r1, r3
|
|
8000d0a: 687b ldr r3, [r7, #4]
|
|
8000d0c: 683a ldr r2, [r7, #0]
|
|
8000d0e: f843 2021 str.w r2, [r3, r1, lsl #2]
|
|
|
|
/* Add the new sample to the sum */
|
|
f->sum += new_sample;
|
|
8000d12: 687b ldr r3, [r7, #4]
|
|
8000d14: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84
|
|
8000d18: 683b ldr r3, [r7, #0]
|
|
8000d1a: 441a add r2, r3
|
|
8000d1c: 687b ldr r3, [r7, #4]
|
|
8000d1e: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Move index to next position, wrap around if at end */
|
|
f->index++;
|
|
8000d22: 687b ldr r3, [r7, #4]
|
|
8000d24: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
|
|
8000d28: 3301 adds r3, #1
|
|
8000d2a: b2da uxtb r2, r3
|
|
8000d2c: 687b ldr r3, [r7, #4]
|
|
8000d2e: f883 2080 strb.w r2, [r3, #128] @ 0x80
|
|
|
|
if (f->index >= AVG_WINDOW)
|
|
8000d32: 687b ldr r3, [r7, #4]
|
|
8000d34: f893 3080 ldrb.w r3, [r3, #128] @ 0x80
|
|
8000d38: 2b1f cmp r3, #31
|
|
8000d3a: d903 bls.n 8000d44 <ADC_Filter_Update+0x68>
|
|
{
|
|
f->index = 0;
|
|
8000d3c: 687b ldr r3, [r7, #4]
|
|
8000d3e: 2200 movs r2, #0
|
|
8000d40: f883 2080 strb.w r2, [r3, #128] @ 0x80
|
|
}
|
|
|
|
/* Return the average */
|
|
return f->sum / AVG_WINDOW;
|
|
8000d44: 687b ldr r3, [r7, #4]
|
|
8000d46: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8000d4a: 095b lsrs r3, r3, #5
|
|
}
|
|
8000d4c: 4618 mov r0, r3
|
|
8000d4e: 370c adds r7, #12
|
|
8000d50: 46bd mov sp, r7
|
|
8000d52: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000d56: 4770 bx lr
|
|
|
|
08000d58 <update_pwm>:
|
|
|
|
int32_t update_pwm (uint32_t measured_mv)
|
|
{
|
|
8000d58: b480 push {r7}
|
|
8000d5a: b085 sub sp, #20
|
|
8000d5c: af00 add r7, sp, #0
|
|
8000d5e: 6078 str r0, [r7, #4]
|
|
/* Calculate Error */
|
|
int32_t new_pwm = 0;
|
|
8000d60: 2300 movs r3, #0
|
|
8000d62: 60fb str r3, [r7, #12]
|
|
uint8_t direction_flag = 0x00;
|
|
8000d64: 2300 movs r3, #0
|
|
8000d66: 72fb strb r3, [r7, #11]
|
|
|
|
if (v_target >= measured_mv)
|
|
8000d68: 4b16 ldr r3, [pc, #88] @ (8000dc4 <update_pwm+0x6c>)
|
|
8000d6a: 681b ldr r3, [r3, #0]
|
|
8000d6c: 687a ldr r2, [r7, #4]
|
|
8000d6e: 429a cmp r2, r3
|
|
8000d70: d802 bhi.n 8000d78 <update_pwm+0x20>
|
|
{
|
|
direction_flag = 0x00;
|
|
8000d72: 2300 movs r3, #0
|
|
8000d74: 72fb strb r3, [r7, #11]
|
|
8000d76: e001 b.n 8000d7c <update_pwm+0x24>
|
|
}
|
|
|
|
else
|
|
{
|
|
direction_flag = 0xFF;
|
|
8000d78: 23ff movs r3, #255 @ 0xff
|
|
8000d7a: 72fb strb r3, [r7, #11]
|
|
}
|
|
|
|
if (direction_flag == 0xFF)
|
|
8000d7c: 7afb ldrb r3, [r7, #11]
|
|
8000d7e: 2bff cmp r3, #255 @ 0xff
|
|
8000d80: d106 bne.n 8000d90 <update_pwm+0x38>
|
|
{
|
|
new_pwm = (uint32_t)pwm_value;
|
|
8000d82: 4b11 ldr r3, [pc, #68] @ (8000dc8 <update_pwm+0x70>)
|
|
8000d84: 881b ldrh r3, [r3, #0]
|
|
8000d86: 60fb str r3, [r7, #12]
|
|
new_pwm--;
|
|
8000d88: 68fb ldr r3, [r7, #12]
|
|
8000d8a: 3b01 subs r3, #1
|
|
8000d8c: 60fb str r3, [r7, #12]
|
|
8000d8e: e005 b.n 8000d9c <update_pwm+0x44>
|
|
}
|
|
|
|
else
|
|
{
|
|
new_pwm = (uint32_t)pwm_value;
|
|
8000d90: 4b0d ldr r3, [pc, #52] @ (8000dc8 <update_pwm+0x70>)
|
|
8000d92: 881b ldrh r3, [r3, #0]
|
|
8000d94: 60fb str r3, [r7, #12]
|
|
new_pwm++;
|
|
8000d96: 68fb ldr r3, [r7, #12]
|
|
8000d98: 3301 adds r3, #1
|
|
8000d9a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Output Saturation (Keep PWM within hardware limits) */
|
|
if (new_pwm > pwm_max)
|
|
8000d9c: 68fa ldr r2, [r7, #12]
|
|
8000d9e: 4b0b ldr r3, [pc, #44] @ (8000dcc <update_pwm+0x74>)
|
|
8000da0: 681b ldr r3, [r3, #0]
|
|
8000da2: 429a cmp r2, r3
|
|
8000da4: d902 bls.n 8000dac <update_pwm+0x54>
|
|
{
|
|
new_pwm = pwm_max;
|
|
8000da6: 4b09 ldr r3, [pc, #36] @ (8000dcc <update_pwm+0x74>)
|
|
8000da8: 681b ldr r3, [r3, #0]
|
|
8000daa: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (new_pwm <= 1)
|
|
8000dac: 68fb ldr r3, [r7, #12]
|
|
8000dae: 2b01 cmp r3, #1
|
|
8000db0: dc01 bgt.n 8000db6 <update_pwm+0x5e>
|
|
{
|
|
new_pwm = 1;
|
|
8000db2: 2301 movs r3, #1
|
|
8000db4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return new_pwm;
|
|
8000db6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000db8: 4618 mov r0, r3
|
|
8000dba: 3714 adds r7, #20
|
|
8000dbc: 46bd mov sp, r7
|
|
8000dbe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000dc2: 4770 bx lr
|
|
8000dc4: 200002a8 .word 0x200002a8
|
|
8000dc8: 200002ae .word 0x200002ae
|
|
8000dcc: 20000018 .word 0x20000018
|
|
|
|
08000dd0 <get_actual_vdda>:
|
|
|
|
float get_actual_vdda(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8000dd0: b580 push {r7, lr}
|
|
8000dd2: b084 sub sp, #16
|
|
8000dd4: af00 add r7, sp, #0
|
|
8000dd6: 6078 str r0, [r7, #4]
|
|
uint32_t vrefint_raw = 0;
|
|
8000dd8: 2300 movs r3, #0
|
|
8000dda: 60fb str r3, [r7, #12]
|
|
|
|
/* Perform ADC reading of the VREFINT channel */
|
|
HAL_ADC_Start(hadc);
|
|
8000ddc: 6878 ldr r0, [r7, #4]
|
|
8000dde: f001 f8d5 bl 8001f8c <HAL_ADC_Start>
|
|
|
|
if (HAL_ADC_PollForConversion(hadc, 10) == HAL_OK)
|
|
8000de2: 210a movs r1, #10
|
|
8000de4: 6878 ldr r0, [r7, #4]
|
|
8000de6: f001 f9c1 bl 800216c <HAL_ADC_PollForConversion>
|
|
8000dea: 4603 mov r3, r0
|
|
8000dec: 2b00 cmp r3, #0
|
|
8000dee: d103 bne.n 8000df8 <get_actual_vdda+0x28>
|
|
{
|
|
vrefint_raw = HAL_ADC_GetValue(hadc);
|
|
8000df0: 6878 ldr r0, [r7, #4]
|
|
8000df2: f001 fa93 bl 800231c <HAL_ADC_GetValue>
|
|
8000df6: 60f8 str r0, [r7, #12]
|
|
}
|
|
|
|
HAL_ADC_Stop(hadc);
|
|
8000df8: 6878 ldr r0, [r7, #4]
|
|
8000dfa: f001 f983 bl 8002104 <HAL_ADC_Stop>
|
|
|
|
if (vrefint_raw == 0)
|
|
8000dfe: 68fb ldr r3, [r7, #12]
|
|
8000e00: 2b00 cmp r3, #0
|
|
8000e02: d102 bne.n 8000e0a <get_actual_vdda+0x3a>
|
|
{
|
|
return 0; /* Avoid division by zero */
|
|
8000e04: f04f 0300 mov.w r3, #0
|
|
8000e08: e014 b.n 8000e34 <get_actual_vdda+0x64>
|
|
}
|
|
|
|
/* Use the standard ST formula to calculate VDDA */
|
|
/* VDDA = VREFINT_CAL_VREF * VREFINT_CAL / VREFINT_DATA */
|
|
float vdda_mv = (VREFINT_CAL_VREF * (uint32_t)(*VREFINT_CAL_ADDR)) / (float)vrefint_raw;
|
|
8000e0a: 4b0e ldr r3, [pc, #56] @ (8000e44 <get_actual_vdda+0x74>)
|
|
8000e0c: 881b ldrh r3, [r3, #0]
|
|
8000e0e: 461a mov r2, r3
|
|
8000e10: f640 33b8 movw r3, #3000 @ 0xbb8
|
|
8000e14: fb02 f303 mul.w r3, r2, r3
|
|
8000e18: ee07 3a90 vmov s15, r3
|
|
8000e1c: eef8 6a67 vcvt.f32.u32 s13, s15
|
|
8000e20: 68fb ldr r3, [r7, #12]
|
|
8000e22: ee07 3a90 vmov s15, r3
|
|
8000e26: eeb8 7a67 vcvt.f32.u32 s14, s15
|
|
8000e2a: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8000e2e: edc7 7a02 vstr s15, [r7, #8]
|
|
|
|
return vdda_mv;
|
|
8000e32: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8000e34: ee07 3a90 vmov s15, r3
|
|
8000e38: eeb0 0a67 vmov.f32 s0, s15
|
|
8000e3c: 3710 adds r7, #16
|
|
8000e3e: 46bd mov sp, r7
|
|
8000e40: bd80 pop {r7, pc}
|
|
8000e42: bf00 nop
|
|
8000e44: 1fff75aa .word 0x1fff75aa
|
|
|
|
08000e48 <serial_number_task>:
|
|
|
|
void serial_number_task (void)
|
|
{
|
|
8000e48: b580 push {r7, lr}
|
|
8000e4a: af00 add r7, sp, #0
|
|
tx_len = 0x13;
|
|
8000e4c: 4b42 ldr r3, [pc, #264] @ (8000f58 <serial_number_task+0x110>)
|
|
8000e4e: 2213 movs r2, #19
|
|
8000e50: 701a strb r2, [r3, #0]
|
|
|
|
tx_buffer[0] = IN_SYNC_BYTE_1;
|
|
8000e52: 4b42 ldr r3, [pc, #264] @ (8000f5c <serial_number_task+0x114>)
|
|
8000e54: 2241 movs r2, #65 @ 0x41
|
|
8000e56: 701a strb r2, [r3, #0]
|
|
tx_buffer[1] = IN_SYNC_BYTE_2;
|
|
8000e58: 4b40 ldr r3, [pc, #256] @ (8000f5c <serial_number_task+0x114>)
|
|
8000e5a: 2252 movs r2, #82 @ 0x52
|
|
8000e5c: 705a strb r2, [r3, #1]
|
|
|
|
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
|
|
8000e5e: 4b40 ldr r3, [pc, #256] @ (8000f60 <serial_number_task+0x118>)
|
|
8000e60: 2200 movs r2, #0
|
|
8000e62: 701a strb r2, [r3, #0]
|
|
8000e64: e00f b.n 8000e86 <serial_number_task+0x3e>
|
|
{
|
|
tx_buffer[tx_len_counter + 3] = serial_number[tx_len_counter];
|
|
8000e66: 4b3e ldr r3, [pc, #248] @ (8000f60 <serial_number_task+0x118>)
|
|
8000e68: 781b ldrb r3, [r3, #0]
|
|
8000e6a: 4619 mov r1, r3
|
|
8000e6c: 4b3c ldr r3, [pc, #240] @ (8000f60 <serial_number_task+0x118>)
|
|
8000e6e: 781b ldrb r3, [r3, #0]
|
|
8000e70: 3303 adds r3, #3
|
|
8000e72: 4a3c ldr r2, [pc, #240] @ (8000f64 <serial_number_task+0x11c>)
|
|
8000e74: 5c51 ldrb r1, [r2, r1]
|
|
8000e76: 4a39 ldr r2, [pc, #228] @ (8000f5c <serial_number_task+0x114>)
|
|
8000e78: 54d1 strb r1, [r2, r3]
|
|
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
|
|
8000e7a: 4b39 ldr r3, [pc, #228] @ (8000f60 <serial_number_task+0x118>)
|
|
8000e7c: 781b ldrb r3, [r3, #0]
|
|
8000e7e: 3301 adds r3, #1
|
|
8000e80: b2da uxtb r2, r3
|
|
8000e82: 4b37 ldr r3, [pc, #220] @ (8000f60 <serial_number_task+0x118>)
|
|
8000e84: 701a strb r2, [r3, #0]
|
|
8000e86: 4b36 ldr r3, [pc, #216] @ (8000f60 <serial_number_task+0x118>)
|
|
8000e88: 781a ldrb r2, [r3, #0]
|
|
8000e8a: 4b33 ldr r3, [pc, #204] @ (8000f58 <serial_number_task+0x110>)
|
|
8000e8c: 781b ldrb r3, [r3, #0]
|
|
8000e8e: 429a cmp r2, r3
|
|
8000e90: d3e9 bcc.n 8000e66 <serial_number_task+0x1e>
|
|
}
|
|
|
|
tx_buffer[tx_len + 3] = 0x3A;
|
|
8000e92: 4b31 ldr r3, [pc, #196] @ (8000f58 <serial_number_task+0x110>)
|
|
8000e94: 781b ldrb r3, [r3, #0]
|
|
8000e96: 3303 adds r3, #3
|
|
8000e98: 4a30 ldr r2, [pc, #192] @ (8000f5c <serial_number_task+0x114>)
|
|
8000e9a: 213a movs r1, #58 @ 0x3a
|
|
8000e9c: 54d1 strb r1, [r2, r3]
|
|
tx_buffer[tx_len + 4] = fw_rev_h + 0x30;
|
|
8000e9e: 4b32 ldr r3, [pc, #200] @ (8000f68 <serial_number_task+0x120>)
|
|
8000ea0: 781a ldrb r2, [r3, #0]
|
|
8000ea2: 4b2d ldr r3, [pc, #180] @ (8000f58 <serial_number_task+0x110>)
|
|
8000ea4: 781b ldrb r3, [r3, #0]
|
|
8000ea6: 3304 adds r3, #4
|
|
8000ea8: 3230 adds r2, #48 @ 0x30
|
|
8000eaa: b2d1 uxtb r1, r2
|
|
8000eac: 4a2b ldr r2, [pc, #172] @ (8000f5c <serial_number_task+0x114>)
|
|
8000eae: 54d1 strb r1, [r2, r3]
|
|
tx_buffer[tx_len + 5] = fw_rev_l + 0x30;
|
|
8000eb0: 4b2e ldr r3, [pc, #184] @ (8000f6c <serial_number_task+0x124>)
|
|
8000eb2: 781a ldrb r2, [r3, #0]
|
|
8000eb4: 4b28 ldr r3, [pc, #160] @ (8000f58 <serial_number_task+0x110>)
|
|
8000eb6: 781b ldrb r3, [r3, #0]
|
|
8000eb8: 3305 adds r3, #5
|
|
8000eba: 3230 adds r2, #48 @ 0x30
|
|
8000ebc: b2d1 uxtb r1, r2
|
|
8000ebe: 4a27 ldr r2, [pc, #156] @ (8000f5c <serial_number_task+0x114>)
|
|
8000ec0: 54d1 strb r1, [r2, r3]
|
|
|
|
tx_len = 0x16;
|
|
8000ec2: 4b25 ldr r3, [pc, #148] @ (8000f58 <serial_number_task+0x110>)
|
|
8000ec4: 2216 movs r2, #22
|
|
8000ec6: 701a strb r2, [r3, #0]
|
|
tx_buffer[2] = tx_len;
|
|
8000ec8: 4b23 ldr r3, [pc, #140] @ (8000f58 <serial_number_task+0x110>)
|
|
8000eca: 781a ldrb r2, [r3, #0]
|
|
8000ecc: 4b23 ldr r3, [pc, #140] @ (8000f5c <serial_number_task+0x114>)
|
|
8000ece: 709a strb r2, [r3, #2]
|
|
|
|
tx_checksum = 0x00;
|
|
8000ed0: 4b27 ldr r3, [pc, #156] @ (8000f70 <serial_number_task+0x128>)
|
|
8000ed2: 2200 movs r2, #0
|
|
8000ed4: 801a strh r2, [r3, #0]
|
|
|
|
/* Need to apply checksum to all data bits */
|
|
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
|
|
8000ed6: 4b22 ldr r3, [pc, #136] @ (8000f60 <serial_number_task+0x118>)
|
|
8000ed8: 2200 movs r2, #0
|
|
8000eda: 701a strb r2, [r3, #0]
|
|
8000edc: e011 b.n 8000f02 <serial_number_task+0xba>
|
|
{
|
|
tx_checksum += tx_buffer[tx_len_counter + 3];
|
|
8000ede: 4b20 ldr r3, [pc, #128] @ (8000f60 <serial_number_task+0x118>)
|
|
8000ee0: 781b ldrb r3, [r3, #0]
|
|
8000ee2: 3303 adds r3, #3
|
|
8000ee4: 4a1d ldr r2, [pc, #116] @ (8000f5c <serial_number_task+0x114>)
|
|
8000ee6: 5cd3 ldrb r3, [r2, r3]
|
|
8000ee8: 461a mov r2, r3
|
|
8000eea: 4b21 ldr r3, [pc, #132] @ (8000f70 <serial_number_task+0x128>)
|
|
8000eec: 881b ldrh r3, [r3, #0]
|
|
8000eee: 4413 add r3, r2
|
|
8000ef0: b29a uxth r2, r3
|
|
8000ef2: 4b1f ldr r3, [pc, #124] @ (8000f70 <serial_number_task+0x128>)
|
|
8000ef4: 801a strh r2, [r3, #0]
|
|
for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++)
|
|
8000ef6: 4b1a ldr r3, [pc, #104] @ (8000f60 <serial_number_task+0x118>)
|
|
8000ef8: 781b ldrb r3, [r3, #0]
|
|
8000efa: 3301 adds r3, #1
|
|
8000efc: b2da uxtb r2, r3
|
|
8000efe: 4b18 ldr r3, [pc, #96] @ (8000f60 <serial_number_task+0x118>)
|
|
8000f00: 701a strb r2, [r3, #0]
|
|
8000f02: 4b17 ldr r3, [pc, #92] @ (8000f60 <serial_number_task+0x118>)
|
|
8000f04: 781a ldrb r2, [r3, #0]
|
|
8000f06: 4b14 ldr r3, [pc, #80] @ (8000f58 <serial_number_task+0x110>)
|
|
8000f08: 781b ldrb r3, [r3, #0]
|
|
8000f0a: 429a cmp r2, r3
|
|
8000f0c: d3e7 bcc.n 8000ede <serial_number_task+0x96>
|
|
}
|
|
|
|
tx_checksum = ~tx_checksum;
|
|
8000f0e: 4b18 ldr r3, [pc, #96] @ (8000f70 <serial_number_task+0x128>)
|
|
8000f10: 881b ldrh r3, [r3, #0]
|
|
8000f12: 43db mvns r3, r3
|
|
8000f14: b29a uxth r2, r3
|
|
8000f16: 4b16 ldr r3, [pc, #88] @ (8000f70 <serial_number_task+0x128>)
|
|
8000f18: 801a strh r2, [r3, #0]
|
|
|
|
tx_buffer[tx_len + 3] = (uint8_t)((tx_checksum >> 8) & 0xFF);
|
|
8000f1a: 4b15 ldr r3, [pc, #84] @ (8000f70 <serial_number_task+0x128>)
|
|
8000f1c: 881b ldrh r3, [r3, #0]
|
|
8000f1e: 0a1b lsrs r3, r3, #8
|
|
8000f20: b29a uxth r2, r3
|
|
8000f22: 4b0d ldr r3, [pc, #52] @ (8000f58 <serial_number_task+0x110>)
|
|
8000f24: 781b ldrb r3, [r3, #0]
|
|
8000f26: 3303 adds r3, #3
|
|
8000f28: b2d1 uxtb r1, r2
|
|
8000f2a: 4a0c ldr r2, [pc, #48] @ (8000f5c <serial_number_task+0x114>)
|
|
8000f2c: 54d1 strb r1, [r2, r3]
|
|
tx_buffer[tx_len + 4] = (uint8_t)(tx_checksum & 0xFF);
|
|
8000f2e: 4b10 ldr r3, [pc, #64] @ (8000f70 <serial_number_task+0x128>)
|
|
8000f30: 881a ldrh r2, [r3, #0]
|
|
8000f32: 4b09 ldr r3, [pc, #36] @ (8000f58 <serial_number_task+0x110>)
|
|
8000f34: 781b ldrb r3, [r3, #0]
|
|
8000f36: 3304 adds r3, #4
|
|
8000f38: b2d1 uxtb r1, r2
|
|
8000f3a: 4a08 ldr r2, [pc, #32] @ (8000f5c <serial_number_task+0x114>)
|
|
8000f3c: 54d1 strb r1, [r2, r3]
|
|
|
|
tx_len = 0x1B;
|
|
8000f3e: 4b06 ldr r3, [pc, #24] @ (8000f58 <serial_number_task+0x110>)
|
|
8000f40: 221b movs r2, #27
|
|
8000f42: 701a strb r2, [r3, #0]
|
|
|
|
HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100);
|
|
8000f44: 4b04 ldr r3, [pc, #16] @ (8000f58 <serial_number_task+0x110>)
|
|
8000f46: 781b ldrb r3, [r3, #0]
|
|
8000f48: 461a mov r2, r3
|
|
8000f4a: 2364 movs r3, #100 @ 0x64
|
|
8000f4c: 4903 ldr r1, [pc, #12] @ (8000f5c <serial_number_task+0x114>)
|
|
8000f4e: 4809 ldr r0, [pc, #36] @ (8000f74 <serial_number_task+0x12c>)
|
|
8000f50: f004 ff58 bl 8005e04 <HAL_UART_Transmit>
|
|
}
|
|
8000f54: bf00 nop
|
|
8000f56: bd80 pop {r7, pc}
|
|
8000f58: 20000290 .word 0x20000290
|
|
8000f5c: 20000270 .word 0x20000270
|
|
8000f60: 20000291 .word 0x20000291
|
|
8000f64: 20000004 .word 0x20000004
|
|
8000f68: 20000248 .word 0x20000248
|
|
8000f6c: 20000000 .word 0x20000000
|
|
8000f70: 20000298 .word 0x20000298
|
|
8000f74: 200001b4 .word 0x200001b4
|
|
|
|
08000f78 <adc_task>:
|
|
|
|
/* ADC task */
|
|
void adc_task (void)
|
|
{
|
|
8000f78: b580 push {r7, lr}
|
|
8000f7a: af00 add r7, sp, #0
|
|
HAL_ADC_Start(&hadc2);
|
|
8000f7c: 4809 ldr r0, [pc, #36] @ (8000fa4 <adc_task+0x2c>)
|
|
8000f7e: f001 f805 bl 8001f8c <HAL_ADC_Start>
|
|
HAL_ADC_PollForConversion(&hadc2, 500);
|
|
8000f82: f44f 71fa mov.w r1, #500 @ 0x1f4
|
|
8000f86: 4807 ldr r0, [pc, #28] @ (8000fa4 <adc_task+0x2c>)
|
|
8000f88: f001 f8f0 bl 800216c <HAL_ADC_PollForConversion>
|
|
vout_adc_val = HAL_ADC_GetValue(&hadc2);
|
|
8000f8c: 4805 ldr r0, [pc, #20] @ (8000fa4 <adc_task+0x2c>)
|
|
8000f8e: f001 f9c5 bl 800231c <HAL_ADC_GetValue>
|
|
8000f92: 4603 mov r3, r0
|
|
8000f94: 4a04 ldr r2, [pc, #16] @ (8000fa8 <adc_task+0x30>)
|
|
8000f96: 6013 str r3, [r2, #0]
|
|
HAL_ADC_Stop(&hadc2);
|
|
8000f98: 4802 ldr r0, [pc, #8] @ (8000fa4 <adc_task+0x2c>)
|
|
8000f9a: f001 f8b3 bl 8002104 <HAL_ADC_Stop>
|
|
}
|
|
8000f9e: bf00 nop
|
|
8000fa0: bd80 pop {r7, pc}
|
|
8000fa2: bf00 nop
|
|
8000fa4: 200000b0 .word 0x200000b0
|
|
8000fa8: 200002b4 .word 0x200002b4
|
|
|
|
08000fac <power_switch>:
|
|
|
|
/* Power switch function */
|
|
void power_switch (uint8_t state)
|
|
{
|
|
8000fac: b580 push {r7, lr}
|
|
8000fae: b082 sub sp, #8
|
|
8000fb0: af00 add r7, sp, #0
|
|
8000fb2: 4603 mov r3, r0
|
|
8000fb4: 71fb strb r3, [r7, #7]
|
|
if (state == 1)
|
|
8000fb6: 79fb ldrb r3, [r7, #7]
|
|
8000fb8: 2b01 cmp r3, #1
|
|
8000fba: d123 bne.n 8001004 <power_switch+0x58>
|
|
{
|
|
vset_task_flag = 0xFF;
|
|
8000fbc: 4b1a ldr r3, [pc, #104] @ (8001028 <power_switch+0x7c>)
|
|
8000fbe: 22ff movs r2, #255 @ 0xff
|
|
8000fc0: 701a strb r2, [r3, #0]
|
|
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET);
|
|
8000fc2: 2201 movs r2, #1
|
|
8000fc4: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8000fc8: 4818 ldr r0, [pc, #96] @ (800102c <power_switch+0x80>)
|
|
8000fca: f002 fbf1 bl 80037b0 <HAL_GPIO_WritePin>
|
|
|
|
v_scale = v_target / 1000;
|
|
8000fce: 4b18 ldr r3, [pc, #96] @ (8001030 <power_switch+0x84>)
|
|
8000fd0: 681b ldr r3, [r3, #0]
|
|
8000fd2: 4a18 ldr r2, [pc, #96] @ (8001034 <power_switch+0x88>)
|
|
8000fd4: fba2 2303 umull r2, r3, r2, r3
|
|
8000fd8: 099b lsrs r3, r3, #6
|
|
8000fda: 4a17 ldr r2, [pc, #92] @ (8001038 <power_switch+0x8c>)
|
|
8000fdc: 6013 str r3, [r2, #0]
|
|
|
|
buffer_count = (uint8_t)v_scale;
|
|
8000fde: 4b16 ldr r3, [pc, #88] @ (8001038 <power_switch+0x8c>)
|
|
8000fe0: 681b ldr r3, [r3, #0]
|
|
8000fe2: b2da uxtb r2, r3
|
|
8000fe4: 4b15 ldr r3, [pc, #84] @ (800103c <power_switch+0x90>)
|
|
8000fe6: 701a strb r2, [r3, #0]
|
|
|
|
pwm_value = dataBuffer[buffer_count];
|
|
8000fe8: 4b14 ldr r3, [pc, #80] @ (800103c <power_switch+0x90>)
|
|
8000fea: 781b ldrb r3, [r3, #0]
|
|
8000fec: 461a mov r2, r3
|
|
8000fee: 4b14 ldr r3, [pc, #80] @ (8001040 <power_switch+0x94>)
|
|
8000ff0: f833 2012 ldrh.w r2, [r3, r2, lsl #1]
|
|
8000ff4: 4b13 ldr r3, [pc, #76] @ (8001044 <power_switch+0x98>)
|
|
8000ff6: 801a strh r2, [r3, #0]
|
|
|
|
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, pwm_value);
|
|
8000ff8: 4b12 ldr r3, [pc, #72] @ (8001044 <power_switch+0x98>)
|
|
8000ffa: 881a ldrh r2, [r3, #0]
|
|
8000ffc: 4b12 ldr r3, [pc, #72] @ (8001048 <power_switch+0x9c>)
|
|
8000ffe: 681b ldr r3, [r3, #0]
|
|
8001000: 635a str r2, [r3, #52] @ 0x34
|
|
{
|
|
vset_task_flag = 0x00;
|
|
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
|
|
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
|
|
}
|
|
}
|
|
8001002: e00c b.n 800101e <power_switch+0x72>
|
|
vset_task_flag = 0x00;
|
|
8001004: 4b08 ldr r3, [pc, #32] @ (8001028 <power_switch+0x7c>)
|
|
8001006: 2200 movs r2, #0
|
|
8001008: 701a strb r2, [r3, #0]
|
|
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
|
|
800100a: 2200 movs r2, #0
|
|
800100c: f44f 7180 mov.w r1, #256 @ 0x100
|
|
8001010: 4806 ldr r0, [pc, #24] @ (800102c <power_switch+0x80>)
|
|
8001012: f002 fbcd bl 80037b0 <HAL_GPIO_WritePin>
|
|
__HAL_TIM_SET_COMPARE(&htim16, TIM_CHANNEL_1, 0);
|
|
8001016: 4b0c ldr r3, [pc, #48] @ (8001048 <power_switch+0x9c>)
|
|
8001018: 681b ldr r3, [r3, #0]
|
|
800101a: 2200 movs r2, #0
|
|
800101c: 635a str r2, [r3, #52] @ 0x34
|
|
}
|
|
800101e: bf00 nop
|
|
8001020: 3708 adds r7, #8
|
|
8001022: 46bd mov sp, r7
|
|
8001024: bd80 pop {r7, pc}
|
|
8001026: bf00 nop
|
|
8001028: 200002ac .word 0x200002ac
|
|
800102c: 48000400 .word 0x48000400
|
|
8001030: 200002a8 .word 0x200002a8
|
|
8001034: 10624dd3 .word 0x10624dd3
|
|
8001038: 200002cc .word 0x200002cc
|
|
800103c: 200002c8 .word 0x200002c8
|
|
8001040: 08007ff4 .word 0x08007ff4
|
|
8001044: 200002ae .word 0x200002ae
|
|
8001048: 20000168 .word 0x20000168
|
|
|
|
0800104c <HAL_UART_TxCpltCallback>:
|
|
|
|
/* UART Tx callback */
|
|
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800104c: b480 push {r7}
|
|
800104e: b083 sub sp, #12
|
|
8001050: af00 add r7, sp, #0
|
|
8001052: 6078 str r0, [r7, #4]
|
|
/* Do nothing here for now */
|
|
}
|
|
8001054: bf00 nop
|
|
8001056: 370c adds r7, #12
|
|
8001058: 46bd mov sp, r7
|
|
800105a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800105e: 4770 bx lr
|
|
|
|
08001060 <HAL_UART_RxCpltCallback>:
|
|
|
|
/* UART Rx callback */
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8001060: b580 push {r7, lr}
|
|
8001062: b082 sub sp, #8
|
|
8001064: af00 add r7, sp, #0
|
|
8001066: 6078 str r0, [r7, #4]
|
|
/* If data received on UART */
|
|
if(huart->Instance==USART2)
|
|
8001068: 687b ldr r3, [r7, #4]
|
|
800106a: 681b ldr r3, [r3, #0]
|
|
800106c: 4a7d ldr r2, [pc, #500] @ (8001264 <HAL_UART_RxCpltCallback+0x204>)
|
|
800106e: 4293 cmp r3, r2
|
|
8001070: f040 80f3 bne.w 800125a <HAL_UART_RxCpltCallback+0x1fa>
|
|
{
|
|
/* Act on received data */
|
|
switch (rx_counter)
|
|
8001074: 4b7c ldr r3, [pc, #496] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
8001076: 781b ldrb r3, [r3, #0]
|
|
8001078: 2b05 cmp r3, #5
|
|
800107a: f200 80e4 bhi.w 8001246 <HAL_UART_RxCpltCallback+0x1e6>
|
|
800107e: a201 add r2, pc, #4 @ (adr r2, 8001084 <HAL_UART_RxCpltCallback+0x24>)
|
|
8001080: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8001084: 0800109d .word 0x0800109d
|
|
8001088: 080010b5 .word 0x080010b5
|
|
800108c: 080010e3 .word 0x080010e3
|
|
8001090: 080010ff .word 0x080010ff
|
|
8001094: 0800113b .word 0x0800113b
|
|
8001098: 08001151 .word 0x08001151
|
|
{
|
|
case 0x00:
|
|
/* Check to see if first sync byte has been received */
|
|
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
|
|
800109c: 4b73 ldr r3, [pc, #460] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
800109e: 781b ldrb r3, [r3, #0]
|
|
80010a0: 2b41 cmp r3, #65 @ 0x41
|
|
80010a2: f040 80d2 bne.w 800124a <HAL_UART_RxCpltCallback+0x1ea>
|
|
{
|
|
/* Got it, so now wait for the second sync byte */
|
|
rx_counter++;
|
|
80010a6: 4b70 ldr r3, [pc, #448] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010a8: 781b ldrb r3, [r3, #0]
|
|
80010aa: 3301 adds r3, #1
|
|
80010ac: b2da uxtb r2, r3
|
|
80010ae: 4b6e ldr r3, [pc, #440] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010b0: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
break;
|
|
80010b2: e0ca b.n 800124a <HAL_UART_RxCpltCallback+0x1ea>
|
|
|
|
case 0x01:
|
|
/* Check to see if second sync byte has been received */
|
|
if (rx_hold_buffer[0] == IN_SYNC_BYTE_2)
|
|
80010b4: 4b6d ldr r3, [pc, #436] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
80010b6: 781b ldrb r3, [r3, #0]
|
|
80010b8: 2b52 cmp r3, #82 @ 0x52
|
|
80010ba: d106 bne.n 80010ca <HAL_UART_RxCpltCallback+0x6a>
|
|
{
|
|
/* Got it, so now wait for the data byte */
|
|
rx_counter++;
|
|
80010bc: 4b6a ldr r3, [pc, #424] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010be: 781b ldrb r3, [r3, #0]
|
|
80010c0: 3301 adds r3, #1
|
|
80010c2: b2da uxtb r2, r3
|
|
80010c4: 4b68 ldr r3, [pc, #416] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010c6: 701a strb r2, [r3, #0]
|
|
{
|
|
rx_counter = 0x00;
|
|
}
|
|
}
|
|
|
|
break;
|
|
80010c8: e0c2 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
if (rx_hold_buffer[0] == IN_SYNC_BYTE_1)
|
|
80010ca: 4b68 ldr r3, [pc, #416] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
80010cc: 781b ldrb r3, [r3, #0]
|
|
80010ce: 2b41 cmp r3, #65 @ 0x41
|
|
80010d0: d103 bne.n 80010da <HAL_UART_RxCpltCallback+0x7a>
|
|
rx_counter = 0x01;
|
|
80010d2: 4b65 ldr r3, [pc, #404] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010d4: 2201 movs r2, #1
|
|
80010d6: 701a strb r2, [r3, #0]
|
|
break;
|
|
80010d8: e0ba b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
rx_counter = 0x00;
|
|
80010da: 4b63 ldr r3, [pc, #396] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010dc: 2200 movs r2, #0
|
|
80010de: 701a strb r2, [r3, #0]
|
|
break;
|
|
80010e0: e0b6 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
|
|
case 0x02:
|
|
/* Get rx length and reset counter */
|
|
rx_len = rx_hold_buffer[0];
|
|
80010e2: 4b62 ldr r3, [pc, #392] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
80010e4: 781a ldrb r2, [r3, #0]
|
|
80010e6: 4b62 ldr r3, [pc, #392] @ (8001270 <HAL_UART_RxCpltCallback+0x210>)
|
|
80010e8: 701a strb r2, [r3, #0]
|
|
rx_len_counter = 0x00;
|
|
80010ea: 4b62 ldr r3, [pc, #392] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
80010ec: 2200 movs r2, #0
|
|
80010ee: 701a strb r2, [r3, #0]
|
|
rx_counter++;
|
|
80010f0: 4b5d ldr r3, [pc, #372] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010f2: 781b ldrb r3, [r3, #0]
|
|
80010f4: 3301 adds r3, #1
|
|
80010f6: b2da uxtb r2, r3
|
|
80010f8: 4b5b ldr r3, [pc, #364] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80010fa: 701a strb r2, [r3, #0]
|
|
break;
|
|
80010fc: e0a8 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
|
|
case 0x03:
|
|
/* Store entire length of Data bytes */
|
|
/* Increase count */
|
|
rx_len_counter++;
|
|
80010fe: 4b5d ldr r3, [pc, #372] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
8001100: 781b ldrb r3, [r3, #0]
|
|
8001102: 3301 adds r3, #1
|
|
8001104: b2da uxtb r2, r3
|
|
8001106: 4b5b ldr r3, [pc, #364] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
8001108: 701a strb r2, [r3, #0]
|
|
|
|
/* Store data */
|
|
rx_buffer[rx_len_counter - 1] = rx_hold_buffer[0];
|
|
800110a: 4b5a ldr r3, [pc, #360] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
800110c: 781b ldrb r3, [r3, #0]
|
|
800110e: 3b01 subs r3, #1
|
|
8001110: 4a56 ldr r2, [pc, #344] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
8001112: 7811 ldrb r1, [r2, #0]
|
|
8001114: 4a58 ldr r2, [pc, #352] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
8001116: 54d1 strb r1, [r2, r3]
|
|
|
|
/* Check to see if we have all the expected data bytes */
|
|
/* If so, then move on the CRC */
|
|
if (rx_len_counter == rx_len)
|
|
8001118: 4b56 ldr r3, [pc, #344] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
800111a: 781a ldrb r2, [r3, #0]
|
|
800111c: 4b54 ldr r3, [pc, #336] @ (8001270 <HAL_UART_RxCpltCallback+0x210>)
|
|
800111e: 781b ldrb r3, [r3, #0]
|
|
8001120: 429a cmp r2, r3
|
|
8001122: f040 8094 bne.w 800124e <HAL_UART_RxCpltCallback+0x1ee>
|
|
{
|
|
rx_counter++;
|
|
8001126: 4b50 ldr r3, [pc, #320] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
8001128: 781b ldrb r3, [r3, #0]
|
|
800112a: 3301 adds r3, #1
|
|
800112c: b2da uxtb r2, r3
|
|
800112e: 4b4e ldr r3, [pc, #312] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
8001130: 701a strb r2, [r3, #0]
|
|
rx_len_counter = 0x00;
|
|
8001132: 4b50 ldr r3, [pc, #320] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
8001134: 2200 movs r2, #0
|
|
8001136: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
break;
|
|
8001138: e089 b.n 800124e <HAL_UART_RxCpltCallback+0x1ee>
|
|
|
|
case 0x04:
|
|
/* Store Rx checksum byte #1 */
|
|
rx_checksum_hold_1 = rx_hold_buffer[0];
|
|
800113a: 4b4c ldr r3, [pc, #304] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
800113c: 781a ldrb r2, [r3, #0]
|
|
800113e: 4b4f ldr r3, [pc, #316] @ (800127c <HAL_UART_RxCpltCallback+0x21c>)
|
|
8001140: 701a strb r2, [r3, #0]
|
|
rx_counter++;
|
|
8001142: 4b49 ldr r3, [pc, #292] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
8001144: 781b ldrb r3, [r3, #0]
|
|
8001146: 3301 adds r3, #1
|
|
8001148: b2da uxtb r2, r3
|
|
800114a: 4b47 ldr r3, [pc, #284] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
800114c: 701a strb r2, [r3, #0]
|
|
break;
|
|
800114e: e07f b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
|
|
case 0x05:
|
|
/* Store Rx checksum byte #2, reset and calculate checksum */
|
|
rx_checksum_hold_2 = rx_hold_buffer[0];
|
|
8001150: 4b46 ldr r3, [pc, #280] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
8001152: 781a ldrb r2, [r3, #0]
|
|
8001154: 4b4a ldr r3, [pc, #296] @ (8001280 <HAL_UART_RxCpltCallback+0x220>)
|
|
8001156: 701a strb r2, [r3, #0]
|
|
|
|
rx_checksum_hold = (rx_checksum_hold_1 << 8) | rx_checksum_hold_2;
|
|
8001158: 4b48 ldr r3, [pc, #288] @ (800127c <HAL_UART_RxCpltCallback+0x21c>)
|
|
800115a: 781b ldrb r3, [r3, #0]
|
|
800115c: b21b sxth r3, r3
|
|
800115e: 021b lsls r3, r3, #8
|
|
8001160: b21a sxth r2, r3
|
|
8001162: 4b47 ldr r3, [pc, #284] @ (8001280 <HAL_UART_RxCpltCallback+0x220>)
|
|
8001164: 781b ldrb r3, [r3, #0]
|
|
8001166: b21b sxth r3, r3
|
|
8001168: 4313 orrs r3, r2
|
|
800116a: b21b sxth r3, r3
|
|
800116c: b29a uxth r2, r3
|
|
800116e: 4b45 ldr r3, [pc, #276] @ (8001284 <HAL_UART_RxCpltCallback+0x224>)
|
|
8001170: 801a strh r2, [r3, #0]
|
|
|
|
rx_checksum = 0;
|
|
8001172: 4b45 ldr r3, [pc, #276] @ (8001288 <HAL_UART_RxCpltCallback+0x228>)
|
|
8001174: 2200 movs r2, #0
|
|
8001176: 801a strh r2, [r3, #0]
|
|
|
|
/* Need to apply to all data bits */
|
|
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
|
|
8001178: 4b3e ldr r3, [pc, #248] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
800117a: 2200 movs r2, #0
|
|
800117c: 701a strb r2, [r3, #0]
|
|
800117e: e011 b.n 80011a4 <HAL_UART_RxCpltCallback+0x144>
|
|
{
|
|
rx_checksum += rx_buffer[rx_len_counter];
|
|
8001180: 4b3c ldr r3, [pc, #240] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
8001182: 781b ldrb r3, [r3, #0]
|
|
8001184: 461a mov r2, r3
|
|
8001186: 4b3c ldr r3, [pc, #240] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
8001188: 5c9b ldrb r3, [r3, r2]
|
|
800118a: 461a mov r2, r3
|
|
800118c: 4b3e ldr r3, [pc, #248] @ (8001288 <HAL_UART_RxCpltCallback+0x228>)
|
|
800118e: 881b ldrh r3, [r3, #0]
|
|
8001190: 4413 add r3, r2
|
|
8001192: b29a uxth r2, r3
|
|
8001194: 4b3c ldr r3, [pc, #240] @ (8001288 <HAL_UART_RxCpltCallback+0x228>)
|
|
8001196: 801a strh r2, [r3, #0]
|
|
for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++)
|
|
8001198: 4b36 ldr r3, [pc, #216] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
800119a: 781b ldrb r3, [r3, #0]
|
|
800119c: 3301 adds r3, #1
|
|
800119e: b2da uxtb r2, r3
|
|
80011a0: 4b34 ldr r3, [pc, #208] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
80011a2: 701a strb r2, [r3, #0]
|
|
80011a4: 4b33 ldr r3, [pc, #204] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
80011a6: 781a ldrb r2, [r3, #0]
|
|
80011a8: 4b31 ldr r3, [pc, #196] @ (8001270 <HAL_UART_RxCpltCallback+0x210>)
|
|
80011aa: 781b ldrb r3, [r3, #0]
|
|
80011ac: 429a cmp r2, r3
|
|
80011ae: d3e7 bcc.n 8001180 <HAL_UART_RxCpltCallback+0x120>
|
|
}
|
|
|
|
rx_len = 0x00;
|
|
80011b0: 4b2f ldr r3, [pc, #188] @ (8001270 <HAL_UART_RxCpltCallback+0x210>)
|
|
80011b2: 2200 movs r2, #0
|
|
80011b4: 701a strb r2, [r3, #0]
|
|
rx_len_counter = 0x00;
|
|
80011b6: 4b2f ldr r3, [pc, #188] @ (8001274 <HAL_UART_RxCpltCallback+0x214>)
|
|
80011b8: 2200 movs r2, #0
|
|
80011ba: 701a strb r2, [r3, #0]
|
|
|
|
rx_checksum = ~rx_checksum;
|
|
80011bc: 4b32 ldr r3, [pc, #200] @ (8001288 <HAL_UART_RxCpltCallback+0x228>)
|
|
80011be: 881b ldrh r3, [r3, #0]
|
|
80011c0: 43db mvns r3, r3
|
|
80011c2: b29a uxth r2, r3
|
|
80011c4: 4b30 ldr r3, [pc, #192] @ (8001288 <HAL_UART_RxCpltCallback+0x228>)
|
|
80011c6: 801a strh r2, [r3, #0]
|
|
|
|
/* If checksum calculated equals the received checksum of packet then we got a good packet */
|
|
if (rx_checksum == rx_checksum_hold)
|
|
80011c8: 4b2f ldr r3, [pc, #188] @ (8001288 <HAL_UART_RxCpltCallback+0x228>)
|
|
80011ca: 881a ldrh r2, [r3, #0]
|
|
80011cc: 4b2d ldr r3, [pc, #180] @ (8001284 <HAL_UART_RxCpltCallback+0x224>)
|
|
80011ce: 881b ldrh r3, [r3, #0]
|
|
80011d0: 429a cmp r2, r3
|
|
80011d2: d132 bne.n 800123a <HAL_UART_RxCpltCallback+0x1da>
|
|
{
|
|
/* Rx is finished, so reset count to wait for another first sync byte (also act on command/data)*/
|
|
rx_counter = 0x00;
|
|
80011d4: 4b24 ldr r3, [pc, #144] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
80011d6: 2200 movs r2, #0
|
|
80011d8: 701a strb r2, [r3, #0]
|
|
|
|
command = rx_buffer[0];
|
|
80011da: 4b27 ldr r3, [pc, #156] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
80011dc: 781a ldrb r2, [r3, #0]
|
|
80011de: 4b2b ldr r3, [pc, #172] @ (800128c <HAL_UART_RxCpltCallback+0x22c>)
|
|
80011e0: 701a strb r2, [r3, #0]
|
|
|
|
switch (command)
|
|
80011e2: 4b2a ldr r3, [pc, #168] @ (800128c <HAL_UART_RxCpltCallback+0x22c>)
|
|
80011e4: 781b ldrb r3, [r3, #0]
|
|
80011e6: 2b56 cmp r3, #86 @ 0x56
|
|
80011e8: d01f beq.n 800122a <HAL_UART_RxCpltCallback+0x1ca>
|
|
80011ea: 2b56 cmp r3, #86 @ 0x56
|
|
80011ec: dc29 bgt.n 8001242 <HAL_UART_RxCpltCallback+0x1e2>
|
|
80011ee: 2b49 cmp r3, #73 @ 0x49
|
|
80011f0: d01f beq.n 8001232 <HAL_UART_RxCpltCallback+0x1d2>
|
|
80011f2: 2b53 cmp r3, #83 @ 0x53
|
|
80011f4: d125 bne.n 8001242 <HAL_UART_RxCpltCallback+0x1e2>
|
|
{
|
|
/* 'S' - Set power output state */
|
|
case 0x53:
|
|
power_state_value = rx_buffer[1];
|
|
80011f6: 4b20 ldr r3, [pc, #128] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
80011f8: 785a ldrb r2, [r3, #1]
|
|
80011fa: 4b25 ldr r3, [pc, #148] @ (8001290 <HAL_UART_RxCpltCallback+0x230>)
|
|
80011fc: 701a strb r2, [r3, #0]
|
|
v_target = ((uint32_t)rx_buffer[2] << 24) | ((uint32_t)rx_buffer[3] << 16) | ((uint32_t)rx_buffer[4] << 8) | ((uint32_t)rx_buffer[5]);
|
|
80011fe: 4b1e ldr r3, [pc, #120] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
8001200: 789b ldrb r3, [r3, #2]
|
|
8001202: 061a lsls r2, r3, #24
|
|
8001204: 4b1c ldr r3, [pc, #112] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
8001206: 78db ldrb r3, [r3, #3]
|
|
8001208: 041b lsls r3, r3, #16
|
|
800120a: 431a orrs r2, r3
|
|
800120c: 4b1a ldr r3, [pc, #104] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
800120e: 791b ldrb r3, [r3, #4]
|
|
8001210: 021b lsls r3, r3, #8
|
|
8001212: 4313 orrs r3, r2
|
|
8001214: 4a18 ldr r2, [pc, #96] @ (8001278 <HAL_UART_RxCpltCallback+0x218>)
|
|
8001216: 7952 ldrb r2, [r2, #5]
|
|
8001218: 4313 orrs r3, r2
|
|
800121a: 4a1e ldr r2, [pc, #120] @ (8001294 <HAL_UART_RxCpltCallback+0x234>)
|
|
800121c: 6013 str r3, [r2, #0]
|
|
power_switch(power_state_value);
|
|
800121e: 4b1c ldr r3, [pc, #112] @ (8001290 <HAL_UART_RxCpltCallback+0x230>)
|
|
8001220: 781b ldrb r3, [r3, #0]
|
|
8001222: 4618 mov r0, r3
|
|
8001224: f7ff fec2 bl 8000fac <power_switch>
|
|
break;
|
|
8001228: e00c b.n 8001244 <HAL_UART_RxCpltCallback+0x1e4>
|
|
|
|
/* 'V' - Get voltages (both input and output) */
|
|
case 0x56:
|
|
adc_task_flag = 0xff;
|
|
800122a: 4b1b ldr r3, [pc, #108] @ (8001298 <HAL_UART_RxCpltCallback+0x238>)
|
|
800122c: 22ff movs r2, #255 @ 0xff
|
|
800122e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001230: e008 b.n 8001244 <HAL_UART_RxCpltCallback+0x1e4>
|
|
|
|
/* 'I' - Get serial number information */
|
|
case 0x49:
|
|
serial_number_flag = 0xff;
|
|
8001232: 4b1a ldr r3, [pc, #104] @ (800129c <HAL_UART_RxCpltCallback+0x23c>)
|
|
8001234: 22ff movs r2, #255 @ 0xff
|
|
8001236: 701a strb r2, [r3, #0]
|
|
break;
|
|
8001238: e004 b.n 8001244 <HAL_UART_RxCpltCallback+0x1e4>
|
|
|
|
/* Bad packet received */
|
|
else
|
|
{
|
|
/* Rx is finished, so reset count to wait for another first sync byte (bad packet so no flag)*/
|
|
rx_counter = 0x00;
|
|
800123a: 4b0b ldr r3, [pc, #44] @ (8001268 <HAL_UART_RxCpltCallback+0x208>)
|
|
800123c: 2200 movs r2, #0
|
|
800123e: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
break;
|
|
8001240: e006 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
break;
|
|
8001242: bf00 nop
|
|
break;
|
|
8001244: e004 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
|
|
/* Default case - NOT USED!*/
|
|
default:
|
|
break;
|
|
8001246: bf00 nop
|
|
8001248: e002 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
break;
|
|
800124a: bf00 nop
|
|
800124c: e000 b.n 8001250 <HAL_UART_RxCpltCallback+0x1f0>
|
|
break;
|
|
800124e: bf00 nop
|
|
}
|
|
|
|
/* Reset interrupts */
|
|
HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1);
|
|
8001250: 2201 movs r2, #1
|
|
8001252: 4906 ldr r1, [pc, #24] @ (800126c <HAL_UART_RxCpltCallback+0x20c>)
|
|
8001254: 4812 ldr r0, [pc, #72] @ (80012a0 <HAL_UART_RxCpltCallback+0x240>)
|
|
8001256: f004 fe63 bl 8005f20 <HAL_UART_Receive_IT>
|
|
}
|
|
}
|
|
800125a: bf00 nop
|
|
800125c: 3708 adds r7, #8
|
|
800125e: 46bd mov sp, r7
|
|
8001260: bd80 pop {r7, pc}
|
|
8001262: bf00 nop
|
|
8001264: 40004400 .word 0x40004400
|
|
8001268: 20000292 .word 0x20000292
|
|
800126c: 2000024c .word 0x2000024c
|
|
8001270: 20000293 .word 0x20000293
|
|
8001274: 20000294 .word 0x20000294
|
|
8001278: 20000250 .word 0x20000250
|
|
800127c: 2000029a .word 0x2000029a
|
|
8001280: 2000029b .word 0x2000029b
|
|
8001284: 2000029c .word 0x2000029c
|
|
8001288: 20000296 .word 0x20000296
|
|
800128c: 2000029f .word 0x2000029f
|
|
8001290: 2000029e .word 0x2000029e
|
|
8001294: 200002a8 .word 0x200002a8
|
|
8001298: 200002a0 .word 0x200002a0
|
|
800129c: 200002ad .word 0x200002ad
|
|
80012a0: 200001b4 .word 0x200001b4
|
|
|
|
080012a4 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
80012a4: b480 push {r7}
|
|
80012a6: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80012a8: b672 cpsid i
|
|
}
|
|
80012aa: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80012ac: bf00 nop
|
|
80012ae: e7fd b.n 80012ac <Error_Handler+0x8>
|
|
|
|
080012b0 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80012b0: b580 push {r7, lr}
|
|
80012b2: b082 sub sp, #8
|
|
80012b4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80012b6: 4b0f ldr r3, [pc, #60] @ (80012f4 <HAL_MspInit+0x44>)
|
|
80012b8: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80012ba: 4a0e ldr r2, [pc, #56] @ (80012f4 <HAL_MspInit+0x44>)
|
|
80012bc: f043 0301 orr.w r3, r3, #1
|
|
80012c0: 6613 str r3, [r2, #96] @ 0x60
|
|
80012c2: 4b0c ldr r3, [pc, #48] @ (80012f4 <HAL_MspInit+0x44>)
|
|
80012c4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80012c6: f003 0301 and.w r3, r3, #1
|
|
80012ca: 607b str r3, [r7, #4]
|
|
80012cc: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80012ce: 4b09 ldr r3, [pc, #36] @ (80012f4 <HAL_MspInit+0x44>)
|
|
80012d0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80012d2: 4a08 ldr r2, [pc, #32] @ (80012f4 <HAL_MspInit+0x44>)
|
|
80012d4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80012d8: 6593 str r3, [r2, #88] @ 0x58
|
|
80012da: 4b06 ldr r3, [pc, #24] @ (80012f4 <HAL_MspInit+0x44>)
|
|
80012dc: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80012de: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80012e2: 603b str r3, [r7, #0]
|
|
80012e4: 683b ldr r3, [r7, #0]
|
|
|
|
/* System interrupt init*/
|
|
|
|
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
|
|
*/
|
|
HAL_PWREx_DisableUCPDDeadBattery();
|
|
80012e6: f002 fb1f bl 8003928 <HAL_PWREx_DisableUCPDDeadBattery>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
80012ea: bf00 nop
|
|
80012ec: 3708 adds r7, #8
|
|
80012ee: 46bd mov sp, r7
|
|
80012f0: bd80 pop {r7, pc}
|
|
80012f2: bf00 nop
|
|
80012f4: 40021000 .word 0x40021000
|
|
|
|
080012f8 <HAL_ADC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
|
{
|
|
80012f8: b580 push {r7, lr}
|
|
80012fa: b09c sub sp, #112 @ 0x70
|
|
80012fc: af00 add r7, sp, #0
|
|
80012fe: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001300: f107 035c add.w r3, r7, #92 @ 0x5c
|
|
8001304: 2200 movs r2, #0
|
|
8001306: 601a str r2, [r3, #0]
|
|
8001308: 605a str r2, [r3, #4]
|
|
800130a: 609a str r2, [r3, #8]
|
|
800130c: 60da str r2, [r3, #12]
|
|
800130e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8001310: f107 0318 add.w r3, r7, #24
|
|
8001314: 2244 movs r2, #68 @ 0x44
|
|
8001316: 2100 movs r1, #0
|
|
8001318: 4618 mov r0, r3
|
|
800131a: f006 fe33 bl 8007f84 <memset>
|
|
if(hadc->Instance==ADC1)
|
|
800131e: 687b ldr r3, [r7, #4]
|
|
8001320: 681b ldr r3, [r3, #0]
|
|
8001322: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8001326: d125 bne.n 8001374 <HAL_ADC_MspInit+0x7c>
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
|
|
8001328: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800132c: 61bb str r3, [r7, #24]
|
|
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
|
|
800132e: f04f 5300 mov.w r3, #536870912 @ 0x20000000
|
|
8001332: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8001334: f107 0318 add.w r3, r7, #24
|
|
8001338: 4618 mov r0, r3
|
|
800133a: f003 f833 bl 80043a4 <HAL_RCCEx_PeriphCLKConfig>
|
|
800133e: 4603 mov r3, r0
|
|
8001340: 2b00 cmp r3, #0
|
|
8001342: d001 beq.n 8001348 <HAL_ADC_MspInit+0x50>
|
|
{
|
|
Error_Handler();
|
|
8001344: f7ff ffae bl 80012a4 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
HAL_RCC_ADC12_CLK_ENABLED++;
|
|
8001348: 4b2e ldr r3, [pc, #184] @ (8001404 <HAL_ADC_MspInit+0x10c>)
|
|
800134a: 681b ldr r3, [r3, #0]
|
|
800134c: 3301 adds r3, #1
|
|
800134e: 4a2d ldr r2, [pc, #180] @ (8001404 <HAL_ADC_MspInit+0x10c>)
|
|
8001350: 6013 str r3, [r2, #0]
|
|
if(HAL_RCC_ADC12_CLK_ENABLED==1){
|
|
8001352: 4b2c ldr r3, [pc, #176] @ (8001404 <HAL_ADC_MspInit+0x10c>)
|
|
8001354: 681b ldr r3, [r3, #0]
|
|
8001356: 2b01 cmp r3, #1
|
|
8001358: d14f bne.n 80013fa <HAL_ADC_MspInit+0x102>
|
|
__HAL_RCC_ADC12_CLK_ENABLE();
|
|
800135a: 4b2b ldr r3, [pc, #172] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
800135c: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800135e: 4a2a ldr r2, [pc, #168] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
8001360: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
8001364: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001366: 4b28 ldr r3, [pc, #160] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
8001368: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
800136a: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800136e: 617b str r3, [r7, #20]
|
|
8001370: 697b ldr r3, [r7, #20]
|
|
/* USER CODE BEGIN ADC2_MspInit 1 */
|
|
|
|
/* USER CODE END ADC2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8001372: e042 b.n 80013fa <HAL_ADC_MspInit+0x102>
|
|
else if(hadc->Instance==ADC2)
|
|
8001374: 687b ldr r3, [r7, #4]
|
|
8001376: 681b ldr r3, [r3, #0]
|
|
8001378: 4a24 ldr r2, [pc, #144] @ (800140c <HAL_ADC_MspInit+0x114>)
|
|
800137a: 4293 cmp r3, r2
|
|
800137c: d13d bne.n 80013fa <HAL_ADC_MspInit+0x102>
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12;
|
|
800137e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8001382: 61bb str r3, [r7, #24]
|
|
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
|
|
8001384: f04f 5300 mov.w r3, #536870912 @ 0x20000000
|
|
8001388: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
800138a: f107 0318 add.w r3, r7, #24
|
|
800138e: 4618 mov r0, r3
|
|
8001390: f003 f808 bl 80043a4 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001394: 4603 mov r3, r0
|
|
8001396: 2b00 cmp r3, #0
|
|
8001398: d001 beq.n 800139e <HAL_ADC_MspInit+0xa6>
|
|
Error_Handler();
|
|
800139a: f7ff ff83 bl 80012a4 <Error_Handler>
|
|
HAL_RCC_ADC12_CLK_ENABLED++;
|
|
800139e: 4b19 ldr r3, [pc, #100] @ (8001404 <HAL_ADC_MspInit+0x10c>)
|
|
80013a0: 681b ldr r3, [r3, #0]
|
|
80013a2: 3301 adds r3, #1
|
|
80013a4: 4a17 ldr r2, [pc, #92] @ (8001404 <HAL_ADC_MspInit+0x10c>)
|
|
80013a6: 6013 str r3, [r2, #0]
|
|
if(HAL_RCC_ADC12_CLK_ENABLED==1){
|
|
80013a8: 4b16 ldr r3, [pc, #88] @ (8001404 <HAL_ADC_MspInit+0x10c>)
|
|
80013aa: 681b ldr r3, [r3, #0]
|
|
80013ac: 2b01 cmp r3, #1
|
|
80013ae: d10b bne.n 80013c8 <HAL_ADC_MspInit+0xd0>
|
|
__HAL_RCC_ADC12_CLK_ENABLE();
|
|
80013b0: 4b15 ldr r3, [pc, #84] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
80013b2: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80013b4: 4a14 ldr r2, [pc, #80] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
80013b6: f443 5300 orr.w r3, r3, #8192 @ 0x2000
|
|
80013ba: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80013bc: 4b12 ldr r3, [pc, #72] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
80013be: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80013c0: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
80013c4: 613b str r3, [r7, #16]
|
|
80013c6: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80013c8: 4b0f ldr r3, [pc, #60] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
80013ca: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80013cc: 4a0e ldr r2, [pc, #56] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
80013ce: f043 0301 orr.w r3, r3, #1
|
|
80013d2: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80013d4: 4b0c ldr r3, [pc, #48] @ (8001408 <HAL_ADC_MspInit+0x110>)
|
|
80013d6: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80013d8: f003 0301 and.w r3, r3, #1
|
|
80013dc: 60fb str r3, [r7, #12]
|
|
80013de: 68fb ldr r3, [r7, #12]
|
|
GPIO_InitStruct.Pin = VOUT_Pin;
|
|
80013e0: 2340 movs r3, #64 @ 0x40
|
|
80013e2: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80013e4: 2303 movs r3, #3
|
|
80013e6: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80013e8: 2300 movs r3, #0
|
|
80013ea: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(VOUT_GPIO_Port, &GPIO_InitStruct);
|
|
80013ec: f107 035c add.w r3, r7, #92 @ 0x5c
|
|
80013f0: 4619 mov r1, r3
|
|
80013f2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80013f6: f002 f859 bl 80034ac <HAL_GPIO_Init>
|
|
}
|
|
80013fa: bf00 nop
|
|
80013fc: 3770 adds r7, #112 @ 0x70
|
|
80013fe: 46bd mov sp, r7
|
|
8001400: bd80 pop {r7, pc}
|
|
8001402: bf00 nop
|
|
8001404: 20000358 .word 0x20000358
|
|
8001408: 40021000 .word 0x40021000
|
|
800140c: 50000100 .word 0x50000100
|
|
|
|
08001410 <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
8001410: b580 push {r7, lr}
|
|
8001412: b084 sub sp, #16
|
|
8001414: af00 add r7, sp, #0
|
|
8001416: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM2)
|
|
8001418: 687b ldr r3, [r7, #4]
|
|
800141a: 681b ldr r3, [r3, #0]
|
|
800141c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8001420: d114 bne.n 800144c <HAL_TIM_Base_MspInit+0x3c>
|
|
{
|
|
/* USER CODE BEGIN TIM2_MspInit 0 */
|
|
|
|
/* USER CODE END TIM2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
8001422: 4b15 ldr r3, [pc, #84] @ (8001478 <HAL_TIM_Base_MspInit+0x68>)
|
|
8001424: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001426: 4a14 ldr r2, [pc, #80] @ (8001478 <HAL_TIM_Base_MspInit+0x68>)
|
|
8001428: f043 0301 orr.w r3, r3, #1
|
|
800142c: 6593 str r3, [r2, #88] @ 0x58
|
|
800142e: 4b12 ldr r3, [pc, #72] @ (8001478 <HAL_TIM_Base_MspInit+0x68>)
|
|
8001430: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001432: f003 0301 and.w r3, r3, #1
|
|
8001436: 60fb str r3, [r7, #12]
|
|
8001438: 68fb ldr r3, [r7, #12]
|
|
/* TIM2 interrupt Init */
|
|
HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
|
|
800143a: 2200 movs r2, #0
|
|
800143c: 2100 movs r1, #0
|
|
800143e: 201c movs r0, #28
|
|
8001440: f001 ff3f bl 80032c2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM2_IRQn);
|
|
8001444: 201c movs r0, #28
|
|
8001446: f001 ff56 bl 80032f6 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN TIM16_MspInit 1 */
|
|
|
|
/* USER CODE END TIM16_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
800144a: e010 b.n 800146e <HAL_TIM_Base_MspInit+0x5e>
|
|
else if(htim_base->Instance==TIM16)
|
|
800144c: 687b ldr r3, [r7, #4]
|
|
800144e: 681b ldr r3, [r3, #0]
|
|
8001450: 4a0a ldr r2, [pc, #40] @ (800147c <HAL_TIM_Base_MspInit+0x6c>)
|
|
8001452: 4293 cmp r3, r2
|
|
8001454: d10b bne.n 800146e <HAL_TIM_Base_MspInit+0x5e>
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
8001456: 4b08 ldr r3, [pc, #32] @ (8001478 <HAL_TIM_Base_MspInit+0x68>)
|
|
8001458: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800145a: 4a07 ldr r2, [pc, #28] @ (8001478 <HAL_TIM_Base_MspInit+0x68>)
|
|
800145c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001460: 6613 str r3, [r2, #96] @ 0x60
|
|
8001462: 4b05 ldr r3, [pc, #20] @ (8001478 <HAL_TIM_Base_MspInit+0x68>)
|
|
8001464: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001466: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800146a: 60bb str r3, [r7, #8]
|
|
800146c: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800146e: bf00 nop
|
|
8001470: 3710 adds r7, #16
|
|
8001472: 46bd mov sp, r7
|
|
8001474: bd80 pop {r7, pc}
|
|
8001476: bf00 nop
|
|
8001478: 40021000 .word 0x40021000
|
|
800147c: 40014400 .word 0x40014400
|
|
|
|
08001480 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8001480: b580 push {r7, lr}
|
|
8001482: b088 sub sp, #32
|
|
8001484: af00 add r7, sp, #0
|
|
8001486: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001488: f107 030c add.w r3, r7, #12
|
|
800148c: 2200 movs r2, #0
|
|
800148e: 601a str r2, [r3, #0]
|
|
8001490: 605a str r2, [r3, #4]
|
|
8001492: 609a str r2, [r3, #8]
|
|
8001494: 60da str r2, [r3, #12]
|
|
8001496: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM16)
|
|
8001498: 687b ldr r3, [r7, #4]
|
|
800149a: 681b ldr r3, [r3, #0]
|
|
800149c: 4a12 ldr r2, [pc, #72] @ (80014e8 <HAL_TIM_MspPostInit+0x68>)
|
|
800149e: 4293 cmp r3, r2
|
|
80014a0: d11d bne.n 80014de <HAL_TIM_MspPostInit+0x5e>
|
|
{
|
|
/* USER CODE BEGIN TIM16_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM16_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80014a2: 4b12 ldr r3, [pc, #72] @ (80014ec <HAL_TIM_MspPostInit+0x6c>)
|
|
80014a4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80014a6: 4a11 ldr r2, [pc, #68] @ (80014ec <HAL_TIM_MspPostInit+0x6c>)
|
|
80014a8: f043 0301 orr.w r3, r3, #1
|
|
80014ac: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80014ae: 4b0f ldr r3, [pc, #60] @ (80014ec <HAL_TIM_MspPostInit+0x6c>)
|
|
80014b0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80014b2: f003 0301 and.w r3, r3, #1
|
|
80014b6: 60bb str r3, [r7, #8]
|
|
80014b8: 68bb ldr r3, [r7, #8]
|
|
/**TIM16 GPIO Configuration
|
|
PA12 ------> TIM16_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
80014ba: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80014be: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80014c0: 2302 movs r3, #2
|
|
80014c2: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80014c4: 2300 movs r3, #0
|
|
80014c6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80014c8: 2300 movs r3, #0
|
|
80014ca: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM16;
|
|
80014cc: 2301 movs r3, #1
|
|
80014ce: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80014d0: f107 030c add.w r3, r7, #12
|
|
80014d4: 4619 mov r1, r3
|
|
80014d6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80014da: f001 ffe7 bl 80034ac <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM16_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM16_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
80014de: bf00 nop
|
|
80014e0: 3720 adds r7, #32
|
|
80014e2: 46bd mov sp, r7
|
|
80014e4: bd80 pop {r7, pc}
|
|
80014e6: bf00 nop
|
|
80014e8: 40014400 .word 0x40014400
|
|
80014ec: 40021000 .word 0x40021000
|
|
|
|
080014f0 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
80014f0: b580 push {r7, lr}
|
|
80014f2: b09a sub sp, #104 @ 0x68
|
|
80014f4: af00 add r7, sp, #0
|
|
80014f6: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80014f8: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
80014fc: 2200 movs r2, #0
|
|
80014fe: 601a str r2, [r3, #0]
|
|
8001500: 605a str r2, [r3, #4]
|
|
8001502: 609a str r2, [r3, #8]
|
|
8001504: 60da str r2, [r3, #12]
|
|
8001506: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8001508: f107 0310 add.w r3, r7, #16
|
|
800150c: 2244 movs r2, #68 @ 0x44
|
|
800150e: 2100 movs r1, #0
|
|
8001510: 4618 mov r0, r3
|
|
8001512: f006 fd37 bl 8007f84 <memset>
|
|
if(huart->Instance==USART2)
|
|
8001516: 687b ldr r3, [r7, #4]
|
|
8001518: 681b ldr r3, [r3, #0]
|
|
800151a: 4a23 ldr r2, [pc, #140] @ (80015a8 <HAL_UART_MspInit+0xb8>)
|
|
800151c: 4293 cmp r3, r2
|
|
800151e: d13e bne.n 800159e <HAL_UART_MspInit+0xae>
|
|
|
|
/* USER CODE END USART2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
|
|
8001520: 2302 movs r3, #2
|
|
8001522: 613b str r3, [r7, #16]
|
|
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
|
|
8001524: 2300 movs r3, #0
|
|
8001526: 61bb str r3, [r7, #24]
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8001528: f107 0310 add.w r3, r7, #16
|
|
800152c: 4618 mov r0, r3
|
|
800152e: f002 ff39 bl 80043a4 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001532: 4603 mov r3, r0
|
|
8001534: 2b00 cmp r3, #0
|
|
8001536: d001 beq.n 800153c <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8001538: f7ff feb4 bl 80012a4 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
800153c: 4b1b ldr r3, [pc, #108] @ (80015ac <HAL_UART_MspInit+0xbc>)
|
|
800153e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001540: 4a1a ldr r2, [pc, #104] @ (80015ac <HAL_UART_MspInit+0xbc>)
|
|
8001542: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
8001546: 6593 str r3, [r2, #88] @ 0x58
|
|
8001548: 4b18 ldr r3, [pc, #96] @ (80015ac <HAL_UART_MspInit+0xbc>)
|
|
800154a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800154c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001550: 60fb str r3, [r7, #12]
|
|
8001552: 68fb ldr r3, [r7, #12]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001554: 4b15 ldr r3, [pc, #84] @ (80015ac <HAL_UART_MspInit+0xbc>)
|
|
8001556: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001558: 4a14 ldr r2, [pc, #80] @ (80015ac <HAL_UART_MspInit+0xbc>)
|
|
800155a: f043 0301 orr.w r3, r3, #1
|
|
800155e: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001560: 4b12 ldr r3, [pc, #72] @ (80015ac <HAL_UART_MspInit+0xbc>)
|
|
8001562: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001564: f003 0301 and.w r3, r3, #1
|
|
8001568: 60bb str r3, [r7, #8]
|
|
800156a: 68bb ldr r3, [r7, #8]
|
|
/**USART2 GPIO Configuration
|
|
PA2 ------> USART2_TX
|
|
PA3 ------> USART2_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin;
|
|
800156c: 230c movs r3, #12
|
|
800156e: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001570: 2302 movs r3, #2
|
|
8001572: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001574: 2300 movs r3, #0
|
|
8001576: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001578: 2300 movs r3, #0
|
|
800157a: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
800157c: 2307 movs r3, #7
|
|
800157e: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001580: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001584: 4619 mov r1, r3
|
|
8001586: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800158a: f001 ff8f bl 80034ac <HAL_GPIO_Init>
|
|
|
|
/* USART2 interrupt Init */
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
|
|
800158e: 2200 movs r2, #0
|
|
8001590: 2100 movs r1, #0
|
|
8001592: 2026 movs r0, #38 @ 0x26
|
|
8001594: f001 fe95 bl 80032c2 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
8001598: 2026 movs r0, #38 @ 0x26
|
|
800159a: f001 feac bl 80032f6 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800159e: bf00 nop
|
|
80015a0: 3768 adds r7, #104 @ 0x68
|
|
80015a2: 46bd mov sp, r7
|
|
80015a4: bd80 pop {r7, pc}
|
|
80015a6: bf00 nop
|
|
80015a8: 40004400 .word 0x40004400
|
|
80015ac: 40021000 .word 0x40021000
|
|
|
|
080015b0 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
80015b0: b480 push {r7}
|
|
80015b2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80015b4: bf00 nop
|
|
80015b6: e7fd b.n 80015b4 <NMI_Handler+0x4>
|
|
|
|
080015b8 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
80015b8: b480 push {r7}
|
|
80015ba: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80015bc: bf00 nop
|
|
80015be: e7fd b.n 80015bc <HardFault_Handler+0x4>
|
|
|
|
080015c0 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
80015c0: b480 push {r7}
|
|
80015c2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
80015c4: bf00 nop
|
|
80015c6: e7fd b.n 80015c4 <MemManage_Handler+0x4>
|
|
|
|
080015c8 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
80015c8: b480 push {r7}
|
|
80015ca: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
80015cc: bf00 nop
|
|
80015ce: e7fd b.n 80015cc <BusFault_Handler+0x4>
|
|
|
|
080015d0 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
80015d0: b480 push {r7}
|
|
80015d2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
80015d4: bf00 nop
|
|
80015d6: e7fd b.n 80015d4 <UsageFault_Handler+0x4>
|
|
|
|
080015d8 <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
80015d8: b480 push {r7}
|
|
80015da: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
80015dc: bf00 nop
|
|
80015de: 46bd mov sp, r7
|
|
80015e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015e4: 4770 bx lr
|
|
|
|
080015e6 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
80015e6: b480 push {r7}
|
|
80015e8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
80015ea: bf00 nop
|
|
80015ec: 46bd mov sp, r7
|
|
80015ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015f2: 4770 bx lr
|
|
|
|
080015f4 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
80015f4: b480 push {r7}
|
|
80015f6: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
80015f8: bf00 nop
|
|
80015fa: 46bd mov sp, r7
|
|
80015fc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001600: 4770 bx lr
|
|
|
|
08001602 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8001602: b580 push {r7, lr}
|
|
8001604: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8001606: f000 f8a5 bl 8001754 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
800160a: bf00 nop
|
|
800160c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08001610 <TIM2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM2 global interrupt.
|
|
*/
|
|
void TIM2_IRQHandler(void)
|
|
{
|
|
8001610: b580 push {r7, lr}
|
|
8001612: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM2_IRQn 0 */
|
|
|
|
/* USER CODE END TIM2_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim2);
|
|
8001614: 4802 ldr r0, [pc, #8] @ (8001620 <TIM2_IRQHandler+0x10>)
|
|
8001616: f003 fa6d bl 8004af4 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM2_IRQn 1 */
|
|
|
|
/* USER CODE END TIM2_IRQn 1 */
|
|
}
|
|
800161a: bf00 nop
|
|
800161c: bd80 pop {r7, pc}
|
|
800161e: bf00 nop
|
|
8001620: 2000011c .word 0x2000011c
|
|
|
|
08001624 <USART2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
|
|
*/
|
|
void USART2_IRQHandler(void)
|
|
{
|
|
8001624: b580 push {r7, lr}
|
|
8001626: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
|
|
|
/* USER CODE END USART2_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart2);
|
|
8001628: 4802 ldr r0, [pc, #8] @ (8001634 <USART2_IRQHandler+0x10>)
|
|
800162a: f004 fcc5 bl 8005fb8 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
|
|
|
/* USER CODE END USART2_IRQn 1 */
|
|
}
|
|
800162e: bf00 nop
|
|
8001630: bd80 pop {r7, pc}
|
|
8001632: bf00 nop
|
|
8001634: 200001b4 .word 0x200001b4
|
|
|
|
08001638 <SystemInit>:
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8001638: b480 push {r7}
|
|
800163a: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
|
|
800163c: 4b06 ldr r3, [pc, #24] @ (8001658 <SystemInit+0x20>)
|
|
800163e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8001642: 4a05 ldr r2, [pc, #20] @ (8001658 <SystemInit+0x20>)
|
|
8001644: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8001648: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
800164c: bf00 nop
|
|
800164e: 46bd mov sp, r7
|
|
8001650: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001654: 4770 bx lr
|
|
8001656: bf00 nop
|
|
8001658: e000ed00 .word 0xe000ed00
|
|
|
|
0800165c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
800165c: 480d ldr r0, [pc, #52] @ (8001694 <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
800165e: 4685 mov sp, r0
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001660: f7ff ffea bl 8001638 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001664: 480c ldr r0, [pc, #48] @ (8001698 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8001666: 490d ldr r1, [pc, #52] @ (800169c <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8001668: 4a0d ldr r2, [pc, #52] @ (80016a0 <LoopForever+0xe>)
|
|
movs r3, #0
|
|
800166a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800166c: e002 b.n 8001674 <LoopCopyDataInit>
|
|
|
|
0800166e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800166e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001670: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001672: 3304 adds r3, #4
|
|
|
|
08001674 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001674: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001676: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001678: d3f9 bcc.n 800166e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800167a: 4a0a ldr r2, [pc, #40] @ (80016a4 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
800167c: 4c0a ldr r4, [pc, #40] @ (80016a8 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
800167e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001680: e001 b.n 8001686 <LoopFillZerobss>
|
|
|
|
08001682 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001682: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001684: 3204 adds r2, #4
|
|
|
|
08001686 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001686: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001688: d3fb bcc.n 8001682 <FillZerobss>
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800168a: f006 fc83 bl 8007f94 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800168e: f7fe ff59 bl 8000544 <main>
|
|
|
|
08001692 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8001692: e7fe b.n 8001692 <LoopForever>
|
|
ldr r0, =_estack
|
|
8001694: 20008000 .word 0x20008000
|
|
ldr r0, =_sdata
|
|
8001698: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800169c: 20000028 .word 0x20000028
|
|
ldr r2, =_sidata
|
|
80016a0: 08008078 .word 0x08008078
|
|
ldr r2, =_sbss
|
|
80016a4: 20000028 .word 0x20000028
|
|
ldr r4, =_ebss
|
|
80016a8: 20000360 .word 0x20000360
|
|
|
|
080016ac <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
80016ac: e7fe b.n 80016ac <ADC1_2_IRQHandler>
|
|
|
|
080016ae <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
80016ae: b580 push {r7, lr}
|
|
80016b0: b082 sub sp, #8
|
|
80016b2: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80016b4: 2300 movs r3, #0
|
|
80016b6: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80016b8: 2003 movs r0, #3
|
|
80016ba: f001 fdf7 bl 80032ac <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
80016be: 2000 movs r0, #0
|
|
80016c0: f000 f80e bl 80016e0 <HAL_InitTick>
|
|
80016c4: 4603 mov r3, r0
|
|
80016c6: 2b00 cmp r3, #0
|
|
80016c8: d002 beq.n 80016d0 <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
80016ca: 2301 movs r3, #1
|
|
80016cc: 71fb strb r3, [r7, #7]
|
|
80016ce: e001 b.n 80016d4 <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80016d0: f7ff fdee bl 80012b0 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80016d4: 79fb ldrb r3, [r7, #7]
|
|
|
|
}
|
|
80016d6: 4618 mov r0, r3
|
|
80016d8: 3708 adds r7, #8
|
|
80016da: 46bd mov sp, r7
|
|
80016dc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080016e0 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80016e0: b580 push {r7, lr}
|
|
80016e2: b084 sub sp, #16
|
|
80016e4: af00 add r7, sp, #0
|
|
80016e6: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80016e8: 2300 movs r3, #0
|
|
80016ea: 73fb strb r3, [r7, #15]
|
|
|
|
if (uwTickFreq != 0U)
|
|
80016ec: 4b16 ldr r3, [pc, #88] @ (8001748 <HAL_InitTick+0x68>)
|
|
80016ee: 681b ldr r3, [r3, #0]
|
|
80016f0: 2b00 cmp r3, #0
|
|
80016f2: d022 beq.n 800173a <HAL_InitTick+0x5a>
|
|
{
|
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
|
|
80016f4: 4b15 ldr r3, [pc, #84] @ (800174c <HAL_InitTick+0x6c>)
|
|
80016f6: 681a ldr r2, [r3, #0]
|
|
80016f8: 4b13 ldr r3, [pc, #76] @ (8001748 <HAL_InitTick+0x68>)
|
|
80016fa: 681b ldr r3, [r3, #0]
|
|
80016fc: f44f 717a mov.w r1, #1000 @ 0x3e8
|
|
8001700: fbb1 f3f3 udiv r3, r1, r3
|
|
8001704: fbb2 f3f3 udiv r3, r2, r3
|
|
8001708: 4618 mov r0, r3
|
|
800170a: f001 fe02 bl 8003312 <HAL_SYSTICK_Config>
|
|
800170e: 4603 mov r3, r0
|
|
8001710: 2b00 cmp r3, #0
|
|
8001712: d10f bne.n 8001734 <HAL_InitTick+0x54>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001714: 687b ldr r3, [r7, #4]
|
|
8001716: 2b0f cmp r3, #15
|
|
8001718: d809 bhi.n 800172e <HAL_InitTick+0x4e>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
800171a: 2200 movs r2, #0
|
|
800171c: 6879 ldr r1, [r7, #4]
|
|
800171e: f04f 30ff mov.w r0, #4294967295
|
|
8001722: f001 fdce bl 80032c2 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001726: 4a0a ldr r2, [pc, #40] @ (8001750 <HAL_InitTick+0x70>)
|
|
8001728: 687b ldr r3, [r7, #4]
|
|
800172a: 6013 str r3, [r2, #0]
|
|
800172c: e007 b.n 800173e <HAL_InitTick+0x5e>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800172e: 2301 movs r3, #1
|
|
8001730: 73fb strb r3, [r7, #15]
|
|
8001732: e004 b.n 800173e <HAL_InitTick+0x5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8001734: 2301 movs r3, #1
|
|
8001736: 73fb strb r3, [r7, #15]
|
|
8001738: e001 b.n 800173e <HAL_InitTick+0x5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800173a: 2301 movs r3, #1
|
|
800173c: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
800173e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8001740: 4618 mov r0, r3
|
|
8001742: 3710 adds r7, #16
|
|
8001744: 46bd mov sp, r7
|
|
8001746: bd80 pop {r7, pc}
|
|
8001748: 20000024 .word 0x20000024
|
|
800174c: 2000001c .word 0x2000001c
|
|
8001750: 20000020 .word 0x20000020
|
|
|
|
08001754 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8001754: b480 push {r7}
|
|
8001756: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
8001758: 4b05 ldr r3, [pc, #20] @ (8001770 <HAL_IncTick+0x1c>)
|
|
800175a: 681a ldr r2, [r3, #0]
|
|
800175c: 4b05 ldr r3, [pc, #20] @ (8001774 <HAL_IncTick+0x20>)
|
|
800175e: 681b ldr r3, [r3, #0]
|
|
8001760: 4413 add r3, r2
|
|
8001762: 4a03 ldr r2, [pc, #12] @ (8001770 <HAL_IncTick+0x1c>)
|
|
8001764: 6013 str r3, [r2, #0]
|
|
}
|
|
8001766: bf00 nop
|
|
8001768: 46bd mov sp, r7
|
|
800176a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800176e: 4770 bx lr
|
|
8001770: 2000035c .word 0x2000035c
|
|
8001774: 20000024 .word 0x20000024
|
|
|
|
08001778 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8001778: b480 push {r7}
|
|
800177a: af00 add r7, sp, #0
|
|
return uwTick;
|
|
800177c: 4b03 ldr r3, [pc, #12] @ (800178c <HAL_GetTick+0x14>)
|
|
800177e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8001780: 4618 mov r0, r3
|
|
8001782: 46bd mov sp, r7
|
|
8001784: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001788: 4770 bx lr
|
|
800178a: bf00 nop
|
|
800178c: 2000035c .word 0x2000035c
|
|
|
|
08001790 <LL_ADC_SetCommonClock>:
|
|
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
|
|
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
|
|
{
|
|
8001790: b480 push {r7}
|
|
8001792: b083 sub sp, #12
|
|
8001794: af00 add r7, sp, #0
|
|
8001796: 6078 str r0, [r7, #4]
|
|
8001798: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
|
|
800179a: 687b ldr r3, [r7, #4]
|
|
800179c: 689b ldr r3, [r3, #8]
|
|
800179e: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000
|
|
80017a2: 683b ldr r3, [r7, #0]
|
|
80017a4: 431a orrs r2, r3
|
|
80017a6: 687b ldr r3, [r7, #4]
|
|
80017a8: 609a str r2, [r3, #8]
|
|
}
|
|
80017aa: bf00 nop
|
|
80017ac: 370c adds r7, #12
|
|
80017ae: 46bd mov sp, r7
|
|
80017b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80017b4: 4770 bx lr
|
|
|
|
080017b6 <LL_ADC_SetCommonPathInternalCh>:
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
|
|
{
|
|
80017b6: b480 push {r7}
|
|
80017b8: b083 sub sp, #12
|
|
80017ba: af00 add r7, sp, #0
|
|
80017bc: 6078 str r0, [r7, #4]
|
|
80017be: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
|
|
80017c0: 687b ldr r3, [r7, #4]
|
|
80017c2: 689b ldr r3, [r3, #8]
|
|
80017c4: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000
|
|
80017c8: 683b ldr r3, [r7, #0]
|
|
80017ca: 431a orrs r2, r3
|
|
80017cc: 687b ldr r3, [r7, #4]
|
|
80017ce: 609a str r2, [r3, #8]
|
|
}
|
|
80017d0: bf00 nop
|
|
80017d2: 370c adds r7, #12
|
|
80017d4: 46bd mov sp, r7
|
|
80017d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80017da: 4770 bx lr
|
|
|
|
080017dc <LL_ADC_GetCommonPathInternalCh>:
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
|
|
{
|
|
80017dc: b480 push {r7}
|
|
80017de: b083 sub sp, #12
|
|
80017e0: af00 add r7, sp, #0
|
|
80017e2: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
|
|
80017e4: 687b ldr r3, [r7, #4]
|
|
80017e6: 689b ldr r3, [r3, #8]
|
|
80017e8: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000
|
|
}
|
|
80017ec: 4618 mov r0, r3
|
|
80017ee: 370c adds r7, #12
|
|
80017f0: 46bd mov sp, r7
|
|
80017f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80017f6: 4770 bx lr
|
|
|
|
080017f8 <LL_ADC_SetOffset>:
|
|
* (fADC) to convert in 12-bit resolution.\n
|
|
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
|
|
{
|
|
80017f8: b480 push {r7}
|
|
80017fa: b087 sub sp, #28
|
|
80017fc: af00 add r7, sp, #0
|
|
80017fe: 60f8 str r0, [r7, #12]
|
|
8001800: 60b9 str r1, [r7, #8]
|
|
8001802: 607a str r2, [r7, #4]
|
|
8001804: 603b str r3, [r7, #0]
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
8001806: 68fb ldr r3, [r7, #12]
|
|
8001808: 3360 adds r3, #96 @ 0x60
|
|
800180a: 461a mov r2, r3
|
|
800180c: 68bb ldr r3, [r7, #8]
|
|
800180e: 009b lsls r3, r3, #2
|
|
8001810: 4413 add r3, r2
|
|
8001812: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
8001814: 697b ldr r3, [r7, #20]
|
|
8001816: 681a ldr r2, [r3, #0]
|
|
8001818: 4b08 ldr r3, [pc, #32] @ (800183c <LL_ADC_SetOffset+0x44>)
|
|
800181a: 4013 ands r3, r2
|
|
800181c: 687a ldr r2, [r7, #4]
|
|
800181e: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000
|
|
8001822: 683a ldr r2, [r7, #0]
|
|
8001824: 430a orrs r2, r1
|
|
8001826: 4313 orrs r3, r2
|
|
8001828: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
|
|
800182c: 697b ldr r3, [r7, #20]
|
|
800182e: 601a str r2, [r3, #0]
|
|
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
|
|
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
|
|
}
|
|
8001830: bf00 nop
|
|
8001832: 371c adds r7, #28
|
|
8001834: 46bd mov sp, r7
|
|
8001836: f85d 7b04 ldr.w r7, [sp], #4
|
|
800183a: 4770 bx lr
|
|
800183c: 03fff000 .word 0x03fff000
|
|
|
|
08001840 <LL_ADC_GetOffsetChannel>:
|
|
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
|
|
* comparison with internal channel parameter to be done
|
|
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
|
|
{
|
|
8001840: b480 push {r7}
|
|
8001842: b085 sub sp, #20
|
|
8001844: af00 add r7, sp, #0
|
|
8001846: 6078 str r0, [r7, #4]
|
|
8001848: 6039 str r1, [r7, #0]
|
|
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
800184a: 687b ldr r3, [r7, #4]
|
|
800184c: 3360 adds r3, #96 @ 0x60
|
|
800184e: 461a mov r2, r3
|
|
8001850: 683b ldr r3, [r7, #0]
|
|
8001852: 009b lsls r3, r3, #2
|
|
8001854: 4413 add r3, r2
|
|
8001856: 60fb str r3, [r7, #12]
|
|
|
|
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
|
|
8001858: 68fb ldr r3, [r7, #12]
|
|
800185a: 681b ldr r3, [r3, #0]
|
|
800185c: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
|
|
}
|
|
8001860: 4618 mov r0, r3
|
|
8001862: 3714 adds r7, #20
|
|
8001864: 46bd mov sp, r7
|
|
8001866: f85d 7b04 ldr.w r7, [sp], #4
|
|
800186a: 4770 bx lr
|
|
|
|
0800186c <LL_ADC_SetOffsetState>:
|
|
* @arg @ref LL_ADC_OFFSET_DISABLE
|
|
* @arg @ref LL_ADC_OFFSET_ENABLE
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
|
|
{
|
|
800186c: b480 push {r7}
|
|
800186e: b087 sub sp, #28
|
|
8001870: af00 add r7, sp, #0
|
|
8001872: 60f8 str r0, [r7, #12]
|
|
8001874: 60b9 str r1, [r7, #8]
|
|
8001876: 607a str r2, [r7, #4]
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
8001878: 68fb ldr r3, [r7, #12]
|
|
800187a: 3360 adds r3, #96 @ 0x60
|
|
800187c: 461a mov r2, r3
|
|
800187e: 68bb ldr r3, [r7, #8]
|
|
8001880: 009b lsls r3, r3, #2
|
|
8001882: 4413 add r3, r2
|
|
8001884: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
8001886: 697b ldr r3, [r7, #20]
|
|
8001888: 681b ldr r3, [r3, #0]
|
|
800188a: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
800188e: 687b ldr r3, [r7, #4]
|
|
8001890: 431a orrs r2, r3
|
|
8001892: 697b ldr r3, [r7, #20]
|
|
8001894: 601a str r2, [r3, #0]
|
|
ADC_OFR1_OFFSET1_EN,
|
|
OffsetState);
|
|
}
|
|
8001896: bf00 nop
|
|
8001898: 371c adds r7, #28
|
|
800189a: 46bd mov sp, r7
|
|
800189c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018a0: 4770 bx lr
|
|
|
|
080018a2 <LL_ADC_SetOffsetSign>:
|
|
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
|
|
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
|
|
{
|
|
80018a2: b480 push {r7}
|
|
80018a4: b087 sub sp, #28
|
|
80018a6: af00 add r7, sp, #0
|
|
80018a8: 60f8 str r0, [r7, #12]
|
|
80018aa: 60b9 str r1, [r7, #8]
|
|
80018ac: 607a str r2, [r7, #4]
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
80018ae: 68fb ldr r3, [r7, #12]
|
|
80018b0: 3360 adds r3, #96 @ 0x60
|
|
80018b2: 461a mov r2, r3
|
|
80018b4: 68bb ldr r3, [r7, #8]
|
|
80018b6: 009b lsls r3, r3, #2
|
|
80018b8: 4413 add r3, r2
|
|
80018ba: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
80018bc: 697b ldr r3, [r7, #20]
|
|
80018be: 681b ldr r3, [r3, #0]
|
|
80018c0: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
|
|
80018c4: 687b ldr r3, [r7, #4]
|
|
80018c6: 431a orrs r2, r3
|
|
80018c8: 697b ldr r3, [r7, #20]
|
|
80018ca: 601a str r2, [r3, #0]
|
|
ADC_OFR1_OFFSETPOS,
|
|
OffsetSign);
|
|
}
|
|
80018cc: bf00 nop
|
|
80018ce: 371c adds r7, #28
|
|
80018d0: 46bd mov sp, r7
|
|
80018d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80018d6: 4770 bx lr
|
|
|
|
080018d8 <LL_ADC_SetOffsetSaturation>:
|
|
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
|
|
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
|
|
{
|
|
80018d8: b480 push {r7}
|
|
80018da: b087 sub sp, #28
|
|
80018dc: af00 add r7, sp, #0
|
|
80018de: 60f8 str r0, [r7, #12]
|
|
80018e0: 60b9 str r1, [r7, #8]
|
|
80018e2: 607a str r2, [r7, #4]
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
80018e4: 68fb ldr r3, [r7, #12]
|
|
80018e6: 3360 adds r3, #96 @ 0x60
|
|
80018e8: 461a mov r2, r3
|
|
80018ea: 68bb ldr r3, [r7, #8]
|
|
80018ec: 009b lsls r3, r3, #2
|
|
80018ee: 4413 add r3, r2
|
|
80018f0: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
80018f2: 697b ldr r3, [r7, #20]
|
|
80018f4: 681b ldr r3, [r3, #0]
|
|
80018f6: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
|
|
80018fa: 687b ldr r3, [r7, #4]
|
|
80018fc: 431a orrs r2, r3
|
|
80018fe: 697b ldr r3, [r7, #20]
|
|
8001900: 601a str r2, [r3, #0]
|
|
ADC_OFR1_SATEN,
|
|
OffsetSaturation);
|
|
}
|
|
8001902: bf00 nop
|
|
8001904: 371c adds r7, #28
|
|
8001906: 46bd mov sp, r7
|
|
8001908: f85d 7b04 ldr.w r7, [sp], #4
|
|
800190c: 4770 bx lr
|
|
|
|
0800190e <LL_ADC_SetSamplingTimeCommonConfig>:
|
|
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
|
|
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
|
|
{
|
|
800190e: b480 push {r7}
|
|
8001910: b083 sub sp, #12
|
|
8001912: af00 add r7, sp, #0
|
|
8001914: 6078 str r0, [r7, #4]
|
|
8001916: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
|
|
8001918: 687b ldr r3, [r7, #4]
|
|
800191a: 695b ldr r3, [r3, #20]
|
|
800191c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
8001920: 683b ldr r3, [r7, #0]
|
|
8001922: 431a orrs r2, r3
|
|
8001924: 687b ldr r3, [r7, #4]
|
|
8001926: 615a str r2, [r3, #20]
|
|
}
|
|
8001928: bf00 nop
|
|
800192a: 370c adds r7, #12
|
|
800192c: 46bd mov sp, r7
|
|
800192e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001932: 4770 bx lr
|
|
|
|
08001934 <LL_ADC_REG_IsTriggerSourceSWStart>:
|
|
* @param ADCx ADC instance
|
|
* @retval Value "0" if trigger source external trigger
|
|
* Value "1" if trigger source SW start.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001934: b480 push {r7}
|
|
8001936: b083 sub sp, #12
|
|
8001938: af00 add r7, sp, #0
|
|
800193a: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
|
|
800193c: 687b ldr r3, [r7, #4]
|
|
800193e: 68db ldr r3, [r3, #12]
|
|
8001940: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
8001944: 2b00 cmp r3, #0
|
|
8001946: d101 bne.n 800194c <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
|
|
8001948: 2301 movs r3, #1
|
|
800194a: e000 b.n 800194e <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
|
|
800194c: 2300 movs r3, #0
|
|
}
|
|
800194e: 4618 mov r0, r3
|
|
8001950: 370c adds r7, #12
|
|
8001952: 46bd mov sp, r7
|
|
8001954: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001958: 4770 bx lr
|
|
|
|
0800195a <LL_ADC_REG_SetSequencerRanks>:
|
|
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
|
|
* (fADC) to convert in 12-bit resolution.\n
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
|
|
{
|
|
800195a: b480 push {r7}
|
|
800195c: b087 sub sp, #28
|
|
800195e: af00 add r7, sp, #0
|
|
8001960: 60f8 str r0, [r7, #12]
|
|
8001962: 60b9 str r1, [r7, #8]
|
|
8001964: 607a str r2, [r7, #4]
|
|
/* Set bits with content of parameter "Channel" with bits position */
|
|
/* in register and register position depending on parameter "Rank". */
|
|
/* Parameters "Rank" and "Channel" are used with masks because containing */
|
|
/* other bits reserved for other purpose. */
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
|
|
8001966: 68fb ldr r3, [r7, #12]
|
|
8001968: 3330 adds r3, #48 @ 0x30
|
|
800196a: 461a mov r2, r3
|
|
800196c: 68bb ldr r3, [r7, #8]
|
|
800196e: 0a1b lsrs r3, r3, #8
|
|
8001970: 009b lsls r3, r3, #2
|
|
8001972: f003 030c and.w r3, r3, #12
|
|
8001976: 4413 add r3, r2
|
|
8001978: 617b str r3, [r7, #20]
|
|
((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
|
|
|
|
MODIFY_REG(*preg,
|
|
800197a: 697b ldr r3, [r7, #20]
|
|
800197c: 681a ldr r2, [r3, #0]
|
|
800197e: 68bb ldr r3, [r7, #8]
|
|
8001980: f003 031f and.w r3, r3, #31
|
|
8001984: 211f movs r1, #31
|
|
8001986: fa01 f303 lsl.w r3, r1, r3
|
|
800198a: 43db mvns r3, r3
|
|
800198c: 401a ands r2, r3
|
|
800198e: 687b ldr r3, [r7, #4]
|
|
8001990: 0e9b lsrs r3, r3, #26
|
|
8001992: f003 011f and.w r1, r3, #31
|
|
8001996: 68bb ldr r3, [r7, #8]
|
|
8001998: f003 031f and.w r3, r3, #31
|
|
800199c: fa01 f303 lsl.w r3, r1, r3
|
|
80019a0: 431a orrs r2, r3
|
|
80019a2: 697b ldr r3, [r7, #20]
|
|
80019a4: 601a str r2, [r3, #0]
|
|
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
|
|
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
|
|
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
|
|
}
|
|
80019a6: bf00 nop
|
|
80019a8: 371c adds r7, #28
|
|
80019aa: 46bd mov sp, r7
|
|
80019ac: f85d 7b04 ldr.w r7, [sp], #4
|
|
80019b0: 4770 bx lr
|
|
|
|
080019b2 <LL_ADC_SetChannelSamplingTime>:
|
|
* can be replaced by 3.5 ADC clock cycles.
|
|
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
|
|
{
|
|
80019b2: b480 push {r7}
|
|
80019b4: b087 sub sp, #28
|
|
80019b6: af00 add r7, sp, #0
|
|
80019b8: 60f8 str r0, [r7, #12]
|
|
80019ba: 60b9 str r1, [r7, #8]
|
|
80019bc: 607a str r2, [r7, #4]
|
|
/* Set bits with content of parameter "SamplingTime" with bits position */
|
|
/* in register and register position depending on parameter "Channel". */
|
|
/* Parameter "Channel" is used with masks because containing */
|
|
/* other bits reserved for other purpose. */
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
|
|
80019be: 68fb ldr r3, [r7, #12]
|
|
80019c0: 3314 adds r3, #20
|
|
80019c2: 461a mov r2, r3
|
|
80019c4: 68bb ldr r3, [r7, #8]
|
|
80019c6: 0e5b lsrs r3, r3, #25
|
|
80019c8: 009b lsls r3, r3, #2
|
|
80019ca: f003 0304 and.w r3, r3, #4
|
|
80019ce: 4413 add r3, r2
|
|
80019d0: 617b str r3, [r7, #20]
|
|
((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
|
|
|
|
MODIFY_REG(*preg,
|
|
80019d2: 697b ldr r3, [r7, #20]
|
|
80019d4: 681a ldr r2, [r3, #0]
|
|
80019d6: 68bb ldr r3, [r7, #8]
|
|
80019d8: 0d1b lsrs r3, r3, #20
|
|
80019da: f003 031f and.w r3, r3, #31
|
|
80019de: 2107 movs r1, #7
|
|
80019e0: fa01 f303 lsl.w r3, r1, r3
|
|
80019e4: 43db mvns r3, r3
|
|
80019e6: 401a ands r2, r3
|
|
80019e8: 68bb ldr r3, [r7, #8]
|
|
80019ea: 0d1b lsrs r3, r3, #20
|
|
80019ec: f003 031f and.w r3, r3, #31
|
|
80019f0: 6879 ldr r1, [r7, #4]
|
|
80019f2: fa01 f303 lsl.w r3, r1, r3
|
|
80019f6: 431a orrs r2, r3
|
|
80019f8: 697b ldr r3, [r7, #20]
|
|
80019fa: 601a str r2, [r3, #0]
|
|
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
|
|
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
|
|
}
|
|
80019fc: bf00 nop
|
|
80019fe: 371c adds r7, #28
|
|
8001a00: 46bd mov sp, r7
|
|
8001a02: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001a06: 4770 bx lr
|
|
|
|
08001a08 <LL_ADC_SetChannelSingleDiff>:
|
|
* @arg @ref LL_ADC_SINGLE_ENDED
|
|
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
|
|
{
|
|
8001a08: b480 push {r7}
|
|
8001a0a: b085 sub sp, #20
|
|
8001a0c: af00 add r7, sp, #0
|
|
8001a0e: 60f8 str r0, [r7, #12]
|
|
8001a10: 60b9 str r1, [r7, #8]
|
|
8001a12: 607a str r2, [r7, #4]
|
|
/* Bits of channels in single or differential mode are set only for */
|
|
/* differential mode (for single mode, mask of bits allowed to be set is */
|
|
/* shifted out of range of bits of channels in single or differential mode. */
|
|
MODIFY_REG(ADCx->DIFSEL,
|
|
8001a14: 68fb ldr r3, [r7, #12]
|
|
8001a16: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0
|
|
8001a1a: 68bb ldr r3, [r7, #8]
|
|
8001a1c: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8001a20: 43db mvns r3, r3
|
|
8001a22: 401a ands r2, r3
|
|
8001a24: 687b ldr r3, [r7, #4]
|
|
8001a26: f003 0318 and.w r3, r3, #24
|
|
8001a2a: 4908 ldr r1, [pc, #32] @ (8001a4c <LL_ADC_SetChannelSingleDiff+0x44>)
|
|
8001a2c: 40d9 lsrs r1, r3
|
|
8001a2e: 68bb ldr r3, [r7, #8]
|
|
8001a30: 400b ands r3, r1
|
|
8001a32: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8001a36: 431a orrs r2, r3
|
|
8001a38: 68fb ldr r3, [r7, #12]
|
|
8001a3a: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
|
|
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
|
|
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
|
|
& (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
|
|
}
|
|
8001a3e: bf00 nop
|
|
8001a40: 3714 adds r7, #20
|
|
8001a42: 46bd mov sp, r7
|
|
8001a44: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001a48: 4770 bx lr
|
|
8001a4a: bf00 nop
|
|
8001a4c: 0007ffff .word 0x0007ffff
|
|
|
|
08001a50 <LL_ADC_GetMultimode>:
|
|
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
|
|
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
|
|
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
|
|
{
|
|
8001a50: b480 push {r7}
|
|
8001a52: b083 sub sp, #12
|
|
8001a54: af00 add r7, sp, #0
|
|
8001a56: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
|
|
8001a58: 687b ldr r3, [r7, #4]
|
|
8001a5a: 689b ldr r3, [r3, #8]
|
|
8001a5c: f003 031f and.w r3, r3, #31
|
|
}
|
|
8001a60: 4618 mov r0, r3
|
|
8001a62: 370c adds r7, #12
|
|
8001a64: 46bd mov sp, r7
|
|
8001a66: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001a6a: 4770 bx lr
|
|
|
|
08001a6c <LL_ADC_GetMultiDMATransfer>:
|
|
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
|
|
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
|
|
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
|
|
{
|
|
8001a6c: b480 push {r7}
|
|
8001a6e: b083 sub sp, #12
|
|
8001a70: af00 add r7, sp, #0
|
|
8001a72: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
|
|
8001a74: 687b ldr r3, [r7, #4]
|
|
8001a76: 689b ldr r3, [r3, #8]
|
|
8001a78: f403 4360 and.w r3, r3, #57344 @ 0xe000
|
|
}
|
|
8001a7c: 4618 mov r0, r3
|
|
8001a7e: 370c adds r7, #12
|
|
8001a80: 46bd mov sp, r7
|
|
8001a82: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001a86: 4770 bx lr
|
|
|
|
08001a88 <LL_ADC_DisableDeepPowerDown>:
|
|
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
|
|
{
|
|
8001a88: b480 push {r7}
|
|
8001a8a: b083 sub sp, #12
|
|
8001a8c: af00 add r7, sp, #0
|
|
8001a8e: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
|
|
8001a90: 687b ldr r3, [r7, #4]
|
|
8001a92: 689b ldr r3, [r3, #8]
|
|
8001a94: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000
|
|
8001a98: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001a9c: 687a ldr r2, [r7, #4]
|
|
8001a9e: 6093 str r3, [r2, #8]
|
|
}
|
|
8001aa0: bf00 nop
|
|
8001aa2: 370c adds r7, #12
|
|
8001aa4: 46bd mov sp, r7
|
|
8001aa6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001aaa: 4770 bx lr
|
|
|
|
08001aac <LL_ADC_IsDeepPowerDownEnabled>:
|
|
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
|
|
* @param ADCx ADC instance
|
|
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001aac: b480 push {r7}
|
|
8001aae: b083 sub sp, #12
|
|
8001ab0: af00 add r7, sp, #0
|
|
8001ab2: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
|
|
8001ab4: 687b ldr r3, [r7, #4]
|
|
8001ab6: 689b ldr r3, [r3, #8]
|
|
8001ab8: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8001abc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8001ac0: d101 bne.n 8001ac6 <LL_ADC_IsDeepPowerDownEnabled+0x1a>
|
|
8001ac2: 2301 movs r3, #1
|
|
8001ac4: e000 b.n 8001ac8 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
|
|
8001ac6: 2300 movs r3, #0
|
|
}
|
|
8001ac8: 4618 mov r0, r3
|
|
8001aca: 370c adds r7, #12
|
|
8001acc: 46bd mov sp, r7
|
|
8001ace: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ad2: 4770 bx lr
|
|
|
|
08001ad4 <LL_ADC_EnableInternalRegulator>:
|
|
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
|
|
{
|
|
8001ad4: b480 push {r7}
|
|
8001ad6: b083 sub sp, #12
|
|
8001ad8: af00 add r7, sp, #0
|
|
8001ada: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8001adc: 687b ldr r3, [r7, #4]
|
|
8001ade: 689b ldr r3, [r3, #8]
|
|
8001ae0: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000
|
|
8001ae4: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001ae8: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000
|
|
8001aec: 687b ldr r3, [r7, #4]
|
|
8001aee: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADVREGEN);
|
|
}
|
|
8001af0: bf00 nop
|
|
8001af2: 370c adds r7, #12
|
|
8001af4: 46bd mov sp, r7
|
|
8001af6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001afa: 4770 bx lr
|
|
|
|
08001afc <LL_ADC_IsInternalRegulatorEnabled>:
|
|
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
|
|
* @param ADCx ADC instance
|
|
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001afc: b480 push {r7}
|
|
8001afe: b083 sub sp, #12
|
|
8001b00: af00 add r7, sp, #0
|
|
8001b02: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
|
|
8001b04: 687b ldr r3, [r7, #4]
|
|
8001b06: 689b ldr r3, [r3, #8]
|
|
8001b08: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001b0c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8001b10: d101 bne.n 8001b16 <LL_ADC_IsInternalRegulatorEnabled+0x1a>
|
|
8001b12: 2301 movs r3, #1
|
|
8001b14: e000 b.n 8001b18 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
|
|
8001b16: 2300 movs r3, #0
|
|
}
|
|
8001b18: 4618 mov r0, r3
|
|
8001b1a: 370c adds r7, #12
|
|
8001b1c: 46bd mov sp, r7
|
|
8001b1e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b22: 4770 bx lr
|
|
|
|
08001b24 <LL_ADC_Enable>:
|
|
* @rmtoll CR ADEN LL_ADC_Enable
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
|
|
{
|
|
8001b24: b480 push {r7}
|
|
8001b26: b083 sub sp, #12
|
|
8001b28: af00 add r7, sp, #0
|
|
8001b2a: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8001b2c: 687b ldr r3, [r7, #4]
|
|
8001b2e: 689b ldr r3, [r3, #8]
|
|
8001b30: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8001b34: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001b38: f043 0201 orr.w r2, r3, #1
|
|
8001b3c: 687b ldr r3, [r7, #4]
|
|
8001b3e: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADEN);
|
|
}
|
|
8001b40: bf00 nop
|
|
8001b42: 370c adds r7, #12
|
|
8001b44: 46bd mov sp, r7
|
|
8001b46: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b4a: 4770 bx lr
|
|
|
|
08001b4c <LL_ADC_Disable>:
|
|
* @rmtoll CR ADDIS LL_ADC_Disable
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
|
|
{
|
|
8001b4c: b480 push {r7}
|
|
8001b4e: b083 sub sp, #12
|
|
8001b50: af00 add r7, sp, #0
|
|
8001b52: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8001b54: 687b ldr r3, [r7, #4]
|
|
8001b56: 689b ldr r3, [r3, #8]
|
|
8001b58: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8001b5c: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001b60: f043 0202 orr.w r2, r3, #2
|
|
8001b64: 687b ldr r3, [r7, #4]
|
|
8001b66: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADDIS);
|
|
}
|
|
8001b68: bf00 nop
|
|
8001b6a: 370c adds r7, #12
|
|
8001b6c: 46bd mov sp, r7
|
|
8001b6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b72: 4770 bx lr
|
|
|
|
08001b74 <LL_ADC_IsEnabled>:
|
|
* @rmtoll CR ADEN LL_ADC_IsEnabled
|
|
* @param ADCx ADC instance
|
|
* @retval 0: ADC is disabled, 1: ADC is enabled.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001b74: b480 push {r7}
|
|
8001b76: b083 sub sp, #12
|
|
8001b78: af00 add r7, sp, #0
|
|
8001b7a: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
|
|
8001b7c: 687b ldr r3, [r7, #4]
|
|
8001b7e: 689b ldr r3, [r3, #8]
|
|
8001b80: f003 0301 and.w r3, r3, #1
|
|
8001b84: 2b01 cmp r3, #1
|
|
8001b86: d101 bne.n 8001b8c <LL_ADC_IsEnabled+0x18>
|
|
8001b88: 2301 movs r3, #1
|
|
8001b8a: e000 b.n 8001b8e <LL_ADC_IsEnabled+0x1a>
|
|
8001b8c: 2300 movs r3, #0
|
|
}
|
|
8001b8e: 4618 mov r0, r3
|
|
8001b90: 370c adds r7, #12
|
|
8001b92: 46bd mov sp, r7
|
|
8001b94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001b98: 4770 bx lr
|
|
|
|
08001b9a <LL_ADC_IsDisableOngoing>:
|
|
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no ADC disable command on going.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001b9a: b480 push {r7}
|
|
8001b9c: b083 sub sp, #12
|
|
8001b9e: af00 add r7, sp, #0
|
|
8001ba0: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
|
|
8001ba2: 687b ldr r3, [r7, #4]
|
|
8001ba4: 689b ldr r3, [r3, #8]
|
|
8001ba6: f003 0302 and.w r3, r3, #2
|
|
8001baa: 2b02 cmp r3, #2
|
|
8001bac: d101 bne.n 8001bb2 <LL_ADC_IsDisableOngoing+0x18>
|
|
8001bae: 2301 movs r3, #1
|
|
8001bb0: e000 b.n 8001bb4 <LL_ADC_IsDisableOngoing+0x1a>
|
|
8001bb2: 2300 movs r3, #0
|
|
}
|
|
8001bb4: 4618 mov r0, r3
|
|
8001bb6: 370c adds r7, #12
|
|
8001bb8: 46bd mov sp, r7
|
|
8001bba: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001bbe: 4770 bx lr
|
|
|
|
08001bc0 <LL_ADC_REG_StartConversion>:
|
|
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
|
|
{
|
|
8001bc0: b480 push {r7}
|
|
8001bc2: b083 sub sp, #12
|
|
8001bc4: af00 add r7, sp, #0
|
|
8001bc6: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8001bc8: 687b ldr r3, [r7, #4]
|
|
8001bca: 689b ldr r3, [r3, #8]
|
|
8001bcc: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8001bd0: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001bd4: f043 0204 orr.w r2, r3, #4
|
|
8001bd8: 687b ldr r3, [r7, #4]
|
|
8001bda: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADSTART);
|
|
}
|
|
8001bdc: bf00 nop
|
|
8001bde: 370c adds r7, #12
|
|
8001be0: 46bd mov sp, r7
|
|
8001be2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001be6: 4770 bx lr
|
|
|
|
08001be8 <LL_ADC_REG_StopConversion>:
|
|
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
|
|
{
|
|
8001be8: b480 push {r7}
|
|
8001bea: b083 sub sp, #12
|
|
8001bec: af00 add r7, sp, #0
|
|
8001bee: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8001bf0: 687b ldr r3, [r7, #4]
|
|
8001bf2: 689b ldr r3, [r3, #8]
|
|
8001bf4: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8001bf8: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001bfc: f043 0210 orr.w r2, r3, #16
|
|
8001c00: 687b ldr r3, [r7, #4]
|
|
8001c02: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADSTP);
|
|
}
|
|
8001c04: bf00 nop
|
|
8001c06: 370c adds r7, #12
|
|
8001c08: 46bd mov sp, r7
|
|
8001c0a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c0e: 4770 bx lr
|
|
|
|
08001c10 <LL_ADC_REG_IsConversionOngoing>:
|
|
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no conversion is on going on ADC group regular.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001c10: b480 push {r7}
|
|
8001c12: b083 sub sp, #12
|
|
8001c14: af00 add r7, sp, #0
|
|
8001c16: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
|
|
8001c18: 687b ldr r3, [r7, #4]
|
|
8001c1a: 689b ldr r3, [r3, #8]
|
|
8001c1c: f003 0304 and.w r3, r3, #4
|
|
8001c20: 2b04 cmp r3, #4
|
|
8001c22: d101 bne.n 8001c28 <LL_ADC_REG_IsConversionOngoing+0x18>
|
|
8001c24: 2301 movs r3, #1
|
|
8001c26: e000 b.n 8001c2a <LL_ADC_REG_IsConversionOngoing+0x1a>
|
|
8001c28: 2300 movs r3, #0
|
|
}
|
|
8001c2a: 4618 mov r0, r3
|
|
8001c2c: 370c adds r7, #12
|
|
8001c2e: 46bd mov sp, r7
|
|
8001c30: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c34: 4770 bx lr
|
|
|
|
08001c36 <LL_ADC_INJ_StopConversion>:
|
|
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
|
|
{
|
|
8001c36: b480 push {r7}
|
|
8001c38: b083 sub sp, #12
|
|
8001c3a: af00 add r7, sp, #0
|
|
8001c3c: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8001c3e: 687b ldr r3, [r7, #4]
|
|
8001c40: 689b ldr r3, [r3, #8]
|
|
8001c42: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8001c46: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001c4a: f043 0220 orr.w r2, r3, #32
|
|
8001c4e: 687b ldr r3, [r7, #4]
|
|
8001c50: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_JADSTP);
|
|
}
|
|
8001c52: bf00 nop
|
|
8001c54: 370c adds r7, #12
|
|
8001c56: 46bd mov sp, r7
|
|
8001c58: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c5c: 4770 bx lr
|
|
|
|
08001c5e <LL_ADC_INJ_IsConversionOngoing>:
|
|
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no conversion is on going on ADC group injected.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
|
|
{
|
|
8001c5e: b480 push {r7}
|
|
8001c60: b083 sub sp, #12
|
|
8001c62: af00 add r7, sp, #0
|
|
8001c64: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
|
|
8001c66: 687b ldr r3, [r7, #4]
|
|
8001c68: 689b ldr r3, [r3, #8]
|
|
8001c6a: f003 0308 and.w r3, r3, #8
|
|
8001c6e: 2b08 cmp r3, #8
|
|
8001c70: d101 bne.n 8001c76 <LL_ADC_INJ_IsConversionOngoing+0x18>
|
|
8001c72: 2301 movs r3, #1
|
|
8001c74: e000 b.n 8001c78 <LL_ADC_INJ_IsConversionOngoing+0x1a>
|
|
8001c76: 2300 movs r3, #0
|
|
}
|
|
8001c78: 4618 mov r0, r3
|
|
8001c7a: 370c adds r7, #12
|
|
8001c7c: 46bd mov sp, r7
|
|
8001c7e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c82: 4770 bx lr
|
|
|
|
08001c84 <HAL_ADC_Init>:
|
|
* without disabling the other ADCs.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8001c84: b590 push {r4, r7, lr}
|
|
8001c86: b089 sub sp, #36 @ 0x24
|
|
8001c88: af00 add r7, sp, #0
|
|
8001c8a: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8001c8c: 2300 movs r3, #0
|
|
8001c8e: 77fb strb r3, [r7, #31]
|
|
uint32_t tmp_cfgr;
|
|
uint32_t tmp_adc_is_conversion_on_going_regular;
|
|
uint32_t tmp_adc_is_conversion_on_going_injected;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8001c90: 2300 movs r3, #0
|
|
8001c92: 60fb str r3, [r7, #12]
|
|
|
|
/* Check ADC handle */
|
|
if (hadc == NULL)
|
|
8001c94: 687b ldr r3, [r7, #4]
|
|
8001c96: 2b00 cmp r3, #0
|
|
8001c98: d101 bne.n 8001c9e <HAL_ADC_Init+0x1a>
|
|
{
|
|
return HAL_ERROR;
|
|
8001c9a: 2301 movs r3, #1
|
|
8001c9c: e167 b.n 8001f6e <HAL_ADC_Init+0x2ea>
|
|
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
|
|
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
|
|
|
|
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
|
8001c9e: 687b ldr r3, [r7, #4]
|
|
8001ca0: 695b ldr r3, [r3, #20]
|
|
8001ca2: 2b00 cmp r3, #0
|
|
/* DISCEN and CONT bits cannot be set at the same time */
|
|
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
8001ca4: 687b ldr r3, [r7, #4]
|
|
8001ca6: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001ca8: 2b00 cmp r3, #0
|
|
8001caa: d109 bne.n 8001cc0 <HAL_ADC_Init+0x3c>
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
8001cac: 6878 ldr r0, [r7, #4]
|
|
8001cae: f7ff fb23 bl 80012f8 <HAL_ADC_MspInit>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8001cb2: 687b ldr r3, [r7, #4]
|
|
8001cb4: 2200 movs r2, #0
|
|
8001cb6: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Initialize Lock */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
8001cb8: 687b ldr r3, [r7, #4]
|
|
8001cba: 2200 movs r2, #0
|
|
8001cbc: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
}
|
|
|
|
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
|
|
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
|
|
8001cc0: 687b ldr r3, [r7, #4]
|
|
8001cc2: 681b ldr r3, [r3, #0]
|
|
8001cc4: 4618 mov r0, r3
|
|
8001cc6: f7ff fef1 bl 8001aac <LL_ADC_IsDeepPowerDownEnabled>
|
|
8001cca: 4603 mov r3, r0
|
|
8001ccc: 2b00 cmp r3, #0
|
|
8001cce: d004 beq.n 8001cda <HAL_ADC_Init+0x56>
|
|
{
|
|
/* Disable ADC deep power down mode */
|
|
LL_ADC_DisableDeepPowerDown(hadc->Instance);
|
|
8001cd0: 687b ldr r3, [r7, #4]
|
|
8001cd2: 681b ldr r3, [r3, #0]
|
|
8001cd4: 4618 mov r0, r3
|
|
8001cd6: f7ff fed7 bl 8001a88 <LL_ADC_DisableDeepPowerDown>
|
|
/* System was in deep power down mode, calibration must
|
|
be relaunched or a previously saved calibration factor
|
|
re-applied once the ADC voltage regulator is enabled */
|
|
}
|
|
|
|
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
|
|
8001cda: 687b ldr r3, [r7, #4]
|
|
8001cdc: 681b ldr r3, [r3, #0]
|
|
8001cde: 4618 mov r0, r3
|
|
8001ce0: f7ff ff0c bl 8001afc <LL_ADC_IsInternalRegulatorEnabled>
|
|
8001ce4: 4603 mov r3, r0
|
|
8001ce6: 2b00 cmp r3, #0
|
|
8001ce8: d115 bne.n 8001d16 <HAL_ADC_Init+0x92>
|
|
{
|
|
/* Enable ADC internal voltage regulator */
|
|
LL_ADC_EnableInternalRegulator(hadc->Instance);
|
|
8001cea: 687b ldr r3, [r7, #4]
|
|
8001cec: 681b ldr r3, [r3, #0]
|
|
8001cee: 4618 mov r0, r3
|
|
8001cf0: f7ff fef0 bl 8001ad4 <LL_ADC_EnableInternalRegulator>
|
|
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
8001cf4: 4ba0 ldr r3, [pc, #640] @ (8001f78 <HAL_ADC_Init+0x2f4>)
|
|
8001cf6: 681b ldr r3, [r3, #0]
|
|
8001cf8: 099b lsrs r3, r3, #6
|
|
8001cfa: 4aa0 ldr r2, [pc, #640] @ (8001f7c <HAL_ADC_Init+0x2f8>)
|
|
8001cfc: fba2 2303 umull r2, r3, r2, r3
|
|
8001d00: 099b lsrs r3, r3, #6
|
|
8001d02: 3301 adds r3, #1
|
|
8001d04: 005b lsls r3, r3, #1
|
|
8001d06: 60fb str r3, [r7, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8001d08: e002 b.n 8001d10 <HAL_ADC_Init+0x8c>
|
|
{
|
|
wait_loop_index--;
|
|
8001d0a: 68fb ldr r3, [r7, #12]
|
|
8001d0c: 3b01 subs r3, #1
|
|
8001d0e: 60fb str r3, [r7, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8001d10: 68fb ldr r3, [r7, #12]
|
|
8001d12: 2b00 cmp r3, #0
|
|
8001d14: d1f9 bne.n 8001d0a <HAL_ADC_Init+0x86>
|
|
}
|
|
|
|
/* Verification that ADC voltage regulator is correctly enabled, whether */
|
|
/* or not ADC is coming from state reset (if any potential problem of */
|
|
/* clocking, voltage regulator would not be enabled). */
|
|
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
|
|
8001d16: 687b ldr r3, [r7, #4]
|
|
8001d18: 681b ldr r3, [r3, #0]
|
|
8001d1a: 4618 mov r0, r3
|
|
8001d1c: f7ff feee bl 8001afc <LL_ADC_IsInternalRegulatorEnabled>
|
|
8001d20: 4603 mov r3, r0
|
|
8001d22: 2b00 cmp r3, #0
|
|
8001d24: d10d bne.n 8001d42 <HAL_ADC_Init+0xbe>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8001d26: 687b ldr r3, [r7, #4]
|
|
8001d28: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001d2a: f043 0210 orr.w r2, r3, #16
|
|
8001d2e: 687b ldr r3, [r7, #4]
|
|
8001d30: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8001d32: 687b ldr r3, [r7, #4]
|
|
8001d34: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001d36: f043 0201 orr.w r2, r3, #1
|
|
8001d3a: 687b ldr r3, [r7, #4]
|
|
8001d3c: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8001d3e: 2301 movs r3, #1
|
|
8001d40: 77fb strb r3, [r7, #31]
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed and if there is no conversion on going on regular */
|
|
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
|
|
/* called to update a parameter on the fly). */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
8001d42: 687b ldr r3, [r7, #4]
|
|
8001d44: 681b ldr r3, [r3, #0]
|
|
8001d46: 4618 mov r0, r3
|
|
8001d48: f7ff ff62 bl 8001c10 <LL_ADC_REG_IsConversionOngoing>
|
|
8001d4c: 6178 str r0, [r7, #20]
|
|
|
|
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
|
|
8001d4e: 687b ldr r3, [r7, #4]
|
|
8001d50: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001d52: f003 0310 and.w r3, r3, #16
|
|
8001d56: 2b00 cmp r3, #0
|
|
8001d58: f040 8100 bne.w 8001f5c <HAL_ADC_Init+0x2d8>
|
|
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
8001d5c: 697b ldr r3, [r7, #20]
|
|
8001d5e: 2b00 cmp r3, #0
|
|
8001d60: f040 80fc bne.w 8001f5c <HAL_ADC_Init+0x2d8>
|
|
)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8001d64: 687b ldr r3, [r7, #4]
|
|
8001d66: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001d68: f423 7381 bic.w r3, r3, #258 @ 0x102
|
|
8001d6c: f043 0202 orr.w r2, r3, #2
|
|
8001d70: 687b ldr r3, [r7, #4]
|
|
8001d72: 65da str r2, [r3, #92] @ 0x5c
|
|
/* Configuration of common ADC parameters */
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - clock configuration */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
8001d74: 687b ldr r3, [r7, #4]
|
|
8001d76: 681b ldr r3, [r3, #0]
|
|
8001d78: 4618 mov r0, r3
|
|
8001d7a: f7ff fefb bl 8001b74 <LL_ADC_IsEnabled>
|
|
8001d7e: 4603 mov r3, r0
|
|
8001d80: 2b00 cmp r3, #0
|
|
8001d82: d111 bne.n 8001da8 <HAL_ADC_Init+0x124>
|
|
{
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
8001d84: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
|
|
8001d88: f7ff fef4 bl 8001b74 <LL_ADC_IsEnabled>
|
|
8001d8c: 4604 mov r4, r0
|
|
8001d8e: 487c ldr r0, [pc, #496] @ (8001f80 <HAL_ADC_Init+0x2fc>)
|
|
8001d90: f7ff fef0 bl 8001b74 <LL_ADC_IsEnabled>
|
|
8001d94: 4603 mov r3, r0
|
|
8001d96: 4323 orrs r3, r4
|
|
8001d98: 2b00 cmp r3, #0
|
|
8001d9a: d105 bne.n 8001da8 <HAL_ADC_Init+0x124>
|
|
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
|
|
/* HAL_ADCEx_MultiModeConfigChannel() ) */
|
|
/* - internal measurement paths: Vbat, temperature sensor, Vref */
|
|
/* (set into HAL_ADC_ConfigChannel() or */
|
|
/* HAL_ADCEx_InjectedConfigChannel() ) */
|
|
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
|
|
8001d9c: 687b ldr r3, [r7, #4]
|
|
8001d9e: 685b ldr r3, [r3, #4]
|
|
8001da0: 4619 mov r1, r3
|
|
8001da2: 4878 ldr r0, [pc, #480] @ (8001f84 <HAL_ADC_Init+0x300>)
|
|
8001da4: f7ff fcf4 bl 8001790 <LL_ADC_SetCommonClock>
|
|
/* - external trigger polarity Init.ExternalTrigConvEdge */
|
|
/* - continuous conversion mode Init.ContinuousConvMode */
|
|
/* - overrun Init.Overrun */
|
|
/* - discontinuous mode Init.DiscontinuousConvMode */
|
|
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
|
|
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
8001da8: 687b ldr r3, [r7, #4]
|
|
8001daa: 7f5b ldrb r3, [r3, #29]
|
|
8001dac: 035a lsls r2, r3, #13
|
|
hadc->Init.Overrun |
|
|
8001dae: 687b ldr r3, [r7, #4]
|
|
8001db0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
8001db2: 431a orrs r2, r3
|
|
hadc->Init.DataAlign |
|
|
8001db4: 687b ldr r3, [r7, #4]
|
|
8001db6: 68db ldr r3, [r3, #12]
|
|
hadc->Init.Overrun |
|
|
8001db8: 431a orrs r2, r3
|
|
hadc->Init.Resolution |
|
|
8001dba: 687b ldr r3, [r7, #4]
|
|
8001dbc: 689b ldr r3, [r3, #8]
|
|
hadc->Init.DataAlign |
|
|
8001dbe: 431a orrs r2, r3
|
|
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
|
|
8001dc0: 687b ldr r3, [r7, #4]
|
|
8001dc2: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8001dc6: 041b lsls r3, r3, #16
|
|
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
8001dc8: 4313 orrs r3, r2
|
|
8001dca: 61bb str r3, [r7, #24]
|
|
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
8001dcc: 687b ldr r3, [r7, #4]
|
|
8001dce: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
|
|
8001dd2: 2b01 cmp r3, #1
|
|
8001dd4: d106 bne.n 8001de4 <HAL_ADC_Init+0x160>
|
|
{
|
|
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
|
|
8001dd6: 687b ldr r3, [r7, #4]
|
|
8001dd8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8001dda: 3b01 subs r3, #1
|
|
8001ddc: 045b lsls r3, r3, #17
|
|
8001dde: 69ba ldr r2, [r7, #24]
|
|
8001de0: 4313 orrs r3, r2
|
|
8001de2: 61bb str r3, [r7, #24]
|
|
/* Enable external trigger if trigger selection is different of software */
|
|
/* start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
8001de4: 687b ldr r3, [r7, #4]
|
|
8001de6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8001de8: 2b00 cmp r3, #0
|
|
8001dea: d009 beq.n 8001e00 <HAL_ADC_Init+0x17c>
|
|
{
|
|
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
|
|
8001dec: 687b ldr r3, [r7, #4]
|
|
8001dee: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8001df0: f403 7278 and.w r2, r3, #992 @ 0x3e0
|
|
| hadc->Init.ExternalTrigConvEdge
|
|
8001df4: 687b ldr r3, [r7, #4]
|
|
8001df6: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001df8: 4313 orrs r3, r2
|
|
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
|
|
8001dfa: 69ba ldr r2, [r7, #24]
|
|
8001dfc: 4313 orrs r3, r2
|
|
8001dfe: 61bb str r3, [r7, #24]
|
|
);
|
|
}
|
|
|
|
/* Update Configuration Register CFGR */
|
|
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
|
|
8001e00: 687b ldr r3, [r7, #4]
|
|
8001e02: 681b ldr r3, [r3, #0]
|
|
8001e04: 68da ldr r2, [r3, #12]
|
|
8001e06: 4b60 ldr r3, [pc, #384] @ (8001f88 <HAL_ADC_Init+0x304>)
|
|
8001e08: 4013 ands r3, r2
|
|
8001e0a: 687a ldr r2, [r7, #4]
|
|
8001e0c: 6812 ldr r2, [r2, #0]
|
|
8001e0e: 69b9 ldr r1, [r7, #24]
|
|
8001e10: 430b orrs r3, r1
|
|
8001e12: 60d3 str r3, [r2, #12]
|
|
|
|
/* Configuration of sampling mode */
|
|
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
|
|
8001e14: 687b ldr r3, [r7, #4]
|
|
8001e16: 681b ldr r3, [r3, #0]
|
|
8001e18: 691b ldr r3, [r3, #16]
|
|
8001e1a: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000
|
|
8001e1e: 687b ldr r3, [r7, #4]
|
|
8001e20: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8001e22: 687b ldr r3, [r7, #4]
|
|
8001e24: 681b ldr r3, [r3, #0]
|
|
8001e26: 430a orrs r2, r1
|
|
8001e28: 611a str r2, [r3, #16]
|
|
/* conversion on going on regular and injected groups: */
|
|
/* - Gain Compensation Init.GainCompensation */
|
|
/* - DMA continuous request Init.DMAContinuousRequests */
|
|
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
|
|
/* - Oversampling parameters Init.Oversampling */
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
8001e2a: 687b ldr r3, [r7, #4]
|
|
8001e2c: 681b ldr r3, [r3, #0]
|
|
8001e2e: 4618 mov r0, r3
|
|
8001e30: f7ff ff15 bl 8001c5e <LL_ADC_INJ_IsConversionOngoing>
|
|
8001e34: 6138 str r0, [r7, #16]
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
8001e36: 697b ldr r3, [r7, #20]
|
|
8001e38: 2b00 cmp r3, #0
|
|
8001e3a: d16d bne.n 8001f18 <HAL_ADC_Init+0x294>
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
8001e3c: 693b ldr r3, [r7, #16]
|
|
8001e3e: 2b00 cmp r3, #0
|
|
8001e40: d16a bne.n 8001f18 <HAL_ADC_Init+0x294>
|
|
)
|
|
{
|
|
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
|
|
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
8001e42: 687b ldr r3, [r7, #4]
|
|
8001e44: 7f1b ldrb r3, [r3, #28]
|
|
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
|
|
8001e46: 039a lsls r2, r3, #14
|
|
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
|
8001e48: 687b ldr r3, [r7, #4]
|
|
8001e4a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
8001e4e: 005b lsls r3, r3, #1
|
|
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
|
|
8001e50: 4313 orrs r3, r2
|
|
8001e52: 61bb str r3, [r7, #24]
|
|
|
|
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
|
|
8001e54: 687b ldr r3, [r7, #4]
|
|
8001e56: 681b ldr r3, [r3, #0]
|
|
8001e58: 68db ldr r3, [r3, #12]
|
|
8001e5a: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8001e5e: f023 0302 bic.w r3, r3, #2
|
|
8001e62: 687a ldr r2, [r7, #4]
|
|
8001e64: 6812 ldr r2, [r2, #0]
|
|
8001e66: 69b9 ldr r1, [r7, #24]
|
|
8001e68: 430b orrs r3, r1
|
|
8001e6a: 60d3 str r3, [r2, #12]
|
|
|
|
if (hadc->Init.GainCompensation != 0UL)
|
|
8001e6c: 687b ldr r3, [r7, #4]
|
|
8001e6e: 691b ldr r3, [r3, #16]
|
|
8001e70: 2b00 cmp r3, #0
|
|
8001e72: d017 beq.n 8001ea4 <HAL_ADC_Init+0x220>
|
|
{
|
|
SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
|
|
8001e74: 687b ldr r3, [r7, #4]
|
|
8001e76: 681b ldr r3, [r3, #0]
|
|
8001e78: 691a ldr r2, [r3, #16]
|
|
8001e7a: 687b ldr r3, [r7, #4]
|
|
8001e7c: 681b ldr r3, [r3, #0]
|
|
8001e7e: f442 3280 orr.w r2, r2, #65536 @ 0x10000
|
|
8001e82: 611a str r2, [r3, #16]
|
|
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
|
|
8001e84: 687b ldr r3, [r7, #4]
|
|
8001e86: 681b ldr r3, [r3, #0]
|
|
8001e88: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
|
|
8001e8c: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
|
|
8001e90: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001e94: 687a ldr r2, [r7, #4]
|
|
8001e96: 6911 ldr r1, [r2, #16]
|
|
8001e98: 687a ldr r2, [r7, #4]
|
|
8001e9a: 6812 ldr r2, [r2, #0]
|
|
8001e9c: 430b orrs r3, r1
|
|
8001e9e: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
|
|
8001ea2: e013 b.n 8001ecc <HAL_ADC_Init+0x248>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
|
|
8001ea4: 687b ldr r3, [r7, #4]
|
|
8001ea6: 681b ldr r3, [r3, #0]
|
|
8001ea8: 691a ldr r2, [r3, #16]
|
|
8001eaa: 687b ldr r3, [r7, #4]
|
|
8001eac: 681b ldr r3, [r3, #0]
|
|
8001eae: f422 3280 bic.w r2, r2, #65536 @ 0x10000
|
|
8001eb2: 611a str r2, [r3, #16]
|
|
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
|
|
8001eb4: 687b ldr r3, [r7, #4]
|
|
8001eb6: 681b ldr r3, [r3, #0]
|
|
8001eb8: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
|
|
8001ebc: 687a ldr r2, [r7, #4]
|
|
8001ebe: 6812 ldr r2, [r2, #0]
|
|
8001ec0: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
|
|
8001ec4: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8001ec8: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
|
|
}
|
|
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
8001ecc: 687b ldr r3, [r7, #4]
|
|
8001ece: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8001ed2: 2b01 cmp r3, #1
|
|
8001ed4: d118 bne.n 8001f08 <HAL_ADC_Init+0x284>
|
|
/* Configuration of Oversampler: */
|
|
/* - Oversampling Ratio */
|
|
/* - Right bit shift */
|
|
/* - Triggered mode */
|
|
/* - Oversampling mode (continued/resumed) */
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
8001ed6: 687b ldr r3, [r7, #4]
|
|
8001ed8: 681b ldr r3, [r3, #0]
|
|
8001eda: 691b ldr r3, [r3, #16]
|
|
8001edc: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
8001ee0: f023 0304 bic.w r3, r3, #4
|
|
8001ee4: 687a ldr r2, [r7, #4]
|
|
8001ee6: 6c51 ldr r1, [r2, #68] @ 0x44
|
|
8001ee8: 687a ldr r2, [r7, #4]
|
|
8001eea: 6c92 ldr r2, [r2, #72] @ 0x48
|
|
8001eec: 4311 orrs r1, r2
|
|
8001eee: 687a ldr r2, [r7, #4]
|
|
8001ef0: 6cd2 ldr r2, [r2, #76] @ 0x4c
|
|
8001ef2: 4311 orrs r1, r2
|
|
8001ef4: 687a ldr r2, [r7, #4]
|
|
8001ef6: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
8001ef8: 430a orrs r2, r1
|
|
8001efa: 431a orrs r2, r3
|
|
8001efc: 687b ldr r3, [r7, #4]
|
|
8001efe: 681b ldr r3, [r3, #0]
|
|
8001f00: f042 0201 orr.w r2, r2, #1
|
|
8001f04: 611a str r2, [r3, #16]
|
|
8001f06: e007 b.n 8001f18 <HAL_ADC_Init+0x294>
|
|
);
|
|
}
|
|
else
|
|
{
|
|
/* Disable ADC oversampling scope on ADC group regular */
|
|
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
|
|
8001f08: 687b ldr r3, [r7, #4]
|
|
8001f0a: 681b ldr r3, [r3, #0]
|
|
8001f0c: 691a ldr r2, [r3, #16]
|
|
8001f0e: 687b ldr r3, [r7, #4]
|
|
8001f10: 681b ldr r3, [r3, #0]
|
|
8001f12: f022 0201 bic.w r2, r2, #1
|
|
8001f16: 611a str r2, [r3, #16]
|
|
/* Note: Scan mode is not present by hardware on this device, but */
|
|
/* emulated by software for alignment over all STM32 devices. */
|
|
/* - if scan mode is enabled, regular channels sequence length is set to */
|
|
/* parameter "NbrOfConversion". */
|
|
|
|
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
|
|
8001f18: 687b ldr r3, [r7, #4]
|
|
8001f1a: 695b ldr r3, [r3, #20]
|
|
8001f1c: 2b01 cmp r3, #1
|
|
8001f1e: d10c bne.n 8001f3a <HAL_ADC_Init+0x2b6>
|
|
{
|
|
/* Set number of ranks in regular group sequencer */
|
|
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
|
|
8001f20: 687b ldr r3, [r7, #4]
|
|
8001f22: 681b ldr r3, [r3, #0]
|
|
8001f24: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001f26: f023 010f bic.w r1, r3, #15
|
|
8001f2a: 687b ldr r3, [r7, #4]
|
|
8001f2c: 6a1b ldr r3, [r3, #32]
|
|
8001f2e: 1e5a subs r2, r3, #1
|
|
8001f30: 687b ldr r3, [r7, #4]
|
|
8001f32: 681b ldr r3, [r3, #0]
|
|
8001f34: 430a orrs r2, r1
|
|
8001f36: 631a str r2, [r3, #48] @ 0x30
|
|
8001f38: e007 b.n 8001f4a <HAL_ADC_Init+0x2c6>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
|
|
8001f3a: 687b ldr r3, [r7, #4]
|
|
8001f3c: 681b ldr r3, [r3, #0]
|
|
8001f3e: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8001f40: 687b ldr r3, [r7, #4]
|
|
8001f42: 681b ldr r3, [r3, #0]
|
|
8001f44: f022 020f bic.w r2, r2, #15
|
|
8001f48: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Initialize the ADC state */
|
|
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
|
|
8001f4a: 687b ldr r3, [r7, #4]
|
|
8001f4c: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001f4e: f023 0303 bic.w r3, r3, #3
|
|
8001f52: f043 0201 orr.w r2, r3, #1
|
|
8001f56: 687b ldr r3, [r7, #4]
|
|
8001f58: 65da str r2, [r3, #92] @ 0x5c
|
|
8001f5a: e007 b.n 8001f6c <HAL_ADC_Init+0x2e8>
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8001f5c: 687b ldr r3, [r7, #4]
|
|
8001f5e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001f60: f043 0210 orr.w r2, r3, #16
|
|
8001f64: 687b ldr r3, [r7, #4]
|
|
8001f66: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8001f68: 2301 movs r3, #1
|
|
8001f6a: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8001f6c: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
8001f6e: 4618 mov r0, r3
|
|
8001f70: 3724 adds r7, #36 @ 0x24
|
|
8001f72: 46bd mov sp, r7
|
|
8001f74: bd90 pop {r4, r7, pc}
|
|
8001f76: bf00 nop
|
|
8001f78: 2000001c .word 0x2000001c
|
|
8001f7c: 053e2d63 .word 0x053e2d63
|
|
8001f80: 50000100 .word 0x50000100
|
|
8001f84: 50000300 .word 0x50000300
|
|
8001f88: fff04007 .word 0xfff04007
|
|
|
|
08001f8c <HAL_ADC_Start>:
|
|
* if ADC is master, ADC is enabled and multimode conversion is started.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8001f8c: b580 push {r7, lr}
|
|
8001f8e: b086 sub sp, #24
|
|
8001f90: af00 add r7, sp, #0
|
|
8001f92: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
const ADC_TypeDef *tmpADC_Master;
|
|
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
8001f94: 4859 ldr r0, [pc, #356] @ (80020fc <HAL_ADC_Start+0x170>)
|
|
8001f96: f7ff fd5b bl 8001a50 <LL_ADC_GetMultimode>
|
|
8001f9a: 6138 str r0, [r7, #16]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Perform ADC enable and conversion start if no conversion is on going */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
8001f9c: 687b ldr r3, [r7, #4]
|
|
8001f9e: 681b ldr r3, [r3, #0]
|
|
8001fa0: 4618 mov r0, r3
|
|
8001fa2: f7ff fe35 bl 8001c10 <LL_ADC_REG_IsConversionOngoing>
|
|
8001fa6: 4603 mov r3, r0
|
|
8001fa8: 2b00 cmp r3, #0
|
|
8001faa: f040 809f bne.w 80020ec <HAL_ADC_Start+0x160>
|
|
{
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8001fae: 687b ldr r3, [r7, #4]
|
|
8001fb0: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
|
|
8001fb4: 2b01 cmp r3, #1
|
|
8001fb6: d101 bne.n 8001fbc <HAL_ADC_Start+0x30>
|
|
8001fb8: 2302 movs r3, #2
|
|
8001fba: e09a b.n 80020f2 <HAL_ADC_Start+0x166>
|
|
8001fbc: 687b ldr r3, [r7, #4]
|
|
8001fbe: 2201 movs r2, #1
|
|
8001fc0: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Enable the ADC peripheral */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
8001fc4: 6878 ldr r0, [r7, #4]
|
|
8001fc6: f000 fe63 bl 8002c90 <ADC_Enable>
|
|
8001fca: 4603 mov r3, r0
|
|
8001fcc: 75fb strb r3, [r7, #23]
|
|
|
|
/* Start conversion if ADC is effectively enabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
8001fce: 7dfb ldrb r3, [r7, #23]
|
|
8001fd0: 2b00 cmp r3, #0
|
|
8001fd2: f040 8086 bne.w 80020e2 <HAL_ADC_Start+0x156>
|
|
{
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to regular group conversion results */
|
|
/* - Set state bitfield related to regular operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8001fd6: 687b ldr r3, [r7, #4]
|
|
8001fd8: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8001fda: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
8001fde: f023 0301 bic.w r3, r3, #1
|
|
8001fe2: f443 7280 orr.w r2, r3, #256 @ 0x100
|
|
8001fe6: 687b ldr r3, [r7, #4]
|
|
8001fe8: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
|
|
- if ADC instance is master or if multimode feature is not available
|
|
- if multimode setting is disabled (ADC instance slave in independent mode) */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
8001fea: 687b ldr r3, [r7, #4]
|
|
8001fec: 681b ldr r3, [r3, #0]
|
|
8001fee: 4a44 ldr r2, [pc, #272] @ (8002100 <HAL_ADC_Start+0x174>)
|
|
8001ff0: 4293 cmp r3, r2
|
|
8001ff2: d002 beq.n 8001ffa <HAL_ADC_Start+0x6e>
|
|
8001ff4: 687b ldr r3, [r7, #4]
|
|
8001ff6: 681b ldr r3, [r3, #0]
|
|
8001ff8: e001 b.n 8001ffe <HAL_ADC_Start+0x72>
|
|
8001ffa: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
8001ffe: 687a ldr r2, [r7, #4]
|
|
8002000: 6812 ldr r2, [r2, #0]
|
|
8002002: 4293 cmp r3, r2
|
|
8002004: d002 beq.n 800200c <HAL_ADC_Start+0x80>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
8002006: 693b ldr r3, [r7, #16]
|
|
8002008: 2b00 cmp r3, #0
|
|
800200a: d105 bne.n 8002018 <HAL_ADC_Start+0x8c>
|
|
)
|
|
{
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
800200c: 687b ldr r3, [r7, #4]
|
|
800200e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002010: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
|
|
8002014: 687b ldr r3, [r7, #4]
|
|
8002016: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
|
|
|
/* Set ADC error code */
|
|
/* Check if a conversion is on going on ADC group injected */
|
|
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
8002018: 687b ldr r3, [r7, #4]
|
|
800201a: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800201c: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8002020: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8002024: d106 bne.n 8002034 <HAL_ADC_Start+0xa8>
|
|
{
|
|
/* Reset ADC error code fields related to regular conversions only */
|
|
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
|
|
8002026: 687b ldr r3, [r7, #4]
|
|
8002028: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800202a: f023 0206 bic.w r2, r3, #6
|
|
800202e: 687b ldr r3, [r7, #4]
|
|
8002030: 661a str r2, [r3, #96] @ 0x60
|
|
8002032: e002 b.n 800203a <HAL_ADC_Start+0xae>
|
|
}
|
|
else
|
|
{
|
|
/* Reset all ADC error code fields */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8002034: 687b ldr r3, [r7, #4]
|
|
8002036: 2200 movs r2, #0
|
|
8002038: 661a str r2, [r3, #96] @ 0x60
|
|
}
|
|
|
|
/* Clear ADC group regular conversion flag and overrun flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
|
|
800203a: 687b ldr r3, [r7, #4]
|
|
800203c: 681b ldr r3, [r3, #0]
|
|
800203e: 221c movs r2, #28
|
|
8002040: 601a str r2, [r3, #0]
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
8002042: 687b ldr r3, [r7, #4]
|
|
8002044: 2200 movs r2, #0
|
|
8002046: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
/* Case of multimode enabled (when multimode feature is available): */
|
|
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
|
|
/* enabled only (conversion is not started), */
|
|
/* - if ADC is master, ADC is enabled and conversion is started. */
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
800204a: 687b ldr r3, [r7, #4]
|
|
800204c: 681b ldr r3, [r3, #0]
|
|
800204e: 4a2c ldr r2, [pc, #176] @ (8002100 <HAL_ADC_Start+0x174>)
|
|
8002050: 4293 cmp r3, r2
|
|
8002052: d002 beq.n 800205a <HAL_ADC_Start+0xce>
|
|
8002054: 687b ldr r3, [r7, #4]
|
|
8002056: 681b ldr r3, [r3, #0]
|
|
8002058: e001 b.n 800205e <HAL_ADC_Start+0xd2>
|
|
800205a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
800205e: 687a ldr r2, [r7, #4]
|
|
8002060: 6812 ldr r2, [r2, #0]
|
|
8002062: 4293 cmp r3, r2
|
|
8002064: d008 beq.n 8002078 <HAL_ADC_Start+0xec>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
8002066: 693b ldr r3, [r7, #16]
|
|
8002068: 2b00 cmp r3, #0
|
|
800206a: d005 beq.n 8002078 <HAL_ADC_Start+0xec>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|
|
800206c: 693b ldr r3, [r7, #16]
|
|
800206e: 2b05 cmp r3, #5
|
|
8002070: d002 beq.n 8002078 <HAL_ADC_Start+0xec>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
|
|
8002072: 693b ldr r3, [r7, #16]
|
|
8002074: 2b09 cmp r3, #9
|
|
8002076: d114 bne.n 80020a2 <HAL_ADC_Start+0x116>
|
|
)
|
|
{
|
|
/* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
|
|
8002078: 687b ldr r3, [r7, #4]
|
|
800207a: 681b ldr r3, [r3, #0]
|
|
800207c: 68db ldr r3, [r3, #12]
|
|
800207e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002082: 2b00 cmp r3, #0
|
|
8002084: d007 beq.n 8002096 <HAL_ADC_Start+0x10a>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
8002086: 687b ldr r3, [r7, #4]
|
|
8002088: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800208a: f423 5340 bic.w r3, r3, #12288 @ 0x3000
|
|
800208e: f443 5280 orr.w r2, r3, #4096 @ 0x1000
|
|
8002092: 687b ldr r3, [r7, #4]
|
|
8002094: 65da str r2, [r3, #92] @ 0x5c
|
|
}
|
|
|
|
/* Start ADC group regular conversion */
|
|
LL_ADC_REG_StartConversion(hadc->Instance);
|
|
8002096: 687b ldr r3, [r7, #4]
|
|
8002098: 681b ldr r3, [r3, #0]
|
|
800209a: 4618 mov r0, r3
|
|
800209c: f7ff fd90 bl 8001bc0 <LL_ADC_REG_StartConversion>
|
|
80020a0: e026 b.n 80020f0 <HAL_ADC_Start+0x164>
|
|
}
|
|
else
|
|
{
|
|
/* ADC instance is a multimode slave instance with multimode regular conversions enabled */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
80020a2: 687b ldr r3, [r7, #4]
|
|
80020a4: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80020a6: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
80020aa: 687b ldr r3, [r7, #4]
|
|
80020ac: 65da str r2, [r3, #92] @ 0x5c
|
|
/* if Master ADC JAUTO bit is set, update Slave State in setting
|
|
HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
|
|
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
|
|
80020ae: 687b ldr r3, [r7, #4]
|
|
80020b0: 681b ldr r3, [r3, #0]
|
|
80020b2: 4a13 ldr r2, [pc, #76] @ (8002100 <HAL_ADC_Start+0x174>)
|
|
80020b4: 4293 cmp r3, r2
|
|
80020b6: d002 beq.n 80020be <HAL_ADC_Start+0x132>
|
|
80020b8: 687b ldr r3, [r7, #4]
|
|
80020ba: 681b ldr r3, [r3, #0]
|
|
80020bc: e001 b.n 80020c2 <HAL_ADC_Start+0x136>
|
|
80020be: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
80020c2: 60fb str r3, [r7, #12]
|
|
if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
|
|
80020c4: 68fb ldr r3, [r7, #12]
|
|
80020c6: 68db ldr r3, [r3, #12]
|
|
80020c8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80020cc: 2b00 cmp r3, #0
|
|
80020ce: d00f beq.n 80020f0 <HAL_ADC_Start+0x164>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
80020d0: 687b ldr r3, [r7, #4]
|
|
80020d2: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80020d4: f423 5340 bic.w r3, r3, #12288 @ 0x3000
|
|
80020d8: f443 5280 orr.w r2, r3, #4096 @ 0x1000
|
|
80020dc: 687b ldr r3, [r7, #4]
|
|
80020de: 65da str r2, [r3, #92] @ 0x5c
|
|
80020e0: e006 b.n 80020f0 <HAL_ADC_Start+0x164>
|
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80020e2: 687b ldr r3, [r7, #4]
|
|
80020e4: 2200 movs r2, #0
|
|
80020e6: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
80020ea: e001 b.n 80020f0 <HAL_ADC_Start+0x164>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_BUSY;
|
|
80020ec: 2302 movs r3, #2
|
|
80020ee: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
80020f0: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80020f2: 4618 mov r0, r3
|
|
80020f4: 3718 adds r7, #24
|
|
80020f6: 46bd mov sp, r7
|
|
80020f8: bd80 pop {r7, pc}
|
|
80020fa: bf00 nop
|
|
80020fc: 50000300 .word 0x50000300
|
|
8002100: 50000100 .word 0x50000100
|
|
|
|
08002104 <HAL_ADC_Stop>:
|
|
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8002104: b580 push {r7, lr}
|
|
8002106: b084 sub sp, #16
|
|
8002108: af00 add r7, sp, #0
|
|
800210a: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
800210c: 687b ldr r3, [r7, #4]
|
|
800210e: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
|
|
8002112: 2b01 cmp r3, #1
|
|
8002114: d101 bne.n 800211a <HAL_ADC_Stop+0x16>
|
|
8002116: 2302 movs r3, #2
|
|
8002118: e023 b.n 8002162 <HAL_ADC_Stop+0x5e>
|
|
800211a: 687b ldr r3, [r7, #4]
|
|
800211c: 2201 movs r2, #1
|
|
800211e: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
|
|
8002122: 2103 movs r1, #3
|
|
8002124: 6878 ldr r0, [r7, #4]
|
|
8002126: f000 fcf7 bl 8002b18 <ADC_ConversionStop>
|
|
800212a: 4603 mov r3, r0
|
|
800212c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Disable ADC peripheral if conversions are effectively stopped */
|
|
if (tmp_hal_status == HAL_OK)
|
|
800212e: 7bfb ldrb r3, [r7, #15]
|
|
8002130: 2b00 cmp r3, #0
|
|
8002132: d111 bne.n 8002158 <HAL_ADC_Stop+0x54>
|
|
{
|
|
/* 2. Disable the ADC peripheral */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
8002134: 6878 ldr r0, [r7, #4]
|
|
8002136: f000 fe31 bl 8002d9c <ADC_Disable>
|
|
800213a: 4603 mov r3, r0
|
|
800213c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
800213e: 7bfb ldrb r3, [r7, #15]
|
|
8002140: 2b00 cmp r3, #0
|
|
8002142: d109 bne.n 8002158 <HAL_ADC_Stop+0x54>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002144: 687b ldr r3, [r7, #4]
|
|
8002146: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002148: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
800214c: f023 0301 bic.w r3, r3, #1
|
|
8002150: f043 0201 orr.w r2, r3, #1
|
|
8002154: 687b ldr r3, [r7, #4]
|
|
8002156: 65da str r2, [r3, #92] @ 0x5c
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8002158: 687b ldr r3, [r7, #4]
|
|
800215a: 2200 movs r2, #0
|
|
800215c: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8002160: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002162: 4618 mov r0, r3
|
|
8002164: 3710 adds r7, #16
|
|
8002166: 46bd mov sp, r7
|
|
8002168: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800216c <HAL_ADC_PollForConversion>:
|
|
* @param hadc ADC handle
|
|
* @param Timeout Timeout value in millisecond.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
|
|
{
|
|
800216c: b580 push {r7, lr}
|
|
800216e: b088 sub sp, #32
|
|
8002170: af00 add r7, sp, #0
|
|
8002172: 6078 str r0, [r7, #4]
|
|
8002174: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t tmp_Flag_End;
|
|
uint32_t tmp_cfgr;
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
const ADC_TypeDef *tmpADC_Master;
|
|
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
8002176: 4867 ldr r0, [pc, #412] @ (8002314 <HAL_ADC_PollForConversion+0x1a8>)
|
|
8002178: f7ff fc6a bl 8001a50 <LL_ADC_GetMultimode>
|
|
800217c: 6178 str r0, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* If end of conversion selected to end of sequence conversions */
|
|
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
|
|
800217e: 687b ldr r3, [r7, #4]
|
|
8002180: 699b ldr r3, [r3, #24]
|
|
8002182: 2b08 cmp r3, #8
|
|
8002184: d102 bne.n 800218c <HAL_ADC_PollForConversion+0x20>
|
|
{
|
|
tmp_Flag_End = ADC_FLAG_EOS;
|
|
8002186: 2308 movs r3, #8
|
|
8002188: 61fb str r3, [r7, #28]
|
|
800218a: e02a b.n 80021e2 <HAL_ADC_PollForConversion+0x76>
|
|
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
|
|
/* several ranks and polling for end of each conversion. */
|
|
/* For code simplicity sake, this particular case is generalized to */
|
|
/* ADC configured in DMA mode and and polling for end of each conversion. */
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
800218c: 697b ldr r3, [r7, #20]
|
|
800218e: 2b00 cmp r3, #0
|
|
8002190: d005 beq.n 800219e <HAL_ADC_PollForConversion+0x32>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|
|
8002192: 697b ldr r3, [r7, #20]
|
|
8002194: 2b05 cmp r3, #5
|
|
8002196: d002 beq.n 800219e <HAL_ADC_PollForConversion+0x32>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
|
|
8002198: 697b ldr r3, [r7, #20]
|
|
800219a: 2b09 cmp r3, #9
|
|
800219c: d111 bne.n 80021c2 <HAL_ADC_PollForConversion+0x56>
|
|
)
|
|
{
|
|
/* Check ADC DMA mode in independent mode on ADC group regular */
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
|
|
800219e: 687b ldr r3, [r7, #4]
|
|
80021a0: 681b ldr r3, [r3, #0]
|
|
80021a2: 68db ldr r3, [r3, #12]
|
|
80021a4: f003 0301 and.w r3, r3, #1
|
|
80021a8: 2b00 cmp r3, #0
|
|
80021aa: d007 beq.n 80021bc <HAL_ADC_PollForConversion+0x50>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
80021ac: 687b ldr r3, [r7, #4]
|
|
80021ae: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80021b0: f043 0220 orr.w r2, r3, #32
|
|
80021b4: 687b ldr r3, [r7, #4]
|
|
80021b6: 65da str r2, [r3, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
80021b8: 2301 movs r3, #1
|
|
80021ba: e0a6 b.n 800230a <HAL_ADC_PollForConversion+0x19e>
|
|
}
|
|
else
|
|
{
|
|
tmp_Flag_End = (ADC_FLAG_EOC);
|
|
80021bc: 2304 movs r3, #4
|
|
80021be: 61fb str r3, [r7, #28]
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
|
|
80021c0: e00f b.n 80021e2 <HAL_ADC_PollForConversion+0x76>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check ADC DMA mode in multimode on ADC group regular */
|
|
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
|
|
80021c2: 4854 ldr r0, [pc, #336] @ (8002314 <HAL_ADC_PollForConversion+0x1a8>)
|
|
80021c4: f7ff fc52 bl 8001a6c <LL_ADC_GetMultiDMATransfer>
|
|
80021c8: 4603 mov r3, r0
|
|
80021ca: 2b00 cmp r3, #0
|
|
80021cc: d007 beq.n 80021de <HAL_ADC_PollForConversion+0x72>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
80021ce: 687b ldr r3, [r7, #4]
|
|
80021d0: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80021d2: f043 0220 orr.w r2, r3, #32
|
|
80021d6: 687b ldr r3, [r7, #4]
|
|
80021d8: 65da str r2, [r3, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
80021da: 2301 movs r3, #1
|
|
80021dc: e095 b.n 800230a <HAL_ADC_PollForConversion+0x19e>
|
|
}
|
|
else
|
|
{
|
|
tmp_Flag_End = (ADC_FLAG_EOC);
|
|
80021de: 2304 movs r3, #4
|
|
80021e0: 61fb str r3, [r7, #28]
|
|
}
|
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
|
}
|
|
|
|
/* Get tick count */
|
|
tickstart = HAL_GetTick();
|
|
80021e2: f7ff fac9 bl 8001778 <HAL_GetTick>
|
|
80021e6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait until End of unitary conversion or sequence conversions flag is raised */
|
|
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
80021e8: e021 b.n 800222e <HAL_ADC_PollForConversion+0xc2>
|
|
{
|
|
/* Check if timeout is disabled (set to infinite wait) */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80021ea: 683b ldr r3, [r7, #0]
|
|
80021ec: f1b3 3fff cmp.w r3, #4294967295
|
|
80021f0: d01d beq.n 800222e <HAL_ADC_PollForConversion+0xc2>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
|
|
80021f2: f7ff fac1 bl 8001778 <HAL_GetTick>
|
|
80021f6: 4602 mov r2, r0
|
|
80021f8: 693b ldr r3, [r7, #16]
|
|
80021fa: 1ad3 subs r3, r2, r3
|
|
80021fc: 683a ldr r2, [r7, #0]
|
|
80021fe: 429a cmp r2, r3
|
|
8002200: d302 bcc.n 8002208 <HAL_ADC_PollForConversion+0x9c>
|
|
8002202: 683b ldr r3, [r7, #0]
|
|
8002204: 2b00 cmp r3, #0
|
|
8002206: d112 bne.n 800222e <HAL_ADC_PollForConversion+0xc2>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
8002208: 687b ldr r3, [r7, #4]
|
|
800220a: 681b ldr r3, [r3, #0]
|
|
800220c: 681a ldr r2, [r3, #0]
|
|
800220e: 69fb ldr r3, [r7, #28]
|
|
8002210: 4013 ands r3, r2
|
|
8002212: 2b00 cmp r3, #0
|
|
8002214: d10b bne.n 800222e <HAL_ADC_PollForConversion+0xc2>
|
|
{
|
|
/* Update ADC state machine to timeout */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
|
8002216: 687b ldr r3, [r7, #4]
|
|
8002218: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800221a: f043 0204 orr.w r2, r3, #4
|
|
800221e: 687b ldr r3, [r7, #4]
|
|
8002220: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8002222: 687b ldr r3, [r7, #4]
|
|
8002224: 2200 movs r2, #0
|
|
8002226: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
return HAL_TIMEOUT;
|
|
800222a: 2303 movs r3, #3
|
|
800222c: e06d b.n 800230a <HAL_ADC_PollForConversion+0x19e>
|
|
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
800222e: 687b ldr r3, [r7, #4]
|
|
8002230: 681b ldr r3, [r3, #0]
|
|
8002232: 681a ldr r2, [r3, #0]
|
|
8002234: 69fb ldr r3, [r7, #28]
|
|
8002236: 4013 ands r3, r2
|
|
8002238: 2b00 cmp r3, #0
|
|
800223a: d0d6 beq.n 80021ea <HAL_ADC_PollForConversion+0x7e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update ADC state machine */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
|
|
800223c: 687b ldr r3, [r7, #4]
|
|
800223e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002240: f443 7200 orr.w r2, r3, #512 @ 0x200
|
|
8002244: 687b ldr r3, [r7, #4]
|
|
8002246: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Determine whether any further conversion upcoming on group regular */
|
|
/* by external trigger, continuous mode or scan sequence on going. */
|
|
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
|
|
8002248: 687b ldr r3, [r7, #4]
|
|
800224a: 681b ldr r3, [r3, #0]
|
|
800224c: 4618 mov r0, r3
|
|
800224e: f7ff fb71 bl 8001934 <LL_ADC_REG_IsTriggerSourceSWStart>
|
|
8002252: 4603 mov r3, r0
|
|
8002254: 2b00 cmp r3, #0
|
|
8002256: d01c beq.n 8002292 <HAL_ADC_PollForConversion+0x126>
|
|
&& (hadc->Init.ContinuousConvMode == DISABLE)
|
|
8002258: 687b ldr r3, [r7, #4]
|
|
800225a: 7f5b ldrb r3, [r3, #29]
|
|
800225c: 2b00 cmp r3, #0
|
|
800225e: d118 bne.n 8002292 <HAL_ADC_PollForConversion+0x126>
|
|
)
|
|
{
|
|
/* Check whether end of sequence is reached */
|
|
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
|
|
8002260: 687b ldr r3, [r7, #4]
|
|
8002262: 681b ldr r3, [r3, #0]
|
|
8002264: 681b ldr r3, [r3, #0]
|
|
8002266: f003 0308 and.w r3, r3, #8
|
|
800226a: 2b08 cmp r3, #8
|
|
800226c: d111 bne.n 8002292 <HAL_ADC_PollForConversion+0x126>
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
800226e: 687b ldr r3, [r7, #4]
|
|
8002270: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002272: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8002276: 687b ldr r3, [r7, #4]
|
|
8002278: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
|
|
800227a: 687b ldr r3, [r7, #4]
|
|
800227c: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800227e: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8002282: 2b00 cmp r3, #0
|
|
8002284: d105 bne.n 8002292 <HAL_ADC_PollForConversion+0x126>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
8002286: 687b ldr r3, [r7, #4]
|
|
8002288: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
800228a: f043 0201 orr.w r2, r3, #1
|
|
800228e: 687b ldr r3, [r7, #4]
|
|
8002290: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Get relevant register CFGR in ADC instance of ADC master or slave */
|
|
/* in function of multimode state (for devices with multimode */
|
|
/* available). */
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
8002292: 687b ldr r3, [r7, #4]
|
|
8002294: 681b ldr r3, [r3, #0]
|
|
8002296: 4a20 ldr r2, [pc, #128] @ (8002318 <HAL_ADC_PollForConversion+0x1ac>)
|
|
8002298: 4293 cmp r3, r2
|
|
800229a: d002 beq.n 80022a2 <HAL_ADC_PollForConversion+0x136>
|
|
800229c: 687b ldr r3, [r7, #4]
|
|
800229e: 681b ldr r3, [r3, #0]
|
|
80022a0: e001 b.n 80022a6 <HAL_ADC_PollForConversion+0x13a>
|
|
80022a2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
80022a6: 687a ldr r2, [r7, #4]
|
|
80022a8: 6812 ldr r2, [r2, #0]
|
|
80022aa: 4293 cmp r3, r2
|
|
80022ac: d008 beq.n 80022c0 <HAL_ADC_PollForConversion+0x154>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
80022ae: 697b ldr r3, [r7, #20]
|
|
80022b0: 2b00 cmp r3, #0
|
|
80022b2: d005 beq.n 80022c0 <HAL_ADC_PollForConversion+0x154>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|
|
80022b4: 697b ldr r3, [r7, #20]
|
|
80022b6: 2b05 cmp r3, #5
|
|
80022b8: d002 beq.n 80022c0 <HAL_ADC_PollForConversion+0x154>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
|
|
80022ba: 697b ldr r3, [r7, #20]
|
|
80022bc: 2b09 cmp r3, #9
|
|
80022be: d104 bne.n 80022ca <HAL_ADC_PollForConversion+0x15e>
|
|
)
|
|
{
|
|
/* Retrieve handle ADC CFGR register */
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
80022c0: 687b ldr r3, [r7, #4]
|
|
80022c2: 681b ldr r3, [r3, #0]
|
|
80022c4: 68db ldr r3, [r3, #12]
|
|
80022c6: 61bb str r3, [r7, #24]
|
|
80022c8: e00d b.n 80022e6 <HAL_ADC_PollForConversion+0x17a>
|
|
}
|
|
else
|
|
{
|
|
/* Retrieve Master ADC CFGR register */
|
|
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
|
|
80022ca: 687b ldr r3, [r7, #4]
|
|
80022cc: 681b ldr r3, [r3, #0]
|
|
80022ce: 4a12 ldr r2, [pc, #72] @ (8002318 <HAL_ADC_PollForConversion+0x1ac>)
|
|
80022d0: 4293 cmp r3, r2
|
|
80022d2: d002 beq.n 80022da <HAL_ADC_PollForConversion+0x16e>
|
|
80022d4: 687b ldr r3, [r7, #4]
|
|
80022d6: 681b ldr r3, [r3, #0]
|
|
80022d8: e001 b.n 80022de <HAL_ADC_PollForConversion+0x172>
|
|
80022da: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
|
|
80022de: 60fb str r3, [r7, #12]
|
|
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
|
|
80022e0: 68fb ldr r3, [r7, #12]
|
|
80022e2: 68db ldr r3, [r3, #12]
|
|
80022e4: 61bb str r3, [r7, #24]
|
|
/* Retrieve handle ADC CFGR register */
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
#endif /* ADC_MULTIMODE_SUPPORT */
|
|
|
|
/* Clear polled flag */
|
|
if (tmp_Flag_End == ADC_FLAG_EOS)
|
|
80022e6: 69fb ldr r3, [r7, #28]
|
|
80022e8: 2b08 cmp r3, #8
|
|
80022ea: d104 bne.n 80022f6 <HAL_ADC_PollForConversion+0x18a>
|
|
{
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
|
|
80022ec: 687b ldr r3, [r7, #4]
|
|
80022ee: 681b ldr r3, [r3, #0]
|
|
80022f0: 2208 movs r2, #8
|
|
80022f2: 601a str r2, [r3, #0]
|
|
80022f4: e008 b.n 8002308 <HAL_ADC_PollForConversion+0x19c>
|
|
else
|
|
{
|
|
/* Clear end of conversion EOC flag of regular group if low power feature */
|
|
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
|
|
/* until data register is read using function HAL_ADC_GetValue(). */
|
|
if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
|
|
80022f6: 69bb ldr r3, [r7, #24]
|
|
80022f8: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80022fc: 2b00 cmp r3, #0
|
|
80022fe: d103 bne.n 8002308 <HAL_ADC_PollForConversion+0x19c>
|
|
{
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
|
|
8002300: 687b ldr r3, [r7, #4]
|
|
8002302: 681b ldr r3, [r3, #0]
|
|
8002304: 220c movs r2, #12
|
|
8002306: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8002308: 2300 movs r3, #0
|
|
}
|
|
800230a: 4618 mov r0, r3
|
|
800230c: 3720 adds r7, #32
|
|
800230e: 46bd mov sp, r7
|
|
8002310: bd80 pop {r7, pc}
|
|
8002312: bf00 nop
|
|
8002314: 50000300 .word 0x50000300
|
|
8002318: 50000100 .word 0x50000100
|
|
|
|
0800231c <HAL_ADC_GetValue>:
|
|
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
|
|
* @param hadc ADC handle
|
|
* @retval ADC group regular conversion data
|
|
*/
|
|
uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
|
|
{
|
|
800231c: b480 push {r7}
|
|
800231e: b083 sub sp, #12
|
|
8002320: af00 add r7, sp, #0
|
|
8002322: 6078 str r0, [r7, #4]
|
|
|
|
/* Note: EOC flag is not cleared here by software because automatically */
|
|
/* cleared by hardware when reading register DR. */
|
|
|
|
/* Return ADC converted value */
|
|
return hadc->Instance->DR;
|
|
8002324: 687b ldr r3, [r7, #4]
|
|
8002326: 681b ldr r3, [r3, #0]
|
|
8002328: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
}
|
|
800232a: 4618 mov r0, r3
|
|
800232c: 370c adds r7, #12
|
|
800232e: 46bd mov sp, r7
|
|
8002330: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002334: 4770 bx lr
|
|
...
|
|
|
|
08002338 <HAL_ADC_ConfigChannel>:
|
|
* @param hadc ADC handle
|
|
* @param pConfig Structure of ADC channel assigned to ADC group regular.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
|
|
{
|
|
8002338: b580 push {r7, lr}
|
|
800233a: b0b6 sub sp, #216 @ 0xd8
|
|
800233c: af00 add r7, sp, #0
|
|
800233e: 6078 str r0, [r7, #4]
|
|
8002340: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8002342: 2300 movs r3, #0
|
|
8002344: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
|
|
uint32_t tmpOffsetShifted;
|
|
uint32_t tmp_config_internal_channel;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8002348: 2300 movs r3, #0
|
|
800234a: 60fb str r3, [r7, #12]
|
|
{
|
|
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
800234c: 687b ldr r3, [r7, #4]
|
|
800234e: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
|
|
8002352: 2b01 cmp r3, #1
|
|
8002354: d101 bne.n 800235a <HAL_ADC_ConfigChannel+0x22>
|
|
8002356: 2302 movs r3, #2
|
|
8002358: e3c8 b.n 8002aec <HAL_ADC_ConfigChannel+0x7b4>
|
|
800235a: 687b ldr r3, [r7, #4]
|
|
800235c: 2201 movs r2, #1
|
|
800235e: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel number */
|
|
/* - Channel rank */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
8002362: 687b ldr r3, [r7, #4]
|
|
8002364: 681b ldr r3, [r3, #0]
|
|
8002366: 4618 mov r0, r3
|
|
8002368: f7ff fc52 bl 8001c10 <LL_ADC_REG_IsConversionOngoing>
|
|
800236c: 4603 mov r3, r0
|
|
800236e: 2b00 cmp r3, #0
|
|
8002370: f040 83ad bne.w 8002ace <HAL_ADC_ConfigChannel+0x796>
|
|
{
|
|
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
|
|
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
|
|
8002374: 687b ldr r3, [r7, #4]
|
|
8002376: 6818 ldr r0, [r3, #0]
|
|
8002378: 683b ldr r3, [r7, #0]
|
|
800237a: 6859 ldr r1, [r3, #4]
|
|
800237c: 683b ldr r3, [r7, #0]
|
|
800237e: 681b ldr r3, [r3, #0]
|
|
8002380: 461a mov r2, r3
|
|
8002382: f7ff faea bl 800195a <LL_ADC_REG_SetSequencerRanks>
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel sampling time */
|
|
/* - Channel offset */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
8002386: 687b ldr r3, [r7, #4]
|
|
8002388: 681b ldr r3, [r3, #0]
|
|
800238a: 4618 mov r0, r3
|
|
800238c: f7ff fc40 bl 8001c10 <LL_ADC_REG_IsConversionOngoing>
|
|
8002390: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
8002394: 687b ldr r3, [r7, #4]
|
|
8002396: 681b ldr r3, [r3, #0]
|
|
8002398: 4618 mov r0, r3
|
|
800239a: f7ff fc60 bl 8001c5e <LL_ADC_INJ_IsConversionOngoing>
|
|
800239e: f8c7 00cc str.w r0, [r7, #204] @ 0xcc
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
80023a2: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
|
|
80023a6: 2b00 cmp r3, #0
|
|
80023a8: f040 81d9 bne.w 800275e <HAL_ADC_ConfigChannel+0x426>
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
80023ac: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
|
|
80023b0: 2b00 cmp r3, #0
|
|
80023b2: f040 81d4 bne.w 800275e <HAL_ADC_ConfigChannel+0x426>
|
|
)
|
|
{
|
|
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
|
|
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
|
|
80023b6: 683b ldr r3, [r7, #0]
|
|
80023b8: 689b ldr r3, [r3, #8]
|
|
80023ba: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
80023be: d10f bne.n 80023e0 <HAL_ADC_ConfigChannel+0xa8>
|
|
{
|
|
/* Set sampling time of the selected ADC channel */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
|
|
80023c0: 687b ldr r3, [r7, #4]
|
|
80023c2: 6818 ldr r0, [r3, #0]
|
|
80023c4: 683b ldr r3, [r7, #0]
|
|
80023c6: 681b ldr r3, [r3, #0]
|
|
80023c8: 2200 movs r2, #0
|
|
80023ca: 4619 mov r1, r3
|
|
80023cc: f7ff faf1 bl 80019b2 <LL_ADC_SetChannelSamplingTime>
|
|
|
|
/* Set ADC sampling time common configuration */
|
|
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
|
|
80023d0: 687b ldr r3, [r7, #4]
|
|
80023d2: 681b ldr r3, [r3, #0]
|
|
80023d4: f04f 4100 mov.w r1, #2147483648 @ 0x80000000
|
|
80023d8: 4618 mov r0, r3
|
|
80023da: f7ff fa98 bl 800190e <LL_ADC_SetSamplingTimeCommonConfig>
|
|
80023de: e00e b.n 80023fe <HAL_ADC_ConfigChannel+0xc6>
|
|
}
|
|
else
|
|
{
|
|
/* Set sampling time of the selected ADC channel */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
|
|
80023e0: 687b ldr r3, [r7, #4]
|
|
80023e2: 6818 ldr r0, [r3, #0]
|
|
80023e4: 683b ldr r3, [r7, #0]
|
|
80023e6: 6819 ldr r1, [r3, #0]
|
|
80023e8: 683b ldr r3, [r7, #0]
|
|
80023ea: 689b ldr r3, [r3, #8]
|
|
80023ec: 461a mov r2, r3
|
|
80023ee: f7ff fae0 bl 80019b2 <LL_ADC_SetChannelSamplingTime>
|
|
|
|
/* Set ADC sampling time common configuration */
|
|
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
|
|
80023f2: 687b ldr r3, [r7, #4]
|
|
80023f4: 681b ldr r3, [r3, #0]
|
|
80023f6: 2100 movs r1, #0
|
|
80023f8: 4618 mov r0, r3
|
|
80023fa: f7ff fa88 bl 800190e <LL_ADC_SetSamplingTimeCommonConfig>
|
|
|
|
/* Configure the offset: offset enable/disable, channel, offset value */
|
|
|
|
/* Shift the offset with respect to the selected ADC resolution. */
|
|
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
|
|
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
|
|
80023fe: 683b ldr r3, [r7, #0]
|
|
8002400: 695a ldr r2, [r3, #20]
|
|
8002402: 687b ldr r3, [r7, #4]
|
|
8002404: 681b ldr r3, [r3, #0]
|
|
8002406: 68db ldr r3, [r3, #12]
|
|
8002408: 08db lsrs r3, r3, #3
|
|
800240a: f003 0303 and.w r3, r3, #3
|
|
800240e: 005b lsls r3, r3, #1
|
|
8002410: fa02 f303 lsl.w r3, r2, r3
|
|
8002414: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
|
|
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
|
|
8002418: 683b ldr r3, [r7, #0]
|
|
800241a: 691b ldr r3, [r3, #16]
|
|
800241c: 2b04 cmp r3, #4
|
|
800241e: d022 beq.n 8002466 <HAL_ADC_ConfigChannel+0x12e>
|
|
{
|
|
/* Set ADC selected offset number */
|
|
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
|
|
8002420: 687b ldr r3, [r7, #4]
|
|
8002422: 6818 ldr r0, [r3, #0]
|
|
8002424: 683b ldr r3, [r7, #0]
|
|
8002426: 6919 ldr r1, [r3, #16]
|
|
8002428: 683b ldr r3, [r7, #0]
|
|
800242a: 681a ldr r2, [r3, #0]
|
|
800242c: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8002430: f7ff f9e2 bl 80017f8 <LL_ADC_SetOffset>
|
|
|
|
assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
|
|
assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
|
|
/* Set ADC selected offset sign & saturation */
|
|
LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
|
|
8002434: 687b ldr r3, [r7, #4]
|
|
8002436: 6818 ldr r0, [r3, #0]
|
|
8002438: 683b ldr r3, [r7, #0]
|
|
800243a: 6919 ldr r1, [r3, #16]
|
|
800243c: 683b ldr r3, [r7, #0]
|
|
800243e: 699b ldr r3, [r3, #24]
|
|
8002440: 461a mov r2, r3
|
|
8002442: f7ff fa2e bl 80018a2 <LL_ADC_SetOffsetSign>
|
|
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
|
|
8002446: 687b ldr r3, [r7, #4]
|
|
8002448: 6818 ldr r0, [r3, #0]
|
|
800244a: 683b ldr r3, [r7, #0]
|
|
800244c: 6919 ldr r1, [r3, #16]
|
|
(pConfig->OffsetSaturation == ENABLE) ?
|
|
800244e: 683b ldr r3, [r7, #0]
|
|
8002450: 7f1b ldrb r3, [r3, #28]
|
|
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
|
|
8002452: 2b01 cmp r3, #1
|
|
8002454: d102 bne.n 800245c <HAL_ADC_ConfigChannel+0x124>
|
|
8002456: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
800245a: e000 b.n 800245e <HAL_ADC_ConfigChannel+0x126>
|
|
800245c: 2300 movs r3, #0
|
|
800245e: 461a mov r2, r3
|
|
8002460: f7ff fa3a bl 80018d8 <LL_ADC_SetOffsetSaturation>
|
|
8002464: e17b b.n 800275e <HAL_ADC_ConfigChannel+0x426>
|
|
}
|
|
else
|
|
{
|
|
/* Scan each offset register to check if the selected channel is targeted. */
|
|
/* If this is the case, the corresponding offset number is disabled. */
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
|
|
8002466: 687b ldr r3, [r7, #4]
|
|
8002468: 681b ldr r3, [r3, #0]
|
|
800246a: 2100 movs r1, #0
|
|
800246c: 4618 mov r0, r3
|
|
800246e: f7ff f9e7 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
8002472: 4603 mov r3, r0
|
|
8002474: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002478: 2b00 cmp r3, #0
|
|
800247a: d10a bne.n 8002492 <HAL_ADC_ConfigChannel+0x15a>
|
|
800247c: 687b ldr r3, [r7, #4]
|
|
800247e: 681b ldr r3, [r3, #0]
|
|
8002480: 2100 movs r1, #0
|
|
8002482: 4618 mov r0, r3
|
|
8002484: f7ff f9dc bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
8002488: 4603 mov r3, r0
|
|
800248a: 0e9b lsrs r3, r3, #26
|
|
800248c: f003 021f and.w r2, r3, #31
|
|
8002490: e01e b.n 80024d0 <HAL_ADC_ConfigChannel+0x198>
|
|
8002492: 687b ldr r3, [r7, #4]
|
|
8002494: 681b ldr r3, [r3, #0]
|
|
8002496: 2100 movs r1, #0
|
|
8002498: 4618 mov r0, r3
|
|
800249a: f7ff f9d1 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
800249e: 4603 mov r3, r0
|
|
80024a0: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
|
|
uint32_t result;
|
|
|
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
|
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80024a4: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
|
|
80024a8: fa93 f3a3 rbit r3, r3
|
|
80024ac: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
result |= value & 1U;
|
|
s--;
|
|
}
|
|
result <<= s; /* shift when v's highest bits are zero */
|
|
#endif
|
|
return result;
|
|
80024b0: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
80024b4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
optimisations using the logic "value was passed to __builtin_clz, so it
|
|
is non-zero".
|
|
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
|
|
single CLZ instruction.
|
|
*/
|
|
if (value == 0U)
|
|
80024b8: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80024bc: 2b00 cmp r3, #0
|
|
80024be: d101 bne.n 80024c4 <HAL_ADC_ConfigChannel+0x18c>
|
|
{
|
|
return 32U;
|
|
80024c0: 2320 movs r3, #32
|
|
80024c2: e004 b.n 80024ce <HAL_ADC_ConfigChannel+0x196>
|
|
}
|
|
return __builtin_clz(value);
|
|
80024c4: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
80024c8: fab3 f383 clz r3, r3
|
|
80024cc: b2db uxtb r3, r3
|
|
80024ce: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
|
80024d0: 683b ldr r3, [r7, #0]
|
|
80024d2: 681b ldr r3, [r3, #0]
|
|
80024d4: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80024d8: 2b00 cmp r3, #0
|
|
80024da: d105 bne.n 80024e8 <HAL_ADC_ConfigChannel+0x1b0>
|
|
80024dc: 683b ldr r3, [r7, #0]
|
|
80024de: 681b ldr r3, [r3, #0]
|
|
80024e0: 0e9b lsrs r3, r3, #26
|
|
80024e2: f003 031f and.w r3, r3, #31
|
|
80024e6: e018 b.n 800251a <HAL_ADC_ConfigChannel+0x1e2>
|
|
80024e8: 683b ldr r3, [r7, #0]
|
|
80024ea: 681b ldr r3, [r3, #0]
|
|
80024ec: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80024f0: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
|
|
80024f4: fa93 f3a3 rbit r3, r3
|
|
80024f8: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
return result;
|
|
80024fc: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8002500: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
if (value == 0U)
|
|
8002504: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8002508: 2b00 cmp r3, #0
|
|
800250a: d101 bne.n 8002510 <HAL_ADC_ConfigChannel+0x1d8>
|
|
return 32U;
|
|
800250c: 2320 movs r3, #32
|
|
800250e: e004 b.n 800251a <HAL_ADC_ConfigChannel+0x1e2>
|
|
return __builtin_clz(value);
|
|
8002510: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8002514: fab3 f383 clz r3, r3
|
|
8002518: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
|
|
800251a: 429a cmp r2, r3
|
|
800251c: d106 bne.n 800252c <HAL_ADC_ConfigChannel+0x1f4>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
|
|
800251e: 687b ldr r3, [r7, #4]
|
|
8002520: 681b ldr r3, [r3, #0]
|
|
8002522: 2200 movs r2, #0
|
|
8002524: 2100 movs r1, #0
|
|
8002526: 4618 mov r0, r3
|
|
8002528: f7ff f9a0 bl 800186c <LL_ADC_SetOffsetState>
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
|
|
800252c: 687b ldr r3, [r7, #4]
|
|
800252e: 681b ldr r3, [r3, #0]
|
|
8002530: 2101 movs r1, #1
|
|
8002532: 4618 mov r0, r3
|
|
8002534: f7ff f984 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
8002538: 4603 mov r3, r0
|
|
800253a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800253e: 2b00 cmp r3, #0
|
|
8002540: d10a bne.n 8002558 <HAL_ADC_ConfigChannel+0x220>
|
|
8002542: 687b ldr r3, [r7, #4]
|
|
8002544: 681b ldr r3, [r3, #0]
|
|
8002546: 2101 movs r1, #1
|
|
8002548: 4618 mov r0, r3
|
|
800254a: f7ff f979 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
800254e: 4603 mov r3, r0
|
|
8002550: 0e9b lsrs r3, r3, #26
|
|
8002552: f003 021f and.w r2, r3, #31
|
|
8002556: e01e b.n 8002596 <HAL_ADC_ConfigChannel+0x25e>
|
|
8002558: 687b ldr r3, [r7, #4]
|
|
800255a: 681b ldr r3, [r3, #0]
|
|
800255c: 2101 movs r1, #1
|
|
800255e: 4618 mov r0, r3
|
|
8002560: f7ff f96e bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
8002564: 4603 mov r3, r0
|
|
8002566: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800256a: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
800256e: fa93 f3a3 rbit r3, r3
|
|
8002572: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return result;
|
|
8002576: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
800257a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
if (value == 0U)
|
|
800257e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8002582: 2b00 cmp r3, #0
|
|
8002584: d101 bne.n 800258a <HAL_ADC_ConfigChannel+0x252>
|
|
return 32U;
|
|
8002586: 2320 movs r3, #32
|
|
8002588: e004 b.n 8002594 <HAL_ADC_ConfigChannel+0x25c>
|
|
return __builtin_clz(value);
|
|
800258a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
800258e: fab3 f383 clz r3, r3
|
|
8002592: b2db uxtb r3, r3
|
|
8002594: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
|
8002596: 683b ldr r3, [r7, #0]
|
|
8002598: 681b ldr r3, [r3, #0]
|
|
800259a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800259e: 2b00 cmp r3, #0
|
|
80025a0: d105 bne.n 80025ae <HAL_ADC_ConfigChannel+0x276>
|
|
80025a2: 683b ldr r3, [r7, #0]
|
|
80025a4: 681b ldr r3, [r3, #0]
|
|
80025a6: 0e9b lsrs r3, r3, #26
|
|
80025a8: f003 031f and.w r3, r3, #31
|
|
80025ac: e018 b.n 80025e0 <HAL_ADC_ConfigChannel+0x2a8>
|
|
80025ae: 683b ldr r3, [r7, #0]
|
|
80025b0: 681b ldr r3, [r3, #0]
|
|
80025b2: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80025b6: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80025ba: fa93 f3a3 rbit r3, r3
|
|
80025be: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
return result;
|
|
80025c2: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
80025c6: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
if (value == 0U)
|
|
80025ca: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80025ce: 2b00 cmp r3, #0
|
|
80025d0: d101 bne.n 80025d6 <HAL_ADC_ConfigChannel+0x29e>
|
|
return 32U;
|
|
80025d2: 2320 movs r3, #32
|
|
80025d4: e004 b.n 80025e0 <HAL_ADC_ConfigChannel+0x2a8>
|
|
return __builtin_clz(value);
|
|
80025d6: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80025da: fab3 f383 clz r3, r3
|
|
80025de: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
|
|
80025e0: 429a cmp r2, r3
|
|
80025e2: d106 bne.n 80025f2 <HAL_ADC_ConfigChannel+0x2ba>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
|
|
80025e4: 687b ldr r3, [r7, #4]
|
|
80025e6: 681b ldr r3, [r3, #0]
|
|
80025e8: 2200 movs r2, #0
|
|
80025ea: 2101 movs r1, #1
|
|
80025ec: 4618 mov r0, r3
|
|
80025ee: f7ff f93d bl 800186c <LL_ADC_SetOffsetState>
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
|
|
80025f2: 687b ldr r3, [r7, #4]
|
|
80025f4: 681b ldr r3, [r3, #0]
|
|
80025f6: 2102 movs r1, #2
|
|
80025f8: 4618 mov r0, r3
|
|
80025fa: f7ff f921 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
80025fe: 4603 mov r3, r0
|
|
8002600: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002604: 2b00 cmp r3, #0
|
|
8002606: d10a bne.n 800261e <HAL_ADC_ConfigChannel+0x2e6>
|
|
8002608: 687b ldr r3, [r7, #4]
|
|
800260a: 681b ldr r3, [r3, #0]
|
|
800260c: 2102 movs r1, #2
|
|
800260e: 4618 mov r0, r3
|
|
8002610: f7ff f916 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
8002614: 4603 mov r3, r0
|
|
8002616: 0e9b lsrs r3, r3, #26
|
|
8002618: f003 021f and.w r2, r3, #31
|
|
800261c: e01e b.n 800265c <HAL_ADC_ConfigChannel+0x324>
|
|
800261e: 687b ldr r3, [r7, #4]
|
|
8002620: 681b ldr r3, [r3, #0]
|
|
8002622: 2102 movs r1, #2
|
|
8002624: 4618 mov r0, r3
|
|
8002626: f7ff f90b bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
800262a: 4603 mov r3, r0
|
|
800262c: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8002630: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8002634: fa93 f3a3 rbit r3, r3
|
|
8002638: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
return result;
|
|
800263c: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
8002640: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
if (value == 0U)
|
|
8002644: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8002648: 2b00 cmp r3, #0
|
|
800264a: d101 bne.n 8002650 <HAL_ADC_ConfigChannel+0x318>
|
|
return 32U;
|
|
800264c: 2320 movs r3, #32
|
|
800264e: e004 b.n 800265a <HAL_ADC_ConfigChannel+0x322>
|
|
return __builtin_clz(value);
|
|
8002650: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8002654: fab3 f383 clz r3, r3
|
|
8002658: b2db uxtb r3, r3
|
|
800265a: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
|
800265c: 683b ldr r3, [r7, #0]
|
|
800265e: 681b ldr r3, [r3, #0]
|
|
8002660: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002664: 2b00 cmp r3, #0
|
|
8002666: d105 bne.n 8002674 <HAL_ADC_ConfigChannel+0x33c>
|
|
8002668: 683b ldr r3, [r7, #0]
|
|
800266a: 681b ldr r3, [r3, #0]
|
|
800266c: 0e9b lsrs r3, r3, #26
|
|
800266e: f003 031f and.w r3, r3, #31
|
|
8002672: e016 b.n 80026a2 <HAL_ADC_ConfigChannel+0x36a>
|
|
8002674: 683b ldr r3, [r7, #0]
|
|
8002676: 681b ldr r3, [r3, #0]
|
|
8002678: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800267c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
8002680: fa93 f3a3 rbit r3, r3
|
|
8002684: 67fb str r3, [r7, #124] @ 0x7c
|
|
return result;
|
|
8002686: 6ffb ldr r3, [r7, #124] @ 0x7c
|
|
8002688: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
if (value == 0U)
|
|
800268c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8002690: 2b00 cmp r3, #0
|
|
8002692: d101 bne.n 8002698 <HAL_ADC_ConfigChannel+0x360>
|
|
return 32U;
|
|
8002694: 2320 movs r3, #32
|
|
8002696: e004 b.n 80026a2 <HAL_ADC_ConfigChannel+0x36a>
|
|
return __builtin_clz(value);
|
|
8002698: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
800269c: fab3 f383 clz r3, r3
|
|
80026a0: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
|
|
80026a2: 429a cmp r2, r3
|
|
80026a4: d106 bne.n 80026b4 <HAL_ADC_ConfigChannel+0x37c>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
|
|
80026a6: 687b ldr r3, [r7, #4]
|
|
80026a8: 681b ldr r3, [r3, #0]
|
|
80026aa: 2200 movs r2, #0
|
|
80026ac: 2102 movs r1, #2
|
|
80026ae: 4618 mov r0, r3
|
|
80026b0: f7ff f8dc bl 800186c <LL_ADC_SetOffsetState>
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
|
|
80026b4: 687b ldr r3, [r7, #4]
|
|
80026b6: 681b ldr r3, [r3, #0]
|
|
80026b8: 2103 movs r1, #3
|
|
80026ba: 4618 mov r0, r3
|
|
80026bc: f7ff f8c0 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
80026c0: 4603 mov r3, r0
|
|
80026c2: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80026c6: 2b00 cmp r3, #0
|
|
80026c8: d10a bne.n 80026e0 <HAL_ADC_ConfigChannel+0x3a8>
|
|
80026ca: 687b ldr r3, [r7, #4]
|
|
80026cc: 681b ldr r3, [r3, #0]
|
|
80026ce: 2103 movs r1, #3
|
|
80026d0: 4618 mov r0, r3
|
|
80026d2: f7ff f8b5 bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
80026d6: 4603 mov r3, r0
|
|
80026d8: 0e9b lsrs r3, r3, #26
|
|
80026da: f003 021f and.w r2, r3, #31
|
|
80026de: e017 b.n 8002710 <HAL_ADC_ConfigChannel+0x3d8>
|
|
80026e0: 687b ldr r3, [r7, #4]
|
|
80026e2: 681b ldr r3, [r3, #0]
|
|
80026e4: 2103 movs r1, #3
|
|
80026e6: 4618 mov r0, r3
|
|
80026e8: f7ff f8aa bl 8001840 <LL_ADC_GetOffsetChannel>
|
|
80026ec: 4603 mov r3, r0
|
|
80026ee: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80026f0: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80026f2: fa93 f3a3 rbit r3, r3
|
|
80026f6: 673b str r3, [r7, #112] @ 0x70
|
|
return result;
|
|
80026f8: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80026fa: 67bb str r3, [r7, #120] @ 0x78
|
|
if (value == 0U)
|
|
80026fc: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80026fe: 2b00 cmp r3, #0
|
|
8002700: d101 bne.n 8002706 <HAL_ADC_ConfigChannel+0x3ce>
|
|
return 32U;
|
|
8002702: 2320 movs r3, #32
|
|
8002704: e003 b.n 800270e <HAL_ADC_ConfigChannel+0x3d6>
|
|
return __builtin_clz(value);
|
|
8002706: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8002708: fab3 f383 clz r3, r3
|
|
800270c: b2db uxtb r3, r3
|
|
800270e: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
|
|
8002710: 683b ldr r3, [r7, #0]
|
|
8002712: 681b ldr r3, [r3, #0]
|
|
8002714: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002718: 2b00 cmp r3, #0
|
|
800271a: d105 bne.n 8002728 <HAL_ADC_ConfigChannel+0x3f0>
|
|
800271c: 683b ldr r3, [r7, #0]
|
|
800271e: 681b ldr r3, [r3, #0]
|
|
8002720: 0e9b lsrs r3, r3, #26
|
|
8002722: f003 031f and.w r3, r3, #31
|
|
8002726: e011 b.n 800274c <HAL_ADC_ConfigChannel+0x414>
|
|
8002728: 683b ldr r3, [r7, #0]
|
|
800272a: 681b ldr r3, [r3, #0]
|
|
800272c: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800272e: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8002730: fa93 f3a3 rbit r3, r3
|
|
8002734: 667b str r3, [r7, #100] @ 0x64
|
|
return result;
|
|
8002736: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8002738: 66fb str r3, [r7, #108] @ 0x6c
|
|
if (value == 0U)
|
|
800273a: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
800273c: 2b00 cmp r3, #0
|
|
800273e: d101 bne.n 8002744 <HAL_ADC_ConfigChannel+0x40c>
|
|
return 32U;
|
|
8002740: 2320 movs r3, #32
|
|
8002742: e003 b.n 800274c <HAL_ADC_ConfigChannel+0x414>
|
|
return __builtin_clz(value);
|
|
8002744: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
8002746: fab3 f383 clz r3, r3
|
|
800274a: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
|
|
800274c: 429a cmp r2, r3
|
|
800274e: d106 bne.n 800275e <HAL_ADC_ConfigChannel+0x426>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
|
|
8002750: 687b ldr r3, [r7, #4]
|
|
8002752: 681b ldr r3, [r3, #0]
|
|
8002754: 2200 movs r2, #0
|
|
8002756: 2103 movs r1, #3
|
|
8002758: 4618 mov r0, r3
|
|
800275a: f7ff f887 bl 800186c <LL_ADC_SetOffsetState>
|
|
}
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Single or differential mode */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
800275e: 687b ldr r3, [r7, #4]
|
|
8002760: 681b ldr r3, [r3, #0]
|
|
8002762: 4618 mov r0, r3
|
|
8002764: f7ff fa06 bl 8001b74 <LL_ADC_IsEnabled>
|
|
8002768: 4603 mov r3, r0
|
|
800276a: 2b00 cmp r3, #0
|
|
800276c: f040 8140 bne.w 80029f0 <HAL_ADC_ConfigChannel+0x6b8>
|
|
{
|
|
/* Set mode single-ended or differential input of the selected ADC channel */
|
|
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
|
|
8002770: 687b ldr r3, [r7, #4]
|
|
8002772: 6818 ldr r0, [r3, #0]
|
|
8002774: 683b ldr r3, [r7, #0]
|
|
8002776: 6819 ldr r1, [r3, #0]
|
|
8002778: 683b ldr r3, [r7, #0]
|
|
800277a: 68db ldr r3, [r3, #12]
|
|
800277c: 461a mov r2, r3
|
|
800277e: f7ff f943 bl 8001a08 <LL_ADC_SetChannelSingleDiff>
|
|
|
|
/* Configuration of differential mode */
|
|
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
|
|
8002782: 683b ldr r3, [r7, #0]
|
|
8002784: 68db ldr r3, [r3, #12]
|
|
8002786: 4a8f ldr r2, [pc, #572] @ (80029c4 <HAL_ADC_ConfigChannel+0x68c>)
|
|
8002788: 4293 cmp r3, r2
|
|
800278a: f040 8131 bne.w 80029f0 <HAL_ADC_ConfigChannel+0x6b8>
|
|
{
|
|
/* Set sampling time of the selected ADC channel */
|
|
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
800278e: 687b ldr r3, [r7, #4]
|
|
8002790: 6818 ldr r0, [r3, #0]
|
|
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
|
|
8002792: 683b ldr r3, [r7, #0]
|
|
8002794: 681b ldr r3, [r3, #0]
|
|
8002796: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800279a: 2b00 cmp r3, #0
|
|
800279c: d10b bne.n 80027b6 <HAL_ADC_ConfigChannel+0x47e>
|
|
800279e: 683b ldr r3, [r7, #0]
|
|
80027a0: 681b ldr r3, [r3, #0]
|
|
80027a2: 0e9b lsrs r3, r3, #26
|
|
80027a4: 3301 adds r3, #1
|
|
80027a6: f003 031f and.w r3, r3, #31
|
|
80027aa: 2b09 cmp r3, #9
|
|
80027ac: bf94 ite ls
|
|
80027ae: 2301 movls r3, #1
|
|
80027b0: 2300 movhi r3, #0
|
|
80027b2: b2db uxtb r3, r3
|
|
80027b4: e019 b.n 80027ea <HAL_ADC_ConfigChannel+0x4b2>
|
|
80027b6: 683b ldr r3, [r7, #0]
|
|
80027b8: 681b ldr r3, [r3, #0]
|
|
80027ba: 65fb str r3, [r7, #92] @ 0x5c
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80027bc: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80027be: fa93 f3a3 rbit r3, r3
|
|
80027c2: 65bb str r3, [r7, #88] @ 0x58
|
|
return result;
|
|
80027c4: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
80027c6: 663b str r3, [r7, #96] @ 0x60
|
|
if (value == 0U)
|
|
80027c8: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
80027ca: 2b00 cmp r3, #0
|
|
80027cc: d101 bne.n 80027d2 <HAL_ADC_ConfigChannel+0x49a>
|
|
return 32U;
|
|
80027ce: 2320 movs r3, #32
|
|
80027d0: e003 b.n 80027da <HAL_ADC_ConfigChannel+0x4a2>
|
|
return __builtin_clz(value);
|
|
80027d2: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
80027d4: fab3 f383 clz r3, r3
|
|
80027d8: b2db uxtb r3, r3
|
|
80027da: 3301 adds r3, #1
|
|
80027dc: f003 031f and.w r3, r3, #31
|
|
80027e0: 2b09 cmp r3, #9
|
|
80027e2: bf94 ite ls
|
|
80027e4: 2301 movls r3, #1
|
|
80027e6: 2300 movhi r3, #0
|
|
80027e8: b2db uxtb r3, r3
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
80027ea: 2b00 cmp r3, #0
|
|
80027ec: d079 beq.n 80028e2 <HAL_ADC_ConfigChannel+0x5aa>
|
|
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
|
|
80027ee: 683b ldr r3, [r7, #0]
|
|
80027f0: 681b ldr r3, [r3, #0]
|
|
80027f2: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80027f6: 2b00 cmp r3, #0
|
|
80027f8: d107 bne.n 800280a <HAL_ADC_ConfigChannel+0x4d2>
|
|
80027fa: 683b ldr r3, [r7, #0]
|
|
80027fc: 681b ldr r3, [r3, #0]
|
|
80027fe: 0e9b lsrs r3, r3, #26
|
|
8002800: 3301 adds r3, #1
|
|
8002802: 069b lsls r3, r3, #26
|
|
8002804: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
8002808: e015 b.n 8002836 <HAL_ADC_ConfigChannel+0x4fe>
|
|
800280a: 683b ldr r3, [r7, #0]
|
|
800280c: 681b ldr r3, [r3, #0]
|
|
800280e: 653b str r3, [r7, #80] @ 0x50
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8002810: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8002812: fa93 f3a3 rbit r3, r3
|
|
8002816: 64fb str r3, [r7, #76] @ 0x4c
|
|
return result;
|
|
8002818: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800281a: 657b str r3, [r7, #84] @ 0x54
|
|
if (value == 0U)
|
|
800281c: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
800281e: 2b00 cmp r3, #0
|
|
8002820: d101 bne.n 8002826 <HAL_ADC_ConfigChannel+0x4ee>
|
|
return 32U;
|
|
8002822: 2320 movs r3, #32
|
|
8002824: e003 b.n 800282e <HAL_ADC_ConfigChannel+0x4f6>
|
|
return __builtin_clz(value);
|
|
8002826: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8002828: fab3 f383 clz r3, r3
|
|
800282c: b2db uxtb r3, r3
|
|
800282e: 3301 adds r3, #1
|
|
8002830: 069b lsls r3, r3, #26
|
|
8002832: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
8002836: 683b ldr r3, [r7, #0]
|
|
8002838: 681b ldr r3, [r3, #0]
|
|
800283a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800283e: 2b00 cmp r3, #0
|
|
8002840: d109 bne.n 8002856 <HAL_ADC_ConfigChannel+0x51e>
|
|
8002842: 683b ldr r3, [r7, #0]
|
|
8002844: 681b ldr r3, [r3, #0]
|
|
8002846: 0e9b lsrs r3, r3, #26
|
|
8002848: 3301 adds r3, #1
|
|
800284a: f003 031f and.w r3, r3, #31
|
|
800284e: 2101 movs r1, #1
|
|
8002850: fa01 f303 lsl.w r3, r1, r3
|
|
8002854: e017 b.n 8002886 <HAL_ADC_ConfigChannel+0x54e>
|
|
8002856: 683b ldr r3, [r7, #0]
|
|
8002858: 681b ldr r3, [r3, #0]
|
|
800285a: 647b str r3, [r7, #68] @ 0x44
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800285c: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800285e: fa93 f3a3 rbit r3, r3
|
|
8002862: 643b str r3, [r7, #64] @ 0x40
|
|
return result;
|
|
8002864: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8002866: 64bb str r3, [r7, #72] @ 0x48
|
|
if (value == 0U)
|
|
8002868: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800286a: 2b00 cmp r3, #0
|
|
800286c: d101 bne.n 8002872 <HAL_ADC_ConfigChannel+0x53a>
|
|
return 32U;
|
|
800286e: 2320 movs r3, #32
|
|
8002870: e003 b.n 800287a <HAL_ADC_ConfigChannel+0x542>
|
|
return __builtin_clz(value);
|
|
8002872: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8002874: fab3 f383 clz r3, r3
|
|
8002878: b2db uxtb r3, r3
|
|
800287a: 3301 adds r3, #1
|
|
800287c: f003 031f and.w r3, r3, #31
|
|
8002880: 2101 movs r1, #1
|
|
8002882: fa01 f303 lsl.w r3, r1, r3
|
|
8002886: ea42 0103 orr.w r1, r2, r3
|
|
800288a: 683b ldr r3, [r7, #0]
|
|
800288c: 681b ldr r3, [r3, #0]
|
|
800288e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002892: 2b00 cmp r3, #0
|
|
8002894: d10a bne.n 80028ac <HAL_ADC_ConfigChannel+0x574>
|
|
8002896: 683b ldr r3, [r7, #0]
|
|
8002898: 681b ldr r3, [r3, #0]
|
|
800289a: 0e9b lsrs r3, r3, #26
|
|
800289c: 3301 adds r3, #1
|
|
800289e: f003 021f and.w r2, r3, #31
|
|
80028a2: 4613 mov r3, r2
|
|
80028a4: 005b lsls r3, r3, #1
|
|
80028a6: 4413 add r3, r2
|
|
80028a8: 051b lsls r3, r3, #20
|
|
80028aa: e018 b.n 80028de <HAL_ADC_ConfigChannel+0x5a6>
|
|
80028ac: 683b ldr r3, [r7, #0]
|
|
80028ae: 681b ldr r3, [r3, #0]
|
|
80028b0: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80028b2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80028b4: fa93 f3a3 rbit r3, r3
|
|
80028b8: 637b str r3, [r7, #52] @ 0x34
|
|
return result;
|
|
80028ba: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80028bc: 63fb str r3, [r7, #60] @ 0x3c
|
|
if (value == 0U)
|
|
80028be: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80028c0: 2b00 cmp r3, #0
|
|
80028c2: d101 bne.n 80028c8 <HAL_ADC_ConfigChannel+0x590>
|
|
return 32U;
|
|
80028c4: 2320 movs r3, #32
|
|
80028c6: e003 b.n 80028d0 <HAL_ADC_ConfigChannel+0x598>
|
|
return __builtin_clz(value);
|
|
80028c8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80028ca: fab3 f383 clz r3, r3
|
|
80028ce: b2db uxtb r3, r3
|
|
80028d0: 3301 adds r3, #1
|
|
80028d2: f003 021f and.w r2, r3, #31
|
|
80028d6: 4613 mov r3, r2
|
|
80028d8: 005b lsls r3, r3, #1
|
|
80028da: 4413 add r3, r2
|
|
80028dc: 051b lsls r3, r3, #20
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
80028de: 430b orrs r3, r1
|
|
80028e0: e081 b.n 80029e6 <HAL_ADC_ConfigChannel+0x6ae>
|
|
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
|
|
80028e2: 683b ldr r3, [r7, #0]
|
|
80028e4: 681b ldr r3, [r3, #0]
|
|
80028e6: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80028ea: 2b00 cmp r3, #0
|
|
80028ec: d107 bne.n 80028fe <HAL_ADC_ConfigChannel+0x5c6>
|
|
80028ee: 683b ldr r3, [r7, #0]
|
|
80028f0: 681b ldr r3, [r3, #0]
|
|
80028f2: 0e9b lsrs r3, r3, #26
|
|
80028f4: 3301 adds r3, #1
|
|
80028f6: 069b lsls r3, r3, #26
|
|
80028f8: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
80028fc: e015 b.n 800292a <HAL_ADC_ConfigChannel+0x5f2>
|
|
80028fe: 683b ldr r3, [r7, #0]
|
|
8002900: 681b ldr r3, [r3, #0]
|
|
8002902: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8002904: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8002906: fa93 f3a3 rbit r3, r3
|
|
800290a: 62bb str r3, [r7, #40] @ 0x28
|
|
return result;
|
|
800290c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800290e: 633b str r3, [r7, #48] @ 0x30
|
|
if (value == 0U)
|
|
8002910: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8002912: 2b00 cmp r3, #0
|
|
8002914: d101 bne.n 800291a <HAL_ADC_ConfigChannel+0x5e2>
|
|
return 32U;
|
|
8002916: 2320 movs r3, #32
|
|
8002918: e003 b.n 8002922 <HAL_ADC_ConfigChannel+0x5ea>
|
|
return __builtin_clz(value);
|
|
800291a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800291c: fab3 f383 clz r3, r3
|
|
8002920: b2db uxtb r3, r3
|
|
8002922: 3301 adds r3, #1
|
|
8002924: 069b lsls r3, r3, #26
|
|
8002926: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
|
|
800292a: 683b ldr r3, [r7, #0]
|
|
800292c: 681b ldr r3, [r3, #0]
|
|
800292e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002932: 2b00 cmp r3, #0
|
|
8002934: d109 bne.n 800294a <HAL_ADC_ConfigChannel+0x612>
|
|
8002936: 683b ldr r3, [r7, #0]
|
|
8002938: 681b ldr r3, [r3, #0]
|
|
800293a: 0e9b lsrs r3, r3, #26
|
|
800293c: 3301 adds r3, #1
|
|
800293e: f003 031f and.w r3, r3, #31
|
|
8002942: 2101 movs r1, #1
|
|
8002944: fa01 f303 lsl.w r3, r1, r3
|
|
8002948: e017 b.n 800297a <HAL_ADC_ConfigChannel+0x642>
|
|
800294a: 683b ldr r3, [r7, #0]
|
|
800294c: 681b ldr r3, [r3, #0]
|
|
800294e: 623b str r3, [r7, #32]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8002950: 6a3b ldr r3, [r7, #32]
|
|
8002952: fa93 f3a3 rbit r3, r3
|
|
8002956: 61fb str r3, [r7, #28]
|
|
return result;
|
|
8002958: 69fb ldr r3, [r7, #28]
|
|
800295a: 627b str r3, [r7, #36] @ 0x24
|
|
if (value == 0U)
|
|
800295c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800295e: 2b00 cmp r3, #0
|
|
8002960: d101 bne.n 8002966 <HAL_ADC_ConfigChannel+0x62e>
|
|
return 32U;
|
|
8002962: 2320 movs r3, #32
|
|
8002964: e003 b.n 800296e <HAL_ADC_ConfigChannel+0x636>
|
|
return __builtin_clz(value);
|
|
8002966: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8002968: fab3 f383 clz r3, r3
|
|
800296c: b2db uxtb r3, r3
|
|
800296e: 3301 adds r3, #1
|
|
8002970: f003 031f and.w r3, r3, #31
|
|
8002974: 2101 movs r1, #1
|
|
8002976: fa01 f303 lsl.w r3, r1, r3
|
|
800297a: ea42 0103 orr.w r1, r2, r3
|
|
800297e: 683b ldr r3, [r7, #0]
|
|
8002980: 681b ldr r3, [r3, #0]
|
|
8002982: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002986: 2b00 cmp r3, #0
|
|
8002988: d10d bne.n 80029a6 <HAL_ADC_ConfigChannel+0x66e>
|
|
800298a: 683b ldr r3, [r7, #0]
|
|
800298c: 681b ldr r3, [r3, #0]
|
|
800298e: 0e9b lsrs r3, r3, #26
|
|
8002990: 3301 adds r3, #1
|
|
8002992: f003 021f and.w r2, r3, #31
|
|
8002996: 4613 mov r3, r2
|
|
8002998: 005b lsls r3, r3, #1
|
|
800299a: 4413 add r3, r2
|
|
800299c: 3b1e subs r3, #30
|
|
800299e: 051b lsls r3, r3, #20
|
|
80029a0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
80029a4: e01e b.n 80029e4 <HAL_ADC_ConfigChannel+0x6ac>
|
|
80029a6: 683b ldr r3, [r7, #0]
|
|
80029a8: 681b ldr r3, [r3, #0]
|
|
80029aa: 617b str r3, [r7, #20]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80029ac: 697b ldr r3, [r7, #20]
|
|
80029ae: fa93 f3a3 rbit r3, r3
|
|
80029b2: 613b str r3, [r7, #16]
|
|
return result;
|
|
80029b4: 693b ldr r3, [r7, #16]
|
|
80029b6: 61bb str r3, [r7, #24]
|
|
if (value == 0U)
|
|
80029b8: 69bb ldr r3, [r7, #24]
|
|
80029ba: 2b00 cmp r3, #0
|
|
80029bc: d104 bne.n 80029c8 <HAL_ADC_ConfigChannel+0x690>
|
|
return 32U;
|
|
80029be: 2320 movs r3, #32
|
|
80029c0: e006 b.n 80029d0 <HAL_ADC_ConfigChannel+0x698>
|
|
80029c2: bf00 nop
|
|
80029c4: 407f0000 .word 0x407f0000
|
|
return __builtin_clz(value);
|
|
80029c8: 69bb ldr r3, [r7, #24]
|
|
80029ca: fab3 f383 clz r3, r3
|
|
80029ce: b2db uxtb r3, r3
|
|
80029d0: 3301 adds r3, #1
|
|
80029d2: f003 021f and.w r2, r3, #31
|
|
80029d6: 4613 mov r3, r2
|
|
80029d8: 005b lsls r3, r3, #1
|
|
80029da: 4413 add r3, r2
|
|
80029dc: 3b1e subs r3, #30
|
|
80029de: 051b lsls r3, r3, #20
|
|
80029e0: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
80029e4: 430b orrs r3, r1
|
|
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
|
|
+ 1UL) & 0x1FUL)),
|
|
pConfig->SamplingTime);
|
|
80029e6: 683a ldr r2, [r7, #0]
|
|
80029e8: 6892 ldr r2, [r2, #8]
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
80029ea: 4619 mov r1, r3
|
|
80029ec: f7fe ffe1 bl 80019b2 <LL_ADC_SetChannelSamplingTime>
|
|
/* If internal channel selected, enable dedicated internal buffers and */
|
|
/* paths. */
|
|
/* Note: these internal measurement paths can be disabled using */
|
|
/* HAL_ADC_DeInit(). */
|
|
|
|
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
|
|
80029f0: 683b ldr r3, [r7, #0]
|
|
80029f2: 681a ldr r2, [r3, #0]
|
|
80029f4: 4b3f ldr r3, [pc, #252] @ (8002af4 <HAL_ADC_ConfigChannel+0x7bc>)
|
|
80029f6: 4013 ands r3, r2
|
|
80029f8: 2b00 cmp r3, #0
|
|
80029fa: d071 beq.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
{
|
|
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
80029fc: 483e ldr r0, [pc, #248] @ (8002af8 <HAL_ADC_ConfigChannel+0x7c0>)
|
|
80029fe: f7fe feed bl 80017dc <LL_ADC_GetCommonPathInternalCh>
|
|
8002a02: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4
|
|
|
|
/* If the requested internal measurement path has already been enabled, */
|
|
/* bypass the configuration processing. */
|
|
if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
|
|
8002a06: 683b ldr r3, [r7, #0]
|
|
8002a08: 681b ldr r3, [r3, #0]
|
|
8002a0a: 4a3c ldr r2, [pc, #240] @ (8002afc <HAL_ADC_ConfigChannel+0x7c4>)
|
|
8002a0c: 4293 cmp r3, r2
|
|
8002a0e: d004 beq.n 8002a1a <HAL_ADC_ConfigChannel+0x6e2>
|
|
8002a10: 683b ldr r3, [r7, #0]
|
|
8002a12: 681b ldr r3, [r3, #0]
|
|
8002a14: 4a3a ldr r2, [pc, #232] @ (8002b00 <HAL_ADC_ConfigChannel+0x7c8>)
|
|
8002a16: 4293 cmp r3, r2
|
|
8002a18: d127 bne.n 8002a6a <HAL_ADC_ConfigChannel+0x732>
|
|
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
|
8002a1a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8002a1e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8002a22: 2b00 cmp r3, #0
|
|
8002a24: d121 bne.n 8002a6a <HAL_ADC_ConfigChannel+0x732>
|
|
{
|
|
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
|
8002a26: 687b ldr r3, [r7, #4]
|
|
8002a28: 681b ldr r3, [r3, #0]
|
|
8002a2a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002a2e: d157 bne.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8002a30: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8002a34: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
|
|
8002a38: 4619 mov r1, r3
|
|
8002a3a: 482f ldr r0, [pc, #188] @ (8002af8 <HAL_ADC_ConfigChannel+0x7c0>)
|
|
8002a3c: f7fe febb bl 80017b6 <LL_ADC_SetCommonPathInternalCh>
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Wait loop initialization and execution */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
8002a40: 4b30 ldr r3, [pc, #192] @ (8002b04 <HAL_ADC_ConfigChannel+0x7cc>)
|
|
8002a42: 681b ldr r3, [r3, #0]
|
|
8002a44: 099b lsrs r3, r3, #6
|
|
8002a46: 4a30 ldr r2, [pc, #192] @ (8002b08 <HAL_ADC_ConfigChannel+0x7d0>)
|
|
8002a48: fba2 2303 umull r2, r3, r2, r3
|
|
8002a4c: 099b lsrs r3, r3, #6
|
|
8002a4e: 1c5a adds r2, r3, #1
|
|
8002a50: 4613 mov r3, r2
|
|
8002a52: 005b lsls r3, r3, #1
|
|
8002a54: 4413 add r3, r2
|
|
8002a56: 009b lsls r3, r3, #2
|
|
8002a58: 60fb str r3, [r7, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8002a5a: e002 b.n 8002a62 <HAL_ADC_ConfigChannel+0x72a>
|
|
{
|
|
wait_loop_index--;
|
|
8002a5c: 68fb ldr r3, [r7, #12]
|
|
8002a5e: 3b01 subs r3, #1
|
|
8002a60: 60fb str r3, [r7, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8002a62: 68fb ldr r3, [r7, #12]
|
|
8002a64: 2b00 cmp r3, #0
|
|
8002a66: d1f9 bne.n 8002a5c <HAL_ADC_ConfigChannel+0x724>
|
|
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
|
8002a68: e03a b.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
|
|
8002a6a: 683b ldr r3, [r7, #0]
|
|
8002a6c: 681b ldr r3, [r3, #0]
|
|
8002a6e: 4a27 ldr r2, [pc, #156] @ (8002b0c <HAL_ADC_ConfigChannel+0x7d4>)
|
|
8002a70: 4293 cmp r3, r2
|
|
8002a72: d113 bne.n 8002a9c <HAL_ADC_ConfigChannel+0x764>
|
|
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
|
8002a74: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8002a78: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
8002a7c: 2b00 cmp r3, #0
|
|
8002a7e: d10d bne.n 8002a9c <HAL_ADC_ConfigChannel+0x764>
|
|
{
|
|
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
|
8002a80: 687b ldr r3, [r7, #4]
|
|
8002a82: 681b ldr r3, [r3, #0]
|
|
8002a84: 4a22 ldr r2, [pc, #136] @ (8002b10 <HAL_ADC_ConfigChannel+0x7d8>)
|
|
8002a86: 4293 cmp r3, r2
|
|
8002a88: d02a beq.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8002a8a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8002a8e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8002a92: 4619 mov r1, r3
|
|
8002a94: 4818 ldr r0, [pc, #96] @ (8002af8 <HAL_ADC_ConfigChannel+0x7c0>)
|
|
8002a96: f7fe fe8e bl 80017b6 <LL_ADC_SetCommonPathInternalCh>
|
|
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
|
8002a9a: e021 b.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
|
|
}
|
|
}
|
|
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
|
|
8002a9c: 683b ldr r3, [r7, #0]
|
|
8002a9e: 681b ldr r3, [r3, #0]
|
|
8002aa0: 4a1c ldr r2, [pc, #112] @ (8002b14 <HAL_ADC_ConfigChannel+0x7dc>)
|
|
8002aa2: 4293 cmp r3, r2
|
|
8002aa4: d11c bne.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
|
8002aa6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8002aaa: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8002aae: 2b00 cmp r3, #0
|
|
8002ab0: d116 bne.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
{
|
|
if (ADC_VREFINT_INSTANCE(hadc))
|
|
8002ab2: 687b ldr r3, [r7, #4]
|
|
8002ab4: 681b ldr r3, [r3, #0]
|
|
8002ab6: 4a16 ldr r2, [pc, #88] @ (8002b10 <HAL_ADC_ConfigChannel+0x7d8>)
|
|
8002ab8: 4293 cmp r3, r2
|
|
8002aba: d011 beq.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8002abc: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
|
|
8002ac0: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8002ac4: 4619 mov r1, r3
|
|
8002ac6: 480c ldr r0, [pc, #48] @ (8002af8 <HAL_ADC_ConfigChannel+0x7c0>)
|
|
8002ac8: f7fe fe75 bl 80017b6 <LL_ADC_SetCommonPathInternalCh>
|
|
8002acc: e008 b.n 8002ae0 <HAL_ADC_ConfigChannel+0x7a8>
|
|
/* channel could be done on neither of the channel configuration structure */
|
|
/* parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8002ace: 687b ldr r3, [r7, #4]
|
|
8002ad0: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002ad2: f043 0220 orr.w r2, r3, #32
|
|
8002ad6: 687b ldr r3, [r7, #4]
|
|
8002ad8: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002ada: 2301 movs r3, #1
|
|
8002adc: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8002ae0: 687b ldr r3, [r7, #4]
|
|
8002ae2: 2200 movs r2, #0
|
|
8002ae4: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8002ae8: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7
|
|
}
|
|
8002aec: 4618 mov r0, r3
|
|
8002aee: 37d8 adds r7, #216 @ 0xd8
|
|
8002af0: 46bd mov sp, r7
|
|
8002af2: bd80 pop {r7, pc}
|
|
8002af4: 80080000 .word 0x80080000
|
|
8002af8: 50000300 .word 0x50000300
|
|
8002afc: c3210000 .word 0xc3210000
|
|
8002b00: 90c00010 .word 0x90c00010
|
|
8002b04: 2000001c .word 0x2000001c
|
|
8002b08: 053e2d63 .word 0x053e2d63
|
|
8002b0c: c7520000 .word 0xc7520000
|
|
8002b10: 50000100 .word 0x50000100
|
|
8002b14: cb840000 .word 0xcb840000
|
|
|
|
08002b18 <ADC_ConversionStop>:
|
|
* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
|
|
* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
|
|
{
|
|
8002b18: b580 push {r7, lr}
|
|
8002b1a: b088 sub sp, #32
|
|
8002b1c: af00 add r7, sp, #0
|
|
8002b1e: 6078 str r0, [r7, #4]
|
|
8002b20: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
|
|
8002b22: 2300 movs r3, #0
|
|
8002b24: 61fb str r3, [r7, #28]
|
|
uint32_t conversion_group_reassigned = ConversionGroup;
|
|
8002b26: 683b ldr r3, [r7, #0]
|
|
8002b28: 61bb str r3, [r7, #24]
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
|
|
|
|
/* Verification if ADC is not already stopped (on regular and injected */
|
|
/* groups) to bypass this function if not needed. */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
8002b2a: 687b ldr r3, [r7, #4]
|
|
8002b2c: 681b ldr r3, [r3, #0]
|
|
8002b2e: 4618 mov r0, r3
|
|
8002b30: f7ff f86e bl 8001c10 <LL_ADC_REG_IsConversionOngoing>
|
|
8002b34: 6138 str r0, [r7, #16]
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
8002b36: 687b ldr r3, [r7, #4]
|
|
8002b38: 681b ldr r3, [r3, #0]
|
|
8002b3a: 4618 mov r0, r3
|
|
8002b3c: f7ff f88f bl 8001c5e <LL_ADC_INJ_IsConversionOngoing>
|
|
8002b40: 60f8 str r0, [r7, #12]
|
|
if ((tmp_adc_is_conversion_on_going_regular != 0UL)
|
|
8002b42: 693b ldr r3, [r7, #16]
|
|
8002b44: 2b00 cmp r3, #0
|
|
8002b46: d103 bne.n 8002b50 <ADC_ConversionStop+0x38>
|
|
|| (tmp_adc_is_conversion_on_going_injected != 0UL)
|
|
8002b48: 68fb ldr r3, [r7, #12]
|
|
8002b4a: 2b00 cmp r3, #0
|
|
8002b4c: f000 8098 beq.w 8002c80 <ADC_ConversionStop+0x168>
|
|
/* auto-delay mode. */
|
|
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
|
|
/* injected group stop ADC_CR_JADSTP). */
|
|
/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
|
|
/* (see reference manual). */
|
|
if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
|
|
8002b50: 687b ldr r3, [r7, #4]
|
|
8002b52: 681b ldr r3, [r3, #0]
|
|
8002b54: 68db ldr r3, [r3, #12]
|
|
8002b56: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002b5a: 2b00 cmp r3, #0
|
|
8002b5c: d02a beq.n 8002bb4 <ADC_ConversionStop+0x9c>
|
|
&& (hadc->Init.ContinuousConvMode == ENABLE)
|
|
8002b5e: 687b ldr r3, [r7, #4]
|
|
8002b60: 7f5b ldrb r3, [r3, #29]
|
|
8002b62: 2b01 cmp r3, #1
|
|
8002b64: d126 bne.n 8002bb4 <ADC_ConversionStop+0x9c>
|
|
&& (hadc->Init.LowPowerAutoWait == ENABLE)
|
|
8002b66: 687b ldr r3, [r7, #4]
|
|
8002b68: 7f1b ldrb r3, [r3, #28]
|
|
8002b6a: 2b01 cmp r3, #1
|
|
8002b6c: d122 bne.n 8002bb4 <ADC_ConversionStop+0x9c>
|
|
)
|
|
{
|
|
/* Use stop of regular group */
|
|
conversion_group_reassigned = ADC_REGULAR_GROUP;
|
|
8002b6e: 2301 movs r3, #1
|
|
8002b70: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
|
|
8002b72: e014 b.n 8002b9e <ADC_ConversionStop+0x86>
|
|
{
|
|
if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
|
|
8002b74: 69fb ldr r3, [r7, #28]
|
|
8002b76: 4a45 ldr r2, [pc, #276] @ (8002c8c <ADC_ConversionStop+0x174>)
|
|
8002b78: 4293 cmp r3, r2
|
|
8002b7a: d90d bls.n 8002b98 <ADC_ConversionStop+0x80>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002b7c: 687b ldr r3, [r7, #4]
|
|
8002b7e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002b80: f043 0210 orr.w r2, r3, #16
|
|
8002b84: 687b ldr r3, [r7, #4]
|
|
8002b86: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002b88: 687b ldr r3, [r7, #4]
|
|
8002b8a: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002b8c: f043 0201 orr.w r2, r3, #1
|
|
8002b90: 687b ldr r3, [r7, #4]
|
|
8002b92: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
return HAL_ERROR;
|
|
8002b94: 2301 movs r3, #1
|
|
8002b96: e074 b.n 8002c82 <ADC_ConversionStop+0x16a>
|
|
}
|
|
Conversion_Timeout_CPU_cycles ++;
|
|
8002b98: 69fb ldr r3, [r7, #28]
|
|
8002b9a: 3301 adds r3, #1
|
|
8002b9c: 61fb str r3, [r7, #28]
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
|
|
8002b9e: 687b ldr r3, [r7, #4]
|
|
8002ba0: 681b ldr r3, [r3, #0]
|
|
8002ba2: 681b ldr r3, [r3, #0]
|
|
8002ba4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002ba8: 2b40 cmp r3, #64 @ 0x40
|
|
8002baa: d1e3 bne.n 8002b74 <ADC_ConversionStop+0x5c>
|
|
}
|
|
|
|
/* Clear JEOS */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
|
|
8002bac: 687b ldr r3, [r7, #4]
|
|
8002bae: 681b ldr r3, [r3, #0]
|
|
8002bb0: 2240 movs r2, #64 @ 0x40
|
|
8002bb2: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Stop potential conversion on going on ADC group regular */
|
|
if (conversion_group_reassigned != ADC_INJECTED_GROUP)
|
|
8002bb4: 69bb ldr r3, [r7, #24]
|
|
8002bb6: 2b02 cmp r3, #2
|
|
8002bb8: d014 beq.n 8002be4 <ADC_ConversionStop+0xcc>
|
|
{
|
|
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
|
|
8002bba: 687b ldr r3, [r7, #4]
|
|
8002bbc: 681b ldr r3, [r3, #0]
|
|
8002bbe: 4618 mov r0, r3
|
|
8002bc0: f7ff f826 bl 8001c10 <LL_ADC_REG_IsConversionOngoing>
|
|
8002bc4: 4603 mov r3, r0
|
|
8002bc6: 2b00 cmp r3, #0
|
|
8002bc8: d00c beq.n 8002be4 <ADC_ConversionStop+0xcc>
|
|
{
|
|
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
|
|
8002bca: 687b ldr r3, [r7, #4]
|
|
8002bcc: 681b ldr r3, [r3, #0]
|
|
8002bce: 4618 mov r0, r3
|
|
8002bd0: f7fe ffe3 bl 8001b9a <LL_ADC_IsDisableOngoing>
|
|
8002bd4: 4603 mov r3, r0
|
|
8002bd6: 2b00 cmp r3, #0
|
|
8002bd8: d104 bne.n 8002be4 <ADC_ConversionStop+0xcc>
|
|
{
|
|
/* Stop ADC group regular conversion */
|
|
LL_ADC_REG_StopConversion(hadc->Instance);
|
|
8002bda: 687b ldr r3, [r7, #4]
|
|
8002bdc: 681b ldr r3, [r3, #0]
|
|
8002bde: 4618 mov r0, r3
|
|
8002be0: f7ff f802 bl 8001be8 <LL_ADC_REG_StopConversion>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Stop potential conversion on going on ADC group injected */
|
|
if (conversion_group_reassigned != ADC_REGULAR_GROUP)
|
|
8002be4: 69bb ldr r3, [r7, #24]
|
|
8002be6: 2b01 cmp r3, #1
|
|
8002be8: d014 beq.n 8002c14 <ADC_ConversionStop+0xfc>
|
|
{
|
|
/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
|
|
8002bea: 687b ldr r3, [r7, #4]
|
|
8002bec: 681b ldr r3, [r3, #0]
|
|
8002bee: 4618 mov r0, r3
|
|
8002bf0: f7ff f835 bl 8001c5e <LL_ADC_INJ_IsConversionOngoing>
|
|
8002bf4: 4603 mov r3, r0
|
|
8002bf6: 2b00 cmp r3, #0
|
|
8002bf8: d00c beq.n 8002c14 <ADC_ConversionStop+0xfc>
|
|
{
|
|
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
|
|
8002bfa: 687b ldr r3, [r7, #4]
|
|
8002bfc: 681b ldr r3, [r3, #0]
|
|
8002bfe: 4618 mov r0, r3
|
|
8002c00: f7fe ffcb bl 8001b9a <LL_ADC_IsDisableOngoing>
|
|
8002c04: 4603 mov r3, r0
|
|
8002c06: 2b00 cmp r3, #0
|
|
8002c08: d104 bne.n 8002c14 <ADC_ConversionStop+0xfc>
|
|
{
|
|
/* Stop ADC group injected conversion */
|
|
LL_ADC_INJ_StopConversion(hadc->Instance);
|
|
8002c0a: 687b ldr r3, [r7, #4]
|
|
8002c0c: 681b ldr r3, [r3, #0]
|
|
8002c0e: 4618 mov r0, r3
|
|
8002c10: f7ff f811 bl 8001c36 <LL_ADC_INJ_StopConversion>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Selection of start and stop bits with respect to the regular or injected group */
|
|
switch (conversion_group_reassigned)
|
|
8002c14: 69bb ldr r3, [r7, #24]
|
|
8002c16: 2b02 cmp r3, #2
|
|
8002c18: d005 beq.n 8002c26 <ADC_ConversionStop+0x10e>
|
|
8002c1a: 69bb ldr r3, [r7, #24]
|
|
8002c1c: 2b03 cmp r3, #3
|
|
8002c1e: d105 bne.n 8002c2c <ADC_ConversionStop+0x114>
|
|
{
|
|
case ADC_REGULAR_INJECTED_GROUP:
|
|
tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
|
|
8002c20: 230c movs r3, #12
|
|
8002c22: 617b str r3, [r7, #20]
|
|
break;
|
|
8002c24: e005 b.n 8002c32 <ADC_ConversionStop+0x11a>
|
|
case ADC_INJECTED_GROUP:
|
|
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
|
|
8002c26: 2308 movs r3, #8
|
|
8002c28: 617b str r3, [r7, #20]
|
|
break;
|
|
8002c2a: e002 b.n 8002c32 <ADC_ConversionStop+0x11a>
|
|
/* Case ADC_REGULAR_GROUP only*/
|
|
default:
|
|
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
|
|
8002c2c: 2304 movs r3, #4
|
|
8002c2e: 617b str r3, [r7, #20]
|
|
break;
|
|
8002c30: bf00 nop
|
|
}
|
|
|
|
/* Wait for conversion effectively stopped */
|
|
tickstart = HAL_GetTick();
|
|
8002c32: f7fe fda1 bl 8001778 <HAL_GetTick>
|
|
8002c36: 60b8 str r0, [r7, #8]
|
|
|
|
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
|
|
8002c38: e01b b.n 8002c72 <ADC_ConversionStop+0x15a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
|
8002c3a: f7fe fd9d bl 8001778 <HAL_GetTick>
|
|
8002c3e: 4602 mov r2, r0
|
|
8002c40: 68bb ldr r3, [r7, #8]
|
|
8002c42: 1ad3 subs r3, r2, r3
|
|
8002c44: 2b05 cmp r3, #5
|
|
8002c46: d914 bls.n 8002c72 <ADC_ConversionStop+0x15a>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
|
|
8002c48: 687b ldr r3, [r7, #4]
|
|
8002c4a: 681b ldr r3, [r3, #0]
|
|
8002c4c: 689a ldr r2, [r3, #8]
|
|
8002c4e: 697b ldr r3, [r7, #20]
|
|
8002c50: 4013 ands r3, r2
|
|
8002c52: 2b00 cmp r3, #0
|
|
8002c54: d00d beq.n 8002c72 <ADC_ConversionStop+0x15a>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002c56: 687b ldr r3, [r7, #4]
|
|
8002c58: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002c5a: f043 0210 orr.w r2, r3, #16
|
|
8002c5e: 687b ldr r3, [r7, #4]
|
|
8002c60: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002c62: 687b ldr r3, [r7, #4]
|
|
8002c64: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002c66: f043 0201 orr.w r2, r3, #1
|
|
8002c6a: 687b ldr r3, [r7, #4]
|
|
8002c6c: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
return HAL_ERROR;
|
|
8002c6e: 2301 movs r3, #1
|
|
8002c70: e007 b.n 8002c82 <ADC_ConversionStop+0x16a>
|
|
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
|
|
8002c72: 687b ldr r3, [r7, #4]
|
|
8002c74: 681b ldr r3, [r3, #0]
|
|
8002c76: 689a ldr r2, [r3, #8]
|
|
8002c78: 697b ldr r3, [r7, #20]
|
|
8002c7a: 4013 ands r3, r2
|
|
8002c7c: 2b00 cmp r3, #0
|
|
8002c7e: d1dc bne.n 8002c3a <ADC_ConversionStop+0x122>
|
|
}
|
|
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
8002c80: 2300 movs r3, #0
|
|
}
|
|
8002c82: 4618 mov r0, r3
|
|
8002c84: 3720 adds r7, #32
|
|
8002c86: 46bd mov sp, r7
|
|
8002c88: bd80 pop {r7, pc}
|
|
8002c8a: bf00 nop
|
|
8002c8c: a33fffff .word 0xa33fffff
|
|
|
|
08002c90 <ADC_Enable>:
|
|
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8002c90: b580 push {r7, lr}
|
|
8002c92: b084 sub sp, #16
|
|
8002c94: af00 add r7, sp, #0
|
|
8002c96: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8002c98: 2300 movs r3, #0
|
|
8002c9a: 60bb str r3, [r7, #8]
|
|
|
|
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
|
|
/* enabling phase not yet completed: flag ADC ready not yet set). */
|
|
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
|
|
/* causes: ADC clock not running, ...). */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
8002c9c: 687b ldr r3, [r7, #4]
|
|
8002c9e: 681b ldr r3, [r3, #0]
|
|
8002ca0: 4618 mov r0, r3
|
|
8002ca2: f7fe ff67 bl 8001b74 <LL_ADC_IsEnabled>
|
|
8002ca6: 4603 mov r3, r0
|
|
8002ca8: 2b00 cmp r3, #0
|
|
8002caa: d169 bne.n 8002d80 <ADC_Enable+0xf0>
|
|
{
|
|
/* Check if conditions to enable the ADC are fulfilled */
|
|
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
|
|
8002cac: 687b ldr r3, [r7, #4]
|
|
8002cae: 681b ldr r3, [r3, #0]
|
|
8002cb0: 689a ldr r2, [r3, #8]
|
|
8002cb2: 4b36 ldr r3, [pc, #216] @ (8002d8c <ADC_Enable+0xfc>)
|
|
8002cb4: 4013 ands r3, r2
|
|
8002cb6: 2b00 cmp r3, #0
|
|
8002cb8: d00d beq.n 8002cd6 <ADC_Enable+0x46>
|
|
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002cba: 687b ldr r3, [r7, #4]
|
|
8002cbc: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002cbe: f043 0210 orr.w r2, r3, #16
|
|
8002cc2: 687b ldr r3, [r7, #4]
|
|
8002cc4: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002cc6: 687b ldr r3, [r7, #4]
|
|
8002cc8: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002cca: f043 0201 orr.w r2, r3, #1
|
|
8002cce: 687b ldr r3, [r7, #4]
|
|
8002cd0: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
return HAL_ERROR;
|
|
8002cd2: 2301 movs r3, #1
|
|
8002cd4: e055 b.n 8002d82 <ADC_Enable+0xf2>
|
|
}
|
|
|
|
/* Enable the ADC peripheral */
|
|
LL_ADC_Enable(hadc->Instance);
|
|
8002cd6: 687b ldr r3, [r7, #4]
|
|
8002cd8: 681b ldr r3, [r3, #0]
|
|
8002cda: 4618 mov r0, r3
|
|
8002cdc: f7fe ff22 bl 8001b24 <LL_ADC_Enable>
|
|
|
|
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
|
|
8002ce0: 482b ldr r0, [pc, #172] @ (8002d90 <ADC_Enable+0x100>)
|
|
8002ce2: f7fe fd7b bl 80017dc <LL_ADC_GetCommonPathInternalCh>
|
|
8002ce6: 4603 mov r3, r0
|
|
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
|
|
8002ce8: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
|
|
8002cec: 2b00 cmp r3, #0
|
|
8002cee: d013 beq.n 8002d18 <ADC_Enable+0x88>
|
|
|
|
/* Wait loop initialization and execution */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
8002cf0: 4b28 ldr r3, [pc, #160] @ (8002d94 <ADC_Enable+0x104>)
|
|
8002cf2: 681b ldr r3, [r3, #0]
|
|
8002cf4: 099b lsrs r3, r3, #6
|
|
8002cf6: 4a28 ldr r2, [pc, #160] @ (8002d98 <ADC_Enable+0x108>)
|
|
8002cf8: fba2 2303 umull r2, r3, r2, r3
|
|
8002cfc: 099b lsrs r3, r3, #6
|
|
8002cfe: 1c5a adds r2, r3, #1
|
|
8002d00: 4613 mov r3, r2
|
|
8002d02: 005b lsls r3, r3, #1
|
|
8002d04: 4413 add r3, r2
|
|
8002d06: 009b lsls r3, r3, #2
|
|
8002d08: 60bb str r3, [r7, #8]
|
|
while (wait_loop_index != 0UL)
|
|
8002d0a: e002 b.n 8002d12 <ADC_Enable+0x82>
|
|
{
|
|
wait_loop_index--;
|
|
8002d0c: 68bb ldr r3, [r7, #8]
|
|
8002d0e: 3b01 subs r3, #1
|
|
8002d10: 60bb str r3, [r7, #8]
|
|
while (wait_loop_index != 0UL)
|
|
8002d12: 68bb ldr r3, [r7, #8]
|
|
8002d14: 2b00 cmp r3, #0
|
|
8002d16: d1f9 bne.n 8002d0c <ADC_Enable+0x7c>
|
|
}
|
|
}
|
|
|
|
/* Wait for ADC effectively enabled */
|
|
tickstart = HAL_GetTick();
|
|
8002d18: f7fe fd2e bl 8001778 <HAL_GetTick>
|
|
8002d1c: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
|
8002d1e: e028 b.n 8002d72 <ADC_Enable+0xe2>
|
|
The workaround is to continue setting ADEN until ADRDY is becomes 1.
|
|
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
|
|
4 ADC clock cycle duration */
|
|
/* Note: Test of ADC enabled required due to hardware constraint to */
|
|
/* not enable ADC if already enabled. */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
8002d20: 687b ldr r3, [r7, #4]
|
|
8002d22: 681b ldr r3, [r3, #0]
|
|
8002d24: 4618 mov r0, r3
|
|
8002d26: f7fe ff25 bl 8001b74 <LL_ADC_IsEnabled>
|
|
8002d2a: 4603 mov r3, r0
|
|
8002d2c: 2b00 cmp r3, #0
|
|
8002d2e: d104 bne.n 8002d3a <ADC_Enable+0xaa>
|
|
{
|
|
LL_ADC_Enable(hadc->Instance);
|
|
8002d30: 687b ldr r3, [r7, #4]
|
|
8002d32: 681b ldr r3, [r3, #0]
|
|
8002d34: 4618 mov r0, r3
|
|
8002d36: f7fe fef5 bl 8001b24 <LL_ADC_Enable>
|
|
}
|
|
|
|
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
|
|
8002d3a: f7fe fd1d bl 8001778 <HAL_GetTick>
|
|
8002d3e: 4602 mov r2, r0
|
|
8002d40: 68fb ldr r3, [r7, #12]
|
|
8002d42: 1ad3 subs r3, r2, r3
|
|
8002d44: 2b02 cmp r3, #2
|
|
8002d46: d914 bls.n 8002d72 <ADC_Enable+0xe2>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
|
8002d48: 687b ldr r3, [r7, #4]
|
|
8002d4a: 681b ldr r3, [r3, #0]
|
|
8002d4c: 681b ldr r3, [r3, #0]
|
|
8002d4e: f003 0301 and.w r3, r3, #1
|
|
8002d52: 2b01 cmp r3, #1
|
|
8002d54: d00d beq.n 8002d72 <ADC_Enable+0xe2>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002d56: 687b ldr r3, [r7, #4]
|
|
8002d58: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002d5a: f043 0210 orr.w r2, r3, #16
|
|
8002d5e: 687b ldr r3, [r7, #4]
|
|
8002d60: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002d62: 687b ldr r3, [r7, #4]
|
|
8002d64: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002d66: f043 0201 orr.w r2, r3, #1
|
|
8002d6a: 687b ldr r3, [r7, #4]
|
|
8002d6c: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
return HAL_ERROR;
|
|
8002d6e: 2301 movs r3, #1
|
|
8002d70: e007 b.n 8002d82 <ADC_Enable+0xf2>
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
|
8002d72: 687b ldr r3, [r7, #4]
|
|
8002d74: 681b ldr r3, [r3, #0]
|
|
8002d76: 681b ldr r3, [r3, #0]
|
|
8002d78: f003 0301 and.w r3, r3, #1
|
|
8002d7c: 2b01 cmp r3, #1
|
|
8002d7e: d1cf bne.n 8002d20 <ADC_Enable+0x90>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
8002d80: 2300 movs r3, #0
|
|
}
|
|
8002d82: 4618 mov r0, r3
|
|
8002d84: 3710 adds r7, #16
|
|
8002d86: 46bd mov sp, r7
|
|
8002d88: bd80 pop {r7, pc}
|
|
8002d8a: bf00 nop
|
|
8002d8c: 8000003f .word 0x8000003f
|
|
8002d90: 50000300 .word 0x50000300
|
|
8002d94: 2000001c .word 0x2000001c
|
|
8002d98: 053e2d63 .word 0x053e2d63
|
|
|
|
08002d9c <ADC_Disable>:
|
|
* stopped.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8002d9c: b580 push {r7, lr}
|
|
8002d9e: b084 sub sp, #16
|
|
8002da0: af00 add r7, sp, #0
|
|
8002da2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
|
|
8002da4: 687b ldr r3, [r7, #4]
|
|
8002da6: 681b ldr r3, [r3, #0]
|
|
8002da8: 4618 mov r0, r3
|
|
8002daa: f7fe fef6 bl 8001b9a <LL_ADC_IsDisableOngoing>
|
|
8002dae: 60f8 str r0, [r7, #12]
|
|
|
|
/* Verification if ADC is not already disabled: */
|
|
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
|
|
/* disabled. */
|
|
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
|
|
8002db0: 687b ldr r3, [r7, #4]
|
|
8002db2: 681b ldr r3, [r3, #0]
|
|
8002db4: 4618 mov r0, r3
|
|
8002db6: f7fe fedd bl 8001b74 <LL_ADC_IsEnabled>
|
|
8002dba: 4603 mov r3, r0
|
|
8002dbc: 2b00 cmp r3, #0
|
|
8002dbe: d047 beq.n 8002e50 <ADC_Disable+0xb4>
|
|
&& (tmp_adc_is_disable_on_going == 0UL)
|
|
8002dc0: 68fb ldr r3, [r7, #12]
|
|
8002dc2: 2b00 cmp r3, #0
|
|
8002dc4: d144 bne.n 8002e50 <ADC_Disable+0xb4>
|
|
)
|
|
{
|
|
/* Check if conditions to disable the ADC are fulfilled */
|
|
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
|
|
8002dc6: 687b ldr r3, [r7, #4]
|
|
8002dc8: 681b ldr r3, [r3, #0]
|
|
8002dca: 689b ldr r3, [r3, #8]
|
|
8002dcc: f003 030d and.w r3, r3, #13
|
|
8002dd0: 2b01 cmp r3, #1
|
|
8002dd2: d10c bne.n 8002dee <ADC_Disable+0x52>
|
|
{
|
|
/* Disable the ADC peripheral */
|
|
LL_ADC_Disable(hadc->Instance);
|
|
8002dd4: 687b ldr r3, [r7, #4]
|
|
8002dd6: 681b ldr r3, [r3, #0]
|
|
8002dd8: 4618 mov r0, r3
|
|
8002dda: f7fe feb7 bl 8001b4c <LL_ADC_Disable>
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
|
|
8002dde: 687b ldr r3, [r7, #4]
|
|
8002de0: 681b ldr r3, [r3, #0]
|
|
8002de2: 2203 movs r2, #3
|
|
8002de4: 601a str r2, [r3, #0]
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Wait for ADC effectively disabled */
|
|
/* Get tick count */
|
|
tickstart = HAL_GetTick();
|
|
8002de6: f7fe fcc7 bl 8001778 <HAL_GetTick>
|
|
8002dea: 60b8 str r0, [r7, #8]
|
|
|
|
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
|
8002dec: e029 b.n 8002e42 <ADC_Disable+0xa6>
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002dee: 687b ldr r3, [r7, #4]
|
|
8002df0: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002df2: f043 0210 orr.w r2, r3, #16
|
|
8002df6: 687b ldr r3, [r7, #4]
|
|
8002df8: 65da str r2, [r3, #92] @ 0x5c
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002dfa: 687b ldr r3, [r7, #4]
|
|
8002dfc: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002dfe: f043 0201 orr.w r2, r3, #1
|
|
8002e02: 687b ldr r3, [r7, #4]
|
|
8002e04: 661a str r2, [r3, #96] @ 0x60
|
|
return HAL_ERROR;
|
|
8002e06: 2301 movs r3, #1
|
|
8002e08: e023 b.n 8002e52 <ADC_Disable+0xb6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
|
|
8002e0a: f7fe fcb5 bl 8001778 <HAL_GetTick>
|
|
8002e0e: 4602 mov r2, r0
|
|
8002e10: 68bb ldr r3, [r7, #8]
|
|
8002e12: 1ad3 subs r3, r2, r3
|
|
8002e14: 2b02 cmp r3, #2
|
|
8002e16: d914 bls.n 8002e42 <ADC_Disable+0xa6>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
|
8002e18: 687b ldr r3, [r7, #4]
|
|
8002e1a: 681b ldr r3, [r3, #0]
|
|
8002e1c: 689b ldr r3, [r3, #8]
|
|
8002e1e: f003 0301 and.w r3, r3, #1
|
|
8002e22: 2b00 cmp r3, #0
|
|
8002e24: d00d beq.n 8002e42 <ADC_Disable+0xa6>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002e26: 687b ldr r3, [r7, #4]
|
|
8002e28: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002e2a: f043 0210 orr.w r2, r3, #16
|
|
8002e2e: 687b ldr r3, [r7, #4]
|
|
8002e30: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002e32: 687b ldr r3, [r7, #4]
|
|
8002e34: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002e36: f043 0201 orr.w r2, r3, #1
|
|
8002e3a: 687b ldr r3, [r7, #4]
|
|
8002e3c: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
return HAL_ERROR;
|
|
8002e3e: 2301 movs r3, #1
|
|
8002e40: e007 b.n 8002e52 <ADC_Disable+0xb6>
|
|
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
|
8002e42: 687b ldr r3, [r7, #4]
|
|
8002e44: 681b ldr r3, [r3, #0]
|
|
8002e46: 689b ldr r3, [r3, #8]
|
|
8002e48: f003 0301 and.w r3, r3, #1
|
|
8002e4c: 2b00 cmp r3, #0
|
|
8002e4e: d1dc bne.n 8002e0a <ADC_Disable+0x6e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
8002e50: 2300 movs r3, #0
|
|
}
|
|
8002e52: 4618 mov r0, r3
|
|
8002e54: 3710 adds r7, #16
|
|
8002e56: 46bd mov sp, r7
|
|
8002e58: bd80 pop {r7, pc}
|
|
|
|
08002e5a <LL_ADC_IsEnabled>:
|
|
{
|
|
8002e5a: b480 push {r7}
|
|
8002e5c: b083 sub sp, #12
|
|
8002e5e: af00 add r7, sp, #0
|
|
8002e60: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
|
|
8002e62: 687b ldr r3, [r7, #4]
|
|
8002e64: 689b ldr r3, [r3, #8]
|
|
8002e66: f003 0301 and.w r3, r3, #1
|
|
8002e6a: 2b01 cmp r3, #1
|
|
8002e6c: d101 bne.n 8002e72 <LL_ADC_IsEnabled+0x18>
|
|
8002e6e: 2301 movs r3, #1
|
|
8002e70: e000 b.n 8002e74 <LL_ADC_IsEnabled+0x1a>
|
|
8002e72: 2300 movs r3, #0
|
|
}
|
|
8002e74: 4618 mov r0, r3
|
|
8002e76: 370c adds r7, #12
|
|
8002e78: 46bd mov sp, r7
|
|
8002e7a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002e7e: 4770 bx lr
|
|
|
|
08002e80 <LL_ADC_StartCalibration>:
|
|
{
|
|
8002e80: b480 push {r7}
|
|
8002e82: b083 sub sp, #12
|
|
8002e84: af00 add r7, sp, #0
|
|
8002e86: 6078 str r0, [r7, #4]
|
|
8002e88: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCx->CR,
|
|
8002e8a: 687b ldr r3, [r7, #4]
|
|
8002e8c: 689b ldr r3, [r3, #8]
|
|
8002e8e: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000
|
|
8002e92: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
8002e96: 683a ldr r2, [r7, #0]
|
|
8002e98: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
|
|
8002e9c: 4313 orrs r3, r2
|
|
8002e9e: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
|
|
8002ea2: 687b ldr r3, [r7, #4]
|
|
8002ea4: 609a str r2, [r3, #8]
|
|
}
|
|
8002ea6: bf00 nop
|
|
8002ea8: 370c adds r7, #12
|
|
8002eaa: 46bd mov sp, r7
|
|
8002eac: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002eb0: 4770 bx lr
|
|
|
|
08002eb2 <LL_ADC_IsCalibrationOnGoing>:
|
|
{
|
|
8002eb2: b480 push {r7}
|
|
8002eb4: b083 sub sp, #12
|
|
8002eb6: af00 add r7, sp, #0
|
|
8002eb8: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
|
|
8002eba: 687b ldr r3, [r7, #4]
|
|
8002ebc: 689b ldr r3, [r3, #8]
|
|
8002ebe: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8002ec2: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8002ec6: d101 bne.n 8002ecc <LL_ADC_IsCalibrationOnGoing+0x1a>
|
|
8002ec8: 2301 movs r3, #1
|
|
8002eca: e000 b.n 8002ece <LL_ADC_IsCalibrationOnGoing+0x1c>
|
|
8002ecc: 2300 movs r3, #0
|
|
}
|
|
8002ece: 4618 mov r0, r3
|
|
8002ed0: 370c adds r7, #12
|
|
8002ed2: 46bd mov sp, r7
|
|
8002ed4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002ed8: 4770 bx lr
|
|
|
|
08002eda <LL_ADC_REG_IsConversionOngoing>:
|
|
{
|
|
8002eda: b480 push {r7}
|
|
8002edc: b083 sub sp, #12
|
|
8002ede: af00 add r7, sp, #0
|
|
8002ee0: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
|
|
8002ee2: 687b ldr r3, [r7, #4]
|
|
8002ee4: 689b ldr r3, [r3, #8]
|
|
8002ee6: f003 0304 and.w r3, r3, #4
|
|
8002eea: 2b04 cmp r3, #4
|
|
8002eec: d101 bne.n 8002ef2 <LL_ADC_REG_IsConversionOngoing+0x18>
|
|
8002eee: 2301 movs r3, #1
|
|
8002ef0: e000 b.n 8002ef4 <LL_ADC_REG_IsConversionOngoing+0x1a>
|
|
8002ef2: 2300 movs r3, #0
|
|
}
|
|
8002ef4: 4618 mov r0, r3
|
|
8002ef6: 370c adds r7, #12
|
|
8002ef8: 46bd mov sp, r7
|
|
8002efa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002efe: 4770 bx lr
|
|
|
|
08002f00 <HAL_ADCEx_Calibration_Start>:
|
|
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
|
|
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
|
|
{
|
|
8002f00: b580 push {r7, lr}
|
|
8002f02: b084 sub sp, #16
|
|
8002f04: af00 add r7, sp, #0
|
|
8002f06: 6078 str r0, [r7, #4]
|
|
8002f08: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8002f0a: 2300 movs r3, #0
|
|
8002f0c: 60bb str r3, [r7, #8]
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8002f0e: 687b ldr r3, [r7, #4]
|
|
8002f10: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
|
|
8002f14: 2b01 cmp r3, #1
|
|
8002f16: d101 bne.n 8002f1c <HAL_ADCEx_Calibration_Start+0x1c>
|
|
8002f18: 2302 movs r3, #2
|
|
8002f1a: e04d b.n 8002fb8 <HAL_ADCEx_Calibration_Start+0xb8>
|
|
8002f1c: 687b ldr r3, [r7, #4]
|
|
8002f1e: 2201 movs r2, #1
|
|
8002f20: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Calibration prerequisite: ADC must be disabled. */
|
|
|
|
/* Disable the ADC (if not already disabled) */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
8002f24: 6878 ldr r0, [r7, #4]
|
|
8002f26: f7ff ff39 bl 8002d9c <ADC_Disable>
|
|
8002f2a: 4603 mov r3, r0
|
|
8002f2c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
8002f2e: 7bfb ldrb r3, [r7, #15]
|
|
8002f30: 2b00 cmp r3, #0
|
|
8002f32: d136 bne.n 8002fa2 <HAL_ADCEx_Calibration_Start+0xa2>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002f34: 687b ldr r3, [r7, #4]
|
|
8002f36: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002f38: f423 5388 bic.w r3, r3, #4352 @ 0x1100
|
|
8002f3c: f023 0302 bic.w r3, r3, #2
|
|
8002f40: f043 0202 orr.w r2, r3, #2
|
|
8002f44: 687b ldr r3, [r7, #4]
|
|
8002f46: 65da str r2, [r3, #92] @ 0x5c
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_BUSY_INTERNAL);
|
|
|
|
/* Start ADC calibration in mode single-ended or differential */
|
|
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
|
|
8002f48: 687b ldr r3, [r7, #4]
|
|
8002f4a: 681b ldr r3, [r3, #0]
|
|
8002f4c: 6839 ldr r1, [r7, #0]
|
|
8002f4e: 4618 mov r0, r3
|
|
8002f50: f7ff ff96 bl 8002e80 <LL_ADC_StartCalibration>
|
|
|
|
/* Wait for calibration completion */
|
|
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
|
|
8002f54: e014 b.n 8002f80 <HAL_ADCEx_Calibration_Start+0x80>
|
|
{
|
|
wait_loop_index++;
|
|
8002f56: 68bb ldr r3, [r7, #8]
|
|
8002f58: 3301 adds r3, #1
|
|
8002f5a: 60bb str r3, [r7, #8]
|
|
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
|
|
8002f5c: 68bb ldr r3, [r7, #8]
|
|
8002f5e: 4a18 ldr r2, [pc, #96] @ (8002fc0 <HAL_ADCEx_Calibration_Start+0xc0>)
|
|
8002f60: 4293 cmp r3, r2
|
|
8002f62: d90d bls.n 8002f80 <HAL_ADCEx_Calibration_Start+0x80>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002f64: 687b ldr r3, [r7, #4]
|
|
8002f66: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002f68: f023 0312 bic.w r3, r3, #18
|
|
8002f6c: f043 0210 orr.w r2, r3, #16
|
|
8002f70: 687b ldr r3, [r7, #4]
|
|
8002f72: 65da str r2, [r3, #92] @ 0x5c
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8002f74: 687b ldr r3, [r7, #4]
|
|
8002f76: 2200 movs r2, #0
|
|
8002f78: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
return HAL_ERROR;
|
|
8002f7c: 2301 movs r3, #1
|
|
8002f7e: e01b b.n 8002fb8 <HAL_ADCEx_Calibration_Start+0xb8>
|
|
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
|
|
8002f80: 687b ldr r3, [r7, #4]
|
|
8002f82: 681b ldr r3, [r3, #0]
|
|
8002f84: 4618 mov r0, r3
|
|
8002f86: f7ff ff94 bl 8002eb2 <LL_ADC_IsCalibrationOnGoing>
|
|
8002f8a: 4603 mov r3, r0
|
|
8002f8c: 2b00 cmp r3, #0
|
|
8002f8e: d1e2 bne.n 8002f56 <HAL_ADCEx_Calibration_Start+0x56>
|
|
}
|
|
}
|
|
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002f90: 687b ldr r3, [r7, #4]
|
|
8002f92: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002f94: f023 0303 bic.w r3, r3, #3
|
|
8002f98: f043 0201 orr.w r2, r3, #1
|
|
8002f9c: 687b ldr r3, [r7, #4]
|
|
8002f9e: 65da str r2, [r3, #92] @ 0x5c
|
|
8002fa0: e005 b.n 8002fae <HAL_ADCEx_Calibration_Start+0xae>
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002fa2: 687b ldr r3, [r7, #4]
|
|
8002fa4: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8002fa6: f043 0210 orr.w r2, r3, #16
|
|
8002faa: 687b ldr r3, [r7, #4]
|
|
8002fac: 65da str r2, [r3, #92] @ 0x5c
|
|
/* Note: No need to update variable "tmp_hal_status" here: already set */
|
|
/* to state "HAL_ERROR" by function disabling the ADC. */
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8002fae: 687b ldr r3, [r7, #4]
|
|
8002fb0: 2200 movs r2, #0
|
|
8002fb2: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8002fb6: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002fb8: 4618 mov r0, r3
|
|
8002fba: 3710 adds r7, #16
|
|
8002fbc: 46bd mov sp, r7
|
|
8002fbe: bd80 pop {r7, pc}
|
|
8002fc0: 0004de01 .word 0x0004de01
|
|
|
|
08002fc4 <HAL_ADCEx_MultiModeConfigChannel>:
|
|
* @param hadc Master ADC handle
|
|
* @param pMultimode Structure of ADC multimode configuration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
|
|
{
|
|
8002fc4: b590 push {r4, r7, lr}
|
|
8002fc6: b0a1 sub sp, #132 @ 0x84
|
|
8002fc8: af00 add r7, sp, #0
|
|
8002fca: 6078 str r0, [r7, #4]
|
|
8002fcc: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8002fce: 2300 movs r3, #0
|
|
8002fd0: f887 307f strb.w r3, [r7, #127] @ 0x7f
|
|
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
|
|
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8002fd4: 687b ldr r3, [r7, #4]
|
|
8002fd6: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
|
|
8002fda: 2b01 cmp r3, #1
|
|
8002fdc: d101 bne.n 8002fe2 <HAL_ADCEx_MultiModeConfigChannel+0x1e>
|
|
8002fde: 2302 movs r3, #2
|
|
8002fe0: e08b b.n 80030fa <HAL_ADCEx_MultiModeConfigChannel+0x136>
|
|
8002fe2: 687b ldr r3, [r7, #4]
|
|
8002fe4: 2201 movs r2, #1
|
|
8002fe6: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Temporary handle minimum initialization */
|
|
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
|
|
8002fea: 2300 movs r3, #0
|
|
8002fec: 667b str r3, [r7, #100] @ 0x64
|
|
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
|
|
8002fee: 2300 movs r3, #0
|
|
8002ff0: 66bb str r3, [r7, #104] @ 0x68
|
|
|
|
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
|
|
8002ff2: 687b ldr r3, [r7, #4]
|
|
8002ff4: 681b ldr r3, [r3, #0]
|
|
8002ff6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
8002ffa: d102 bne.n 8003002 <HAL_ADCEx_MultiModeConfigChannel+0x3e>
|
|
8002ffc: 4b41 ldr r3, [pc, #260] @ (8003104 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
|
|
8002ffe: 60bb str r3, [r7, #8]
|
|
8003000: e001 b.n 8003006 <HAL_ADCEx_MultiModeConfigChannel+0x42>
|
|
8003002: 2300 movs r3, #0
|
|
8003004: 60bb str r3, [r7, #8]
|
|
|
|
if (tmp_hadc_slave.Instance == NULL)
|
|
8003006: 68bb ldr r3, [r7, #8]
|
|
8003008: 2b00 cmp r3, #0
|
|
800300a: d10b bne.n 8003024 <HAL_ADCEx_MultiModeConfigChannel+0x60>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
800300c: 687b ldr r3, [r7, #4]
|
|
800300e: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
8003010: f043 0220 orr.w r2, r3, #32
|
|
8003014: 687b ldr r3, [r7, #4]
|
|
8003016: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8003018: 687b ldr r3, [r7, #4]
|
|
800301a: 2200 movs r2, #0
|
|
800301c: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
return HAL_ERROR;
|
|
8003020: 2301 movs r3, #1
|
|
8003022: e06a b.n 80030fa <HAL_ADCEx_MultiModeConfigChannel+0x136>
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Multimode DMA configuration */
|
|
/* - Multimode DMA mode */
|
|
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
|
|
8003024: 68bb ldr r3, [r7, #8]
|
|
8003026: 4618 mov r0, r3
|
|
8003028: f7ff ff57 bl 8002eda <LL_ADC_REG_IsConversionOngoing>
|
|
800302c: 67b8 str r0, [r7, #120] @ 0x78
|
|
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
800302e: 687b ldr r3, [r7, #4]
|
|
8003030: 681b ldr r3, [r3, #0]
|
|
8003032: 4618 mov r0, r3
|
|
8003034: f7ff ff51 bl 8002eda <LL_ADC_REG_IsConversionOngoing>
|
|
8003038: 4603 mov r3, r0
|
|
800303a: 2b00 cmp r3, #0
|
|
800303c: d14c bne.n 80030d8 <HAL_ADCEx_MultiModeConfigChannel+0x114>
|
|
&& (tmp_hadc_slave_conversion_on_going == 0UL))
|
|
800303e: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8003040: 2b00 cmp r3, #0
|
|
8003042: d149 bne.n 80030d8 <HAL_ADCEx_MultiModeConfigChannel+0x114>
|
|
{
|
|
/* Pointer to the common control register */
|
|
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
|
8003044: 4b30 ldr r3, [pc, #192] @ (8003108 <HAL_ADCEx_MultiModeConfigChannel+0x144>)
|
|
8003046: 677b str r3, [r7, #116] @ 0x74
|
|
|
|
/* If multimode is selected, configure all multimode parameters. */
|
|
/* Otherwise, reset multimode parameters (can be used in case of */
|
|
/* transition from multimode to independent mode). */
|
|
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
|
|
8003048: 683b ldr r3, [r7, #0]
|
|
800304a: 681b ldr r3, [r3, #0]
|
|
800304c: 2b00 cmp r3, #0
|
|
800304e: d028 beq.n 80030a2 <HAL_ADCEx_MultiModeConfigChannel+0xde>
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
|
|
8003050: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8003052: 689b ldr r3, [r3, #8]
|
|
8003054: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8003058: 683b ldr r3, [r7, #0]
|
|
800305a: 6859 ldr r1, [r3, #4]
|
|
800305c: 687b ldr r3, [r7, #4]
|
|
800305e: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
8003062: 035b lsls r3, r3, #13
|
|
8003064: 430b orrs r3, r1
|
|
8003066: 431a orrs r2, r3
|
|
8003068: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800306a: 609a str r2, [r3, #8]
|
|
/* from 1 to 10 clock cycles for 10 bits, */
|
|
/* from 1 to 8 clock cycles for 8 bits */
|
|
/* from 1 to 6 clock cycles for 6 bits */
|
|
/* If a higher delay is selected, it will be clipped to maximum delay */
|
|
/* range */
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
800306c: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
|
|
8003070: f7ff fef3 bl 8002e5a <LL_ADC_IsEnabled>
|
|
8003074: 4604 mov r4, r0
|
|
8003076: 4823 ldr r0, [pc, #140] @ (8003104 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
|
|
8003078: f7ff feef bl 8002e5a <LL_ADC_IsEnabled>
|
|
800307c: 4603 mov r3, r0
|
|
800307e: 4323 orrs r3, r4
|
|
8003080: 2b00 cmp r3, #0
|
|
8003082: d133 bne.n 80030ec <HAL_ADCEx_MultiModeConfigChannel+0x128>
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR,
|
|
8003084: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8003086: 689b ldr r3, [r3, #8]
|
|
8003088: f423 6371 bic.w r3, r3, #3856 @ 0xf10
|
|
800308c: f023 030f bic.w r3, r3, #15
|
|
8003090: 683a ldr r2, [r7, #0]
|
|
8003092: 6811 ldr r1, [r2, #0]
|
|
8003094: 683a ldr r2, [r7, #0]
|
|
8003096: 6892 ldr r2, [r2, #8]
|
|
8003098: 430a orrs r2, r1
|
|
800309a: 431a orrs r2, r3
|
|
800309c: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
800309e: 609a str r2, [r3, #8]
|
|
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
|
|
80030a0: e024 b.n 80030ec <HAL_ADCEx_MultiModeConfigChannel+0x128>
|
|
);
|
|
}
|
|
}
|
|
else /* ADC_MODE_INDEPENDENT */
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
|
|
80030a2: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80030a4: 689b ldr r3, [r3, #8]
|
|
80030a6: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
80030aa: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80030ac: 609a str r2, [r3, #8]
|
|
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Multimode mode selection */
|
|
/* - Multimode delay */
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
80030ae: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
|
|
80030b2: f7ff fed2 bl 8002e5a <LL_ADC_IsEnabled>
|
|
80030b6: 4604 mov r4, r0
|
|
80030b8: 4812 ldr r0, [pc, #72] @ (8003104 <HAL_ADCEx_MultiModeConfigChannel+0x140>)
|
|
80030ba: f7ff fece bl 8002e5a <LL_ADC_IsEnabled>
|
|
80030be: 4603 mov r3, r0
|
|
80030c0: 4323 orrs r3, r4
|
|
80030c2: 2b00 cmp r3, #0
|
|
80030c4: d112 bne.n 80030ec <HAL_ADCEx_MultiModeConfigChannel+0x128>
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
|
|
80030c6: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80030c8: 689b ldr r3, [r3, #8]
|
|
80030ca: f423 6371 bic.w r3, r3, #3856 @ 0xf10
|
|
80030ce: f023 030f bic.w r3, r3, #15
|
|
80030d2: 6f7a ldr r2, [r7, #116] @ 0x74
|
|
80030d4: 6093 str r3, [r2, #8]
|
|
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
|
|
80030d6: e009 b.n 80030ec <HAL_ADCEx_MultiModeConfigChannel+0x128>
|
|
/* If one of the ADC sharing the same common group is enabled, no update */
|
|
/* could be done on neither of the multimode structure parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
80030d8: 687b ldr r3, [r7, #4]
|
|
80030da: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80030dc: f043 0220 orr.w r2, r3, #32
|
|
80030e0: 687b ldr r3, [r7, #4]
|
|
80030e2: 65da str r2, [r3, #92] @ 0x5c
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80030e4: 2301 movs r3, #1
|
|
80030e6: f887 307f strb.w r3, [r7, #127] @ 0x7f
|
|
80030ea: e000 b.n 80030ee <HAL_ADCEx_MultiModeConfigChannel+0x12a>
|
|
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
|
|
80030ec: bf00 nop
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80030ee: 687b ldr r3, [r7, #4]
|
|
80030f0: 2200 movs r2, #0
|
|
80030f2: f883 2058 strb.w r2, [r3, #88] @ 0x58
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
80030f6: f897 307f ldrb.w r3, [r7, #127] @ 0x7f
|
|
}
|
|
80030fa: 4618 mov r0, r3
|
|
80030fc: 3784 adds r7, #132 @ 0x84
|
|
80030fe: 46bd mov sp, r7
|
|
8003100: bd90 pop {r4, r7, pc}
|
|
8003102: bf00 nop
|
|
8003104: 50000100 .word 0x50000100
|
|
8003108: 50000300 .word 0x50000300
|
|
|
|
0800310c <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800310c: b480 push {r7}
|
|
800310e: b085 sub sp, #20
|
|
8003110: af00 add r7, sp, #0
|
|
8003112: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8003114: 687b ldr r3, [r7, #4]
|
|
8003116: f003 0307 and.w r3, r3, #7
|
|
800311a: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
800311c: 4b0c ldr r3, [pc, #48] @ (8003150 <__NVIC_SetPriorityGrouping+0x44>)
|
|
800311e: 68db ldr r3, [r3, #12]
|
|
8003120: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8003122: 68ba ldr r2, [r7, #8]
|
|
8003124: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8003128: 4013 ands r3, r2
|
|
800312a: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
800312c: 68fb ldr r3, [r7, #12]
|
|
800312e: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8003130: 68bb ldr r3, [r7, #8]
|
|
8003132: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8003134: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8003138: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
800313c: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
800313e: 4a04 ldr r2, [pc, #16] @ (8003150 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8003140: 68bb ldr r3, [r7, #8]
|
|
8003142: 60d3 str r3, [r2, #12]
|
|
}
|
|
8003144: bf00 nop
|
|
8003146: 3714 adds r7, #20
|
|
8003148: 46bd mov sp, r7
|
|
800314a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800314e: 4770 bx lr
|
|
8003150: e000ed00 .word 0xe000ed00
|
|
|
|
08003154 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8003154: b480 push {r7}
|
|
8003156: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8003158: 4b04 ldr r3, [pc, #16] @ (800316c <__NVIC_GetPriorityGrouping+0x18>)
|
|
800315a: 68db ldr r3, [r3, #12]
|
|
800315c: 0a1b lsrs r3, r3, #8
|
|
800315e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8003162: 4618 mov r0, r3
|
|
8003164: 46bd mov sp, r7
|
|
8003166: f85d 7b04 ldr.w r7, [sp], #4
|
|
800316a: 4770 bx lr
|
|
800316c: e000ed00 .word 0xe000ed00
|
|
|
|
08003170 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8003170: b480 push {r7}
|
|
8003172: b083 sub sp, #12
|
|
8003174: af00 add r7, sp, #0
|
|
8003176: 4603 mov r3, r0
|
|
8003178: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800317a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800317e: 2b00 cmp r3, #0
|
|
8003180: db0b blt.n 800319a <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8003182: 79fb ldrb r3, [r7, #7]
|
|
8003184: f003 021f and.w r2, r3, #31
|
|
8003188: 4907 ldr r1, [pc, #28] @ (80031a8 <__NVIC_EnableIRQ+0x38>)
|
|
800318a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800318e: 095b lsrs r3, r3, #5
|
|
8003190: 2001 movs r0, #1
|
|
8003192: fa00 f202 lsl.w r2, r0, r2
|
|
8003196: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
800319a: bf00 nop
|
|
800319c: 370c adds r7, #12
|
|
800319e: 46bd mov sp, r7
|
|
80031a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80031a4: 4770 bx lr
|
|
80031a6: bf00 nop
|
|
80031a8: e000e100 .word 0xe000e100
|
|
|
|
080031ac <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
80031ac: b480 push {r7}
|
|
80031ae: b083 sub sp, #12
|
|
80031b0: af00 add r7, sp, #0
|
|
80031b2: 4603 mov r3, r0
|
|
80031b4: 6039 str r1, [r7, #0]
|
|
80031b6: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80031b8: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80031bc: 2b00 cmp r3, #0
|
|
80031be: db0a blt.n 80031d6 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80031c0: 683b ldr r3, [r7, #0]
|
|
80031c2: b2da uxtb r2, r3
|
|
80031c4: 490c ldr r1, [pc, #48] @ (80031f8 <__NVIC_SetPriority+0x4c>)
|
|
80031c6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80031ca: 0112 lsls r2, r2, #4
|
|
80031cc: b2d2 uxtb r2, r2
|
|
80031ce: 440b add r3, r1
|
|
80031d0: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
80031d4: e00a b.n 80031ec <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80031d6: 683b ldr r3, [r7, #0]
|
|
80031d8: b2da uxtb r2, r3
|
|
80031da: 4908 ldr r1, [pc, #32] @ (80031fc <__NVIC_SetPriority+0x50>)
|
|
80031dc: 79fb ldrb r3, [r7, #7]
|
|
80031de: f003 030f and.w r3, r3, #15
|
|
80031e2: 3b04 subs r3, #4
|
|
80031e4: 0112 lsls r2, r2, #4
|
|
80031e6: b2d2 uxtb r2, r2
|
|
80031e8: 440b add r3, r1
|
|
80031ea: 761a strb r2, [r3, #24]
|
|
}
|
|
80031ec: bf00 nop
|
|
80031ee: 370c adds r7, #12
|
|
80031f0: 46bd mov sp, r7
|
|
80031f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80031f6: 4770 bx lr
|
|
80031f8: e000e100 .word 0xe000e100
|
|
80031fc: e000ed00 .word 0xe000ed00
|
|
|
|
08003200 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8003200: b480 push {r7}
|
|
8003202: b089 sub sp, #36 @ 0x24
|
|
8003204: af00 add r7, sp, #0
|
|
8003206: 60f8 str r0, [r7, #12]
|
|
8003208: 60b9 str r1, [r7, #8]
|
|
800320a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800320c: 68fb ldr r3, [r7, #12]
|
|
800320e: f003 0307 and.w r3, r3, #7
|
|
8003212: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8003214: 69fb ldr r3, [r7, #28]
|
|
8003216: f1c3 0307 rsb r3, r3, #7
|
|
800321a: 2b04 cmp r3, #4
|
|
800321c: bf28 it cs
|
|
800321e: 2304 movcs r3, #4
|
|
8003220: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8003222: 69fb ldr r3, [r7, #28]
|
|
8003224: 3304 adds r3, #4
|
|
8003226: 2b06 cmp r3, #6
|
|
8003228: d902 bls.n 8003230 <NVIC_EncodePriority+0x30>
|
|
800322a: 69fb ldr r3, [r7, #28]
|
|
800322c: 3b03 subs r3, #3
|
|
800322e: e000 b.n 8003232 <NVIC_EncodePriority+0x32>
|
|
8003230: 2300 movs r3, #0
|
|
8003232: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8003234: f04f 32ff mov.w r2, #4294967295
|
|
8003238: 69bb ldr r3, [r7, #24]
|
|
800323a: fa02 f303 lsl.w r3, r2, r3
|
|
800323e: 43da mvns r2, r3
|
|
8003240: 68bb ldr r3, [r7, #8]
|
|
8003242: 401a ands r2, r3
|
|
8003244: 697b ldr r3, [r7, #20]
|
|
8003246: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8003248: f04f 31ff mov.w r1, #4294967295
|
|
800324c: 697b ldr r3, [r7, #20]
|
|
800324e: fa01 f303 lsl.w r3, r1, r3
|
|
8003252: 43d9 mvns r1, r3
|
|
8003254: 687b ldr r3, [r7, #4]
|
|
8003256: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8003258: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
800325a: 4618 mov r0, r3
|
|
800325c: 3724 adds r7, #36 @ 0x24
|
|
800325e: 46bd mov sp, r7
|
|
8003260: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003264: 4770 bx lr
|
|
...
|
|
|
|
08003268 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8003268: b580 push {r7, lr}
|
|
800326a: b082 sub sp, #8
|
|
800326c: af00 add r7, sp, #0
|
|
800326e: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8003270: 687b ldr r3, [r7, #4]
|
|
8003272: 3b01 subs r3, #1
|
|
8003274: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8003278: d301 bcc.n 800327e <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
800327a: 2301 movs r3, #1
|
|
800327c: e00f b.n 800329e <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
800327e: 4a0a ldr r2, [pc, #40] @ (80032a8 <SysTick_Config+0x40>)
|
|
8003280: 687b ldr r3, [r7, #4]
|
|
8003282: 3b01 subs r3, #1
|
|
8003284: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8003286: 210f movs r1, #15
|
|
8003288: f04f 30ff mov.w r0, #4294967295
|
|
800328c: f7ff ff8e bl 80031ac <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8003290: 4b05 ldr r3, [pc, #20] @ (80032a8 <SysTick_Config+0x40>)
|
|
8003292: 2200 movs r2, #0
|
|
8003294: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8003296: 4b04 ldr r3, [pc, #16] @ (80032a8 <SysTick_Config+0x40>)
|
|
8003298: 2207 movs r2, #7
|
|
800329a: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
800329c: 2300 movs r3, #0
|
|
}
|
|
800329e: 4618 mov r0, r3
|
|
80032a0: 3708 adds r7, #8
|
|
80032a2: 46bd mov sp, r7
|
|
80032a4: bd80 pop {r7, pc}
|
|
80032a6: bf00 nop
|
|
80032a8: e000e010 .word 0xe000e010
|
|
|
|
080032ac <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80032ac: b580 push {r7, lr}
|
|
80032ae: b082 sub sp, #8
|
|
80032b0: af00 add r7, sp, #0
|
|
80032b2: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
80032b4: 6878 ldr r0, [r7, #4]
|
|
80032b6: f7ff ff29 bl 800310c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
80032ba: bf00 nop
|
|
80032bc: 3708 adds r7, #8
|
|
80032be: 46bd mov sp, r7
|
|
80032c0: bd80 pop {r7, pc}
|
|
|
|
080032c2 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80032c2: b580 push {r7, lr}
|
|
80032c4: b086 sub sp, #24
|
|
80032c6: af00 add r7, sp, #0
|
|
80032c8: 4603 mov r3, r0
|
|
80032ca: 60b9 str r1, [r7, #8]
|
|
80032cc: 607a str r2, [r7, #4]
|
|
80032ce: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
80032d0: f7ff ff40 bl 8003154 <__NVIC_GetPriorityGrouping>
|
|
80032d4: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
80032d6: 687a ldr r2, [r7, #4]
|
|
80032d8: 68b9 ldr r1, [r7, #8]
|
|
80032da: 6978 ldr r0, [r7, #20]
|
|
80032dc: f7ff ff90 bl 8003200 <NVIC_EncodePriority>
|
|
80032e0: 4602 mov r2, r0
|
|
80032e2: f997 300f ldrsb.w r3, [r7, #15]
|
|
80032e6: 4611 mov r1, r2
|
|
80032e8: 4618 mov r0, r3
|
|
80032ea: f7ff ff5f bl 80031ac <__NVIC_SetPriority>
|
|
}
|
|
80032ee: bf00 nop
|
|
80032f0: 3718 adds r7, #24
|
|
80032f2: 46bd mov sp, r7
|
|
80032f4: bd80 pop {r7, pc}
|
|
|
|
080032f6 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80032f6: b580 push {r7, lr}
|
|
80032f8: b082 sub sp, #8
|
|
80032fa: af00 add r7, sp, #0
|
|
80032fc: 4603 mov r3, r0
|
|
80032fe: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8003300: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8003304: 4618 mov r0, r3
|
|
8003306: f7ff ff33 bl 8003170 <__NVIC_EnableIRQ>
|
|
}
|
|
800330a: bf00 nop
|
|
800330c: 3708 adds r7, #8
|
|
800330e: 46bd mov sp, r7
|
|
8003310: bd80 pop {r7, pc}
|
|
|
|
08003312 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
8003312: b580 push {r7, lr}
|
|
8003314: b082 sub sp, #8
|
|
8003316: af00 add r7, sp, #0
|
|
8003318: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
800331a: 6878 ldr r0, [r7, #4]
|
|
800331c: f7ff ffa4 bl 8003268 <SysTick_Config>
|
|
8003320: 4603 mov r3, r0
|
|
}
|
|
8003322: 4618 mov r0, r3
|
|
8003324: 3708 adds r7, #8
|
|
8003326: 46bd mov sp, r7
|
|
8003328: bd80 pop {r7, pc}
|
|
|
|
0800332a <HAL_DMA_Abort>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800332a: b480 push {r7}
|
|
800332c: b085 sub sp, #20
|
|
800332e: af00 add r7, sp, #0
|
|
8003330: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003332: 2300 movs r3, #0
|
|
8003334: 73fb strb r3, [r7, #15]
|
|
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
8003336: 687b ldr r3, [r7, #4]
|
|
8003338: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
800333c: b2db uxtb r3, r3
|
|
800333e: 2b02 cmp r3, #2
|
|
8003340: d005 beq.n 800334e <HAL_DMA_Abort+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8003342: 687b ldr r3, [r7, #4]
|
|
8003344: 2204 movs r2, #4
|
|
8003346: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
8003348: 2301 movs r3, #1
|
|
800334a: 73fb strb r3, [r7, #15]
|
|
800334c: e037 b.n 80033be <HAL_DMA_Abort+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
800334e: 687b ldr r3, [r7, #4]
|
|
8003350: 681b ldr r3, [r3, #0]
|
|
8003352: 681a ldr r2, [r3, #0]
|
|
8003354: 687b ldr r3, [r7, #4]
|
|
8003356: 681b ldr r3, [r3, #0]
|
|
8003358: f022 020e bic.w r2, r2, #14
|
|
800335c: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
800335e: 687b ldr r3, [r7, #4]
|
|
8003360: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003362: 681a ldr r2, [r3, #0]
|
|
8003364: 687b ldr r3, [r7, #4]
|
|
8003366: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003368: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
800336c: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
800336e: 687b ldr r3, [r7, #4]
|
|
8003370: 681b ldr r3, [r3, #0]
|
|
8003372: 681a ldr r2, [r3, #0]
|
|
8003374: 687b ldr r3, [r7, #4]
|
|
8003376: 681b ldr r3, [r3, #0]
|
|
8003378: f022 0201 bic.w r2, r2, #1
|
|
800337c: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
|
|
800337e: 687b ldr r3, [r7, #4]
|
|
8003380: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003382: f003 021f and.w r2, r3, #31
|
|
8003386: 687b ldr r3, [r7, #4]
|
|
8003388: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800338a: 2101 movs r1, #1
|
|
800338c: fa01 f202 lsl.w r2, r1, r2
|
|
8003390: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8003392: 687b ldr r3, [r7, #4]
|
|
8003394: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003396: 687a ldr r2, [r7, #4]
|
|
8003398: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
800339a: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
800339c: 687b ldr r3, [r7, #4]
|
|
800339e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80033a0: 2b00 cmp r3, #0
|
|
80033a2: d00c beq.n 80033be <HAL_DMA_Abort+0x94>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
80033a4: 687b ldr r3, [r7, #4]
|
|
80033a6: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80033a8: 681a ldr r2, [r3, #0]
|
|
80033aa: 687b ldr r3, [r7, #4]
|
|
80033ac: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
80033ae: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
80033b2: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
80033b4: 687b ldr r3, [r7, #4]
|
|
80033b6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80033b8: 687a ldr r2, [r7, #4]
|
|
80033ba: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
80033bc: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80033be: 687b ldr r3, [r7, #4]
|
|
80033c0: 2201 movs r2, #1
|
|
80033c2: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80033c6: 687b ldr r3, [r7, #4]
|
|
80033c8: 2200 movs r2, #0
|
|
80033ca: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return status;
|
|
80033ce: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80033d0: 4618 mov r0, r3
|
|
80033d2: 3714 adds r7, #20
|
|
80033d4: 46bd mov sp, r7
|
|
80033d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80033da: 4770 bx lr
|
|
|
|
080033dc <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80033dc: b580 push {r7, lr}
|
|
80033de: b084 sub sp, #16
|
|
80033e0: af00 add r7, sp, #0
|
|
80033e2: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80033e4: 2300 movs r3, #0
|
|
80033e6: 73fb strb r3, [r7, #15]
|
|
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
80033e8: 687b ldr r3, [r7, #4]
|
|
80033ea: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
80033ee: b2db uxtb r3, r3
|
|
80033f0: 2b02 cmp r3, #2
|
|
80033f2: d00d beq.n 8003410 <HAL_DMA_Abort_IT+0x34>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
80033f4: 687b ldr r3, [r7, #4]
|
|
80033f6: 2204 movs r2, #4
|
|
80033f8: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80033fa: 687b ldr r3, [r7, #4]
|
|
80033fc: 2201 movs r2, #1
|
|
80033fe: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8003402: 687b ldr r3, [r7, #4]
|
|
8003404: 2200 movs r2, #0
|
|
8003406: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
status = HAL_ERROR;
|
|
800340a: 2301 movs r3, #1
|
|
800340c: 73fb strb r3, [r7, #15]
|
|
800340e: e047 b.n 80034a0 <HAL_DMA_Abort_IT+0xc4>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8003410: 687b ldr r3, [r7, #4]
|
|
8003412: 681b ldr r3, [r3, #0]
|
|
8003414: 681a ldr r2, [r3, #0]
|
|
8003416: 687b ldr r3, [r7, #4]
|
|
8003418: 681b ldr r3, [r3, #0]
|
|
800341a: f022 020e bic.w r2, r2, #14
|
|
800341e: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8003420: 687b ldr r3, [r7, #4]
|
|
8003422: 681b ldr r3, [r3, #0]
|
|
8003424: 681a ldr r2, [r3, #0]
|
|
8003426: 687b ldr r3, [r7, #4]
|
|
8003428: 681b ldr r3, [r3, #0]
|
|
800342a: f022 0201 bic.w r2, r2, #1
|
|
800342e: 601a str r2, [r3, #0]
|
|
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8003430: 687b ldr r3, [r7, #4]
|
|
8003432: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8003434: 681a ldr r2, [r3, #0]
|
|
8003436: 687b ldr r3, [r7, #4]
|
|
8003438: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800343a: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
800343e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
|
|
8003440: 687b ldr r3, [r7, #4]
|
|
8003442: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003444: f003 021f and.w r2, r3, #31
|
|
8003448: 687b ldr r3, [r7, #4]
|
|
800344a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800344c: 2101 movs r1, #1
|
|
800344e: fa01 f202 lsl.w r2, r1, r2
|
|
8003452: 605a str r2, [r3, #4]
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8003454: 687b ldr r3, [r7, #4]
|
|
8003456: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8003458: 687a ldr r2, [r7, #4]
|
|
800345a: 6d12 ldr r2, [r2, #80] @ 0x50
|
|
800345c: 605a str r2, [r3, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
800345e: 687b ldr r3, [r7, #4]
|
|
8003460: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003462: 2b00 cmp r3, #0
|
|
8003464: d00c beq.n 8003480 <HAL_DMA_Abort_IT+0xa4>
|
|
{
|
|
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
|
|
/* disable the request gen overrun IT*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8003466: 687b ldr r3, [r7, #4]
|
|
8003468: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800346a: 681a ldr r2, [r3, #0]
|
|
800346c: 687b ldr r3, [r7, #4]
|
|
800346e: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8003470: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8003474: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8003476: 687b ldr r3, [r7, #4]
|
|
8003478: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800347a: 687a ldr r2, [r7, #4]
|
|
800347c: 6dd2 ldr r2, [r2, #92] @ 0x5c
|
|
800347e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8003480: 687b ldr r3, [r7, #4]
|
|
8003482: 2201 movs r2, #1
|
|
8003484: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8003488: 687b ldr r3, [r7, #4]
|
|
800348a: 2200 movs r2, #0
|
|
800348c: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if (hdma->XferAbortCallback != NULL)
|
|
8003490: 687b ldr r3, [r7, #4]
|
|
8003492: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003494: 2b00 cmp r3, #0
|
|
8003496: d003 beq.n 80034a0 <HAL_DMA_Abort_IT+0xc4>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
8003498: 687b ldr r3, [r7, #4]
|
|
800349a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800349c: 6878 ldr r0, [r7, #4]
|
|
800349e: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
80034a0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80034a2: 4618 mov r0, r3
|
|
80034a4: 3710 adds r7, #16
|
|
80034a6: 46bd mov sp, r7
|
|
80034a8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080034ac <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80034ac: b480 push {r7}
|
|
80034ae: b087 sub sp, #28
|
|
80034b0: af00 add r7, sp, #0
|
|
80034b2: 6078 str r0, [r7, #4]
|
|
80034b4: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00U;
|
|
80034b6: 2300 movs r3, #0
|
|
80034b8: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0U)
|
|
80034ba: e15a b.n 8003772 <HAL_GPIO_Init+0x2c6>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1UL << position);
|
|
80034bc: 683b ldr r3, [r7, #0]
|
|
80034be: 681a ldr r2, [r3, #0]
|
|
80034c0: 2101 movs r1, #1
|
|
80034c2: 697b ldr r3, [r7, #20]
|
|
80034c4: fa01 f303 lsl.w r3, r1, r3
|
|
80034c8: 4013 ands r3, r2
|
|
80034ca: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80034cc: 68fb ldr r3, [r7, #12]
|
|
80034ce: 2b00 cmp r3, #0
|
|
80034d0: f000 814c beq.w 800376c <HAL_GPIO_Init+0x2c0>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
|
80034d4: 683b ldr r3, [r7, #0]
|
|
80034d6: 685b ldr r3, [r3, #4]
|
|
80034d8: f003 0303 and.w r3, r3, #3
|
|
80034dc: 2b01 cmp r3, #1
|
|
80034de: d005 beq.n 80034ec <HAL_GPIO_Init+0x40>
|
|
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
80034e0: 683b ldr r3, [r7, #0]
|
|
80034e2: 685b ldr r3, [r3, #4]
|
|
80034e4: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
|
|
80034e8: 2b02 cmp r3, #2
|
|
80034ea: d130 bne.n 800354e <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
80034ec: 687b ldr r3, [r7, #4]
|
|
80034ee: 689b ldr r3, [r3, #8]
|
|
80034f0: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
|
|
80034f2: 697b ldr r3, [r7, #20]
|
|
80034f4: 005b lsls r3, r3, #1
|
|
80034f6: 2203 movs r2, #3
|
|
80034f8: fa02 f303 lsl.w r3, r2, r3
|
|
80034fc: 43db mvns r3, r3
|
|
80034fe: 693a ldr r2, [r7, #16]
|
|
8003500: 4013 ands r3, r2
|
|
8003502: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8003504: 683b ldr r3, [r7, #0]
|
|
8003506: 68da ldr r2, [r3, #12]
|
|
8003508: 697b ldr r3, [r7, #20]
|
|
800350a: 005b lsls r3, r3, #1
|
|
800350c: fa02 f303 lsl.w r3, r2, r3
|
|
8003510: 693a ldr r2, [r7, #16]
|
|
8003512: 4313 orrs r3, r2
|
|
8003514: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8003516: 687b ldr r3, [r7, #4]
|
|
8003518: 693a ldr r2, [r7, #16]
|
|
800351a: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
800351c: 687b ldr r3, [r7, #4]
|
|
800351e: 685b ldr r3, [r3, #4]
|
|
8003520: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8003522: 2201 movs r2, #1
|
|
8003524: 697b ldr r3, [r7, #20]
|
|
8003526: fa02 f303 lsl.w r3, r2, r3
|
|
800352a: 43db mvns r3, r3
|
|
800352c: 693a ldr r2, [r7, #16]
|
|
800352e: 4013 ands r3, r2
|
|
8003530: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8003532: 683b ldr r3, [r7, #0]
|
|
8003534: 685b ldr r3, [r3, #4]
|
|
8003536: 091b lsrs r3, r3, #4
|
|
8003538: f003 0201 and.w r2, r3, #1
|
|
800353c: 697b ldr r3, [r7, #20]
|
|
800353e: fa02 f303 lsl.w r3, r2, r3
|
|
8003542: 693a ldr r2, [r7, #16]
|
|
8003544: 4313 orrs r3, r2
|
|
8003546: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8003548: 687b ldr r3, [r7, #4]
|
|
800354a: 693a ldr r2, [r7, #16]
|
|
800354c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
800354e: 683b ldr r3, [r7, #0]
|
|
8003550: 685b ldr r3, [r3, #4]
|
|
8003552: f003 0303 and.w r3, r3, #3
|
|
8003556: 2b03 cmp r3, #3
|
|
8003558: d017 beq.n 800358a <HAL_GPIO_Init+0xde>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
800355a: 687b ldr r3, [r7, #4]
|
|
800355c: 68db ldr r3, [r3, #12]
|
|
800355e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
8003560: 697b ldr r3, [r7, #20]
|
|
8003562: 005b lsls r3, r3, #1
|
|
8003564: 2203 movs r2, #3
|
|
8003566: fa02 f303 lsl.w r3, r2, r3
|
|
800356a: 43db mvns r3, r3
|
|
800356c: 693a ldr r2, [r7, #16]
|
|
800356e: 4013 ands r3, r2
|
|
8003570: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8003572: 683b ldr r3, [r7, #0]
|
|
8003574: 689a ldr r2, [r3, #8]
|
|
8003576: 697b ldr r3, [r7, #20]
|
|
8003578: 005b lsls r3, r3, #1
|
|
800357a: fa02 f303 lsl.w r3, r2, r3
|
|
800357e: 693a ldr r2, [r7, #16]
|
|
8003580: 4313 orrs r3, r2
|
|
8003582: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8003584: 687b ldr r3, [r7, #4]
|
|
8003586: 693a ldr r2, [r7, #16]
|
|
8003588: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
800358a: 683b ldr r3, [r7, #0]
|
|
800358c: 685b ldr r3, [r3, #4]
|
|
800358e: f003 0303 and.w r3, r3, #3
|
|
8003592: 2b02 cmp r3, #2
|
|
8003594: d123 bne.n 80035de <HAL_GPIO_Init+0x132>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
8003596: 697b ldr r3, [r7, #20]
|
|
8003598: 08da lsrs r2, r3, #3
|
|
800359a: 687b ldr r3, [r7, #4]
|
|
800359c: 3208 adds r2, #8
|
|
800359e: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
80035a2: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFU << ((position & 0x07U) * 4U));
|
|
80035a4: 697b ldr r3, [r7, #20]
|
|
80035a6: f003 0307 and.w r3, r3, #7
|
|
80035aa: 009b lsls r3, r3, #2
|
|
80035ac: 220f movs r2, #15
|
|
80035ae: fa02 f303 lsl.w r3, r2, r3
|
|
80035b2: 43db mvns r3, r3
|
|
80035b4: 693a ldr r2, [r7, #16]
|
|
80035b6: 4013 ands r3, r2
|
|
80035b8: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
|
|
80035ba: 683b ldr r3, [r7, #0]
|
|
80035bc: 691a ldr r2, [r3, #16]
|
|
80035be: 697b ldr r3, [r7, #20]
|
|
80035c0: f003 0307 and.w r3, r3, #7
|
|
80035c4: 009b lsls r3, r3, #2
|
|
80035c6: fa02 f303 lsl.w r3, r2, r3
|
|
80035ca: 693a ldr r2, [r7, #16]
|
|
80035cc: 4313 orrs r3, r2
|
|
80035ce: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
80035d0: 697b ldr r3, [r7, #20]
|
|
80035d2: 08da lsrs r2, r3, #3
|
|
80035d4: 687b ldr r3, [r7, #4]
|
|
80035d6: 3208 adds r2, #8
|
|
80035d8: 6939 ldr r1, [r7, #16]
|
|
80035da: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
80035de: 687b ldr r3, [r7, #4]
|
|
80035e0: 681b ldr r3, [r3, #0]
|
|
80035e2: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
|
|
80035e4: 697b ldr r3, [r7, #20]
|
|
80035e6: 005b lsls r3, r3, #1
|
|
80035e8: 2203 movs r2, #3
|
|
80035ea: fa02 f303 lsl.w r3, r2, r3
|
|
80035ee: 43db mvns r3, r3
|
|
80035f0: 693a ldr r2, [r7, #16]
|
|
80035f2: 4013 ands r3, r2
|
|
80035f4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
80035f6: 683b ldr r3, [r7, #0]
|
|
80035f8: 685b ldr r3, [r3, #4]
|
|
80035fa: f003 0203 and.w r2, r3, #3
|
|
80035fe: 697b ldr r3, [r7, #20]
|
|
8003600: 005b lsls r3, r3, #1
|
|
8003602: fa02 f303 lsl.w r3, r2, r3
|
|
8003606: 693a ldr r2, [r7, #16]
|
|
8003608: 4313 orrs r3, r2
|
|
800360a: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
800360c: 687b ldr r3, [r7, #4]
|
|
800360e: 693a ldr r2, [r7, #16]
|
|
8003610: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
8003612: 683b ldr r3, [r7, #0]
|
|
8003614: 685b ldr r3, [r3, #4]
|
|
8003616: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
800361a: 2b00 cmp r3, #0
|
|
800361c: f000 80a6 beq.w 800376c <HAL_GPIO_Init+0x2c0>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8003620: 4b5b ldr r3, [pc, #364] @ (8003790 <HAL_GPIO_Init+0x2e4>)
|
|
8003622: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003624: 4a5a ldr r2, [pc, #360] @ (8003790 <HAL_GPIO_Init+0x2e4>)
|
|
8003626: f043 0301 orr.w r3, r3, #1
|
|
800362a: 6613 str r3, [r2, #96] @ 0x60
|
|
800362c: 4b58 ldr r3, [pc, #352] @ (8003790 <HAL_GPIO_Init+0x2e4>)
|
|
800362e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8003630: f003 0301 and.w r3, r3, #1
|
|
8003634: 60bb str r3, [r7, #8]
|
|
8003636: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8003638: 4a56 ldr r2, [pc, #344] @ (8003794 <HAL_GPIO_Init+0x2e8>)
|
|
800363a: 697b ldr r3, [r7, #20]
|
|
800363c: 089b lsrs r3, r3, #2
|
|
800363e: 3302 adds r3, #2
|
|
8003640: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8003644: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
|
|
8003646: 697b ldr r3, [r7, #20]
|
|
8003648: f003 0303 and.w r3, r3, #3
|
|
800364c: 009b lsls r3, r3, #2
|
|
800364e: 220f movs r2, #15
|
|
8003650: fa02 f303 lsl.w r3, r2, r3
|
|
8003654: 43db mvns r3, r3
|
|
8003656: 693a ldr r2, [r7, #16]
|
|
8003658: 4013 ands r3, r2
|
|
800365a: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
|
|
800365c: 687b ldr r3, [r7, #4]
|
|
800365e: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
8003662: d01f beq.n 80036a4 <HAL_GPIO_Init+0x1f8>
|
|
8003664: 687b ldr r3, [r7, #4]
|
|
8003666: 4a4c ldr r2, [pc, #304] @ (8003798 <HAL_GPIO_Init+0x2ec>)
|
|
8003668: 4293 cmp r3, r2
|
|
800366a: d019 beq.n 80036a0 <HAL_GPIO_Init+0x1f4>
|
|
800366c: 687b ldr r3, [r7, #4]
|
|
800366e: 4a4b ldr r2, [pc, #300] @ (800379c <HAL_GPIO_Init+0x2f0>)
|
|
8003670: 4293 cmp r3, r2
|
|
8003672: d013 beq.n 800369c <HAL_GPIO_Init+0x1f0>
|
|
8003674: 687b ldr r3, [r7, #4]
|
|
8003676: 4a4a ldr r2, [pc, #296] @ (80037a0 <HAL_GPIO_Init+0x2f4>)
|
|
8003678: 4293 cmp r3, r2
|
|
800367a: d00d beq.n 8003698 <HAL_GPIO_Init+0x1ec>
|
|
800367c: 687b ldr r3, [r7, #4]
|
|
800367e: 4a49 ldr r2, [pc, #292] @ (80037a4 <HAL_GPIO_Init+0x2f8>)
|
|
8003680: 4293 cmp r3, r2
|
|
8003682: d007 beq.n 8003694 <HAL_GPIO_Init+0x1e8>
|
|
8003684: 687b ldr r3, [r7, #4]
|
|
8003686: 4a48 ldr r2, [pc, #288] @ (80037a8 <HAL_GPIO_Init+0x2fc>)
|
|
8003688: 4293 cmp r3, r2
|
|
800368a: d101 bne.n 8003690 <HAL_GPIO_Init+0x1e4>
|
|
800368c: 2305 movs r3, #5
|
|
800368e: e00a b.n 80036a6 <HAL_GPIO_Init+0x1fa>
|
|
8003690: 2306 movs r3, #6
|
|
8003692: e008 b.n 80036a6 <HAL_GPIO_Init+0x1fa>
|
|
8003694: 2304 movs r3, #4
|
|
8003696: e006 b.n 80036a6 <HAL_GPIO_Init+0x1fa>
|
|
8003698: 2303 movs r3, #3
|
|
800369a: e004 b.n 80036a6 <HAL_GPIO_Init+0x1fa>
|
|
800369c: 2302 movs r3, #2
|
|
800369e: e002 b.n 80036a6 <HAL_GPIO_Init+0x1fa>
|
|
80036a0: 2301 movs r3, #1
|
|
80036a2: e000 b.n 80036a6 <HAL_GPIO_Init+0x1fa>
|
|
80036a4: 2300 movs r3, #0
|
|
80036a6: 697a ldr r2, [r7, #20]
|
|
80036a8: f002 0203 and.w r2, r2, #3
|
|
80036ac: 0092 lsls r2, r2, #2
|
|
80036ae: 4093 lsls r3, r2
|
|
80036b0: 693a ldr r2, [r7, #16]
|
|
80036b2: 4313 orrs r3, r2
|
|
80036b4: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
80036b6: 4937 ldr r1, [pc, #220] @ (8003794 <HAL_GPIO_Init+0x2e8>)
|
|
80036b8: 697b ldr r3, [r7, #20]
|
|
80036ba: 089b lsrs r3, r3, #2
|
|
80036bc: 3302 adds r3, #2
|
|
80036be: 693a ldr r2, [r7, #16]
|
|
80036c0: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
80036c4: 4b39 ldr r3, [pc, #228] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
80036c6: 689b ldr r3, [r3, #8]
|
|
80036c8: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80036ca: 68fb ldr r3, [r7, #12]
|
|
80036cc: 43db mvns r3, r3
|
|
80036ce: 693a ldr r2, [r7, #16]
|
|
80036d0: 4013 ands r3, r2
|
|
80036d2: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
80036d4: 683b ldr r3, [r7, #0]
|
|
80036d6: 685b ldr r3, [r3, #4]
|
|
80036d8: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80036dc: 2b00 cmp r3, #0
|
|
80036de: d003 beq.n 80036e8 <HAL_GPIO_Init+0x23c>
|
|
{
|
|
temp |= iocurrent;
|
|
80036e0: 693a ldr r2, [r7, #16]
|
|
80036e2: 68fb ldr r3, [r7, #12]
|
|
80036e4: 4313 orrs r3, r2
|
|
80036e6: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
80036e8: 4a30 ldr r2, [pc, #192] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
80036ea: 693b ldr r3, [r7, #16]
|
|
80036ec: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
80036ee: 4b2f ldr r3, [pc, #188] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
80036f0: 68db ldr r3, [r3, #12]
|
|
80036f2: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80036f4: 68fb ldr r3, [r7, #12]
|
|
80036f6: 43db mvns r3, r3
|
|
80036f8: 693a ldr r2, [r7, #16]
|
|
80036fa: 4013 ands r3, r2
|
|
80036fc: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
80036fe: 683b ldr r3, [r7, #0]
|
|
8003700: 685b ldr r3, [r3, #4]
|
|
8003702: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8003706: 2b00 cmp r3, #0
|
|
8003708: d003 beq.n 8003712 <HAL_GPIO_Init+0x266>
|
|
{
|
|
temp |= iocurrent;
|
|
800370a: 693a ldr r2, [r7, #16]
|
|
800370c: 68fb ldr r3, [r7, #12]
|
|
800370e: 4313 orrs r3, r2
|
|
8003710: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8003712: 4a26 ldr r2, [pc, #152] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
8003714: 693b ldr r3, [r7, #16]
|
|
8003716: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR1;
|
|
8003718: 4b24 ldr r3, [pc, #144] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
800371a: 685b ldr r3, [r3, #4]
|
|
800371c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800371e: 68fb ldr r3, [r7, #12]
|
|
8003720: 43db mvns r3, r3
|
|
8003722: 693a ldr r2, [r7, #16]
|
|
8003724: 4013 ands r3, r2
|
|
8003726: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8003728: 683b ldr r3, [r7, #0]
|
|
800372a: 685b ldr r3, [r3, #4]
|
|
800372c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003730: 2b00 cmp r3, #0
|
|
8003732: d003 beq.n 800373c <HAL_GPIO_Init+0x290>
|
|
{
|
|
temp |= iocurrent;
|
|
8003734: 693a ldr r2, [r7, #16]
|
|
8003736: 68fb ldr r3, [r7, #12]
|
|
8003738: 4313 orrs r3, r2
|
|
800373a: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
800373c: 4a1b ldr r2, [pc, #108] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
800373e: 693b ldr r3, [r7, #16]
|
|
8003740: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR1;
|
|
8003742: 4b1a ldr r3, [pc, #104] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
8003744: 681b ldr r3, [r3, #0]
|
|
8003746: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8003748: 68fb ldr r3, [r7, #12]
|
|
800374a: 43db mvns r3, r3
|
|
800374c: 693a ldr r2, [r7, #16]
|
|
800374e: 4013 ands r3, r2
|
|
8003750: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8003752: 683b ldr r3, [r7, #0]
|
|
8003754: 685b ldr r3, [r3, #4]
|
|
8003756: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
800375a: 2b00 cmp r3, #0
|
|
800375c: d003 beq.n 8003766 <HAL_GPIO_Init+0x2ba>
|
|
{
|
|
temp |= iocurrent;
|
|
800375e: 693a ldr r2, [r7, #16]
|
|
8003760: 68fb ldr r3, [r7, #12]
|
|
8003762: 4313 orrs r3, r2
|
|
8003764: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8003766: 4a11 ldr r2, [pc, #68] @ (80037ac <HAL_GPIO_Init+0x300>)
|
|
8003768: 693b ldr r3, [r7, #16]
|
|
800376a: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
800376c: 697b ldr r3, [r7, #20]
|
|
800376e: 3301 adds r3, #1
|
|
8003770: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0U)
|
|
8003772: 683b ldr r3, [r7, #0]
|
|
8003774: 681a ldr r2, [r3, #0]
|
|
8003776: 697b ldr r3, [r7, #20]
|
|
8003778: fa22 f303 lsr.w r3, r2, r3
|
|
800377c: 2b00 cmp r3, #0
|
|
800377e: f47f ae9d bne.w 80034bc <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8003782: bf00 nop
|
|
8003784: bf00 nop
|
|
8003786: 371c adds r7, #28
|
|
8003788: 46bd mov sp, r7
|
|
800378a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800378e: 4770 bx lr
|
|
8003790: 40021000 .word 0x40021000
|
|
8003794: 40010000 .word 0x40010000
|
|
8003798: 48000400 .word 0x48000400
|
|
800379c: 48000800 .word 0x48000800
|
|
80037a0: 48000c00 .word 0x48000c00
|
|
80037a4: 48001000 .word 0x48001000
|
|
80037a8: 48001400 .word 0x48001400
|
|
80037ac: 40010400 .word 0x40010400
|
|
|
|
080037b0 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
80037b0: b480 push {r7}
|
|
80037b2: b083 sub sp, #12
|
|
80037b4: af00 add r7, sp, #0
|
|
80037b6: 6078 str r0, [r7, #4]
|
|
80037b8: 460b mov r3, r1
|
|
80037ba: 807b strh r3, [r7, #2]
|
|
80037bc: 4613 mov r3, r2
|
|
80037be: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
80037c0: 787b ldrb r3, [r7, #1]
|
|
80037c2: 2b00 cmp r3, #0
|
|
80037c4: d003 beq.n 80037ce <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
80037c6: 887a ldrh r2, [r7, #2]
|
|
80037c8: 687b ldr r3, [r7, #4]
|
|
80037ca: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
80037cc: e002 b.n 80037d4 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
80037ce: 887a ldrh r2, [r7, #2]
|
|
80037d0: 687b ldr r3, [r7, #4]
|
|
80037d2: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
80037d4: bf00 nop
|
|
80037d6: 370c adds r7, #12
|
|
80037d8: 46bd mov sp, r7
|
|
80037da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80037de: 4770 bx lr
|
|
|
|
080037e0 <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
80037e0: b480 push {r7}
|
|
80037e2: b085 sub sp, #20
|
|
80037e4: af00 add r7, sp, #0
|
|
80037e6: 6078 str r0, [r7, #4]
|
|
uint32_t wait_loop_index;
|
|
|
|
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
|
|
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
|
|
80037e8: 687b ldr r3, [r7, #4]
|
|
80037ea: 2b00 cmp r3, #0
|
|
80037ec: d141 bne.n 8003872 <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
{
|
|
/* If current range is range 2 */
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
80037ee: 4b4b ldr r3, [pc, #300] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80037f0: 681b ldr r3, [r3, #0]
|
|
80037f2: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
80037f6: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80037fa: d131 bne.n 8003860 <HAL_PWREx_ControlVoltageScaling+0x80>
|
|
{
|
|
/* Make sure Range 1 Boost is enabled */
|
|
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
80037fc: 4b47 ldr r3, [pc, #284] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80037fe: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003802: 4a46 ldr r2, [pc, #280] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003804: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8003808: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
800380c: 4b43 ldr r3, [pc, #268] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800380e: 681b ldr r3, [r3, #0]
|
|
8003810: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8003814: 4a41 ldr r2, [pc, #260] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003816: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800381a: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
800381c: 4b40 ldr r3, [pc, #256] @ (8003920 <HAL_PWREx_ControlVoltageScaling+0x140>)
|
|
800381e: 681b ldr r3, [r3, #0]
|
|
8003820: 2232 movs r2, #50 @ 0x32
|
|
8003822: fb02 f303 mul.w r3, r2, r3
|
|
8003826: 4a3f ldr r2, [pc, #252] @ (8003924 <HAL_PWREx_ControlVoltageScaling+0x144>)
|
|
8003828: fba2 2303 umull r2, r3, r2, r3
|
|
800382c: 0c9b lsrs r3, r3, #18
|
|
800382e: 3301 adds r3, #1
|
|
8003830: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8003832: e002 b.n 800383a <HAL_PWREx_ControlVoltageScaling+0x5a>
|
|
{
|
|
wait_loop_index--;
|
|
8003834: 68fb ldr r3, [r7, #12]
|
|
8003836: 3b01 subs r3, #1
|
|
8003838: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
800383a: 4b38 ldr r3, [pc, #224] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800383c: 695b ldr r3, [r3, #20]
|
|
800383e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003842: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8003846: d102 bne.n 800384e <HAL_PWREx_ControlVoltageScaling+0x6e>
|
|
8003848: 68fb ldr r3, [r7, #12]
|
|
800384a: 2b00 cmp r3, #0
|
|
800384c: d1f2 bne.n 8003834 <HAL_PWREx_ControlVoltageScaling+0x54>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
800384e: 4b33 ldr r3, [pc, #204] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003850: 695b ldr r3, [r3, #20]
|
|
8003852: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003856: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800385a: d158 bne.n 800390e <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800385c: 2303 movs r3, #3
|
|
800385e: e057 b.n 8003910 <HAL_PWREx_ControlVoltageScaling+0x130>
|
|
}
|
|
/* If current range is range 1 normal or boost mode */
|
|
else
|
|
{
|
|
/* Enable Range 1 Boost (no issue if bit already reset) */
|
|
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
8003860: 4b2e ldr r3, [pc, #184] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003862: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8003866: 4a2d ldr r2, [pc, #180] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003868: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800386c: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
8003870: e04d b.n 800390e <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
}
|
|
}
|
|
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8003872: 687b ldr r3, [r7, #4]
|
|
8003874: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8003878: d141 bne.n 80038fe <HAL_PWREx_ControlVoltageScaling+0x11e>
|
|
{
|
|
/* If current range is range 2 */
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
800387a: 4b28 ldr r3, [pc, #160] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800387c: 681b ldr r3, [r3, #0]
|
|
800387e: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
8003882: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8003886: d131 bne.n 80038ec <HAL_PWREx_ControlVoltageScaling+0x10c>
|
|
{
|
|
/* Make sure Range 1 Boost is disabled */
|
|
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
8003888: 4b24 ldr r3, [pc, #144] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800388a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800388e: 4a23 ldr r2, [pc, #140] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003890: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003894: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8003898: 4b20 ldr r3, [pc, #128] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
800389a: 681b ldr r3, [r3, #0]
|
|
800389c: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
80038a0: 4a1e ldr r2, [pc, #120] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80038a2: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
80038a6: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
80038a8: 4b1d ldr r3, [pc, #116] @ (8003920 <HAL_PWREx_ControlVoltageScaling+0x140>)
|
|
80038aa: 681b ldr r3, [r3, #0]
|
|
80038ac: 2232 movs r2, #50 @ 0x32
|
|
80038ae: fb02 f303 mul.w r3, r2, r3
|
|
80038b2: 4a1c ldr r2, [pc, #112] @ (8003924 <HAL_PWREx_ControlVoltageScaling+0x144>)
|
|
80038b4: fba2 2303 umull r2, r3, r2, r3
|
|
80038b8: 0c9b lsrs r3, r3, #18
|
|
80038ba: 3301 adds r3, #1
|
|
80038bc: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
80038be: e002 b.n 80038c6 <HAL_PWREx_ControlVoltageScaling+0xe6>
|
|
{
|
|
wait_loop_index--;
|
|
80038c0: 68fb ldr r3, [r7, #12]
|
|
80038c2: 3b01 subs r3, #1
|
|
80038c4: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
80038c6: 4b15 ldr r3, [pc, #84] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80038c8: 695b ldr r3, [r3, #20]
|
|
80038ca: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80038ce: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80038d2: d102 bne.n 80038da <HAL_PWREx_ControlVoltageScaling+0xfa>
|
|
80038d4: 68fb ldr r3, [r7, #12]
|
|
80038d6: 2b00 cmp r3, #0
|
|
80038d8: d1f2 bne.n 80038c0 <HAL_PWREx_ControlVoltageScaling+0xe0>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
80038da: 4b10 ldr r3, [pc, #64] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80038dc: 695b ldr r3, [r3, #20]
|
|
80038de: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80038e2: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80038e6: d112 bne.n 800390e <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80038e8: 2303 movs r3, #3
|
|
80038ea: e011 b.n 8003910 <HAL_PWREx_ControlVoltageScaling+0x130>
|
|
}
|
|
/* If current range is range 1 normal or boost mode */
|
|
else
|
|
{
|
|
/* Disable Range 1 Boost (no issue if bit already set) */
|
|
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
|
|
80038ec: 4b0b ldr r3, [pc, #44] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80038ee: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80038f2: 4a0a ldr r2, [pc, #40] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
80038f4: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80038f8: f8c2 3080 str.w r3, [r2, #128] @ 0x80
|
|
80038fc: e007 b.n 800390e <HAL_PWREx_ControlVoltageScaling+0x12e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
80038fe: 4b07 ldr r3, [pc, #28] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003900: 681b ldr r3, [r3, #0]
|
|
8003902: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
8003906: 4a05 ldr r2, [pc, #20] @ (800391c <HAL_PWREx_ControlVoltageScaling+0x13c>)
|
|
8003908: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800390c: 6013 str r3, [r2, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
|
|
}
|
|
|
|
return HAL_OK;
|
|
800390e: 2300 movs r3, #0
|
|
}
|
|
8003910: 4618 mov r0, r3
|
|
8003912: 3714 adds r7, #20
|
|
8003914: 46bd mov sp, r7
|
|
8003916: f85d 7b04 ldr.w r7, [sp], #4
|
|
800391a: 4770 bx lr
|
|
800391c: 40007000 .word 0x40007000
|
|
8003920: 2000001c .word 0x2000001c
|
|
8003924: 431bde83 .word 0x431bde83
|
|
|
|
08003928 <HAL_PWREx_DisableUCPDDeadBattery>:
|
|
* or to hand over control to the UCPD (which should therefore be
|
|
* initialized before doing the disable).
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_DisableUCPDDeadBattery(void)
|
|
{
|
|
8003928: b480 push {r7}
|
|
800392a: af00 add r7, sp, #0
|
|
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
|
|
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
|
|
800392c: 4b05 ldr r3, [pc, #20] @ (8003944 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
|
|
800392e: 689b ldr r3, [r3, #8]
|
|
8003930: 4a04 ldr r2, [pc, #16] @ (8003944 <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
|
|
8003932: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8003936: 6093 str r3, [r2, #8]
|
|
}
|
|
8003938: bf00 nop
|
|
800393a: 46bd mov sp, r7
|
|
800393c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003940: 4770 bx lr
|
|
8003942: bf00 nop
|
|
8003944: 40007000 .word 0x40007000
|
|
|
|
08003948 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8003948: b580 push {r7, lr}
|
|
800394a: b088 sub sp, #32
|
|
800394c: af00 add r7, sp, #0
|
|
800394e: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t temp_sysclksrc;
|
|
uint32_t temp_pllckcfg;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8003950: 687b ldr r3, [r7, #4]
|
|
8003952: 2b00 cmp r3, #0
|
|
8003954: d101 bne.n 800395a <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003956: 2301 movs r3, #1
|
|
8003958: e2fe b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800395a: 687b ldr r3, [r7, #4]
|
|
800395c: 681b ldr r3, [r3, #0]
|
|
800395e: f003 0301 and.w r3, r3, #1
|
|
8003962: 2b00 cmp r3, #0
|
|
8003964: d075 beq.n 8003a52 <HAL_RCC_OscConfig+0x10a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8003966: 4b97 ldr r3, [pc, #604] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003968: 689b ldr r3, [r3, #8]
|
|
800396a: f003 030c and.w r3, r3, #12
|
|
800396e: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8003970: 4b94 ldr r3, [pc, #592] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003972: 68db ldr r3, [r3, #12]
|
|
8003974: f003 0303 and.w r3, r3, #3
|
|
8003978: 617b str r3, [r7, #20]
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
|
|
800397a: 69bb ldr r3, [r7, #24]
|
|
800397c: 2b0c cmp r3, #12
|
|
800397e: d102 bne.n 8003986 <HAL_RCC_OscConfig+0x3e>
|
|
8003980: 697b ldr r3, [r7, #20]
|
|
8003982: 2b03 cmp r3, #3
|
|
8003984: d002 beq.n 800398c <HAL_RCC_OscConfig+0x44>
|
|
8003986: 69bb ldr r3, [r7, #24]
|
|
8003988: 2b08 cmp r3, #8
|
|
800398a: d10b bne.n 80039a4 <HAL_RCC_OscConfig+0x5c>
|
|
{
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
800398c: 4b8d ldr r3, [pc, #564] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
800398e: 681b ldr r3, [r3, #0]
|
|
8003990: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003994: 2b00 cmp r3, #0
|
|
8003996: d05b beq.n 8003a50 <HAL_RCC_OscConfig+0x108>
|
|
8003998: 687b ldr r3, [r7, #4]
|
|
800399a: 685b ldr r3, [r3, #4]
|
|
800399c: 2b00 cmp r3, #0
|
|
800399e: d157 bne.n 8003a50 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
return HAL_ERROR;
|
|
80039a0: 2301 movs r3, #1
|
|
80039a2: e2d9 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80039a4: 687b ldr r3, [r7, #4]
|
|
80039a6: 685b ldr r3, [r3, #4]
|
|
80039a8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
80039ac: d106 bne.n 80039bc <HAL_RCC_OscConfig+0x74>
|
|
80039ae: 4b85 ldr r3, [pc, #532] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039b0: 681b ldr r3, [r3, #0]
|
|
80039b2: 4a84 ldr r2, [pc, #528] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039b4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80039b8: 6013 str r3, [r2, #0]
|
|
80039ba: e01d b.n 80039f8 <HAL_RCC_OscConfig+0xb0>
|
|
80039bc: 687b ldr r3, [r7, #4]
|
|
80039be: 685b ldr r3, [r3, #4]
|
|
80039c0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
80039c4: d10c bne.n 80039e0 <HAL_RCC_OscConfig+0x98>
|
|
80039c6: 4b7f ldr r3, [pc, #508] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039c8: 681b ldr r3, [r3, #0]
|
|
80039ca: 4a7e ldr r2, [pc, #504] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039cc: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
80039d0: 6013 str r3, [r2, #0]
|
|
80039d2: 4b7c ldr r3, [pc, #496] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039d4: 681b ldr r3, [r3, #0]
|
|
80039d6: 4a7b ldr r2, [pc, #492] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039d8: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80039dc: 6013 str r3, [r2, #0]
|
|
80039de: e00b b.n 80039f8 <HAL_RCC_OscConfig+0xb0>
|
|
80039e0: 4b78 ldr r3, [pc, #480] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039e2: 681b ldr r3, [r3, #0]
|
|
80039e4: 4a77 ldr r2, [pc, #476] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039e6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80039ea: 6013 str r3, [r2, #0]
|
|
80039ec: 4b75 ldr r3, [pc, #468] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039ee: 681b ldr r3, [r3, #0]
|
|
80039f0: 4a74 ldr r2, [pc, #464] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
80039f2: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80039f6: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
80039f8: 687b ldr r3, [r7, #4]
|
|
80039fa: 685b ldr r3, [r3, #4]
|
|
80039fc: 2b00 cmp r3, #0
|
|
80039fe: d013 beq.n 8003a28 <HAL_RCC_OscConfig+0xe0>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003a00: f7fd feba bl 8001778 <HAL_GetTick>
|
|
8003a04: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003a06: e008 b.n 8003a1a <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003a08: f7fd feb6 bl 8001778 <HAL_GetTick>
|
|
8003a0c: 4602 mov r2, r0
|
|
8003a0e: 693b ldr r3, [r7, #16]
|
|
8003a10: 1ad3 subs r3, r2, r3
|
|
8003a12: 2b64 cmp r3, #100 @ 0x64
|
|
8003a14: d901 bls.n 8003a1a <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003a16: 2303 movs r3, #3
|
|
8003a18: e29e b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003a1a: 4b6a ldr r3, [pc, #424] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003a1c: 681b ldr r3, [r3, #0]
|
|
8003a1e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003a22: 2b00 cmp r3, #0
|
|
8003a24: d0f0 beq.n 8003a08 <HAL_RCC_OscConfig+0xc0>
|
|
8003a26: e014 b.n 8003a52 <HAL_RCC_OscConfig+0x10a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003a28: f7fd fea6 bl 8001778 <HAL_GetTick>
|
|
8003a2c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8003a2e: e008 b.n 8003a42 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003a30: f7fd fea2 bl 8001778 <HAL_GetTick>
|
|
8003a34: 4602 mov r2, r0
|
|
8003a36: 693b ldr r3, [r7, #16]
|
|
8003a38: 1ad3 subs r3, r2, r3
|
|
8003a3a: 2b64 cmp r3, #100 @ 0x64
|
|
8003a3c: d901 bls.n 8003a42 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003a3e: 2303 movs r3, #3
|
|
8003a40: e28a b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8003a42: 4b60 ldr r3, [pc, #384] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003a44: 681b ldr r3, [r3, #0]
|
|
8003a46: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003a4a: 2b00 cmp r3, #0
|
|
8003a4c: d1f0 bne.n 8003a30 <HAL_RCC_OscConfig+0xe8>
|
|
8003a4e: e000 b.n 8003a52 <HAL_RCC_OscConfig+0x10a>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8003a50: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8003a52: 687b ldr r3, [r7, #4]
|
|
8003a54: 681b ldr r3, [r3, #0]
|
|
8003a56: f003 0302 and.w r3, r3, #2
|
|
8003a5a: 2b00 cmp r3, #0
|
|
8003a5c: d075 beq.n 8003b4a <HAL_RCC_OscConfig+0x202>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8003a5e: 4b59 ldr r3, [pc, #356] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003a60: 689b ldr r3, [r3, #8]
|
|
8003a62: f003 030c and.w r3, r3, #12
|
|
8003a66: 61bb str r3, [r7, #24]
|
|
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8003a68: 4b56 ldr r3, [pc, #344] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003a6a: 68db ldr r3, [r3, #12]
|
|
8003a6c: f003 0303 and.w r3, r3, #3
|
|
8003a70: 617b str r3, [r7, #20]
|
|
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
|
|
8003a72: 69bb ldr r3, [r7, #24]
|
|
8003a74: 2b0c cmp r3, #12
|
|
8003a76: d102 bne.n 8003a7e <HAL_RCC_OscConfig+0x136>
|
|
8003a78: 697b ldr r3, [r7, #20]
|
|
8003a7a: 2b02 cmp r3, #2
|
|
8003a7c: d002 beq.n 8003a84 <HAL_RCC_OscConfig+0x13c>
|
|
8003a7e: 69bb ldr r3, [r7, #24]
|
|
8003a80: 2b04 cmp r3, #4
|
|
8003a82: d11f bne.n 8003ac4 <HAL_RCC_OscConfig+0x17c>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8003a84: 4b4f ldr r3, [pc, #316] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003a86: 681b ldr r3, [r3, #0]
|
|
8003a88: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003a8c: 2b00 cmp r3, #0
|
|
8003a8e: d005 beq.n 8003a9c <HAL_RCC_OscConfig+0x154>
|
|
8003a90: 687b ldr r3, [r7, #4]
|
|
8003a92: 68db ldr r3, [r3, #12]
|
|
8003a94: 2b00 cmp r3, #0
|
|
8003a96: d101 bne.n 8003a9c <HAL_RCC_OscConfig+0x154>
|
|
{
|
|
return HAL_ERROR;
|
|
8003a98: 2301 movs r3, #1
|
|
8003a9a: e25d b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003a9c: 4b49 ldr r3, [pc, #292] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003a9e: 685b ldr r3, [r3, #4]
|
|
8003aa0: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
|
|
8003aa4: 687b ldr r3, [r7, #4]
|
|
8003aa6: 691b ldr r3, [r3, #16]
|
|
8003aa8: 061b lsls r3, r3, #24
|
|
8003aaa: 4946 ldr r1, [pc, #280] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003aac: 4313 orrs r3, r2
|
|
8003aae: 604b str r3, [r1, #4]
|
|
|
|
/* Adapt Systick interrupt period */
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
8003ab0: 4b45 ldr r3, [pc, #276] @ (8003bc8 <HAL_RCC_OscConfig+0x280>)
|
|
8003ab2: 681b ldr r3, [r3, #0]
|
|
8003ab4: 4618 mov r0, r3
|
|
8003ab6: f7fd fe13 bl 80016e0 <HAL_InitTick>
|
|
8003aba: 4603 mov r3, r0
|
|
8003abc: 2b00 cmp r3, #0
|
|
8003abe: d043 beq.n 8003b48 <HAL_RCC_OscConfig+0x200>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ac0: 2301 movs r3, #1
|
|
8003ac2: e249 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8003ac4: 687b ldr r3, [r7, #4]
|
|
8003ac6: 68db ldr r3, [r3, #12]
|
|
8003ac8: 2b00 cmp r3, #0
|
|
8003aca: d023 beq.n 8003b14 <HAL_RCC_OscConfig+0x1cc>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8003acc: 4b3d ldr r3, [pc, #244] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003ace: 681b ldr r3, [r3, #0]
|
|
8003ad0: 4a3c ldr r2, [pc, #240] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003ad2: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003ad6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ad8: f7fd fe4e bl 8001778 <HAL_GetTick>
|
|
8003adc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003ade: e008 b.n 8003af2 <HAL_RCC_OscConfig+0x1aa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003ae0: f7fd fe4a bl 8001778 <HAL_GetTick>
|
|
8003ae4: 4602 mov r2, r0
|
|
8003ae6: 693b ldr r3, [r7, #16]
|
|
8003ae8: 1ad3 subs r3, r2, r3
|
|
8003aea: 2b02 cmp r3, #2
|
|
8003aec: d901 bls.n 8003af2 <HAL_RCC_OscConfig+0x1aa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003aee: 2303 movs r3, #3
|
|
8003af0: e232 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003af2: 4b34 ldr r3, [pc, #208] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003af4: 681b ldr r3, [r3, #0]
|
|
8003af6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003afa: 2b00 cmp r3, #0
|
|
8003afc: d0f0 beq.n 8003ae0 <HAL_RCC_OscConfig+0x198>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003afe: 4b31 ldr r3, [pc, #196] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b00: 685b ldr r3, [r3, #4]
|
|
8003b02: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
|
|
8003b06: 687b ldr r3, [r7, #4]
|
|
8003b08: 691b ldr r3, [r3, #16]
|
|
8003b0a: 061b lsls r3, r3, #24
|
|
8003b0c: 492d ldr r1, [pc, #180] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b0e: 4313 orrs r3, r2
|
|
8003b10: 604b str r3, [r1, #4]
|
|
8003b12: e01a b.n 8003b4a <HAL_RCC_OscConfig+0x202>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8003b14: 4b2b ldr r3, [pc, #172] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b16: 681b ldr r3, [r3, #0]
|
|
8003b18: 4a2a ldr r2, [pc, #168] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b1a: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8003b1e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003b20: f7fd fe2a bl 8001778 <HAL_GetTick>
|
|
8003b24: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8003b26: e008 b.n 8003b3a <HAL_RCC_OscConfig+0x1f2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003b28: f7fd fe26 bl 8001778 <HAL_GetTick>
|
|
8003b2c: 4602 mov r2, r0
|
|
8003b2e: 693b ldr r3, [r7, #16]
|
|
8003b30: 1ad3 subs r3, r2, r3
|
|
8003b32: 2b02 cmp r3, #2
|
|
8003b34: d901 bls.n 8003b3a <HAL_RCC_OscConfig+0x1f2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b36: 2303 movs r3, #3
|
|
8003b38: e20e b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8003b3a: 4b22 ldr r3, [pc, #136] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b3c: 681b ldr r3, [r3, #0]
|
|
8003b3e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003b42: 2b00 cmp r3, #0
|
|
8003b44: d1f0 bne.n 8003b28 <HAL_RCC_OscConfig+0x1e0>
|
|
8003b46: e000 b.n 8003b4a <HAL_RCC_OscConfig+0x202>
|
|
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8003b48: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8003b4a: 687b ldr r3, [r7, #4]
|
|
8003b4c: 681b ldr r3, [r3, #0]
|
|
8003b4e: f003 0308 and.w r3, r3, #8
|
|
8003b52: 2b00 cmp r3, #0
|
|
8003b54: d041 beq.n 8003bda <HAL_RCC_OscConfig+0x292>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8003b56: 687b ldr r3, [r7, #4]
|
|
8003b58: 695b ldr r3, [r3, #20]
|
|
8003b5a: 2b00 cmp r3, #0
|
|
8003b5c: d01c beq.n 8003b98 <HAL_RCC_OscConfig+0x250>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003b5e: 4b19 ldr r3, [pc, #100] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b60: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003b64: 4a17 ldr r2, [pc, #92] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b66: f043 0301 orr.w r3, r3, #1
|
|
8003b6a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003b6e: f7fd fe03 bl 8001778 <HAL_GetTick>
|
|
8003b72: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8003b74: e008 b.n 8003b88 <HAL_RCC_OscConfig+0x240>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003b76: f7fd fdff bl 8001778 <HAL_GetTick>
|
|
8003b7a: 4602 mov r2, r0
|
|
8003b7c: 693b ldr r3, [r7, #16]
|
|
8003b7e: 1ad3 subs r3, r2, r3
|
|
8003b80: 2b02 cmp r3, #2
|
|
8003b82: d901 bls.n 8003b88 <HAL_RCC_OscConfig+0x240>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b84: 2303 movs r3, #3
|
|
8003b86: e1e7 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8003b88: 4b0e ldr r3, [pc, #56] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b8a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003b8e: f003 0302 and.w r3, r3, #2
|
|
8003b92: 2b00 cmp r3, #0
|
|
8003b94: d0ef beq.n 8003b76 <HAL_RCC_OscConfig+0x22e>
|
|
8003b96: e020 b.n 8003bda <HAL_RCC_OscConfig+0x292>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8003b98: 4b0a ldr r3, [pc, #40] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003b9a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003b9e: 4a09 ldr r2, [pc, #36] @ (8003bc4 <HAL_RCC_OscConfig+0x27c>)
|
|
8003ba0: f023 0301 bic.w r3, r3, #1
|
|
8003ba4: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ba8: f7fd fde6 bl 8001778 <HAL_GetTick>
|
|
8003bac: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8003bae: e00d b.n 8003bcc <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003bb0: f7fd fde2 bl 8001778 <HAL_GetTick>
|
|
8003bb4: 4602 mov r2, r0
|
|
8003bb6: 693b ldr r3, [r7, #16]
|
|
8003bb8: 1ad3 subs r3, r2, r3
|
|
8003bba: 2b02 cmp r3, #2
|
|
8003bbc: d906 bls.n 8003bcc <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003bbe: 2303 movs r3, #3
|
|
8003bc0: e1ca b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
8003bc2: bf00 nop
|
|
8003bc4: 40021000 .word 0x40021000
|
|
8003bc8: 20000020 .word 0x20000020
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8003bcc: 4b8c ldr r3, [pc, #560] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003bce: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003bd2: f003 0302 and.w r3, r3, #2
|
|
8003bd6: 2b00 cmp r3, #0
|
|
8003bd8: d1ea bne.n 8003bb0 <HAL_RCC_OscConfig+0x268>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8003bda: 687b ldr r3, [r7, #4]
|
|
8003bdc: 681b ldr r3, [r3, #0]
|
|
8003bde: f003 0304 and.w r3, r3, #4
|
|
8003be2: 2b00 cmp r3, #0
|
|
8003be4: f000 80a6 beq.w 8003d34 <HAL_RCC_OscConfig+0x3ec>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003be8: 2300 movs r3, #0
|
|
8003bea: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain if necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
8003bec: 4b84 ldr r3, [pc, #528] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003bee: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003bf0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003bf4: 2b00 cmp r3, #0
|
|
8003bf6: d101 bne.n 8003bfc <HAL_RCC_OscConfig+0x2b4>
|
|
8003bf8: 2301 movs r3, #1
|
|
8003bfa: e000 b.n 8003bfe <HAL_RCC_OscConfig+0x2b6>
|
|
8003bfc: 2300 movs r3, #0
|
|
8003bfe: 2b00 cmp r3, #0
|
|
8003c00: d00d beq.n 8003c1e <HAL_RCC_OscConfig+0x2d6>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003c02: 4b7f ldr r3, [pc, #508] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c04: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003c06: 4a7e ldr r2, [pc, #504] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c08: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003c0c: 6593 str r3, [r2, #88] @ 0x58
|
|
8003c0e: 4b7c ldr r3, [pc, #496] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c10: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003c12: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003c16: 60fb str r3, [r7, #12]
|
|
8003c18: 68fb ldr r3, [r7, #12]
|
|
pwrclkchanged = SET;
|
|
8003c1a: 2301 movs r3, #1
|
|
8003c1c: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003c1e: 4b79 ldr r3, [pc, #484] @ (8003e04 <HAL_RCC_OscConfig+0x4bc>)
|
|
8003c20: 681b ldr r3, [r3, #0]
|
|
8003c22: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003c26: 2b00 cmp r3, #0
|
|
8003c28: d118 bne.n 8003c5c <HAL_RCC_OscConfig+0x314>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8003c2a: 4b76 ldr r3, [pc, #472] @ (8003e04 <HAL_RCC_OscConfig+0x4bc>)
|
|
8003c2c: 681b ldr r3, [r3, #0]
|
|
8003c2e: 4a75 ldr r2, [pc, #468] @ (8003e04 <HAL_RCC_OscConfig+0x4bc>)
|
|
8003c30: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003c34: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8003c36: f7fd fd9f bl 8001778 <HAL_GetTick>
|
|
8003c3a: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003c3c: e008 b.n 8003c50 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8003c3e: f7fd fd9b bl 8001778 <HAL_GetTick>
|
|
8003c42: 4602 mov r2, r0
|
|
8003c44: 693b ldr r3, [r7, #16]
|
|
8003c46: 1ad3 subs r3, r2, r3
|
|
8003c48: 2b02 cmp r3, #2
|
|
8003c4a: d901 bls.n 8003c50 <HAL_RCC_OscConfig+0x308>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c4c: 2303 movs r3, #3
|
|
8003c4e: e183 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003c50: 4b6c ldr r3, [pc, #432] @ (8003e04 <HAL_RCC_OscConfig+0x4bc>)
|
|
8003c52: 681b ldr r3, [r3, #0]
|
|
8003c54: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003c58: 2b00 cmp r3, #0
|
|
8003c5a: d0f0 beq.n 8003c3e <HAL_RCC_OscConfig+0x2f6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8003c5c: 687b ldr r3, [r7, #4]
|
|
8003c5e: 689b ldr r3, [r3, #8]
|
|
8003c60: 2b01 cmp r3, #1
|
|
8003c62: d108 bne.n 8003c76 <HAL_RCC_OscConfig+0x32e>
|
|
8003c64: 4b66 ldr r3, [pc, #408] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c66: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003c6a: 4a65 ldr r2, [pc, #404] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c6c: f043 0301 orr.w r3, r3, #1
|
|
8003c70: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003c74: e024 b.n 8003cc0 <HAL_RCC_OscConfig+0x378>
|
|
8003c76: 687b ldr r3, [r7, #4]
|
|
8003c78: 689b ldr r3, [r3, #8]
|
|
8003c7a: 2b05 cmp r3, #5
|
|
8003c7c: d110 bne.n 8003ca0 <HAL_RCC_OscConfig+0x358>
|
|
8003c7e: 4b60 ldr r3, [pc, #384] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c80: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003c84: 4a5e ldr r2, [pc, #376] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c86: f043 0304 orr.w r3, r3, #4
|
|
8003c8a: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003c8e: 4b5c ldr r3, [pc, #368] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c90: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003c94: 4a5a ldr r2, [pc, #360] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003c96: f043 0301 orr.w r3, r3, #1
|
|
8003c9a: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003c9e: e00f b.n 8003cc0 <HAL_RCC_OscConfig+0x378>
|
|
8003ca0: 4b57 ldr r3, [pc, #348] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003ca2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003ca6: 4a56 ldr r2, [pc, #344] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003ca8: f023 0301 bic.w r3, r3, #1
|
|
8003cac: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003cb0: 4b53 ldr r3, [pc, #332] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003cb2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003cb6: 4a52 ldr r2, [pc, #328] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003cb8: f023 0304 bic.w r3, r3, #4
|
|
8003cbc: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
|
|
/* Check the LSE State */
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8003cc0: 687b ldr r3, [r7, #4]
|
|
8003cc2: 689b ldr r3, [r3, #8]
|
|
8003cc4: 2b00 cmp r3, #0
|
|
8003cc6: d016 beq.n 8003cf6 <HAL_RCC_OscConfig+0x3ae>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003cc8: f7fd fd56 bl 8001778 <HAL_GetTick>
|
|
8003ccc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003cce: e00a b.n 8003ce6 <HAL_RCC_OscConfig+0x39e>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003cd0: f7fd fd52 bl 8001778 <HAL_GetTick>
|
|
8003cd4: 4602 mov r2, r0
|
|
8003cd6: 693b ldr r3, [r7, #16]
|
|
8003cd8: 1ad3 subs r3, r2, r3
|
|
8003cda: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003cde: 4293 cmp r3, r2
|
|
8003ce0: d901 bls.n 8003ce6 <HAL_RCC_OscConfig+0x39e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ce2: 2303 movs r3, #3
|
|
8003ce4: e138 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003ce6: 4b46 ldr r3, [pc, #280] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003ce8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003cec: f003 0302 and.w r3, r3, #2
|
|
8003cf0: 2b00 cmp r3, #0
|
|
8003cf2: d0ed beq.n 8003cd0 <HAL_RCC_OscConfig+0x388>
|
|
8003cf4: e015 b.n 8003d22 <HAL_RCC_OscConfig+0x3da>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003cf6: f7fd fd3f bl 8001778 <HAL_GetTick>
|
|
8003cfa: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8003cfc: e00a b.n 8003d14 <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003cfe: f7fd fd3b bl 8001778 <HAL_GetTick>
|
|
8003d02: 4602 mov r2, r0
|
|
8003d04: 693b ldr r3, [r7, #16]
|
|
8003d06: 1ad3 subs r3, r2, r3
|
|
8003d08: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003d0c: 4293 cmp r3, r2
|
|
8003d0e: d901 bls.n 8003d14 <HAL_RCC_OscConfig+0x3cc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d10: 2303 movs r3, #3
|
|
8003d12: e121 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8003d14: 4b3a ldr r3, [pc, #232] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d16: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d1a: f003 0302 and.w r3, r3, #2
|
|
8003d1e: 2b00 cmp r3, #0
|
|
8003d20: d1ed bne.n 8003cfe <HAL_RCC_OscConfig+0x3b6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8003d22: 7ffb ldrb r3, [r7, #31]
|
|
8003d24: 2b01 cmp r3, #1
|
|
8003d26: d105 bne.n 8003d34 <HAL_RCC_OscConfig+0x3ec>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8003d28: 4b35 ldr r3, [pc, #212] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d2a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003d2c: 4a34 ldr r2, [pc, #208] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d2e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003d32: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*------------------------------ HSI48 Configuration -----------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
|
|
8003d34: 687b ldr r3, [r7, #4]
|
|
8003d36: 681b ldr r3, [r3, #0]
|
|
8003d38: f003 0320 and.w r3, r3, #32
|
|
8003d3c: 2b00 cmp r3, #0
|
|
8003d3e: d03c beq.n 8003dba <HAL_RCC_OscConfig+0x472>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
|
|
|
|
/* Check the HSI48 State */
|
|
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
|
|
8003d40: 687b ldr r3, [r7, #4]
|
|
8003d42: 699b ldr r3, [r3, #24]
|
|
8003d44: 2b00 cmp r3, #0
|
|
8003d46: d01c beq.n 8003d82 <HAL_RCC_OscConfig+0x43a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_ENABLE();
|
|
8003d48: 4b2d ldr r3, [pc, #180] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d4a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8003d4e: 4a2c ldr r2, [pc, #176] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d50: f043 0301 orr.w r3, r3, #1
|
|
8003d54: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003d58: f7fd fd0e bl 8001778 <HAL_GetTick>
|
|
8003d5c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI48 is ready */
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
8003d5e: e008 b.n 8003d72 <HAL_RCC_OscConfig+0x42a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
8003d60: f7fd fd0a bl 8001778 <HAL_GetTick>
|
|
8003d64: 4602 mov r2, r0
|
|
8003d66: 693b ldr r3, [r7, #16]
|
|
8003d68: 1ad3 subs r3, r2, r3
|
|
8003d6a: 2b02 cmp r3, #2
|
|
8003d6c: d901 bls.n 8003d72 <HAL_RCC_OscConfig+0x42a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d6e: 2303 movs r3, #3
|
|
8003d70: e0f2 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
|
|
8003d72: 4b23 ldr r3, [pc, #140] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d74: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8003d78: f003 0302 and.w r3, r3, #2
|
|
8003d7c: 2b00 cmp r3, #0
|
|
8003d7e: d0ef beq.n 8003d60 <HAL_RCC_OscConfig+0x418>
|
|
8003d80: e01b b.n 8003dba <HAL_RCC_OscConfig+0x472>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (HSI48). */
|
|
__HAL_RCC_HSI48_DISABLE();
|
|
8003d82: 4b1f ldr r3, [pc, #124] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d84: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8003d88: 4a1d ldr r2, [pc, #116] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003d8a: f023 0301 bic.w r3, r3, #1
|
|
8003d8e: f8c2 3098 str.w r3, [r2, #152] @ 0x98
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003d92: f7fd fcf1 bl 8001778 <HAL_GetTick>
|
|
8003d96: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI48 is disabled */
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
8003d98: e008 b.n 8003dac <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
|
|
8003d9a: f7fd fced bl 8001778 <HAL_GetTick>
|
|
8003d9e: 4602 mov r2, r0
|
|
8003da0: 693b ldr r3, [r7, #16]
|
|
8003da2: 1ad3 subs r3, r2, r3
|
|
8003da4: 2b02 cmp r3, #2
|
|
8003da6: d901 bls.n 8003dac <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003da8: 2303 movs r3, #3
|
|
8003daa: e0d5 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
|
|
8003dac: 4b14 ldr r3, [pc, #80] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003dae: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
|
|
8003db2: f003 0302 and.w r3, r3, #2
|
|
8003db6: 2b00 cmp r3, #0
|
|
8003db8: d1ef bne.n 8003d9a <HAL_RCC_OscConfig+0x452>
|
|
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8003dba: 687b ldr r3, [r7, #4]
|
|
8003dbc: 69db ldr r3, [r3, #28]
|
|
8003dbe: 2b00 cmp r3, #0
|
|
8003dc0: f000 80c9 beq.w 8003f56 <HAL_RCC_OscConfig+0x60e>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
8003dc4: 4b0e ldr r3, [pc, #56] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003dc6: 689b ldr r3, [r3, #8]
|
|
8003dc8: f003 030c and.w r3, r3, #12
|
|
8003dcc: 2b0c cmp r3, #12
|
|
8003dce: f000 8083 beq.w 8003ed8 <HAL_RCC_OscConfig+0x590>
|
|
{
|
|
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8003dd2: 687b ldr r3, [r7, #4]
|
|
8003dd4: 69db ldr r3, [r3, #28]
|
|
8003dd6: 2b02 cmp r3, #2
|
|
8003dd8: d15e bne.n 8003e98 <HAL_RCC_OscConfig+0x550>
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003dda: 4b09 ldr r3, [pc, #36] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003ddc: 681b ldr r3, [r3, #0]
|
|
8003dde: 4a08 ldr r2, [pc, #32] @ (8003e00 <HAL_RCC_OscConfig+0x4b8>)
|
|
8003de0: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8003de4: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003de6: f7fd fcc7 bl 8001778 <HAL_GetTick>
|
|
8003dea: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003dec: e00c b.n 8003e08 <HAL_RCC_OscConfig+0x4c0>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003dee: f7fd fcc3 bl 8001778 <HAL_GetTick>
|
|
8003df2: 4602 mov r2, r0
|
|
8003df4: 693b ldr r3, [r7, #16]
|
|
8003df6: 1ad3 subs r3, r2, r3
|
|
8003df8: 2b02 cmp r3, #2
|
|
8003dfa: d905 bls.n 8003e08 <HAL_RCC_OscConfig+0x4c0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003dfc: 2303 movs r3, #3
|
|
8003dfe: e0ab b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
8003e00: 40021000 .word 0x40021000
|
|
8003e04: 40007000 .word 0x40007000
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003e08: 4b55 ldr r3, [pc, #340] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e0a: 681b ldr r3, [r3, #0]
|
|
8003e0c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003e10: 2b00 cmp r3, #0
|
|
8003e12: d1ec bne.n 8003dee <HAL_RCC_OscConfig+0x4a6>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8003e14: 4b52 ldr r3, [pc, #328] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e16: 68da ldr r2, [r3, #12]
|
|
8003e18: 4b52 ldr r3, [pc, #328] @ (8003f64 <HAL_RCC_OscConfig+0x61c>)
|
|
8003e1a: 4013 ands r3, r2
|
|
8003e1c: 687a ldr r2, [r7, #4]
|
|
8003e1e: 6a11 ldr r1, [r2, #32]
|
|
8003e20: 687a ldr r2, [r7, #4]
|
|
8003e22: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
8003e24: 3a01 subs r2, #1
|
|
8003e26: 0112 lsls r2, r2, #4
|
|
8003e28: 4311 orrs r1, r2
|
|
8003e2a: 687a ldr r2, [r7, #4]
|
|
8003e2c: 6a92 ldr r2, [r2, #40] @ 0x28
|
|
8003e2e: 0212 lsls r2, r2, #8
|
|
8003e30: 4311 orrs r1, r2
|
|
8003e32: 687a ldr r2, [r7, #4]
|
|
8003e34: 6b12 ldr r2, [r2, #48] @ 0x30
|
|
8003e36: 0852 lsrs r2, r2, #1
|
|
8003e38: 3a01 subs r2, #1
|
|
8003e3a: 0552 lsls r2, r2, #21
|
|
8003e3c: 4311 orrs r1, r2
|
|
8003e3e: 687a ldr r2, [r7, #4]
|
|
8003e40: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
8003e42: 0852 lsrs r2, r2, #1
|
|
8003e44: 3a01 subs r2, #1
|
|
8003e46: 0652 lsls r2, r2, #25
|
|
8003e48: 4311 orrs r1, r2
|
|
8003e4a: 687a ldr r2, [r7, #4]
|
|
8003e4c: 6ad2 ldr r2, [r2, #44] @ 0x2c
|
|
8003e4e: 06d2 lsls r2, r2, #27
|
|
8003e50: 430a orrs r2, r1
|
|
8003e52: 4943 ldr r1, [pc, #268] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e54: 4313 orrs r3, r2
|
|
8003e56: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8003e58: 4b41 ldr r3, [pc, #260] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e5a: 681b ldr r3, [r3, #0]
|
|
8003e5c: 4a40 ldr r2, [pc, #256] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e5e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003e62: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8003e64: 4b3e ldr r3, [pc, #248] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e66: 68db ldr r3, [r3, #12]
|
|
8003e68: 4a3d ldr r2, [pc, #244] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e6a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003e6e: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003e70: f7fd fc82 bl 8001778 <HAL_GetTick>
|
|
8003e74: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003e76: e008 b.n 8003e8a <HAL_RCC_OscConfig+0x542>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003e78: f7fd fc7e bl 8001778 <HAL_GetTick>
|
|
8003e7c: 4602 mov r2, r0
|
|
8003e7e: 693b ldr r3, [r7, #16]
|
|
8003e80: 1ad3 subs r3, r2, r3
|
|
8003e82: 2b02 cmp r3, #2
|
|
8003e84: d901 bls.n 8003e8a <HAL_RCC_OscConfig+0x542>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003e86: 2303 movs r3, #3
|
|
8003e88: e066 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003e8a: 4b35 ldr r3, [pc, #212] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e8c: 681b ldr r3, [r3, #0]
|
|
8003e8e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003e92: 2b00 cmp r3, #0
|
|
8003e94: d0f0 beq.n 8003e78 <HAL_RCC_OscConfig+0x530>
|
|
8003e96: e05e b.n 8003f56 <HAL_RCC_OscConfig+0x60e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003e98: 4b31 ldr r3, [pc, #196] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e9a: 681b ldr r3, [r3, #0]
|
|
8003e9c: 4a30 ldr r2, [pc, #192] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003e9e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8003ea2: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ea4: f7fd fc68 bl 8001778 <HAL_GetTick>
|
|
8003ea8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003eaa: e008 b.n 8003ebe <HAL_RCC_OscConfig+0x576>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003eac: f7fd fc64 bl 8001778 <HAL_GetTick>
|
|
8003eb0: 4602 mov r2, r0
|
|
8003eb2: 693b ldr r3, [r7, #16]
|
|
8003eb4: 1ad3 subs r3, r2, r3
|
|
8003eb6: 2b02 cmp r3, #2
|
|
8003eb8: d901 bls.n 8003ebe <HAL_RCC_OscConfig+0x576>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003eba: 2303 movs r3, #3
|
|
8003ebc: e04c b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003ebe: 4b28 ldr r3, [pc, #160] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ec0: 681b ldr r3, [r3, #0]
|
|
8003ec2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003ec6: 2b00 cmp r3, #0
|
|
8003ec8: d1f0 bne.n 8003eac <HAL_RCC_OscConfig+0x564>
|
|
}
|
|
}
|
|
|
|
/* Unselect PLL clock source and disable outputs to save power */
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
|
|
8003eca: 4b25 ldr r3, [pc, #148] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ecc: 68da ldr r2, [r3, #12]
|
|
8003ece: 4924 ldr r1, [pc, #144] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ed0: 4b25 ldr r3, [pc, #148] @ (8003f68 <HAL_RCC_OscConfig+0x620>)
|
|
8003ed2: 4013 ands r3, r2
|
|
8003ed4: 60cb str r3, [r1, #12]
|
|
8003ed6: e03e b.n 8003f56 <HAL_RCC_OscConfig+0x60e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8003ed8: 687b ldr r3, [r7, #4]
|
|
8003eda: 69db ldr r3, [r3, #28]
|
|
8003edc: 2b01 cmp r3, #1
|
|
8003ede: d101 bne.n 8003ee4 <HAL_RCC_OscConfig+0x59c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ee0: 2301 movs r3, #1
|
|
8003ee2: e039 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
temp_pllckcfg = RCC->PLLCFGR;
|
|
8003ee4: 4b1e ldr r3, [pc, #120] @ (8003f60 <HAL_RCC_OscConfig+0x618>)
|
|
8003ee6: 68db ldr r3, [r3, #12]
|
|
8003ee8: 617b str r3, [r7, #20]
|
|
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003eea: 697b ldr r3, [r7, #20]
|
|
8003eec: f003 0203 and.w r2, r3, #3
|
|
8003ef0: 687b ldr r3, [r7, #4]
|
|
8003ef2: 6a1b ldr r3, [r3, #32]
|
|
8003ef4: 429a cmp r2, r3
|
|
8003ef6: d12c bne.n 8003f52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8003ef8: 697b ldr r3, [r7, #20]
|
|
8003efa: f003 02f0 and.w r2, r3, #240 @ 0xf0
|
|
8003efe: 687b ldr r3, [r7, #4]
|
|
8003f00: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003f02: 3b01 subs r3, #1
|
|
8003f04: 011b lsls r3, r3, #4
|
|
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003f06: 429a cmp r2, r3
|
|
8003f08: d123 bne.n 8003f52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003f0a: 697b ldr r3, [r7, #20]
|
|
8003f0c: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
8003f10: 687b ldr r3, [r7, #4]
|
|
8003f12: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003f14: 021b lsls r3, r3, #8
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8003f16: 429a cmp r2, r3
|
|
8003f18: d11b bne.n 8003f52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
8003f1a: 697b ldr r3, [r7, #20]
|
|
8003f1c: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
|
|
8003f20: 687b ldr r3, [r7, #4]
|
|
8003f22: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003f24: 06db lsls r3, r3, #27
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003f26: 429a cmp r2, r3
|
|
8003f28: d113 bne.n 8003f52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8003f2a: 697b ldr r3, [r7, #20]
|
|
8003f2c: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
|
|
8003f30: 687b ldr r3, [r7, #4]
|
|
8003f32: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003f34: 085b lsrs r3, r3, #1
|
|
8003f36: 3b01 subs r3, #1
|
|
8003f38: 055b lsls r3, r3, #21
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
8003f3a: 429a cmp r2, r3
|
|
8003f3c: d109 bne.n 8003f52 <HAL_RCC_OscConfig+0x60a>
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
8003f3e: 697b ldr r3, [r7, #20]
|
|
8003f40: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
|
|
8003f44: 687b ldr r3, [r7, #4]
|
|
8003f46: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003f48: 085b lsrs r3, r3, #1
|
|
8003f4a: 3b01 subs r3, #1
|
|
8003f4c: 065b lsls r3, r3, #25
|
|
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8003f4e: 429a cmp r2, r3
|
|
8003f50: d001 beq.n 8003f56 <HAL_RCC_OscConfig+0x60e>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f52: 2301 movs r3, #1
|
|
8003f54: e000 b.n 8003f58 <HAL_RCC_OscConfig+0x610>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003f56: 2300 movs r3, #0
|
|
}
|
|
8003f58: 4618 mov r0, r3
|
|
8003f5a: 3720 adds r7, #32
|
|
8003f5c: 46bd mov sp, r7
|
|
8003f5e: bd80 pop {r7, pc}
|
|
8003f60: 40021000 .word 0x40021000
|
|
8003f64: 019f800c .word 0x019f800c
|
|
8003f68: feeefffc .word 0xfeeefffc
|
|
|
|
08003f6c <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8003f6c: b580 push {r7, lr}
|
|
8003f6e: b086 sub sp, #24
|
|
8003f70: af00 add r7, sp, #0
|
|
8003f72: 6078 str r0, [r7, #4]
|
|
8003f74: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t pllfreq;
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
8003f76: 2300 movs r3, #0
|
|
8003f78: 617b str r3, [r7, #20]
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
8003f7a: 687b ldr r3, [r7, #4]
|
|
8003f7c: 2b00 cmp r3, #0
|
|
8003f7e: d101 bne.n 8003f84 <HAL_RCC_ClockConfig+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8003f80: 2301 movs r3, #1
|
|
8003f82: e11e b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8003f84: 4b91 ldr r3, [pc, #580] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
8003f86: 681b ldr r3, [r3, #0]
|
|
8003f88: f003 030f and.w r3, r3, #15
|
|
8003f8c: 683a ldr r2, [r7, #0]
|
|
8003f8e: 429a cmp r2, r3
|
|
8003f90: d910 bls.n 8003fb4 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003f92: 4b8e ldr r3, [pc, #568] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
8003f94: 681b ldr r3, [r3, #0]
|
|
8003f96: f023 020f bic.w r2, r3, #15
|
|
8003f9a: 498c ldr r1, [pc, #560] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
8003f9c: 683b ldr r3, [r7, #0]
|
|
8003f9e: 4313 orrs r3, r2
|
|
8003fa0: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8003fa2: 4b8a ldr r3, [pc, #552] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
8003fa4: 681b ldr r3, [r3, #0]
|
|
8003fa6: f003 030f and.w r3, r3, #15
|
|
8003faa: 683a ldr r2, [r7, #0]
|
|
8003fac: 429a cmp r2, r3
|
|
8003fae: d001 beq.n 8003fb4 <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
return HAL_ERROR;
|
|
8003fb0: 2301 movs r3, #1
|
|
8003fb2: e106 b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003fb4: 687b ldr r3, [r7, #4]
|
|
8003fb6: 681b ldr r3, [r3, #0]
|
|
8003fb8: f003 0301 and.w r3, r3, #1
|
|
8003fbc: 2b00 cmp r3, #0
|
|
8003fbe: d073 beq.n 80040a8 <HAL_RCC_ClockConfig+0x13c>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8003fc0: 687b ldr r3, [r7, #4]
|
|
8003fc2: 685b ldr r3, [r3, #4]
|
|
8003fc4: 2b03 cmp r3, #3
|
|
8003fc6: d129 bne.n 800401c <HAL_RCC_ClockConfig+0xb0>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003fc8: 4b81 ldr r3, [pc, #516] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8003fca: 681b ldr r3, [r3, #0]
|
|
8003fcc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003fd0: 2b00 cmp r3, #0
|
|
8003fd2: d101 bne.n 8003fd8 <HAL_RCC_ClockConfig+0x6c>
|
|
{
|
|
return HAL_ERROR;
|
|
8003fd4: 2301 movs r3, #1
|
|
8003fd6: e0f4 b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
|
|
/* Compute target PLL output frequency */
|
|
pllfreq = RCC_GetSysClockFreqFromPLLSource();
|
|
8003fd8: f000 f99e bl 8004318 <RCC_GetSysClockFreqFromPLLSource>
|
|
8003fdc: 6138 str r0, [r7, #16]
|
|
|
|
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
|
|
if(pllfreq > 80000000U)
|
|
8003fde: 693b ldr r3, [r7, #16]
|
|
8003fe0: 4a7c ldr r2, [pc, #496] @ (80041d4 <HAL_RCC_ClockConfig+0x268>)
|
|
8003fe2: 4293 cmp r3, r2
|
|
8003fe4: d93f bls.n 8004066 <HAL_RCC_ClockConfig+0xfa>
|
|
{
|
|
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
|
|
8003fe6: 4b7a ldr r3, [pc, #488] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8003fe8: 689b ldr r3, [r3, #8]
|
|
8003fea: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8003fee: 2b00 cmp r3, #0
|
|
8003ff0: d009 beq.n 8004006 <HAL_RCC_ClockConfig+0x9a>
|
|
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
|
|
8003ff2: 687b ldr r3, [r7, #4]
|
|
8003ff4: 681b ldr r3, [r3, #0]
|
|
8003ff6: f003 0302 and.w r3, r3, #2
|
|
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
|
|
8003ffa: 2b00 cmp r3, #0
|
|
8003ffc: d033 beq.n 8004066 <HAL_RCC_ClockConfig+0xfa>
|
|
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
|
|
8003ffe: 687b ldr r3, [r7, #4]
|
|
8004000: 689b ldr r3, [r3, #8]
|
|
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
|
|
8004002: 2b00 cmp r3, #0
|
|
8004004: d12f bne.n 8004066 <HAL_RCC_ClockConfig+0xfa>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
|
|
8004006: 4b72 ldr r3, [pc, #456] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004008: 689b ldr r3, [r3, #8]
|
|
800400a: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800400e: 4a70 ldr r2, [pc, #448] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004010: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8004014: 6093 str r3, [r2, #8]
|
|
hpre = RCC_SYSCLK_DIV2;
|
|
8004016: 2380 movs r3, #128 @ 0x80
|
|
8004018: 617b str r3, [r7, #20]
|
|
800401a: e024 b.n 8004066 <HAL_RCC_ClockConfig+0xfa>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800401c: 687b ldr r3, [r7, #4]
|
|
800401e: 685b ldr r3, [r3, #4]
|
|
8004020: 2b02 cmp r3, #2
|
|
8004022: d107 bne.n 8004034 <HAL_RCC_ClockConfig+0xc8>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8004024: 4b6a ldr r3, [pc, #424] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004026: 681b ldr r3, [r3, #0]
|
|
8004028: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
800402c: 2b00 cmp r3, #0
|
|
800402e: d109 bne.n 8004044 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
8004030: 2301 movs r3, #1
|
|
8004032: e0c6 b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8004034: 4b66 ldr r3, [pc, #408] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004036: 681b ldr r3, [r3, #0]
|
|
8004038: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800403c: 2b00 cmp r3, #0
|
|
800403e: d101 bne.n 8004044 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
8004040: 2301 movs r3, #1
|
|
8004042: e0be b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
}
|
|
}
|
|
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
|
|
pllfreq = HAL_RCC_GetSysClockFreq();
|
|
8004044: f000 f8ce bl 80041e4 <HAL_RCC_GetSysClockFreq>
|
|
8004048: 6138 str r0, [r7, #16]
|
|
|
|
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
|
|
if(pllfreq > 80000000U)
|
|
800404a: 693b ldr r3, [r7, #16]
|
|
800404c: 4a61 ldr r2, [pc, #388] @ (80041d4 <HAL_RCC_ClockConfig+0x268>)
|
|
800404e: 4293 cmp r3, r2
|
|
8004050: d909 bls.n 8004066 <HAL_RCC_ClockConfig+0xfa>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
|
|
8004052: 4b5f ldr r3, [pc, #380] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004054: 689b ldr r3, [r3, #8]
|
|
8004056: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800405a: 4a5d ldr r2, [pc, #372] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
800405c: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8004060: 6093 str r3, [r2, #8]
|
|
hpre = RCC_SYSCLK_DIV2;
|
|
8004062: 2380 movs r3, #128 @ 0x80
|
|
8004064: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
8004066: 4b5a ldr r3, [pc, #360] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004068: 689b ldr r3, [r3, #8]
|
|
800406a: f023 0203 bic.w r2, r3, #3
|
|
800406e: 687b ldr r3, [r7, #4]
|
|
8004070: 685b ldr r3, [r3, #4]
|
|
8004072: 4957 ldr r1, [pc, #348] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004074: 4313 orrs r3, r2
|
|
8004076: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004078: f7fd fb7e bl 8001778 <HAL_GetTick>
|
|
800407c: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800407e: e00a b.n 8004096 <HAL_RCC_ClockConfig+0x12a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8004080: f7fd fb7a bl 8001778 <HAL_GetTick>
|
|
8004084: 4602 mov r2, r0
|
|
8004086: 68fb ldr r3, [r7, #12]
|
|
8004088: 1ad3 subs r3, r2, r3
|
|
800408a: f241 3288 movw r2, #5000 @ 0x1388
|
|
800408e: 4293 cmp r3, r2
|
|
8004090: d901 bls.n 8004096 <HAL_RCC_ClockConfig+0x12a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004092: 2303 movs r3, #3
|
|
8004094: e095 b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8004096: 4b4e ldr r3, [pc, #312] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004098: 689b ldr r3, [r3, #8]
|
|
800409a: f003 020c and.w r2, r3, #12
|
|
800409e: 687b ldr r3, [r7, #4]
|
|
80040a0: 685b ldr r3, [r3, #4]
|
|
80040a2: 009b lsls r3, r3, #2
|
|
80040a4: 429a cmp r2, r3
|
|
80040a6: d1eb bne.n 8004080 <HAL_RCC_ClockConfig+0x114>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80040a8: 687b ldr r3, [r7, #4]
|
|
80040aa: 681b ldr r3, [r3, #0]
|
|
80040ac: f003 0302 and.w r3, r3, #2
|
|
80040b0: 2b00 cmp r3, #0
|
|
80040b2: d023 beq.n 80040fc <HAL_RCC_ClockConfig+0x190>
|
|
{
|
|
/* Set the highest APB divider in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80040b4: 687b ldr r3, [r7, #4]
|
|
80040b6: 681b ldr r3, [r3, #0]
|
|
80040b8: f003 0304 and.w r3, r3, #4
|
|
80040bc: 2b00 cmp r3, #0
|
|
80040be: d005 beq.n 80040cc <HAL_RCC_ClockConfig+0x160>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
80040c0: 4b43 ldr r3, [pc, #268] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
80040c2: 689b ldr r3, [r3, #8]
|
|
80040c4: 4a42 ldr r2, [pc, #264] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
80040c6: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
80040ca: 6093 str r3, [r2, #8]
|
|
}
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80040cc: 687b ldr r3, [r7, #4]
|
|
80040ce: 681b ldr r3, [r3, #0]
|
|
80040d0: f003 0308 and.w r3, r3, #8
|
|
80040d4: 2b00 cmp r3, #0
|
|
80040d6: d007 beq.n 80040e8 <HAL_RCC_ClockConfig+0x17c>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
|
|
80040d8: 4b3d ldr r3, [pc, #244] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
80040da: 689b ldr r3, [r3, #8]
|
|
80040dc: f423 537c bic.w r3, r3, #16128 @ 0x3f00
|
|
80040e0: 4a3b ldr r2, [pc, #236] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
80040e2: f443 63e0 orr.w r3, r3, #1792 @ 0x700
|
|
80040e6: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80040e8: 4b39 ldr r3, [pc, #228] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
80040ea: 689b ldr r3, [r3, #8]
|
|
80040ec: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
80040f0: 687b ldr r3, [r7, #4]
|
|
80040f2: 689b ldr r3, [r3, #8]
|
|
80040f4: 4936 ldr r1, [pc, #216] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
80040f6: 4313 orrs r3, r2
|
|
80040f8: 608b str r3, [r1, #8]
|
|
80040fa: e008 b.n 800410e <HAL_RCC_ClockConfig+0x1a2>
|
|
}
|
|
else
|
|
{
|
|
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
|
|
if(hpre == RCC_SYSCLK_DIV2)
|
|
80040fc: 697b ldr r3, [r7, #20]
|
|
80040fe: 2b80 cmp r3, #128 @ 0x80
|
|
8004100: d105 bne.n 800410e <HAL_RCC_ClockConfig+0x1a2>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
|
|
8004102: 4b33 ldr r3, [pc, #204] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004104: 689b ldr r3, [r3, #8]
|
|
8004106: 4a32 ldr r2, [pc, #200] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004108: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
800410c: 6093 str r3, [r2, #8]
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800410e: 4b2f ldr r3, [pc, #188] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
8004110: 681b ldr r3, [r3, #0]
|
|
8004112: f003 030f and.w r3, r3, #15
|
|
8004116: 683a ldr r2, [r7, #0]
|
|
8004118: 429a cmp r2, r3
|
|
800411a: d21d bcs.n 8004158 <HAL_RCC_ClockConfig+0x1ec>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800411c: 4b2b ldr r3, [pc, #172] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
800411e: 681b ldr r3, [r3, #0]
|
|
8004120: f023 020f bic.w r2, r3, #15
|
|
8004124: 4929 ldr r1, [pc, #164] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
8004126: 683b ldr r3, [r7, #0]
|
|
8004128: 4313 orrs r3, r2
|
|
800412a: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by polling the FLASH_ACR register */
|
|
tickstart = HAL_GetTick();
|
|
800412c: f7fd fb24 bl 8001778 <HAL_GetTick>
|
|
8004130: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8004132: e00a b.n 800414a <HAL_RCC_ClockConfig+0x1de>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8004134: f7fd fb20 bl 8001778 <HAL_GetTick>
|
|
8004138: 4602 mov r2, r0
|
|
800413a: 68fb ldr r3, [r7, #12]
|
|
800413c: 1ad3 subs r3, r2, r3
|
|
800413e: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004142: 4293 cmp r3, r2
|
|
8004144: d901 bls.n 800414a <HAL_RCC_ClockConfig+0x1de>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004146: 2303 movs r3, #3
|
|
8004148: e03b b.n 80041c2 <HAL_RCC_ClockConfig+0x256>
|
|
while (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800414a: 4b20 ldr r3, [pc, #128] @ (80041cc <HAL_RCC_ClockConfig+0x260>)
|
|
800414c: 681b ldr r3, [r3, #0]
|
|
800414e: f003 030f and.w r3, r3, #15
|
|
8004152: 683a ldr r2, [r7, #0]
|
|
8004154: 429a cmp r2, r3
|
|
8004156: d1ed bne.n 8004134 <HAL_RCC_ClockConfig+0x1c8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8004158: 687b ldr r3, [r7, #4]
|
|
800415a: 681b ldr r3, [r3, #0]
|
|
800415c: f003 0304 and.w r3, r3, #4
|
|
8004160: 2b00 cmp r3, #0
|
|
8004162: d008 beq.n 8004176 <HAL_RCC_ClockConfig+0x20a>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8004164: 4b1a ldr r3, [pc, #104] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004166: 689b ldr r3, [r3, #8]
|
|
8004168: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
800416c: 687b ldr r3, [r7, #4]
|
|
800416e: 68db ldr r3, [r3, #12]
|
|
8004170: 4917 ldr r1, [pc, #92] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004172: 4313 orrs r3, r2
|
|
8004174: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8004176: 687b ldr r3, [r7, #4]
|
|
8004178: 681b ldr r3, [r3, #0]
|
|
800417a: f003 0308 and.w r3, r3, #8
|
|
800417e: 2b00 cmp r3, #0
|
|
8004180: d009 beq.n 8004196 <HAL_RCC_ClockConfig+0x22a>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8004182: 4b13 ldr r3, [pc, #76] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004184: 689b ldr r3, [r3, #8]
|
|
8004186: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
800418a: 687b ldr r3, [r7, #4]
|
|
800418c: 691b ldr r3, [r3, #16]
|
|
800418e: 00db lsls r3, r3, #3
|
|
8004190: 490f ldr r1, [pc, #60] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
8004192: 4313 orrs r3, r2
|
|
8004194: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8004196: f000 f825 bl 80041e4 <HAL_RCC_GetSysClockFreq>
|
|
800419a: 4602 mov r2, r0
|
|
800419c: 4b0c ldr r3, [pc, #48] @ (80041d0 <HAL_RCC_ClockConfig+0x264>)
|
|
800419e: 689b ldr r3, [r3, #8]
|
|
80041a0: 091b lsrs r3, r3, #4
|
|
80041a2: f003 030f and.w r3, r3, #15
|
|
80041a6: 490c ldr r1, [pc, #48] @ (80041d8 <HAL_RCC_ClockConfig+0x26c>)
|
|
80041a8: 5ccb ldrb r3, [r1, r3]
|
|
80041aa: f003 031f and.w r3, r3, #31
|
|
80041ae: fa22 f303 lsr.w r3, r2, r3
|
|
80041b2: 4a0a ldr r2, [pc, #40] @ (80041dc <HAL_RCC_ClockConfig+0x270>)
|
|
80041b4: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
return HAL_InitTick(uwTickPrio);
|
|
80041b6: 4b0a ldr r3, [pc, #40] @ (80041e0 <HAL_RCC_ClockConfig+0x274>)
|
|
80041b8: 681b ldr r3, [r3, #0]
|
|
80041ba: 4618 mov r0, r3
|
|
80041bc: f7fd fa90 bl 80016e0 <HAL_InitTick>
|
|
80041c0: 4603 mov r3, r0
|
|
}
|
|
80041c2: 4618 mov r0, r3
|
|
80041c4: 3718 adds r7, #24
|
|
80041c6: 46bd mov sp, r7
|
|
80041c8: bd80 pop {r7, pc}
|
|
80041ca: bf00 nop
|
|
80041cc: 40022000 .word 0x40022000
|
|
80041d0: 40021000 .word 0x40021000
|
|
80041d4: 04c4b400 .word 0x04c4b400
|
|
80041d8: 08008028 .word 0x08008028
|
|
80041dc: 2000001c .word 0x2000001c
|
|
80041e0: 20000020 .word 0x20000020
|
|
|
|
080041e4 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
80041e4: b480 push {r7}
|
|
80041e6: b087 sub sp, #28
|
|
80041e8: af00 add r7, sp, #0
|
|
uint32_t pllvco, pllsource, pllr, pllm;
|
|
uint32_t sysclockfreq;
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
80041ea: 4b2c ldr r3, [pc, #176] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80041ec: 689b ldr r3, [r3, #8]
|
|
80041ee: f003 030c and.w r3, r3, #12
|
|
80041f2: 2b04 cmp r3, #4
|
|
80041f4: d102 bne.n 80041fc <HAL_RCC_GetSysClockFreq+0x18>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
80041f6: 4b2a ldr r3, [pc, #168] @ (80042a0 <HAL_RCC_GetSysClockFreq+0xbc>)
|
|
80041f8: 613b str r3, [r7, #16]
|
|
80041fa: e047 b.n 800428c <HAL_RCC_GetSysClockFreq+0xa8>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
80041fc: 4b27 ldr r3, [pc, #156] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
80041fe: 689b ldr r3, [r3, #8]
|
|
8004200: f003 030c and.w r3, r3, #12
|
|
8004204: 2b08 cmp r3, #8
|
|
8004206: d102 bne.n 800420e <HAL_RCC_GetSysClockFreq+0x2a>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
8004208: 4b26 ldr r3, [pc, #152] @ (80042a4 <HAL_RCC_GetSysClockFreq+0xc0>)
|
|
800420a: 613b str r3, [r7, #16]
|
|
800420c: e03e b.n 800428c <HAL_RCC_GetSysClockFreq+0xa8>
|
|
}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
|
|
800420e: 4b23 ldr r3, [pc, #140] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8004210: 689b ldr r3, [r3, #8]
|
|
8004212: f003 030c and.w r3, r3, #12
|
|
8004216: 2b0c cmp r3, #12
|
|
8004218: d136 bne.n 8004288 <HAL_RCC_GetSysClockFreq+0xa4>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
800421a: 4b20 ldr r3, [pc, #128] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
800421c: 68db ldr r3, [r3, #12]
|
|
800421e: f003 0303 and.w r3, r3, #3
|
|
8004222: 60fb str r3, [r7, #12]
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8004224: 4b1d ldr r3, [pc, #116] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8004226: 68db ldr r3, [r3, #12]
|
|
8004228: 091b lsrs r3, r3, #4
|
|
800422a: f003 030f and.w r3, r3, #15
|
|
800422e: 3301 adds r3, #1
|
|
8004230: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
8004232: 68fb ldr r3, [r7, #12]
|
|
8004234: 2b03 cmp r3, #3
|
|
8004236: d10c bne.n 8004252 <HAL_RCC_GetSysClockFreq+0x6e>
|
|
{
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8004238: 4a1a ldr r2, [pc, #104] @ (80042a4 <HAL_RCC_GetSysClockFreq+0xc0>)
|
|
800423a: 68bb ldr r3, [r7, #8]
|
|
800423c: fbb2 f3f3 udiv r3, r2, r3
|
|
8004240: 4a16 ldr r2, [pc, #88] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
8004242: 68d2 ldr r2, [r2, #12]
|
|
8004244: 0a12 lsrs r2, r2, #8
|
|
8004246: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
800424a: fb02 f303 mul.w r3, r2, r3
|
|
800424e: 617b str r3, [r7, #20]
|
|
break;
|
|
8004250: e00c b.n 800426c <HAL_RCC_GetSysClockFreq+0x88>
|
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
default:
|
|
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8004252: 4a13 ldr r2, [pc, #76] @ (80042a0 <HAL_RCC_GetSysClockFreq+0xbc>)
|
|
8004254: 68bb ldr r3, [r7, #8]
|
|
8004256: fbb2 f3f3 udiv r3, r2, r3
|
|
800425a: 4a10 ldr r2, [pc, #64] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
800425c: 68d2 ldr r2, [r2, #12]
|
|
800425e: 0a12 lsrs r2, r2, #8
|
|
8004260: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
8004264: fb02 f303 mul.w r3, r2, r3
|
|
8004268: 617b str r3, [r7, #20]
|
|
break;
|
|
800426a: bf00 nop
|
|
}
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
800426c: 4b0b ldr r3, [pc, #44] @ (800429c <HAL_RCC_GetSysClockFreq+0xb8>)
|
|
800426e: 68db ldr r3, [r3, #12]
|
|
8004270: 0e5b lsrs r3, r3, #25
|
|
8004272: f003 0303 and.w r3, r3, #3
|
|
8004276: 3301 adds r3, #1
|
|
8004278: 005b lsls r3, r3, #1
|
|
800427a: 607b str r3, [r7, #4]
|
|
sysclockfreq = pllvco/pllr;
|
|
800427c: 697a ldr r2, [r7, #20]
|
|
800427e: 687b ldr r3, [r7, #4]
|
|
8004280: fbb2 f3f3 udiv r3, r2, r3
|
|
8004284: 613b str r3, [r7, #16]
|
|
8004286: e001 b.n 800428c <HAL_RCC_GetSysClockFreq+0xa8>
|
|
}
|
|
else
|
|
{
|
|
sysclockfreq = 0U;
|
|
8004288: 2300 movs r3, #0
|
|
800428a: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
800428c: 693b ldr r3, [r7, #16]
|
|
}
|
|
800428e: 4618 mov r0, r3
|
|
8004290: 371c adds r7, #28
|
|
8004292: 46bd mov sp, r7
|
|
8004294: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004298: 4770 bx lr
|
|
800429a: bf00 nop
|
|
800429c: 40021000 .word 0x40021000
|
|
80042a0: 00f42400 .word 0x00f42400
|
|
80042a4: 007a1200 .word 0x007a1200
|
|
|
|
080042a8 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
80042a8: b480 push {r7}
|
|
80042aa: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
80042ac: 4b03 ldr r3, [pc, #12] @ (80042bc <HAL_RCC_GetHCLKFreq+0x14>)
|
|
80042ae: 681b ldr r3, [r3, #0]
|
|
}
|
|
80042b0: 4618 mov r0, r3
|
|
80042b2: 46bd mov sp, r7
|
|
80042b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80042b8: 4770 bx lr
|
|
80042ba: bf00 nop
|
|
80042bc: 2000001c .word 0x2000001c
|
|
|
|
080042c0 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80042c0: b580 push {r7, lr}
|
|
80042c2: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
80042c4: f7ff fff0 bl 80042a8 <HAL_RCC_GetHCLKFreq>
|
|
80042c8: 4602 mov r2, r0
|
|
80042ca: 4b06 ldr r3, [pc, #24] @ (80042e4 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
80042cc: 689b ldr r3, [r3, #8]
|
|
80042ce: 0a1b lsrs r3, r3, #8
|
|
80042d0: f003 0307 and.w r3, r3, #7
|
|
80042d4: 4904 ldr r1, [pc, #16] @ (80042e8 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
80042d6: 5ccb ldrb r3, [r1, r3]
|
|
80042d8: f003 031f and.w r3, r3, #31
|
|
80042dc: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80042e0: 4618 mov r0, r3
|
|
80042e2: bd80 pop {r7, pc}
|
|
80042e4: 40021000 .word 0x40021000
|
|
80042e8: 08008038 .word 0x08008038
|
|
|
|
080042ec <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
80042ec: b580 push {r7, lr}
|
|
80042ee: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
80042f0: f7ff ffda bl 80042a8 <HAL_RCC_GetHCLKFreq>
|
|
80042f4: 4602 mov r2, r0
|
|
80042f6: 4b06 ldr r3, [pc, #24] @ (8004310 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80042f8: 689b ldr r3, [r3, #8]
|
|
80042fa: 0adb lsrs r3, r3, #11
|
|
80042fc: f003 0307 and.w r3, r3, #7
|
|
8004300: 4904 ldr r1, [pc, #16] @ (8004314 <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
8004302: 5ccb ldrb r3, [r1, r3]
|
|
8004304: f003 031f and.w r3, r3, #31
|
|
8004308: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
800430c: 4618 mov r0, r3
|
|
800430e: bd80 pop {r7, pc}
|
|
8004310: 40021000 .word 0x40021000
|
|
8004314: 08008038 .word 0x08008038
|
|
|
|
08004318 <RCC_GetSysClockFreqFromPLLSource>:
|
|
/**
|
|
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
|
|
{
|
|
8004318: b480 push {r7}
|
|
800431a: b087 sub sp, #28
|
|
800431c: af00 add r7, sp, #0
|
|
uint32_t sysclockfreq;
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
800431e: 4b1e ldr r3, [pc, #120] @ (8004398 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8004320: 68db ldr r3, [r3, #12]
|
|
8004322: f003 0303 and.w r3, r3, #3
|
|
8004326: 613b str r3, [r7, #16]
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8004328: 4b1b ldr r3, [pc, #108] @ (8004398 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
800432a: 68db ldr r3, [r3, #12]
|
|
800432c: 091b lsrs r3, r3, #4
|
|
800432e: f003 030f and.w r3, r3, #15
|
|
8004332: 3301 adds r3, #1
|
|
8004334: 60fb str r3, [r7, #12]
|
|
|
|
switch (pllsource)
|
|
8004336: 693b ldr r3, [r7, #16]
|
|
8004338: 2b03 cmp r3, #3
|
|
800433a: d10c bne.n 8004356 <RCC_GetSysClockFreqFromPLLSource+0x3e>
|
|
{
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
800433c: 4a17 ldr r2, [pc, #92] @ (800439c <RCC_GetSysClockFreqFromPLLSource+0x84>)
|
|
800433e: 68fb ldr r3, [r7, #12]
|
|
8004340: fbb2 f3f3 udiv r3, r2, r3
|
|
8004344: 4a14 ldr r2, [pc, #80] @ (8004398 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8004346: 68d2 ldr r2, [r2, #12]
|
|
8004348: 0a12 lsrs r2, r2, #8
|
|
800434a: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
800434e: fb02 f303 mul.w r3, r2, r3
|
|
8004352: 617b str r3, [r7, #20]
|
|
break;
|
|
8004354: e00c b.n 8004370 <RCC_GetSysClockFreqFromPLLSource+0x58>
|
|
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
default:
|
|
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
|
8004356: 4a12 ldr r2, [pc, #72] @ (80043a0 <RCC_GetSysClockFreqFromPLLSource+0x88>)
|
|
8004358: 68fb ldr r3, [r7, #12]
|
|
800435a: fbb2 f3f3 udiv r3, r2, r3
|
|
800435e: 4a0e ldr r2, [pc, #56] @ (8004398 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8004360: 68d2 ldr r2, [r2, #12]
|
|
8004362: 0a12 lsrs r2, r2, #8
|
|
8004364: f002 027f and.w r2, r2, #127 @ 0x7f
|
|
8004368: fb02 f303 mul.w r3, r2, r3
|
|
800436c: 617b str r3, [r7, #20]
|
|
break;
|
|
800436e: bf00 nop
|
|
}
|
|
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
8004370: 4b09 ldr r3, [pc, #36] @ (8004398 <RCC_GetSysClockFreqFromPLLSource+0x80>)
|
|
8004372: 68db ldr r3, [r3, #12]
|
|
8004374: 0e5b lsrs r3, r3, #25
|
|
8004376: f003 0303 and.w r3, r3, #3
|
|
800437a: 3301 adds r3, #1
|
|
800437c: 005b lsls r3, r3, #1
|
|
800437e: 60bb str r3, [r7, #8]
|
|
sysclockfreq = pllvco/pllr;
|
|
8004380: 697a ldr r2, [r7, #20]
|
|
8004382: 68bb ldr r3, [r7, #8]
|
|
8004384: fbb2 f3f3 udiv r3, r2, r3
|
|
8004388: 607b str r3, [r7, #4]
|
|
|
|
return sysclockfreq;
|
|
800438a: 687b ldr r3, [r7, #4]
|
|
}
|
|
800438c: 4618 mov r0, r3
|
|
800438e: 371c adds r7, #28
|
|
8004390: 46bd mov sp, r7
|
|
8004392: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004396: 4770 bx lr
|
|
8004398: 40021000 .word 0x40021000
|
|
800439c: 007a1200 .word 0x007a1200
|
|
80043a0: 00f42400 .word 0x00f42400
|
|
|
|
080043a4 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80043a4: b580 push {r7, lr}
|
|
80043a6: b086 sub sp, #24
|
|
80043a8: af00 add r7, sp, #0
|
|
80043aa: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister;
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
80043ac: 2300 movs r3, #0
|
|
80043ae: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
80043b0: 2300 movs r3, #0
|
|
80043b2: 74bb strb r3, [r7, #18]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
80043b4: 687b ldr r3, [r7, #4]
|
|
80043b6: 681b ldr r3, [r3, #0]
|
|
80043b8: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80043bc: 2b00 cmp r3, #0
|
|
80043be: f000 8098 beq.w 80044f2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
80043c2: 2300 movs r3, #0
|
|
80043c4: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
80043c6: 4b43 ldr r3, [pc, #268] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80043c8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80043ce: 2b00 cmp r3, #0
|
|
80043d0: d10d bne.n 80043ee <HAL_RCCEx_PeriphCLKConfig+0x4a>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80043d2: 4b40 ldr r3, [pc, #256] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80043d4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043d6: 4a3f ldr r2, [pc, #252] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80043d8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80043dc: 6593 str r3, [r2, #88] @ 0x58
|
|
80043de: 4b3d ldr r3, [pc, #244] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80043e0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043e2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80043e6: 60bb str r3, [r7, #8]
|
|
80043e8: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
80043ea: 2301 movs r3, #1
|
|
80043ec: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80043ee: 4b3a ldr r3, [pc, #232] @ (80044d8 <HAL_RCCEx_PeriphCLKConfig+0x134>)
|
|
80043f0: 681b ldr r3, [r3, #0]
|
|
80043f2: 4a39 ldr r2, [pc, #228] @ (80044d8 <HAL_RCCEx_PeriphCLKConfig+0x134>)
|
|
80043f4: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80043f8: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80043fa: f7fd f9bd bl 8001778 <HAL_GetTick>
|
|
80043fe: 60f8 str r0, [r7, #12]
|
|
|
|
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
|
|
8004400: e009 b.n 8004416 <HAL_RCCEx_PeriphCLKConfig+0x72>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004402: f7fd f9b9 bl 8001778 <HAL_GetTick>
|
|
8004406: 4602 mov r2, r0
|
|
8004408: 68fb ldr r3, [r7, #12]
|
|
800440a: 1ad3 subs r3, r2, r3
|
|
800440c: 2b02 cmp r3, #2
|
|
800440e: d902 bls.n 8004416 <HAL_RCCEx_PeriphCLKConfig+0x72>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8004410: 2303 movs r3, #3
|
|
8004412: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8004414: e005 b.n 8004422 <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
|
|
8004416: 4b30 ldr r3, [pc, #192] @ (80044d8 <HAL_RCCEx_PeriphCLKConfig+0x134>)
|
|
8004418: 681b ldr r3, [r3, #0]
|
|
800441a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800441e: 2b00 cmp r3, #0
|
|
8004420: d0ef beq.n 8004402 <HAL_RCCEx_PeriphCLKConfig+0x5e>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8004422: 7cfb ldrb r3, [r7, #19]
|
|
8004424: 2b00 cmp r3, #0
|
|
8004426: d159 bne.n 80044dc <HAL_RCCEx_PeriphCLKConfig+0x138>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
8004428: 4b2a ldr r3, [pc, #168] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
800442a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800442e: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004432: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
8004434: 697b ldr r3, [r7, #20]
|
|
8004436: 2b00 cmp r3, #0
|
|
8004438: d01e beq.n 8004478 <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
800443a: 687b ldr r3, [r7, #4]
|
|
800443c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800443e: 697a ldr r2, [r7, #20]
|
|
8004440: 429a cmp r2, r3
|
|
8004442: d019 beq.n 8004478 <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
8004444: 4b23 ldr r3, [pc, #140] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8004446: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800444a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800444e: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8004450: 4b20 ldr r3, [pc, #128] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8004452: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004456: 4a1f ldr r2, [pc, #124] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8004458: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800445c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8004460: 4b1c ldr r3, [pc, #112] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8004462: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004466: 4a1b ldr r2, [pc, #108] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8004468: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800446c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8004470: 4a18 ldr r2, [pc, #96] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
8004472: 697b ldr r3, [r7, #20]
|
|
8004474: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8004478: 697b ldr r3, [r7, #20]
|
|
800447a: f003 0301 and.w r3, r3, #1
|
|
800447e: 2b00 cmp r3, #0
|
|
8004480: d016 beq.n 80044b0 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004482: f7fd f979 bl 8001778 <HAL_GetTick>
|
|
8004486: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8004488: e00b b.n 80044a2 <HAL_RCCEx_PeriphCLKConfig+0xfe>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800448a: f7fd f975 bl 8001778 <HAL_GetTick>
|
|
800448e: 4602 mov r2, r0
|
|
8004490: 68fb ldr r3, [r7, #12]
|
|
8004492: 1ad3 subs r3, r2, r3
|
|
8004494: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004498: 4293 cmp r3, r2
|
|
800449a: d902 bls.n 80044a2 <HAL_RCCEx_PeriphCLKConfig+0xfe>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
800449c: 2303 movs r3, #3
|
|
800449e: 74fb strb r3, [r7, #19]
|
|
break;
|
|
80044a0: e006 b.n 80044b0 <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
80044a2: 4b0c ldr r3, [pc, #48] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80044a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80044a8: f003 0302 and.w r3, r3, #2
|
|
80044ac: 2b00 cmp r3, #0
|
|
80044ae: d0ec beq.n 800448a <HAL_RCCEx_PeriphCLKConfig+0xe6>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
80044b0: 7cfb ldrb r3, [r7, #19]
|
|
80044b2: 2b00 cmp r3, #0
|
|
80044b4: d10b bne.n 80044ce <HAL_RCCEx_PeriphCLKConfig+0x12a>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80044b6: 4b07 ldr r3, [pc, #28] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80044b8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80044bc: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
80044c0: 687b ldr r3, [r7, #4]
|
|
80044c2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80044c4: 4903 ldr r1, [pc, #12] @ (80044d4 <HAL_RCCEx_PeriphCLKConfig+0x130>)
|
|
80044c6: 4313 orrs r3, r2
|
|
80044c8: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
80044cc: e008 b.n 80044e0 <HAL_RCCEx_PeriphCLKConfig+0x13c>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80044ce: 7cfb ldrb r3, [r7, #19]
|
|
80044d0: 74bb strb r3, [r7, #18]
|
|
80044d2: e005 b.n 80044e0 <HAL_RCCEx_PeriphCLKConfig+0x13c>
|
|
80044d4: 40021000 .word 0x40021000
|
|
80044d8: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80044dc: 7cfb ldrb r3, [r7, #19]
|
|
80044de: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
80044e0: 7c7b ldrb r3, [r7, #17]
|
|
80044e2: 2b01 cmp r3, #1
|
|
80044e4: d105 bne.n 80044f2 <HAL_RCCEx_PeriphCLKConfig+0x14e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80044e6: 4ba6 ldr r3, [pc, #664] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80044e8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80044ea: 4aa5 ldr r2, [pc, #660] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80044ec: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80044f0: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
80044f2: 687b ldr r3, [r7, #4]
|
|
80044f4: 681b ldr r3, [r3, #0]
|
|
80044f6: f003 0301 and.w r3, r3, #1
|
|
80044fa: 2b00 cmp r3, #0
|
|
80044fc: d00a beq.n 8004514 <HAL_RCCEx_PeriphCLKConfig+0x170>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
80044fe: 4ba0 ldr r3, [pc, #640] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004500: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004504: f023 0203 bic.w r2, r3, #3
|
|
8004508: 687b ldr r3, [r7, #4]
|
|
800450a: 685b ldr r3, [r3, #4]
|
|
800450c: 499c ldr r1, [pc, #624] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800450e: 4313 orrs r3, r2
|
|
8004510: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8004514: 687b ldr r3, [r7, #4]
|
|
8004516: 681b ldr r3, [r3, #0]
|
|
8004518: f003 0302 and.w r3, r3, #2
|
|
800451c: 2b00 cmp r3, #0
|
|
800451e: d00a beq.n 8004536 <HAL_RCCEx_PeriphCLKConfig+0x192>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
8004520: 4b97 ldr r3, [pc, #604] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004522: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004526: f023 020c bic.w r2, r3, #12
|
|
800452a: 687b ldr r3, [r7, #4]
|
|
800452c: 689b ldr r3, [r3, #8]
|
|
800452e: 4994 ldr r1, [pc, #592] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004530: 4313 orrs r3, r2
|
|
8004532: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
8004536: 687b ldr r3, [r7, #4]
|
|
8004538: 681b ldr r3, [r3, #0]
|
|
800453a: f003 0304 and.w r3, r3, #4
|
|
800453e: 2b00 cmp r3, #0
|
|
8004540: d00a beq.n 8004558 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
8004542: 4b8f ldr r3, [pc, #572] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004544: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004548: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
800454c: 687b ldr r3, [r7, #4]
|
|
800454e: 68db ldr r3, [r3, #12]
|
|
8004550: 498b ldr r1, [pc, #556] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004552: 4313 orrs r3, r2
|
|
8004554: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
8004558: 687b ldr r3, [r7, #4]
|
|
800455a: 681b ldr r3, [r3, #0]
|
|
800455c: f003 0308 and.w r3, r3, #8
|
|
8004560: 2b00 cmp r3, #0
|
|
8004562: d00a beq.n 800457a <HAL_RCCEx_PeriphCLKConfig+0x1d6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
8004564: 4b86 ldr r3, [pc, #536] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004566: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800456a: f023 02c0 bic.w r2, r3, #192 @ 0xc0
|
|
800456e: 687b ldr r3, [r7, #4]
|
|
8004570: 691b ldr r3, [r3, #16]
|
|
8004572: 4983 ldr r1, [pc, #524] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004574: 4313 orrs r3, r2
|
|
8004576: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
800457a: 687b ldr r3, [r7, #4]
|
|
800457c: 681b ldr r3, [r3, #0]
|
|
800457e: f003 0320 and.w r3, r3, #32
|
|
8004582: 2b00 cmp r3, #0
|
|
8004584: d00a beq.n 800459c <HAL_RCCEx_PeriphCLKConfig+0x1f8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUAR1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
8004586: 4b7e ldr r3, [pc, #504] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004588: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800458c: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
8004590: 687b ldr r3, [r7, #4]
|
|
8004592: 695b ldr r3, [r3, #20]
|
|
8004594: 497a ldr r1, [pc, #488] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004596: 4313 orrs r3, r2
|
|
8004598: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
800459c: 687b ldr r3, [r7, #4]
|
|
800459e: 681b ldr r3, [r3, #0]
|
|
80045a0: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80045a4: 2b00 cmp r3, #0
|
|
80045a6: d00a beq.n 80045be <HAL_RCCEx_PeriphCLKConfig+0x21a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
80045a8: 4b75 ldr r3, [pc, #468] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80045aa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80045ae: f423 5240 bic.w r2, r3, #12288 @ 0x3000
|
|
80045b2: 687b ldr r3, [r7, #4]
|
|
80045b4: 699b ldr r3, [r3, #24]
|
|
80045b6: 4972 ldr r1, [pc, #456] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80045b8: 4313 orrs r3, r2
|
|
80045ba: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
80045be: 687b ldr r3, [r7, #4]
|
|
80045c0: 681b ldr r3, [r3, #0]
|
|
80045c2: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80045c6: 2b00 cmp r3, #0
|
|
80045c8: d00a beq.n 80045e0 <HAL_RCCEx_PeriphCLKConfig+0x23c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
80045ca: 4b6d ldr r3, [pc, #436] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80045cc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80045d0: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
80045d4: 687b ldr r3, [r7, #4]
|
|
80045d6: 69db ldr r3, [r3, #28]
|
|
80045d8: 4969 ldr r1, [pc, #420] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80045da: 4313 orrs r3, r2
|
|
80045dc: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
#if defined(I2C3)
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
80045e0: 687b ldr r3, [r7, #4]
|
|
80045e2: 681b ldr r3, [r3, #0]
|
|
80045e4: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80045e8: 2b00 cmp r3, #0
|
|
80045ea: d00a beq.n 8004602 <HAL_RCCEx_PeriphCLKConfig+0x25e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
80045ec: 4b64 ldr r3, [pc, #400] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80045ee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80045f2: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
80045f6: 687b ldr r3, [r7, #4]
|
|
80045f8: 6a1b ldr r3, [r3, #32]
|
|
80045fa: 4961 ldr r1, [pc, #388] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80045fc: 4313 orrs r3, r2
|
|
80045fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* I2C4 */
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
|
|
8004602: 687b ldr r3, [r7, #4]
|
|
8004604: 681b ldr r3, [r3, #0]
|
|
8004606: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
800460a: 2b00 cmp r3, #0
|
|
800460c: d00a beq.n 8004624 <HAL_RCCEx_PeriphCLKConfig+0x280>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
|
|
|
|
/* Configure the LPTIM1 clock source */
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
800460e: 4b5c ldr r3, [pc, #368] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004610: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004614: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
8004618: 687b ldr r3, [r7, #4]
|
|
800461a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800461c: 4958 ldr r1, [pc, #352] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800461e: 4313 orrs r3, r2
|
|
8004620: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(SAI1)
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
|
|
8004624: 687b ldr r3, [r7, #4]
|
|
8004626: 681b ldr r3, [r3, #0]
|
|
8004628: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800462c: 2b00 cmp r3, #0
|
|
800462e: d015 beq.n 800465c <HAL_RCCEx_PeriphCLKConfig+0x2b8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure the SAI1 interface clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8004630: 4b53 ldr r3, [pc, #332] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004632: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004636: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
800463a: 687b ldr r3, [r7, #4]
|
|
800463c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800463e: 4950 ldr r1, [pc, #320] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004640: 4313 orrs r3, r2
|
|
8004642: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
|
|
8004646: 687b ldr r3, [r7, #4]
|
|
8004648: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800464a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
800464e: d105 bne.n 800465c <HAL_RCCEx_PeriphCLKConfig+0x2b8>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8004650: 4b4b ldr r3, [pc, #300] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004652: 68db ldr r3, [r3, #12]
|
|
8004654: 4a4a ldr r2, [pc, #296] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004656: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
800465a: 60d3 str r3, [r2, #12]
|
|
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SPI_I2S_SUPPORT)
|
|
/*-------------------------- I2S clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
|
|
800465c: 687b ldr r3, [r7, #4]
|
|
800465e: 681b ldr r3, [r3, #0]
|
|
8004660: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8004664: 2b00 cmp r3, #0
|
|
8004666: d015 beq.n 8004694 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
|
|
|
|
/* Configure the I2S interface clock source */
|
|
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
|
|
8004668: 4b45 ldr r3, [pc, #276] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800466a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800466e: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
8004672: 687b ldr r3, [r7, #4]
|
|
8004674: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004676: 4942 ldr r1, [pc, #264] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004678: 4313 orrs r3, r2
|
|
800467a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
|
|
800467e: 687b ldr r3, [r7, #4]
|
|
8004680: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004682: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8004686: d105 bne.n 8004694 <HAL_RCCEx_PeriphCLKConfig+0x2f0>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8004688: 4b3d ldr r3, [pc, #244] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800468a: 68db ldr r3, [r3, #12]
|
|
800468c: 4a3c ldr r2, [pc, #240] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800468e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8004692: 60d3 str r3, [r2, #12]
|
|
|
|
#endif /* SPI_I2S_SUPPORT */
|
|
|
|
#if defined(FDCAN1)
|
|
/*-------------------------- FDCAN clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
|
|
8004694: 687b ldr r3, [r7, #4]
|
|
8004696: 681b ldr r3, [r3, #0]
|
|
8004698: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
800469c: 2b00 cmp r3, #0
|
|
800469e: d015 beq.n 80046cc <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
|
|
|
|
/* Configure the FDCAN interface clock source */
|
|
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
|
|
80046a0: 4b37 ldr r3, [pc, #220] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046a2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80046a6: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
|
|
80046aa: 687b ldr r3, [r7, #4]
|
|
80046ac: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80046ae: 4934 ldr r1, [pc, #208] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046b0: 4313 orrs r3, r2
|
|
80046b2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
|
|
80046b6: 687b ldr r3, [r7, #4]
|
|
80046b8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80046ba: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80046be: d105 bne.n 80046cc <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
80046c0: 4b2f ldr r3, [pc, #188] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046c2: 68db ldr r3, [r3, #12]
|
|
80046c4: 4a2e ldr r2, [pc, #184] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046c6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80046ca: 60d3 str r3, [r2, #12]
|
|
#endif /* FDCAN1 */
|
|
|
|
#if defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
80046cc: 687b ldr r3, [r7, #4]
|
|
80046ce: 681b ldr r3, [r3, #0]
|
|
80046d0: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
80046d4: 2b00 cmp r3, #0
|
|
80046d6: d015 beq.n 8004704 <HAL_RCCEx_PeriphCLKConfig+0x360>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
80046d8: 4b29 ldr r3, [pc, #164] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046da: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80046de: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
80046e2: 687b ldr r3, [r7, #4]
|
|
80046e4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80046e6: 4926 ldr r1, [pc, #152] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046e8: 4313 orrs r3, r2
|
|
80046ea: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
80046ee: 687b ldr r3, [r7, #4]
|
|
80046f0: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80046f2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
80046f6: d105 bne.n 8004704 <HAL_RCCEx_PeriphCLKConfig+0x360>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
80046f8: 4b21 ldr r3, [pc, #132] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046fa: 68db ldr r3, [r3, #12]
|
|
80046fc: 4a20 ldr r2, [pc, #128] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
80046fe: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8004702: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
#endif /* USB */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8004704: 687b ldr r3, [r7, #4]
|
|
8004706: 681b ldr r3, [r3, #0]
|
|
8004708: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800470c: 2b00 cmp r3, #0
|
|
800470e: d015 beq.n 800473c <HAL_RCCEx_PeriphCLKConfig+0x398>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
8004710: 4b1b ldr r3, [pc, #108] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004712: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004716: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
800471a: 687b ldr r3, [r7, #4]
|
|
800471c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800471e: 4918 ldr r1, [pc, #96] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004720: 4313 orrs r3, r2
|
|
8004722: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8004726: 687b ldr r3, [r7, #4]
|
|
8004728: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800472a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800472e: d105 bne.n 800473c <HAL_RCCEx_PeriphCLKConfig+0x398>
|
|
{
|
|
/* Enable PLL48M1CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8004730: 4b13 ldr r3, [pc, #76] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004732: 68db ldr r3, [r3, #12]
|
|
8004734: 4a12 ldr r2, [pc, #72] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004736: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
800473a: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC12 clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
|
|
800473c: 687b ldr r3, [r7, #4]
|
|
800473e: 681b ldr r3, [r3, #0]
|
|
8004740: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8004744: 2b00 cmp r3, #0
|
|
8004746: d015 beq.n 8004774 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
|
|
|
|
/* Configure the ADC12 interface clock source */
|
|
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
|
|
8004748: 4b0d ldr r3, [pc, #52] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800474a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800474e: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
8004752: 687b ldr r3, [r7, #4]
|
|
8004754: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004756: 490a ldr r1, [pc, #40] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
8004758: 4313 orrs r3, r2
|
|
800475a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
|
|
800475e: 687b ldr r3, [r7, #4]
|
|
8004760: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8004762: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8004766: d105 bne.n 8004774 <HAL_RCCEx_PeriphCLKConfig+0x3d0>
|
|
{
|
|
/* Enable PLLADCCLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
|
|
8004768: 4b05 ldr r3, [pc, #20] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800476a: 68db ldr r3, [r3, #12]
|
|
800476c: 4a04 ldr r2, [pc, #16] @ (8004780 <HAL_RCCEx_PeriphCLKConfig+0x3dc>)
|
|
800476e: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004772: 60d3 str r3, [r2, #12]
|
|
}
|
|
}
|
|
|
|
#endif /* QUADSPI */
|
|
|
|
return status;
|
|
8004774: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8004776: 4618 mov r0, r3
|
|
8004778: 3718 adds r7, #24
|
|
800477a: 46bd mov sp, r7
|
|
800477c: bd80 pop {r7, pc}
|
|
800477e: bf00 nop
|
|
8004780: 40021000 .word 0x40021000
|
|
|
|
08004784 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004784: b580 push {r7, lr}
|
|
8004786: b082 sub sp, #8
|
|
8004788: af00 add r7, sp, #0
|
|
800478a: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 2b00 cmp r3, #0
|
|
8004790: d101 bne.n 8004796 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004792: 2301 movs r3, #1
|
|
8004794: e049 b.n 800482a <HAL_TIM_Base_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8004796: 687b ldr r3, [r7, #4]
|
|
8004798: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800479c: b2db uxtb r3, r3
|
|
800479e: 2b00 cmp r3, #0
|
|
80047a0: d106 bne.n 80047b0 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
80047a2: 687b ldr r3, [r7, #4]
|
|
80047a4: 2200 movs r2, #0
|
|
80047a6: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
80047aa: 6878 ldr r0, [r7, #4]
|
|
80047ac: f7fc fe30 bl 8001410 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80047b0: 687b ldr r3, [r7, #4]
|
|
80047b2: 2202 movs r2, #2
|
|
80047b4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
80047b8: 687b ldr r3, [r7, #4]
|
|
80047ba: 681a ldr r2, [r3, #0]
|
|
80047bc: 687b ldr r3, [r7, #4]
|
|
80047be: 3304 adds r3, #4
|
|
80047c0: 4619 mov r1, r3
|
|
80047c2: 4610 mov r0, r2
|
|
80047c4: f000 fd26 bl 8005214 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
80047c8: 687b ldr r3, [r7, #4]
|
|
80047ca: 2201 movs r2, #1
|
|
80047cc: f883 2048 strb.w r2, [r3, #72] @ 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80047d0: 687b ldr r3, [r7, #4]
|
|
80047d2: 2201 movs r2, #1
|
|
80047d4: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
80047d8: 687b ldr r3, [r7, #4]
|
|
80047da: 2201 movs r2, #1
|
|
80047dc: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
80047e0: 687b ldr r3, [r7, #4]
|
|
80047e2: 2201 movs r2, #1
|
|
80047e4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80047e8: 687b ldr r3, [r7, #4]
|
|
80047ea: 2201 movs r2, #1
|
|
80047ec: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
80047f0: 687b ldr r3, [r7, #4]
|
|
80047f2: 2201 movs r2, #1
|
|
80047f4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80047f8: 687b ldr r3, [r7, #4]
|
|
80047fa: 2201 movs r2, #1
|
|
80047fc: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8004800: 687b ldr r3, [r7, #4]
|
|
8004802: 2201 movs r2, #1
|
|
8004804: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8004808: 687b ldr r3, [r7, #4]
|
|
800480a: 2201 movs r2, #1
|
|
800480c: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
8004810: 687b ldr r3, [r7, #4]
|
|
8004812: 2201 movs r2, #1
|
|
8004814: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
8004818: 687b ldr r3, [r7, #4]
|
|
800481a: 2201 movs r2, #1
|
|
800481c: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8004820: 687b ldr r3, [r7, #4]
|
|
8004822: 2201 movs r2, #1
|
|
8004824: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8004828: 2300 movs r3, #0
|
|
}
|
|
800482a: 4618 mov r0, r3
|
|
800482c: 3708 adds r7, #8
|
|
800482e: 46bd mov sp, r7
|
|
8004830: bd80 pop {r7, pc}
|
|
|
|
08004832 <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004832: b580 push {r7, lr}
|
|
8004834: b082 sub sp, #8
|
|
8004836: af00 add r7, sp, #0
|
|
8004838: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800483a: 687b ldr r3, [r7, #4]
|
|
800483c: 2b00 cmp r3, #0
|
|
800483e: d101 bne.n 8004844 <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004840: 2301 movs r3, #1
|
|
8004842: e049 b.n 80048d8 <HAL_TIM_PWM_Init+0xa6>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8004844: 687b ldr r3, [r7, #4]
|
|
8004846: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
800484a: b2db uxtb r3, r3
|
|
800484c: 2b00 cmp r3, #0
|
|
800484e: d106 bne.n 800485e <HAL_TIM_PWM_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8004850: 687b ldr r3, [r7, #4]
|
|
8004852: 2200 movs r2, #0
|
|
8004854: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
8004858: 6878 ldr r0, [r7, #4]
|
|
800485a: f000 f841 bl 80048e0 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800485e: 687b ldr r3, [r7, #4]
|
|
8004860: 2202 movs r2, #2
|
|
8004862: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8004866: 687b ldr r3, [r7, #4]
|
|
8004868: 681a ldr r2, [r3, #0]
|
|
800486a: 687b ldr r3, [r7, #4]
|
|
800486c: 3304 adds r3, #4
|
|
800486e: 4619 mov r1, r3
|
|
8004870: 4610 mov r0, r2
|
|
8004872: f000 fccf bl 8005214 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8004876: 687b ldr r3, [r7, #4]
|
|
8004878: 2201 movs r2, #1
|
|
800487a: f883 2048 strb.w r2, [r3, #72] @ 0x48
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
800487e: 687b ldr r3, [r7, #4]
|
|
8004880: 2201 movs r2, #1
|
|
8004882: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8004886: 687b ldr r3, [r7, #4]
|
|
8004888: 2201 movs r2, #1
|
|
800488a: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
800488e: 687b ldr r3, [r7, #4]
|
|
8004890: 2201 movs r2, #1
|
|
8004892: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8004896: 687b ldr r3, [r7, #4]
|
|
8004898: 2201 movs r2, #1
|
|
800489a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
800489e: 687b ldr r3, [r7, #4]
|
|
80048a0: 2201 movs r2, #1
|
|
80048a2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80048a6: 687b ldr r3, [r7, #4]
|
|
80048a8: 2201 movs r2, #1
|
|
80048aa: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80048ae: 687b ldr r3, [r7, #4]
|
|
80048b0: 2201 movs r2, #1
|
|
80048b2: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
80048b6: 687b ldr r3, [r7, #4]
|
|
80048b8: 2201 movs r2, #1
|
|
80048ba: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
80048be: 687b ldr r3, [r7, #4]
|
|
80048c0: 2201 movs r2, #1
|
|
80048c2: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
80048c6: 687b ldr r3, [r7, #4]
|
|
80048c8: 2201 movs r2, #1
|
|
80048ca: f883 2047 strb.w r2, [r3, #71] @ 0x47
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80048ce: 687b ldr r3, [r7, #4]
|
|
80048d0: 2201 movs r2, #1
|
|
80048d2: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80048d6: 2300 movs r3, #0
|
|
}
|
|
80048d8: 4618 mov r0, r3
|
|
80048da: 3708 adds r7, #8
|
|
80048dc: 46bd mov sp, r7
|
|
80048de: bd80 pop {r7, pc}
|
|
|
|
080048e0 <HAL_TIM_PWM_MspInit>:
|
|
* @brief Initializes the TIM PWM MSP.
|
|
* @param htim TIM PWM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
80048e0: b480 push {r7}
|
|
80048e2: b083 sub sp, #12
|
|
80048e4: af00 add r7, sp, #0
|
|
80048e6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
80048e8: bf00 nop
|
|
80048ea: 370c adds r7, #12
|
|
80048ec: 46bd mov sp, r7
|
|
80048ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80048f2: 4770 bx lr
|
|
|
|
080048f4 <HAL_TIM_PWM_Start>:
|
|
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
|
|
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
{
|
|
80048f4: b580 push {r7, lr}
|
|
80048f6: b084 sub sp, #16
|
|
80048f8: af00 add r7, sp, #0
|
|
80048fa: 6078 str r0, [r7, #4]
|
|
80048fc: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
|
|
|
/* Check the TIM channel state */
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
80048fe: 683b ldr r3, [r7, #0]
|
|
8004900: 2b00 cmp r3, #0
|
|
8004902: d109 bne.n 8004918 <HAL_TIM_PWM_Start+0x24>
|
|
8004904: 687b ldr r3, [r7, #4]
|
|
8004906: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
|
|
800490a: b2db uxtb r3, r3
|
|
800490c: 2b01 cmp r3, #1
|
|
800490e: bf14 ite ne
|
|
8004910: 2301 movne r3, #1
|
|
8004912: 2300 moveq r3, #0
|
|
8004914: b2db uxtb r3, r3
|
|
8004916: e03c b.n 8004992 <HAL_TIM_PWM_Start+0x9e>
|
|
8004918: 683b ldr r3, [r7, #0]
|
|
800491a: 2b04 cmp r3, #4
|
|
800491c: d109 bne.n 8004932 <HAL_TIM_PWM_Start+0x3e>
|
|
800491e: 687b ldr r3, [r7, #4]
|
|
8004920: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
|
|
8004924: b2db uxtb r3, r3
|
|
8004926: 2b01 cmp r3, #1
|
|
8004928: bf14 ite ne
|
|
800492a: 2301 movne r3, #1
|
|
800492c: 2300 moveq r3, #0
|
|
800492e: b2db uxtb r3, r3
|
|
8004930: e02f b.n 8004992 <HAL_TIM_PWM_Start+0x9e>
|
|
8004932: 683b ldr r3, [r7, #0]
|
|
8004934: 2b08 cmp r3, #8
|
|
8004936: d109 bne.n 800494c <HAL_TIM_PWM_Start+0x58>
|
|
8004938: 687b ldr r3, [r7, #4]
|
|
800493a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800493e: b2db uxtb r3, r3
|
|
8004940: 2b01 cmp r3, #1
|
|
8004942: bf14 ite ne
|
|
8004944: 2301 movne r3, #1
|
|
8004946: 2300 moveq r3, #0
|
|
8004948: b2db uxtb r3, r3
|
|
800494a: e022 b.n 8004992 <HAL_TIM_PWM_Start+0x9e>
|
|
800494c: 683b ldr r3, [r7, #0]
|
|
800494e: 2b0c cmp r3, #12
|
|
8004950: d109 bne.n 8004966 <HAL_TIM_PWM_Start+0x72>
|
|
8004952: 687b ldr r3, [r7, #4]
|
|
8004954: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8004958: b2db uxtb r3, r3
|
|
800495a: 2b01 cmp r3, #1
|
|
800495c: bf14 ite ne
|
|
800495e: 2301 movne r3, #1
|
|
8004960: 2300 moveq r3, #0
|
|
8004962: b2db uxtb r3, r3
|
|
8004964: e015 b.n 8004992 <HAL_TIM_PWM_Start+0x9e>
|
|
8004966: 683b ldr r3, [r7, #0]
|
|
8004968: 2b10 cmp r3, #16
|
|
800496a: d109 bne.n 8004980 <HAL_TIM_PWM_Start+0x8c>
|
|
800496c: 687b ldr r3, [r7, #4]
|
|
800496e: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
8004972: b2db uxtb r3, r3
|
|
8004974: 2b01 cmp r3, #1
|
|
8004976: bf14 ite ne
|
|
8004978: 2301 movne r3, #1
|
|
800497a: 2300 moveq r3, #0
|
|
800497c: b2db uxtb r3, r3
|
|
800497e: e008 b.n 8004992 <HAL_TIM_PWM_Start+0x9e>
|
|
8004980: 687b ldr r3, [r7, #4]
|
|
8004982: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
|
|
8004986: b2db uxtb r3, r3
|
|
8004988: 2b01 cmp r3, #1
|
|
800498a: bf14 ite ne
|
|
800498c: 2301 movne r3, #1
|
|
800498e: 2300 moveq r3, #0
|
|
8004990: b2db uxtb r3, r3
|
|
8004992: 2b00 cmp r3, #0
|
|
8004994: d001 beq.n 800499a <HAL_TIM_PWM_Start+0xa6>
|
|
{
|
|
return HAL_ERROR;
|
|
8004996: 2301 movs r3, #1
|
|
8004998: e097 b.n 8004aca <HAL_TIM_PWM_Start+0x1d6>
|
|
}
|
|
|
|
/* Set the TIM channel state */
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
800499a: 683b ldr r3, [r7, #0]
|
|
800499c: 2b00 cmp r3, #0
|
|
800499e: d104 bne.n 80049aa <HAL_TIM_PWM_Start+0xb6>
|
|
80049a0: 687b ldr r3, [r7, #4]
|
|
80049a2: 2202 movs r2, #2
|
|
80049a4: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
80049a8: e023 b.n 80049f2 <HAL_TIM_PWM_Start+0xfe>
|
|
80049aa: 683b ldr r3, [r7, #0]
|
|
80049ac: 2b04 cmp r3, #4
|
|
80049ae: d104 bne.n 80049ba <HAL_TIM_PWM_Start+0xc6>
|
|
80049b0: 687b ldr r3, [r7, #4]
|
|
80049b2: 2202 movs r2, #2
|
|
80049b4: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
80049b8: e01b b.n 80049f2 <HAL_TIM_PWM_Start+0xfe>
|
|
80049ba: 683b ldr r3, [r7, #0]
|
|
80049bc: 2b08 cmp r3, #8
|
|
80049be: d104 bne.n 80049ca <HAL_TIM_PWM_Start+0xd6>
|
|
80049c0: 687b ldr r3, [r7, #4]
|
|
80049c2: 2202 movs r2, #2
|
|
80049c4: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80049c8: e013 b.n 80049f2 <HAL_TIM_PWM_Start+0xfe>
|
|
80049ca: 683b ldr r3, [r7, #0]
|
|
80049cc: 2b0c cmp r3, #12
|
|
80049ce: d104 bne.n 80049da <HAL_TIM_PWM_Start+0xe6>
|
|
80049d0: 687b ldr r3, [r7, #4]
|
|
80049d2: 2202 movs r2, #2
|
|
80049d4: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
80049d8: e00b b.n 80049f2 <HAL_TIM_PWM_Start+0xfe>
|
|
80049da: 683b ldr r3, [r7, #0]
|
|
80049dc: 2b10 cmp r3, #16
|
|
80049de: d104 bne.n 80049ea <HAL_TIM_PWM_Start+0xf6>
|
|
80049e0: 687b ldr r3, [r7, #4]
|
|
80049e2: 2202 movs r2, #2
|
|
80049e4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80049e8: e003 b.n 80049f2 <HAL_TIM_PWM_Start+0xfe>
|
|
80049ea: 687b ldr r3, [r7, #4]
|
|
80049ec: 2202 movs r2, #2
|
|
80049ee: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
|
|
/* Enable the Capture compare channel */
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
80049f2: 687b ldr r3, [r7, #4]
|
|
80049f4: 681b ldr r3, [r3, #0]
|
|
80049f6: 2201 movs r2, #1
|
|
80049f8: 6839 ldr r1, [r7, #0]
|
|
80049fa: 4618 mov r0, r3
|
|
80049fc: f001 f838 bl 8005a70 <TIM_CCxChannelCmd>
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
8004a00: 687b ldr r3, [r7, #4]
|
|
8004a02: 681b ldr r3, [r3, #0]
|
|
8004a04: 4a33 ldr r2, [pc, #204] @ (8004ad4 <HAL_TIM_PWM_Start+0x1e0>)
|
|
8004a06: 4293 cmp r3, r2
|
|
8004a08: d013 beq.n 8004a32 <HAL_TIM_PWM_Start+0x13e>
|
|
8004a0a: 687b ldr r3, [r7, #4]
|
|
8004a0c: 681b ldr r3, [r3, #0]
|
|
8004a0e: 4a32 ldr r2, [pc, #200] @ (8004ad8 <HAL_TIM_PWM_Start+0x1e4>)
|
|
8004a10: 4293 cmp r3, r2
|
|
8004a12: d00e beq.n 8004a32 <HAL_TIM_PWM_Start+0x13e>
|
|
8004a14: 687b ldr r3, [r7, #4]
|
|
8004a16: 681b ldr r3, [r3, #0]
|
|
8004a18: 4a30 ldr r2, [pc, #192] @ (8004adc <HAL_TIM_PWM_Start+0x1e8>)
|
|
8004a1a: 4293 cmp r3, r2
|
|
8004a1c: d009 beq.n 8004a32 <HAL_TIM_PWM_Start+0x13e>
|
|
8004a1e: 687b ldr r3, [r7, #4]
|
|
8004a20: 681b ldr r3, [r3, #0]
|
|
8004a22: 4a2f ldr r2, [pc, #188] @ (8004ae0 <HAL_TIM_PWM_Start+0x1ec>)
|
|
8004a24: 4293 cmp r3, r2
|
|
8004a26: d004 beq.n 8004a32 <HAL_TIM_PWM_Start+0x13e>
|
|
8004a28: 687b ldr r3, [r7, #4]
|
|
8004a2a: 681b ldr r3, [r3, #0]
|
|
8004a2c: 4a2d ldr r2, [pc, #180] @ (8004ae4 <HAL_TIM_PWM_Start+0x1f0>)
|
|
8004a2e: 4293 cmp r3, r2
|
|
8004a30: d101 bne.n 8004a36 <HAL_TIM_PWM_Start+0x142>
|
|
8004a32: 2301 movs r3, #1
|
|
8004a34: e000 b.n 8004a38 <HAL_TIM_PWM_Start+0x144>
|
|
8004a36: 2300 movs r3, #0
|
|
8004a38: 2b00 cmp r3, #0
|
|
8004a3a: d007 beq.n 8004a4c <HAL_TIM_PWM_Start+0x158>
|
|
{
|
|
/* Enable the main output */
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
8004a3c: 687b ldr r3, [r7, #4]
|
|
8004a3e: 681b ldr r3, [r3, #0]
|
|
8004a40: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8004a42: 687b ldr r3, [r7, #4]
|
|
8004a44: 681b ldr r3, [r3, #0]
|
|
8004a46: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8004a4a: 645a str r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004a4c: 687b ldr r3, [r7, #4]
|
|
8004a4e: 681b ldr r3, [r3, #0]
|
|
8004a50: 4a20 ldr r2, [pc, #128] @ (8004ad4 <HAL_TIM_PWM_Start+0x1e0>)
|
|
8004a52: 4293 cmp r3, r2
|
|
8004a54: d018 beq.n 8004a88 <HAL_TIM_PWM_Start+0x194>
|
|
8004a56: 687b ldr r3, [r7, #4]
|
|
8004a58: 681b ldr r3, [r3, #0]
|
|
8004a5a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8004a5e: d013 beq.n 8004a88 <HAL_TIM_PWM_Start+0x194>
|
|
8004a60: 687b ldr r3, [r7, #4]
|
|
8004a62: 681b ldr r3, [r3, #0]
|
|
8004a64: 4a20 ldr r2, [pc, #128] @ (8004ae8 <HAL_TIM_PWM_Start+0x1f4>)
|
|
8004a66: 4293 cmp r3, r2
|
|
8004a68: d00e beq.n 8004a88 <HAL_TIM_PWM_Start+0x194>
|
|
8004a6a: 687b ldr r3, [r7, #4]
|
|
8004a6c: 681b ldr r3, [r3, #0]
|
|
8004a6e: 4a1f ldr r2, [pc, #124] @ (8004aec <HAL_TIM_PWM_Start+0x1f8>)
|
|
8004a70: 4293 cmp r3, r2
|
|
8004a72: d009 beq.n 8004a88 <HAL_TIM_PWM_Start+0x194>
|
|
8004a74: 687b ldr r3, [r7, #4]
|
|
8004a76: 681b ldr r3, [r3, #0]
|
|
8004a78: 4a17 ldr r2, [pc, #92] @ (8004ad8 <HAL_TIM_PWM_Start+0x1e4>)
|
|
8004a7a: 4293 cmp r3, r2
|
|
8004a7c: d004 beq.n 8004a88 <HAL_TIM_PWM_Start+0x194>
|
|
8004a7e: 687b ldr r3, [r7, #4]
|
|
8004a80: 681b ldr r3, [r3, #0]
|
|
8004a82: 4a16 ldr r2, [pc, #88] @ (8004adc <HAL_TIM_PWM_Start+0x1e8>)
|
|
8004a84: 4293 cmp r3, r2
|
|
8004a86: d115 bne.n 8004ab4 <HAL_TIM_PWM_Start+0x1c0>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8004a88: 687b ldr r3, [r7, #4]
|
|
8004a8a: 681b ldr r3, [r3, #0]
|
|
8004a8c: 689a ldr r2, [r3, #8]
|
|
8004a8e: 4b18 ldr r3, [pc, #96] @ (8004af0 <HAL_TIM_PWM_Start+0x1fc>)
|
|
8004a90: 4013 ands r3, r2
|
|
8004a92: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8004a94: 68fb ldr r3, [r7, #12]
|
|
8004a96: 2b06 cmp r3, #6
|
|
8004a98: d015 beq.n 8004ac6 <HAL_TIM_PWM_Start+0x1d2>
|
|
8004a9a: 68fb ldr r3, [r7, #12]
|
|
8004a9c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004aa0: d011 beq.n 8004ac6 <HAL_TIM_PWM_Start+0x1d2>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8004aa2: 687b ldr r3, [r7, #4]
|
|
8004aa4: 681b ldr r3, [r3, #0]
|
|
8004aa6: 681a ldr r2, [r3, #0]
|
|
8004aa8: 687b ldr r3, [r7, #4]
|
|
8004aaa: 681b ldr r3, [r3, #0]
|
|
8004aac: f042 0201 orr.w r2, r2, #1
|
|
8004ab0: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8004ab2: e008 b.n 8004ac6 <HAL_TIM_PWM_Start+0x1d2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8004ab4: 687b ldr r3, [r7, #4]
|
|
8004ab6: 681b ldr r3, [r3, #0]
|
|
8004ab8: 681a ldr r2, [r3, #0]
|
|
8004aba: 687b ldr r3, [r7, #4]
|
|
8004abc: 681b ldr r3, [r3, #0]
|
|
8004abe: f042 0201 orr.w r2, r2, #1
|
|
8004ac2: 601a str r2, [r3, #0]
|
|
8004ac4: e000 b.n 8004ac8 <HAL_TIM_PWM_Start+0x1d4>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8004ac6: bf00 nop
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8004ac8: 2300 movs r3, #0
|
|
}
|
|
8004aca: 4618 mov r0, r3
|
|
8004acc: 3710 adds r7, #16
|
|
8004ace: 46bd mov sp, r7
|
|
8004ad0: bd80 pop {r7, pc}
|
|
8004ad2: bf00 nop
|
|
8004ad4: 40012c00 .word 0x40012c00
|
|
8004ad8: 40013400 .word 0x40013400
|
|
8004adc: 40014000 .word 0x40014000
|
|
8004ae0: 40014400 .word 0x40014400
|
|
8004ae4: 40014800 .word 0x40014800
|
|
8004ae8: 40000400 .word 0x40000400
|
|
8004aec: 40000800 .word 0x40000800
|
|
8004af0: 00010007 .word 0x00010007
|
|
|
|
08004af4 <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
8004af4: b580 push {r7, lr}
|
|
8004af6: b084 sub sp, #16
|
|
8004af8: af00 add r7, sp, #0
|
|
8004afa: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
8004afc: 687b ldr r3, [r7, #4]
|
|
8004afe: 681b ldr r3, [r3, #0]
|
|
8004b00: 68db ldr r3, [r3, #12]
|
|
8004b02: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
8004b04: 687b ldr r3, [r7, #4]
|
|
8004b06: 681b ldr r3, [r3, #0]
|
|
8004b08: 691b ldr r3, [r3, #16]
|
|
8004b0a: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
8004b0c: 68bb ldr r3, [r7, #8]
|
|
8004b0e: f003 0302 and.w r3, r3, #2
|
|
8004b12: 2b00 cmp r3, #0
|
|
8004b14: d020 beq.n 8004b58 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
8004b16: 68fb ldr r3, [r7, #12]
|
|
8004b18: f003 0302 and.w r3, r3, #2
|
|
8004b1c: 2b00 cmp r3, #0
|
|
8004b1e: d01b beq.n 8004b58 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
8004b20: 687b ldr r3, [r7, #4]
|
|
8004b22: 681b ldr r3, [r3, #0]
|
|
8004b24: f06f 0202 mvn.w r2, #2
|
|
8004b28: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
8004b2a: 687b ldr r3, [r7, #4]
|
|
8004b2c: 2201 movs r2, #1
|
|
8004b2e: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
8004b30: 687b ldr r3, [r7, #4]
|
|
8004b32: 681b ldr r3, [r3, #0]
|
|
8004b34: 699b ldr r3, [r3, #24]
|
|
8004b36: f003 0303 and.w r3, r3, #3
|
|
8004b3a: 2b00 cmp r3, #0
|
|
8004b3c: d003 beq.n 8004b46 <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8004b3e: 6878 ldr r0, [r7, #4]
|
|
8004b40: f000 fb4a bl 80051d8 <HAL_TIM_IC_CaptureCallback>
|
|
8004b44: e005 b.n 8004b52 <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8004b46: 6878 ldr r0, [r7, #4]
|
|
8004b48: f000 fb3c bl 80051c4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004b4c: 6878 ldr r0, [r7, #4]
|
|
8004b4e: f000 fb4d bl 80051ec <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8004b52: 687b ldr r3, [r7, #4]
|
|
8004b54: 2200 movs r2, #0
|
|
8004b56: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
8004b58: 68bb ldr r3, [r7, #8]
|
|
8004b5a: f003 0304 and.w r3, r3, #4
|
|
8004b5e: 2b00 cmp r3, #0
|
|
8004b60: d020 beq.n 8004ba4 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
8004b62: 68fb ldr r3, [r7, #12]
|
|
8004b64: f003 0304 and.w r3, r3, #4
|
|
8004b68: 2b00 cmp r3, #0
|
|
8004b6a: d01b beq.n 8004ba4 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
8004b6c: 687b ldr r3, [r7, #4]
|
|
8004b6e: 681b ldr r3, [r3, #0]
|
|
8004b70: f06f 0204 mvn.w r2, #4
|
|
8004b74: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
8004b76: 687b ldr r3, [r7, #4]
|
|
8004b78: 2202 movs r2, #2
|
|
8004b7a: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8004b7c: 687b ldr r3, [r7, #4]
|
|
8004b7e: 681b ldr r3, [r3, #0]
|
|
8004b80: 699b ldr r3, [r3, #24]
|
|
8004b82: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004b86: 2b00 cmp r3, #0
|
|
8004b88: d003 beq.n 8004b92 <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8004b8a: 6878 ldr r0, [r7, #4]
|
|
8004b8c: f000 fb24 bl 80051d8 <HAL_TIM_IC_CaptureCallback>
|
|
8004b90: e005 b.n 8004b9e <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8004b92: 6878 ldr r0, [r7, #4]
|
|
8004b94: f000 fb16 bl 80051c4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004b98: 6878 ldr r0, [r7, #4]
|
|
8004b9a: f000 fb27 bl 80051ec <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8004b9e: 687b ldr r3, [r7, #4]
|
|
8004ba0: 2200 movs r2, #0
|
|
8004ba2: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
8004ba4: 68bb ldr r3, [r7, #8]
|
|
8004ba6: f003 0308 and.w r3, r3, #8
|
|
8004baa: 2b00 cmp r3, #0
|
|
8004bac: d020 beq.n 8004bf0 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
8004bae: 68fb ldr r3, [r7, #12]
|
|
8004bb0: f003 0308 and.w r3, r3, #8
|
|
8004bb4: 2b00 cmp r3, #0
|
|
8004bb6: d01b beq.n 8004bf0 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
8004bb8: 687b ldr r3, [r7, #4]
|
|
8004bba: 681b ldr r3, [r3, #0]
|
|
8004bbc: f06f 0208 mvn.w r2, #8
|
|
8004bc0: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8004bc2: 687b ldr r3, [r7, #4]
|
|
8004bc4: 2204 movs r2, #4
|
|
8004bc6: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
8004bc8: 687b ldr r3, [r7, #4]
|
|
8004bca: 681b ldr r3, [r3, #0]
|
|
8004bcc: 69db ldr r3, [r3, #28]
|
|
8004bce: f003 0303 and.w r3, r3, #3
|
|
8004bd2: 2b00 cmp r3, #0
|
|
8004bd4: d003 beq.n 8004bde <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8004bd6: 6878 ldr r0, [r7, #4]
|
|
8004bd8: f000 fafe bl 80051d8 <HAL_TIM_IC_CaptureCallback>
|
|
8004bdc: e005 b.n 8004bea <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8004bde: 6878 ldr r0, [r7, #4]
|
|
8004be0: f000 faf0 bl 80051c4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004be4: 6878 ldr r0, [r7, #4]
|
|
8004be6: f000 fb01 bl 80051ec <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8004bea: 687b ldr r3, [r7, #4]
|
|
8004bec: 2200 movs r2, #0
|
|
8004bee: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
8004bf0: 68bb ldr r3, [r7, #8]
|
|
8004bf2: f003 0310 and.w r3, r3, #16
|
|
8004bf6: 2b00 cmp r3, #0
|
|
8004bf8: d020 beq.n 8004c3c <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
8004bfa: 68fb ldr r3, [r7, #12]
|
|
8004bfc: f003 0310 and.w r3, r3, #16
|
|
8004c00: 2b00 cmp r3, #0
|
|
8004c02: d01b beq.n 8004c3c <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
8004c04: 687b ldr r3, [r7, #4]
|
|
8004c06: 681b ldr r3, [r3, #0]
|
|
8004c08: f06f 0210 mvn.w r2, #16
|
|
8004c0c: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
8004c0e: 687b ldr r3, [r7, #4]
|
|
8004c10: 2208 movs r2, #8
|
|
8004c12: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
8004c14: 687b ldr r3, [r7, #4]
|
|
8004c16: 681b ldr r3, [r3, #0]
|
|
8004c18: 69db ldr r3, [r3, #28]
|
|
8004c1a: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004c1e: 2b00 cmp r3, #0
|
|
8004c20: d003 beq.n 8004c2a <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8004c22: 6878 ldr r0, [r7, #4]
|
|
8004c24: f000 fad8 bl 80051d8 <HAL_TIM_IC_CaptureCallback>
|
|
8004c28: e005 b.n 8004c36 <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8004c2a: 6878 ldr r0, [r7, #4]
|
|
8004c2c: f000 faca bl 80051c4 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8004c30: 6878 ldr r0, [r7, #4]
|
|
8004c32: f000 fadb bl 80051ec <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8004c36: 687b ldr r3, [r7, #4]
|
|
8004c38: 2200 movs r2, #0
|
|
8004c3a: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
8004c3c: 68bb ldr r3, [r7, #8]
|
|
8004c3e: f003 0301 and.w r3, r3, #1
|
|
8004c42: 2b00 cmp r3, #0
|
|
8004c44: d00c beq.n 8004c60 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
8004c46: 68fb ldr r3, [r7, #12]
|
|
8004c48: f003 0301 and.w r3, r3, #1
|
|
8004c4c: 2b00 cmp r3, #0
|
|
8004c4e: d007 beq.n 8004c60 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8004c50: 687b ldr r3, [r7, #4]
|
|
8004c52: 681b ldr r3, [r3, #0]
|
|
8004c54: f06f 0201 mvn.w r2, #1
|
|
8004c58: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
8004c5a: 6878 ldr r0, [r7, #4]
|
|
8004c5c: f000 faa8 bl 80051b0 <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
8004c60: 68bb ldr r3, [r7, #8]
|
|
8004c62: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004c66: 2b00 cmp r3, #0
|
|
8004c68: d104 bne.n 8004c74 <HAL_TIM_IRQHandler+0x180>
|
|
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
|
|
8004c6a: 68bb ldr r3, [r7, #8]
|
|
8004c6c: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
8004c70: 2b00 cmp r3, #0
|
|
8004c72: d00c beq.n 8004c8e <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8004c74: 68fb ldr r3, [r7, #12]
|
|
8004c76: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004c7a: 2b00 cmp r3, #0
|
|
8004c7c: d007 beq.n 8004c8e <HAL_TIM_IRQHandler+0x19a>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
|
8004c7e: 687b ldr r3, [r7, #4]
|
|
8004c80: 681b ldr r3, [r3, #0]
|
|
8004c82: f46f 5202 mvn.w r2, #8320 @ 0x2080
|
|
8004c86: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8004c88: 6878 ldr r0, [r7, #4]
|
|
8004c8a: f001 f82f bl 8005cec <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break2 input event */
|
|
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
|
|
8004c8e: 68bb ldr r3, [r7, #8]
|
|
8004c90: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004c94: 2b00 cmp r3, #0
|
|
8004c96: d00c beq.n 8004cb2 <HAL_TIM_IRQHandler+0x1be>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8004c98: 68fb ldr r3, [r7, #12]
|
|
8004c9a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004c9e: 2b00 cmp r3, #0
|
|
8004ca0: d007 beq.n 8004cb2 <HAL_TIM_IRQHandler+0x1be>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
8004ca2: 687b ldr r3, [r7, #4]
|
|
8004ca4: 681b ldr r3, [r3, #0]
|
|
8004ca6: f46f 7280 mvn.w r2, #256 @ 0x100
|
|
8004caa: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->Break2Callback(htim);
|
|
#else
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
8004cac: 6878 ldr r0, [r7, #4]
|
|
8004cae: f001 f827 bl 8005d00 <HAL_TIMEx_Break2Callback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
8004cb2: 68bb ldr r3, [r7, #8]
|
|
8004cb4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004cb8: 2b00 cmp r3, #0
|
|
8004cba: d00c beq.n 8004cd6 <HAL_TIM_IRQHandler+0x1e2>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
8004cbc: 68fb ldr r3, [r7, #12]
|
|
8004cbe: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004cc2: 2b00 cmp r3, #0
|
|
8004cc4: d007 beq.n 8004cd6 <HAL_TIM_IRQHandler+0x1e2>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8004cc6: 687b ldr r3, [r7, #4]
|
|
8004cc8: 681b ldr r3, [r3, #0]
|
|
8004cca: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8004cce: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
8004cd0: 6878 ldr r0, [r7, #4]
|
|
8004cd2: f000 fa95 bl 8005200 <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
8004cd6: 68bb ldr r3, [r7, #8]
|
|
8004cd8: f003 0320 and.w r3, r3, #32
|
|
8004cdc: 2b00 cmp r3, #0
|
|
8004cde: d00c beq.n 8004cfa <HAL_TIM_IRQHandler+0x206>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
8004ce0: 68fb ldr r3, [r7, #12]
|
|
8004ce2: f003 0320 and.w r3, r3, #32
|
|
8004ce6: 2b00 cmp r3, #0
|
|
8004ce8: d007 beq.n 8004cfa <HAL_TIM_IRQHandler+0x206>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
8004cea: 687b ldr r3, [r7, #4]
|
|
8004cec: 681b ldr r3, [r3, #0]
|
|
8004cee: f06f 0220 mvn.w r2, #32
|
|
8004cf2: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
8004cf4: 6878 ldr r0, [r7, #4]
|
|
8004cf6: f000 ffef bl 8005cd8 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Encoder index event */
|
|
if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
|
|
8004cfa: 68bb ldr r3, [r7, #8]
|
|
8004cfc: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8004d00: 2b00 cmp r3, #0
|
|
8004d02: d00c beq.n 8004d1e <HAL_TIM_IRQHandler+0x22a>
|
|
{
|
|
if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
|
|
8004d04: 68fb ldr r3, [r7, #12]
|
|
8004d06: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8004d0a: 2b00 cmp r3, #0
|
|
8004d0c: d007 beq.n 8004d1e <HAL_TIM_IRQHandler+0x22a>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
|
|
8004d0e: 687b ldr r3, [r7, #4]
|
|
8004d10: 681b ldr r3, [r3, #0]
|
|
8004d12: f46f 1280 mvn.w r2, #1048576 @ 0x100000
|
|
8004d16: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->EncoderIndexCallback(htim);
|
|
#else
|
|
HAL_TIMEx_EncoderIndexCallback(htim);
|
|
8004d18: 6878 ldr r0, [r7, #4]
|
|
8004d1a: f000 fffb bl 8005d14 <HAL_TIMEx_EncoderIndexCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Direction change event */
|
|
if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
|
|
8004d1e: 68bb ldr r3, [r7, #8]
|
|
8004d20: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8004d24: 2b00 cmp r3, #0
|
|
8004d26: d00c beq.n 8004d42 <HAL_TIM_IRQHandler+0x24e>
|
|
{
|
|
if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
|
|
8004d28: 68fb ldr r3, [r7, #12]
|
|
8004d2a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8004d2e: 2b00 cmp r3, #0
|
|
8004d30: d007 beq.n 8004d42 <HAL_TIM_IRQHandler+0x24e>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
|
|
8004d32: 687b ldr r3, [r7, #4]
|
|
8004d34: 681b ldr r3, [r3, #0]
|
|
8004d36: f46f 1200 mvn.w r2, #2097152 @ 0x200000
|
|
8004d3a: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->DirectionChangeCallback(htim);
|
|
#else
|
|
HAL_TIMEx_DirectionChangeCallback(htim);
|
|
8004d3c: 6878 ldr r0, [r7, #4]
|
|
8004d3e: f000 fff3 bl 8005d28 <HAL_TIMEx_DirectionChangeCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Index error event */
|
|
if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
|
|
8004d42: 68bb ldr r3, [r7, #8]
|
|
8004d44: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004d48: 2b00 cmp r3, #0
|
|
8004d4a: d00c beq.n 8004d66 <HAL_TIM_IRQHandler+0x272>
|
|
{
|
|
if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
|
|
8004d4c: 68fb ldr r3, [r7, #12]
|
|
8004d4e: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004d52: 2b00 cmp r3, #0
|
|
8004d54: d007 beq.n 8004d66 <HAL_TIM_IRQHandler+0x272>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
|
|
8004d56: 687b ldr r3, [r7, #4]
|
|
8004d58: 681b ldr r3, [r3, #0]
|
|
8004d5a: f46f 0280 mvn.w r2, #4194304 @ 0x400000
|
|
8004d5e: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IndexErrorCallback(htim);
|
|
#else
|
|
HAL_TIMEx_IndexErrorCallback(htim);
|
|
8004d60: 6878 ldr r0, [r7, #4]
|
|
8004d62: f000 ffeb bl 8005d3c <HAL_TIMEx_IndexErrorCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Transition error event */
|
|
if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
|
|
8004d66: 68bb ldr r3, [r7, #8]
|
|
8004d68: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8004d6c: 2b00 cmp r3, #0
|
|
8004d6e: d00c beq.n 8004d8a <HAL_TIM_IRQHandler+0x296>
|
|
{
|
|
if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
|
|
8004d70: 68fb ldr r3, [r7, #12]
|
|
8004d72: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8004d76: 2b00 cmp r3, #0
|
|
8004d78: d007 beq.n 8004d8a <HAL_TIM_IRQHandler+0x296>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
|
|
8004d7a: 687b ldr r3, [r7, #4]
|
|
8004d7c: 681b ldr r3, [r3, #0]
|
|
8004d7e: f46f 0200 mvn.w r2, #8388608 @ 0x800000
|
|
8004d82: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TransitionErrorCallback(htim);
|
|
#else
|
|
HAL_TIMEx_TransitionErrorCallback(htim);
|
|
8004d84: 6878 ldr r0, [r7, #4]
|
|
8004d86: f000 ffe3 bl 8005d50 <HAL_TIMEx_TransitionErrorCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
8004d8a: bf00 nop
|
|
8004d8c: 3710 adds r7, #16
|
|
8004d8e: 46bd mov sp, r7
|
|
8004d90: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004d94 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
const TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
8004d94: b580 push {r7, lr}
|
|
8004d96: b086 sub sp, #24
|
|
8004d98: af00 add r7, sp, #0
|
|
8004d9a: 60f8 str r0, [r7, #12]
|
|
8004d9c: 60b9 str r1, [r7, #8]
|
|
8004d9e: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004da0: 2300 movs r3, #0
|
|
8004da2: 75fb strb r3, [r7, #23]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8004da4: 68fb ldr r3, [r7, #12]
|
|
8004da6: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004daa: 2b01 cmp r3, #1
|
|
8004dac: d101 bne.n 8004db2 <HAL_TIM_PWM_ConfigChannel+0x1e>
|
|
8004dae: 2302 movs r3, #2
|
|
8004db0: e0ff b.n 8004fb2 <HAL_TIM_PWM_ConfigChannel+0x21e>
|
|
8004db2: 68fb ldr r3, [r7, #12]
|
|
8004db4: 2201 movs r2, #1
|
|
8004db6: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
switch (Channel)
|
|
8004dba: 687b ldr r3, [r7, #4]
|
|
8004dbc: 2b14 cmp r3, #20
|
|
8004dbe: f200 80f0 bhi.w 8004fa2 <HAL_TIM_PWM_ConfigChannel+0x20e>
|
|
8004dc2: a201 add r2, pc, #4 @ (adr r2, 8004dc8 <HAL_TIM_PWM_ConfigChannel+0x34>)
|
|
8004dc4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8004dc8: 08004e1d .word 0x08004e1d
|
|
8004dcc: 08004fa3 .word 0x08004fa3
|
|
8004dd0: 08004fa3 .word 0x08004fa3
|
|
8004dd4: 08004fa3 .word 0x08004fa3
|
|
8004dd8: 08004e5d .word 0x08004e5d
|
|
8004ddc: 08004fa3 .word 0x08004fa3
|
|
8004de0: 08004fa3 .word 0x08004fa3
|
|
8004de4: 08004fa3 .word 0x08004fa3
|
|
8004de8: 08004e9f .word 0x08004e9f
|
|
8004dec: 08004fa3 .word 0x08004fa3
|
|
8004df0: 08004fa3 .word 0x08004fa3
|
|
8004df4: 08004fa3 .word 0x08004fa3
|
|
8004df8: 08004edf .word 0x08004edf
|
|
8004dfc: 08004fa3 .word 0x08004fa3
|
|
8004e00: 08004fa3 .word 0x08004fa3
|
|
8004e04: 08004fa3 .word 0x08004fa3
|
|
8004e08: 08004f21 .word 0x08004f21
|
|
8004e0c: 08004fa3 .word 0x08004fa3
|
|
8004e10: 08004fa3 .word 0x08004fa3
|
|
8004e14: 08004fa3 .word 0x08004fa3
|
|
8004e18: 08004f61 .word 0x08004f61
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
8004e1c: 68fb ldr r3, [r7, #12]
|
|
8004e1e: 681b ldr r3, [r3, #0]
|
|
8004e20: 68b9 ldr r1, [r7, #8]
|
|
8004e22: 4618 mov r0, r3
|
|
8004e24: f000 fa92 bl 800534c <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
8004e28: 68fb ldr r3, [r7, #12]
|
|
8004e2a: 681b ldr r3, [r3, #0]
|
|
8004e2c: 699a ldr r2, [r3, #24]
|
|
8004e2e: 68fb ldr r3, [r7, #12]
|
|
8004e30: 681b ldr r3, [r3, #0]
|
|
8004e32: f042 0208 orr.w r2, r2, #8
|
|
8004e36: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
8004e38: 68fb ldr r3, [r7, #12]
|
|
8004e3a: 681b ldr r3, [r3, #0]
|
|
8004e3c: 699a ldr r2, [r3, #24]
|
|
8004e3e: 68fb ldr r3, [r7, #12]
|
|
8004e40: 681b ldr r3, [r3, #0]
|
|
8004e42: f022 0204 bic.w r2, r2, #4
|
|
8004e46: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
8004e48: 68fb ldr r3, [r7, #12]
|
|
8004e4a: 681b ldr r3, [r3, #0]
|
|
8004e4c: 6999 ldr r1, [r3, #24]
|
|
8004e4e: 68bb ldr r3, [r7, #8]
|
|
8004e50: 691a ldr r2, [r3, #16]
|
|
8004e52: 68fb ldr r3, [r7, #12]
|
|
8004e54: 681b ldr r3, [r3, #0]
|
|
8004e56: 430a orrs r2, r1
|
|
8004e58: 619a str r2, [r3, #24]
|
|
break;
|
|
8004e5a: e0a5 b.n 8004fa8 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
8004e5c: 68fb ldr r3, [r7, #12]
|
|
8004e5e: 681b ldr r3, [r3, #0]
|
|
8004e60: 68b9 ldr r1, [r7, #8]
|
|
8004e62: 4618 mov r0, r3
|
|
8004e64: f000 fb02 bl 800546c <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
8004e68: 68fb ldr r3, [r7, #12]
|
|
8004e6a: 681b ldr r3, [r3, #0]
|
|
8004e6c: 699a ldr r2, [r3, #24]
|
|
8004e6e: 68fb ldr r3, [r7, #12]
|
|
8004e70: 681b ldr r3, [r3, #0]
|
|
8004e72: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8004e76: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
8004e78: 68fb ldr r3, [r7, #12]
|
|
8004e7a: 681b ldr r3, [r3, #0]
|
|
8004e7c: 699a ldr r2, [r3, #24]
|
|
8004e7e: 68fb ldr r3, [r7, #12]
|
|
8004e80: 681b ldr r3, [r3, #0]
|
|
8004e82: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8004e86: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
8004e88: 68fb ldr r3, [r7, #12]
|
|
8004e8a: 681b ldr r3, [r3, #0]
|
|
8004e8c: 6999 ldr r1, [r3, #24]
|
|
8004e8e: 68bb ldr r3, [r7, #8]
|
|
8004e90: 691b ldr r3, [r3, #16]
|
|
8004e92: 021a lsls r2, r3, #8
|
|
8004e94: 68fb ldr r3, [r7, #12]
|
|
8004e96: 681b ldr r3, [r3, #0]
|
|
8004e98: 430a orrs r2, r1
|
|
8004e9a: 619a str r2, [r3, #24]
|
|
break;
|
|
8004e9c: e084 b.n 8004fa8 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
8004e9e: 68fb ldr r3, [r7, #12]
|
|
8004ea0: 681b ldr r3, [r3, #0]
|
|
8004ea2: 68b9 ldr r1, [r7, #8]
|
|
8004ea4: 4618 mov r0, r3
|
|
8004ea6: f000 fb6b bl 8005580 <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
8004eaa: 68fb ldr r3, [r7, #12]
|
|
8004eac: 681b ldr r3, [r3, #0]
|
|
8004eae: 69da ldr r2, [r3, #28]
|
|
8004eb0: 68fb ldr r3, [r7, #12]
|
|
8004eb2: 681b ldr r3, [r3, #0]
|
|
8004eb4: f042 0208 orr.w r2, r2, #8
|
|
8004eb8: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
8004eba: 68fb ldr r3, [r7, #12]
|
|
8004ebc: 681b ldr r3, [r3, #0]
|
|
8004ebe: 69da ldr r2, [r3, #28]
|
|
8004ec0: 68fb ldr r3, [r7, #12]
|
|
8004ec2: 681b ldr r3, [r3, #0]
|
|
8004ec4: f022 0204 bic.w r2, r2, #4
|
|
8004ec8: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
8004eca: 68fb ldr r3, [r7, #12]
|
|
8004ecc: 681b ldr r3, [r3, #0]
|
|
8004ece: 69d9 ldr r1, [r3, #28]
|
|
8004ed0: 68bb ldr r3, [r7, #8]
|
|
8004ed2: 691a ldr r2, [r3, #16]
|
|
8004ed4: 68fb ldr r3, [r7, #12]
|
|
8004ed6: 681b ldr r3, [r3, #0]
|
|
8004ed8: 430a orrs r2, r1
|
|
8004eda: 61da str r2, [r3, #28]
|
|
break;
|
|
8004edc: e064 b.n 8004fa8 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
8004ede: 68fb ldr r3, [r7, #12]
|
|
8004ee0: 681b ldr r3, [r3, #0]
|
|
8004ee2: 68b9 ldr r1, [r7, #8]
|
|
8004ee4: 4618 mov r0, r3
|
|
8004ee6: f000 fbd3 bl 8005690 <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
8004eea: 68fb ldr r3, [r7, #12]
|
|
8004eec: 681b ldr r3, [r3, #0]
|
|
8004eee: 69da ldr r2, [r3, #28]
|
|
8004ef0: 68fb ldr r3, [r7, #12]
|
|
8004ef2: 681b ldr r3, [r3, #0]
|
|
8004ef4: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8004ef8: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
8004efa: 68fb ldr r3, [r7, #12]
|
|
8004efc: 681b ldr r3, [r3, #0]
|
|
8004efe: 69da ldr r2, [r3, #28]
|
|
8004f00: 68fb ldr r3, [r7, #12]
|
|
8004f02: 681b ldr r3, [r3, #0]
|
|
8004f04: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8004f08: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
8004f0a: 68fb ldr r3, [r7, #12]
|
|
8004f0c: 681b ldr r3, [r3, #0]
|
|
8004f0e: 69d9 ldr r1, [r3, #28]
|
|
8004f10: 68bb ldr r3, [r7, #8]
|
|
8004f12: 691b ldr r3, [r3, #16]
|
|
8004f14: 021a lsls r2, r3, #8
|
|
8004f16: 68fb ldr r3, [r7, #12]
|
|
8004f18: 681b ldr r3, [r3, #0]
|
|
8004f1a: 430a orrs r2, r1
|
|
8004f1c: 61da str r2, [r3, #28]
|
|
break;
|
|
8004f1e: e043 b.n 8004fa8 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
8004f20: 68fb ldr r3, [r7, #12]
|
|
8004f22: 681b ldr r3, [r3, #0]
|
|
8004f24: 68b9 ldr r1, [r7, #8]
|
|
8004f26: 4618 mov r0, r3
|
|
8004f28: f000 fc3c bl 80057a4 <TIM_OC5_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
8004f2c: 68fb ldr r3, [r7, #12]
|
|
8004f2e: 681b ldr r3, [r3, #0]
|
|
8004f30: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8004f32: 68fb ldr r3, [r7, #12]
|
|
8004f34: 681b ldr r3, [r3, #0]
|
|
8004f36: f042 0208 orr.w r2, r2, #8
|
|
8004f3a: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
8004f3c: 68fb ldr r3, [r7, #12]
|
|
8004f3e: 681b ldr r3, [r3, #0]
|
|
8004f40: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8004f42: 68fb ldr r3, [r7, #12]
|
|
8004f44: 681b ldr r3, [r3, #0]
|
|
8004f46: f022 0204 bic.w r2, r2, #4
|
|
8004f4a: 651a str r2, [r3, #80] @ 0x50
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
8004f4c: 68fb ldr r3, [r7, #12]
|
|
8004f4e: 681b ldr r3, [r3, #0]
|
|
8004f50: 6d19 ldr r1, [r3, #80] @ 0x50
|
|
8004f52: 68bb ldr r3, [r7, #8]
|
|
8004f54: 691a ldr r2, [r3, #16]
|
|
8004f56: 68fb ldr r3, [r7, #12]
|
|
8004f58: 681b ldr r3, [r3, #0]
|
|
8004f5a: 430a orrs r2, r1
|
|
8004f5c: 651a str r2, [r3, #80] @ 0x50
|
|
break;
|
|
8004f5e: e023 b.n 8004fa8 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
8004f60: 68fb ldr r3, [r7, #12]
|
|
8004f62: 681b ldr r3, [r3, #0]
|
|
8004f64: 68b9 ldr r1, [r7, #8]
|
|
8004f66: 4618 mov r0, r3
|
|
8004f68: f000 fc80 bl 800586c <TIM_OC6_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
8004f6c: 68fb ldr r3, [r7, #12]
|
|
8004f6e: 681b ldr r3, [r3, #0]
|
|
8004f70: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8004f72: 68fb ldr r3, [r7, #12]
|
|
8004f74: 681b ldr r3, [r3, #0]
|
|
8004f76: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8004f7a: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
8004f7c: 68fb ldr r3, [r7, #12]
|
|
8004f7e: 681b ldr r3, [r3, #0]
|
|
8004f80: 6d1a ldr r2, [r3, #80] @ 0x50
|
|
8004f82: 68fb ldr r3, [r7, #12]
|
|
8004f84: 681b ldr r3, [r3, #0]
|
|
8004f86: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8004f8a: 651a str r2, [r3, #80] @ 0x50
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
8004f8c: 68fb ldr r3, [r7, #12]
|
|
8004f8e: 681b ldr r3, [r3, #0]
|
|
8004f90: 6d19 ldr r1, [r3, #80] @ 0x50
|
|
8004f92: 68bb ldr r3, [r7, #8]
|
|
8004f94: 691b ldr r3, [r3, #16]
|
|
8004f96: 021a lsls r2, r3, #8
|
|
8004f98: 68fb ldr r3, [r7, #12]
|
|
8004f9a: 681b ldr r3, [r3, #0]
|
|
8004f9c: 430a orrs r2, r1
|
|
8004f9e: 651a str r2, [r3, #80] @ 0x50
|
|
break;
|
|
8004fa0: e002 b.n 8004fa8 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004fa2: 2301 movs r3, #1
|
|
8004fa4: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8004fa6: bf00 nop
|
|
}
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8004fa8: 68fb ldr r3, [r7, #12]
|
|
8004faa: 2200 movs r2, #0
|
|
8004fac: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8004fb0: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8004fb2: 4618 mov r0, r3
|
|
8004fb4: 3718 adds r7, #24
|
|
8004fb6: 46bd mov sp, r7
|
|
8004fb8: bd80 pop {r7, pc}
|
|
8004fba: bf00 nop
|
|
|
|
08004fbc <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
8004fbc: b580 push {r7, lr}
|
|
8004fbe: b084 sub sp, #16
|
|
8004fc0: af00 add r7, sp, #0
|
|
8004fc2: 6078 str r0, [r7, #4]
|
|
8004fc4: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004fc6: 2300 movs r3, #0
|
|
8004fc8: 73fb strb r3, [r7, #15]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8004fca: 687b ldr r3, [r7, #4]
|
|
8004fcc: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8004fd0: 2b01 cmp r3, #1
|
|
8004fd2: d101 bne.n 8004fd8 <HAL_TIM_ConfigClockSource+0x1c>
|
|
8004fd4: 2302 movs r3, #2
|
|
8004fd6: e0de b.n 8005196 <HAL_TIM_ConfigClockSource+0x1da>
|
|
8004fd8: 687b ldr r3, [r7, #4]
|
|
8004fda: 2201 movs r2, #1
|
|
8004fdc: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004fe0: 687b ldr r3, [r7, #4]
|
|
8004fe2: 2202 movs r2, #2
|
|
8004fe4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004fe8: 687b ldr r3, [r7, #4]
|
|
8004fea: 681b ldr r3, [r3, #0]
|
|
8004fec: 689b ldr r3, [r3, #8]
|
|
8004fee: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
8004ff0: 68bb ldr r3, [r7, #8]
|
|
8004ff2: f423 1344 bic.w r3, r3, #3211264 @ 0x310000
|
|
8004ff6: f023 0377 bic.w r3, r3, #119 @ 0x77
|
|
8004ffa: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8004ffc: 68bb ldr r3, [r7, #8]
|
|
8004ffe: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
8005002: 60bb str r3, [r7, #8]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005004: 687b ldr r3, [r7, #4]
|
|
8005006: 681b ldr r3, [r3, #0]
|
|
8005008: 68ba ldr r2, [r7, #8]
|
|
800500a: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
800500c: 683b ldr r3, [r7, #0]
|
|
800500e: 681b ldr r3, [r3, #0]
|
|
8005010: 4a63 ldr r2, [pc, #396] @ (80051a0 <HAL_TIM_ConfigClockSource+0x1e4>)
|
|
8005012: 4293 cmp r3, r2
|
|
8005014: f000 80a9 beq.w 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
8005018: 4a61 ldr r2, [pc, #388] @ (80051a0 <HAL_TIM_ConfigClockSource+0x1e4>)
|
|
800501a: 4293 cmp r3, r2
|
|
800501c: f200 80ae bhi.w 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005020: 4a60 ldr r2, [pc, #384] @ (80051a4 <HAL_TIM_ConfigClockSource+0x1e8>)
|
|
8005022: 4293 cmp r3, r2
|
|
8005024: f000 80a1 beq.w 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
8005028: 4a5e ldr r2, [pc, #376] @ (80051a4 <HAL_TIM_ConfigClockSource+0x1e8>)
|
|
800502a: 4293 cmp r3, r2
|
|
800502c: f200 80a6 bhi.w 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005030: 4a5d ldr r2, [pc, #372] @ (80051a8 <HAL_TIM_ConfigClockSource+0x1ec>)
|
|
8005032: 4293 cmp r3, r2
|
|
8005034: f000 8099 beq.w 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
8005038: 4a5b ldr r2, [pc, #364] @ (80051a8 <HAL_TIM_ConfigClockSource+0x1ec>)
|
|
800503a: 4293 cmp r3, r2
|
|
800503c: f200 809e bhi.w 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005040: 4a5a ldr r2, [pc, #360] @ (80051ac <HAL_TIM_ConfigClockSource+0x1f0>)
|
|
8005042: 4293 cmp r3, r2
|
|
8005044: f000 8091 beq.w 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
8005048: 4a58 ldr r2, [pc, #352] @ (80051ac <HAL_TIM_ConfigClockSource+0x1f0>)
|
|
800504a: 4293 cmp r3, r2
|
|
800504c: f200 8096 bhi.w 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005050: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
|
|
8005054: f000 8089 beq.w 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
8005058: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
|
|
800505c: f200 808e bhi.w 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005060: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8005064: d03e beq.n 80050e4 <HAL_TIM_ConfigClockSource+0x128>
|
|
8005066: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
800506a: f200 8087 bhi.w 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
800506e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005072: f000 8086 beq.w 8005182 <HAL_TIM_ConfigClockSource+0x1c6>
|
|
8005076: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800507a: d87f bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
800507c: 2b70 cmp r3, #112 @ 0x70
|
|
800507e: d01a beq.n 80050b6 <HAL_TIM_ConfigClockSource+0xfa>
|
|
8005080: 2b70 cmp r3, #112 @ 0x70
|
|
8005082: d87b bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005084: 2b60 cmp r3, #96 @ 0x60
|
|
8005086: d050 beq.n 800512a <HAL_TIM_ConfigClockSource+0x16e>
|
|
8005088: 2b60 cmp r3, #96 @ 0x60
|
|
800508a: d877 bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
800508c: 2b50 cmp r3, #80 @ 0x50
|
|
800508e: d03c beq.n 800510a <HAL_TIM_ConfigClockSource+0x14e>
|
|
8005090: 2b50 cmp r3, #80 @ 0x50
|
|
8005092: d873 bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
8005094: 2b40 cmp r3, #64 @ 0x40
|
|
8005096: d058 beq.n 800514a <HAL_TIM_ConfigClockSource+0x18e>
|
|
8005098: 2b40 cmp r3, #64 @ 0x40
|
|
800509a: d86f bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
800509c: 2b30 cmp r3, #48 @ 0x30
|
|
800509e: d064 beq.n 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
80050a0: 2b30 cmp r3, #48 @ 0x30
|
|
80050a2: d86b bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
80050a4: 2b20 cmp r3, #32
|
|
80050a6: d060 beq.n 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
80050a8: 2b20 cmp r3, #32
|
|
80050aa: d867 bhi.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
80050ac: 2b00 cmp r3, #0
|
|
80050ae: d05c beq.n 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
80050b0: 2b10 cmp r3, #16
|
|
80050b2: d05a beq.n 800516a <HAL_TIM_ConfigClockSource+0x1ae>
|
|
80050b4: e062 b.n 800517c <HAL_TIM_ConfigClockSource+0x1c0>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80050b6: 687b ldr r3, [r7, #4]
|
|
80050b8: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
80050ba: 683b ldr r3, [r7, #0]
|
|
80050bc: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80050be: 683b ldr r3, [r7, #0]
|
|
80050c0: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80050c2: 683b ldr r3, [r7, #0]
|
|
80050c4: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80050c6: f000 fcb3 bl 8005a30 <TIM_ETR_SetConfig>
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80050ca: 687b ldr r3, [r7, #4]
|
|
80050cc: 681b ldr r3, [r3, #0]
|
|
80050ce: 689b ldr r3, [r3, #8]
|
|
80050d0: 60bb str r3, [r7, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
80050d2: 68bb ldr r3, [r7, #8]
|
|
80050d4: f043 0377 orr.w r3, r3, #119 @ 0x77
|
|
80050d8: 60bb str r3, [r7, #8]
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80050da: 687b ldr r3, [r7, #4]
|
|
80050dc: 681b ldr r3, [r3, #0]
|
|
80050de: 68ba ldr r2, [r7, #8]
|
|
80050e0: 609a str r2, [r3, #8]
|
|
break;
|
|
80050e2: e04f b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80050e4: 687b ldr r3, [r7, #4]
|
|
80050e6: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
80050e8: 683b ldr r3, [r7, #0]
|
|
80050ea: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80050ec: 683b ldr r3, [r7, #0]
|
|
80050ee: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80050f0: 683b ldr r3, [r7, #0]
|
|
80050f2: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80050f4: f000 fc9c bl 8005a30 <TIM_ETR_SetConfig>
|
|
/* Enable the External clock mode2 */
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
80050f8: 687b ldr r3, [r7, #4]
|
|
80050fa: 681b ldr r3, [r3, #0]
|
|
80050fc: 689a ldr r2, [r3, #8]
|
|
80050fe: 687b ldr r3, [r7, #4]
|
|
8005100: 681b ldr r3, [r3, #0]
|
|
8005102: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8005106: 609a str r2, [r3, #8]
|
|
break;
|
|
8005108: e03c b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800510a: 687b ldr r3, [r7, #4]
|
|
800510c: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
800510e: 683b ldr r3, [r7, #0]
|
|
8005110: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005112: 683b ldr r3, [r7, #0]
|
|
8005114: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005116: 461a mov r2, r3
|
|
8005118: f000 fc0e bl 8005938 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
800511c: 687b ldr r3, [r7, #4]
|
|
800511e: 681b ldr r3, [r3, #0]
|
|
8005120: 2150 movs r1, #80 @ 0x50
|
|
8005122: 4618 mov r0, r3
|
|
8005124: f000 fc67 bl 80059f6 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005128: e02c b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
800512a: 687b ldr r3, [r7, #4]
|
|
800512c: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
800512e: 683b ldr r3, [r7, #0]
|
|
8005130: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005132: 683b ldr r3, [r7, #0]
|
|
8005134: 68db ldr r3, [r3, #12]
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
8005136: 461a mov r2, r3
|
|
8005138: f000 fc2d bl 8005996 <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
800513c: 687b ldr r3, [r7, #4]
|
|
800513e: 681b ldr r3, [r3, #0]
|
|
8005140: 2160 movs r1, #96 @ 0x60
|
|
8005142: 4618 mov r0, r3
|
|
8005144: f000 fc57 bl 80059f6 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005148: e01c b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800514a: 687b ldr r3, [r7, #4]
|
|
800514c: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
800514e: 683b ldr r3, [r7, #0]
|
|
8005150: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005152: 683b ldr r3, [r7, #0]
|
|
8005154: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005156: 461a mov r2, r3
|
|
8005158: f000 fbee bl 8005938 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
800515c: 687b ldr r3, [r7, #4]
|
|
800515e: 681b ldr r3, [r3, #0]
|
|
8005160: 2140 movs r1, #64 @ 0x40
|
|
8005162: 4618 mov r0, r3
|
|
8005164: f000 fc47 bl 80059f6 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005168: e00c b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
case TIM_CLOCKSOURCE_ITR11:
|
|
{
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
800516a: 687b ldr r3, [r7, #4]
|
|
800516c: 681a ldr r2, [r3, #0]
|
|
800516e: 683b ldr r3, [r7, #0]
|
|
8005170: 681b ldr r3, [r3, #0]
|
|
8005172: 4619 mov r1, r3
|
|
8005174: 4610 mov r0, r2
|
|
8005176: f000 fc3e bl 80059f6 <TIM_ITRx_SetConfig>
|
|
break;
|
|
800517a: e003 b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
800517c: 2301 movs r3, #1
|
|
800517e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8005180: e000 b.n 8005184 <HAL_TIM_ConfigClockSource+0x1c8>
|
|
break;
|
|
8005182: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005184: 687b ldr r3, [r7, #4]
|
|
8005186: 2201 movs r2, #1
|
|
8005188: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800518c: 687b ldr r3, [r7, #4]
|
|
800518e: 2200 movs r2, #0
|
|
8005190: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8005194: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8005196: 4618 mov r0, r3
|
|
8005198: 3710 adds r7, #16
|
|
800519a: 46bd mov sp, r7
|
|
800519c: bd80 pop {r7, pc}
|
|
800519e: bf00 nop
|
|
80051a0: 00100070 .word 0x00100070
|
|
80051a4: 00100040 .word 0x00100040
|
|
80051a8: 00100030 .word 0x00100030
|
|
80051ac: 00100020 .word 0x00100020
|
|
|
|
080051b0 <HAL_TIM_PeriodElapsedCallback>:
|
|
* @brief Period elapsed callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80051b0: b480 push {r7}
|
|
80051b2: b083 sub sp, #12
|
|
80051b4: af00 add r7, sp, #0
|
|
80051b6: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80051b8: bf00 nop
|
|
80051ba: 370c adds r7, #12
|
|
80051bc: 46bd mov sp, r7
|
|
80051be: f85d 7b04 ldr.w r7, [sp], #4
|
|
80051c2: 4770 bx lr
|
|
|
|
080051c4 <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80051c4: b480 push {r7}
|
|
80051c6: b083 sub sp, #12
|
|
80051c8: af00 add r7, sp, #0
|
|
80051ca: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80051cc: bf00 nop
|
|
80051ce: 370c adds r7, #12
|
|
80051d0: 46bd mov sp, r7
|
|
80051d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80051d6: 4770 bx lr
|
|
|
|
080051d8 <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80051d8: b480 push {r7}
|
|
80051da: b083 sub sp, #12
|
|
80051dc: af00 add r7, sp, #0
|
|
80051de: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80051e0: bf00 nop
|
|
80051e2: 370c adds r7, #12
|
|
80051e4: 46bd mov sp, r7
|
|
80051e6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80051ea: 4770 bx lr
|
|
|
|
080051ec <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80051ec: b480 push {r7}
|
|
80051ee: b083 sub sp, #12
|
|
80051f0: af00 add r7, sp, #0
|
|
80051f2: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80051f4: bf00 nop
|
|
80051f6: 370c adds r7, #12
|
|
80051f8: 46bd mov sp, r7
|
|
80051fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80051fe: 4770 bx lr
|
|
|
|
08005200 <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005200: b480 push {r7}
|
|
8005202: b083 sub sp, #12
|
|
8005204: af00 add r7, sp, #0
|
|
8005206: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005208: bf00 nop
|
|
800520a: 370c adds r7, #12
|
|
800520c: 46bd mov sp, r7
|
|
800520e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005212: 4770 bx lr
|
|
|
|
08005214 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8005214: b480 push {r7}
|
|
8005216: b085 sub sp, #20
|
|
8005218: af00 add r7, sp, #0
|
|
800521a: 6078 str r0, [r7, #4]
|
|
800521c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800521e: 687b ldr r3, [r7, #4]
|
|
8005220: 681b ldr r3, [r3, #0]
|
|
8005222: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8005224: 687b ldr r3, [r7, #4]
|
|
8005226: 4a42 ldr r2, [pc, #264] @ (8005330 <TIM_Base_SetConfig+0x11c>)
|
|
8005228: 4293 cmp r3, r2
|
|
800522a: d00f beq.n 800524c <TIM_Base_SetConfig+0x38>
|
|
800522c: 687b ldr r3, [r7, #4]
|
|
800522e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005232: d00b beq.n 800524c <TIM_Base_SetConfig+0x38>
|
|
8005234: 687b ldr r3, [r7, #4]
|
|
8005236: 4a3f ldr r2, [pc, #252] @ (8005334 <TIM_Base_SetConfig+0x120>)
|
|
8005238: 4293 cmp r3, r2
|
|
800523a: d007 beq.n 800524c <TIM_Base_SetConfig+0x38>
|
|
800523c: 687b ldr r3, [r7, #4]
|
|
800523e: 4a3e ldr r2, [pc, #248] @ (8005338 <TIM_Base_SetConfig+0x124>)
|
|
8005240: 4293 cmp r3, r2
|
|
8005242: d003 beq.n 800524c <TIM_Base_SetConfig+0x38>
|
|
8005244: 687b ldr r3, [r7, #4]
|
|
8005246: 4a3d ldr r2, [pc, #244] @ (800533c <TIM_Base_SetConfig+0x128>)
|
|
8005248: 4293 cmp r3, r2
|
|
800524a: d108 bne.n 800525e <TIM_Base_SetConfig+0x4a>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
800524c: 68fb ldr r3, [r7, #12]
|
|
800524e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005252: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
8005254: 683b ldr r3, [r7, #0]
|
|
8005256: 685b ldr r3, [r3, #4]
|
|
8005258: 68fa ldr r2, [r7, #12]
|
|
800525a: 4313 orrs r3, r2
|
|
800525c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
800525e: 687b ldr r3, [r7, #4]
|
|
8005260: 4a33 ldr r2, [pc, #204] @ (8005330 <TIM_Base_SetConfig+0x11c>)
|
|
8005262: 4293 cmp r3, r2
|
|
8005264: d01b beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
8005266: 687b ldr r3, [r7, #4]
|
|
8005268: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800526c: d017 beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
800526e: 687b ldr r3, [r7, #4]
|
|
8005270: 4a30 ldr r2, [pc, #192] @ (8005334 <TIM_Base_SetConfig+0x120>)
|
|
8005272: 4293 cmp r3, r2
|
|
8005274: d013 beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
8005276: 687b ldr r3, [r7, #4]
|
|
8005278: 4a2f ldr r2, [pc, #188] @ (8005338 <TIM_Base_SetConfig+0x124>)
|
|
800527a: 4293 cmp r3, r2
|
|
800527c: d00f beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
800527e: 687b ldr r3, [r7, #4]
|
|
8005280: 4a2e ldr r2, [pc, #184] @ (800533c <TIM_Base_SetConfig+0x128>)
|
|
8005282: 4293 cmp r3, r2
|
|
8005284: d00b beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
8005286: 687b ldr r3, [r7, #4]
|
|
8005288: 4a2d ldr r2, [pc, #180] @ (8005340 <TIM_Base_SetConfig+0x12c>)
|
|
800528a: 4293 cmp r3, r2
|
|
800528c: d007 beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
800528e: 687b ldr r3, [r7, #4]
|
|
8005290: 4a2c ldr r2, [pc, #176] @ (8005344 <TIM_Base_SetConfig+0x130>)
|
|
8005292: 4293 cmp r3, r2
|
|
8005294: d003 beq.n 800529e <TIM_Base_SetConfig+0x8a>
|
|
8005296: 687b ldr r3, [r7, #4]
|
|
8005298: 4a2b ldr r2, [pc, #172] @ (8005348 <TIM_Base_SetConfig+0x134>)
|
|
800529a: 4293 cmp r3, r2
|
|
800529c: d108 bne.n 80052b0 <TIM_Base_SetConfig+0x9c>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800529e: 68fb ldr r3, [r7, #12]
|
|
80052a0: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80052a4: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
80052a6: 683b ldr r3, [r7, #0]
|
|
80052a8: 68db ldr r3, [r3, #12]
|
|
80052aa: 68fa ldr r2, [r7, #12]
|
|
80052ac: 4313 orrs r3, r2
|
|
80052ae: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
80052b0: 68fb ldr r3, [r7, #12]
|
|
80052b2: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
80052b6: 683b ldr r3, [r7, #0]
|
|
80052b8: 695b ldr r3, [r3, #20]
|
|
80052ba: 4313 orrs r3, r2
|
|
80052bc: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
80052be: 687b ldr r3, [r7, #4]
|
|
80052c0: 68fa ldr r2, [r7, #12]
|
|
80052c2: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
80052c4: 683b ldr r3, [r7, #0]
|
|
80052c6: 689a ldr r2, [r3, #8]
|
|
80052c8: 687b ldr r3, [r7, #4]
|
|
80052ca: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
80052cc: 683b ldr r3, [r7, #0]
|
|
80052ce: 681a ldr r2, [r3, #0]
|
|
80052d0: 687b ldr r3, [r7, #4]
|
|
80052d2: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
80052d4: 687b ldr r3, [r7, #4]
|
|
80052d6: 4a16 ldr r2, [pc, #88] @ (8005330 <TIM_Base_SetConfig+0x11c>)
|
|
80052d8: 4293 cmp r3, r2
|
|
80052da: d00f beq.n 80052fc <TIM_Base_SetConfig+0xe8>
|
|
80052dc: 687b ldr r3, [r7, #4]
|
|
80052de: 4a17 ldr r2, [pc, #92] @ (800533c <TIM_Base_SetConfig+0x128>)
|
|
80052e0: 4293 cmp r3, r2
|
|
80052e2: d00b beq.n 80052fc <TIM_Base_SetConfig+0xe8>
|
|
80052e4: 687b ldr r3, [r7, #4]
|
|
80052e6: 4a16 ldr r2, [pc, #88] @ (8005340 <TIM_Base_SetConfig+0x12c>)
|
|
80052e8: 4293 cmp r3, r2
|
|
80052ea: d007 beq.n 80052fc <TIM_Base_SetConfig+0xe8>
|
|
80052ec: 687b ldr r3, [r7, #4]
|
|
80052ee: 4a15 ldr r2, [pc, #84] @ (8005344 <TIM_Base_SetConfig+0x130>)
|
|
80052f0: 4293 cmp r3, r2
|
|
80052f2: d003 beq.n 80052fc <TIM_Base_SetConfig+0xe8>
|
|
80052f4: 687b ldr r3, [r7, #4]
|
|
80052f6: 4a14 ldr r2, [pc, #80] @ (8005348 <TIM_Base_SetConfig+0x134>)
|
|
80052f8: 4293 cmp r3, r2
|
|
80052fa: d103 bne.n 8005304 <TIM_Base_SetConfig+0xf0>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
80052fc: 683b ldr r3, [r7, #0]
|
|
80052fe: 691a ldr r2, [r3, #16]
|
|
8005300: 687b ldr r3, [r7, #4]
|
|
8005302: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8005304: 687b ldr r3, [r7, #4]
|
|
8005306: 2201 movs r2, #1
|
|
8005308: 615a str r2, [r3, #20]
|
|
|
|
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
|
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
|
800530a: 687b ldr r3, [r7, #4]
|
|
800530c: 691b ldr r3, [r3, #16]
|
|
800530e: f003 0301 and.w r3, r3, #1
|
|
8005312: 2b01 cmp r3, #1
|
|
8005314: d105 bne.n 8005322 <TIM_Base_SetConfig+0x10e>
|
|
{
|
|
/* Clear the update flag */
|
|
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
|
8005316: 687b ldr r3, [r7, #4]
|
|
8005318: 691b ldr r3, [r3, #16]
|
|
800531a: f023 0201 bic.w r2, r3, #1
|
|
800531e: 687b ldr r3, [r7, #4]
|
|
8005320: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
8005322: bf00 nop
|
|
8005324: 3714 adds r7, #20
|
|
8005326: 46bd mov sp, r7
|
|
8005328: f85d 7b04 ldr.w r7, [sp], #4
|
|
800532c: 4770 bx lr
|
|
800532e: bf00 nop
|
|
8005330: 40012c00 .word 0x40012c00
|
|
8005334: 40000400 .word 0x40000400
|
|
8005338: 40000800 .word 0x40000800
|
|
800533c: 40013400 .word 0x40013400
|
|
8005340: 40014000 .word 0x40014000
|
|
8005344: 40014400 .word 0x40014400
|
|
8005348: 40014800 .word 0x40014800
|
|
|
|
0800534c <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800534c: b480 push {r7}
|
|
800534e: b087 sub sp, #28
|
|
8005350: af00 add r7, sp, #0
|
|
8005352: 6078 str r0, [r7, #4]
|
|
8005354: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005356: 687b ldr r3, [r7, #4]
|
|
8005358: 6a1b ldr r3, [r3, #32]
|
|
800535a: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800535c: 687b ldr r3, [r7, #4]
|
|
800535e: 6a1b ldr r3, [r3, #32]
|
|
8005360: f023 0201 bic.w r2, r3, #1
|
|
8005364: 687b ldr r3, [r7, #4]
|
|
8005366: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005368: 687b ldr r3, [r7, #4]
|
|
800536a: 685b ldr r3, [r3, #4]
|
|
800536c: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800536e: 687b ldr r3, [r7, #4]
|
|
8005370: 699b ldr r3, [r3, #24]
|
|
8005372: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
8005374: 68fb ldr r3, [r7, #12]
|
|
8005376: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800537a: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800537e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8005380: 68fb ldr r3, [r7, #12]
|
|
8005382: f023 0303 bic.w r3, r3, #3
|
|
8005386: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8005388: 683b ldr r3, [r7, #0]
|
|
800538a: 681b ldr r3, [r3, #0]
|
|
800538c: 68fa ldr r2, [r7, #12]
|
|
800538e: 4313 orrs r3, r2
|
|
8005390: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8005392: 697b ldr r3, [r7, #20]
|
|
8005394: f023 0302 bic.w r3, r3, #2
|
|
8005398: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
800539a: 683b ldr r3, [r7, #0]
|
|
800539c: 689b ldr r3, [r3, #8]
|
|
800539e: 697a ldr r2, [r7, #20]
|
|
80053a0: 4313 orrs r3, r2
|
|
80053a2: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
80053a4: 687b ldr r3, [r7, #4]
|
|
80053a6: 4a2c ldr r2, [pc, #176] @ (8005458 <TIM_OC1_SetConfig+0x10c>)
|
|
80053a8: 4293 cmp r3, r2
|
|
80053aa: d00f beq.n 80053cc <TIM_OC1_SetConfig+0x80>
|
|
80053ac: 687b ldr r3, [r7, #4]
|
|
80053ae: 4a2b ldr r2, [pc, #172] @ (800545c <TIM_OC1_SetConfig+0x110>)
|
|
80053b0: 4293 cmp r3, r2
|
|
80053b2: d00b beq.n 80053cc <TIM_OC1_SetConfig+0x80>
|
|
80053b4: 687b ldr r3, [r7, #4]
|
|
80053b6: 4a2a ldr r2, [pc, #168] @ (8005460 <TIM_OC1_SetConfig+0x114>)
|
|
80053b8: 4293 cmp r3, r2
|
|
80053ba: d007 beq.n 80053cc <TIM_OC1_SetConfig+0x80>
|
|
80053bc: 687b ldr r3, [r7, #4]
|
|
80053be: 4a29 ldr r2, [pc, #164] @ (8005464 <TIM_OC1_SetConfig+0x118>)
|
|
80053c0: 4293 cmp r3, r2
|
|
80053c2: d003 beq.n 80053cc <TIM_OC1_SetConfig+0x80>
|
|
80053c4: 687b ldr r3, [r7, #4]
|
|
80053c6: 4a28 ldr r2, [pc, #160] @ (8005468 <TIM_OC1_SetConfig+0x11c>)
|
|
80053c8: 4293 cmp r3, r2
|
|
80053ca: d10c bne.n 80053e6 <TIM_OC1_SetConfig+0x9a>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
80053cc: 697b ldr r3, [r7, #20]
|
|
80053ce: f023 0308 bic.w r3, r3, #8
|
|
80053d2: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
80053d4: 683b ldr r3, [r7, #0]
|
|
80053d6: 68db ldr r3, [r3, #12]
|
|
80053d8: 697a ldr r2, [r7, #20]
|
|
80053da: 4313 orrs r3, r2
|
|
80053dc: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
80053de: 697b ldr r3, [r7, #20]
|
|
80053e0: f023 0304 bic.w r3, r3, #4
|
|
80053e4: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80053e6: 687b ldr r3, [r7, #4]
|
|
80053e8: 4a1b ldr r2, [pc, #108] @ (8005458 <TIM_OC1_SetConfig+0x10c>)
|
|
80053ea: 4293 cmp r3, r2
|
|
80053ec: d00f beq.n 800540e <TIM_OC1_SetConfig+0xc2>
|
|
80053ee: 687b ldr r3, [r7, #4]
|
|
80053f0: 4a1a ldr r2, [pc, #104] @ (800545c <TIM_OC1_SetConfig+0x110>)
|
|
80053f2: 4293 cmp r3, r2
|
|
80053f4: d00b beq.n 800540e <TIM_OC1_SetConfig+0xc2>
|
|
80053f6: 687b ldr r3, [r7, #4]
|
|
80053f8: 4a19 ldr r2, [pc, #100] @ (8005460 <TIM_OC1_SetConfig+0x114>)
|
|
80053fa: 4293 cmp r3, r2
|
|
80053fc: d007 beq.n 800540e <TIM_OC1_SetConfig+0xc2>
|
|
80053fe: 687b ldr r3, [r7, #4]
|
|
8005400: 4a18 ldr r2, [pc, #96] @ (8005464 <TIM_OC1_SetConfig+0x118>)
|
|
8005402: 4293 cmp r3, r2
|
|
8005404: d003 beq.n 800540e <TIM_OC1_SetConfig+0xc2>
|
|
8005406: 687b ldr r3, [r7, #4]
|
|
8005408: 4a17 ldr r2, [pc, #92] @ (8005468 <TIM_OC1_SetConfig+0x11c>)
|
|
800540a: 4293 cmp r3, r2
|
|
800540c: d111 bne.n 8005432 <TIM_OC1_SetConfig+0xe6>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
800540e: 693b ldr r3, [r7, #16]
|
|
8005410: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8005414: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8005416: 693b ldr r3, [r7, #16]
|
|
8005418: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
800541c: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
800541e: 683b ldr r3, [r7, #0]
|
|
8005420: 695b ldr r3, [r3, #20]
|
|
8005422: 693a ldr r2, [r7, #16]
|
|
8005424: 4313 orrs r3, r2
|
|
8005426: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8005428: 683b ldr r3, [r7, #0]
|
|
800542a: 699b ldr r3, [r3, #24]
|
|
800542c: 693a ldr r2, [r7, #16]
|
|
800542e: 4313 orrs r3, r2
|
|
8005430: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005432: 687b ldr r3, [r7, #4]
|
|
8005434: 693a ldr r2, [r7, #16]
|
|
8005436: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8005438: 687b ldr r3, [r7, #4]
|
|
800543a: 68fa ldr r2, [r7, #12]
|
|
800543c: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
800543e: 683b ldr r3, [r7, #0]
|
|
8005440: 685a ldr r2, [r3, #4]
|
|
8005442: 687b ldr r3, [r7, #4]
|
|
8005444: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005446: 687b ldr r3, [r7, #4]
|
|
8005448: 697a ldr r2, [r7, #20]
|
|
800544a: 621a str r2, [r3, #32]
|
|
}
|
|
800544c: bf00 nop
|
|
800544e: 371c adds r7, #28
|
|
8005450: 46bd mov sp, r7
|
|
8005452: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005456: 4770 bx lr
|
|
8005458: 40012c00 .word 0x40012c00
|
|
800545c: 40013400 .word 0x40013400
|
|
8005460: 40014000 .word 0x40014000
|
|
8005464: 40014400 .word 0x40014400
|
|
8005468: 40014800 .word 0x40014800
|
|
|
|
0800546c <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800546c: b480 push {r7}
|
|
800546e: b087 sub sp, #28
|
|
8005470: af00 add r7, sp, #0
|
|
8005472: 6078 str r0, [r7, #4]
|
|
8005474: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005476: 687b ldr r3, [r7, #4]
|
|
8005478: 6a1b ldr r3, [r3, #32]
|
|
800547a: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
800547c: 687b ldr r3, [r7, #4]
|
|
800547e: 6a1b ldr r3, [r3, #32]
|
|
8005480: f023 0210 bic.w r2, r3, #16
|
|
8005484: 687b ldr r3, [r7, #4]
|
|
8005486: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005488: 687b ldr r3, [r7, #4]
|
|
800548a: 685b ldr r3, [r3, #4]
|
|
800548c: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800548e: 687b ldr r3, [r7, #4]
|
|
8005490: 699b ldr r3, [r3, #24]
|
|
8005492: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
8005494: 68fb ldr r3, [r7, #12]
|
|
8005496: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800549a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800549e: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
80054a0: 68fb ldr r3, [r7, #12]
|
|
80054a2: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80054a6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80054a8: 683b ldr r3, [r7, #0]
|
|
80054aa: 681b ldr r3, [r3, #0]
|
|
80054ac: 021b lsls r3, r3, #8
|
|
80054ae: 68fa ldr r2, [r7, #12]
|
|
80054b0: 4313 orrs r3, r2
|
|
80054b2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
80054b4: 697b ldr r3, [r7, #20]
|
|
80054b6: f023 0320 bic.w r3, r3, #32
|
|
80054ba: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
80054bc: 683b ldr r3, [r7, #0]
|
|
80054be: 689b ldr r3, [r3, #8]
|
|
80054c0: 011b lsls r3, r3, #4
|
|
80054c2: 697a ldr r2, [r7, #20]
|
|
80054c4: 4313 orrs r3, r2
|
|
80054c6: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
80054c8: 687b ldr r3, [r7, #4]
|
|
80054ca: 4a28 ldr r2, [pc, #160] @ (800556c <TIM_OC2_SetConfig+0x100>)
|
|
80054cc: 4293 cmp r3, r2
|
|
80054ce: d003 beq.n 80054d8 <TIM_OC2_SetConfig+0x6c>
|
|
80054d0: 687b ldr r3, [r7, #4]
|
|
80054d2: 4a27 ldr r2, [pc, #156] @ (8005570 <TIM_OC2_SetConfig+0x104>)
|
|
80054d4: 4293 cmp r3, r2
|
|
80054d6: d10d bne.n 80054f4 <TIM_OC2_SetConfig+0x88>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
80054d8: 697b ldr r3, [r7, #20]
|
|
80054da: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
80054de: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
80054e0: 683b ldr r3, [r7, #0]
|
|
80054e2: 68db ldr r3, [r3, #12]
|
|
80054e4: 011b lsls r3, r3, #4
|
|
80054e6: 697a ldr r2, [r7, #20]
|
|
80054e8: 4313 orrs r3, r2
|
|
80054ea: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
80054ec: 697b ldr r3, [r7, #20]
|
|
80054ee: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80054f2: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80054f4: 687b ldr r3, [r7, #4]
|
|
80054f6: 4a1d ldr r2, [pc, #116] @ (800556c <TIM_OC2_SetConfig+0x100>)
|
|
80054f8: 4293 cmp r3, r2
|
|
80054fa: d00f beq.n 800551c <TIM_OC2_SetConfig+0xb0>
|
|
80054fc: 687b ldr r3, [r7, #4]
|
|
80054fe: 4a1c ldr r2, [pc, #112] @ (8005570 <TIM_OC2_SetConfig+0x104>)
|
|
8005500: 4293 cmp r3, r2
|
|
8005502: d00b beq.n 800551c <TIM_OC2_SetConfig+0xb0>
|
|
8005504: 687b ldr r3, [r7, #4]
|
|
8005506: 4a1b ldr r2, [pc, #108] @ (8005574 <TIM_OC2_SetConfig+0x108>)
|
|
8005508: 4293 cmp r3, r2
|
|
800550a: d007 beq.n 800551c <TIM_OC2_SetConfig+0xb0>
|
|
800550c: 687b ldr r3, [r7, #4]
|
|
800550e: 4a1a ldr r2, [pc, #104] @ (8005578 <TIM_OC2_SetConfig+0x10c>)
|
|
8005510: 4293 cmp r3, r2
|
|
8005512: d003 beq.n 800551c <TIM_OC2_SetConfig+0xb0>
|
|
8005514: 687b ldr r3, [r7, #4]
|
|
8005516: 4a19 ldr r2, [pc, #100] @ (800557c <TIM_OC2_SetConfig+0x110>)
|
|
8005518: 4293 cmp r3, r2
|
|
800551a: d113 bne.n 8005544 <TIM_OC2_SetConfig+0xd8>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
800551c: 693b ldr r3, [r7, #16]
|
|
800551e: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8005522: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8005524: 693b ldr r3, [r7, #16]
|
|
8005526: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
800552a: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
800552c: 683b ldr r3, [r7, #0]
|
|
800552e: 695b ldr r3, [r3, #20]
|
|
8005530: 009b lsls r3, r3, #2
|
|
8005532: 693a ldr r2, [r7, #16]
|
|
8005534: 4313 orrs r3, r2
|
|
8005536: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8005538: 683b ldr r3, [r7, #0]
|
|
800553a: 699b ldr r3, [r3, #24]
|
|
800553c: 009b lsls r3, r3, #2
|
|
800553e: 693a ldr r2, [r7, #16]
|
|
8005540: 4313 orrs r3, r2
|
|
8005542: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005544: 687b ldr r3, [r7, #4]
|
|
8005546: 693a ldr r2, [r7, #16]
|
|
8005548: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800554a: 687b ldr r3, [r7, #4]
|
|
800554c: 68fa ldr r2, [r7, #12]
|
|
800554e: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8005550: 683b ldr r3, [r7, #0]
|
|
8005552: 685a ldr r2, [r3, #4]
|
|
8005554: 687b ldr r3, [r7, #4]
|
|
8005556: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005558: 687b ldr r3, [r7, #4]
|
|
800555a: 697a ldr r2, [r7, #20]
|
|
800555c: 621a str r2, [r3, #32]
|
|
}
|
|
800555e: bf00 nop
|
|
8005560: 371c adds r7, #28
|
|
8005562: 46bd mov sp, r7
|
|
8005564: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005568: 4770 bx lr
|
|
800556a: bf00 nop
|
|
800556c: 40012c00 .word 0x40012c00
|
|
8005570: 40013400 .word 0x40013400
|
|
8005574: 40014000 .word 0x40014000
|
|
8005578: 40014400 .word 0x40014400
|
|
800557c: 40014800 .word 0x40014800
|
|
|
|
08005580 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005580: b480 push {r7}
|
|
8005582: b087 sub sp, #28
|
|
8005584: af00 add r7, sp, #0
|
|
8005586: 6078 str r0, [r7, #4]
|
|
8005588: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800558a: 687b ldr r3, [r7, #4]
|
|
800558c: 6a1b ldr r3, [r3, #32]
|
|
800558e: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8005590: 687b ldr r3, [r7, #4]
|
|
8005592: 6a1b ldr r3, [r3, #32]
|
|
8005594: f423 7280 bic.w r2, r3, #256 @ 0x100
|
|
8005598: 687b ldr r3, [r7, #4]
|
|
800559a: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800559c: 687b ldr r3, [r7, #4]
|
|
800559e: 685b ldr r3, [r3, #4]
|
|
80055a0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80055a2: 687b ldr r3, [r7, #4]
|
|
80055a4: 69db ldr r3, [r3, #28]
|
|
80055a6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
80055a8: 68fb ldr r3, [r7, #12]
|
|
80055aa: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80055ae: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80055b2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
80055b4: 68fb ldr r3, [r7, #12]
|
|
80055b6: f023 0303 bic.w r3, r3, #3
|
|
80055ba: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80055bc: 683b ldr r3, [r7, #0]
|
|
80055be: 681b ldr r3, [r3, #0]
|
|
80055c0: 68fa ldr r2, [r7, #12]
|
|
80055c2: 4313 orrs r3, r2
|
|
80055c4: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
80055c6: 697b ldr r3, [r7, #20]
|
|
80055c8: f423 7300 bic.w r3, r3, #512 @ 0x200
|
|
80055cc: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
80055ce: 683b ldr r3, [r7, #0]
|
|
80055d0: 689b ldr r3, [r3, #8]
|
|
80055d2: 021b lsls r3, r3, #8
|
|
80055d4: 697a ldr r2, [r7, #20]
|
|
80055d6: 4313 orrs r3, r2
|
|
80055d8: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
80055da: 687b ldr r3, [r7, #4]
|
|
80055dc: 4a27 ldr r2, [pc, #156] @ (800567c <TIM_OC3_SetConfig+0xfc>)
|
|
80055de: 4293 cmp r3, r2
|
|
80055e0: d003 beq.n 80055ea <TIM_OC3_SetConfig+0x6a>
|
|
80055e2: 687b ldr r3, [r7, #4]
|
|
80055e4: 4a26 ldr r2, [pc, #152] @ (8005680 <TIM_OC3_SetConfig+0x100>)
|
|
80055e6: 4293 cmp r3, r2
|
|
80055e8: d10d bne.n 8005606 <TIM_OC3_SetConfig+0x86>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
80055ea: 697b ldr r3, [r7, #20]
|
|
80055ec: f423 6300 bic.w r3, r3, #2048 @ 0x800
|
|
80055f0: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
80055f2: 683b ldr r3, [r7, #0]
|
|
80055f4: 68db ldr r3, [r3, #12]
|
|
80055f6: 021b lsls r3, r3, #8
|
|
80055f8: 697a ldr r2, [r7, #20]
|
|
80055fa: 4313 orrs r3, r2
|
|
80055fc: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
80055fe: 697b ldr r3, [r7, #20]
|
|
8005600: f423 6380 bic.w r3, r3, #1024 @ 0x400
|
|
8005604: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005606: 687b ldr r3, [r7, #4]
|
|
8005608: 4a1c ldr r2, [pc, #112] @ (800567c <TIM_OC3_SetConfig+0xfc>)
|
|
800560a: 4293 cmp r3, r2
|
|
800560c: d00f beq.n 800562e <TIM_OC3_SetConfig+0xae>
|
|
800560e: 687b ldr r3, [r7, #4]
|
|
8005610: 4a1b ldr r2, [pc, #108] @ (8005680 <TIM_OC3_SetConfig+0x100>)
|
|
8005612: 4293 cmp r3, r2
|
|
8005614: d00b beq.n 800562e <TIM_OC3_SetConfig+0xae>
|
|
8005616: 687b ldr r3, [r7, #4]
|
|
8005618: 4a1a ldr r2, [pc, #104] @ (8005684 <TIM_OC3_SetConfig+0x104>)
|
|
800561a: 4293 cmp r3, r2
|
|
800561c: d007 beq.n 800562e <TIM_OC3_SetConfig+0xae>
|
|
800561e: 687b ldr r3, [r7, #4]
|
|
8005620: 4a19 ldr r2, [pc, #100] @ (8005688 <TIM_OC3_SetConfig+0x108>)
|
|
8005622: 4293 cmp r3, r2
|
|
8005624: d003 beq.n 800562e <TIM_OC3_SetConfig+0xae>
|
|
8005626: 687b ldr r3, [r7, #4]
|
|
8005628: 4a18 ldr r2, [pc, #96] @ (800568c <TIM_OC3_SetConfig+0x10c>)
|
|
800562a: 4293 cmp r3, r2
|
|
800562c: d113 bne.n 8005656 <TIM_OC3_SetConfig+0xd6>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
800562e: 693b ldr r3, [r7, #16]
|
|
8005630: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
8005634: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
8005636: 693b ldr r3, [r7, #16]
|
|
8005638: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
800563c: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
800563e: 683b ldr r3, [r7, #0]
|
|
8005640: 695b ldr r3, [r3, #20]
|
|
8005642: 011b lsls r3, r3, #4
|
|
8005644: 693a ldr r2, [r7, #16]
|
|
8005646: 4313 orrs r3, r2
|
|
8005648: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
800564a: 683b ldr r3, [r7, #0]
|
|
800564c: 699b ldr r3, [r3, #24]
|
|
800564e: 011b lsls r3, r3, #4
|
|
8005650: 693a ldr r2, [r7, #16]
|
|
8005652: 4313 orrs r3, r2
|
|
8005654: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005656: 687b ldr r3, [r7, #4]
|
|
8005658: 693a ldr r2, [r7, #16]
|
|
800565a: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800565c: 687b ldr r3, [r7, #4]
|
|
800565e: 68fa ldr r2, [r7, #12]
|
|
8005660: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
8005662: 683b ldr r3, [r7, #0]
|
|
8005664: 685a ldr r2, [r3, #4]
|
|
8005666: 687b ldr r3, [r7, #4]
|
|
8005668: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800566a: 687b ldr r3, [r7, #4]
|
|
800566c: 697a ldr r2, [r7, #20]
|
|
800566e: 621a str r2, [r3, #32]
|
|
}
|
|
8005670: bf00 nop
|
|
8005672: 371c adds r7, #28
|
|
8005674: 46bd mov sp, r7
|
|
8005676: f85d 7b04 ldr.w r7, [sp], #4
|
|
800567a: 4770 bx lr
|
|
800567c: 40012c00 .word 0x40012c00
|
|
8005680: 40013400 .word 0x40013400
|
|
8005684: 40014000 .word 0x40014000
|
|
8005688: 40014400 .word 0x40014400
|
|
800568c: 40014800 .word 0x40014800
|
|
|
|
08005690 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8005690: b480 push {r7}
|
|
8005692: b087 sub sp, #28
|
|
8005694: af00 add r7, sp, #0
|
|
8005696: 6078 str r0, [r7, #4]
|
|
8005698: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800569a: 687b ldr r3, [r7, #4]
|
|
800569c: 6a1b ldr r3, [r3, #32]
|
|
800569e: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
80056a0: 687b ldr r3, [r7, #4]
|
|
80056a2: 6a1b ldr r3, [r3, #32]
|
|
80056a4: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
80056a8: 687b ldr r3, [r7, #4]
|
|
80056aa: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80056ac: 687b ldr r3, [r7, #4]
|
|
80056ae: 685b ldr r3, [r3, #4]
|
|
80056b0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
80056b2: 687b ldr r3, [r7, #4]
|
|
80056b4: 69db ldr r3, [r3, #28]
|
|
80056b6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
80056b8: 68fb ldr r3, [r7, #12]
|
|
80056ba: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
80056be: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
80056c2: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
80056c4: 68fb ldr r3, [r7, #12]
|
|
80056c6: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80056ca: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80056cc: 683b ldr r3, [r7, #0]
|
|
80056ce: 681b ldr r3, [r3, #0]
|
|
80056d0: 021b lsls r3, r3, #8
|
|
80056d2: 68fa ldr r2, [r7, #12]
|
|
80056d4: 4313 orrs r3, r2
|
|
80056d6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
80056d8: 697b ldr r3, [r7, #20]
|
|
80056da: f423 5300 bic.w r3, r3, #8192 @ 0x2000
|
|
80056de: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
80056e0: 683b ldr r3, [r7, #0]
|
|
80056e2: 689b ldr r3, [r3, #8]
|
|
80056e4: 031b lsls r3, r3, #12
|
|
80056e6: 697a ldr r2, [r7, #20]
|
|
80056e8: 4313 orrs r3, r2
|
|
80056ea: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
|
|
80056ec: 687b ldr r3, [r7, #4]
|
|
80056ee: 4a28 ldr r2, [pc, #160] @ (8005790 <TIM_OC4_SetConfig+0x100>)
|
|
80056f0: 4293 cmp r3, r2
|
|
80056f2: d003 beq.n 80056fc <TIM_OC4_SetConfig+0x6c>
|
|
80056f4: 687b ldr r3, [r7, #4]
|
|
80056f6: 4a27 ldr r2, [pc, #156] @ (8005794 <TIM_OC4_SetConfig+0x104>)
|
|
80056f8: 4293 cmp r3, r2
|
|
80056fa: d10d bne.n 8005718 <TIM_OC4_SetConfig+0x88>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4NP;
|
|
80056fc: 697b ldr r3, [r7, #20]
|
|
80056fe: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
8005702: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 12U);
|
|
8005704: 683b ldr r3, [r7, #0]
|
|
8005706: 68db ldr r3, [r3, #12]
|
|
8005708: 031b lsls r3, r3, #12
|
|
800570a: 697a ldr r2, [r7, #20]
|
|
800570c: 4313 orrs r3, r2
|
|
800570e: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC4NE;
|
|
8005710: 697b ldr r3, [r7, #20]
|
|
8005712: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8005716: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8005718: 687b ldr r3, [r7, #4]
|
|
800571a: 4a1d ldr r2, [pc, #116] @ (8005790 <TIM_OC4_SetConfig+0x100>)
|
|
800571c: 4293 cmp r3, r2
|
|
800571e: d00f beq.n 8005740 <TIM_OC4_SetConfig+0xb0>
|
|
8005720: 687b ldr r3, [r7, #4]
|
|
8005722: 4a1c ldr r2, [pc, #112] @ (8005794 <TIM_OC4_SetConfig+0x104>)
|
|
8005724: 4293 cmp r3, r2
|
|
8005726: d00b beq.n 8005740 <TIM_OC4_SetConfig+0xb0>
|
|
8005728: 687b ldr r3, [r7, #4]
|
|
800572a: 4a1b ldr r2, [pc, #108] @ (8005798 <TIM_OC4_SetConfig+0x108>)
|
|
800572c: 4293 cmp r3, r2
|
|
800572e: d007 beq.n 8005740 <TIM_OC4_SetConfig+0xb0>
|
|
8005730: 687b ldr r3, [r7, #4]
|
|
8005732: 4a1a ldr r2, [pc, #104] @ (800579c <TIM_OC4_SetConfig+0x10c>)
|
|
8005734: 4293 cmp r3, r2
|
|
8005736: d003 beq.n 8005740 <TIM_OC4_SetConfig+0xb0>
|
|
8005738: 687b ldr r3, [r7, #4]
|
|
800573a: 4a19 ldr r2, [pc, #100] @ (80057a0 <TIM_OC4_SetConfig+0x110>)
|
|
800573c: 4293 cmp r3, r2
|
|
800573e: d113 bne.n 8005768 <TIM_OC4_SetConfig+0xd8>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8005740: 693b ldr r3, [r7, #16]
|
|
8005742: f423 4380 bic.w r3, r3, #16384 @ 0x4000
|
|
8005746: 613b str r3, [r7, #16]
|
|
/* Reset the Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4N;
|
|
8005748: 693b ldr r3, [r7, #16]
|
|
800574a: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
800574e: 613b str r3, [r7, #16]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8005750: 683b ldr r3, [r7, #0]
|
|
8005752: 695b ldr r3, [r3, #20]
|
|
8005754: 019b lsls r3, r3, #6
|
|
8005756: 693a ldr r2, [r7, #16]
|
|
8005758: 4313 orrs r3, r2
|
|
800575a: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 6U);
|
|
800575c: 683b ldr r3, [r7, #0]
|
|
800575e: 699b ldr r3, [r3, #24]
|
|
8005760: 019b lsls r3, r3, #6
|
|
8005762: 693a ldr r2, [r7, #16]
|
|
8005764: 4313 orrs r3, r2
|
|
8005766: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005768: 687b ldr r3, [r7, #4]
|
|
800576a: 693a ldr r2, [r7, #16]
|
|
800576c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800576e: 687b ldr r3, [r7, #4]
|
|
8005770: 68fa ldr r2, [r7, #12]
|
|
8005772: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8005774: 683b ldr r3, [r7, #0]
|
|
8005776: 685a ldr r2, [r3, #4]
|
|
8005778: 687b ldr r3, [r7, #4]
|
|
800577a: 641a str r2, [r3, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800577c: 687b ldr r3, [r7, #4]
|
|
800577e: 697a ldr r2, [r7, #20]
|
|
8005780: 621a str r2, [r3, #32]
|
|
}
|
|
8005782: bf00 nop
|
|
8005784: 371c adds r7, #28
|
|
8005786: 46bd mov sp, r7
|
|
8005788: f85d 7b04 ldr.w r7, [sp], #4
|
|
800578c: 4770 bx lr
|
|
800578e: bf00 nop
|
|
8005790: 40012c00 .word 0x40012c00
|
|
8005794: 40013400 .word 0x40013400
|
|
8005798: 40014000 .word 0x40014000
|
|
800579c: 40014400 .word 0x40014400
|
|
80057a0: 40014800 .word 0x40014800
|
|
|
|
080057a4 <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
80057a4: b480 push {r7}
|
|
80057a6: b087 sub sp, #28
|
|
80057a8: af00 add r7, sp, #0
|
|
80057aa: 6078 str r0, [r7, #4]
|
|
80057ac: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
80057ae: 687b ldr r3, [r7, #4]
|
|
80057b0: 6a1b ldr r3, [r3, #32]
|
|
80057b2: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
80057b4: 687b ldr r3, [r7, #4]
|
|
80057b6: 6a1b ldr r3, [r3, #32]
|
|
80057b8: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
80057bc: 687b ldr r3, [r7, #4]
|
|
80057be: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
80057c0: 687b ldr r3, [r7, #4]
|
|
80057c2: 685b ldr r3, [r3, #4]
|
|
80057c4: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
80057c6: 687b ldr r3, [r7, #4]
|
|
80057c8: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
80057ca: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
80057cc: 68fb ldr r3, [r7, #12]
|
|
80057ce: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80057d2: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80057d6: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
80057d8: 683b ldr r3, [r7, #0]
|
|
80057da: 681b ldr r3, [r3, #0]
|
|
80057dc: 68fa ldr r2, [r7, #12]
|
|
80057de: 4313 orrs r3, r2
|
|
80057e0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
80057e2: 693b ldr r3, [r7, #16]
|
|
80057e4: f423 3300 bic.w r3, r3, #131072 @ 0x20000
|
|
80057e8: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
80057ea: 683b ldr r3, [r7, #0]
|
|
80057ec: 689b ldr r3, [r3, #8]
|
|
80057ee: 041b lsls r3, r3, #16
|
|
80057f0: 693a ldr r2, [r7, #16]
|
|
80057f2: 4313 orrs r3, r2
|
|
80057f4: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80057f6: 687b ldr r3, [r7, #4]
|
|
80057f8: 4a17 ldr r2, [pc, #92] @ (8005858 <TIM_OC5_SetConfig+0xb4>)
|
|
80057fa: 4293 cmp r3, r2
|
|
80057fc: d00f beq.n 800581e <TIM_OC5_SetConfig+0x7a>
|
|
80057fe: 687b ldr r3, [r7, #4]
|
|
8005800: 4a16 ldr r2, [pc, #88] @ (800585c <TIM_OC5_SetConfig+0xb8>)
|
|
8005802: 4293 cmp r3, r2
|
|
8005804: d00b beq.n 800581e <TIM_OC5_SetConfig+0x7a>
|
|
8005806: 687b ldr r3, [r7, #4]
|
|
8005808: 4a15 ldr r2, [pc, #84] @ (8005860 <TIM_OC5_SetConfig+0xbc>)
|
|
800580a: 4293 cmp r3, r2
|
|
800580c: d007 beq.n 800581e <TIM_OC5_SetConfig+0x7a>
|
|
800580e: 687b ldr r3, [r7, #4]
|
|
8005810: 4a14 ldr r2, [pc, #80] @ (8005864 <TIM_OC5_SetConfig+0xc0>)
|
|
8005812: 4293 cmp r3, r2
|
|
8005814: d003 beq.n 800581e <TIM_OC5_SetConfig+0x7a>
|
|
8005816: 687b ldr r3, [r7, #4]
|
|
8005818: 4a13 ldr r2, [pc, #76] @ (8005868 <TIM_OC5_SetConfig+0xc4>)
|
|
800581a: 4293 cmp r3, r2
|
|
800581c: d109 bne.n 8005832 <TIM_OC5_SetConfig+0x8e>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
800581e: 697b ldr r3, [r7, #20]
|
|
8005820: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8005824: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
8005826: 683b ldr r3, [r7, #0]
|
|
8005828: 695b ldr r3, [r3, #20]
|
|
800582a: 021b lsls r3, r3, #8
|
|
800582c: 697a ldr r2, [r7, #20]
|
|
800582e: 4313 orrs r3, r2
|
|
8005830: 617b str r3, [r7, #20]
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8005832: 687b ldr r3, [r7, #4]
|
|
8005834: 697a ldr r2, [r7, #20]
|
|
8005836: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8005838: 687b ldr r3, [r7, #4]
|
|
800583a: 68fa ldr r2, [r7, #12]
|
|
800583c: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
800583e: 683b ldr r3, [r7, #0]
|
|
8005840: 685a ldr r2, [r3, #4]
|
|
8005842: 687b ldr r3, [r7, #4]
|
|
8005844: 649a str r2, [r3, #72] @ 0x48
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005846: 687b ldr r3, [r7, #4]
|
|
8005848: 693a ldr r2, [r7, #16]
|
|
800584a: 621a str r2, [r3, #32]
|
|
}
|
|
800584c: bf00 nop
|
|
800584e: 371c adds r7, #28
|
|
8005850: 46bd mov sp, r7
|
|
8005852: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005856: 4770 bx lr
|
|
8005858: 40012c00 .word 0x40012c00
|
|
800585c: 40013400 .word 0x40013400
|
|
8005860: 40014000 .word 0x40014000
|
|
8005864: 40014400 .word 0x40014400
|
|
8005868: 40014800 .word 0x40014800
|
|
|
|
0800586c <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800586c: b480 push {r7}
|
|
800586e: b087 sub sp, #28
|
|
8005870: af00 add r7, sp, #0
|
|
8005872: 6078 str r0, [r7, #4]
|
|
8005874: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8005876: 687b ldr r3, [r7, #4]
|
|
8005878: 6a1b ldr r3, [r3, #32]
|
|
800587a: 613b str r3, [r7, #16]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
800587c: 687b ldr r3, [r7, #4]
|
|
800587e: 6a1b ldr r3, [r3, #32]
|
|
8005880: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
|
|
8005884: 687b ldr r3, [r7, #4]
|
|
8005886: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8005888: 687b ldr r3, [r7, #4]
|
|
800588a: 685b ldr r3, [r3, #4]
|
|
800588c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
800588e: 687b ldr r3, [r7, #4]
|
|
8005890: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8005892: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
8005894: 68fb ldr r3, [r7, #12]
|
|
8005896: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
800589a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
|
|
800589e: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
80058a0: 683b ldr r3, [r7, #0]
|
|
80058a2: 681b ldr r3, [r3, #0]
|
|
80058a4: 021b lsls r3, r3, #8
|
|
80058a6: 68fa ldr r2, [r7, #12]
|
|
80058a8: 4313 orrs r3, r2
|
|
80058aa: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
80058ac: 693b ldr r3, [r7, #16]
|
|
80058ae: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
|
|
80058b2: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
80058b4: 683b ldr r3, [r7, #0]
|
|
80058b6: 689b ldr r3, [r3, #8]
|
|
80058b8: 051b lsls r3, r3, #20
|
|
80058ba: 693a ldr r2, [r7, #16]
|
|
80058bc: 4313 orrs r3, r2
|
|
80058be: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80058c0: 687b ldr r3, [r7, #4]
|
|
80058c2: 4a18 ldr r2, [pc, #96] @ (8005924 <TIM_OC6_SetConfig+0xb8>)
|
|
80058c4: 4293 cmp r3, r2
|
|
80058c6: d00f beq.n 80058e8 <TIM_OC6_SetConfig+0x7c>
|
|
80058c8: 687b ldr r3, [r7, #4]
|
|
80058ca: 4a17 ldr r2, [pc, #92] @ (8005928 <TIM_OC6_SetConfig+0xbc>)
|
|
80058cc: 4293 cmp r3, r2
|
|
80058ce: d00b beq.n 80058e8 <TIM_OC6_SetConfig+0x7c>
|
|
80058d0: 687b ldr r3, [r7, #4]
|
|
80058d2: 4a16 ldr r2, [pc, #88] @ (800592c <TIM_OC6_SetConfig+0xc0>)
|
|
80058d4: 4293 cmp r3, r2
|
|
80058d6: d007 beq.n 80058e8 <TIM_OC6_SetConfig+0x7c>
|
|
80058d8: 687b ldr r3, [r7, #4]
|
|
80058da: 4a15 ldr r2, [pc, #84] @ (8005930 <TIM_OC6_SetConfig+0xc4>)
|
|
80058dc: 4293 cmp r3, r2
|
|
80058de: d003 beq.n 80058e8 <TIM_OC6_SetConfig+0x7c>
|
|
80058e0: 687b ldr r3, [r7, #4]
|
|
80058e2: 4a14 ldr r2, [pc, #80] @ (8005934 <TIM_OC6_SetConfig+0xc8>)
|
|
80058e4: 4293 cmp r3, r2
|
|
80058e6: d109 bne.n 80058fc <TIM_OC6_SetConfig+0x90>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
80058e8: 697b ldr r3, [r7, #20]
|
|
80058ea: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
80058ee: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
80058f0: 683b ldr r3, [r7, #0]
|
|
80058f2: 695b ldr r3, [r3, #20]
|
|
80058f4: 029b lsls r3, r3, #10
|
|
80058f6: 697a ldr r2, [r7, #20]
|
|
80058f8: 4313 orrs r3, r2
|
|
80058fa: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80058fc: 687b ldr r3, [r7, #4]
|
|
80058fe: 697a ldr r2, [r7, #20]
|
|
8005900: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8005902: 687b ldr r3, [r7, #4]
|
|
8005904: 68fa ldr r2, [r7, #12]
|
|
8005906: 651a str r2, [r3, #80] @ 0x50
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
8005908: 683b ldr r3, [r7, #0]
|
|
800590a: 685a ldr r2, [r3, #4]
|
|
800590c: 687b ldr r3, [r7, #4]
|
|
800590e: 64da str r2, [r3, #76] @ 0x4c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8005910: 687b ldr r3, [r7, #4]
|
|
8005912: 693a ldr r2, [r7, #16]
|
|
8005914: 621a str r2, [r3, #32]
|
|
}
|
|
8005916: bf00 nop
|
|
8005918: 371c adds r7, #28
|
|
800591a: 46bd mov sp, r7
|
|
800591c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005920: 4770 bx lr
|
|
8005922: bf00 nop
|
|
8005924: 40012c00 .word 0x40012c00
|
|
8005928: 40013400 .word 0x40013400
|
|
800592c: 40014000 .word 0x40014000
|
|
8005930: 40014400 .word 0x40014400
|
|
8005934: 40014800 .word 0x40014800
|
|
|
|
08005938 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8005938: b480 push {r7}
|
|
800593a: b087 sub sp, #28
|
|
800593c: af00 add r7, sp, #0
|
|
800593e: 60f8 str r0, [r7, #12]
|
|
8005940: 60b9 str r1, [r7, #8]
|
|
8005942: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8005944: 68fb ldr r3, [r7, #12]
|
|
8005946: 6a1b ldr r3, [r3, #32]
|
|
8005948: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800594a: 68fb ldr r3, [r7, #12]
|
|
800594c: 6a1b ldr r3, [r3, #32]
|
|
800594e: f023 0201 bic.w r2, r3, #1
|
|
8005952: 68fb ldr r3, [r7, #12]
|
|
8005954: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8005956: 68fb ldr r3, [r7, #12]
|
|
8005958: 699b ldr r3, [r3, #24]
|
|
800595a: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
800595c: 693b ldr r3, [r7, #16]
|
|
800595e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
8005962: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8005964: 687b ldr r3, [r7, #4]
|
|
8005966: 011b lsls r3, r3, #4
|
|
8005968: 693a ldr r2, [r7, #16]
|
|
800596a: 4313 orrs r3, r2
|
|
800596c: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
800596e: 697b ldr r3, [r7, #20]
|
|
8005970: f023 030a bic.w r3, r3, #10
|
|
8005974: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
8005976: 697a ldr r2, [r7, #20]
|
|
8005978: 68bb ldr r3, [r7, #8]
|
|
800597a: 4313 orrs r3, r2
|
|
800597c: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
800597e: 68fb ldr r3, [r7, #12]
|
|
8005980: 693a ldr r2, [r7, #16]
|
|
8005982: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8005984: 68fb ldr r3, [r7, #12]
|
|
8005986: 697a ldr r2, [r7, #20]
|
|
8005988: 621a str r2, [r3, #32]
|
|
}
|
|
800598a: bf00 nop
|
|
800598c: 371c adds r7, #28
|
|
800598e: 46bd mov sp, r7
|
|
8005990: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005994: 4770 bx lr
|
|
|
|
08005996 <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8005996: b480 push {r7}
|
|
8005998: b087 sub sp, #28
|
|
800599a: af00 add r7, sp, #0
|
|
800599c: 60f8 str r0, [r7, #12]
|
|
800599e: 60b9 str r1, [r7, #8]
|
|
80059a0: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
80059a2: 68fb ldr r3, [r7, #12]
|
|
80059a4: 6a1b ldr r3, [r3, #32]
|
|
80059a6: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
80059a8: 68fb ldr r3, [r7, #12]
|
|
80059aa: 6a1b ldr r3, [r3, #32]
|
|
80059ac: f023 0210 bic.w r2, r3, #16
|
|
80059b0: 68fb ldr r3, [r7, #12]
|
|
80059b2: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
80059b4: 68fb ldr r3, [r7, #12]
|
|
80059b6: 699b ldr r3, [r3, #24]
|
|
80059b8: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
80059ba: 693b ldr r3, [r7, #16]
|
|
80059bc: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
80059c0: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
80059c2: 687b ldr r3, [r7, #4]
|
|
80059c4: 031b lsls r3, r3, #12
|
|
80059c6: 693a ldr r2, [r7, #16]
|
|
80059c8: 4313 orrs r3, r2
|
|
80059ca: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
80059cc: 697b ldr r3, [r7, #20]
|
|
80059ce: f023 03a0 bic.w r3, r3, #160 @ 0xa0
|
|
80059d2: 617b str r3, [r7, #20]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
80059d4: 68bb ldr r3, [r7, #8]
|
|
80059d6: 011b lsls r3, r3, #4
|
|
80059d8: 697a ldr r2, [r7, #20]
|
|
80059da: 4313 orrs r3, r2
|
|
80059dc: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
80059de: 68fb ldr r3, [r7, #12]
|
|
80059e0: 693a ldr r2, [r7, #16]
|
|
80059e2: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
80059e4: 68fb ldr r3, [r7, #12]
|
|
80059e6: 697a ldr r2, [r7, #20]
|
|
80059e8: 621a str r2, [r3, #32]
|
|
}
|
|
80059ea: bf00 nop
|
|
80059ec: 371c adds r7, #28
|
|
80059ee: 46bd mov sp, r7
|
|
80059f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80059f4: 4770 bx lr
|
|
|
|
080059f6 <TIM_ITRx_SetConfig>:
|
|
* (*) Value not defined in all devices.
|
|
*
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
80059f6: b480 push {r7}
|
|
80059f8: b085 sub sp, #20
|
|
80059fa: af00 add r7, sp, #0
|
|
80059fc: 6078 str r0, [r7, #4]
|
|
80059fe: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
8005a00: 687b ldr r3, [r7, #4]
|
|
8005a02: 689b ldr r3, [r3, #8]
|
|
8005a04: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8005a06: 68fb ldr r3, [r7, #12]
|
|
8005a08: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
|
|
8005a0c: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005a10: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8005a12: 683a ldr r2, [r7, #0]
|
|
8005a14: 68fb ldr r3, [r7, #12]
|
|
8005a16: 4313 orrs r3, r2
|
|
8005a18: f043 0307 orr.w r3, r3, #7
|
|
8005a1c: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8005a1e: 687b ldr r3, [r7, #4]
|
|
8005a20: 68fa ldr r2, [r7, #12]
|
|
8005a22: 609a str r2, [r3, #8]
|
|
}
|
|
8005a24: bf00 nop
|
|
8005a26: 3714 adds r7, #20
|
|
8005a28: 46bd mov sp, r7
|
|
8005a2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005a2e: 4770 bx lr
|
|
|
|
08005a30 <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
8005a30: b480 push {r7}
|
|
8005a32: b087 sub sp, #28
|
|
8005a34: af00 add r7, sp, #0
|
|
8005a36: 60f8 str r0, [r7, #12]
|
|
8005a38: 60b9 str r1, [r7, #8]
|
|
8005a3a: 607a str r2, [r7, #4]
|
|
8005a3c: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
8005a3e: 68fb ldr r3, [r7, #12]
|
|
8005a40: 689b ldr r3, [r3, #8]
|
|
8005a42: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8005a44: 697b ldr r3, [r7, #20]
|
|
8005a46: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
8005a4a: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
8005a4c: 683b ldr r3, [r7, #0]
|
|
8005a4e: 021a lsls r2, r3, #8
|
|
8005a50: 687b ldr r3, [r7, #4]
|
|
8005a52: 431a orrs r2, r3
|
|
8005a54: 68bb ldr r3, [r7, #8]
|
|
8005a56: 4313 orrs r3, r2
|
|
8005a58: 697a ldr r2, [r7, #20]
|
|
8005a5a: 4313 orrs r3, r2
|
|
8005a5c: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8005a5e: 68fb ldr r3, [r7, #12]
|
|
8005a60: 697a ldr r2, [r7, #20]
|
|
8005a62: 609a str r2, [r3, #8]
|
|
}
|
|
8005a64: bf00 nop
|
|
8005a66: 371c adds r7, #28
|
|
8005a68: 46bd mov sp, r7
|
|
8005a6a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005a6e: 4770 bx lr
|
|
|
|
08005a70 <TIM_CCxChannelCmd>:
|
|
* @param ChannelState specifies the TIM Channel CCxE bit new state.
|
|
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
|
|
* @retval None
|
|
*/
|
|
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
|
|
{
|
|
8005a70: b480 push {r7}
|
|
8005a72: b087 sub sp, #28
|
|
8005a74: af00 add r7, sp, #0
|
|
8005a76: 60f8 str r0, [r7, #12]
|
|
8005a78: 60b9 str r1, [r7, #8]
|
|
8005a7a: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8005a7c: 68bb ldr r3, [r7, #8]
|
|
8005a7e: f003 031f and.w r3, r3, #31
|
|
8005a82: 2201 movs r2, #1
|
|
8005a84: fa02 f303 lsl.w r3, r2, r3
|
|
8005a88: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8005a8a: 68fb ldr r3, [r7, #12]
|
|
8005a8c: 6a1a ldr r2, [r3, #32]
|
|
8005a8e: 697b ldr r3, [r7, #20]
|
|
8005a90: 43db mvns r3, r3
|
|
8005a92: 401a ands r2, r3
|
|
8005a94: 68fb ldr r3, [r7, #12]
|
|
8005a96: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8005a98: 68fb ldr r3, [r7, #12]
|
|
8005a9a: 6a1a ldr r2, [r3, #32]
|
|
8005a9c: 68bb ldr r3, [r7, #8]
|
|
8005a9e: f003 031f and.w r3, r3, #31
|
|
8005aa2: 6879 ldr r1, [r7, #4]
|
|
8005aa4: fa01 f303 lsl.w r3, r1, r3
|
|
8005aa8: 431a orrs r2, r3
|
|
8005aaa: 68fb ldr r3, [r7, #12]
|
|
8005aac: 621a str r2, [r3, #32]
|
|
}
|
|
8005aae: bf00 nop
|
|
8005ab0: 371c adds r7, #28
|
|
8005ab2: 46bd mov sp, r7
|
|
8005ab4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ab8: 4770 bx lr
|
|
...
|
|
|
|
08005abc <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8005abc: b480 push {r7}
|
|
8005abe: b085 sub sp, #20
|
|
8005ac0: af00 add r7, sp, #0
|
|
8005ac2: 6078 str r0, [r7, #4]
|
|
8005ac4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8005ac6: 687b ldr r3, [r7, #4]
|
|
8005ac8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005acc: 2b01 cmp r3, #1
|
|
8005ace: d101 bne.n 8005ad4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8005ad0: 2302 movs r3, #2
|
|
8005ad2: e065 b.n 8005ba0 <HAL_TIMEx_MasterConfigSynchronization+0xe4>
|
|
8005ad4: 687b ldr r3, [r7, #4]
|
|
8005ad6: 2201 movs r2, #1
|
|
8005ad8: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005adc: 687b ldr r3, [r7, #4]
|
|
8005ade: 2202 movs r2, #2
|
|
8005ae0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8005ae4: 687b ldr r3, [r7, #4]
|
|
8005ae6: 681b ldr r3, [r3, #0]
|
|
8005ae8: 685b ldr r3, [r3, #4]
|
|
8005aea: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005aec: 687b ldr r3, [r7, #4]
|
|
8005aee: 681b ldr r3, [r3, #0]
|
|
8005af0: 689b ldr r3, [r3, #8]
|
|
8005af2: 60bb str r3, [r7, #8]
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
8005af4: 687b ldr r3, [r7, #4]
|
|
8005af6: 681b ldr r3, [r3, #0]
|
|
8005af8: 4a2c ldr r2, [pc, #176] @ (8005bac <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8005afa: 4293 cmp r3, r2
|
|
8005afc: d004 beq.n 8005b08 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
|
|
8005afe: 687b ldr r3, [r7, #4]
|
|
8005b00: 681b ldr r3, [r3, #0]
|
|
8005b02: 4a2b ldr r2, [pc, #172] @ (8005bb0 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
8005b04: 4293 cmp r3, r2
|
|
8005b06: d108 bne.n 8005b1a <HAL_TIMEx_MasterConfigSynchronization+0x5e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
8005b08: 68fb ldr r3, [r7, #12]
|
|
8005b0a: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
|
|
8005b0e: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
8005b10: 683b ldr r3, [r7, #0]
|
|
8005b12: 685b ldr r3, [r3, #4]
|
|
8005b14: 68fa ldr r2, [r7, #12]
|
|
8005b16: 4313 orrs r3, r2
|
|
8005b18: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8005b1a: 68fb ldr r3, [r7, #12]
|
|
8005b1c: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000
|
|
8005b20: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005b24: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8005b26: 683b ldr r3, [r7, #0]
|
|
8005b28: 681b ldr r3, [r3, #0]
|
|
8005b2a: 68fa ldr r2, [r7, #12]
|
|
8005b2c: 4313 orrs r3, r2
|
|
8005b2e: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8005b30: 687b ldr r3, [r7, #4]
|
|
8005b32: 681b ldr r3, [r3, #0]
|
|
8005b34: 68fa ldr r2, [r7, #12]
|
|
8005b36: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005b38: 687b ldr r3, [r7, #4]
|
|
8005b3a: 681b ldr r3, [r3, #0]
|
|
8005b3c: 4a1b ldr r2, [pc, #108] @ (8005bac <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8005b3e: 4293 cmp r3, r2
|
|
8005b40: d018 beq.n 8005b74 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
8005b42: 687b ldr r3, [r7, #4]
|
|
8005b44: 681b ldr r3, [r3, #0]
|
|
8005b46: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005b4a: d013 beq.n 8005b74 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
8005b4c: 687b ldr r3, [r7, #4]
|
|
8005b4e: 681b ldr r3, [r3, #0]
|
|
8005b50: 4a18 ldr r2, [pc, #96] @ (8005bb4 <HAL_TIMEx_MasterConfigSynchronization+0xf8>)
|
|
8005b52: 4293 cmp r3, r2
|
|
8005b54: d00e beq.n 8005b74 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
8005b56: 687b ldr r3, [r7, #4]
|
|
8005b58: 681b ldr r3, [r3, #0]
|
|
8005b5a: 4a17 ldr r2, [pc, #92] @ (8005bb8 <HAL_TIMEx_MasterConfigSynchronization+0xfc>)
|
|
8005b5c: 4293 cmp r3, r2
|
|
8005b5e: d009 beq.n 8005b74 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
8005b60: 687b ldr r3, [r7, #4]
|
|
8005b62: 681b ldr r3, [r3, #0]
|
|
8005b64: 4a12 ldr r2, [pc, #72] @ (8005bb0 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
8005b66: 4293 cmp r3, r2
|
|
8005b68: d004 beq.n 8005b74 <HAL_TIMEx_MasterConfigSynchronization+0xb8>
|
|
8005b6a: 687b ldr r3, [r7, #4]
|
|
8005b6c: 681b ldr r3, [r3, #0]
|
|
8005b6e: 4a13 ldr r2, [pc, #76] @ (8005bbc <HAL_TIMEx_MasterConfigSynchronization+0x100>)
|
|
8005b70: 4293 cmp r3, r2
|
|
8005b72: d10c bne.n 8005b8e <HAL_TIMEx_MasterConfigSynchronization+0xd2>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8005b74: 68bb ldr r3, [r7, #8]
|
|
8005b76: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005b7a: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8005b7c: 683b ldr r3, [r7, #0]
|
|
8005b7e: 689b ldr r3, [r3, #8]
|
|
8005b80: 68ba ldr r2, [r7, #8]
|
|
8005b82: 4313 orrs r3, r2
|
|
8005b84: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005b86: 687b ldr r3, [r7, #4]
|
|
8005b88: 681b ldr r3, [r3, #0]
|
|
8005b8a: 68ba ldr r2, [r7, #8]
|
|
8005b8c: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005b8e: 687b ldr r3, [r7, #4]
|
|
8005b90: 2201 movs r2, #1
|
|
8005b92: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005b96: 687b ldr r3, [r7, #4]
|
|
8005b98: 2200 movs r2, #0
|
|
8005b9a: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8005b9e: 2300 movs r3, #0
|
|
}
|
|
8005ba0: 4618 mov r0, r3
|
|
8005ba2: 3714 adds r7, #20
|
|
8005ba4: 46bd mov sp, r7
|
|
8005ba6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005baa: 4770 bx lr
|
|
8005bac: 40012c00 .word 0x40012c00
|
|
8005bb0: 40013400 .word 0x40013400
|
|
8005bb4: 40000400 .word 0x40000400
|
|
8005bb8: 40000800 .word 0x40000800
|
|
8005bbc: 40014000 .word 0x40014000
|
|
|
|
08005bc0 <HAL_TIMEx_ConfigBreakDeadTime>:
|
|
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
|
|
{
|
|
8005bc0: b480 push {r7}
|
|
8005bc2: b085 sub sp, #20
|
|
8005bc4: af00 add r7, sp, #0
|
|
8005bc6: 6078 str r0, [r7, #4]
|
|
8005bc8: 6039 str r1, [r7, #0]
|
|
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
|
|
uint32_t tmpbdtr = 0U;
|
|
8005bca: 2300 movs r3, #0
|
|
8005bcc: 60fb str r3, [r7, #12]
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8005bce: 687b ldr r3, [r7, #4]
|
|
8005bd0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005bd4: 2b01 cmp r3, #1
|
|
8005bd6: d101 bne.n 8005bdc <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
|
|
8005bd8: 2302 movs r3, #2
|
|
8005bda: e073 b.n 8005cc4 <HAL_TIMEx_ConfigBreakDeadTime+0x104>
|
|
8005bdc: 687b ldr r3, [r7, #4]
|
|
8005bde: 2201 movs r2, #1
|
|
8005be0: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
/* Set the BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
8005be4: 68fb ldr r3, [r7, #12]
|
|
8005be6: f023 02ff bic.w r2, r3, #255 @ 0xff
|
|
8005bea: 683b ldr r3, [r7, #0]
|
|
8005bec: 68db ldr r3, [r3, #12]
|
|
8005bee: 4313 orrs r3, r2
|
|
8005bf0: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
8005bf2: 68fb ldr r3, [r7, #12]
|
|
8005bf4: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
8005bf8: 683b ldr r3, [r7, #0]
|
|
8005bfa: 689b ldr r3, [r3, #8]
|
|
8005bfc: 4313 orrs r3, r2
|
|
8005bfe: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
8005c00: 68fb ldr r3, [r7, #12]
|
|
8005c02: f423 6280 bic.w r2, r3, #1024 @ 0x400
|
|
8005c06: 683b ldr r3, [r7, #0]
|
|
8005c08: 685b ldr r3, [r3, #4]
|
|
8005c0a: 4313 orrs r3, r2
|
|
8005c0c: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
8005c0e: 68fb ldr r3, [r7, #12]
|
|
8005c10: f423 6200 bic.w r2, r3, #2048 @ 0x800
|
|
8005c14: 683b ldr r3, [r7, #0]
|
|
8005c16: 681b ldr r3, [r3, #0]
|
|
8005c18: 4313 orrs r3, r2
|
|
8005c1a: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
8005c1c: 68fb ldr r3, [r7, #12]
|
|
8005c1e: f423 5280 bic.w r2, r3, #4096 @ 0x1000
|
|
8005c22: 683b ldr r3, [r7, #0]
|
|
8005c24: 691b ldr r3, [r3, #16]
|
|
8005c26: 4313 orrs r3, r2
|
|
8005c28: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
8005c2a: 68fb ldr r3, [r7, #12]
|
|
8005c2c: f423 5200 bic.w r2, r3, #8192 @ 0x2000
|
|
8005c30: 683b ldr r3, [r7, #0]
|
|
8005c32: 695b ldr r3, [r3, #20]
|
|
8005c34: 4313 orrs r3, r2
|
|
8005c36: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
8005c38: 68fb ldr r3, [r7, #12]
|
|
8005c3a: f423 4280 bic.w r2, r3, #16384 @ 0x4000
|
|
8005c3e: 683b ldr r3, [r7, #0]
|
|
8005c40: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8005c42: 4313 orrs r3, r2
|
|
8005c44: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
|
8005c46: 68fb ldr r3, [r7, #12]
|
|
8005c48: f423 2270 bic.w r2, r3, #983040 @ 0xf0000
|
|
8005c4c: 683b ldr r3, [r7, #0]
|
|
8005c4e: 699b ldr r3, [r3, #24]
|
|
8005c50: 041b lsls r3, r3, #16
|
|
8005c52: 4313 orrs r3, r2
|
|
8005c54: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
|
|
8005c56: 68fb ldr r3, [r7, #12]
|
|
8005c58: f023 5280 bic.w r2, r3, #268435456 @ 0x10000000
|
|
8005c5c: 683b ldr r3, [r7, #0]
|
|
8005c5e: 69db ldr r3, [r3, #28]
|
|
8005c60: 4313 orrs r3, r2
|
|
8005c62: 60fb str r3, [r7, #12]
|
|
|
|
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
|
8005c64: 687b ldr r3, [r7, #4]
|
|
8005c66: 681b ldr r3, [r3, #0]
|
|
8005c68: 4a19 ldr r2, [pc, #100] @ (8005cd0 <HAL_TIMEx_ConfigBreakDeadTime+0x110>)
|
|
8005c6a: 4293 cmp r3, r2
|
|
8005c6c: d004 beq.n 8005c78 <HAL_TIMEx_ConfigBreakDeadTime+0xb8>
|
|
8005c6e: 687b ldr r3, [r7, #4]
|
|
8005c70: 681b ldr r3, [r3, #0]
|
|
8005c72: 4a18 ldr r2, [pc, #96] @ (8005cd4 <HAL_TIMEx_ConfigBreakDeadTime+0x114>)
|
|
8005c74: 4293 cmp r3, r2
|
|
8005c76: d11c bne.n 8005cb2 <HAL_TIMEx_ConfigBreakDeadTime+0xf2>
|
|
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
|
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
|
|
|
|
/* Set the BREAK2 input related BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
|
|
8005c78: 68fb ldr r3, [r7, #12]
|
|
8005c7a: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000
|
|
8005c7e: 683b ldr r3, [r7, #0]
|
|
8005c80: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005c82: 051b lsls r3, r3, #20
|
|
8005c84: 4313 orrs r3, r2
|
|
8005c86: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
|
8005c88: 68fb ldr r3, [r7, #12]
|
|
8005c8a: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
|
|
8005c8e: 683b ldr r3, [r7, #0]
|
|
8005c90: 6a1b ldr r3, [r3, #32]
|
|
8005c92: 4313 orrs r3, r2
|
|
8005c94: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
|
8005c96: 68fb ldr r3, [r7, #12]
|
|
8005c98: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
|
|
8005c9c: 683b ldr r3, [r7, #0]
|
|
8005c9e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005ca0: 4313 orrs r3, r2
|
|
8005ca2: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
|
|
8005ca4: 68fb ldr r3, [r7, #12]
|
|
8005ca6: f023 5200 bic.w r2, r3, #536870912 @ 0x20000000
|
|
8005caa: 683b ldr r3, [r7, #0]
|
|
8005cac: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8005cae: 4313 orrs r3, r2
|
|
8005cb0: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set TIMx_BDTR */
|
|
htim->Instance->BDTR = tmpbdtr;
|
|
8005cb2: 687b ldr r3, [r7, #4]
|
|
8005cb4: 681b ldr r3, [r3, #0]
|
|
8005cb6: 68fa ldr r2, [r7, #12]
|
|
8005cb8: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005cba: 687b ldr r3, [r7, #4]
|
|
8005cbc: 2200 movs r2, #0
|
|
8005cbe: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8005cc2: 2300 movs r3, #0
|
|
}
|
|
8005cc4: 4618 mov r0, r3
|
|
8005cc6: 3714 adds r7, #20
|
|
8005cc8: 46bd mov sp, r7
|
|
8005cca: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cce: 4770 bx lr
|
|
8005cd0: 40012c00 .word 0x40012c00
|
|
8005cd4: 40013400 .word 0x40013400
|
|
|
|
08005cd8 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005cd8: b480 push {r7}
|
|
8005cda: b083 sub sp, #12
|
|
8005cdc: af00 add r7, sp, #0
|
|
8005cde: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005ce0: bf00 nop
|
|
8005ce2: 370c adds r7, #12
|
|
8005ce4: 46bd mov sp, r7
|
|
8005ce6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cea: 4770 bx lr
|
|
|
|
08005cec <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005cec: b480 push {r7}
|
|
8005cee: b083 sub sp, #12
|
|
8005cf0: af00 add r7, sp, #0
|
|
8005cf2: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005cf4: bf00 nop
|
|
8005cf6: 370c adds r7, #12
|
|
8005cf8: 46bd mov sp, r7
|
|
8005cfa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005cfe: 4770 bx lr
|
|
|
|
08005d00 <HAL_TIMEx_Break2Callback>:
|
|
* @brief Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005d00: b480 push {r7}
|
|
8005d02: b083 sub sp, #12
|
|
8005d04: af00 add r7, sp, #0
|
|
8005d06: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005d08: bf00 nop
|
|
8005d0a: 370c adds r7, #12
|
|
8005d0c: 46bd mov sp, r7
|
|
8005d0e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d12: 4770 bx lr
|
|
|
|
08005d14 <HAL_TIMEx_EncoderIndexCallback>:
|
|
* @brief Encoder index callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005d14: b480 push {r7}
|
|
8005d16: b083 sub sp, #12
|
|
8005d18: af00 add r7, sp, #0
|
|
8005d1a: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005d1c: bf00 nop
|
|
8005d1e: 370c adds r7, #12
|
|
8005d20: 46bd mov sp, r7
|
|
8005d22: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d26: 4770 bx lr
|
|
|
|
08005d28 <HAL_TIMEx_DirectionChangeCallback>:
|
|
* @brief Direction change callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005d28: b480 push {r7}
|
|
8005d2a: b083 sub sp, #12
|
|
8005d2c: af00 add r7, sp, #0
|
|
8005d2e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005d30: bf00 nop
|
|
8005d32: 370c adds r7, #12
|
|
8005d34: 46bd mov sp, r7
|
|
8005d36: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d3a: 4770 bx lr
|
|
|
|
08005d3c <HAL_TIMEx_IndexErrorCallback>:
|
|
* @brief Index error callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005d3c: b480 push {r7}
|
|
8005d3e: b083 sub sp, #12
|
|
8005d40: af00 add r7, sp, #0
|
|
8005d42: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005d44: bf00 nop
|
|
8005d46: 370c adds r7, #12
|
|
8005d48: 46bd mov sp, r7
|
|
8005d4a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d4e: 4770 bx lr
|
|
|
|
08005d50 <HAL_TIMEx_TransitionErrorCallback>:
|
|
* @brief Transition error callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005d50: b480 push {r7}
|
|
8005d52: b083 sub sp, #12
|
|
8005d54: af00 add r7, sp, #0
|
|
8005d56: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005d58: bf00 nop
|
|
8005d5a: 370c adds r7, #12
|
|
8005d5c: 46bd mov sp, r7
|
|
8005d5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d62: 4770 bx lr
|
|
|
|
08005d64 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8005d64: b580 push {r7, lr}
|
|
8005d66: b082 sub sp, #8
|
|
8005d68: af00 add r7, sp, #0
|
|
8005d6a: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8005d6c: 687b ldr r3, [r7, #4]
|
|
8005d6e: 2b00 cmp r3, #0
|
|
8005d70: d101 bne.n 8005d76 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005d72: 2301 movs r3, #1
|
|
8005d74: e042 b.n 8005dfc <HAL_UART_Init+0x98>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8005d76: 687b ldr r3, [r7, #4]
|
|
8005d78: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005d7c: 2b00 cmp r3, #0
|
|
8005d7e: d106 bne.n 8005d8e <HAL_UART_Init+0x2a>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8005d80: 687b ldr r3, [r7, #4]
|
|
8005d82: 2200 movs r2, #0
|
|
8005d84: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8005d88: 6878 ldr r0, [r7, #4]
|
|
8005d8a: f7fb fbb1 bl 80014f0 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005d8e: 687b ldr r3, [r7, #4]
|
|
8005d90: 2224 movs r2, #36 @ 0x24
|
|
8005d92: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8005d96: 687b ldr r3, [r7, #4]
|
|
8005d98: 681b ldr r3, [r3, #0]
|
|
8005d9a: 681a ldr r2, [r3, #0]
|
|
8005d9c: 687b ldr r3, [r7, #4]
|
|
8005d9e: 681b ldr r3, [r3, #0]
|
|
8005da0: f022 0201 bic.w r2, r2, #1
|
|
8005da4: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8005da6: 687b ldr r3, [r7, #4]
|
|
8005da8: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005daa: 2b00 cmp r3, #0
|
|
8005dac: d002 beq.n 8005db4 <HAL_UART_Init+0x50>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8005dae: 6878 ldr r0, [r7, #4]
|
|
8005db0: f000 ff26 bl 8006c00 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8005db4: 6878 ldr r0, [r7, #4]
|
|
8005db6: f000 fc57 bl 8006668 <UART_SetConfig>
|
|
8005dba: 4603 mov r3, r0
|
|
8005dbc: 2b01 cmp r3, #1
|
|
8005dbe: d101 bne.n 8005dc4 <HAL_UART_Init+0x60>
|
|
{
|
|
return HAL_ERROR;
|
|
8005dc0: 2301 movs r3, #1
|
|
8005dc2: e01b b.n 8005dfc <HAL_UART_Init+0x98>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8005dc4: 687b ldr r3, [r7, #4]
|
|
8005dc6: 681b ldr r3, [r3, #0]
|
|
8005dc8: 685a ldr r2, [r3, #4]
|
|
8005dca: 687b ldr r3, [r7, #4]
|
|
8005dcc: 681b ldr r3, [r3, #0]
|
|
8005dce: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8005dd2: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8005dd4: 687b ldr r3, [r7, #4]
|
|
8005dd6: 681b ldr r3, [r3, #0]
|
|
8005dd8: 689a ldr r2, [r3, #8]
|
|
8005dda: 687b ldr r3, [r7, #4]
|
|
8005ddc: 681b ldr r3, [r3, #0]
|
|
8005dde: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8005de2: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
8005de4: 687b ldr r3, [r7, #4]
|
|
8005de6: 681b ldr r3, [r3, #0]
|
|
8005de8: 681a ldr r2, [r3, #0]
|
|
8005dea: 687b ldr r3, [r7, #4]
|
|
8005dec: 681b ldr r3, [r3, #0]
|
|
8005dee: f042 0201 orr.w r2, r2, #1
|
|
8005df2: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
8005df4: 6878 ldr r0, [r7, #4]
|
|
8005df6: f000 ffa5 bl 8006d44 <UART_CheckIdleState>
|
|
8005dfa: 4603 mov r3, r0
|
|
}
|
|
8005dfc: 4618 mov r0, r3
|
|
8005dfe: 3708 adds r7, #8
|
|
8005e00: 46bd mov sp, r7
|
|
8005e02: bd80 pop {r7, pc}
|
|
|
|
08005e04 <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8005e04: b580 push {r7, lr}
|
|
8005e06: b08a sub sp, #40 @ 0x28
|
|
8005e08: af02 add r7, sp, #8
|
|
8005e0a: 60f8 str r0, [r7, #12]
|
|
8005e0c: 60b9 str r1, [r7, #8]
|
|
8005e0e: 603b str r3, [r7, #0]
|
|
8005e10: 4613 mov r3, r2
|
|
8005e12: 80fb strh r3, [r7, #6]
|
|
const uint8_t *pdata8bits;
|
|
const uint16_t *pdata16bits;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8005e14: 68fb ldr r3, [r7, #12]
|
|
8005e16: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005e1a: 2b20 cmp r3, #32
|
|
8005e1c: d17b bne.n 8005f16 <HAL_UART_Transmit+0x112>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005e1e: 68bb ldr r3, [r7, #8]
|
|
8005e20: 2b00 cmp r3, #0
|
|
8005e22: d002 beq.n 8005e2a <HAL_UART_Transmit+0x26>
|
|
8005e24: 88fb ldrh r3, [r7, #6]
|
|
8005e26: 2b00 cmp r3, #0
|
|
8005e28: d101 bne.n 8005e2e <HAL_UART_Transmit+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8005e2a: 2301 movs r3, #1
|
|
8005e2c: e074 b.n 8005f18 <HAL_UART_Transmit+0x114>
|
|
}
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005e2e: 68fb ldr r3, [r7, #12]
|
|
8005e30: 2200 movs r2, #0
|
|
8005e32: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8005e36: 68fb ldr r3, [r7, #12]
|
|
8005e38: 2221 movs r2, #33 @ 0x21
|
|
8005e3a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8005e3e: f7fb fc9b bl 8001778 <HAL_GetTick>
|
|
8005e42: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
8005e44: 68fb ldr r3, [r7, #12]
|
|
8005e46: 88fa ldrh r2, [r7, #6]
|
|
8005e48: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
|
|
huart->TxXferCount = Size;
|
|
8005e4c: 68fb ldr r3, [r7, #12]
|
|
8005e4e: 88fa ldrh r2, [r7, #6]
|
|
8005e50: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8005e54: 68fb ldr r3, [r7, #12]
|
|
8005e56: 689b ldr r3, [r3, #8]
|
|
8005e58: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005e5c: d108 bne.n 8005e70 <HAL_UART_Transmit+0x6c>
|
|
8005e5e: 68fb ldr r3, [r7, #12]
|
|
8005e60: 691b ldr r3, [r3, #16]
|
|
8005e62: 2b00 cmp r3, #0
|
|
8005e64: d104 bne.n 8005e70 <HAL_UART_Transmit+0x6c>
|
|
{
|
|
pdata8bits = NULL;
|
|
8005e66: 2300 movs r3, #0
|
|
8005e68: 61fb str r3, [r7, #28]
|
|
pdata16bits = (const uint16_t *) pData;
|
|
8005e6a: 68bb ldr r3, [r7, #8]
|
|
8005e6c: 61bb str r3, [r7, #24]
|
|
8005e6e: e003 b.n 8005e78 <HAL_UART_Transmit+0x74>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
8005e70: 68bb ldr r3, [r7, #8]
|
|
8005e72: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
8005e74: 2300 movs r3, #0
|
|
8005e76: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
8005e78: e030 b.n 8005edc <HAL_UART_Transmit+0xd8>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8005e7a: 683b ldr r3, [r7, #0]
|
|
8005e7c: 9300 str r3, [sp, #0]
|
|
8005e7e: 697b ldr r3, [r7, #20]
|
|
8005e80: 2200 movs r2, #0
|
|
8005e82: 2180 movs r1, #128 @ 0x80
|
|
8005e84: 68f8 ldr r0, [r7, #12]
|
|
8005e86: f001 f807 bl 8006e98 <UART_WaitOnFlagUntilTimeout>
|
|
8005e8a: 4603 mov r3, r0
|
|
8005e8c: 2b00 cmp r3, #0
|
|
8005e8e: d005 beq.n 8005e9c <HAL_UART_Transmit+0x98>
|
|
{
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005e90: 68fb ldr r3, [r7, #12]
|
|
8005e92: 2220 movs r2, #32
|
|
8005e94: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
return HAL_TIMEOUT;
|
|
8005e98: 2303 movs r3, #3
|
|
8005e9a: e03d b.n 8005f18 <HAL_UART_Transmit+0x114>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
8005e9c: 69fb ldr r3, [r7, #28]
|
|
8005e9e: 2b00 cmp r3, #0
|
|
8005ea0: d10b bne.n 8005eba <HAL_UART_Transmit+0xb6>
|
|
{
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8005ea2: 69bb ldr r3, [r7, #24]
|
|
8005ea4: 881b ldrh r3, [r3, #0]
|
|
8005ea6: 461a mov r2, r3
|
|
8005ea8: 68fb ldr r3, [r7, #12]
|
|
8005eaa: 681b ldr r3, [r3, #0]
|
|
8005eac: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8005eb0: 629a str r2, [r3, #40] @ 0x28
|
|
pdata16bits++;
|
|
8005eb2: 69bb ldr r3, [r7, #24]
|
|
8005eb4: 3302 adds r3, #2
|
|
8005eb6: 61bb str r3, [r7, #24]
|
|
8005eb8: e007 b.n 8005eca <HAL_UART_Transmit+0xc6>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8005eba: 69fb ldr r3, [r7, #28]
|
|
8005ebc: 781a ldrb r2, [r3, #0]
|
|
8005ebe: 68fb ldr r3, [r7, #12]
|
|
8005ec0: 681b ldr r3, [r3, #0]
|
|
8005ec2: 629a str r2, [r3, #40] @ 0x28
|
|
pdata8bits++;
|
|
8005ec4: 69fb ldr r3, [r7, #28]
|
|
8005ec6: 3301 adds r3, #1
|
|
8005ec8: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
8005eca: 68fb ldr r3, [r7, #12]
|
|
8005ecc: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
|
|
8005ed0: b29b uxth r3, r3
|
|
8005ed2: 3b01 subs r3, #1
|
|
8005ed4: b29a uxth r2, r3
|
|
8005ed6: 68fb ldr r3, [r7, #12]
|
|
8005ed8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
|
|
while (huart->TxXferCount > 0U)
|
|
8005edc: 68fb ldr r3, [r7, #12]
|
|
8005ede: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
|
|
8005ee2: b29b uxth r3, r3
|
|
8005ee4: 2b00 cmp r3, #0
|
|
8005ee6: d1c8 bne.n 8005e7a <HAL_UART_Transmit+0x76>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8005ee8: 683b ldr r3, [r7, #0]
|
|
8005eea: 9300 str r3, [sp, #0]
|
|
8005eec: 697b ldr r3, [r7, #20]
|
|
8005eee: 2200 movs r2, #0
|
|
8005ef0: 2140 movs r1, #64 @ 0x40
|
|
8005ef2: 68f8 ldr r0, [r7, #12]
|
|
8005ef4: f000 ffd0 bl 8006e98 <UART_WaitOnFlagUntilTimeout>
|
|
8005ef8: 4603 mov r3, r0
|
|
8005efa: 2b00 cmp r3, #0
|
|
8005efc: d005 beq.n 8005f0a <HAL_UART_Transmit+0x106>
|
|
{
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005efe: 68fb ldr r3, [r7, #12]
|
|
8005f00: 2220 movs r2, #32
|
|
8005f02: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
return HAL_TIMEOUT;
|
|
8005f06: 2303 movs r3, #3
|
|
8005f08: e006 b.n 8005f18 <HAL_UART_Transmit+0x114>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005f0a: 68fb ldr r3, [r7, #12]
|
|
8005f0c: 2220 movs r2, #32
|
|
8005f0e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
return HAL_OK;
|
|
8005f12: 2300 movs r3, #0
|
|
8005f14: e000 b.n 8005f18 <HAL_UART_Transmit+0x114>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005f16: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005f18: 4618 mov r0, r3
|
|
8005f1a: 3720 adds r7, #32
|
|
8005f1c: 46bd mov sp, r7
|
|
8005f1e: bd80 pop {r7, pc}
|
|
|
|
08005f20 <HAL_UART_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005f20: b580 push {r7, lr}
|
|
8005f22: b08a sub sp, #40 @ 0x28
|
|
8005f24: af00 add r7, sp, #0
|
|
8005f26: 60f8 str r0, [r7, #12]
|
|
8005f28: 60b9 str r1, [r7, #8]
|
|
8005f2a: 4613 mov r3, r2
|
|
8005f2c: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8005f2e: 68fb ldr r3, [r7, #12]
|
|
8005f30: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8005f34: 2b20 cmp r3, #32
|
|
8005f36: d137 bne.n 8005fa8 <HAL_UART_Receive_IT+0x88>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005f38: 68bb ldr r3, [r7, #8]
|
|
8005f3a: 2b00 cmp r3, #0
|
|
8005f3c: d002 beq.n 8005f44 <HAL_UART_Receive_IT+0x24>
|
|
8005f3e: 88fb ldrh r3, [r7, #6]
|
|
8005f40: 2b00 cmp r3, #0
|
|
8005f42: d101 bne.n 8005f48 <HAL_UART_Receive_IT+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
8005f44: 2301 movs r3, #1
|
|
8005f46: e030 b.n 8005faa <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005f48: 68fb ldr r3, [r7, #12]
|
|
8005f4a: 2200 movs r2, #0
|
|
8005f4c: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8005f4e: 68fb ldr r3, [r7, #12]
|
|
8005f50: 681b ldr r3, [r3, #0]
|
|
8005f52: 4a18 ldr r2, [pc, #96] @ (8005fb4 <HAL_UART_Receive_IT+0x94>)
|
|
8005f54: 4293 cmp r3, r2
|
|
8005f56: d01f beq.n 8005f98 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8005f58: 68fb ldr r3, [r7, #12]
|
|
8005f5a: 681b ldr r3, [r3, #0]
|
|
8005f5c: 685b ldr r3, [r3, #4]
|
|
8005f5e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8005f62: 2b00 cmp r3, #0
|
|
8005f64: d018 beq.n 8005f98 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8005f66: 68fb ldr r3, [r7, #12]
|
|
8005f68: 681b ldr r3, [r3, #0]
|
|
8005f6a: 617b str r3, [r7, #20]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005f6c: 697b ldr r3, [r7, #20]
|
|
8005f6e: e853 3f00 ldrex r3, [r3]
|
|
8005f72: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8005f74: 693b ldr r3, [r7, #16]
|
|
8005f76: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8005f7a: 627b str r3, [r7, #36] @ 0x24
|
|
8005f7c: 68fb ldr r3, [r7, #12]
|
|
8005f7e: 681b ldr r3, [r3, #0]
|
|
8005f80: 461a mov r2, r3
|
|
8005f82: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005f84: 623b str r3, [r7, #32]
|
|
8005f86: 61fa str r2, [r7, #28]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005f88: 69f9 ldr r1, [r7, #28]
|
|
8005f8a: 6a3a ldr r2, [r7, #32]
|
|
8005f8c: e841 2300 strex r3, r2, [r1]
|
|
8005f90: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8005f92: 69bb ldr r3, [r7, #24]
|
|
8005f94: 2b00 cmp r3, #0
|
|
8005f96: d1e6 bne.n 8005f66 <HAL_UART_Receive_IT+0x46>
|
|
}
|
|
}
|
|
|
|
return (UART_Start_Receive_IT(huart, pData, Size));
|
|
8005f98: 88fb ldrh r3, [r7, #6]
|
|
8005f9a: 461a mov r2, r3
|
|
8005f9c: 68b9 ldr r1, [r7, #8]
|
|
8005f9e: 68f8 ldr r0, [r7, #12]
|
|
8005fa0: f000 ffe8 bl 8006f74 <UART_Start_Receive_IT>
|
|
8005fa4: 4603 mov r3, r0
|
|
8005fa6: e000 b.n 8005faa <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005fa8: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005faa: 4618 mov r0, r3
|
|
8005fac: 3728 adds r7, #40 @ 0x28
|
|
8005fae: 46bd mov sp, r7
|
|
8005fb0: bd80 pop {r7, pc}
|
|
8005fb2: bf00 nop
|
|
8005fb4: 40008000 .word 0x40008000
|
|
|
|
08005fb8 <HAL_UART_IRQHandler>:
|
|
* @brief Handle UART interrupt request.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8005fb8: b580 push {r7, lr}
|
|
8005fba: b0ba sub sp, #232 @ 0xe8
|
|
8005fbc: af00 add r7, sp, #0
|
|
8005fbe: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8005fc0: 687b ldr r3, [r7, #4]
|
|
8005fc2: 681b ldr r3, [r3, #0]
|
|
8005fc4: 69db ldr r3, [r3, #28]
|
|
8005fc6: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8005fca: 687b ldr r3, [r7, #4]
|
|
8005fcc: 681b ldr r3, [r3, #0]
|
|
8005fce: 681b ldr r3, [r3, #0]
|
|
8005fd0: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8005fd4: 687b ldr r3, [r7, #4]
|
|
8005fd6: 681b ldr r3, [r3, #0]
|
|
8005fd8: 689b ldr r3, [r3, #8]
|
|
8005fda: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
|
|
uint32_t errorflags;
|
|
uint32_t errorcode;
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
8005fde: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
|
|
8005fe2: f640 030f movw r3, #2063 @ 0x80f
|
|
8005fe6: 4013 ands r3, r2
|
|
8005fe8: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == 0U)
|
|
8005fec: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8005ff0: 2b00 cmp r3, #0
|
|
8005ff2: d11b bne.n 800602c <HAL_UART_IRQHandler+0x74>
|
|
{
|
|
/* UART in mode Receiver ---------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
8005ff4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005ff8: f003 0320 and.w r3, r3, #32
|
|
8005ffc: 2b00 cmp r3, #0
|
|
8005ffe: d015 beq.n 800602c <HAL_UART_IRQHandler+0x74>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
8006000: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006004: f003 0320 and.w r3, r3, #32
|
|
8006008: 2b00 cmp r3, #0
|
|
800600a: d105 bne.n 8006018 <HAL_UART_IRQHandler+0x60>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
800600c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8006010: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8006014: 2b00 cmp r3, #0
|
|
8006016: d009 beq.n 800602c <HAL_UART_IRQHandler+0x74>
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
8006018: 687b ldr r3, [r7, #4]
|
|
800601a: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800601c: 2b00 cmp r3, #0
|
|
800601e: f000 8300 beq.w 8006622 <HAL_UART_IRQHandler+0x66a>
|
|
{
|
|
huart->RxISR(huart);
|
|
8006022: 687b ldr r3, [r7, #4]
|
|
8006024: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8006026: 6878 ldr r0, [r7, #4]
|
|
8006028: 4798 blx r3
|
|
}
|
|
return;
|
|
800602a: e2fa b.n 8006622 <HAL_UART_IRQHandler+0x66a>
|
|
}
|
|
}
|
|
|
|
/* If some errors occur */
|
|
if ((errorflags != 0U)
|
|
800602c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8006030: 2b00 cmp r3, #0
|
|
8006032: f000 8123 beq.w 800627c <HAL_UART_IRQHandler+0x2c4>
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
8006036: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
|
|
800603a: 4b8d ldr r3, [pc, #564] @ (8006270 <HAL_UART_IRQHandler+0x2b8>)
|
|
800603c: 4013 ands r3, r2
|
|
800603e: 2b00 cmp r3, #0
|
|
8006040: d106 bne.n 8006050 <HAL_UART_IRQHandler+0x98>
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
8006042: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
|
|
8006046: 4b8b ldr r3, [pc, #556] @ (8006274 <HAL_UART_IRQHandler+0x2bc>)
|
|
8006048: 4013 ands r3, r2
|
|
800604a: 2b00 cmp r3, #0
|
|
800604c: f000 8116 beq.w 800627c <HAL_UART_IRQHandler+0x2c4>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8006050: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006054: f003 0301 and.w r3, r3, #1
|
|
8006058: 2b00 cmp r3, #0
|
|
800605a: d011 beq.n 8006080 <HAL_UART_IRQHandler+0xc8>
|
|
800605c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006060: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8006064: 2b00 cmp r3, #0
|
|
8006066: d00b beq.n 8006080 <HAL_UART_IRQHandler+0xc8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8006068: 687b ldr r3, [r7, #4]
|
|
800606a: 681b ldr r3, [r3, #0]
|
|
800606c: 2201 movs r2, #1
|
|
800606e: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8006070: 687b ldr r3, [r7, #4]
|
|
8006072: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006076: f043 0201 orr.w r2, r3, #1
|
|
800607a: 687b ldr r3, [r7, #4]
|
|
800607c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8006080: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006084: f003 0302 and.w r3, r3, #2
|
|
8006088: 2b00 cmp r3, #0
|
|
800608a: d011 beq.n 80060b0 <HAL_UART_IRQHandler+0xf8>
|
|
800608c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8006090: f003 0301 and.w r3, r3, #1
|
|
8006094: 2b00 cmp r3, #0
|
|
8006096: d00b beq.n 80060b0 <HAL_UART_IRQHandler+0xf8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8006098: 687b ldr r3, [r7, #4]
|
|
800609a: 681b ldr r3, [r3, #0]
|
|
800609c: 2202 movs r2, #2
|
|
800609e: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
80060a0: 687b ldr r3, [r7, #4]
|
|
80060a2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80060a6: f043 0204 orr.w r2, r3, #4
|
|
80060aa: 687b ldr r3, [r7, #4]
|
|
80060ac: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
80060b0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80060b4: f003 0304 and.w r3, r3, #4
|
|
80060b8: 2b00 cmp r3, #0
|
|
80060ba: d011 beq.n 80060e0 <HAL_UART_IRQHandler+0x128>
|
|
80060bc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80060c0: f003 0301 and.w r3, r3, #1
|
|
80060c4: 2b00 cmp r3, #0
|
|
80060c6: d00b beq.n 80060e0 <HAL_UART_IRQHandler+0x128>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
80060c8: 687b ldr r3, [r7, #4]
|
|
80060ca: 681b ldr r3, [r3, #0]
|
|
80060cc: 2204 movs r2, #4
|
|
80060ce: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
80060d0: 687b ldr r3, [r7, #4]
|
|
80060d2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80060d6: f043 0202 orr.w r2, r3, #2
|
|
80060da: 687b ldr r3, [r7, #4]
|
|
80060dc: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART Over-Run interrupt occurred -----------------------------------------*/
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
80060e0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80060e4: f003 0308 and.w r3, r3, #8
|
|
80060e8: 2b00 cmp r3, #0
|
|
80060ea: d017 beq.n 800611c <HAL_UART_IRQHandler+0x164>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
80060ec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80060f0: f003 0320 and.w r3, r3, #32
|
|
80060f4: 2b00 cmp r3, #0
|
|
80060f6: d105 bne.n 8006104 <HAL_UART_IRQHandler+0x14c>
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
80060f8: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc
|
|
80060fc: 4b5c ldr r3, [pc, #368] @ (8006270 <HAL_UART_IRQHandler+0x2b8>)
|
|
80060fe: 4013 ands r3, r2
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
8006100: 2b00 cmp r3, #0
|
|
8006102: d00b beq.n 800611c <HAL_UART_IRQHandler+0x164>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8006104: 687b ldr r3, [r7, #4]
|
|
8006106: 681b ldr r3, [r3, #0]
|
|
8006108: 2208 movs r2, #8
|
|
800610a: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
800610c: 687b ldr r3, [r7, #4]
|
|
800610e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006112: f043 0208 orr.w r2, r3, #8
|
|
8006116: 687b ldr r3, [r7, #4]
|
|
8006118: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
800611c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006120: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8006124: 2b00 cmp r3, #0
|
|
8006126: d012 beq.n 800614e <HAL_UART_IRQHandler+0x196>
|
|
8006128: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800612c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8006130: 2b00 cmp r3, #0
|
|
8006132: d00c beq.n 800614e <HAL_UART_IRQHandler+0x196>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8006134: 687b ldr r3, [r7, #4]
|
|
8006136: 681b ldr r3, [r3, #0]
|
|
8006138: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
800613c: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
800613e: 687b ldr r3, [r7, #4]
|
|
8006140: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006144: f043 0220 orr.w r2, r3, #32
|
|
8006148: 687b ldr r3, [r7, #4]
|
|
800614a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
800614e: 687b ldr r3, [r7, #4]
|
|
8006150: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006154: 2b00 cmp r3, #0
|
|
8006156: f000 8266 beq.w 8006626 <HAL_UART_IRQHandler+0x66e>
|
|
{
|
|
/* UART in mode Receiver --------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
800615a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800615e: f003 0320 and.w r3, r3, #32
|
|
8006162: 2b00 cmp r3, #0
|
|
8006164: d013 beq.n 800618e <HAL_UART_IRQHandler+0x1d6>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
8006166: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800616a: f003 0320 and.w r3, r3, #32
|
|
800616e: 2b00 cmp r3, #0
|
|
8006170: d105 bne.n 800617e <HAL_UART_IRQHandler+0x1c6>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
8006172: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8006176: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800617a: 2b00 cmp r3, #0
|
|
800617c: d007 beq.n 800618e <HAL_UART_IRQHandler+0x1d6>
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
800617e: 687b ldr r3, [r7, #4]
|
|
8006180: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8006182: 2b00 cmp r3, #0
|
|
8006184: d003 beq.n 800618e <HAL_UART_IRQHandler+0x1d6>
|
|
{
|
|
huart->RxISR(huart);
|
|
8006186: 687b ldr r3, [r7, #4]
|
|
8006188: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800618a: 6878 ldr r0, [r7, #4]
|
|
800618c: 4798 blx r3
|
|
/* If Error is to be considered as blocking :
|
|
- Receiver Timeout error in Reception
|
|
- Overrun error in Reception
|
|
- any error occurs in DMA mode reception
|
|
*/
|
|
errorcode = huart->ErrorCode;
|
|
800618e: 687b ldr r3, [r7, #4]
|
|
8006190: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8006194: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8006198: 687b ldr r3, [r7, #4]
|
|
800619a: 681b ldr r3, [r3, #0]
|
|
800619c: 689b ldr r3, [r3, #8]
|
|
800619e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80061a2: 2b40 cmp r3, #64 @ 0x40
|
|
80061a4: d005 beq.n 80061b2 <HAL_UART_IRQHandler+0x1fa>
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
80061a6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
80061aa: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
80061ae: 2b00 cmp r3, #0
|
|
80061b0: d054 beq.n 800625c <HAL_UART_IRQHandler+0x2a4>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
80061b2: 6878 ldr r0, [r7, #4]
|
|
80061b4: f001 f800 bl 80071b8 <UART_EndRxTransfer>
|
|
|
|
/* Abort the UART DMA Rx channel if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80061b8: 687b ldr r3, [r7, #4]
|
|
80061ba: 681b ldr r3, [r3, #0]
|
|
80061bc: 689b ldr r3, [r3, #8]
|
|
80061be: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80061c2: 2b40 cmp r3, #64 @ 0x40
|
|
80061c4: d146 bne.n 8006254 <HAL_UART_IRQHandler+0x29c>
|
|
{
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80061c6: 687b ldr r3, [r7, #4]
|
|
80061c8: 681b ldr r3, [r3, #0]
|
|
80061ca: 3308 adds r3, #8
|
|
80061cc: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80061d0: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
80061d4: e853 3f00 ldrex r3, [r3]
|
|
80061d8: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
80061dc: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80061e0: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80061e4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80061e8: 687b ldr r3, [r7, #4]
|
|
80061ea: 681b ldr r3, [r3, #0]
|
|
80061ec: 3308 adds r3, #8
|
|
80061ee: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
80061f2: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
80061f6: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80061fa: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
80061fe: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
8006202: e841 2300 strex r3, r2, [r1]
|
|
8006206: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
800620a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
800620e: 2b00 cmp r3, #0
|
|
8006210: d1d9 bne.n 80061c6 <HAL_UART_IRQHandler+0x20e>
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
8006212: 687b ldr r3, [r7, #4]
|
|
8006214: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006218: 2b00 cmp r3, #0
|
|
800621a: d017 beq.n 800624c <HAL_UART_IRQHandler+0x294>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
800621c: 687b ldr r3, [r7, #4]
|
|
800621e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006222: 4a15 ldr r2, [pc, #84] @ (8006278 <HAL_UART_IRQHandler+0x2c0>)
|
|
8006224: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
8006226: 687b ldr r3, [r7, #4]
|
|
8006228: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800622c: 4618 mov r0, r3
|
|
800622e: f7fd f8d5 bl 80033dc <HAL_DMA_Abort_IT>
|
|
8006232: 4603 mov r3, r0
|
|
8006234: 2b00 cmp r3, #0
|
|
8006236: d019 beq.n 800626c <HAL_UART_IRQHandler+0x2b4>
|
|
{
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
8006238: 687b ldr r3, [r7, #4]
|
|
800623a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
800623e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006240: 687a ldr r2, [r7, #4]
|
|
8006242: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80
|
|
8006246: 4610 mov r0, r2
|
|
8006248: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800624a: e00f b.n 800626c <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800624c: 6878 ldr r0, [r7, #4]
|
|
800624e: f000 f9f5 bl 800663c <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8006252: e00b b.n 800626c <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8006254: 6878 ldr r0, [r7, #4]
|
|
8006256: f000 f9f1 bl 800663c <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800625a: e007 b.n 800626c <HAL_UART_IRQHandler+0x2b4>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800625c: 6878 ldr r0, [r7, #4]
|
|
800625e: f000 f9ed bl 800663c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006262: 687b ldr r3, [r7, #4]
|
|
8006264: 2200 movs r2, #0
|
|
8006266: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
return;
|
|
800626a: e1dc b.n 8006626 <HAL_UART_IRQHandler+0x66e>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800626c: bf00 nop
|
|
return;
|
|
800626e: e1da b.n 8006626 <HAL_UART_IRQHandler+0x66e>
|
|
8006270: 10000001 .word 0x10000001
|
|
8006274: 04000120 .word 0x04000120
|
|
8006278: 08007285 .word 0x08007285
|
|
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800627c: 687b ldr r3, [r7, #4]
|
|
800627e: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8006280: 2b01 cmp r3, #1
|
|
8006282: f040 8170 bne.w 8006566 <HAL_UART_IRQHandler+0x5ae>
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
8006286: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800628a: f003 0310 and.w r3, r3, #16
|
|
800628e: 2b00 cmp r3, #0
|
|
8006290: f000 8169 beq.w 8006566 <HAL_UART_IRQHandler+0x5ae>
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
8006294: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006298: f003 0310 and.w r3, r3, #16
|
|
800629c: 2b00 cmp r3, #0
|
|
800629e: f000 8162 beq.w 8006566 <HAL_UART_IRQHandler+0x5ae>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80062a2: 687b ldr r3, [r7, #4]
|
|
80062a4: 681b ldr r3, [r3, #0]
|
|
80062a6: 2210 movs r2, #16
|
|
80062a8: 621a str r2, [r3, #32]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80062aa: 687b ldr r3, [r7, #4]
|
|
80062ac: 681b ldr r3, [r3, #0]
|
|
80062ae: 689b ldr r3, [r3, #8]
|
|
80062b0: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80062b4: 2b40 cmp r3, #64 @ 0x40
|
|
80062b6: f040 80d8 bne.w 800646a <HAL_UART_IRQHandler+0x4b2>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
80062ba: 687b ldr r3, [r7, #4]
|
|
80062bc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80062c0: 681b ldr r3, [r3, #0]
|
|
80062c2: 685b ldr r3, [r3, #4]
|
|
80062c4: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
80062c8: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
80062cc: 2b00 cmp r3, #0
|
|
80062ce: f000 80af beq.w 8006430 <HAL_UART_IRQHandler+0x478>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
80062d2: 687b ldr r3, [r7, #4]
|
|
80062d4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
80062d8: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80062dc: 429a cmp r2, r3
|
|
80062de: f080 80a7 bcs.w 8006430 <HAL_UART_IRQHandler+0x478>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
80062e2: 687b ldr r3, [r7, #4]
|
|
80062e4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
80062e8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
80062ec: 687b ldr r3, [r7, #4]
|
|
80062ee: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
80062f2: 681b ldr r3, [r3, #0]
|
|
80062f4: 681b ldr r3, [r3, #0]
|
|
80062f6: f003 0320 and.w r3, r3, #32
|
|
80062fa: 2b00 cmp r3, #0
|
|
80062fc: f040 8087 bne.w 800640e <HAL_UART_IRQHandler+0x456>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8006300: 687b ldr r3, [r7, #4]
|
|
8006302: 681b ldr r3, [r3, #0]
|
|
8006304: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006308: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800630c: e853 3f00 ldrex r3, [r3]
|
|
8006310: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
8006314: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8006318: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800631c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8006320: 687b ldr r3, [r7, #4]
|
|
8006322: 681b ldr r3, [r3, #0]
|
|
8006324: 461a mov r2, r3
|
|
8006326: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
800632a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
800632e: f8c7 2090 str.w r2, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006332: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
8006336: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
800633a: e841 2300 strex r3, r2, [r1]
|
|
800633e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
8006342: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8006346: 2b00 cmp r3, #0
|
|
8006348: d1da bne.n 8006300 <HAL_UART_IRQHandler+0x348>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800634a: 687b ldr r3, [r7, #4]
|
|
800634c: 681b ldr r3, [r3, #0]
|
|
800634e: 3308 adds r3, #8
|
|
8006350: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006352: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8006354: e853 3f00 ldrex r3, [r3]
|
|
8006358: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
800635a: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
800635c: f023 0301 bic.w r3, r3, #1
|
|
8006360: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8006364: 687b ldr r3, [r7, #4]
|
|
8006366: 681b ldr r3, [r3, #0]
|
|
8006368: 3308 adds r3, #8
|
|
800636a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
800636e: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
8006372: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006374: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8006376: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
800637a: e841 2300 strex r3, r2, [r1]
|
|
800637e: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8006380: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8006382: 2b00 cmp r3, #0
|
|
8006384: d1e1 bne.n 800634a <HAL_UART_IRQHandler+0x392>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8006386: 687b ldr r3, [r7, #4]
|
|
8006388: 681b ldr r3, [r3, #0]
|
|
800638a: 3308 adds r3, #8
|
|
800638c: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800638e: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006390: e853 3f00 ldrex r3, [r3]
|
|
8006394: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8006396: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006398: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
800639c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
80063a0: 687b ldr r3, [r7, #4]
|
|
80063a2: 681b ldr r3, [r3, #0]
|
|
80063a4: 3308 adds r3, #8
|
|
80063a6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
80063aa: 66fa str r2, [r7, #108] @ 0x6c
|
|
80063ac: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80063ae: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
80063b0: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
80063b2: e841 2300 strex r3, r2, [r1]
|
|
80063b6: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
80063b8: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
80063ba: 2b00 cmp r3, #0
|
|
80063bc: d1e3 bne.n 8006386 <HAL_UART_IRQHandler+0x3ce>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80063be: 687b ldr r3, [r7, #4]
|
|
80063c0: 2220 movs r2, #32
|
|
80063c2: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80063c6: 687b ldr r3, [r7, #4]
|
|
80063c8: 2200 movs r2, #0
|
|
80063ca: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80063cc: 687b ldr r3, [r7, #4]
|
|
80063ce: 681b ldr r3, [r3, #0]
|
|
80063d0: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80063d2: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80063d4: e853 3f00 ldrex r3, [r3]
|
|
80063d8: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80063da: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80063dc: f023 0310 bic.w r3, r3, #16
|
|
80063e0: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
80063e4: 687b ldr r3, [r7, #4]
|
|
80063e6: 681b ldr r3, [r3, #0]
|
|
80063e8: 461a mov r2, r3
|
|
80063ea: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
80063ee: 65bb str r3, [r7, #88] @ 0x58
|
|
80063f0: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80063f2: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80063f4: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80063f6: e841 2300 strex r3, r2, [r1]
|
|
80063fa: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80063fc: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80063fe: 2b00 cmp r3, #0
|
|
8006400: d1e4 bne.n 80063cc <HAL_UART_IRQHandler+0x414>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
8006402: 687b ldr r3, [r7, #4]
|
|
8006404: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006408: 4618 mov r0, r3
|
|
800640a: f7fc ff8e bl 800332a <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800640e: 687b ldr r3, [r7, #4]
|
|
8006410: 2202 movs r2, #2
|
|
8006412: 671a str r2, [r3, #112] @ 0x70
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8006414: 687b ldr r3, [r7, #4]
|
|
8006416: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
|
|
800641a: 687b ldr r3, [r7, #4]
|
|
800641c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006420: b29b uxth r3, r3
|
|
8006422: 1ad3 subs r3, r2, r3
|
|
8006424: b29b uxth r3, r3
|
|
8006426: 4619 mov r1, r3
|
|
8006428: 6878 ldr r0, [r7, #4]
|
|
800642a: f000 f911 bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
800642e: e0fc b.n 800662a <HAL_UART_IRQHandler+0x672>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
8006430: 687b ldr r3, [r7, #4]
|
|
8006432: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8006436: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
800643a: 429a cmp r2, r3
|
|
800643c: f040 80f5 bne.w 800662a <HAL_UART_IRQHandler+0x672>
|
|
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
8006440: 687b ldr r3, [r7, #4]
|
|
8006442: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006446: 681b ldr r3, [r3, #0]
|
|
8006448: 681b ldr r3, [r3, #0]
|
|
800644a: f003 0320 and.w r3, r3, #32
|
|
800644e: 2b20 cmp r3, #32
|
|
8006450: f040 80eb bne.w 800662a <HAL_UART_IRQHandler+0x672>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8006454: 687b ldr r3, [r7, #4]
|
|
8006456: 2202 movs r2, #2
|
|
8006458: 671a str r2, [r3, #112] @ 0x70
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
800645a: 687b ldr r3, [r7, #4]
|
|
800645c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8006460: 4619 mov r1, r3
|
|
8006462: 6878 ldr r0, [r7, #4]
|
|
8006464: f000 f8f4 bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
8006468: e0df b.n 800662a <HAL_UART_IRQHandler+0x672>
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
800646a: 687b ldr r3, [r7, #4]
|
|
800646c: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c
|
|
8006470: 687b ldr r3, [r7, #4]
|
|
8006472: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006476: b29b uxth r3, r3
|
|
8006478: 1ad3 subs r3, r2, r3
|
|
800647a: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
800647e: 687b ldr r3, [r7, #4]
|
|
8006480: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8006484: b29b uxth r3, r3
|
|
8006486: 2b00 cmp r3, #0
|
|
8006488: f000 80d1 beq.w 800662e <HAL_UART_IRQHandler+0x676>
|
|
&& (nb_rx_data > 0U))
|
|
800648c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
8006490: 2b00 cmp r3, #0
|
|
8006492: f000 80cc beq.w 800662e <HAL_UART_IRQHandler+0x676>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8006496: 687b ldr r3, [r7, #4]
|
|
8006498: 681b ldr r3, [r3, #0]
|
|
800649a: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800649c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800649e: e853 3f00 ldrex r3, [r3]
|
|
80064a2: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
80064a4: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80064a6: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80064aa: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
80064ae: 687b ldr r3, [r7, #4]
|
|
80064b0: 681b ldr r3, [r3, #0]
|
|
80064b2: 461a mov r2, r3
|
|
80064b4: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
80064b8: 647b str r3, [r7, #68] @ 0x44
|
|
80064ba: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80064bc: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80064be: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80064c0: e841 2300 strex r3, r2, [r1]
|
|
80064c4: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80064c6: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80064c8: 2b00 cmp r3, #0
|
|
80064ca: d1e4 bne.n 8006496 <HAL_UART_IRQHandler+0x4de>
|
|
|
|
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
80064cc: 687b ldr r3, [r7, #4]
|
|
80064ce: 681b ldr r3, [r3, #0]
|
|
80064d0: 3308 adds r3, #8
|
|
80064d2: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80064d4: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80064d6: e853 3f00 ldrex r3, [r3]
|
|
80064da: 623b str r3, [r7, #32]
|
|
return(result);
|
|
80064dc: 6a3b ldr r3, [r7, #32]
|
|
80064de: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80064e2: f023 0301 bic.w r3, r3, #1
|
|
80064e6: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
80064ea: 687b ldr r3, [r7, #4]
|
|
80064ec: 681b ldr r3, [r3, #0]
|
|
80064ee: 3308 adds r3, #8
|
|
80064f0: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
80064f4: 633a str r2, [r7, #48] @ 0x30
|
|
80064f6: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80064f8: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80064fa: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
80064fc: e841 2300 strex r3, r2, [r1]
|
|
8006500: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006502: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006504: 2b00 cmp r3, #0
|
|
8006506: d1e1 bne.n 80064cc <HAL_UART_IRQHandler+0x514>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006508: 687b ldr r3, [r7, #4]
|
|
800650a: 2220 movs r2, #32
|
|
800650c: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006510: 687b ldr r3, [r7, #4]
|
|
8006512: 2200 movs r2, #0
|
|
8006514: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8006516: 687b ldr r3, [r7, #4]
|
|
8006518: 2200 movs r2, #0
|
|
800651a: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800651c: 687b ldr r3, [r7, #4]
|
|
800651e: 681b ldr r3, [r3, #0]
|
|
8006520: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006522: 693b ldr r3, [r7, #16]
|
|
8006524: e853 3f00 ldrex r3, [r3]
|
|
8006528: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
800652a: 68fb ldr r3, [r7, #12]
|
|
800652c: f023 0310 bic.w r3, r3, #16
|
|
8006530: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8006534: 687b ldr r3, [r7, #4]
|
|
8006536: 681b ldr r3, [r3, #0]
|
|
8006538: 461a mov r2, r3
|
|
800653a: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
800653e: 61fb str r3, [r7, #28]
|
|
8006540: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006542: 69b9 ldr r1, [r7, #24]
|
|
8006544: 69fa ldr r2, [r7, #28]
|
|
8006546: e841 2300 strex r3, r2, [r1]
|
|
800654a: 617b str r3, [r7, #20]
|
|
return(result);
|
|
800654c: 697b ldr r3, [r7, #20]
|
|
800654e: 2b00 cmp r3, #0
|
|
8006550: d1e4 bne.n 800651c <HAL_UART_IRQHandler+0x564>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8006552: 687b ldr r3, [r7, #4]
|
|
8006554: 2202 movs r2, #2
|
|
8006556: 671a str r2, [r3, #112] @ 0x70
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
8006558: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
800655c: 4619 mov r1, r3
|
|
800655e: 6878 ldr r0, [r7, #4]
|
|
8006560: f000 f876 bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
return;
|
|
8006564: e063 b.n 800662e <HAL_UART_IRQHandler+0x676>
|
|
}
|
|
}
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
8006566: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800656a: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
800656e: 2b00 cmp r3, #0
|
|
8006570: d00e beq.n 8006590 <HAL_UART_IRQHandler+0x5d8>
|
|
8006572: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8006576: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800657a: 2b00 cmp r3, #0
|
|
800657c: d008 beq.n 8006590 <HAL_UART_IRQHandler+0x5d8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
800657e: 687b ldr r3, [r7, #4]
|
|
8006580: 681b ldr r3, [r3, #0]
|
|
8006582: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
8006586: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Wakeup Callback */
|
|
huart->WakeupCallback(huart);
|
|
#else
|
|
/* Call legacy weak Wakeup Callback */
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
8006588: 6878 ldr r0, [r7, #4]
|
|
800658a: f001 fbd9 bl 8007d40 <HAL_UARTEx_WakeupCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
800658e: e051 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART in mode Transmitter ------------------------------------------------*/
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
8006590: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8006594: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006598: 2b00 cmp r3, #0
|
|
800659a: d014 beq.n 80065c6 <HAL_UART_IRQHandler+0x60e>
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
800659c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80065a0: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80065a4: 2b00 cmp r3, #0
|
|
80065a6: d105 bne.n 80065b4 <HAL_UART_IRQHandler+0x5fc>
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
80065a8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80065ac: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80065b0: 2b00 cmp r3, #0
|
|
80065b2: d008 beq.n 80065c6 <HAL_UART_IRQHandler+0x60e>
|
|
{
|
|
if (huart->TxISR != NULL)
|
|
80065b4: 687b ldr r3, [r7, #4]
|
|
80065b6: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
80065b8: 2b00 cmp r3, #0
|
|
80065ba: d03a beq.n 8006632 <HAL_UART_IRQHandler+0x67a>
|
|
{
|
|
huart->TxISR(huart);
|
|
80065bc: 687b ldr r3, [r7, #4]
|
|
80065be: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
80065c0: 6878 ldr r0, [r7, #4]
|
|
80065c2: 4798 blx r3
|
|
}
|
|
return;
|
|
80065c4: e035 b.n 8006632 <HAL_UART_IRQHandler+0x67a>
|
|
}
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
80065c6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80065ca: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80065ce: 2b00 cmp r3, #0
|
|
80065d0: d009 beq.n 80065e6 <HAL_UART_IRQHandler+0x62e>
|
|
80065d2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80065d6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80065da: 2b00 cmp r3, #0
|
|
80065dc: d003 beq.n 80065e6 <HAL_UART_IRQHandler+0x62e>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
80065de: 6878 ldr r0, [r7, #4]
|
|
80065e0: f000 fe62 bl 80072a8 <UART_EndTransmit_IT>
|
|
return;
|
|
80065e4: e026 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART TX Fifo Empty occurred ----------------------------------------------*/
|
|
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
|
|
80065e6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80065ea: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80065ee: 2b00 cmp r3, #0
|
|
80065f0: d009 beq.n 8006606 <HAL_UART_IRQHandler+0x64e>
|
|
80065f2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80065f6: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
|
|
80065fa: 2b00 cmp r3, #0
|
|
80065fc: d003 beq.n 8006606 <HAL_UART_IRQHandler+0x64e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Tx Fifo Empty Callback */
|
|
huart->TxFifoEmptyCallback(huart);
|
|
#else
|
|
/* Call legacy weak Tx Fifo Empty Callback */
|
|
HAL_UARTEx_TxFifoEmptyCallback(huart);
|
|
80065fe: 6878 ldr r0, [r7, #4]
|
|
8006600: f001 fbb2 bl 8007d68 <HAL_UARTEx_TxFifoEmptyCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
8006604: e016 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
}
|
|
|
|
/* UART RX Fifo Full occurred ----------------------------------------------*/
|
|
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
|
|
8006606: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800660a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
800660e: 2b00 cmp r3, #0
|
|
8006610: d010 beq.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
8006612: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8006616: 2b00 cmp r3, #0
|
|
8006618: da0c bge.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Rx Fifo Full Callback */
|
|
huart->RxFifoFullCallback(huart);
|
|
#else
|
|
/* Call legacy weak Rx Fifo Full Callback */
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
800661a: 6878 ldr r0, [r7, #4]
|
|
800661c: f001 fb9a bl 8007d54 <HAL_UARTEx_RxFifoFullCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
8006620: e008 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8006622: bf00 nop
|
|
8006624: e006 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8006626: bf00 nop
|
|
8006628: e004 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
800662a: bf00 nop
|
|
800662c: e002 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
800662e: bf00 nop
|
|
8006630: e000 b.n 8006634 <HAL_UART_IRQHandler+0x67c>
|
|
return;
|
|
8006632: bf00 nop
|
|
}
|
|
}
|
|
8006634: 37e8 adds r7, #232 @ 0xe8
|
|
8006636: 46bd mov sp, r7
|
|
8006638: bd80 pop {r7, pc}
|
|
800663a: bf00 nop
|
|
|
|
0800663c <HAL_UART_ErrorCallback>:
|
|
* @brief UART error callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800663c: b480 push {r7}
|
|
800663e: b083 sub sp, #12
|
|
8006640: af00 add r7, sp, #0
|
|
8006642: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8006644: bf00 nop
|
|
8006646: 370c adds r7, #12
|
|
8006648: 46bd mov sp, r7
|
|
800664a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800664e: 4770 bx lr
|
|
|
|
08006650 <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
8006650: b480 push {r7}
|
|
8006652: b083 sub sp, #12
|
|
8006654: af00 add r7, sp, #0
|
|
8006656: 6078 str r0, [r7, #4]
|
|
8006658: 460b mov r3, r1
|
|
800665a: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800665c: bf00 nop
|
|
800665e: 370c adds r7, #12
|
|
8006660: 46bd mov sp, r7
|
|
8006662: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006666: 4770 bx lr
|
|
|
|
08006668 <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8006668: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
800666c: b08c sub sp, #48 @ 0x30
|
|
800666e: af00 add r7, sp, #0
|
|
8006670: 6178 str r0, [r7, #20]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8006672: 2300 movs r3, #0
|
|
8006674: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8006678: 697b ldr r3, [r7, #20]
|
|
800667a: 689a ldr r2, [r3, #8]
|
|
800667c: 697b ldr r3, [r7, #20]
|
|
800667e: 691b ldr r3, [r3, #16]
|
|
8006680: 431a orrs r2, r3
|
|
8006682: 697b ldr r3, [r7, #20]
|
|
8006684: 695b ldr r3, [r3, #20]
|
|
8006686: 431a orrs r2, r3
|
|
8006688: 697b ldr r3, [r7, #20]
|
|
800668a: 69db ldr r3, [r3, #28]
|
|
800668c: 4313 orrs r3, r2
|
|
800668e: 62fb str r3, [r7, #44] @ 0x2c
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8006690: 697b ldr r3, [r7, #20]
|
|
8006692: 681b ldr r3, [r3, #0]
|
|
8006694: 681a ldr r2, [r3, #0]
|
|
8006696: 4bab ldr r3, [pc, #684] @ (8006944 <UART_SetConfig+0x2dc>)
|
|
8006698: 4013 ands r3, r2
|
|
800669a: 697a ldr r2, [r7, #20]
|
|
800669c: 6812 ldr r2, [r2, #0]
|
|
800669e: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80066a0: 430b orrs r3, r1
|
|
80066a2: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80066a4: 697b ldr r3, [r7, #20]
|
|
80066a6: 681b ldr r3, [r3, #0]
|
|
80066a8: 685b ldr r3, [r3, #4]
|
|
80066aa: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
80066ae: 697b ldr r3, [r7, #20]
|
|
80066b0: 68da ldr r2, [r3, #12]
|
|
80066b2: 697b ldr r3, [r7, #20]
|
|
80066b4: 681b ldr r3, [r3, #0]
|
|
80066b6: 430a orrs r2, r1
|
|
80066b8: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
80066ba: 697b ldr r3, [r7, #20]
|
|
80066bc: 699b ldr r3, [r3, #24]
|
|
80066be: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
80066c0: 697b ldr r3, [r7, #20]
|
|
80066c2: 681b ldr r3, [r3, #0]
|
|
80066c4: 4aa0 ldr r2, [pc, #640] @ (8006948 <UART_SetConfig+0x2e0>)
|
|
80066c6: 4293 cmp r3, r2
|
|
80066c8: d004 beq.n 80066d4 <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
80066ca: 697b ldr r3, [r7, #20]
|
|
80066cc: 6a1b ldr r3, [r3, #32]
|
|
80066ce: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80066d0: 4313 orrs r3, r2
|
|
80066d2: 62fb str r3, [r7, #44] @ 0x2c
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
80066d4: 697b ldr r3, [r7, #20]
|
|
80066d6: 681b ldr r3, [r3, #0]
|
|
80066d8: 689b ldr r3, [r3, #8]
|
|
80066da: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
|
|
80066de: f423 6330 bic.w r3, r3, #2816 @ 0xb00
|
|
80066e2: 697a ldr r2, [r7, #20]
|
|
80066e4: 6812 ldr r2, [r2, #0]
|
|
80066e6: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
80066e8: 430b orrs r3, r1
|
|
80066ea: 6093 str r3, [r2, #8]
|
|
|
|
/*-------------------------- USART PRESC Configuration -----------------------*/
|
|
/* Configure
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
80066ec: 697b ldr r3, [r7, #20]
|
|
80066ee: 681b ldr r3, [r3, #0]
|
|
80066f0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80066f2: f023 010f bic.w r1, r3, #15
|
|
80066f6: 697b ldr r3, [r7, #20]
|
|
80066f8: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80066fa: 697b ldr r3, [r7, #20]
|
|
80066fc: 681b ldr r3, [r3, #0]
|
|
80066fe: 430a orrs r2, r1
|
|
8006700: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8006702: 697b ldr r3, [r7, #20]
|
|
8006704: 681b ldr r3, [r3, #0]
|
|
8006706: 4a91 ldr r2, [pc, #580] @ (800694c <UART_SetConfig+0x2e4>)
|
|
8006708: 4293 cmp r3, r2
|
|
800670a: d125 bne.n 8006758 <UART_SetConfig+0xf0>
|
|
800670c: 4b90 ldr r3, [pc, #576] @ (8006950 <UART_SetConfig+0x2e8>)
|
|
800670e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006712: f003 0303 and.w r3, r3, #3
|
|
8006716: 2b03 cmp r3, #3
|
|
8006718: d81a bhi.n 8006750 <UART_SetConfig+0xe8>
|
|
800671a: a201 add r2, pc, #4 @ (adr r2, 8006720 <UART_SetConfig+0xb8>)
|
|
800671c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006720: 08006731 .word 0x08006731
|
|
8006724: 08006741 .word 0x08006741
|
|
8006728: 08006739 .word 0x08006739
|
|
800672c: 08006749 .word 0x08006749
|
|
8006730: 2301 movs r3, #1
|
|
8006732: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006736: e0d6 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006738: 2302 movs r3, #2
|
|
800673a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800673e: e0d2 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006740: 2304 movs r3, #4
|
|
8006742: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006746: e0ce b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006748: 2308 movs r3, #8
|
|
800674a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800674e: e0ca b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006750: 2310 movs r3, #16
|
|
8006752: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006756: e0c6 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006758: 697b ldr r3, [r7, #20]
|
|
800675a: 681b ldr r3, [r3, #0]
|
|
800675c: 4a7d ldr r2, [pc, #500] @ (8006954 <UART_SetConfig+0x2ec>)
|
|
800675e: 4293 cmp r3, r2
|
|
8006760: d138 bne.n 80067d4 <UART_SetConfig+0x16c>
|
|
8006762: 4b7b ldr r3, [pc, #492] @ (8006950 <UART_SetConfig+0x2e8>)
|
|
8006764: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006768: f003 030c and.w r3, r3, #12
|
|
800676c: 2b0c cmp r3, #12
|
|
800676e: d82d bhi.n 80067cc <UART_SetConfig+0x164>
|
|
8006770: a201 add r2, pc, #4 @ (adr r2, 8006778 <UART_SetConfig+0x110>)
|
|
8006772: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006776: bf00 nop
|
|
8006778: 080067ad .word 0x080067ad
|
|
800677c: 080067cd .word 0x080067cd
|
|
8006780: 080067cd .word 0x080067cd
|
|
8006784: 080067cd .word 0x080067cd
|
|
8006788: 080067bd .word 0x080067bd
|
|
800678c: 080067cd .word 0x080067cd
|
|
8006790: 080067cd .word 0x080067cd
|
|
8006794: 080067cd .word 0x080067cd
|
|
8006798: 080067b5 .word 0x080067b5
|
|
800679c: 080067cd .word 0x080067cd
|
|
80067a0: 080067cd .word 0x080067cd
|
|
80067a4: 080067cd .word 0x080067cd
|
|
80067a8: 080067c5 .word 0x080067c5
|
|
80067ac: 2300 movs r3, #0
|
|
80067ae: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80067b2: e098 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80067b4: 2302 movs r3, #2
|
|
80067b6: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80067ba: e094 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80067bc: 2304 movs r3, #4
|
|
80067be: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80067c2: e090 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80067c4: 2308 movs r3, #8
|
|
80067c6: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80067ca: e08c b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80067cc: 2310 movs r3, #16
|
|
80067ce: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80067d2: e088 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80067d4: 697b ldr r3, [r7, #20]
|
|
80067d6: 681b ldr r3, [r3, #0]
|
|
80067d8: 4a5f ldr r2, [pc, #380] @ (8006958 <UART_SetConfig+0x2f0>)
|
|
80067da: 4293 cmp r3, r2
|
|
80067dc: d125 bne.n 800682a <UART_SetConfig+0x1c2>
|
|
80067de: 4b5c ldr r3, [pc, #368] @ (8006950 <UART_SetConfig+0x2e8>)
|
|
80067e0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80067e4: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
80067e8: 2b30 cmp r3, #48 @ 0x30
|
|
80067ea: d016 beq.n 800681a <UART_SetConfig+0x1b2>
|
|
80067ec: 2b30 cmp r3, #48 @ 0x30
|
|
80067ee: d818 bhi.n 8006822 <UART_SetConfig+0x1ba>
|
|
80067f0: 2b20 cmp r3, #32
|
|
80067f2: d00a beq.n 800680a <UART_SetConfig+0x1a2>
|
|
80067f4: 2b20 cmp r3, #32
|
|
80067f6: d814 bhi.n 8006822 <UART_SetConfig+0x1ba>
|
|
80067f8: 2b00 cmp r3, #0
|
|
80067fa: d002 beq.n 8006802 <UART_SetConfig+0x19a>
|
|
80067fc: 2b10 cmp r3, #16
|
|
80067fe: d008 beq.n 8006812 <UART_SetConfig+0x1aa>
|
|
8006800: e00f b.n 8006822 <UART_SetConfig+0x1ba>
|
|
8006802: 2300 movs r3, #0
|
|
8006804: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006808: e06d b.n 80068e6 <UART_SetConfig+0x27e>
|
|
800680a: 2302 movs r3, #2
|
|
800680c: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006810: e069 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006812: 2304 movs r3, #4
|
|
8006814: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006818: e065 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
800681a: 2308 movs r3, #8
|
|
800681c: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006820: e061 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006822: 2310 movs r3, #16
|
|
8006824: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006828: e05d b.n 80068e6 <UART_SetConfig+0x27e>
|
|
800682a: 697b ldr r3, [r7, #20]
|
|
800682c: 681b ldr r3, [r3, #0]
|
|
800682e: 4a4b ldr r2, [pc, #300] @ (800695c <UART_SetConfig+0x2f4>)
|
|
8006830: 4293 cmp r3, r2
|
|
8006832: d125 bne.n 8006880 <UART_SetConfig+0x218>
|
|
8006834: 4b46 ldr r3, [pc, #280] @ (8006950 <UART_SetConfig+0x2e8>)
|
|
8006836: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800683a: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
800683e: 2bc0 cmp r3, #192 @ 0xc0
|
|
8006840: d016 beq.n 8006870 <UART_SetConfig+0x208>
|
|
8006842: 2bc0 cmp r3, #192 @ 0xc0
|
|
8006844: d818 bhi.n 8006878 <UART_SetConfig+0x210>
|
|
8006846: 2b80 cmp r3, #128 @ 0x80
|
|
8006848: d00a beq.n 8006860 <UART_SetConfig+0x1f8>
|
|
800684a: 2b80 cmp r3, #128 @ 0x80
|
|
800684c: d814 bhi.n 8006878 <UART_SetConfig+0x210>
|
|
800684e: 2b00 cmp r3, #0
|
|
8006850: d002 beq.n 8006858 <UART_SetConfig+0x1f0>
|
|
8006852: 2b40 cmp r3, #64 @ 0x40
|
|
8006854: d008 beq.n 8006868 <UART_SetConfig+0x200>
|
|
8006856: e00f b.n 8006878 <UART_SetConfig+0x210>
|
|
8006858: 2300 movs r3, #0
|
|
800685a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800685e: e042 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006860: 2302 movs r3, #2
|
|
8006862: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006866: e03e b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006868: 2304 movs r3, #4
|
|
800686a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800686e: e03a b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006870: 2308 movs r3, #8
|
|
8006872: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
8006876: e036 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006878: 2310 movs r3, #16
|
|
800687a: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
800687e: e032 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
8006880: 697b ldr r3, [r7, #20]
|
|
8006882: 681b ldr r3, [r3, #0]
|
|
8006884: 4a30 ldr r2, [pc, #192] @ (8006948 <UART_SetConfig+0x2e0>)
|
|
8006886: 4293 cmp r3, r2
|
|
8006888: d12a bne.n 80068e0 <UART_SetConfig+0x278>
|
|
800688a: 4b31 ldr r3, [pc, #196] @ (8006950 <UART_SetConfig+0x2e8>)
|
|
800688c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8006890: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
8006894: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
8006898: d01a beq.n 80068d0 <UART_SetConfig+0x268>
|
|
800689a: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
800689e: d81b bhi.n 80068d8 <UART_SetConfig+0x270>
|
|
80068a0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80068a4: d00c beq.n 80068c0 <UART_SetConfig+0x258>
|
|
80068a6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
80068aa: d815 bhi.n 80068d8 <UART_SetConfig+0x270>
|
|
80068ac: 2b00 cmp r3, #0
|
|
80068ae: d003 beq.n 80068b8 <UART_SetConfig+0x250>
|
|
80068b0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80068b4: d008 beq.n 80068c8 <UART_SetConfig+0x260>
|
|
80068b6: e00f b.n 80068d8 <UART_SetConfig+0x270>
|
|
80068b8: 2300 movs r3, #0
|
|
80068ba: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80068be: e012 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80068c0: 2302 movs r3, #2
|
|
80068c2: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80068c6: e00e b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80068c8: 2304 movs r3, #4
|
|
80068ca: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80068ce: e00a b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80068d0: 2308 movs r3, #8
|
|
80068d2: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80068d6: e006 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80068d8: 2310 movs r3, #16
|
|
80068da: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
80068de: e002 b.n 80068e6 <UART_SetConfig+0x27e>
|
|
80068e0: 2310 movs r3, #16
|
|
80068e2: f887 302b strb.w r3, [r7, #43] @ 0x2b
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
80068e6: 697b ldr r3, [r7, #20]
|
|
80068e8: 681b ldr r3, [r3, #0]
|
|
80068ea: 4a17 ldr r2, [pc, #92] @ (8006948 <UART_SetConfig+0x2e0>)
|
|
80068ec: 4293 cmp r3, r2
|
|
80068ee: f040 80a8 bne.w 8006a42 <UART_SetConfig+0x3da>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
80068f2: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
80068f6: 2b08 cmp r3, #8
|
|
80068f8: d834 bhi.n 8006964 <UART_SetConfig+0x2fc>
|
|
80068fa: a201 add r2, pc, #4 @ (adr r2, 8006900 <UART_SetConfig+0x298>)
|
|
80068fc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006900: 08006925 .word 0x08006925
|
|
8006904: 08006965 .word 0x08006965
|
|
8006908: 0800692d .word 0x0800692d
|
|
800690c: 08006965 .word 0x08006965
|
|
8006910: 08006933 .word 0x08006933
|
|
8006914: 08006965 .word 0x08006965
|
|
8006918: 08006965 .word 0x08006965
|
|
800691c: 08006965 .word 0x08006965
|
|
8006920: 0800693b .word 0x0800693b
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006924: f7fd fccc bl 80042c0 <HAL_RCC_GetPCLK1Freq>
|
|
8006928: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
800692a: e021 b.n 8006970 <UART_SetConfig+0x308>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
800692c: 4b0c ldr r3, [pc, #48] @ (8006960 <UART_SetConfig+0x2f8>)
|
|
800692e: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8006930: e01e b.n 8006970 <UART_SetConfig+0x308>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006932: f7fd fc57 bl 80041e4 <HAL_RCC_GetSysClockFreq>
|
|
8006936: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006938: e01a b.n 8006970 <UART_SetConfig+0x308>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800693a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800693e: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8006940: e016 b.n 8006970 <UART_SetConfig+0x308>
|
|
8006942: bf00 nop
|
|
8006944: cfff69f3 .word 0xcfff69f3
|
|
8006948: 40008000 .word 0x40008000
|
|
800694c: 40013800 .word 0x40013800
|
|
8006950: 40021000 .word 0x40021000
|
|
8006954: 40004400 .word 0x40004400
|
|
8006958: 40004800 .word 0x40004800
|
|
800695c: 40004c00 .word 0x40004c00
|
|
8006960: 00f42400 .word 0x00f42400
|
|
default:
|
|
pclk = 0U;
|
|
8006964: 2300 movs r3, #0
|
|
8006966: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
8006968: 2301 movs r3, #1
|
|
800696a: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
800696e: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
8006970: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006972: 2b00 cmp r3, #0
|
|
8006974: f000 812a beq.w 8006bcc <UART_SetConfig+0x564>
|
|
{
|
|
/* Compute clock after Prescaler */
|
|
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
|
|
8006978: 697b ldr r3, [r7, #20]
|
|
800697a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800697c: 4a9e ldr r2, [pc, #632] @ (8006bf8 <UART_SetConfig+0x590>)
|
|
800697e: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8006982: 461a mov r2, r3
|
|
8006984: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006986: fbb3 f3f2 udiv r3, r3, r2
|
|
800698a: 61bb str r3, [r7, #24]
|
|
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
|
|
800698c: 697b ldr r3, [r7, #20]
|
|
800698e: 685a ldr r2, [r3, #4]
|
|
8006990: 4613 mov r3, r2
|
|
8006992: 005b lsls r3, r3, #1
|
|
8006994: 4413 add r3, r2
|
|
8006996: 69ba ldr r2, [r7, #24]
|
|
8006998: 429a cmp r2, r3
|
|
800699a: d305 bcc.n 80069a8 <UART_SetConfig+0x340>
|
|
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
|
|
800699c: 697b ldr r3, [r7, #20]
|
|
800699e: 685b ldr r3, [r3, #4]
|
|
80069a0: 031b lsls r3, r3, #12
|
|
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
|
|
80069a2: 69ba ldr r2, [r7, #24]
|
|
80069a4: 429a cmp r2, r3
|
|
80069a6: d903 bls.n 80069b0 <UART_SetConfig+0x348>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80069a8: 2301 movs r3, #1
|
|
80069aa: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
80069ae: e10d b.n 8006bcc <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
/* Check computed UsartDiv value is in allocated range
|
|
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
80069b0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80069b2: 2200 movs r2, #0
|
|
80069b4: 60bb str r3, [r7, #8]
|
|
80069b6: 60fa str r2, [r7, #12]
|
|
80069b8: 697b ldr r3, [r7, #20]
|
|
80069ba: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80069bc: 4a8e ldr r2, [pc, #568] @ (8006bf8 <UART_SetConfig+0x590>)
|
|
80069be: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
80069c2: b29b uxth r3, r3
|
|
80069c4: 2200 movs r2, #0
|
|
80069c6: 603b str r3, [r7, #0]
|
|
80069c8: 607a str r2, [r7, #4]
|
|
80069ca: e9d7 2300 ldrd r2, r3, [r7]
|
|
80069ce: e9d7 0102 ldrd r0, r1, [r7, #8]
|
|
80069d2: f7f9 fc21 bl 8000218 <__aeabi_uldivmod>
|
|
80069d6: 4602 mov r2, r0
|
|
80069d8: 460b mov r3, r1
|
|
80069da: 4610 mov r0, r2
|
|
80069dc: 4619 mov r1, r3
|
|
80069de: f04f 0200 mov.w r2, #0
|
|
80069e2: f04f 0300 mov.w r3, #0
|
|
80069e6: 020b lsls r3, r1, #8
|
|
80069e8: ea43 6310 orr.w r3, r3, r0, lsr #24
|
|
80069ec: 0202 lsls r2, r0, #8
|
|
80069ee: 6979 ldr r1, [r7, #20]
|
|
80069f0: 6849 ldr r1, [r1, #4]
|
|
80069f2: 0849 lsrs r1, r1, #1
|
|
80069f4: 2000 movs r0, #0
|
|
80069f6: 460c mov r4, r1
|
|
80069f8: 4605 mov r5, r0
|
|
80069fa: eb12 0804 adds.w r8, r2, r4
|
|
80069fe: eb43 0905 adc.w r9, r3, r5
|
|
8006a02: 697b ldr r3, [r7, #20]
|
|
8006a04: 685b ldr r3, [r3, #4]
|
|
8006a06: 2200 movs r2, #0
|
|
8006a08: 469a mov sl, r3
|
|
8006a0a: 4693 mov fp, r2
|
|
8006a0c: 4652 mov r2, sl
|
|
8006a0e: 465b mov r3, fp
|
|
8006a10: 4640 mov r0, r8
|
|
8006a12: 4649 mov r1, r9
|
|
8006a14: f7f9 fc00 bl 8000218 <__aeabi_uldivmod>
|
|
8006a18: 4602 mov r2, r0
|
|
8006a1a: 460b mov r3, r1
|
|
8006a1c: 4613 mov r3, r2
|
|
8006a1e: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
8006a20: 6a3b ldr r3, [r7, #32]
|
|
8006a22: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8006a26: d308 bcc.n 8006a3a <UART_SetConfig+0x3d2>
|
|
8006a28: 6a3b ldr r3, [r7, #32]
|
|
8006a2a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8006a2e: d204 bcs.n 8006a3a <UART_SetConfig+0x3d2>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8006a30: 697b ldr r3, [r7, #20]
|
|
8006a32: 681b ldr r3, [r3, #0]
|
|
8006a34: 6a3a ldr r2, [r7, #32]
|
|
8006a36: 60da str r2, [r3, #12]
|
|
8006a38: e0c8 b.n 8006bcc <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006a3a: 2301 movs r3, #1
|
|
8006a3c: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8006a40: e0c4 b.n 8006bcc <UART_SetConfig+0x564>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8006a42: 697b ldr r3, [r7, #20]
|
|
8006a44: 69db ldr r3, [r3, #28]
|
|
8006a46: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8006a4a: d167 bne.n 8006b1c <UART_SetConfig+0x4b4>
|
|
{
|
|
switch (clocksource)
|
|
8006a4c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
8006a50: 2b08 cmp r3, #8
|
|
8006a52: d828 bhi.n 8006aa6 <UART_SetConfig+0x43e>
|
|
8006a54: a201 add r2, pc, #4 @ (adr r2, 8006a5c <UART_SetConfig+0x3f4>)
|
|
8006a56: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006a5a: bf00 nop
|
|
8006a5c: 08006a81 .word 0x08006a81
|
|
8006a60: 08006a89 .word 0x08006a89
|
|
8006a64: 08006a91 .word 0x08006a91
|
|
8006a68: 08006aa7 .word 0x08006aa7
|
|
8006a6c: 08006a97 .word 0x08006a97
|
|
8006a70: 08006aa7 .word 0x08006aa7
|
|
8006a74: 08006aa7 .word 0x08006aa7
|
|
8006a78: 08006aa7 .word 0x08006aa7
|
|
8006a7c: 08006a9f .word 0x08006a9f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006a80: f7fd fc1e bl 80042c0 <HAL_RCC_GetPCLK1Freq>
|
|
8006a84: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006a86: e014 b.n 8006ab2 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006a88: f7fd fc30 bl 80042ec <HAL_RCC_GetPCLK2Freq>
|
|
8006a8c: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006a8e: e010 b.n 8006ab2 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8006a90: 4b5a ldr r3, [pc, #360] @ (8006bfc <UART_SetConfig+0x594>)
|
|
8006a92: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8006a94: e00d b.n 8006ab2 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006a96: f7fd fba5 bl 80041e4 <HAL_RCC_GetSysClockFreq>
|
|
8006a9a: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006a9c: e009 b.n 8006ab2 <UART_SetConfig+0x44a>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8006a9e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8006aa2: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8006aa4: e005 b.n 8006ab2 <UART_SetConfig+0x44a>
|
|
default:
|
|
pclk = 0U;
|
|
8006aa6: 2300 movs r3, #0
|
|
8006aa8: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
8006aaa: 2301 movs r3, #1
|
|
8006aac: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8006ab0: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
8006ab2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006ab4: 2b00 cmp r3, #0
|
|
8006ab6: f000 8089 beq.w 8006bcc <UART_SetConfig+0x564>
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8006aba: 697b ldr r3, [r7, #20]
|
|
8006abc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006abe: 4a4e ldr r2, [pc, #312] @ (8006bf8 <UART_SetConfig+0x590>)
|
|
8006ac0: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8006ac4: 461a mov r2, r3
|
|
8006ac6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006ac8: fbb3 f3f2 udiv r3, r3, r2
|
|
8006acc: 005a lsls r2, r3, #1
|
|
8006ace: 697b ldr r3, [r7, #20]
|
|
8006ad0: 685b ldr r3, [r3, #4]
|
|
8006ad2: 085b lsrs r3, r3, #1
|
|
8006ad4: 441a add r2, r3
|
|
8006ad6: 697b ldr r3, [r7, #20]
|
|
8006ad8: 685b ldr r3, [r3, #4]
|
|
8006ada: fbb2 f3f3 udiv r3, r2, r3
|
|
8006ade: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8006ae0: 6a3b ldr r3, [r7, #32]
|
|
8006ae2: 2b0f cmp r3, #15
|
|
8006ae4: d916 bls.n 8006b14 <UART_SetConfig+0x4ac>
|
|
8006ae6: 6a3b ldr r3, [r7, #32]
|
|
8006ae8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006aec: d212 bcs.n 8006b14 <UART_SetConfig+0x4ac>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8006aee: 6a3b ldr r3, [r7, #32]
|
|
8006af0: b29b uxth r3, r3
|
|
8006af2: f023 030f bic.w r3, r3, #15
|
|
8006af6: 83fb strh r3, [r7, #30]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8006af8: 6a3b ldr r3, [r7, #32]
|
|
8006afa: 085b lsrs r3, r3, #1
|
|
8006afc: b29b uxth r3, r3
|
|
8006afe: f003 0307 and.w r3, r3, #7
|
|
8006b02: b29a uxth r2, r3
|
|
8006b04: 8bfb ldrh r3, [r7, #30]
|
|
8006b06: 4313 orrs r3, r2
|
|
8006b08: 83fb strh r3, [r7, #30]
|
|
huart->Instance->BRR = brrtemp;
|
|
8006b0a: 697b ldr r3, [r7, #20]
|
|
8006b0c: 681b ldr r3, [r3, #0]
|
|
8006b0e: 8bfa ldrh r2, [r7, #30]
|
|
8006b10: 60da str r2, [r3, #12]
|
|
8006b12: e05b b.n 8006bcc <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006b14: 2301 movs r3, #1
|
|
8006b16: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
8006b1a: e057 b.n 8006bcc <UART_SetConfig+0x564>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
8006b1c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
|
|
8006b20: 2b08 cmp r3, #8
|
|
8006b22: d828 bhi.n 8006b76 <UART_SetConfig+0x50e>
|
|
8006b24: a201 add r2, pc, #4 @ (adr r2, 8006b2c <UART_SetConfig+0x4c4>)
|
|
8006b26: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006b2a: bf00 nop
|
|
8006b2c: 08006b51 .word 0x08006b51
|
|
8006b30: 08006b59 .word 0x08006b59
|
|
8006b34: 08006b61 .word 0x08006b61
|
|
8006b38: 08006b77 .word 0x08006b77
|
|
8006b3c: 08006b67 .word 0x08006b67
|
|
8006b40: 08006b77 .word 0x08006b77
|
|
8006b44: 08006b77 .word 0x08006b77
|
|
8006b48: 08006b77 .word 0x08006b77
|
|
8006b4c: 08006b6f .word 0x08006b6f
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006b50: f7fd fbb6 bl 80042c0 <HAL_RCC_GetPCLK1Freq>
|
|
8006b54: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006b56: e014 b.n 8006b82 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8006b58: f7fd fbc8 bl 80042ec <HAL_RCC_GetPCLK2Freq>
|
|
8006b5c: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006b5e: e010 b.n 8006b82 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8006b60: 4b26 ldr r3, [pc, #152] @ (8006bfc <UART_SetConfig+0x594>)
|
|
8006b62: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8006b64: e00d b.n 8006b82 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8006b66: f7fd fb3d bl 80041e4 <HAL_RCC_GetSysClockFreq>
|
|
8006b6a: 6278 str r0, [r7, #36] @ 0x24
|
|
break;
|
|
8006b6c: e009 b.n 8006b82 <UART_SetConfig+0x51a>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8006b6e: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8006b72: 627b str r3, [r7, #36] @ 0x24
|
|
break;
|
|
8006b74: e005 b.n 8006b82 <UART_SetConfig+0x51a>
|
|
default:
|
|
pclk = 0U;
|
|
8006b76: 2300 movs r3, #0
|
|
8006b78: 627b str r3, [r7, #36] @ 0x24
|
|
ret = HAL_ERROR;
|
|
8006b7a: 2301 movs r3, #1
|
|
8006b7c: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
break;
|
|
8006b80: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8006b82: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b84: 2b00 cmp r3, #0
|
|
8006b86: d021 beq.n 8006bcc <UART_SetConfig+0x564>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8006b88: 697b ldr r3, [r7, #20]
|
|
8006b8a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006b8c: 4a1a ldr r2, [pc, #104] @ (8006bf8 <UART_SetConfig+0x590>)
|
|
8006b8e: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
|
|
8006b92: 461a mov r2, r3
|
|
8006b94: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006b96: fbb3 f2f2 udiv r2, r3, r2
|
|
8006b9a: 697b ldr r3, [r7, #20]
|
|
8006b9c: 685b ldr r3, [r3, #4]
|
|
8006b9e: 085b lsrs r3, r3, #1
|
|
8006ba0: 441a add r2, r3
|
|
8006ba2: 697b ldr r3, [r7, #20]
|
|
8006ba4: 685b ldr r3, [r3, #4]
|
|
8006ba6: fbb2 f3f3 udiv r3, r2, r3
|
|
8006baa: 623b str r3, [r7, #32]
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8006bac: 6a3b ldr r3, [r7, #32]
|
|
8006bae: 2b0f cmp r3, #15
|
|
8006bb0: d909 bls.n 8006bc6 <UART_SetConfig+0x55e>
|
|
8006bb2: 6a3b ldr r3, [r7, #32]
|
|
8006bb4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8006bb8: d205 bcs.n 8006bc6 <UART_SetConfig+0x55e>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
8006bba: 6a3b ldr r3, [r7, #32]
|
|
8006bbc: b29a uxth r2, r3
|
|
8006bbe: 697b ldr r3, [r7, #20]
|
|
8006bc0: 681b ldr r3, [r3, #0]
|
|
8006bc2: 60da str r2, [r3, #12]
|
|
8006bc4: e002 b.n 8006bcc <UART_SetConfig+0x564>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006bc6: 2301 movs r3, #1
|
|
8006bc8: f887 302a strb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Initialize the number of data to process during RX/TX ISR execution */
|
|
huart->NbTxDataToProcess = 1;
|
|
8006bcc: 697b ldr r3, [r7, #20]
|
|
8006bce: 2201 movs r2, #1
|
|
8006bd0: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = 1;
|
|
8006bd4: 697b ldr r3, [r7, #20]
|
|
8006bd6: 2201 movs r2, #1
|
|
8006bd8: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
8006bdc: 697b ldr r3, [r7, #20]
|
|
8006bde: 2200 movs r2, #0
|
|
8006be0: 675a str r2, [r3, #116] @ 0x74
|
|
huart->TxISR = NULL;
|
|
8006be2: 697b ldr r3, [r7, #20]
|
|
8006be4: 2200 movs r2, #0
|
|
8006be6: 679a str r2, [r3, #120] @ 0x78
|
|
|
|
return ret;
|
|
8006be8: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
|
|
}
|
|
8006bec: 4618 mov r0, r3
|
|
8006bee: 3730 adds r7, #48 @ 0x30
|
|
8006bf0: 46bd mov sp, r7
|
|
8006bf2: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8006bf6: bf00 nop
|
|
8006bf8: 08008040 .word 0x08008040
|
|
8006bfc: 00f42400 .word 0x00f42400
|
|
|
|
08006c00 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8006c00: b480 push {r7}
|
|
8006c02: b083 sub sp, #12
|
|
8006c04: af00 add r7, sp, #0
|
|
8006c06: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8006c08: 687b ldr r3, [r7, #4]
|
|
8006c0a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006c0c: f003 0308 and.w r3, r3, #8
|
|
8006c10: 2b00 cmp r3, #0
|
|
8006c12: d00a beq.n 8006c2a <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8006c14: 687b ldr r3, [r7, #4]
|
|
8006c16: 681b ldr r3, [r3, #0]
|
|
8006c18: 685b ldr r3, [r3, #4]
|
|
8006c1a: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
8006c1e: 687b ldr r3, [r7, #4]
|
|
8006c20: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8006c22: 687b ldr r3, [r7, #4]
|
|
8006c24: 681b ldr r3, [r3, #0]
|
|
8006c26: 430a orrs r2, r1
|
|
8006c28: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8006c2a: 687b ldr r3, [r7, #4]
|
|
8006c2c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006c2e: f003 0301 and.w r3, r3, #1
|
|
8006c32: 2b00 cmp r3, #0
|
|
8006c34: d00a beq.n 8006c4c <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
8006c36: 687b ldr r3, [r7, #4]
|
|
8006c38: 681b ldr r3, [r3, #0]
|
|
8006c3a: 685b ldr r3, [r3, #4]
|
|
8006c3c: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8006c40: 687b ldr r3, [r7, #4]
|
|
8006c42: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8006c44: 687b ldr r3, [r7, #4]
|
|
8006c46: 681b ldr r3, [r3, #0]
|
|
8006c48: 430a orrs r2, r1
|
|
8006c4a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8006c4c: 687b ldr r3, [r7, #4]
|
|
8006c4e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006c50: f003 0302 and.w r3, r3, #2
|
|
8006c54: 2b00 cmp r3, #0
|
|
8006c56: d00a beq.n 8006c6e <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8006c58: 687b ldr r3, [r7, #4]
|
|
8006c5a: 681b ldr r3, [r3, #0]
|
|
8006c5c: 685b ldr r3, [r3, #4]
|
|
8006c5e: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8006c62: 687b ldr r3, [r7, #4]
|
|
8006c64: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8006c66: 687b ldr r3, [r7, #4]
|
|
8006c68: 681b ldr r3, [r3, #0]
|
|
8006c6a: 430a orrs r2, r1
|
|
8006c6c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8006c6e: 687b ldr r3, [r7, #4]
|
|
8006c70: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006c72: f003 0304 and.w r3, r3, #4
|
|
8006c76: 2b00 cmp r3, #0
|
|
8006c78: d00a beq.n 8006c90 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8006c7a: 687b ldr r3, [r7, #4]
|
|
8006c7c: 681b ldr r3, [r3, #0]
|
|
8006c7e: 685b ldr r3, [r3, #4]
|
|
8006c80: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8006c84: 687b ldr r3, [r7, #4]
|
|
8006c86: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8006c88: 687b ldr r3, [r7, #4]
|
|
8006c8a: 681b ldr r3, [r3, #0]
|
|
8006c8c: 430a orrs r2, r1
|
|
8006c8e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8006c90: 687b ldr r3, [r7, #4]
|
|
8006c92: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006c94: f003 0310 and.w r3, r3, #16
|
|
8006c98: 2b00 cmp r3, #0
|
|
8006c9a: d00a beq.n 8006cb2 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8006c9c: 687b ldr r3, [r7, #4]
|
|
8006c9e: 681b ldr r3, [r3, #0]
|
|
8006ca0: 689b ldr r3, [r3, #8]
|
|
8006ca2: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8006ca6: 687b ldr r3, [r7, #4]
|
|
8006ca8: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8006caa: 687b ldr r3, [r7, #4]
|
|
8006cac: 681b ldr r3, [r3, #0]
|
|
8006cae: 430a orrs r2, r1
|
|
8006cb0: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8006cb2: 687b ldr r3, [r7, #4]
|
|
8006cb4: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006cb6: f003 0320 and.w r3, r3, #32
|
|
8006cba: 2b00 cmp r3, #0
|
|
8006cbc: d00a beq.n 8006cd4 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8006cbe: 687b ldr r3, [r7, #4]
|
|
8006cc0: 681b ldr r3, [r3, #0]
|
|
8006cc2: 689b ldr r3, [r3, #8]
|
|
8006cc4: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8006cc8: 687b ldr r3, [r7, #4]
|
|
8006cca: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8006ccc: 687b ldr r3, [r7, #4]
|
|
8006cce: 681b ldr r3, [r3, #0]
|
|
8006cd0: 430a orrs r2, r1
|
|
8006cd2: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8006cd4: 687b ldr r3, [r7, #4]
|
|
8006cd6: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006cd8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006cdc: 2b00 cmp r3, #0
|
|
8006cde: d01a beq.n 8006d16 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8006ce0: 687b ldr r3, [r7, #4]
|
|
8006ce2: 681b ldr r3, [r3, #0]
|
|
8006ce4: 685b ldr r3, [r3, #4]
|
|
8006ce6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
8006cea: 687b ldr r3, [r7, #4]
|
|
8006cec: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8006cee: 687b ldr r3, [r7, #4]
|
|
8006cf0: 681b ldr r3, [r3, #0]
|
|
8006cf2: 430a orrs r2, r1
|
|
8006cf4: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8006cf6: 687b ldr r3, [r7, #4]
|
|
8006cf8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8006cfa: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8006cfe: d10a bne.n 8006d16 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8006d00: 687b ldr r3, [r7, #4]
|
|
8006d02: 681b ldr r3, [r3, #0]
|
|
8006d04: 685b ldr r3, [r3, #4]
|
|
8006d06: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
8006d0a: 687b ldr r3, [r7, #4]
|
|
8006d0c: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8006d0e: 687b ldr r3, [r7, #4]
|
|
8006d10: 681b ldr r3, [r3, #0]
|
|
8006d12: 430a orrs r2, r1
|
|
8006d14: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8006d16: 687b ldr r3, [r7, #4]
|
|
8006d18: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8006d1a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8006d1e: 2b00 cmp r3, #0
|
|
8006d20: d00a beq.n 8006d38 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8006d22: 687b ldr r3, [r7, #4]
|
|
8006d24: 681b ldr r3, [r3, #0]
|
|
8006d26: 685b ldr r3, [r3, #4]
|
|
8006d28: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8006d2c: 687b ldr r3, [r7, #4]
|
|
8006d2e: 6cda ldr r2, [r3, #76] @ 0x4c
|
|
8006d30: 687b ldr r3, [r7, #4]
|
|
8006d32: 681b ldr r3, [r3, #0]
|
|
8006d34: 430a orrs r2, r1
|
|
8006d36: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8006d38: bf00 nop
|
|
8006d3a: 370c adds r7, #12
|
|
8006d3c: 46bd mov sp, r7
|
|
8006d3e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d42: 4770 bx lr
|
|
|
|
08006d44 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8006d44: b580 push {r7, lr}
|
|
8006d46: b098 sub sp, #96 @ 0x60
|
|
8006d48: af02 add r7, sp, #8
|
|
8006d4a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006d4c: 687b ldr r3, [r7, #4]
|
|
8006d4e: 2200 movs r2, #0
|
|
8006d50: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8006d54: f7fa fd10 bl 8001778 <HAL_GetTick>
|
|
8006d58: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8006d5a: 687b ldr r3, [r7, #4]
|
|
8006d5c: 681b ldr r3, [r3, #0]
|
|
8006d5e: 681b ldr r3, [r3, #0]
|
|
8006d60: f003 0308 and.w r3, r3, #8
|
|
8006d64: 2b08 cmp r3, #8
|
|
8006d66: d12f bne.n 8006dc8 <UART_CheckIdleState+0x84>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006d68: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006d6c: 9300 str r3, [sp, #0]
|
|
8006d6e: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006d70: 2200 movs r2, #0
|
|
8006d72: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8006d76: 6878 ldr r0, [r7, #4]
|
|
8006d78: f000 f88e bl 8006e98 <UART_WaitOnFlagUntilTimeout>
|
|
8006d7c: 4603 mov r3, r0
|
|
8006d7e: 2b00 cmp r3, #0
|
|
8006d80: d022 beq.n 8006dc8 <UART_CheckIdleState+0x84>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
8006d82: 687b ldr r3, [r7, #4]
|
|
8006d84: 681b ldr r3, [r3, #0]
|
|
8006d86: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006d88: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006d8a: e853 3f00 ldrex r3, [r3]
|
|
8006d8e: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8006d90: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006d92: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8006d96: 653b str r3, [r7, #80] @ 0x50
|
|
8006d98: 687b ldr r3, [r7, #4]
|
|
8006d9a: 681b ldr r3, [r3, #0]
|
|
8006d9c: 461a mov r2, r3
|
|
8006d9e: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8006da0: 647b str r3, [r7, #68] @ 0x44
|
|
8006da2: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006da4: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8006da6: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8006da8: e841 2300 strex r3, r2, [r1]
|
|
8006dac: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8006dae: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8006db0: 2b00 cmp r3, #0
|
|
8006db2: d1e6 bne.n 8006d82 <UART_CheckIdleState+0x3e>
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006db4: 687b ldr r3, [r7, #4]
|
|
8006db6: 2220 movs r2, #32
|
|
8006db8: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006dbc: 687b ldr r3, [r7, #4]
|
|
8006dbe: 2200 movs r2, #0
|
|
8006dc0: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006dc4: 2303 movs r3, #3
|
|
8006dc6: e063 b.n 8006e90 <UART_CheckIdleState+0x14c>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8006dc8: 687b ldr r3, [r7, #4]
|
|
8006dca: 681b ldr r3, [r3, #0]
|
|
8006dcc: 681b ldr r3, [r3, #0]
|
|
8006dce: f003 0304 and.w r3, r3, #4
|
|
8006dd2: 2b04 cmp r3, #4
|
|
8006dd4: d149 bne.n 8006e6a <UART_CheckIdleState+0x126>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8006dd6: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8006dda: 9300 str r3, [sp, #0]
|
|
8006ddc: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8006dde: 2200 movs r2, #0
|
|
8006de0: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
8006de4: 6878 ldr r0, [r7, #4]
|
|
8006de6: f000 f857 bl 8006e98 <UART_WaitOnFlagUntilTimeout>
|
|
8006dea: 4603 mov r3, r0
|
|
8006dec: 2b00 cmp r3, #0
|
|
8006dee: d03c beq.n 8006e6a <UART_CheckIdleState+0x126>
|
|
{
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8006df0: 687b ldr r3, [r7, #4]
|
|
8006df2: 681b ldr r3, [r3, #0]
|
|
8006df4: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006df6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006df8: e853 3f00 ldrex r3, [r3]
|
|
8006dfc: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006dfe: 6a3b ldr r3, [r7, #32]
|
|
8006e00: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006e04: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006e06: 687b ldr r3, [r7, #4]
|
|
8006e08: 681b ldr r3, [r3, #0]
|
|
8006e0a: 461a mov r2, r3
|
|
8006e0c: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006e0e: 633b str r3, [r7, #48] @ 0x30
|
|
8006e10: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006e12: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8006e14: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006e16: e841 2300 strex r3, r2, [r1]
|
|
8006e1a: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006e1c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006e1e: 2b00 cmp r3, #0
|
|
8006e20: d1e6 bne.n 8006df0 <UART_CheckIdleState+0xac>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006e22: 687b ldr r3, [r7, #4]
|
|
8006e24: 681b ldr r3, [r3, #0]
|
|
8006e26: 3308 adds r3, #8
|
|
8006e28: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006e2a: 693b ldr r3, [r7, #16]
|
|
8006e2c: e853 3f00 ldrex r3, [r3]
|
|
8006e30: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006e32: 68fb ldr r3, [r7, #12]
|
|
8006e34: f023 0301 bic.w r3, r3, #1
|
|
8006e38: 64bb str r3, [r7, #72] @ 0x48
|
|
8006e3a: 687b ldr r3, [r7, #4]
|
|
8006e3c: 681b ldr r3, [r3, #0]
|
|
8006e3e: 3308 adds r3, #8
|
|
8006e40: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006e42: 61fa str r2, [r7, #28]
|
|
8006e44: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006e46: 69b9 ldr r1, [r7, #24]
|
|
8006e48: 69fa ldr r2, [r7, #28]
|
|
8006e4a: e841 2300 strex r3, r2, [r1]
|
|
8006e4e: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006e50: 697b ldr r3, [r7, #20]
|
|
8006e52: 2b00 cmp r3, #0
|
|
8006e54: d1e5 bne.n 8006e22 <UART_CheckIdleState+0xde>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006e56: 687b ldr r3, [r7, #4]
|
|
8006e58: 2220 movs r2, #32
|
|
8006e5a: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006e5e: 687b ldr r3, [r7, #4]
|
|
8006e60: 2200 movs r2, #0
|
|
8006e62: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8006e66: 2303 movs r3, #3
|
|
8006e68: e012 b.n 8006e90 <UART_CheckIdleState+0x14c>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006e6a: 687b ldr r3, [r7, #4]
|
|
8006e6c: 2220 movs r2, #32
|
|
8006e6e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006e72: 687b ldr r3, [r7, #4]
|
|
8006e74: 2220 movs r2, #32
|
|
8006e76: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006e7a: 687b ldr r3, [r7, #4]
|
|
8006e7c: 2200 movs r2, #0
|
|
8006e7e: 66da str r2, [r3, #108] @ 0x6c
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8006e80: 687b ldr r3, [r7, #4]
|
|
8006e82: 2200 movs r2, #0
|
|
8006e84: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8006e86: 687b ldr r3, [r7, #4]
|
|
8006e88: 2200 movs r2, #0
|
|
8006e8a: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
8006e8e: 2300 movs r3, #0
|
|
}
|
|
8006e90: 4618 mov r0, r3
|
|
8006e92: 3758 adds r7, #88 @ 0x58
|
|
8006e94: 46bd mov sp, r7
|
|
8006e96: bd80 pop {r7, pc}
|
|
|
|
08006e98 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8006e98: b580 push {r7, lr}
|
|
8006e9a: b084 sub sp, #16
|
|
8006e9c: af00 add r7, sp, #0
|
|
8006e9e: 60f8 str r0, [r7, #12]
|
|
8006ea0: 60b9 str r1, [r7, #8]
|
|
8006ea2: 603b str r3, [r7, #0]
|
|
8006ea4: 4613 mov r3, r2
|
|
8006ea6: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8006ea8: e04f b.n 8006f4a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8006eaa: 69bb ldr r3, [r7, #24]
|
|
8006eac: f1b3 3fff cmp.w r3, #4294967295
|
|
8006eb0: d04b beq.n 8006f4a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8006eb2: f7fa fc61 bl 8001778 <HAL_GetTick>
|
|
8006eb6: 4602 mov r2, r0
|
|
8006eb8: 683b ldr r3, [r7, #0]
|
|
8006eba: 1ad3 subs r3, r2, r3
|
|
8006ebc: 69ba ldr r2, [r7, #24]
|
|
8006ebe: 429a cmp r2, r3
|
|
8006ec0: d302 bcc.n 8006ec8 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8006ec2: 69bb ldr r3, [r7, #24]
|
|
8006ec4: 2b00 cmp r3, #0
|
|
8006ec6: d101 bne.n 8006ecc <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
8006ec8: 2303 movs r3, #3
|
|
8006eca: e04e b.n 8006f6a <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
8006ecc: 68fb ldr r3, [r7, #12]
|
|
8006ece: 681b ldr r3, [r3, #0]
|
|
8006ed0: 681b ldr r3, [r3, #0]
|
|
8006ed2: f003 0304 and.w r3, r3, #4
|
|
8006ed6: 2b00 cmp r3, #0
|
|
8006ed8: d037 beq.n 8006f4a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8006eda: 68bb ldr r3, [r7, #8]
|
|
8006edc: 2b80 cmp r3, #128 @ 0x80
|
|
8006ede: d034 beq.n 8006f4a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8006ee0: 68bb ldr r3, [r7, #8]
|
|
8006ee2: 2b40 cmp r3, #64 @ 0x40
|
|
8006ee4: d031 beq.n 8006f4a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8006ee6: 68fb ldr r3, [r7, #12]
|
|
8006ee8: 681b ldr r3, [r3, #0]
|
|
8006eea: 69db ldr r3, [r3, #28]
|
|
8006eec: f003 0308 and.w r3, r3, #8
|
|
8006ef0: 2b08 cmp r3, #8
|
|
8006ef2: d110 bne.n 8006f16 <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8006ef4: 68fb ldr r3, [r7, #12]
|
|
8006ef6: 681b ldr r3, [r3, #0]
|
|
8006ef8: 2208 movs r2, #8
|
|
8006efa: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8006efc: 68f8 ldr r0, [r7, #12]
|
|
8006efe: f000 f95b bl 80071b8 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
8006f02: 68fb ldr r3, [r7, #12]
|
|
8006f04: 2208 movs r2, #8
|
|
8006f06: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006f0a: 68fb ldr r3, [r7, #12]
|
|
8006f0c: 2200 movs r2, #0
|
|
8006f0e: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_ERROR;
|
|
8006f12: 2301 movs r3, #1
|
|
8006f14: e029 b.n 8006f6a <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8006f16: 68fb ldr r3, [r7, #12]
|
|
8006f18: 681b ldr r3, [r3, #0]
|
|
8006f1a: 69db ldr r3, [r3, #28]
|
|
8006f1c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8006f20: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8006f24: d111 bne.n 8006f4a <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8006f26: 68fb ldr r3, [r7, #12]
|
|
8006f28: 681b ldr r3, [r3, #0]
|
|
8006f2a: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8006f2e: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8006f30: 68f8 ldr r0, [r7, #12]
|
|
8006f32: f000 f941 bl 80071b8 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
8006f36: 68fb ldr r3, [r7, #12]
|
|
8006f38: 2220 movs r2, #32
|
|
8006f3a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8006f3e: 68fb ldr r3, [r7, #12]
|
|
8006f40: 2200 movs r2, #0
|
|
8006f42: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_TIMEOUT;
|
|
8006f46: 2303 movs r3, #3
|
|
8006f48: e00f b.n 8006f6a <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8006f4a: 68fb ldr r3, [r7, #12]
|
|
8006f4c: 681b ldr r3, [r3, #0]
|
|
8006f4e: 69da ldr r2, [r3, #28]
|
|
8006f50: 68bb ldr r3, [r7, #8]
|
|
8006f52: 4013 ands r3, r2
|
|
8006f54: 68ba ldr r2, [r7, #8]
|
|
8006f56: 429a cmp r2, r3
|
|
8006f58: bf0c ite eq
|
|
8006f5a: 2301 moveq r3, #1
|
|
8006f5c: 2300 movne r3, #0
|
|
8006f5e: b2db uxtb r3, r3
|
|
8006f60: 461a mov r2, r3
|
|
8006f62: 79fb ldrb r3, [r7, #7]
|
|
8006f64: 429a cmp r2, r3
|
|
8006f66: d0a0 beq.n 8006eaa <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8006f68: 2300 movs r3, #0
|
|
}
|
|
8006f6a: 4618 mov r0, r3
|
|
8006f6c: 3710 adds r7, #16
|
|
8006f6e: 46bd mov sp, r7
|
|
8006f70: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08006f74 <UART_Start_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8006f74: b480 push {r7}
|
|
8006f76: b0a3 sub sp, #140 @ 0x8c
|
|
8006f78: af00 add r7, sp, #0
|
|
8006f7a: 60f8 str r0, [r7, #12]
|
|
8006f7c: 60b9 str r1, [r7, #8]
|
|
8006f7e: 4613 mov r3, r2
|
|
8006f80: 80fb strh r3, [r7, #6]
|
|
huart->pRxBuffPtr = pData;
|
|
8006f82: 68fb ldr r3, [r7, #12]
|
|
8006f84: 68ba ldr r2, [r7, #8]
|
|
8006f86: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferSize = Size;
|
|
8006f88: 68fb ldr r3, [r7, #12]
|
|
8006f8a: 88fa ldrh r2, [r7, #6]
|
|
8006f8c: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
huart->RxXferCount = Size;
|
|
8006f90: 68fb ldr r3, [r7, #12]
|
|
8006f92: 88fa ldrh r2, [r7, #6]
|
|
8006f94: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
huart->RxISR = NULL;
|
|
8006f98: 68fb ldr r3, [r7, #12]
|
|
8006f9a: 2200 movs r2, #0
|
|
8006f9c: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
UART_MASK_COMPUTATION(huart);
|
|
8006f9e: 68fb ldr r3, [r7, #12]
|
|
8006fa0: 689b ldr r3, [r3, #8]
|
|
8006fa2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8006fa6: d10e bne.n 8006fc6 <UART_Start_Receive_IT+0x52>
|
|
8006fa8: 68fb ldr r3, [r7, #12]
|
|
8006faa: 691b ldr r3, [r3, #16]
|
|
8006fac: 2b00 cmp r3, #0
|
|
8006fae: d105 bne.n 8006fbc <UART_Start_Receive_IT+0x48>
|
|
8006fb0: 68fb ldr r3, [r7, #12]
|
|
8006fb2: f240 12ff movw r2, #511 @ 0x1ff
|
|
8006fb6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006fba: e02d b.n 8007018 <UART_Start_Receive_IT+0xa4>
|
|
8006fbc: 68fb ldr r3, [r7, #12]
|
|
8006fbe: 22ff movs r2, #255 @ 0xff
|
|
8006fc0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006fc4: e028 b.n 8007018 <UART_Start_Receive_IT+0xa4>
|
|
8006fc6: 68fb ldr r3, [r7, #12]
|
|
8006fc8: 689b ldr r3, [r3, #8]
|
|
8006fca: 2b00 cmp r3, #0
|
|
8006fcc: d10d bne.n 8006fea <UART_Start_Receive_IT+0x76>
|
|
8006fce: 68fb ldr r3, [r7, #12]
|
|
8006fd0: 691b ldr r3, [r3, #16]
|
|
8006fd2: 2b00 cmp r3, #0
|
|
8006fd4: d104 bne.n 8006fe0 <UART_Start_Receive_IT+0x6c>
|
|
8006fd6: 68fb ldr r3, [r7, #12]
|
|
8006fd8: 22ff movs r2, #255 @ 0xff
|
|
8006fda: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006fde: e01b b.n 8007018 <UART_Start_Receive_IT+0xa4>
|
|
8006fe0: 68fb ldr r3, [r7, #12]
|
|
8006fe2: 227f movs r2, #127 @ 0x7f
|
|
8006fe4: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8006fe8: e016 b.n 8007018 <UART_Start_Receive_IT+0xa4>
|
|
8006fea: 68fb ldr r3, [r7, #12]
|
|
8006fec: 689b ldr r3, [r3, #8]
|
|
8006fee: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8006ff2: d10d bne.n 8007010 <UART_Start_Receive_IT+0x9c>
|
|
8006ff4: 68fb ldr r3, [r7, #12]
|
|
8006ff6: 691b ldr r3, [r3, #16]
|
|
8006ff8: 2b00 cmp r3, #0
|
|
8006ffa: d104 bne.n 8007006 <UART_Start_Receive_IT+0x92>
|
|
8006ffc: 68fb ldr r3, [r7, #12]
|
|
8006ffe: 227f movs r2, #127 @ 0x7f
|
|
8007000: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
8007004: e008 b.n 8007018 <UART_Start_Receive_IT+0xa4>
|
|
8007006: 68fb ldr r3, [r7, #12]
|
|
8007008: 223f movs r2, #63 @ 0x3f
|
|
800700a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
800700e: e003 b.n 8007018 <UART_Start_Receive_IT+0xa4>
|
|
8007010: 68fb ldr r3, [r7, #12]
|
|
8007012: 2200 movs r2, #0
|
|
8007014: f8a3 2060 strh.w r2, [r3, #96] @ 0x60
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8007018: 68fb ldr r3, [r7, #12]
|
|
800701a: 2200 movs r2, #0
|
|
800701c: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8007020: 68fb ldr r3, [r7, #12]
|
|
8007022: 2222 movs r2, #34 @ 0x22
|
|
8007024: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8007028: 68fb ldr r3, [r7, #12]
|
|
800702a: 681b ldr r3, [r3, #0]
|
|
800702c: 3308 adds r3, #8
|
|
800702e: 667b str r3, [r7, #100] @ 0x64
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007030: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8007032: e853 3f00 ldrex r3, [r3]
|
|
8007036: 663b str r3, [r7, #96] @ 0x60
|
|
return(result);
|
|
8007038: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800703a: f043 0301 orr.w r3, r3, #1
|
|
800703e: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8007042: 68fb ldr r3, [r7, #12]
|
|
8007044: 681b ldr r3, [r3, #0]
|
|
8007046: 3308 adds r3, #8
|
|
8007048: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
|
|
800704c: 673a str r2, [r7, #112] @ 0x70
|
|
800704e: 66fb str r3, [r7, #108] @ 0x6c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007050: 6ef9 ldr r1, [r7, #108] @ 0x6c
|
|
8007052: 6f3a ldr r2, [r7, #112] @ 0x70
|
|
8007054: e841 2300 strex r3, r2, [r1]
|
|
8007058: 66bb str r3, [r7, #104] @ 0x68
|
|
return(result);
|
|
800705a: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
800705c: 2b00 cmp r3, #0
|
|
800705e: d1e3 bne.n 8007028 <UART_Start_Receive_IT+0xb4>
|
|
|
|
/* Configure Rx interrupt processing */
|
|
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
|
|
8007060: 68fb ldr r3, [r7, #12]
|
|
8007062: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8007064: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8007068: d14f bne.n 800710a <UART_Start_Receive_IT+0x196>
|
|
800706a: 68fb ldr r3, [r7, #12]
|
|
800706c: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8007070: 88fa ldrh r2, [r7, #6]
|
|
8007072: 429a cmp r2, r3
|
|
8007074: d349 bcc.n 800710a <UART_Start_Receive_IT+0x196>
|
|
{
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8007076: 68fb ldr r3, [r7, #12]
|
|
8007078: 689b ldr r3, [r3, #8]
|
|
800707a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800707e: d107 bne.n 8007090 <UART_Start_Receive_IT+0x11c>
|
|
8007080: 68fb ldr r3, [r7, #12]
|
|
8007082: 691b ldr r3, [r3, #16]
|
|
8007084: 2b00 cmp r3, #0
|
|
8007086: d103 bne.n 8007090 <UART_Start_Receive_IT+0x11c>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
|
|
8007088: 68fb ldr r3, [r7, #12]
|
|
800708a: 4a47 ldr r2, [pc, #284] @ (80071a8 <UART_Start_Receive_IT+0x234>)
|
|
800708c: 675a str r2, [r3, #116] @ 0x74
|
|
800708e: e002 b.n 8007096 <UART_Start_Receive_IT+0x122>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
|
|
8007090: 68fb ldr r3, [r7, #12]
|
|
8007092: 4a46 ldr r2, [pc, #280] @ (80071ac <UART_Start_Receive_IT+0x238>)
|
|
8007094: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
8007096: 68fb ldr r3, [r7, #12]
|
|
8007098: 691b ldr r3, [r3, #16]
|
|
800709a: 2b00 cmp r3, #0
|
|
800709c: d01a beq.n 80070d4 <UART_Start_Receive_IT+0x160>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
800709e: 68fb ldr r3, [r7, #12]
|
|
80070a0: 681b ldr r3, [r3, #0]
|
|
80070a2: 653b str r3, [r7, #80] @ 0x50
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80070a4: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80070a6: e853 3f00 ldrex r3, [r3]
|
|
80070aa: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
80070ac: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80070ae: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80070b2: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
80070b6: 68fb ldr r3, [r7, #12]
|
|
80070b8: 681b ldr r3, [r3, #0]
|
|
80070ba: 461a mov r2, r3
|
|
80070bc: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
80070c0: 65fb str r3, [r7, #92] @ 0x5c
|
|
80070c2: 65ba str r2, [r7, #88] @ 0x58
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80070c4: 6db9 ldr r1, [r7, #88] @ 0x58
|
|
80070c6: 6dfa ldr r2, [r7, #92] @ 0x5c
|
|
80070c8: e841 2300 strex r3, r2, [r1]
|
|
80070cc: 657b str r3, [r7, #84] @ 0x54
|
|
return(result);
|
|
80070ce: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
80070d0: 2b00 cmp r3, #0
|
|
80070d2: d1e4 bne.n 800709e <UART_Start_Receive_IT+0x12a>
|
|
}
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
80070d4: 68fb ldr r3, [r7, #12]
|
|
80070d6: 681b ldr r3, [r3, #0]
|
|
80070d8: 3308 adds r3, #8
|
|
80070da: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80070dc: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80070de: e853 3f00 ldrex r3, [r3]
|
|
80070e2: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
80070e4: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80070e6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80070ea: 67fb str r3, [r7, #124] @ 0x7c
|
|
80070ec: 68fb ldr r3, [r7, #12]
|
|
80070ee: 681b ldr r3, [r3, #0]
|
|
80070f0: 3308 adds r3, #8
|
|
80070f2: 6ffa ldr r2, [r7, #124] @ 0x7c
|
|
80070f4: 64ba str r2, [r7, #72] @ 0x48
|
|
80070f6: 647b str r3, [r7, #68] @ 0x44
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80070f8: 6c79 ldr r1, [r7, #68] @ 0x44
|
|
80070fa: 6cba ldr r2, [r7, #72] @ 0x48
|
|
80070fc: e841 2300 strex r3, r2, [r1]
|
|
8007100: 643b str r3, [r7, #64] @ 0x40
|
|
return(result);
|
|
8007102: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8007104: 2b00 cmp r3, #0
|
|
8007106: d1e5 bne.n 80070d4 <UART_Start_Receive_IT+0x160>
|
|
8007108: e046 b.n 8007198 <UART_Start_Receive_IT+0x224>
|
|
}
|
|
else
|
|
{
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
800710a: 68fb ldr r3, [r7, #12]
|
|
800710c: 689b ldr r3, [r3, #8]
|
|
800710e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8007112: d107 bne.n 8007124 <UART_Start_Receive_IT+0x1b0>
|
|
8007114: 68fb ldr r3, [r7, #12]
|
|
8007116: 691b ldr r3, [r3, #16]
|
|
8007118: 2b00 cmp r3, #0
|
|
800711a: d103 bne.n 8007124 <UART_Start_Receive_IT+0x1b0>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
800711c: 68fb ldr r3, [r7, #12]
|
|
800711e: 4a24 ldr r2, [pc, #144] @ (80071b0 <UART_Start_Receive_IT+0x23c>)
|
|
8007120: 675a str r2, [r3, #116] @ 0x74
|
|
8007122: e002 b.n 800712a <UART_Start_Receive_IT+0x1b6>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
8007124: 68fb ldr r3, [r7, #12]
|
|
8007126: 4a23 ldr r2, [pc, #140] @ (80071b4 <UART_Start_Receive_IT+0x240>)
|
|
8007128: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
800712a: 68fb ldr r3, [r7, #12]
|
|
800712c: 691b ldr r3, [r3, #16]
|
|
800712e: 2b00 cmp r3, #0
|
|
8007130: d019 beq.n 8007166 <UART_Start_Receive_IT+0x1f2>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
|
|
8007132: 68fb ldr r3, [r7, #12]
|
|
8007134: 681b ldr r3, [r3, #0]
|
|
8007136: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007138: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800713a: e853 3f00 ldrex r3, [r3]
|
|
800713e: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8007140: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007142: f443 7390 orr.w r3, r3, #288 @ 0x120
|
|
8007146: 677b str r3, [r7, #116] @ 0x74
|
|
8007148: 68fb ldr r3, [r7, #12]
|
|
800714a: 681b ldr r3, [r3, #0]
|
|
800714c: 461a mov r2, r3
|
|
800714e: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8007150: 637b str r3, [r7, #52] @ 0x34
|
|
8007152: 633a str r2, [r7, #48] @ 0x30
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007154: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
8007156: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8007158: e841 2300 strex r3, r2, [r1]
|
|
800715c: 62fb str r3, [r7, #44] @ 0x2c
|
|
return(result);
|
|
800715e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8007160: 2b00 cmp r3, #0
|
|
8007162: d1e6 bne.n 8007132 <UART_Start_Receive_IT+0x1be>
|
|
8007164: e018 b.n 8007198 <UART_Start_Receive_IT+0x224>
|
|
}
|
|
else
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
8007166: 68fb ldr r3, [r7, #12]
|
|
8007168: 681b ldr r3, [r3, #0]
|
|
800716a: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800716c: 697b ldr r3, [r7, #20]
|
|
800716e: e853 3f00 ldrex r3, [r3]
|
|
8007172: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8007174: 693b ldr r3, [r7, #16]
|
|
8007176: f043 0320 orr.w r3, r3, #32
|
|
800717a: 67bb str r3, [r7, #120] @ 0x78
|
|
800717c: 68fb ldr r3, [r7, #12]
|
|
800717e: 681b ldr r3, [r3, #0]
|
|
8007180: 461a mov r2, r3
|
|
8007182: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8007184: 623b str r3, [r7, #32]
|
|
8007186: 61fa str r2, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007188: 69f9 ldr r1, [r7, #28]
|
|
800718a: 6a3a ldr r2, [r7, #32]
|
|
800718c: e841 2300 strex r3, r2, [r1]
|
|
8007190: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
8007192: 69bb ldr r3, [r7, #24]
|
|
8007194: 2b00 cmp r3, #0
|
|
8007196: d1e6 bne.n 8007166 <UART_Start_Receive_IT+0x1f2>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8007198: 2300 movs r3, #0
|
|
}
|
|
800719a: 4618 mov r0, r3
|
|
800719c: 378c adds r7, #140 @ 0x8c
|
|
800719e: 46bd mov sp, r7
|
|
80071a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80071a4: 4770 bx lr
|
|
80071a6: bf00 nop
|
|
80071a8: 080079d5 .word 0x080079d5
|
|
80071ac: 08007671 .word 0x08007671
|
|
80071b0: 080074b9 .word 0x080074b9
|
|
80071b4: 08007301 .word 0x08007301
|
|
|
|
080071b8 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80071b8: b480 push {r7}
|
|
80071ba: b095 sub sp, #84 @ 0x54
|
|
80071bc: af00 add r7, sp, #0
|
|
80071be: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
80071c0: 687b ldr r3, [r7, #4]
|
|
80071c2: 681b ldr r3, [r3, #0]
|
|
80071c4: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80071c6: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80071c8: e853 3f00 ldrex r3, [r3]
|
|
80071cc: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
80071ce: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80071d0: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80071d4: 64fb str r3, [r7, #76] @ 0x4c
|
|
80071d6: 687b ldr r3, [r7, #4]
|
|
80071d8: 681b ldr r3, [r3, #0]
|
|
80071da: 461a mov r2, r3
|
|
80071dc: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80071de: 643b str r3, [r7, #64] @ 0x40
|
|
80071e0: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80071e2: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80071e4: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80071e6: e841 2300 strex r3, r2, [r1]
|
|
80071ea: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
80071ec: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80071ee: 2b00 cmp r3, #0
|
|
80071f0: d1e6 bne.n 80071c0 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
80071f2: 687b ldr r3, [r7, #4]
|
|
80071f4: 681b ldr r3, [r3, #0]
|
|
80071f6: 3308 adds r3, #8
|
|
80071f8: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80071fa: 6a3b ldr r3, [r7, #32]
|
|
80071fc: e853 3f00 ldrex r3, [r3]
|
|
8007200: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8007202: 69fb ldr r3, [r7, #28]
|
|
8007204: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8007208: f023 0301 bic.w r3, r3, #1
|
|
800720c: 64bb str r3, [r7, #72] @ 0x48
|
|
800720e: 687b ldr r3, [r7, #4]
|
|
8007210: 681b ldr r3, [r3, #0]
|
|
8007212: 3308 adds r3, #8
|
|
8007214: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8007216: 62fa str r2, [r7, #44] @ 0x2c
|
|
8007218: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800721a: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800721c: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800721e: e841 2300 strex r3, r2, [r1]
|
|
8007222: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8007224: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007226: 2b00 cmp r3, #0
|
|
8007228: d1e3 bne.n 80071f2 <UART_EndRxTransfer+0x3a>
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800722a: 687b ldr r3, [r7, #4]
|
|
800722c: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
800722e: 2b01 cmp r3, #1
|
|
8007230: d118 bne.n 8007264 <UART_EndRxTransfer+0xac>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8007232: 687b ldr r3, [r7, #4]
|
|
8007234: 681b ldr r3, [r3, #0]
|
|
8007236: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007238: 68fb ldr r3, [r7, #12]
|
|
800723a: e853 3f00 ldrex r3, [r3]
|
|
800723e: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8007240: 68bb ldr r3, [r7, #8]
|
|
8007242: f023 0310 bic.w r3, r3, #16
|
|
8007246: 647b str r3, [r7, #68] @ 0x44
|
|
8007248: 687b ldr r3, [r7, #4]
|
|
800724a: 681b ldr r3, [r3, #0]
|
|
800724c: 461a mov r2, r3
|
|
800724e: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8007250: 61bb str r3, [r7, #24]
|
|
8007252: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007254: 6979 ldr r1, [r7, #20]
|
|
8007256: 69ba ldr r2, [r7, #24]
|
|
8007258: e841 2300 strex r3, r2, [r1]
|
|
800725c: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800725e: 693b ldr r3, [r7, #16]
|
|
8007260: 2b00 cmp r3, #0
|
|
8007262: d1e6 bne.n 8007232 <UART_EndRxTransfer+0x7a>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8007264: 687b ldr r3, [r7, #4]
|
|
8007266: 2220 movs r2, #32
|
|
8007268: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800726c: 687b ldr r3, [r7, #4]
|
|
800726e: 2200 movs r2, #0
|
|
8007270: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8007272: 687b ldr r3, [r7, #4]
|
|
8007274: 2200 movs r2, #0
|
|
8007276: 675a str r2, [r3, #116] @ 0x74
|
|
}
|
|
8007278: bf00 nop
|
|
800727a: 3754 adds r7, #84 @ 0x54
|
|
800727c: 46bd mov sp, r7
|
|
800727e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007282: 4770 bx lr
|
|
|
|
08007284 <UART_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8007284: b580 push {r7, lr}
|
|
8007286: b084 sub sp, #16
|
|
8007288: af00 add r7, sp, #0
|
|
800728a: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
800728c: 687b ldr r3, [r7, #4]
|
|
800728e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8007290: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0U;
|
|
8007292: 68fb ldr r3, [r7, #12]
|
|
8007294: 2200 movs r2, #0
|
|
8007296: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800729a: 68f8 ldr r0, [r7, #12]
|
|
800729c: f7ff f9ce bl 800663c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
80072a0: bf00 nop
|
|
80072a2: 3710 adds r7, #16
|
|
80072a4: 46bd mov sp, r7
|
|
80072a6: bd80 pop {r7, pc}
|
|
|
|
080072a8 <UART_EndTransmit_IT>:
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
80072a8: b580 push {r7, lr}
|
|
80072aa: b088 sub sp, #32
|
|
80072ac: af00 add r7, sp, #0
|
|
80072ae: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
80072b0: 687b ldr r3, [r7, #4]
|
|
80072b2: 681b ldr r3, [r3, #0]
|
|
80072b4: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80072b6: 68fb ldr r3, [r7, #12]
|
|
80072b8: e853 3f00 ldrex r3, [r3]
|
|
80072bc: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80072be: 68bb ldr r3, [r7, #8]
|
|
80072c0: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80072c4: 61fb str r3, [r7, #28]
|
|
80072c6: 687b ldr r3, [r7, #4]
|
|
80072c8: 681b ldr r3, [r3, #0]
|
|
80072ca: 461a mov r2, r3
|
|
80072cc: 69fb ldr r3, [r7, #28]
|
|
80072ce: 61bb str r3, [r7, #24]
|
|
80072d0: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80072d2: 6979 ldr r1, [r7, #20]
|
|
80072d4: 69ba ldr r2, [r7, #24]
|
|
80072d6: e841 2300 strex r3, r2, [r1]
|
|
80072da: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80072dc: 693b ldr r3, [r7, #16]
|
|
80072de: 2b00 cmp r3, #0
|
|
80072e0: d1e6 bne.n 80072b0 <UART_EndTransmit_IT+0x8>
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80072e2: 687b ldr r3, [r7, #4]
|
|
80072e4: 2220 movs r2, #32
|
|
80072e6: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
80072ea: 687b ldr r3, [r7, #4]
|
|
80072ec: 2200 movs r2, #0
|
|
80072ee: 679a str r2, [r3, #120] @ 0x78
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
80072f0: 6878 ldr r0, [r7, #4]
|
|
80072f2: f7f9 feab bl 800104c <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
80072f6: bf00 nop
|
|
80072f8: 3720 adds r7, #32
|
|
80072fa: 46bd mov sp, r7
|
|
80072fc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007300 <UART_RxISR_8BIT>:
|
|
* @brief RX interrupt handler for 7 or 8 bits data word length .
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8007300: b580 push {r7, lr}
|
|
8007302: b09c sub sp, #112 @ 0x70
|
|
8007304: af00 add r7, sp, #0
|
|
8007306: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
8007308: 687b ldr r3, [r7, #4]
|
|
800730a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
800730e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8007312: 687b ldr r3, [r7, #4]
|
|
8007314: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8007318: 2b22 cmp r3, #34 @ 0x22
|
|
800731a: f040 80be bne.w 800749a <UART_RxISR_8BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
800731e: 687b ldr r3, [r7, #4]
|
|
8007320: 681b ldr r3, [r3, #0]
|
|
8007322: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007324: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
8007328: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
800732c: b2d9 uxtb r1, r3
|
|
800732e: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
8007332: b2da uxtb r2, r3
|
|
8007334: 687b ldr r3, [r7, #4]
|
|
8007336: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007338: 400a ands r2, r1
|
|
800733a: b2d2 uxtb r2, r2
|
|
800733c: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
800733e: 687b ldr r3, [r7, #4]
|
|
8007340: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007342: 1c5a adds r2, r3, #1
|
|
8007344: 687b ldr r3, [r7, #4]
|
|
8007346: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8007348: 687b ldr r3, [r7, #4]
|
|
800734a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
800734e: b29b uxth r3, r3
|
|
8007350: 3b01 subs r3, #1
|
|
8007352: b29a uxth r2, r3
|
|
8007354: 687b ldr r3, [r7, #4]
|
|
8007356: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
800735a: 687b ldr r3, [r7, #4]
|
|
800735c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007360: b29b uxth r3, r3
|
|
8007362: 2b00 cmp r3, #0
|
|
8007364: f040 80a1 bne.w 80074aa <UART_RxISR_8BIT+0x1aa>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8007368: 687b ldr r3, [r7, #4]
|
|
800736a: 681b ldr r3, [r3, #0]
|
|
800736c: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800736e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8007370: e853 3f00 ldrex r3, [r3]
|
|
8007374: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8007376: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8007378: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
800737c: 66bb str r3, [r7, #104] @ 0x68
|
|
800737e: 687b ldr r3, [r7, #4]
|
|
8007380: 681b ldr r3, [r3, #0]
|
|
8007382: 461a mov r2, r3
|
|
8007384: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8007386: 65bb str r3, [r7, #88] @ 0x58
|
|
8007388: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800738a: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
800738c: 6dba ldr r2, [r7, #88] @ 0x58
|
|
800738e: e841 2300 strex r3, r2, [r1]
|
|
8007392: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8007394: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8007396: 2b00 cmp r3, #0
|
|
8007398: d1e6 bne.n 8007368 <UART_RxISR_8BIT+0x68>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800739a: 687b ldr r3, [r7, #4]
|
|
800739c: 681b ldr r3, [r3, #0]
|
|
800739e: 3308 adds r3, #8
|
|
80073a0: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80073a2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80073a4: e853 3f00 ldrex r3, [r3]
|
|
80073a8: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
80073aa: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80073ac: f023 0301 bic.w r3, r3, #1
|
|
80073b0: 667b str r3, [r7, #100] @ 0x64
|
|
80073b2: 687b ldr r3, [r7, #4]
|
|
80073b4: 681b ldr r3, [r3, #0]
|
|
80073b6: 3308 adds r3, #8
|
|
80073b8: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
80073ba: 647a str r2, [r7, #68] @ 0x44
|
|
80073bc: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80073be: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80073c0: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80073c2: e841 2300 strex r3, r2, [r1]
|
|
80073c6: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80073c8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80073ca: 2b00 cmp r3, #0
|
|
80073cc: d1e5 bne.n 800739a <UART_RxISR_8BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80073ce: 687b ldr r3, [r7, #4]
|
|
80073d0: 2220 movs r2, #32
|
|
80073d2: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
80073d6: 687b ldr r3, [r7, #4]
|
|
80073d8: 2200 movs r2, #0
|
|
80073da: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
80073dc: 687b ldr r3, [r7, #4]
|
|
80073de: 2200 movs r2, #0
|
|
80073e0: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
80073e2: 687b ldr r3, [r7, #4]
|
|
80073e4: 681b ldr r3, [r3, #0]
|
|
80073e6: 4a33 ldr r2, [pc, #204] @ (80074b4 <UART_RxISR_8BIT+0x1b4>)
|
|
80073e8: 4293 cmp r3, r2
|
|
80073ea: d01f beq.n 800742c <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
80073ec: 687b ldr r3, [r7, #4]
|
|
80073ee: 681b ldr r3, [r3, #0]
|
|
80073f0: 685b ldr r3, [r3, #4]
|
|
80073f2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80073f6: 2b00 cmp r3, #0
|
|
80073f8: d018 beq.n 800742c <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
80073fa: 687b ldr r3, [r7, #4]
|
|
80073fc: 681b ldr r3, [r3, #0]
|
|
80073fe: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007400: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007402: e853 3f00 ldrex r3, [r3]
|
|
8007406: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8007408: 6a3b ldr r3, [r7, #32]
|
|
800740a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
800740e: 663b str r3, [r7, #96] @ 0x60
|
|
8007410: 687b ldr r3, [r7, #4]
|
|
8007412: 681b ldr r3, [r3, #0]
|
|
8007414: 461a mov r2, r3
|
|
8007416: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8007418: 633b str r3, [r7, #48] @ 0x30
|
|
800741a: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800741c: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800741e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8007420: e841 2300 strex r3, r2, [r1]
|
|
8007424: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8007426: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8007428: 2b00 cmp r3, #0
|
|
800742a: d1e6 bne.n 80073fa <UART_RxISR_8BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800742c: 687b ldr r3, [r7, #4]
|
|
800742e: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8007430: 2b01 cmp r3, #1
|
|
8007432: d12e bne.n 8007492 <UART_RxISR_8BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8007434: 687b ldr r3, [r7, #4]
|
|
8007436: 2200 movs r2, #0
|
|
8007438: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800743a: 687b ldr r3, [r7, #4]
|
|
800743c: 681b ldr r3, [r3, #0]
|
|
800743e: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007440: 693b ldr r3, [r7, #16]
|
|
8007442: e853 3f00 ldrex r3, [r3]
|
|
8007446: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8007448: 68fb ldr r3, [r7, #12]
|
|
800744a: f023 0310 bic.w r3, r3, #16
|
|
800744e: 65fb str r3, [r7, #92] @ 0x5c
|
|
8007450: 687b ldr r3, [r7, #4]
|
|
8007452: 681b ldr r3, [r3, #0]
|
|
8007454: 461a mov r2, r3
|
|
8007456: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8007458: 61fb str r3, [r7, #28]
|
|
800745a: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800745c: 69b9 ldr r1, [r7, #24]
|
|
800745e: 69fa ldr r2, [r7, #28]
|
|
8007460: e841 2300 strex r3, r2, [r1]
|
|
8007464: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8007466: 697b ldr r3, [r7, #20]
|
|
8007468: 2b00 cmp r3, #0
|
|
800746a: d1e6 bne.n 800743a <UART_RxISR_8BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
800746c: 687b ldr r3, [r7, #4]
|
|
800746e: 681b ldr r3, [r3, #0]
|
|
8007470: 69db ldr r3, [r3, #28]
|
|
8007472: f003 0310 and.w r3, r3, #16
|
|
8007476: 2b10 cmp r3, #16
|
|
8007478: d103 bne.n 8007482 <UART_RxISR_8BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
800747a: 687b ldr r3, [r7, #4]
|
|
800747c: 681b ldr r3, [r3, #0]
|
|
800747e: 2210 movs r2, #16
|
|
8007480: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8007482: 687b ldr r3, [r7, #4]
|
|
8007484: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8007488: 4619 mov r1, r3
|
|
800748a: 6878 ldr r0, [r7, #4]
|
|
800748c: f7ff f8e0 bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8007490: e00b b.n 80074aa <UART_RxISR_8BIT+0x1aa>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8007492: 6878 ldr r0, [r7, #4]
|
|
8007494: f7f9 fde4 bl 8001060 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8007498: e007 b.n 80074aa <UART_RxISR_8BIT+0x1aa>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
800749a: 687b ldr r3, [r7, #4]
|
|
800749c: 681b ldr r3, [r3, #0]
|
|
800749e: 699a ldr r2, [r3, #24]
|
|
80074a0: 687b ldr r3, [r7, #4]
|
|
80074a2: 681b ldr r3, [r3, #0]
|
|
80074a4: f042 0208 orr.w r2, r2, #8
|
|
80074a8: 619a str r2, [r3, #24]
|
|
}
|
|
80074aa: bf00 nop
|
|
80074ac: 3770 adds r7, #112 @ 0x70
|
|
80074ae: 46bd mov sp, r7
|
|
80074b0: bd80 pop {r7, pc}
|
|
80074b2: bf00 nop
|
|
80074b4: 40008000 .word 0x40008000
|
|
|
|
080074b8 <UART_RxISR_16BIT>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
80074b8: b580 push {r7, lr}
|
|
80074ba: b09c sub sp, #112 @ 0x70
|
|
80074bc: af00 add r7, sp, #0
|
|
80074be: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
80074c0: 687b ldr r3, [r7, #4]
|
|
80074c2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
80074c6: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
80074ca: 687b ldr r3, [r7, #4]
|
|
80074cc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80074d0: 2b22 cmp r3, #34 @ 0x22
|
|
80074d2: f040 80be bne.w 8007652 <UART_RxISR_16BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
80074d6: 687b ldr r3, [r7, #4]
|
|
80074d8: 681b ldr r3, [r3, #0]
|
|
80074da: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80074dc: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
80074e0: 687b ldr r3, [r7, #4]
|
|
80074e2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80074e4: 66bb str r3, [r7, #104] @ 0x68
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
80074e6: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
|
|
80074ea: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
80074ee: 4013 ands r3, r2
|
|
80074f0: b29a uxth r2, r3
|
|
80074f2: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80074f4: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
80074f6: 687b ldr r3, [r7, #4]
|
|
80074f8: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80074fa: 1c9a adds r2, r3, #2
|
|
80074fc: 687b ldr r3, [r7, #4]
|
|
80074fe: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8007500: 687b ldr r3, [r7, #4]
|
|
8007502: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007506: b29b uxth r3, r3
|
|
8007508: 3b01 subs r3, #1
|
|
800750a: b29a uxth r2, r3
|
|
800750c: 687b ldr r3, [r7, #4]
|
|
800750e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8007512: 687b ldr r3, [r7, #4]
|
|
8007514: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007518: b29b uxth r3, r3
|
|
800751a: 2b00 cmp r3, #0
|
|
800751c: f040 80a1 bne.w 8007662 <UART_RxISR_16BIT+0x1aa>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8007520: 687b ldr r3, [r7, #4]
|
|
8007522: 681b ldr r3, [r3, #0]
|
|
8007524: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007526: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8007528: e853 3f00 ldrex r3, [r3]
|
|
800752c: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
800752e: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8007530: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8007534: 667b str r3, [r7, #100] @ 0x64
|
|
8007536: 687b ldr r3, [r7, #4]
|
|
8007538: 681b ldr r3, [r3, #0]
|
|
800753a: 461a mov r2, r3
|
|
800753c: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800753e: 657b str r3, [r7, #84] @ 0x54
|
|
8007540: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007542: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
8007544: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8007546: e841 2300 strex r3, r2, [r1]
|
|
800754a: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
800754c: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800754e: 2b00 cmp r3, #0
|
|
8007550: d1e6 bne.n 8007520 <UART_RxISR_16BIT+0x68>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8007552: 687b ldr r3, [r7, #4]
|
|
8007554: 681b ldr r3, [r3, #0]
|
|
8007556: 3308 adds r3, #8
|
|
8007558: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800755a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800755c: e853 3f00 ldrex r3, [r3]
|
|
8007560: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8007562: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8007564: f023 0301 bic.w r3, r3, #1
|
|
8007568: 663b str r3, [r7, #96] @ 0x60
|
|
800756a: 687b ldr r3, [r7, #4]
|
|
800756c: 681b ldr r3, [r3, #0]
|
|
800756e: 3308 adds r3, #8
|
|
8007570: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
8007572: 643a str r2, [r7, #64] @ 0x40
|
|
8007574: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007576: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8007578: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
800757a: e841 2300 strex r3, r2, [r1]
|
|
800757e: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8007580: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8007582: 2b00 cmp r3, #0
|
|
8007584: d1e5 bne.n 8007552 <UART_RxISR_16BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8007586: 687b ldr r3, [r7, #4]
|
|
8007588: 2220 movs r2, #32
|
|
800758a: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
800758e: 687b ldr r3, [r7, #4]
|
|
8007590: 2200 movs r2, #0
|
|
8007592: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8007594: 687b ldr r3, [r7, #4]
|
|
8007596: 2200 movs r2, #0
|
|
8007598: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
800759a: 687b ldr r3, [r7, #4]
|
|
800759c: 681b ldr r3, [r3, #0]
|
|
800759e: 4a33 ldr r2, [pc, #204] @ (800766c <UART_RxISR_16BIT+0x1b4>)
|
|
80075a0: 4293 cmp r3, r2
|
|
80075a2: d01f beq.n 80075e4 <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
80075a4: 687b ldr r3, [r7, #4]
|
|
80075a6: 681b ldr r3, [r3, #0]
|
|
80075a8: 685b ldr r3, [r3, #4]
|
|
80075aa: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80075ae: 2b00 cmp r3, #0
|
|
80075b0: d018 beq.n 80075e4 <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
80075b2: 687b ldr r3, [r7, #4]
|
|
80075b4: 681b ldr r3, [r3, #0]
|
|
80075b6: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80075b8: 6a3b ldr r3, [r7, #32]
|
|
80075ba: e853 3f00 ldrex r3, [r3]
|
|
80075be: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80075c0: 69fb ldr r3, [r7, #28]
|
|
80075c2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
80075c6: 65fb str r3, [r7, #92] @ 0x5c
|
|
80075c8: 687b ldr r3, [r7, #4]
|
|
80075ca: 681b ldr r3, [r3, #0]
|
|
80075cc: 461a mov r2, r3
|
|
80075ce: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80075d0: 62fb str r3, [r7, #44] @ 0x2c
|
|
80075d2: 62ba str r2, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80075d4: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
80075d6: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
80075d8: e841 2300 strex r3, r2, [r1]
|
|
80075dc: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
80075de: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80075e0: 2b00 cmp r3, #0
|
|
80075e2: d1e6 bne.n 80075b2 <UART_RxISR_16BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80075e4: 687b ldr r3, [r7, #4]
|
|
80075e6: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80075e8: 2b01 cmp r3, #1
|
|
80075ea: d12e bne.n 800764a <UART_RxISR_16BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
80075ec: 687b ldr r3, [r7, #4]
|
|
80075ee: 2200 movs r2, #0
|
|
80075f0: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80075f2: 687b ldr r3, [r7, #4]
|
|
80075f4: 681b ldr r3, [r3, #0]
|
|
80075f6: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80075f8: 68fb ldr r3, [r7, #12]
|
|
80075fa: e853 3f00 ldrex r3, [r3]
|
|
80075fe: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8007600: 68bb ldr r3, [r7, #8]
|
|
8007602: f023 0310 bic.w r3, r3, #16
|
|
8007606: 65bb str r3, [r7, #88] @ 0x58
|
|
8007608: 687b ldr r3, [r7, #4]
|
|
800760a: 681b ldr r3, [r3, #0]
|
|
800760c: 461a mov r2, r3
|
|
800760e: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8007610: 61bb str r3, [r7, #24]
|
|
8007612: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007614: 6979 ldr r1, [r7, #20]
|
|
8007616: 69ba ldr r2, [r7, #24]
|
|
8007618: e841 2300 strex r3, r2, [r1]
|
|
800761c: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800761e: 693b ldr r3, [r7, #16]
|
|
8007620: 2b00 cmp r3, #0
|
|
8007622: d1e6 bne.n 80075f2 <UART_RxISR_16BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8007624: 687b ldr r3, [r7, #4]
|
|
8007626: 681b ldr r3, [r3, #0]
|
|
8007628: 69db ldr r3, [r3, #28]
|
|
800762a: f003 0310 and.w r3, r3, #16
|
|
800762e: 2b10 cmp r3, #16
|
|
8007630: d103 bne.n 800763a <UART_RxISR_16BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8007632: 687b ldr r3, [r7, #4]
|
|
8007634: 681b ldr r3, [r3, #0]
|
|
8007636: 2210 movs r2, #16
|
|
8007638: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
800763a: 687b ldr r3, [r7, #4]
|
|
800763c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8007640: 4619 mov r1, r3
|
|
8007642: 6878 ldr r0, [r7, #4]
|
|
8007644: f7ff f804 bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8007648: e00b b.n 8007662 <UART_RxISR_16BIT+0x1aa>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
800764a: 6878 ldr r0, [r7, #4]
|
|
800764c: f7f9 fd08 bl 8001060 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8007650: e007 b.n 8007662 <UART_RxISR_16BIT+0x1aa>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8007652: 687b ldr r3, [r7, #4]
|
|
8007654: 681b ldr r3, [r3, #0]
|
|
8007656: 699a ldr r2, [r3, #24]
|
|
8007658: 687b ldr r3, [r7, #4]
|
|
800765a: 681b ldr r3, [r3, #0]
|
|
800765c: f042 0208 orr.w r2, r2, #8
|
|
8007660: 619a str r2, [r3, #24]
|
|
}
|
|
8007662: bf00 nop
|
|
8007664: 3770 adds r7, #112 @ 0x70
|
|
8007666: 46bd mov sp, r7
|
|
8007668: bd80 pop {r7, pc}
|
|
800766a: bf00 nop
|
|
800766c: 40008000 .word 0x40008000
|
|
|
|
08007670 <UART_RxISR_8BIT_FIFOEN>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|
{
|
|
8007670: b580 push {r7, lr}
|
|
8007672: b0ac sub sp, #176 @ 0xb0
|
|
8007674: af00 add r7, sp, #0
|
|
8007676: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
8007678: 687b ldr r3, [r7, #4]
|
|
800767a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
800767e: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa
|
|
uint16_t uhdata;
|
|
uint16_t nb_rx_data;
|
|
uint16_t rxdatacount;
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8007682: 687b ldr r3, [r7, #4]
|
|
8007684: 681b ldr r3, [r3, #0]
|
|
8007686: 69db ldr r3, [r3, #28]
|
|
8007688: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
800768c: 687b ldr r3, [r7, #4]
|
|
800768e: 681b ldr r3, [r3, #0]
|
|
8007690: 681b ldr r3, [r3, #0]
|
|
8007692: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8007696: 687b ldr r3, [r7, #4]
|
|
8007698: 681b ldr r3, [r3, #0]
|
|
800769a: 689b ldr r3, [r3, #8]
|
|
800769c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
80076a0: 687b ldr r3, [r7, #4]
|
|
80076a2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80076a6: 2b22 cmp r3, #34 @ 0x22
|
|
80076a8: f040 8183 bne.w 80079b2 <UART_RxISR_8BIT_FIFOEN+0x342>
|
|
{
|
|
nb_rx_data = huart->NbRxDataToProcess;
|
|
80076ac: 687b ldr r3, [r7, #4]
|
|
80076ae: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
80076b2: f8a7 309e strh.w r3, [r7, #158] @ 0x9e
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
80076b6: e126 b.n 8007906 <UART_RxISR_8BIT_FIFOEN+0x296>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
80076b8: 687b ldr r3, [r7, #4]
|
|
80076ba: 681b ldr r3, [r3, #0]
|
|
80076bc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80076be: f8a7 309c strh.w r3, [r7, #156] @ 0x9c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
80076c2: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c
|
|
80076c6: b2d9 uxtb r1, r3
|
|
80076c8: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa
|
|
80076cc: b2da uxtb r2, r3
|
|
80076ce: 687b ldr r3, [r7, #4]
|
|
80076d0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80076d2: 400a ands r2, r1
|
|
80076d4: b2d2 uxtb r2, r2
|
|
80076d6: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
80076d8: 687b ldr r3, [r7, #4]
|
|
80076da: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80076dc: 1c5a adds r2, r3, #1
|
|
80076de: 687b ldr r3, [r7, #4]
|
|
80076e0: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
80076e2: 687b ldr r3, [r7, #4]
|
|
80076e4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80076e8: b29b uxth r3, r3
|
|
80076ea: 3b01 subs r3, #1
|
|
80076ec: b29a uxth r2, r3
|
|
80076ee: 687b ldr r3, [r7, #4]
|
|
80076f0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
isrflags = READ_REG(huart->Instance->ISR);
|
|
80076f4: 687b ldr r3, [r7, #4]
|
|
80076f6: 681b ldr r3, [r3, #0]
|
|
80076f8: 69db ldr r3, [r3, #28]
|
|
80076fa: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
|
|
/* If some non blocking errors occurred */
|
|
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
|
|
80076fe: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8007702: f003 0307 and.w r3, r3, #7
|
|
8007706: 2b00 cmp r3, #0
|
|
8007708: d053 beq.n 80077b2 <UART_RxISR_8BIT_FIFOEN+0x142>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
800770a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800770e: f003 0301 and.w r3, r3, #1
|
|
8007712: 2b00 cmp r3, #0
|
|
8007714: d011 beq.n 800773a <UART_RxISR_8BIT_FIFOEN+0xca>
|
|
8007716: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
|
|
800771a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800771e: 2b00 cmp r3, #0
|
|
8007720: d00b beq.n 800773a <UART_RxISR_8BIT_FIFOEN+0xca>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8007722: 687b ldr r3, [r7, #4]
|
|
8007724: 681b ldr r3, [r3, #0]
|
|
8007726: 2201 movs r2, #1
|
|
8007728: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
800772a: 687b ldr r3, [r7, #4]
|
|
800772c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007730: f043 0201 orr.w r2, r3, #1
|
|
8007734: 687b ldr r3, [r7, #4]
|
|
8007736: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800773a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800773e: f003 0302 and.w r3, r3, #2
|
|
8007742: 2b00 cmp r3, #0
|
|
8007744: d011 beq.n 800776a <UART_RxISR_8BIT_FIFOEN+0xfa>
|
|
8007746: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
800774a: f003 0301 and.w r3, r3, #1
|
|
800774e: 2b00 cmp r3, #0
|
|
8007750: d00b beq.n 800776a <UART_RxISR_8BIT_FIFOEN+0xfa>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8007752: 687b ldr r3, [r7, #4]
|
|
8007754: 681b ldr r3, [r3, #0]
|
|
8007756: 2202 movs r2, #2
|
|
8007758: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
800775a: 687b ldr r3, [r7, #4]
|
|
800775c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007760: f043 0204 orr.w r2, r3, #4
|
|
8007764: 687b ldr r3, [r7, #4]
|
|
8007766: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800776a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800776e: f003 0304 and.w r3, r3, #4
|
|
8007772: 2b00 cmp r3, #0
|
|
8007774: d011 beq.n 800779a <UART_RxISR_8BIT_FIFOEN+0x12a>
|
|
8007776: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
800777a: f003 0301 and.w r3, r3, #1
|
|
800777e: 2b00 cmp r3, #0
|
|
8007780: d00b beq.n 800779a <UART_RxISR_8BIT_FIFOEN+0x12a>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8007782: 687b ldr r3, [r7, #4]
|
|
8007784: 681b ldr r3, [r3, #0]
|
|
8007786: 2204 movs r2, #4
|
|
8007788: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
800778a: 687b ldr r3, [r7, #4]
|
|
800778c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007790: f043 0202 orr.w r2, r3, #2
|
|
8007794: 687b ldr r3, [r7, #4]
|
|
8007796: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
800779a: 687b ldr r3, [r7, #4]
|
|
800779c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80077a0: 2b00 cmp r3, #0
|
|
80077a2: d006 beq.n 80077b2 <UART_RxISR_8BIT_FIFOEN+0x142>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80077a4: 6878 ldr r0, [r7, #4]
|
|
80077a6: f7fe ff49 bl 800663c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80077aa: 687b ldr r3, [r7, #4]
|
|
80077ac: 2200 movs r2, #0
|
|
80077ae: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
80077b2: 687b ldr r3, [r7, #4]
|
|
80077b4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
80077b8: b29b uxth r3, r3
|
|
80077ba: 2b00 cmp r3, #0
|
|
80077bc: f040 80a3 bne.w 8007906 <UART_RxISR_8BIT_FIFOEN+0x296>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
80077c0: 687b ldr r3, [r7, #4]
|
|
80077c2: 681b ldr r3, [r3, #0]
|
|
80077c4: 673b str r3, [r7, #112] @ 0x70
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80077c6: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80077c8: e853 3f00 ldrex r3, [r3]
|
|
80077cc: 66fb str r3, [r7, #108] @ 0x6c
|
|
return(result);
|
|
80077ce: 6efb ldr r3, [r7, #108] @ 0x6c
|
|
80077d0: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80077d4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80077d8: 687b ldr r3, [r7, #4]
|
|
80077da: 681b ldr r3, [r3, #0]
|
|
80077dc: 461a mov r2, r3
|
|
80077de: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
80077e2: 67fb str r3, [r7, #124] @ 0x7c
|
|
80077e4: 67ba str r2, [r7, #120] @ 0x78
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80077e6: 6fb9 ldr r1, [r7, #120] @ 0x78
|
|
80077e8: 6ffa ldr r2, [r7, #124] @ 0x7c
|
|
80077ea: e841 2300 strex r3, r2, [r1]
|
|
80077ee: 677b str r3, [r7, #116] @ 0x74
|
|
return(result);
|
|
80077f0: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80077f2: 2b00 cmp r3, #0
|
|
80077f4: d1e4 bne.n 80077c0 <UART_RxISR_8BIT_FIFOEN+0x150>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
|
and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
80077f6: 687b ldr r3, [r7, #4]
|
|
80077f8: 681b ldr r3, [r3, #0]
|
|
80077fa: 3308 adds r3, #8
|
|
80077fc: 65fb str r3, [r7, #92] @ 0x5c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80077fe: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8007800: e853 3f00 ldrex r3, [r3]
|
|
8007804: 65bb str r3, [r7, #88] @ 0x58
|
|
return(result);
|
|
8007806: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8007808: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800780c: f023 0301 bic.w r3, r3, #1
|
|
8007810: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8007814: 687b ldr r3, [r7, #4]
|
|
8007816: 681b ldr r3, [r3, #0]
|
|
8007818: 3308 adds r3, #8
|
|
800781a: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
800781e: 66ba str r2, [r7, #104] @ 0x68
|
|
8007820: 667b str r3, [r7, #100] @ 0x64
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007822: 6e79 ldr r1, [r7, #100] @ 0x64
|
|
8007824: 6eba ldr r2, [r7, #104] @ 0x68
|
|
8007826: e841 2300 strex r3, r2, [r1]
|
|
800782a: 663b str r3, [r7, #96] @ 0x60
|
|
return(result);
|
|
800782c: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
800782e: 2b00 cmp r3, #0
|
|
8007830: d1e1 bne.n 80077f6 <UART_RxISR_8BIT_FIFOEN+0x186>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8007832: 687b ldr r3, [r7, #4]
|
|
8007834: 2220 movs r2, #32
|
|
8007836: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
800783a: 687b ldr r3, [r7, #4]
|
|
800783c: 2200 movs r2, #0
|
|
800783e: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8007840: 687b ldr r3, [r7, #4]
|
|
8007842: 2200 movs r2, #0
|
|
8007844: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8007846: 687b ldr r3, [r7, #4]
|
|
8007848: 681b ldr r3, [r3, #0]
|
|
800784a: 4a60 ldr r2, [pc, #384] @ (80079cc <UART_RxISR_8BIT_FIFOEN+0x35c>)
|
|
800784c: 4293 cmp r3, r2
|
|
800784e: d021 beq.n 8007894 <UART_RxISR_8BIT_FIFOEN+0x224>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8007850: 687b ldr r3, [r7, #4]
|
|
8007852: 681b ldr r3, [r3, #0]
|
|
8007854: 685b ldr r3, [r3, #4]
|
|
8007856: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
800785a: 2b00 cmp r3, #0
|
|
800785c: d01a beq.n 8007894 <UART_RxISR_8BIT_FIFOEN+0x224>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
800785e: 687b ldr r3, [r7, #4]
|
|
8007860: 681b ldr r3, [r3, #0]
|
|
8007862: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007864: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8007866: e853 3f00 ldrex r3, [r3]
|
|
800786a: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
800786c: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800786e: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8007872: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8007876: 687b ldr r3, [r7, #4]
|
|
8007878: 681b ldr r3, [r3, #0]
|
|
800787a: 461a mov r2, r3
|
|
800787c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8007880: 657b str r3, [r7, #84] @ 0x54
|
|
8007882: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007884: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
8007886: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8007888: e841 2300 strex r3, r2, [r1]
|
|
800788c: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
800788e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8007890: 2b00 cmp r3, #0
|
|
8007892: d1e4 bne.n 800785e <UART_RxISR_8BIT_FIFOEN+0x1ee>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8007894: 687b ldr r3, [r7, #4]
|
|
8007896: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8007898: 2b01 cmp r3, #1
|
|
800789a: d130 bne.n 80078fe <UART_RxISR_8BIT_FIFOEN+0x28e>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800789c: 687b ldr r3, [r7, #4]
|
|
800789e: 2200 movs r2, #0
|
|
80078a0: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
80078a2: 687b ldr r3, [r7, #4]
|
|
80078a4: 681b ldr r3, [r3, #0]
|
|
80078a6: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80078a8: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80078aa: e853 3f00 ldrex r3, [r3]
|
|
80078ae: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
80078b0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
80078b2: f023 0310 bic.w r3, r3, #16
|
|
80078b6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
80078ba: 687b ldr r3, [r7, #4]
|
|
80078bc: 681b ldr r3, [r3, #0]
|
|
80078be: 461a mov r2, r3
|
|
80078c0: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
80078c4: 643b str r3, [r7, #64] @ 0x40
|
|
80078c6: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80078c8: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80078ca: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80078cc: e841 2300 strex r3, r2, [r1]
|
|
80078d0: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
80078d2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80078d4: 2b00 cmp r3, #0
|
|
80078d6: d1e4 bne.n 80078a2 <UART_RxISR_8BIT_FIFOEN+0x232>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
80078d8: 687b ldr r3, [r7, #4]
|
|
80078da: 681b ldr r3, [r3, #0]
|
|
80078dc: 69db ldr r3, [r3, #28]
|
|
80078de: f003 0310 and.w r3, r3, #16
|
|
80078e2: 2b10 cmp r3, #16
|
|
80078e4: d103 bne.n 80078ee <UART_RxISR_8BIT_FIFOEN+0x27e>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80078e6: 687b ldr r3, [r7, #4]
|
|
80078e8: 681b ldr r3, [r3, #0]
|
|
80078ea: 2210 movs r2, #16
|
|
80078ec: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80078ee: 687b ldr r3, [r7, #4]
|
|
80078f0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
80078f4: 4619 mov r1, r3
|
|
80078f6: 6878 ldr r0, [r7, #4]
|
|
80078f8: f7fe feaa bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
break;
|
|
80078fc: e00e b.n 800791c <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
80078fe: 6878 ldr r0, [r7, #4]
|
|
8007900: f7f9 fbae bl 8001060 <HAL_UART_RxCpltCallback>
|
|
break;
|
|
8007904: e00a b.n 800791c <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8007906: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e
|
|
800790a: 2b00 cmp r3, #0
|
|
800790c: d006 beq.n 800791c <UART_RxISR_8BIT_FIFOEN+0x2ac>
|
|
800790e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8007912: f003 0320 and.w r3, r3, #32
|
|
8007916: 2b00 cmp r3, #0
|
|
8007918: f47f aece bne.w 80076b8 <UART_RxISR_8BIT_FIFOEN+0x48>
|
|
|
|
/* When remaining number of bytes to receive is less than the RX FIFO
|
|
threshold, next incoming frames are processed as if FIFO mode was
|
|
disabled (i.e. one interrupt per received frame).
|
|
*/
|
|
rxdatacount = huart->RxXferCount;
|
|
800791c: 687b ldr r3, [r7, #4]
|
|
800791e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007922: f8a7 308a strh.w r3, [r7, #138] @ 0x8a
|
|
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
|
8007926: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a
|
|
800792a: 2b00 cmp r3, #0
|
|
800792c: d049 beq.n 80079c2 <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
800792e: 687b ldr r3, [r7, #4]
|
|
8007930: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8007934: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a
|
|
8007938: 429a cmp r2, r3
|
|
800793a: d242 bcs.n 80079c2 <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
{
|
|
/* Disable the UART RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
800793c: 687b ldr r3, [r7, #4]
|
|
800793e: 681b ldr r3, [r3, #0]
|
|
8007940: 3308 adds r3, #8
|
|
8007942: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007944: 6a3b ldr r3, [r7, #32]
|
|
8007946: e853 3f00 ldrex r3, [r3]
|
|
800794a: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
800794c: 69fb ldr r3, [r7, #28]
|
|
800794e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8007952: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8007956: 687b ldr r3, [r7, #4]
|
|
8007958: 681b ldr r3, [r3, #0]
|
|
800795a: 3308 adds r3, #8
|
|
800795c: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84
|
|
8007960: 62fa str r2, [r7, #44] @ 0x2c
|
|
8007962: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007964: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8007966: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
8007968: e841 2300 strex r3, r2, [r1]
|
|
800796c: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
800796e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007970: 2b00 cmp r3, #0
|
|
8007972: d1e3 bne.n 800793c <UART_RxISR_8BIT_FIFOEN+0x2cc>
|
|
|
|
/* Update the RxISR function pointer */
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
8007974: 687b ldr r3, [r7, #4]
|
|
8007976: 4a16 ldr r2, [pc, #88] @ (80079d0 <UART_RxISR_8BIT_FIFOEN+0x360>)
|
|
8007978: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Enable the UART Data Register Not Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
800797a: 687b ldr r3, [r7, #4]
|
|
800797c: 681b ldr r3, [r3, #0]
|
|
800797e: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007980: 68fb ldr r3, [r7, #12]
|
|
8007982: e853 3f00 ldrex r3, [r3]
|
|
8007986: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8007988: 68bb ldr r3, [r7, #8]
|
|
800798a: f043 0320 orr.w r3, r3, #32
|
|
800798e: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8007992: 687b ldr r3, [r7, #4]
|
|
8007994: 681b ldr r3, [r3, #0]
|
|
8007996: 461a mov r2, r3
|
|
8007998: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
|
|
800799c: 61bb str r3, [r7, #24]
|
|
800799e: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80079a0: 6979 ldr r1, [r7, #20]
|
|
80079a2: 69ba ldr r2, [r7, #24]
|
|
80079a4: e841 2300 strex r3, r2, [r1]
|
|
80079a8: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80079aa: 693b ldr r3, [r7, #16]
|
|
80079ac: 2b00 cmp r3, #0
|
|
80079ae: d1e4 bne.n 800797a <UART_RxISR_8BIT_FIFOEN+0x30a>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
80079b0: e007 b.n 80079c2 <UART_RxISR_8BIT_FIFOEN+0x352>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
80079b2: 687b ldr r3, [r7, #4]
|
|
80079b4: 681b ldr r3, [r3, #0]
|
|
80079b6: 699a ldr r2, [r3, #24]
|
|
80079b8: 687b ldr r3, [r7, #4]
|
|
80079ba: 681b ldr r3, [r3, #0]
|
|
80079bc: f042 0208 orr.w r2, r2, #8
|
|
80079c0: 619a str r2, [r3, #24]
|
|
}
|
|
80079c2: bf00 nop
|
|
80079c4: 37b0 adds r7, #176 @ 0xb0
|
|
80079c6: 46bd mov sp, r7
|
|
80079c8: bd80 pop {r7, pc}
|
|
80079ca: bf00 nop
|
|
80079cc: 40008000 .word 0x40008000
|
|
80079d0: 08007301 .word 0x08007301
|
|
|
|
080079d4 <UART_RxISR_16BIT_FIFOEN>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
|
|
{
|
|
80079d4: b580 push {r7, lr}
|
|
80079d6: b0ae sub sp, #184 @ 0xb8
|
|
80079d8: af00 add r7, sp, #0
|
|
80079da: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
80079dc: 687b ldr r3, [r7, #4]
|
|
80079de: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60
|
|
80079e2: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2
|
|
uint16_t uhdata;
|
|
uint16_t nb_rx_data;
|
|
uint16_t rxdatacount;
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
80079e6: 687b ldr r3, [r7, #4]
|
|
80079e8: 681b ldr r3, [r3, #0]
|
|
80079ea: 69db ldr r3, [r3, #28]
|
|
80079ec: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
80079f0: 687b ldr r3, [r7, #4]
|
|
80079f2: 681b ldr r3, [r3, #0]
|
|
80079f4: 681b ldr r3, [r3, #0]
|
|
80079f6: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
80079fa: 687b ldr r3, [r7, #4]
|
|
80079fc: 681b ldr r3, [r3, #0]
|
|
80079fe: 689b ldr r3, [r3, #8]
|
|
8007a00: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8007a04: 687b ldr r3, [r7, #4]
|
|
8007a06: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8007a0a: 2b22 cmp r3, #34 @ 0x22
|
|
8007a0c: f040 8187 bne.w 8007d1e <UART_RxISR_16BIT_FIFOEN+0x34a>
|
|
{
|
|
nb_rx_data = huart->NbRxDataToProcess;
|
|
8007a10: 687b ldr r3, [r7, #4]
|
|
8007a12: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8007a16: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8007a1a: e12a b.n 8007c72 <UART_RxISR_16BIT_FIFOEN+0x29e>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
8007a1c: 687b ldr r3, [r7, #4]
|
|
8007a1e: 681b ldr r3, [r3, #0]
|
|
8007a20: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007a22: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
8007a26: 687b ldr r3, [r7, #4]
|
|
8007a28: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007a2a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
8007a2e: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4
|
|
8007a32: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2
|
|
8007a36: 4013 ands r3, r2
|
|
8007a38: b29a uxth r2, r3
|
|
8007a3a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
8007a3e: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
8007a40: 687b ldr r3, [r7, #4]
|
|
8007a42: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8007a44: 1c9a adds r2, r3, #2
|
|
8007a46: 687b ldr r3, [r7, #4]
|
|
8007a48: 659a str r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount--;
|
|
8007a4a: 687b ldr r3, [r7, #4]
|
|
8007a4c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007a50: b29b uxth r3, r3
|
|
8007a52: 3b01 subs r3, #1
|
|
8007a54: b29a uxth r2, r3
|
|
8007a56: 687b ldr r3, [r7, #4]
|
|
8007a58: f8a3 205e strh.w r2, [r3, #94] @ 0x5e
|
|
isrflags = READ_REG(huart->Instance->ISR);
|
|
8007a5c: 687b ldr r3, [r7, #4]
|
|
8007a5e: 681b ldr r3, [r3, #0]
|
|
8007a60: 69db ldr r3, [r3, #28]
|
|
8007a62: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
|
|
/* If some non blocking errors occurred */
|
|
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
|
|
8007a66: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8007a6a: f003 0307 and.w r3, r3, #7
|
|
8007a6e: 2b00 cmp r3, #0
|
|
8007a70: d053 beq.n 8007b1a <UART_RxISR_16BIT_FIFOEN+0x146>
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
8007a72: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8007a76: f003 0301 and.w r3, r3, #1
|
|
8007a7a: 2b00 cmp r3, #0
|
|
8007a7c: d011 beq.n 8007aa2 <UART_RxISR_16BIT_FIFOEN+0xce>
|
|
8007a7e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
8007a82: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8007a86: 2b00 cmp r3, #0
|
|
8007a88: d00b beq.n 8007aa2 <UART_RxISR_16BIT_FIFOEN+0xce>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
8007a8a: 687b ldr r3, [r7, #4]
|
|
8007a8c: 681b ldr r3, [r3, #0]
|
|
8007a8e: 2201 movs r2, #1
|
|
8007a90: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
8007a92: 687b ldr r3, [r7, #4]
|
|
8007a94: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007a98: f043 0201 orr.w r2, r3, #1
|
|
8007a9c: 687b ldr r3, [r7, #4]
|
|
8007a9e: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8007aa2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8007aa6: f003 0302 and.w r3, r3, #2
|
|
8007aaa: 2b00 cmp r3, #0
|
|
8007aac: d011 beq.n 8007ad2 <UART_RxISR_16BIT_FIFOEN+0xfe>
|
|
8007aae: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8007ab2: f003 0301 and.w r3, r3, #1
|
|
8007ab6: 2b00 cmp r3, #0
|
|
8007ab8: d00b beq.n 8007ad2 <UART_RxISR_16BIT_FIFOEN+0xfe>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8007aba: 687b ldr r3, [r7, #4]
|
|
8007abc: 681b ldr r3, [r3, #0]
|
|
8007abe: 2202 movs r2, #2
|
|
8007ac0: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
8007ac2: 687b ldr r3, [r7, #4]
|
|
8007ac4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007ac8: f043 0204 orr.w r2, r3, #4
|
|
8007acc: 687b ldr r3, [r7, #4]
|
|
8007ace: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8007ad2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8007ad6: f003 0304 and.w r3, r3, #4
|
|
8007ada: 2b00 cmp r3, #0
|
|
8007adc: d011 beq.n 8007b02 <UART_RxISR_16BIT_FIFOEN+0x12e>
|
|
8007ade: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
|
|
8007ae2: f003 0301 and.w r3, r3, #1
|
|
8007ae6: 2b00 cmp r3, #0
|
|
8007ae8: d00b beq.n 8007b02 <UART_RxISR_16BIT_FIFOEN+0x12e>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8007aea: 687b ldr r3, [r7, #4]
|
|
8007aec: 681b ldr r3, [r3, #0]
|
|
8007aee: 2204 movs r2, #4
|
|
8007af0: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8007af2: 687b ldr r3, [r7, #4]
|
|
8007af4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007af8: f043 0202 orr.w r2, r3, #2
|
|
8007afc: 687b ldr r3, [r7, #4]
|
|
8007afe: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
8007b02: 687b ldr r3, [r7, #4]
|
|
8007b04: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8007b08: 2b00 cmp r3, #0
|
|
8007b0a: d006 beq.n 8007b1a <UART_RxISR_16BIT_FIFOEN+0x146>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8007b0c: 6878 ldr r0, [r7, #4]
|
|
8007b0e: f7fe fd95 bl 800663c <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8007b12: 687b ldr r3, [r7, #4]
|
|
8007b14: 2200 movs r2, #0
|
|
8007b16: f8c3 2090 str.w r2, [r3, #144] @ 0x90
|
|
}
|
|
}
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8007b1a: 687b ldr r3, [r7, #4]
|
|
8007b1c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007b20: b29b uxth r3, r3
|
|
8007b22: 2b00 cmp r3, #0
|
|
8007b24: f040 80a5 bne.w 8007c72 <UART_RxISR_16BIT_FIFOEN+0x29e>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8007b28: 687b ldr r3, [r7, #4]
|
|
8007b2a: 681b ldr r3, [r3, #0]
|
|
8007b2c: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007b2e: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
8007b30: e853 3f00 ldrex r3, [r3]
|
|
8007b34: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
8007b36: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
8007b38: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8007b3c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8007b40: 687b ldr r3, [r7, #4]
|
|
8007b42: 681b ldr r3, [r3, #0]
|
|
8007b44: 461a mov r2, r3
|
|
8007b46: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8007b4a: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8007b4e: 67fa str r2, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007b50: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
8007b52: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
8007b56: e841 2300 strex r3, r2, [r1]
|
|
8007b5a: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
8007b5c: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
8007b5e: 2b00 cmp r3, #0
|
|
8007b60: d1e2 bne.n 8007b28 <UART_RxISR_16BIT_FIFOEN+0x154>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
|
|
and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
8007b62: 687b ldr r3, [r7, #4]
|
|
8007b64: 681b ldr r3, [r3, #0]
|
|
8007b66: 3308 adds r3, #8
|
|
8007b68: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007b6a: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8007b6c: e853 3f00 ldrex r3, [r3]
|
|
8007b70: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
8007b72: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8007b74: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8007b78: f023 0301 bic.w r3, r3, #1
|
|
8007b7c: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8007b80: 687b ldr r3, [r7, #4]
|
|
8007b82: 681b ldr r3, [r3, #0]
|
|
8007b84: 3308 adds r3, #8
|
|
8007b86: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98
|
|
8007b8a: 66fa str r2, [r7, #108] @ 0x6c
|
|
8007b8c: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007b8e: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8007b90: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
8007b92: e841 2300 strex r3, r2, [r1]
|
|
8007b96: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8007b98: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8007b9a: 2b00 cmp r3, #0
|
|
8007b9c: d1e1 bne.n 8007b62 <UART_RxISR_16BIT_FIFOEN+0x18e>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8007b9e: 687b ldr r3, [r7, #4]
|
|
8007ba0: 2220 movs r2, #32
|
|
8007ba2: f8c3 208c str.w r2, [r3, #140] @ 0x8c
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8007ba6: 687b ldr r3, [r7, #4]
|
|
8007ba8: 2200 movs r2, #0
|
|
8007baa: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8007bac: 687b ldr r3, [r7, #4]
|
|
8007bae: 2200 movs r2, #0
|
|
8007bb0: 671a str r2, [r3, #112] @ 0x70
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8007bb2: 687b ldr r3, [r7, #4]
|
|
8007bb4: 681b ldr r3, [r3, #0]
|
|
8007bb6: 4a60 ldr r2, [pc, #384] @ (8007d38 <UART_RxISR_16BIT_FIFOEN+0x364>)
|
|
8007bb8: 4293 cmp r3, r2
|
|
8007bba: d021 beq.n 8007c00 <UART_RxISR_16BIT_FIFOEN+0x22c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8007bbc: 687b ldr r3, [r7, #4]
|
|
8007bbe: 681b ldr r3, [r3, #0]
|
|
8007bc0: 685b ldr r3, [r3, #4]
|
|
8007bc2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8007bc6: 2b00 cmp r3, #0
|
|
8007bc8: d01a beq.n 8007c00 <UART_RxISR_16BIT_FIFOEN+0x22c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8007bca: 687b ldr r3, [r7, #4]
|
|
8007bcc: 681b ldr r3, [r3, #0]
|
|
8007bce: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007bd0: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8007bd2: e853 3f00 ldrex r3, [r3]
|
|
8007bd6: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
8007bd8: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
8007bda: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8007bde: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
8007be2: 687b ldr r3, [r7, #4]
|
|
8007be4: 681b ldr r3, [r3, #0]
|
|
8007be6: 461a mov r2, r3
|
|
8007be8: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
|
|
8007bec: 65bb str r3, [r7, #88] @ 0x58
|
|
8007bee: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007bf0: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8007bf2: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8007bf4: e841 2300 strex r3, r2, [r1]
|
|
8007bf8: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
8007bfa: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8007bfc: 2b00 cmp r3, #0
|
|
8007bfe: d1e4 bne.n 8007bca <UART_RxISR_16BIT_FIFOEN+0x1f6>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8007c00: 687b ldr r3, [r7, #4]
|
|
8007c02: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
8007c04: 2b01 cmp r3, #1
|
|
8007c06: d130 bne.n 8007c6a <UART_RxISR_16BIT_FIFOEN+0x296>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8007c08: 687b ldr r3, [r7, #4]
|
|
8007c0a: 2200 movs r2, #0
|
|
8007c0c: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8007c0e: 687b ldr r3, [r7, #4]
|
|
8007c10: 681b ldr r3, [r3, #0]
|
|
8007c12: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007c14: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8007c16: e853 3f00 ldrex r3, [r3]
|
|
8007c1a: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8007c1c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8007c1e: f023 0310 bic.w r3, r3, #16
|
|
8007c22: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8007c26: 687b ldr r3, [r7, #4]
|
|
8007c28: 681b ldr r3, [r3, #0]
|
|
8007c2a: 461a mov r2, r3
|
|
8007c2c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
|
|
8007c30: 647b str r3, [r7, #68] @ 0x44
|
|
8007c32: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007c34: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8007c36: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8007c38: e841 2300 strex r3, r2, [r1]
|
|
8007c3c: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8007c3e: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8007c40: 2b00 cmp r3, #0
|
|
8007c42: d1e4 bne.n 8007c0e <UART_RxISR_16BIT_FIFOEN+0x23a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8007c44: 687b ldr r3, [r7, #4]
|
|
8007c46: 681b ldr r3, [r3, #0]
|
|
8007c48: 69db ldr r3, [r3, #28]
|
|
8007c4a: f003 0310 and.w r3, r3, #16
|
|
8007c4e: 2b10 cmp r3, #16
|
|
8007c50: d103 bne.n 8007c5a <UART_RxISR_16BIT_FIFOEN+0x286>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8007c52: 687b ldr r3, [r7, #4]
|
|
8007c54: 681b ldr r3, [r3, #0]
|
|
8007c56: 2210 movs r2, #16
|
|
8007c58: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
8007c5a: 687b ldr r3, [r7, #4]
|
|
8007c5c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
8007c60: 4619 mov r1, r3
|
|
8007c62: 6878 ldr r0, [r7, #4]
|
|
8007c64: f7fe fcf4 bl 8006650 <HAL_UARTEx_RxEventCallback>
|
|
#else
|
|
/*Call legacy weak Rx complete callback*/
|
|
HAL_UART_RxCpltCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
break;
|
|
8007c68: e00e b.n 8007c88 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8007c6a: 6878 ldr r0, [r7, #4]
|
|
8007c6c: f7f9 f9f8 bl 8001060 <HAL_UART_RxCpltCallback>
|
|
break;
|
|
8007c70: e00a b.n 8007c88 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
|
|
8007c72: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6
|
|
8007c76: 2b00 cmp r3, #0
|
|
8007c78: d006 beq.n 8007c88 <UART_RxISR_16BIT_FIFOEN+0x2b4>
|
|
8007c7a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
|
|
8007c7e: f003 0320 and.w r3, r3, #32
|
|
8007c82: 2b00 cmp r3, #0
|
|
8007c84: f47f aeca bne.w 8007a1c <UART_RxISR_16BIT_FIFOEN+0x48>
|
|
|
|
/* When remaining number of bytes to receive is less than the RX FIFO
|
|
threshold, next incoming frames are processed as if FIFO mode was
|
|
disabled (i.e. one interrupt per received frame).
|
|
*/
|
|
rxdatacount = huart->RxXferCount;
|
|
8007c88: 687b ldr r3, [r7, #4]
|
|
8007c8a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e
|
|
8007c8e: f8a7 308e strh.w r3, [r7, #142] @ 0x8e
|
|
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
|
|
8007c92: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e
|
|
8007c96: 2b00 cmp r3, #0
|
|
8007c98: d049 beq.n 8007d2e <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
8007c9a: 687b ldr r3, [r7, #4]
|
|
8007c9c: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68
|
|
8007ca0: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e
|
|
8007ca4: 429a cmp r2, r3
|
|
8007ca6: d242 bcs.n 8007d2e <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
{
|
|
/* Disable the UART RXFT interrupt*/
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
|
|
8007ca8: 687b ldr r3, [r7, #4]
|
|
8007caa: 681b ldr r3, [r3, #0]
|
|
8007cac: 3308 adds r3, #8
|
|
8007cae: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007cb0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8007cb2: e853 3f00 ldrex r3, [r3]
|
|
8007cb6: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8007cb8: 6a3b ldr r3, [r7, #32]
|
|
8007cba: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8007cbe: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8007cc2: 687b ldr r3, [r7, #4]
|
|
8007cc4: 681b ldr r3, [r3, #0]
|
|
8007cc6: 3308 adds r3, #8
|
|
8007cc8: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88
|
|
8007ccc: 633a str r2, [r7, #48] @ 0x30
|
|
8007cce: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007cd0: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8007cd2: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8007cd4: e841 2300 strex r3, r2, [r1]
|
|
8007cd8: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8007cda: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8007cdc: 2b00 cmp r3, #0
|
|
8007cde: d1e3 bne.n 8007ca8 <UART_RxISR_16BIT_FIFOEN+0x2d4>
|
|
|
|
/* Update the RxISR function pointer */
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
8007ce0: 687b ldr r3, [r7, #4]
|
|
8007ce2: 4a16 ldr r2, [pc, #88] @ (8007d3c <UART_RxISR_16BIT_FIFOEN+0x368>)
|
|
8007ce4: 675a str r2, [r3, #116] @ 0x74
|
|
|
|
/* Enable the UART Data Register Not Empty interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
8007ce6: 687b ldr r3, [r7, #4]
|
|
8007ce8: 681b ldr r3, [r3, #0]
|
|
8007cea: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8007cec: 693b ldr r3, [r7, #16]
|
|
8007cee: e853 3f00 ldrex r3, [r3]
|
|
8007cf2: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8007cf4: 68fb ldr r3, [r7, #12]
|
|
8007cf6: f043 0320 orr.w r3, r3, #32
|
|
8007cfa: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8007cfe: 687b ldr r3, [r7, #4]
|
|
8007d00: 681b ldr r3, [r3, #0]
|
|
8007d02: 461a mov r2, r3
|
|
8007d04: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8007d08: 61fb str r3, [r7, #28]
|
|
8007d0a: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8007d0c: 69b9 ldr r1, [r7, #24]
|
|
8007d0e: 69fa ldr r2, [r7, #28]
|
|
8007d10: e841 2300 strex r3, r2, [r1]
|
|
8007d14: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8007d16: 697b ldr r3, [r7, #20]
|
|
8007d18: 2b00 cmp r3, #0
|
|
8007d1a: d1e4 bne.n 8007ce6 <UART_RxISR_16BIT_FIFOEN+0x312>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
8007d1c: e007 b.n 8007d2e <UART_RxISR_16BIT_FIFOEN+0x35a>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8007d1e: 687b ldr r3, [r7, #4]
|
|
8007d20: 681b ldr r3, [r3, #0]
|
|
8007d22: 699a ldr r2, [r3, #24]
|
|
8007d24: 687b ldr r3, [r7, #4]
|
|
8007d26: 681b ldr r3, [r3, #0]
|
|
8007d28: f042 0208 orr.w r2, r2, #8
|
|
8007d2c: 619a str r2, [r3, #24]
|
|
}
|
|
8007d2e: bf00 nop
|
|
8007d30: 37b8 adds r7, #184 @ 0xb8
|
|
8007d32: 46bd mov sp, r7
|
|
8007d34: bd80 pop {r7, pc}
|
|
8007d36: bf00 nop
|
|
8007d38: 40008000 .word 0x40008000
|
|
8007d3c: 080074b9 .word 0x080074b9
|
|
|
|
08007d40 <HAL_UARTEx_WakeupCallback>:
|
|
* @brief UART wakeup from Stop mode callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8007d40: b480 push {r7}
|
|
8007d42: b083 sub sp, #12
|
|
8007d44: af00 add r7, sp, #0
|
|
8007d46: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8007d48: bf00 nop
|
|
8007d4a: 370c adds r7, #12
|
|
8007d4c: 46bd mov sp, r7
|
|
8007d4e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d52: 4770 bx lr
|
|
|
|
08007d54 <HAL_UARTEx_RxFifoFullCallback>:
|
|
* @brief UART RX Fifo full callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8007d54: b480 push {r7}
|
|
8007d56: b083 sub sp, #12
|
|
8007d58: af00 add r7, sp, #0
|
|
8007d5a: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8007d5c: bf00 nop
|
|
8007d5e: 370c adds r7, #12
|
|
8007d60: 46bd mov sp, r7
|
|
8007d62: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d66: 4770 bx lr
|
|
|
|
08007d68 <HAL_UARTEx_TxFifoEmptyCallback>:
|
|
* @brief UART TX Fifo empty callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8007d68: b480 push {r7}
|
|
8007d6a: b083 sub sp, #12
|
|
8007d6c: af00 add r7, sp, #0
|
|
8007d6e: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8007d70: bf00 nop
|
|
8007d72: 370c adds r7, #12
|
|
8007d74: 46bd mov sp, r7
|
|
8007d76: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d7a: 4770 bx lr
|
|
|
|
08007d7c <HAL_UARTEx_DisableFifoMode>:
|
|
* @brief Disable the FIFO mode.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
|
|
{
|
|
8007d7c: b480 push {r7}
|
|
8007d7e: b085 sub sp, #20
|
|
8007d80: af00 add r7, sp, #0
|
|
8007d82: 6078 str r0, [r7, #4]
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8007d84: 687b ldr r3, [r7, #4]
|
|
8007d86: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8007d8a: 2b01 cmp r3, #1
|
|
8007d8c: d101 bne.n 8007d92 <HAL_UARTEx_DisableFifoMode+0x16>
|
|
8007d8e: 2302 movs r3, #2
|
|
8007d90: e027 b.n 8007de2 <HAL_UARTEx_DisableFifoMode+0x66>
|
|
8007d92: 687b ldr r3, [r7, #4]
|
|
8007d94: 2201 movs r2, #1
|
|
8007d96: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8007d9a: 687b ldr r3, [r7, #4]
|
|
8007d9c: 2224 movs r2, #36 @ 0x24
|
|
8007d9e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
8007da2: 687b ldr r3, [r7, #4]
|
|
8007da4: 681b ldr r3, [r3, #0]
|
|
8007da6: 681b ldr r3, [r3, #0]
|
|
8007da8: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
8007daa: 687b ldr r3, [r7, #4]
|
|
8007dac: 681b ldr r3, [r3, #0]
|
|
8007dae: 681a ldr r2, [r3, #0]
|
|
8007db0: 687b ldr r3, [r7, #4]
|
|
8007db2: 681b ldr r3, [r3, #0]
|
|
8007db4: f022 0201 bic.w r2, r2, #1
|
|
8007db8: 601a str r2, [r3, #0]
|
|
|
|
/* Disable FIFO mode */
|
|
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
|
|
8007dba: 68fb ldr r3, [r7, #12]
|
|
8007dbc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
|
|
8007dc0: 60fb str r3, [r7, #12]
|
|
huart->FifoMode = UART_FIFOMODE_DISABLE;
|
|
8007dc2: 687b ldr r3, [r7, #4]
|
|
8007dc4: 2200 movs r2, #0
|
|
8007dc6: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8007dc8: 687b ldr r3, [r7, #4]
|
|
8007dca: 681b ldr r3, [r3, #0]
|
|
8007dcc: 68fa ldr r2, [r7, #12]
|
|
8007dce: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8007dd0: 687b ldr r3, [r7, #4]
|
|
8007dd2: 2220 movs r2, #32
|
|
8007dd4: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8007dd8: 687b ldr r3, [r7, #4]
|
|
8007dda: 2200 movs r2, #0
|
|
8007ddc: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
8007de0: 2300 movs r3, #0
|
|
}
|
|
8007de2: 4618 mov r0, r3
|
|
8007de4: 3714 adds r7, #20
|
|
8007de6: 46bd mov sp, r7
|
|
8007de8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007dec: 4770 bx lr
|
|
|
|
08007dee <HAL_UARTEx_SetTxFifoThreshold>:
|
|
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
|
|
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
|
{
|
|
8007dee: b580 push {r7, lr}
|
|
8007df0: b084 sub sp, #16
|
|
8007df2: af00 add r7, sp, #0
|
|
8007df4: 6078 str r0, [r7, #4]
|
|
8007df6: 6039 str r1, [r7, #0]
|
|
/* Check parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8007df8: 687b ldr r3, [r7, #4]
|
|
8007dfa: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8007dfe: 2b01 cmp r3, #1
|
|
8007e00: d101 bne.n 8007e06 <HAL_UARTEx_SetTxFifoThreshold+0x18>
|
|
8007e02: 2302 movs r3, #2
|
|
8007e04: e02d b.n 8007e62 <HAL_UARTEx_SetTxFifoThreshold+0x74>
|
|
8007e06: 687b ldr r3, [r7, #4]
|
|
8007e08: 2201 movs r2, #1
|
|
8007e0a: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8007e0e: 687b ldr r3, [r7, #4]
|
|
8007e10: 2224 movs r2, #36 @ 0x24
|
|
8007e12: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
8007e16: 687b ldr r3, [r7, #4]
|
|
8007e18: 681b ldr r3, [r3, #0]
|
|
8007e1a: 681b ldr r3, [r3, #0]
|
|
8007e1c: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
8007e1e: 687b ldr r3, [r7, #4]
|
|
8007e20: 681b ldr r3, [r3, #0]
|
|
8007e22: 681a ldr r2, [r3, #0]
|
|
8007e24: 687b ldr r3, [r7, #4]
|
|
8007e26: 681b ldr r3, [r3, #0]
|
|
8007e28: f022 0201 bic.w r2, r2, #1
|
|
8007e2c: 601a str r2, [r3, #0]
|
|
|
|
/* Update TX threshold configuration */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
|
|
8007e2e: 687b ldr r3, [r7, #4]
|
|
8007e30: 681b ldr r3, [r3, #0]
|
|
8007e32: 689b ldr r3, [r3, #8]
|
|
8007e34: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
|
|
8007e38: 687b ldr r3, [r7, #4]
|
|
8007e3a: 681b ldr r3, [r3, #0]
|
|
8007e3c: 683a ldr r2, [r7, #0]
|
|
8007e3e: 430a orrs r2, r1
|
|
8007e40: 609a str r2, [r3, #8]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
8007e42: 6878 ldr r0, [r7, #4]
|
|
8007e44: f000 f850 bl 8007ee8 <UARTEx_SetNbDataToProcess>
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8007e48: 687b ldr r3, [r7, #4]
|
|
8007e4a: 681b ldr r3, [r3, #0]
|
|
8007e4c: 68fa ldr r2, [r7, #12]
|
|
8007e4e: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8007e50: 687b ldr r3, [r7, #4]
|
|
8007e52: 2220 movs r2, #32
|
|
8007e54: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8007e58: 687b ldr r3, [r7, #4]
|
|
8007e5a: 2200 movs r2, #0
|
|
8007e5c: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
8007e60: 2300 movs r3, #0
|
|
}
|
|
8007e62: 4618 mov r0, r3
|
|
8007e64: 3710 adds r7, #16
|
|
8007e66: 46bd mov sp, r7
|
|
8007e68: bd80 pop {r7, pc}
|
|
|
|
08007e6a <HAL_UARTEx_SetRxFifoThreshold>:
|
|
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
|
|
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
|
|
{
|
|
8007e6a: b580 push {r7, lr}
|
|
8007e6c: b084 sub sp, #16
|
|
8007e6e: af00 add r7, sp, #0
|
|
8007e70: 6078 str r0, [r7, #4]
|
|
8007e72: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(huart);
|
|
8007e74: 687b ldr r3, [r7, #4]
|
|
8007e76: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
|
|
8007e7a: 2b01 cmp r3, #1
|
|
8007e7c: d101 bne.n 8007e82 <HAL_UARTEx_SetRxFifoThreshold+0x18>
|
|
8007e7e: 2302 movs r3, #2
|
|
8007e80: e02d b.n 8007ede <HAL_UARTEx_SetRxFifoThreshold+0x74>
|
|
8007e82: 687b ldr r3, [r7, #4]
|
|
8007e84: 2201 movs r2, #1
|
|
8007e86: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8007e8a: 687b ldr r3, [r7, #4]
|
|
8007e8c: 2224 movs r2, #36 @ 0x24
|
|
8007e8e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Save actual UART configuration */
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
8007e92: 687b ldr r3, [r7, #4]
|
|
8007e94: 681b ldr r3, [r3, #0]
|
|
8007e96: 681b ldr r3, [r3, #0]
|
|
8007e98: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable UART */
|
|
__HAL_UART_DISABLE(huart);
|
|
8007e9a: 687b ldr r3, [r7, #4]
|
|
8007e9c: 681b ldr r3, [r3, #0]
|
|
8007e9e: 681a ldr r2, [r3, #0]
|
|
8007ea0: 687b ldr r3, [r7, #4]
|
|
8007ea2: 681b ldr r3, [r3, #0]
|
|
8007ea4: f022 0201 bic.w r2, r2, #1
|
|
8007ea8: 601a str r2, [r3, #0]
|
|
|
|
/* Update RX threshold configuration */
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
|
|
8007eaa: 687b ldr r3, [r7, #4]
|
|
8007eac: 681b ldr r3, [r3, #0]
|
|
8007eae: 689b ldr r3, [r3, #8]
|
|
8007eb0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
|
|
8007eb4: 687b ldr r3, [r7, #4]
|
|
8007eb6: 681b ldr r3, [r3, #0]
|
|
8007eb8: 683a ldr r2, [r7, #0]
|
|
8007eba: 430a orrs r2, r1
|
|
8007ebc: 609a str r2, [r3, #8]
|
|
|
|
/* Determine the number of data to process during RX/TX ISR execution */
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
8007ebe: 6878 ldr r0, [r7, #4]
|
|
8007ec0: f000 f812 bl 8007ee8 <UARTEx_SetNbDataToProcess>
|
|
|
|
/* Restore UART configuration */
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
8007ec4: 687b ldr r3, [r7, #4]
|
|
8007ec6: 681b ldr r3, [r3, #0]
|
|
8007ec8: 68fa ldr r2, [r7, #12]
|
|
8007eca: 601a str r2, [r3, #0]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8007ecc: 687b ldr r3, [r7, #4]
|
|
8007ece: 2220 movs r2, #32
|
|
8007ed0: f8c3 2088 str.w r2, [r3, #136] @ 0x88
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8007ed4: 687b ldr r3, [r7, #4]
|
|
8007ed6: 2200 movs r2, #0
|
|
8007ed8: f883 2084 strb.w r2, [r3, #132] @ 0x84
|
|
|
|
return HAL_OK;
|
|
8007edc: 2300 movs r3, #0
|
|
}
|
|
8007ede: 4618 mov r0, r3
|
|
8007ee0: 3710 adds r7, #16
|
|
8007ee2: 46bd mov sp, r7
|
|
8007ee4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007ee8 <UARTEx_SetNbDataToProcess>:
|
|
* the UART configuration registers.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
|
|
{
|
|
8007ee8: b480 push {r7}
|
|
8007eea: b085 sub sp, #20
|
|
8007eec: af00 add r7, sp, #0
|
|
8007eee: 6078 str r0, [r7, #4]
|
|
uint8_t rx_fifo_threshold;
|
|
uint8_t tx_fifo_threshold;
|
|
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
|
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
|
|
|
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
|
8007ef0: 687b ldr r3, [r7, #4]
|
|
8007ef2: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8007ef4: 2b00 cmp r3, #0
|
|
8007ef6: d108 bne.n 8007f0a <UARTEx_SetNbDataToProcess+0x22>
|
|
{
|
|
huart->NbTxDataToProcess = 1U;
|
|
8007ef8: 687b ldr r3, [r7, #4]
|
|
8007efa: 2201 movs r2, #1
|
|
8007efc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = 1U;
|
|
8007f00: 687b ldr r3, [r7, #4]
|
|
8007f02: 2201 movs r2, #1
|
|
8007f04: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
}
|
|
}
|
|
8007f08: e031 b.n 8007f6e <UARTEx_SetNbDataToProcess+0x86>
|
|
rx_fifo_depth = RX_FIFO_DEPTH;
|
|
8007f0a: 2308 movs r3, #8
|
|
8007f0c: 73fb strb r3, [r7, #15]
|
|
tx_fifo_depth = TX_FIFO_DEPTH;
|
|
8007f0e: 2308 movs r3, #8
|
|
8007f10: 73bb strb r3, [r7, #14]
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
8007f12: 687b ldr r3, [r7, #4]
|
|
8007f14: 681b ldr r3, [r3, #0]
|
|
8007f16: 689b ldr r3, [r3, #8]
|
|
8007f18: 0e5b lsrs r3, r3, #25
|
|
8007f1a: b2db uxtb r3, r3
|
|
8007f1c: f003 0307 and.w r3, r3, #7
|
|
8007f20: 737b strb r3, [r7, #13]
|
|
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
|
8007f22: 687b ldr r3, [r7, #4]
|
|
8007f24: 681b ldr r3, [r3, #0]
|
|
8007f26: 689b ldr r3, [r3, #8]
|
|
8007f28: 0f5b lsrs r3, r3, #29
|
|
8007f2a: b2db uxtb r3, r3
|
|
8007f2c: f003 0307 and.w r3, r3, #7
|
|
8007f30: 733b strb r3, [r7, #12]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8007f32: 7bbb ldrb r3, [r7, #14]
|
|
8007f34: 7b3a ldrb r2, [r7, #12]
|
|
8007f36: 4911 ldr r1, [pc, #68] @ (8007f7c <UARTEx_SetNbDataToProcess+0x94>)
|
|
8007f38: 5c8a ldrb r2, [r1, r2]
|
|
8007f3a: fb02 f303 mul.w r3, r2, r3
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
8007f3e: 7b3a ldrb r2, [r7, #12]
|
|
8007f40: 490f ldr r1, [pc, #60] @ (8007f80 <UARTEx_SetNbDataToProcess+0x98>)
|
|
8007f42: 5c8a ldrb r2, [r1, r2]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8007f44: fb93 f3f2 sdiv r3, r3, r2
|
|
8007f48: b29a uxth r2, r3
|
|
8007f4a: 687b ldr r3, [r7, #4]
|
|
8007f4c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
8007f50: 7bfb ldrb r3, [r7, #15]
|
|
8007f52: 7b7a ldrb r2, [r7, #13]
|
|
8007f54: 4909 ldr r1, [pc, #36] @ (8007f7c <UARTEx_SetNbDataToProcess+0x94>)
|
|
8007f56: 5c8a ldrb r2, [r1, r2]
|
|
8007f58: fb02 f303 mul.w r3, r2, r3
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
8007f5c: 7b7a ldrb r2, [r7, #13]
|
|
8007f5e: 4908 ldr r1, [pc, #32] @ (8007f80 <UARTEx_SetNbDataToProcess+0x98>)
|
|
8007f60: 5c8a ldrb r2, [r1, r2]
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
8007f62: fb93 f3f2 sdiv r3, r3, r2
|
|
8007f66: b29a uxth r2, r3
|
|
8007f68: 687b ldr r3, [r7, #4]
|
|
8007f6a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
|
|
}
|
|
8007f6e: bf00 nop
|
|
8007f70: 3714 adds r7, #20
|
|
8007f72: 46bd mov sp, r7
|
|
8007f74: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007f78: 4770 bx lr
|
|
8007f7a: bf00 nop
|
|
8007f7c: 08008058 .word 0x08008058
|
|
8007f80: 08008060 .word 0x08008060
|
|
|
|
08007f84 <memset>:
|
|
8007f84: 4402 add r2, r0
|
|
8007f86: 4603 mov r3, r0
|
|
8007f88: 4293 cmp r3, r2
|
|
8007f8a: d100 bne.n 8007f8e <memset+0xa>
|
|
8007f8c: 4770 bx lr
|
|
8007f8e: f803 1b01 strb.w r1, [r3], #1
|
|
8007f92: e7f9 b.n 8007f88 <memset+0x4>
|
|
|
|
08007f94 <__libc_init_array>:
|
|
8007f94: b570 push {r4, r5, r6, lr}
|
|
8007f96: 4d0d ldr r5, [pc, #52] @ (8007fcc <__libc_init_array+0x38>)
|
|
8007f98: 4c0d ldr r4, [pc, #52] @ (8007fd0 <__libc_init_array+0x3c>)
|
|
8007f9a: 1b64 subs r4, r4, r5
|
|
8007f9c: 10a4 asrs r4, r4, #2
|
|
8007f9e: 2600 movs r6, #0
|
|
8007fa0: 42a6 cmp r6, r4
|
|
8007fa2: d109 bne.n 8007fb8 <__libc_init_array+0x24>
|
|
8007fa4: 4d0b ldr r5, [pc, #44] @ (8007fd4 <__libc_init_array+0x40>)
|
|
8007fa6: 4c0c ldr r4, [pc, #48] @ (8007fd8 <__libc_init_array+0x44>)
|
|
8007fa8: f000 f818 bl 8007fdc <_init>
|
|
8007fac: 1b64 subs r4, r4, r5
|
|
8007fae: 10a4 asrs r4, r4, #2
|
|
8007fb0: 2600 movs r6, #0
|
|
8007fb2: 42a6 cmp r6, r4
|
|
8007fb4: d105 bne.n 8007fc2 <__libc_init_array+0x2e>
|
|
8007fb6: bd70 pop {r4, r5, r6, pc}
|
|
8007fb8: f855 3b04 ldr.w r3, [r5], #4
|
|
8007fbc: 4798 blx r3
|
|
8007fbe: 3601 adds r6, #1
|
|
8007fc0: e7ee b.n 8007fa0 <__libc_init_array+0xc>
|
|
8007fc2: f855 3b04 ldr.w r3, [r5], #4
|
|
8007fc6: 4798 blx r3
|
|
8007fc8: 3601 adds r6, #1
|
|
8007fca: e7f2 b.n 8007fb2 <__libc_init_array+0x1e>
|
|
8007fcc: 08008070 .word 0x08008070
|
|
8007fd0: 08008070 .word 0x08008070
|
|
8007fd4: 08008070 .word 0x08008070
|
|
8007fd8: 08008074 .word 0x08008074
|
|
|
|
08007fdc <_init>:
|
|
8007fdc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8007fde: bf00 nop
|
|
8007fe0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8007fe2: bc08 pop {r3}
|
|
8007fe4: 469e mov lr, r3
|
|
8007fe6: 4770 bx lr
|
|
|
|
08007fe8 <_fini>:
|
|
8007fe8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8007fea: bf00 nop
|
|
8007fec: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8007fee: bc08 pop {r3}
|
|
8007ff0: 469e mov lr, r3
|
|
8007ff2: 4770 bx lr
|