POWER_SWITCH.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00006b5c 080001d8 080001d8 000011d8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000040 08006d34 08006d34 00007d34 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08006d74 08006d74 0000800c 2**0 CONTENTS, READONLY 4 .ARM 00000008 08006d74 08006d74 00007d74 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08006d7c 08006d7c 0000800c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08006d7c 08006d7c 00007d7c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08006d80 08006d80 00007d80 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 08006d84 00008000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000238 2000000c 08006d90 0000800c 2**2 ALLOC 10 ._user_heap_stack 00000604 20000244 08006d90 00008244 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 0000800c 2**0 CONTENTS, READONLY 12 .debug_info 00016fd6 00000000 00000000 0000803c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002a58 00000000 00000000 0001f012 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00001490 00000000 00000000 00021a70 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00001012 00000000 00000000 00022f00 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 0001f9ca 00000000 00000000 00023f12 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 0001664c 00000000 00000000 000438dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 000d7e8e 00000000 00000000 00059f28 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 00131db6 2**0 CONTENTS, READONLY 20 .debug_frame 0000595c 00000000 00000000 00131dfc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000006d 00000000 00000000 00137758 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001d8 <__do_global_dtors_aux>: 80001d8: b510 push {r4, lr} 80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>) 80001dc: 7823 ldrb r3, [r4, #0] 80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16> 80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>) 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12> 80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>) 80001e6: f3af 8000 nop.w 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} 80001f0: 2000000c .word 0x2000000c 80001f4: 00000000 .word 0x00000000 80001f8: 08006d1c .word 0x08006d1c 080001fc : 80001fc: b508 push {r3, lr} 80001fe: 4b03 ldr r3, [pc, #12] @ (800020c ) 8000200: b11b cbz r3, 800020a 8000202: 4903 ldr r1, [pc, #12] @ (8000210 ) 8000204: 4803 ldr r0, [pc, #12] @ (8000214 ) 8000206: f3af 8000 nop.w 800020a: bd08 pop {r3, pc} 800020c: 00000000 .word 0x00000000 8000210: 20000010 .word 0x20000010 8000214: 08006d1c .word 0x08006d1c 08000218 <__aeabi_uldivmod>: 8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18> 800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18> 800021c: 2900 cmp r1, #0 800021e: bf08 it eq 8000220: 2800 cmpeq r0, #0 8000222: bf1c itt ne 8000224: f04f 31ff movne.w r1, #4294967295 8000228: f04f 30ff movne.w r0, #4294967295 800022c: f000 b988 b.w 8000540 <__aeabi_idiv0> 8000230: f1ad 0c08 sub.w ip, sp, #8 8000234: e96d ce04 strd ip, lr, [sp, #-16]! 8000238: f000 f806 bl 8000248 <__udivmoddi4> 800023c: f8dd e004 ldr.w lr, [sp, #4] 8000240: e9dd 2302 ldrd r2, r3, [sp, #8] 8000244: b004 add sp, #16 8000246: 4770 bx lr 08000248 <__udivmoddi4>: 8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800024c: 9d08 ldr r5, [sp, #32] 800024e: 468e mov lr, r1 8000250: 4604 mov r4, r0 8000252: 4688 mov r8, r1 8000254: 2b00 cmp r3, #0 8000256: d14a bne.n 80002ee <__udivmoddi4+0xa6> 8000258: 428a cmp r2, r1 800025a: 4617 mov r7, r2 800025c: d962 bls.n 8000324 <__udivmoddi4+0xdc> 800025e: fab2 f682 clz r6, r2 8000262: b14e cbz r6, 8000278 <__udivmoddi4+0x30> 8000264: f1c6 0320 rsb r3, r6, #32 8000268: fa01 f806 lsl.w r8, r1, r6 800026c: fa20 f303 lsr.w r3, r0, r3 8000270: 40b7 lsls r7, r6 8000272: ea43 0808 orr.w r8, r3, r8 8000276: 40b4 lsls r4, r6 8000278: ea4f 4e17 mov.w lr, r7, lsr #16 800027c: fa1f fc87 uxth.w ip, r7 8000280: fbb8 f1fe udiv r1, r8, lr 8000284: 0c23 lsrs r3, r4, #16 8000286: fb0e 8811 mls r8, lr, r1, r8 800028a: ea43 4308 orr.w r3, r3, r8, lsl #16 800028e: fb01 f20c mul.w r2, r1, ip 8000292: 429a cmp r2, r3 8000294: d909 bls.n 80002aa <__udivmoddi4+0x62> 8000296: 18fb adds r3, r7, r3 8000298: f101 30ff add.w r0, r1, #4294967295 800029c: f080 80ea bcs.w 8000474 <__udivmoddi4+0x22c> 80002a0: 429a cmp r2, r3 80002a2: f240 80e7 bls.w 8000474 <__udivmoddi4+0x22c> 80002a6: 3902 subs r1, #2 80002a8: 443b add r3, r7 80002aa: 1a9a subs r2, r3, r2 80002ac: b2a3 uxth r3, r4 80002ae: fbb2 f0fe udiv r0, r2, lr 80002b2: fb0e 2210 mls r2, lr, r0, r2 80002b6: ea43 4302 orr.w r3, r3, r2, lsl #16 80002ba: fb00 fc0c mul.w ip, r0, ip 80002be: 459c cmp ip, r3 80002c0: d909 bls.n 80002d6 <__udivmoddi4+0x8e> 80002c2: 18fb adds r3, r7, r3 80002c4: f100 32ff add.w r2, r0, #4294967295 80002c8: f080 80d6 bcs.w 8000478 <__udivmoddi4+0x230> 80002cc: 459c cmp ip, r3 80002ce: f240 80d3 bls.w 8000478 <__udivmoddi4+0x230> 80002d2: 443b add r3, r7 80002d4: 3802 subs r0, #2 80002d6: ea40 4001 orr.w r0, r0, r1, lsl #16 80002da: eba3 030c sub.w r3, r3, ip 80002de: 2100 movs r1, #0 80002e0: b11d cbz r5, 80002ea <__udivmoddi4+0xa2> 80002e2: 40f3 lsrs r3, r6 80002e4: 2200 movs r2, #0 80002e6: e9c5 3200 strd r3, r2, [r5] 80002ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002ee: 428b cmp r3, r1 80002f0: d905 bls.n 80002fe <__udivmoddi4+0xb6> 80002f2: b10d cbz r5, 80002f8 <__udivmoddi4+0xb0> 80002f4: e9c5 0100 strd r0, r1, [r5] 80002f8: 2100 movs r1, #0 80002fa: 4608 mov r0, r1 80002fc: e7f5 b.n 80002ea <__udivmoddi4+0xa2> 80002fe: fab3 f183 clz r1, r3 8000302: 2900 cmp r1, #0 8000304: d146 bne.n 8000394 <__udivmoddi4+0x14c> 8000306: 4573 cmp r3, lr 8000308: d302 bcc.n 8000310 <__udivmoddi4+0xc8> 800030a: 4282 cmp r2, r0 800030c: f200 8105 bhi.w 800051a <__udivmoddi4+0x2d2> 8000310: 1a84 subs r4, r0, r2 8000312: eb6e 0203 sbc.w r2, lr, r3 8000316: 2001 movs r0, #1 8000318: 4690 mov r8, r2 800031a: 2d00 cmp r5, #0 800031c: d0e5 beq.n 80002ea <__udivmoddi4+0xa2> 800031e: e9c5 4800 strd r4, r8, [r5] 8000322: e7e2 b.n 80002ea <__udivmoddi4+0xa2> 8000324: 2a00 cmp r2, #0 8000326: f000 8090 beq.w 800044a <__udivmoddi4+0x202> 800032a: fab2 f682 clz r6, r2 800032e: 2e00 cmp r6, #0 8000330: f040 80a4 bne.w 800047c <__udivmoddi4+0x234> 8000334: 1a8a subs r2, r1, r2 8000336: 0c03 lsrs r3, r0, #16 8000338: ea4f 4e17 mov.w lr, r7, lsr #16 800033c: b280 uxth r0, r0 800033e: b2bc uxth r4, r7 8000340: 2101 movs r1, #1 8000342: fbb2 fcfe udiv ip, r2, lr 8000346: fb0e 221c mls r2, lr, ip, r2 800034a: ea43 4302 orr.w r3, r3, r2, lsl #16 800034e: fb04 f20c mul.w r2, r4, ip 8000352: 429a cmp r2, r3 8000354: d907 bls.n 8000366 <__udivmoddi4+0x11e> 8000356: 18fb adds r3, r7, r3 8000358: f10c 38ff add.w r8, ip, #4294967295 800035c: d202 bcs.n 8000364 <__udivmoddi4+0x11c> 800035e: 429a cmp r2, r3 8000360: f200 80e0 bhi.w 8000524 <__udivmoddi4+0x2dc> 8000364: 46c4 mov ip, r8 8000366: 1a9b subs r3, r3, r2 8000368: fbb3 f2fe udiv r2, r3, lr 800036c: fb0e 3312 mls r3, lr, r2, r3 8000370: ea40 4303 orr.w r3, r0, r3, lsl #16 8000374: fb02 f404 mul.w r4, r2, r4 8000378: 429c cmp r4, r3 800037a: d907 bls.n 800038c <__udivmoddi4+0x144> 800037c: 18fb adds r3, r7, r3 800037e: f102 30ff add.w r0, r2, #4294967295 8000382: d202 bcs.n 800038a <__udivmoddi4+0x142> 8000384: 429c cmp r4, r3 8000386: f200 80ca bhi.w 800051e <__udivmoddi4+0x2d6> 800038a: 4602 mov r2, r0 800038c: 1b1b subs r3, r3, r4 800038e: ea42 400c orr.w r0, r2, ip, lsl #16 8000392: e7a5 b.n 80002e0 <__udivmoddi4+0x98> 8000394: f1c1 0620 rsb r6, r1, #32 8000398: 408b lsls r3, r1 800039a: fa22 f706 lsr.w r7, r2, r6 800039e: 431f orrs r7, r3 80003a0: fa0e f401 lsl.w r4, lr, r1 80003a4: fa20 f306 lsr.w r3, r0, r6 80003a8: fa2e fe06 lsr.w lr, lr, r6 80003ac: ea4f 4917 mov.w r9, r7, lsr #16 80003b0: 4323 orrs r3, r4 80003b2: fa00 f801 lsl.w r8, r0, r1 80003b6: fa1f fc87 uxth.w ip, r7 80003ba: fbbe f0f9 udiv r0, lr, r9 80003be: 0c1c lsrs r4, r3, #16 80003c0: fb09 ee10 mls lr, r9, r0, lr 80003c4: ea44 440e orr.w r4, r4, lr, lsl #16 80003c8: fb00 fe0c mul.w lr, r0, ip 80003cc: 45a6 cmp lr, r4 80003ce: fa02 f201 lsl.w r2, r2, r1 80003d2: d909 bls.n 80003e8 <__udivmoddi4+0x1a0> 80003d4: 193c adds r4, r7, r4 80003d6: f100 3aff add.w sl, r0, #4294967295 80003da: f080 809c bcs.w 8000516 <__udivmoddi4+0x2ce> 80003de: 45a6 cmp lr, r4 80003e0: f240 8099 bls.w 8000516 <__udivmoddi4+0x2ce> 80003e4: 3802 subs r0, #2 80003e6: 443c add r4, r7 80003e8: eba4 040e sub.w r4, r4, lr 80003ec: fa1f fe83 uxth.w lr, r3 80003f0: fbb4 f3f9 udiv r3, r4, r9 80003f4: fb09 4413 mls r4, r9, r3, r4 80003f8: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003fc: fb03 fc0c mul.w ip, r3, ip 8000400: 45a4 cmp ip, r4 8000402: d908 bls.n 8000416 <__udivmoddi4+0x1ce> 8000404: 193c adds r4, r7, r4 8000406: f103 3eff add.w lr, r3, #4294967295 800040a: f080 8082 bcs.w 8000512 <__udivmoddi4+0x2ca> 800040e: 45a4 cmp ip, r4 8000410: d97f bls.n 8000512 <__udivmoddi4+0x2ca> 8000412: 3b02 subs r3, #2 8000414: 443c add r4, r7 8000416: ea43 4000 orr.w r0, r3, r0, lsl #16 800041a: eba4 040c sub.w r4, r4, ip 800041e: fba0 ec02 umull lr, ip, r0, r2 8000422: 4564 cmp r4, ip 8000424: 4673 mov r3, lr 8000426: 46e1 mov r9, ip 8000428: d362 bcc.n 80004f0 <__udivmoddi4+0x2a8> 800042a: d05f beq.n 80004ec <__udivmoddi4+0x2a4> 800042c: b15d cbz r5, 8000446 <__udivmoddi4+0x1fe> 800042e: ebb8 0203 subs.w r2, r8, r3 8000432: eb64 0409 sbc.w r4, r4, r9 8000436: fa04 f606 lsl.w r6, r4, r6 800043a: fa22 f301 lsr.w r3, r2, r1 800043e: 431e orrs r6, r3 8000440: 40cc lsrs r4, r1 8000442: e9c5 6400 strd r6, r4, [r5] 8000446: 2100 movs r1, #0 8000448: e74f b.n 80002ea <__udivmoddi4+0xa2> 800044a: fbb1 fcf2 udiv ip, r1, r2 800044e: 0c01 lsrs r1, r0, #16 8000450: ea41 410e orr.w r1, r1, lr, lsl #16 8000454: b280 uxth r0, r0 8000456: ea40 4201 orr.w r2, r0, r1, lsl #16 800045a: 463b mov r3, r7 800045c: 4638 mov r0, r7 800045e: 463c mov r4, r7 8000460: 46b8 mov r8, r7 8000462: 46be mov lr, r7 8000464: 2620 movs r6, #32 8000466: fbb1 f1f7 udiv r1, r1, r7 800046a: eba2 0208 sub.w r2, r2, r8 800046e: ea41 410c orr.w r1, r1, ip, lsl #16 8000472: e766 b.n 8000342 <__udivmoddi4+0xfa> 8000474: 4601 mov r1, r0 8000476: e718 b.n 80002aa <__udivmoddi4+0x62> 8000478: 4610 mov r0, r2 800047a: e72c b.n 80002d6 <__udivmoddi4+0x8e> 800047c: f1c6 0220 rsb r2, r6, #32 8000480: fa2e f302 lsr.w r3, lr, r2 8000484: 40b7 lsls r7, r6 8000486: 40b1 lsls r1, r6 8000488: fa20 f202 lsr.w r2, r0, r2 800048c: ea4f 4e17 mov.w lr, r7, lsr #16 8000490: 430a orrs r2, r1 8000492: fbb3 f8fe udiv r8, r3, lr 8000496: b2bc uxth r4, r7 8000498: fb0e 3318 mls r3, lr, r8, r3 800049c: 0c11 lsrs r1, r2, #16 800049e: ea41 4103 orr.w r1, r1, r3, lsl #16 80004a2: fb08 f904 mul.w r9, r8, r4 80004a6: 40b0 lsls r0, r6 80004a8: 4589 cmp r9, r1 80004aa: ea4f 4310 mov.w r3, r0, lsr #16 80004ae: b280 uxth r0, r0 80004b0: d93e bls.n 8000530 <__udivmoddi4+0x2e8> 80004b2: 1879 adds r1, r7, r1 80004b4: f108 3cff add.w ip, r8, #4294967295 80004b8: d201 bcs.n 80004be <__udivmoddi4+0x276> 80004ba: 4589 cmp r9, r1 80004bc: d81f bhi.n 80004fe <__udivmoddi4+0x2b6> 80004be: eba1 0109 sub.w r1, r1, r9 80004c2: fbb1 f9fe udiv r9, r1, lr 80004c6: fb09 f804 mul.w r8, r9, r4 80004ca: fb0e 1119 mls r1, lr, r9, r1 80004ce: b292 uxth r2, r2 80004d0: ea42 4201 orr.w r2, r2, r1, lsl #16 80004d4: 4542 cmp r2, r8 80004d6: d229 bcs.n 800052c <__udivmoddi4+0x2e4> 80004d8: 18ba adds r2, r7, r2 80004da: f109 31ff add.w r1, r9, #4294967295 80004de: d2c4 bcs.n 800046a <__udivmoddi4+0x222> 80004e0: 4542 cmp r2, r8 80004e2: d2c2 bcs.n 800046a <__udivmoddi4+0x222> 80004e4: f1a9 0102 sub.w r1, r9, #2 80004e8: 443a add r2, r7 80004ea: e7be b.n 800046a <__udivmoddi4+0x222> 80004ec: 45f0 cmp r8, lr 80004ee: d29d bcs.n 800042c <__udivmoddi4+0x1e4> 80004f0: ebbe 0302 subs.w r3, lr, r2 80004f4: eb6c 0c07 sbc.w ip, ip, r7 80004f8: 3801 subs r0, #1 80004fa: 46e1 mov r9, ip 80004fc: e796 b.n 800042c <__udivmoddi4+0x1e4> 80004fe: eba7 0909 sub.w r9, r7, r9 8000502: 4449 add r1, r9 8000504: f1a8 0c02 sub.w ip, r8, #2 8000508: fbb1 f9fe udiv r9, r1, lr 800050c: fb09 f804 mul.w r8, r9, r4 8000510: e7db b.n 80004ca <__udivmoddi4+0x282> 8000512: 4673 mov r3, lr 8000514: e77f b.n 8000416 <__udivmoddi4+0x1ce> 8000516: 4650 mov r0, sl 8000518: e766 b.n 80003e8 <__udivmoddi4+0x1a0> 800051a: 4608 mov r0, r1 800051c: e6fd b.n 800031a <__udivmoddi4+0xd2> 800051e: 443b add r3, r7 8000520: 3a02 subs r2, #2 8000522: e733 b.n 800038c <__udivmoddi4+0x144> 8000524: f1ac 0c02 sub.w ip, ip, #2 8000528: 443b add r3, r7 800052a: e71c b.n 8000366 <__udivmoddi4+0x11e> 800052c: 4649 mov r1, r9 800052e: e79c b.n 800046a <__udivmoddi4+0x222> 8000530: eba1 0109 sub.w r1, r1, r9 8000534: 46c4 mov ip, r8 8000536: fbb1 f9fe udiv r9, r1, lr 800053a: fb09 f804 mul.w r8, r9, r4 800053e: e7c4 b.n 80004ca <__udivmoddi4+0x282> 08000540 <__aeabi_idiv0>: 8000540: 4770 bx lr 8000542: bf00 nop 08000544
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000544: b580 push {r7, lr} 8000546: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000548: f000 fdfd bl 8001146 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800054c: f000 f886 bl 800065c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000550: f000 fa58 bl 8000a04 MX_USART2_UART_Init(); 8000554: f000 fa0a bl 800096c MX_ADC2_Init(); 8000558: f000 f944 bl 80007e4 MX_TIM2_Init(); 800055c: f000 f9b8 bl 80008d0 MX_ADC1_Init(); 8000560: f000 f8c8 bl 80006f4 /* USER CODE BEGIN 2 */ /*Configure GPIO pin output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8000564: 2200 movs r2, #0 8000566: f44f 7180 mov.w r1, #256 @ 0x100 800056a: 4830 ldr r0, [pc, #192] @ (800062c ) 800056c: f002 fdde bl 800312c HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); 8000570: 2200 movs r2, #0 8000572: f44f 5180 mov.w r1, #4096 @ 0x1000 8000576: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 800057a: f002 fdd7 bl 800312c /* Setup UART interrupts */ /* Make sure UART Rx counters and flags are reset */ rx_counter = 0x00; 800057e: 4b2c ldr r3, [pc, #176] @ (8000630 ) 8000580: 2200 movs r2, #0 8000582: 701a strb r2, [r3, #0] rx_len = 0x00; 8000584: 4b2b ldr r3, [pc, #172] @ (8000634 ) 8000586: 2200 movs r2, #0 8000588: 701a strb r2, [r3, #0] rx_len_counter = 0x00; 800058a: 4b2b ldr r3, [pc, #172] @ (8000638 ) 800058c: 2200 movs r2, #0 800058e: 701a strb r2, [r3, #0] adc_task_flag = 0x00; 8000590: 4b2a ldr r3, [pc, #168] @ (800063c ) 8000592: 2200 movs r2, #0 8000594: 701a strb r2, [r3, #0] uart_tx_flag = 0x00; 8000596: 4b2a ldr r3, [pc, #168] @ (8000640 ) 8000598: 2200 movs r2, #0 800059a: 701a strb r2, [r3, #0] HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1); 800059c: 2201 movs r2, #1 800059e: 4929 ldr r1, [pc, #164] @ (8000644 ) 80005a0: 4829 ldr r0, [pc, #164] @ (8000648 ) 80005a2: f004 fb5d bl 8004c60 /* Get real VDDA value */ vdd_ref = get_actual_vdda(&hadc1); 80005a6: 4829 ldr r0, [pc, #164] @ (800064c ) 80005a8: f000 fa84 bl 8000ab4 80005ac: 4603 mov r3, r0 80005ae: 4a28 ldr r2, [pc, #160] @ (8000650 ) 80005b0: 6013 str r3, [r2, #0] tx_buffer[0] = vdd_ref >> 24; 80005b2: 4b27 ldr r3, [pc, #156] @ (8000650 ) 80005b4: 681b ldr r3, [r3, #0] 80005b6: 0e1b lsrs r3, r3, #24 80005b8: b2da uxtb r2, r3 80005ba: 4b26 ldr r3, [pc, #152] @ (8000654 ) 80005bc: 701a strb r2, [r3, #0] tx_buffer[1] = vdd_ref >> 16; 80005be: 4b24 ldr r3, [pc, #144] @ (8000650 ) 80005c0: 681b ldr r3, [r3, #0] 80005c2: 0c1b lsrs r3, r3, #16 80005c4: b2da uxtb r2, r3 80005c6: 4b23 ldr r3, [pc, #140] @ (8000654 ) 80005c8: 705a strb r2, [r3, #1] tx_buffer[2] = vdd_ref >> 8; 80005ca: 4b21 ldr r3, [pc, #132] @ (8000650 ) 80005cc: 681b ldr r3, [r3, #0] 80005ce: 0a1b lsrs r3, r3, #8 80005d0: b2da uxtb r2, r3 80005d2: 4b20 ldr r3, [pc, #128] @ (8000654 ) 80005d4: 709a strb r2, [r3, #2] tx_buffer[3] = vdd_ref; 80005d6: 4b1e ldr r3, [pc, #120] @ (8000650 ) 80005d8: 681b ldr r3, [r3, #0] 80005da: b2da uxtb r2, r3 80005dc: 4b1d ldr r3, [pc, #116] @ (8000654 ) 80005de: 70da strb r2, [r3, #3] tx_len = 4; 80005e0: 4b1d ldr r3, [pc, #116] @ (8000658 ) 80005e2: 2204 movs r2, #4 80005e4: 701a strb r2, [r3, #0] HAL_UART_Transmit(&huart2, tx_buffer, tx_len, HAL_MAX_DELAY); 80005e6: 4b1c ldr r3, [pc, #112] @ (8000658 ) 80005e8: 781b ldrb r3, [r3, #0] 80005ea: 461a mov r2, r3 80005ec: f04f 33ff mov.w r3, #4294967295 80005f0: 4918 ldr r1, [pc, #96] @ (8000654 ) 80005f2: 4815 ldr r0, [pc, #84] @ (8000648 ) 80005f4: f004 faa6 bl 8004b44 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { if (adc_task_flag == 0xff) 80005f8: 4b10 ldr r3, [pc, #64] @ (800063c ) 80005fa: 781b ldrb r3, [r3, #0] 80005fc: 2bff cmp r3, #255 @ 0xff 80005fe: d104 bne.n 800060a { adc_task_flag = 0x00; 8000600: 4b0e ldr r3, [pc, #56] @ (800063c ) 8000602: 2200 movs r2, #0 8000604: 701a strb r2, [r3, #0] adc_task(); 8000606: f000 fa83 bl 8000b10 } if (uart_tx_flag == 0xff) 800060a: 4b0d ldr r3, [pc, #52] @ (8000640 ) 800060c: 781b ldrb r3, [r3, #0] 800060e: 2bff cmp r3, #255 @ 0xff 8000610: d1f2 bne.n 80005f8 { uart_tx_flag = 0x00; 8000612: 4b0b ldr r3, [pc, #44] @ (8000640 ) 8000614: 2200 movs r2, #0 8000616: 701a strb r2, [r3, #0] HAL_UART_Transmit(&huart2, tx_buffer, tx_len, HAL_MAX_DELAY); 8000618: 4b0f ldr r3, [pc, #60] @ (8000658 ) 800061a: 781b ldrb r3, [r3, #0] 800061c: 461a mov r2, r3 800061e: f04f 33ff mov.w r3, #4294967295 8000622: 490c ldr r1, [pc, #48] @ (8000654 ) 8000624: 4808 ldr r0, [pc, #32] @ (8000648 ) 8000626: f004 fa8d bl 8004b44 if (adc_task_flag == 0xff) 800062a: e7e5 b.n 80005f8 800062c: 48000400 .word 0x48000400 8000630: 20000225 .word 0x20000225 8000634: 20000226 .word 0x20000226 8000638: 20000227 .word 0x20000227 800063c: 20000230 .word 0x20000230 8000640: 20000231 .word 0x20000231 8000644: 200001e0 .word 0x200001e0 8000648: 2000014c .word 0x2000014c 800064c: 20000028 .word 0x20000028 8000650: 20000238 .word 0x20000238 8000654: 20000204 .word 0x20000204 8000658: 20000224 .word 0x20000224 0800065c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800065c: b580 push {r7, lr} 800065e: b094 sub sp, #80 @ 0x50 8000660: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000662: f107 0318 add.w r3, r7, #24 8000666: 2238 movs r2, #56 @ 0x38 8000668: 2100 movs r1, #0 800066a: 4618 mov r0, r3 800066c: f006 fb2a bl 8006cc4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000670: 1d3b adds r3, r7, #4 8000672: 2200 movs r2, #0 8000674: 601a str r2, [r3, #0] 8000676: 605a str r2, [r3, #4] 8000678: 609a str r2, [r3, #8] 800067a: 60da str r2, [r3, #12] 800067c: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 800067e: f44f 7000 mov.w r0, #512 @ 0x200 8000682: f002 fd6b bl 800315c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8000686: 2302 movs r3, #2 8000688: 61bb str r3, [r7, #24] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 800068a: f44f 7380 mov.w r3, #256 @ 0x100 800068e: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000690: 2340 movs r3, #64 @ 0x40 8000692: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000694: 2302 movs r3, #2 8000696: 637b str r3, [r7, #52] @ 0x34 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 8000698: 2302 movs r3, #2 800069a: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; 800069c: 2301 movs r3, #1 800069e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLN = 16; 80006a0: 2310 movs r3, #16 80006a2: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80006a4: 2302 movs r3, #2 80006a6: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; 80006a8: 2302 movs r3, #2 80006aa: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; 80006ac: 2302 movs r3, #2 80006ae: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80006b0: f107 0318 add.w r3, r7, #24 80006b4: 4618 mov r0, r3 80006b6: f002 fe05 bl 80032c4 80006ba: 4603 mov r3, r0 80006bc: 2b00 cmp r3, #0 80006be: d001 beq.n 80006c4 { Error_Handler(); 80006c0: f000 fb88 bl 8000dd4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80006c4: 230f movs r3, #15 80006c6: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80006c8: 2303 movs r3, #3 80006ca: 60bb str r3, [r7, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80006cc: 2300 movs r3, #0 80006ce: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 80006d0: 2300 movs r3, #0 80006d2: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 80006d4: 2300 movs r3, #0 80006d6: 617b str r3, [r7, #20] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) 80006d8: 1d3b adds r3, r7, #4 80006da: 2104 movs r1, #4 80006dc: 4618 mov r0, r3 80006de: f003 f903 bl 80038e8 80006e2: 4603 mov r3, r0 80006e4: 2b00 cmp r3, #0 80006e6: d001 beq.n 80006ec { Error_Handler(); 80006e8: f000 fb74 bl 8000dd4 } } 80006ec: bf00 nop 80006ee: 3750 adds r7, #80 @ 0x50 80006f0: 46bd mov sp, r7 80006f2: bd80 pop {r7, pc} 080006f4 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 80006f4: b580 push {r7, lr} 80006f6: b08c sub sp, #48 @ 0x30 80006f8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 80006fa: f107 0324 add.w r3, r7, #36 @ 0x24 80006fe: 2200 movs r2, #0 8000700: 601a str r2, [r3, #0] 8000702: 605a str r2, [r3, #4] 8000704: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 8000706: 1d3b adds r3, r7, #4 8000708: 2220 movs r2, #32 800070a: 2100 movs r1, #0 800070c: 4618 mov r0, r3 800070e: f006 fad9 bl 8006cc4 /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000712: 4b32 ldr r3, [pc, #200] @ (80007dc ) 8000714: f04f 42a0 mov.w r2, #1342177280 @ 0x50000000 8000718: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV16; 800071a: 4b30 ldr r3, [pc, #192] @ (80007dc ) 800071c: f44f 12e0 mov.w r2, #1835008 @ 0x1c0000 8000720: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_12B; 8000722: 4b2e ldr r3, [pc, #184] @ (80007dc ) 8000724: 2200 movs r2, #0 8000726: 609a str r2, [r3, #8] hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; 8000728: 4b2c ldr r3, [pc, #176] @ (80007dc ) 800072a: 2200 movs r2, #0 800072c: 60da str r2, [r3, #12] hadc1.Init.GainCompensation = 0; 800072e: 4b2b ldr r3, [pc, #172] @ (80007dc ) 8000730: 2200 movs r2, #0 8000732: 611a str r2, [r3, #16] hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 8000734: 4b29 ldr r3, [pc, #164] @ (80007dc ) 8000736: 2200 movs r2, #0 8000738: 615a str r2, [r3, #20] hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 800073a: 4b28 ldr r3, [pc, #160] @ (80007dc ) 800073c: 2204 movs r2, #4 800073e: 619a str r2, [r3, #24] hadc1.Init.LowPowerAutoWait = DISABLE; 8000740: 4b26 ldr r3, [pc, #152] @ (80007dc ) 8000742: 2200 movs r2, #0 8000744: 771a strb r2, [r3, #28] hadc1.Init.ContinuousConvMode = DISABLE; 8000746: 4b25 ldr r3, [pc, #148] @ (80007dc ) 8000748: 2200 movs r2, #0 800074a: 775a strb r2, [r3, #29] hadc1.Init.NbrOfConversion = 1; 800074c: 4b23 ldr r3, [pc, #140] @ (80007dc ) 800074e: 2201 movs r2, #1 8000750: 621a str r2, [r3, #32] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000752: 4b22 ldr r3, [pc, #136] @ (80007dc ) 8000754: 2200 movs r2, #0 8000756: f883 2024 strb.w r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 800075a: 4b20 ldr r3, [pc, #128] @ (80007dc ) 800075c: 2200 movs r2, #0 800075e: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 8000760: 4b1e ldr r3, [pc, #120] @ (80007dc ) 8000762: 2200 movs r2, #0 8000764: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.DMAContinuousRequests = DISABLE; 8000766: 4b1d ldr r3, [pc, #116] @ (80007dc ) 8000768: 2200 movs r2, #0 800076a: f883 2038 strb.w r2, [r3, #56] @ 0x38 hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 800076e: 4b1b ldr r3, [pc, #108] @ (80007dc ) 8000770: 2200 movs r2, #0 8000772: 63da str r2, [r3, #60] @ 0x3c hadc1.Init.OversamplingMode = DISABLE; 8000774: 4b19 ldr r3, [pc, #100] @ (80007dc ) 8000776: 2200 movs r2, #0 8000778: f883 2040 strb.w r2, [r3, #64] @ 0x40 if (HAL_ADC_Init(&hadc1) != HAL_OK) 800077c: 4817 ldr r0, [pc, #92] @ (80007dc ) 800077e: f000 ffcd bl 800171c 8000782: 4603 mov r3, r0 8000784: 2b00 cmp r3, #0 8000786: d001 beq.n 800078c { Error_Handler(); 8000788: f000 fb24 bl 8000dd4 } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 800078c: 2300 movs r3, #0 800078e: 627b str r3, [r7, #36] @ 0x24 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000790: f107 0324 add.w r3, r7, #36 @ 0x24 8000794: 4619 mov r1, r3 8000796: 4811 ldr r0, [pc, #68] @ (80007dc ) 8000798: f002 f8d2 bl 8002940 800079c: 4603 mov r3, r0 800079e: 2b00 cmp r3, #0 80007a0: d001 beq.n 80007a6 { Error_Handler(); 80007a2: f000 fb17 bl 8000dd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 80007a6: 4b0e ldr r3, [pc, #56] @ (80007e0 ) 80007a8: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 80007aa: 2306 movs r3, #6 80007ac: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5; 80007ae: 2300 movs r3, #0 80007b0: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 80007b2: 237f movs r3, #127 @ 0x7f 80007b4: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 80007b6: 2304 movs r3, #4 80007b8: 617b str r3, [r7, #20] sConfig.Offset = 0; 80007ba: 2300 movs r3, #0 80007bc: 61bb str r3, [r7, #24] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 80007be: 1d3b adds r3, r7, #4 80007c0: 4619 mov r1, r3 80007c2: 4806 ldr r0, [pc, #24] @ (80007dc ) 80007c4: f001 fb04 bl 8001dd0 80007c8: 4603 mov r3, r0 80007ca: 2b00 cmp r3, #0 80007cc: d001 beq.n 80007d2 { Error_Handler(); 80007ce: f000 fb01 bl 8000dd4 } /* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */ } 80007d2: bf00 nop 80007d4: 3730 adds r7, #48 @ 0x30 80007d6: 46bd mov sp, r7 80007d8: bd80 pop {r7, pc} 80007da: bf00 nop 80007dc: 20000028 .word 0x20000028 80007e0: cb840000 .word 0xcb840000 080007e4 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 80007e4: b580 push {r7, lr} 80007e6: b088 sub sp, #32 80007e8: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 80007ea: 463b mov r3, r7 80007ec: 2220 movs r2, #32 80007ee: 2100 movs r1, #0 80007f0: 4618 mov r0, r3 80007f2: f006 fa67 bl 8006cc4 /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 80007f6: 4b32 ldr r3, [pc, #200] @ (80008c0 ) 80007f8: 4a32 ldr r2, [pc, #200] @ (80008c4 ) 80007fa: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV16; 80007fc: 4b30 ldr r3, [pc, #192] @ (80008c0 ) 80007fe: f44f 12e0 mov.w r2, #1835008 @ 0x1c0000 8000802: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_12B; 8000804: 4b2e ldr r3, [pc, #184] @ (80008c0 ) 8000806: 2200 movs r2, #0 8000808: 609a str r2, [r3, #8] hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; 800080a: 4b2d ldr r3, [pc, #180] @ (80008c0 ) 800080c: 2200 movs r2, #0 800080e: 60da str r2, [r3, #12] hadc2.Init.GainCompensation = 0; 8000810: 4b2b ldr r3, [pc, #172] @ (80008c0 ) 8000812: 2200 movs r2, #0 8000814: 611a str r2, [r3, #16] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000816: 4b2a ldr r3, [pc, #168] @ (80008c0 ) 8000818: 2201 movs r2, #1 800081a: 615a str r2, [r3, #20] hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 800081c: 4b28 ldr r3, [pc, #160] @ (80008c0 ) 800081e: 2204 movs r2, #4 8000820: 619a str r2, [r3, #24] hadc2.Init.LowPowerAutoWait = DISABLE; 8000822: 4b27 ldr r3, [pc, #156] @ (80008c0 ) 8000824: 2200 movs r2, #0 8000826: 771a strb r2, [r3, #28] hadc2.Init.ContinuousConvMode = DISABLE; 8000828: 4b25 ldr r3, [pc, #148] @ (80008c0 ) 800082a: 2200 movs r2, #0 800082c: 775a strb r2, [r3, #29] hadc2.Init.NbrOfConversion = 2; 800082e: 4b24 ldr r3, [pc, #144] @ (80008c0 ) 8000830: 2202 movs r2, #2 8000832: 621a str r2, [r3, #32] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000834: 4b22 ldr r3, [pc, #136] @ (80008c0 ) 8000836: 2200 movs r2, #0 8000838: f883 2024 strb.w r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; 800083c: 4b20 ldr r3, [pc, #128] @ (80008c0 ) 800083e: 2200 movs r2, #0 8000840: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 8000842: 4b1f ldr r3, [pc, #124] @ (80008c0 ) 8000844: 2200 movs r2, #0 8000846: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.DMAContinuousRequests = DISABLE; 8000848: 4b1d ldr r3, [pc, #116] @ (80008c0 ) 800084a: 2200 movs r2, #0 800084c: f883 2038 strb.w r2, [r3, #56] @ 0x38 hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000850: 4b1b ldr r3, [pc, #108] @ (80008c0 ) 8000852: 2200 movs r2, #0 8000854: 63da str r2, [r3, #60] @ 0x3c hadc2.Init.OversamplingMode = DISABLE; 8000856: 4b1a ldr r3, [pc, #104] @ (80008c0 ) 8000858: 2200 movs r2, #0 800085a: f883 2040 strb.w r2, [r3, #64] @ 0x40 if (HAL_ADC_Init(&hadc2) != HAL_OK) 800085e: 4818 ldr r0, [pc, #96] @ (80008c0 ) 8000860: f000 ff5c bl 800171c 8000864: 4603 mov r3, r0 8000866: 2b00 cmp r3, #0 8000868: d001 beq.n 800086e { Error_Handler(); 800086a: f000 fab3 bl 8000dd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 800086e: 4b16 ldr r3, [pc, #88] @ (80008c8 ) 8000870: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000872: 2306 movs r3, #6 8000874: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_24CYCLES_5; 8000876: 2303 movs r3, #3 8000878: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 800087a: 237f movs r3, #127 @ 0x7f 800087c: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 800087e: 2304 movs r3, #4 8000880: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000882: 2300 movs r3, #0 8000884: 617b str r3, [r7, #20] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000886: 463b mov r3, r7 8000888: 4619 mov r1, r3 800088a: 480d ldr r0, [pc, #52] @ (80008c0 ) 800088c: f001 faa0 bl 8001dd0 8000890: 4603 mov r3, r0 8000892: 2b00 cmp r3, #0 8000894: d001 beq.n 800089a { Error_Handler(); 8000896: f000 fa9d bl 8000dd4 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 800089a: 4b0c ldr r3, [pc, #48] @ (80008cc ) 800089c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 800089e: 230c movs r3, #12 80008a0: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 80008a2: 463b mov r3, r7 80008a4: 4619 mov r1, r3 80008a6: 4806 ldr r0, [pc, #24] @ (80008c0 ) 80008a8: f001 fa92 bl 8001dd0 80008ac: 4603 mov r3, r0 80008ae: 2b00 cmp r3, #0 80008b0: d001 beq.n 80008b6 { Error_Handler(); 80008b2: f000 fa8f bl 8000dd4 } /* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */ } 80008b6: bf00 nop 80008b8: 3720 adds r7, #32 80008ba: 46bd mov sp, r7 80008bc: bd80 pop {r7, pc} 80008be: bf00 nop 80008c0: 20000094 .word 0x20000094 80008c4: 50000100 .word 0x50000100 80008c8: 0c900008 .word 0x0c900008 80008cc: 10c00010 .word 0x10c00010 080008d0 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80008d0: b580 push {r7, lr} 80008d2: b088 sub sp, #32 80008d4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80008d6: f107 0310 add.w r3, r7, #16 80008da: 2200 movs r2, #0 80008dc: 601a str r2, [r3, #0] 80008de: 605a str r2, [r3, #4] 80008e0: 609a str r2, [r3, #8] 80008e2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80008e4: 1d3b adds r3, r7, #4 80008e6: 2200 movs r2, #0 80008e8: 601a str r2, [r3, #0] 80008ea: 605a str r2, [r3, #4] 80008ec: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80008ee: 4b1d ldr r3, [pc, #116] @ (8000964 ) 80008f0: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80008f4: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 80008f6: 4b1b ldr r3, [pc, #108] @ (8000964 ) 80008f8: 2200 movs r2, #0 80008fa: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80008fc: 4b19 ldr r3, [pc, #100] @ (8000964 ) 80008fe: 2200 movs r2, #0 8000900: 609a str r2, [r3, #8] htim2.Init.Period = 128999; 8000902: 4b18 ldr r3, [pc, #96] @ (8000964 ) 8000904: 4a18 ldr r2, [pc, #96] @ (8000968 ) 8000906: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000908: 4b16 ldr r3, [pc, #88] @ (8000964 ) 800090a: 2200 movs r2, #0 800090c: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800090e: 4b15 ldr r3, [pc, #84] @ (8000964 ) 8000910: 2200 movs r2, #0 8000912: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8000914: 4813 ldr r0, [pc, #76] @ (8000964 ) 8000916: f003 fbf3 bl 8004100 800091a: 4603 mov r3, r0 800091c: 2b00 cmp r3, #0 800091e: d001 beq.n 8000924 { Error_Handler(); 8000920: f000 fa58 bl 8000dd4 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000924: f44f 5380 mov.w r3, #4096 @ 0x1000 8000928: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800092a: f107 0310 add.w r3, r7, #16 800092e: 4619 mov r1, r3 8000930: 480c ldr r0, [pc, #48] @ (8000964 ) 8000932: f003 fd8b bl 800444c 8000936: 4603 mov r3, r0 8000938: 2b00 cmp r3, #0 800093a: d001 beq.n 8000940 { Error_Handler(); 800093c: f000 fa4a bl 8000dd4 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000940: 2300 movs r3, #0 8000942: 607b str r3, [r7, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000944: 2300 movs r3, #0 8000946: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8000948: 1d3b adds r3, r7, #4 800094a: 4619 mov r1, r3 800094c: 4805 ldr r0, [pc, #20] @ (8000964 ) 800094e: f003 ffe1 bl 8004914 8000952: 4603 mov r3, r0 8000954: 2b00 cmp r3, #0 8000956: d001 beq.n 800095c { Error_Handler(); 8000958: f000 fa3c bl 8000dd4 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 800095c: bf00 nop 800095e: 3720 adds r7, #32 8000960: 46bd mov sp, r7 8000962: bd80 pop {r7, pc} 8000964: 20000100 .word 0x20000100 8000968: 0001f7e7 .word 0x0001f7e7 0800096c : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 800096c: b580 push {r7, lr} 800096e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8000970: 4b22 ldr r3, [pc, #136] @ (80009fc ) 8000972: 4a23 ldr r2, [pc, #140] @ (8000a00 ) 8000974: 601a str r2, [r3, #0] huart2.Init.BaudRate = 921600; 8000976: 4b21 ldr r3, [pc, #132] @ (80009fc ) 8000978: f44f 2261 mov.w r2, #921600 @ 0xe1000 800097c: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800097e: 4b1f ldr r3, [pc, #124] @ (80009fc ) 8000980: 2200 movs r2, #0 8000982: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000984: 4b1d ldr r3, [pc, #116] @ (80009fc ) 8000986: 2200 movs r2, #0 8000988: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800098a: 4b1c ldr r3, [pc, #112] @ (80009fc ) 800098c: 2200 movs r2, #0 800098e: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8000990: 4b1a ldr r3, [pc, #104] @ (80009fc ) 8000992: 220c movs r2, #12 8000994: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000996: 4b19 ldr r3, [pc, #100] @ (80009fc ) 8000998: 2200 movs r2, #0 800099a: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800099c: 4b17 ldr r3, [pc, #92] @ (80009fc ) 800099e: 2200 movs r2, #0 80009a0: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80009a2: 4b16 ldr r3, [pc, #88] @ (80009fc ) 80009a4: 2200 movs r2, #0 80009a6: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80009a8: 4b14 ldr r3, [pc, #80] @ (80009fc ) 80009aa: 2200 movs r2, #0 80009ac: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80009ae: 4b13 ldr r3, [pc, #76] @ (80009fc ) 80009b0: 2200 movs r2, #0 80009b2: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 80009b4: 4811 ldr r0, [pc, #68] @ (80009fc ) 80009b6: f004 f875 bl 8004aa4 80009ba: 4603 mov r3, r0 80009bc: 2b00 cmp r3, #0 80009be: d001 beq.n 80009c4 { Error_Handler(); 80009c0: f000 fa08 bl 8000dd4 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80009c4: 2100 movs r1, #0 80009c6: 480d ldr r0, [pc, #52] @ (80009fc ) 80009c8: f006 f8b1 bl 8006b2e 80009cc: 4603 mov r3, r0 80009ce: 2b00 cmp r3, #0 80009d0: d001 beq.n 80009d6 { Error_Handler(); 80009d2: f000 f9ff bl 8000dd4 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80009d6: 2100 movs r1, #0 80009d8: 4808 ldr r0, [pc, #32] @ (80009fc ) 80009da: f006 f8e6 bl 8006baa 80009de: 4603 mov r3, r0 80009e0: 2b00 cmp r3, #0 80009e2: d001 beq.n 80009e8 { Error_Handler(); 80009e4: f000 f9f6 bl 8000dd4 } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 80009e8: 4804 ldr r0, [pc, #16] @ (80009fc ) 80009ea: f006 f867 bl 8006abc 80009ee: 4603 mov r3, r0 80009f0: 2b00 cmp r3, #0 80009f2: d001 beq.n 80009f8 { Error_Handler(); 80009f4: f000 f9ee bl 8000dd4 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80009f8: bf00 nop 80009fa: bd80 pop {r7, pc} 80009fc: 2000014c .word 0x2000014c 8000a00: 40004400 .word 0x40004400 08000a04 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000a04: b580 push {r7, lr} 8000a06: b088 sub sp, #32 8000a08: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000a0a: f107 030c add.w r3, r7, #12 8000a0e: 2200 movs r2, #0 8000a10: 601a str r2, [r3, #0] 8000a12: 605a str r2, [r3, #4] 8000a14: 609a str r2, [r3, #8] 8000a16: 60da str r2, [r3, #12] 8000a18: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8000a1a: 4b24 ldr r3, [pc, #144] @ (8000aac ) 8000a1c: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a1e: 4a23 ldr r2, [pc, #140] @ (8000aac ) 8000a20: f043 0301 orr.w r3, r3, #1 8000a24: 64d3 str r3, [r2, #76] @ 0x4c 8000a26: 4b21 ldr r3, [pc, #132] @ (8000aac ) 8000a28: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a2a: f003 0301 and.w r3, r3, #1 8000a2e: 60bb str r3, [r7, #8] 8000a30: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000a32: 4b1e ldr r3, [pc, #120] @ (8000aac ) 8000a34: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a36: 4a1d ldr r2, [pc, #116] @ (8000aac ) 8000a38: f043 0302 orr.w r3, r3, #2 8000a3c: 64d3 str r3, [r2, #76] @ 0x4c 8000a3e: 4b1b ldr r3, [pc, #108] @ (8000aac ) 8000a40: 6cdb ldr r3, [r3, #76] @ 0x4c 8000a42: f003 0302 and.w r3, r3, #2 8000a46: 607b str r3, [r7, #4] 8000a48: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); 8000a4a: 2200 movs r2, #0 8000a4c: f44f 5180 mov.w r1, #4096 @ 0x1000 8000a50: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000a54: f002 fb6a bl 800312c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8000a58: 2200 movs r2, #0 8000a5a: f44f 7180 mov.w r1, #256 @ 0x100 8000a5e: 4814 ldr r0, [pc, #80] @ (8000ab0 ) 8000a60: f002 fb64 bl 800312c /*Configure GPIO pin : POWER_SWITCH_Pin */ GPIO_InitStruct.Pin = POWER_SWITCH_Pin; 8000a64: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a68: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000a6a: 2301 movs r3, #1 8000a6c: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a6e: 2300 movs r3, #0 8000a70: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000a72: 2300 movs r3, #0 8000a74: 61bb str r3, [r7, #24] HAL_GPIO_Init(POWER_SWITCH_GPIO_Port, &GPIO_InitStruct); 8000a76: f107 030c add.w r3, r7, #12 8000a7a: 4619 mov r1, r3 8000a7c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000a80: f002 f9d2 bl 8002e28 /*Configure GPIO pin : LD2_Pin */ GPIO_InitStruct.Pin = LD2_Pin; 8000a84: f44f 7380 mov.w r3, #256 @ 0x100 8000a88: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000a8a: 2301 movs r3, #1 8000a8c: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000a8e: 2300 movs r3, #0 8000a90: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000a92: 2300 movs r3, #0 8000a94: 61bb str r3, [r7, #24] HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 8000a96: f107 030c add.w r3, r7, #12 8000a9a: 4619 mov r1, r3 8000a9c: 4804 ldr r0, [pc, #16] @ (8000ab0 ) 8000a9e: f002 f9c3 bl 8002e28 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000aa2: bf00 nop 8000aa4: 3720 adds r7, #32 8000aa6: 46bd mov sp, r7 8000aa8: bd80 pop {r7, pc} 8000aaa: bf00 nop 8000aac: 40021000 .word 0x40021000 8000ab0: 48000400 .word 0x48000400 08000ab4 : /* USER CODE BEGIN 4 */ uint32_t get_actual_vdda(ADC_HandleTypeDef *hadc) { 8000ab4: b580 push {r7, lr} 8000ab6: b084 sub sp, #16 8000ab8: af00 add r7, sp, #0 8000aba: 6078 str r0, [r7, #4] uint32_t vrefint_raw = 0; 8000abc: 2300 movs r3, #0 8000abe: 60fb str r3, [r7, #12] /* Perform ADC reading of the VREFINT channel */ HAL_ADC_Start(hadc); 8000ac0: 6878 ldr r0, [r7, #4] 8000ac2: f000 ffaf bl 8001a24 if (HAL_ADC_PollForConversion(hadc, 10) == HAL_OK) { 8000ac6: 210a movs r1, #10 8000ac8: 6878 ldr r0, [r7, #4] 8000aca: f001 f89b bl 8001c04 8000ace: 4603 mov r3, r0 8000ad0: 2b00 cmp r3, #0 8000ad2: d103 bne.n 8000adc vrefint_raw = HAL_ADC_GetValue(hadc); 8000ad4: 6878 ldr r0, [r7, #4] 8000ad6: f001 f96d bl 8001db4 8000ada: 60f8 str r0, [r7, #12] } HAL_ADC_Stop(hadc); 8000adc: 6878 ldr r0, [r7, #4] 8000ade: f001 f85d bl 8001b9c if (vrefint_raw == 0) return 0; /* Avoid division by zero */ 8000ae2: 68fb ldr r3, [r7, #12] 8000ae4: 2b00 cmp r3, #0 8000ae6: d101 bne.n 8000aec 8000ae8: 2300 movs r3, #0 8000aea: e00b b.n 8000b04 /* Use the standard ST formula to calculate VDDA */ /* VDDA = VREFINT_CAL_VREF * VREFINT_CAL / VREFINT_DATA */ uint32_t vdda_mv = (VREFINT_CAL_VREF * (uint32_t)(*VREFINT_CAL_ADDR)) / vrefint_raw; 8000aec: 4b07 ldr r3, [pc, #28] @ (8000b0c ) 8000aee: 881b ldrh r3, [r3, #0] 8000af0: 461a mov r2, r3 8000af2: f640 33b8 movw r3, #3000 @ 0xbb8 8000af6: fb03 f202 mul.w r2, r3, r2 8000afa: 68fb ldr r3, [r7, #12] 8000afc: fbb2 f3f3 udiv r3, r2, r3 8000b00: 60bb str r3, [r7, #8] return vdda_mv; 8000b02: 68bb ldr r3, [r7, #8] } 8000b04: 4618 mov r0, r3 8000b06: 3710 adds r7, #16 8000b08: 46bd mov sp, r7 8000b0a: bd80 pop {r7, pc} 8000b0c: 1fff75aa .word 0x1fff75aa 08000b10 : return (raw_adc_value * vdda_mv) / 4095; } /* ADC task */ void adc_task (void) { 8000b10: b580 push {r7, lr} 8000b12: af00 add r7, sp, #0 HAL_ADC_Start(&hadc2); 8000b14: 4810 ldr r0, [pc, #64] @ (8000b58 ) 8000b16: f000 ff85 bl 8001a24 HAL_ADC_PollForConversion(&hadc2, 100); 8000b1a: 2164 movs r1, #100 @ 0x64 8000b1c: 480e ldr r0, [pc, #56] @ (8000b58 ) 8000b1e: f001 f871 bl 8001c04 vin_adc_val = HAL_ADC_GetValue(&hadc2); 8000b22: 480d ldr r0, [pc, #52] @ (8000b58 ) 8000b24: f001 f946 bl 8001db4 8000b28: 4603 mov r3, r0 8000b2a: b29a uxth r2, r3 8000b2c: 4b0b ldr r3, [pc, #44] @ (8000b5c ) 8000b2e: 801a strh r2, [r3, #0] HAL_ADC_Start(&hadc2); 8000b30: 4809 ldr r0, [pc, #36] @ (8000b58 ) 8000b32: f000 ff77 bl 8001a24 HAL_ADC_PollForConversion(&hadc2, 100); 8000b36: 2164 movs r1, #100 @ 0x64 8000b38: 4807 ldr r0, [pc, #28] @ (8000b58 ) 8000b3a: f001 f863 bl 8001c04 vout_adc_val = HAL_ADC_GetValue(&hadc2); 8000b3e: 4806 ldr r0, [pc, #24] @ (8000b58 ) 8000b40: f001 f938 bl 8001db4 8000b44: 4603 mov r3, r0 8000b46: b29a uxth r2, r3 8000b48: 4b05 ldr r3, [pc, #20] @ (8000b60 ) 8000b4a: 801a strh r2, [r3, #0] HAL_ADC_Stop(&hadc2); 8000b4c: 4802 ldr r0, [pc, #8] @ (8000b58 ) 8000b4e: f001 f825 bl 8001b9c } 8000b52: bf00 nop 8000b54: bd80 pop {r7, pc} 8000b56: bf00 nop 8000b58: 20000094 .word 0x20000094 8000b5c: 20000232 .word 0x20000232 8000b60: 20000234 .word 0x20000234 08000b64 : /* Power switch function */ void power_switch (uint8_t state) { 8000b64: b580 push {r7, lr} 8000b66: b082 sub sp, #8 8000b68: af00 add r7, sp, #0 8000b6a: 4603 mov r3, r0 8000b6c: 71fb strb r3, [r7, #7] if (state == 1) 8000b6e: 79fb ldrb r3, [r7, #7] 8000b70: 2b01 cmp r3, #1 8000b72: d10d bne.n 8000b90 { HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_SET); 8000b74: 2201 movs r2, #1 8000b76: f44f 5180 mov.w r1, #4096 @ 0x1000 8000b7a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000b7e: f002 fad5 bl 800312c HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET); 8000b82: 2201 movs r2, #1 8000b84: f44f 7180 mov.w r1, #256 @ 0x100 8000b88: 480a ldr r0, [pc, #40] @ (8000bb4 ) 8000b8a: f002 facf bl 800312c else { HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); } } 8000b8e: e00c b.n 8000baa HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); 8000b90: 2200 movs r2, #0 8000b92: f44f 5180 mov.w r1, #4096 @ 0x1000 8000b96: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000b9a: f002 fac7 bl 800312c HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8000b9e: 2200 movs r2, #0 8000ba0: f44f 7180 mov.w r1, #256 @ 0x100 8000ba4: 4803 ldr r0, [pc, #12] @ (8000bb4 ) 8000ba6: f002 fac1 bl 800312c } 8000baa: bf00 nop 8000bac: 3708 adds r7, #8 8000bae: 46bd mov sp, r7 8000bb0: bd80 pop {r7, pc} 8000bb2: bf00 nop 8000bb4: 48000400 .word 0x48000400 08000bb8 : /* UART Tx callback */ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { 8000bb8: b480 push {r7} 8000bba: b083 sub sp, #12 8000bbc: af00 add r7, sp, #0 8000bbe: 6078 str r0, [r7, #4] /* Do nothing here for now */ } 8000bc0: bf00 nop 8000bc2: 370c adds r7, #12 8000bc4: 46bd mov sp, r7 8000bc6: f85d 7b04 ldr.w r7, [sp], #4 8000bca: 4770 bx lr 08000bcc : /* UART Rx callback */ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8000bcc: b580 push {r7, lr} 8000bce: b082 sub sp, #8 8000bd0: af00 add r7, sp, #0 8000bd2: 6078 str r0, [r7, #4] /* If data received on UART */ if(huart->Instance==USART2) 8000bd4: 687b ldr r3, [r7, #4] 8000bd6: 681b ldr r3, [r3, #0] 8000bd8: 4a70 ldr r2, [pc, #448] @ (8000d9c ) 8000bda: 4293 cmp r3, r2 8000bdc: f040 80da bne.w 8000d94 { /* Act on received data */ switch (rx_counter) 8000be0: 4b6f ldr r3, [pc, #444] @ (8000da0 ) 8000be2: 781b ldrb r3, [r3, #0] 8000be4: 2b05 cmp r3, #5 8000be6: f200 80cb bhi.w 8000d80 8000bea: a201 add r2, pc, #4 @ (adr r2, 8000bf0 ) 8000bec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000bf0: 08000c09 .word 0x08000c09 8000bf4: 08000c21 .word 0x08000c21 8000bf8: 08000c4f .word 0x08000c4f 8000bfc: 08000c6b .word 0x08000c6b 8000c00: 08000ca5 .word 0x08000ca5 8000c04: 08000cbb .word 0x08000cbb { case 0x00: /* Check to see if first sync byte has been received */ if (rx_hold_buffer[0] == IN_SYNC_BYTE_1) 8000c08: 4b66 ldr r3, [pc, #408] @ (8000da4 ) 8000c0a: 781b ldrb r3, [r3, #0] 8000c0c: 2b41 cmp r3, #65 @ 0x41 8000c0e: f040 80b9 bne.w 8000d84 { /* Got it, so now wait for the second sync byte */ rx_counter++; 8000c12: 4b63 ldr r3, [pc, #396] @ (8000da0 ) 8000c14: 781b ldrb r3, [r3, #0] 8000c16: 3301 adds r3, #1 8000c18: b2da uxtb r2, r3 8000c1a: 4b61 ldr r3, [pc, #388] @ (8000da0 ) 8000c1c: 701a strb r2, [r3, #0] } break; 8000c1e: e0b1 b.n 8000d84 case 0x01: /* Check to see if second sync byte has been received */ if (rx_hold_buffer[0] == IN_SYNC_BYTE_2) 8000c20: 4b60 ldr r3, [pc, #384] @ (8000da4 ) 8000c22: 781b ldrb r3, [r3, #0] 8000c24: 2b52 cmp r3, #82 @ 0x52 8000c26: d106 bne.n 8000c36 { /* Got it, so now wait for the data byte */ rx_counter++; 8000c28: 4b5d ldr r3, [pc, #372] @ (8000da0 ) 8000c2a: 781b ldrb r3, [r3, #0] 8000c2c: 3301 adds r3, #1 8000c2e: b2da uxtb r2, r3 8000c30: 4b5b ldr r3, [pc, #364] @ (8000da0 ) 8000c32: 701a strb r2, [r3, #0] { rx_counter = 0x00; } } break; 8000c34: e0a9 b.n 8000d8a if (rx_hold_buffer[0] == IN_SYNC_BYTE_1) 8000c36: 4b5b ldr r3, [pc, #364] @ (8000da4 ) 8000c38: 781b ldrb r3, [r3, #0] 8000c3a: 2b41 cmp r3, #65 @ 0x41 8000c3c: d103 bne.n 8000c46 rx_counter = 0x01; 8000c3e: 4b58 ldr r3, [pc, #352] @ (8000da0 ) 8000c40: 2201 movs r2, #1 8000c42: 701a strb r2, [r3, #0] break; 8000c44: e0a1 b.n 8000d8a rx_counter = 0x00; 8000c46: 4b56 ldr r3, [pc, #344] @ (8000da0 ) 8000c48: 2200 movs r2, #0 8000c4a: 701a strb r2, [r3, #0] break; 8000c4c: e09d b.n 8000d8a case 0x02: /* Get rx length and reset counter */ rx_len = rx_hold_buffer[0]; 8000c4e: 4b55 ldr r3, [pc, #340] @ (8000da4 ) 8000c50: 781a ldrb r2, [r3, #0] 8000c52: 4b55 ldr r3, [pc, #340] @ (8000da8 ) 8000c54: 701a strb r2, [r3, #0] rx_len_counter = 0x00; 8000c56: 4b55 ldr r3, [pc, #340] @ (8000dac ) 8000c58: 2200 movs r2, #0 8000c5a: 701a strb r2, [r3, #0] rx_counter++; 8000c5c: 4b50 ldr r3, [pc, #320] @ (8000da0 ) 8000c5e: 781b ldrb r3, [r3, #0] 8000c60: 3301 adds r3, #1 8000c62: b2da uxtb r2, r3 8000c64: 4b4e ldr r3, [pc, #312] @ (8000da0 ) 8000c66: 701a strb r2, [r3, #0] break; 8000c68: e08f b.n 8000d8a case 0x03: /* Store entire length of Data bytes */ /* Increase count */ rx_len_counter++; 8000c6a: 4b50 ldr r3, [pc, #320] @ (8000dac ) 8000c6c: 781b ldrb r3, [r3, #0] 8000c6e: 3301 adds r3, #1 8000c70: b2da uxtb r2, r3 8000c72: 4b4e ldr r3, [pc, #312] @ (8000dac ) 8000c74: 701a strb r2, [r3, #0] /* Store data */ rx_buffer[rx_len_counter - 1] = rx_hold_buffer[0]; 8000c76: 4b4d ldr r3, [pc, #308] @ (8000dac ) 8000c78: 781b ldrb r3, [r3, #0] 8000c7a: 3b01 subs r3, #1 8000c7c: 4a49 ldr r2, [pc, #292] @ (8000da4 ) 8000c7e: 7811 ldrb r1, [r2, #0] 8000c80: 4a4b ldr r2, [pc, #300] @ (8000db0 ) 8000c82: 54d1 strb r1, [r2, r3] /* Check to see if we have all the expected data bytes */ /* If so, then move on the CRC */ if (rx_len_counter == rx_len) 8000c84: 4b49 ldr r3, [pc, #292] @ (8000dac ) 8000c86: 781a ldrb r2, [r3, #0] 8000c88: 4b47 ldr r3, [pc, #284] @ (8000da8 ) 8000c8a: 781b ldrb r3, [r3, #0] 8000c8c: 429a cmp r2, r3 8000c8e: d17b bne.n 8000d88 { rx_counter++; 8000c90: 4b43 ldr r3, [pc, #268] @ (8000da0 ) 8000c92: 781b ldrb r3, [r3, #0] 8000c94: 3301 adds r3, #1 8000c96: b2da uxtb r2, r3 8000c98: 4b41 ldr r3, [pc, #260] @ (8000da0 ) 8000c9a: 701a strb r2, [r3, #0] rx_len_counter = 0x00; 8000c9c: 4b43 ldr r3, [pc, #268] @ (8000dac ) 8000c9e: 2200 movs r2, #0 8000ca0: 701a strb r2, [r3, #0] } break; 8000ca2: e071 b.n 8000d88 case 0x04: /* Store Rx checksum byte #1 */ rx_checksum_hold_1 = rx_hold_buffer[0]; 8000ca4: 4b3f ldr r3, [pc, #252] @ (8000da4 ) 8000ca6: 781a ldrb r2, [r3, #0] 8000ca8: 4b42 ldr r3, [pc, #264] @ (8000db4 ) 8000caa: 701a strb r2, [r3, #0] rx_counter++; 8000cac: 4b3c ldr r3, [pc, #240] @ (8000da0 ) 8000cae: 781b ldrb r3, [r3, #0] 8000cb0: 3301 adds r3, #1 8000cb2: b2da uxtb r2, r3 8000cb4: 4b3a ldr r3, [pc, #232] @ (8000da0 ) 8000cb6: 701a strb r2, [r3, #0] break; 8000cb8: e067 b.n 8000d8a case 0x05: /* Store Rx checksum byte #2, reset and calculate checksum */ rx_checksum_hold_2 = rx_hold_buffer[0]; 8000cba: 4b3a ldr r3, [pc, #232] @ (8000da4 ) 8000cbc: 781a ldrb r2, [r3, #0] 8000cbe: 4b3e ldr r3, [pc, #248] @ (8000db8 ) 8000cc0: 701a strb r2, [r3, #0] rx_checksum_hold = (rx_checksum_hold_1 << 8) | rx_checksum_hold_2; 8000cc2: 4b3c ldr r3, [pc, #240] @ (8000db4 ) 8000cc4: 781b ldrb r3, [r3, #0] 8000cc6: b21b sxth r3, r3 8000cc8: 021b lsls r3, r3, #8 8000cca: b21a sxth r2, r3 8000ccc: 4b3a ldr r3, [pc, #232] @ (8000db8 ) 8000cce: 781b ldrb r3, [r3, #0] 8000cd0: b21b sxth r3, r3 8000cd2: 4313 orrs r3, r2 8000cd4: b21b sxth r3, r3 8000cd6: b29a uxth r2, r3 8000cd8: 4b38 ldr r3, [pc, #224] @ (8000dbc ) 8000cda: 801a strh r2, [r3, #0] rx_checksum = 0; 8000cdc: 4b38 ldr r3, [pc, #224] @ (8000dc0 ) 8000cde: 2200 movs r2, #0 8000ce0: 801a strh r2, [r3, #0] /* Need to apply to all data bits */ for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++) 8000ce2: 4b32 ldr r3, [pc, #200] @ (8000dac ) 8000ce4: 2200 movs r2, #0 8000ce6: 701a strb r2, [r3, #0] 8000ce8: e011 b.n 8000d0e { rx_checksum += rx_buffer[rx_len_counter]; 8000cea: 4b30 ldr r3, [pc, #192] @ (8000dac ) 8000cec: 781b ldrb r3, [r3, #0] 8000cee: 461a mov r2, r3 8000cf0: 4b2f ldr r3, [pc, #188] @ (8000db0 ) 8000cf2: 5c9b ldrb r3, [r3, r2] 8000cf4: 461a mov r2, r3 8000cf6: 4b32 ldr r3, [pc, #200] @ (8000dc0 ) 8000cf8: 881b ldrh r3, [r3, #0] 8000cfa: 4413 add r3, r2 8000cfc: b29a uxth r2, r3 8000cfe: 4b30 ldr r3, [pc, #192] @ (8000dc0 ) 8000d00: 801a strh r2, [r3, #0] for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++) 8000d02: 4b2a ldr r3, [pc, #168] @ (8000dac ) 8000d04: 781b ldrb r3, [r3, #0] 8000d06: 3301 adds r3, #1 8000d08: b2da uxtb r2, r3 8000d0a: 4b28 ldr r3, [pc, #160] @ (8000dac ) 8000d0c: 701a strb r2, [r3, #0] 8000d0e: 4b27 ldr r3, [pc, #156] @ (8000dac ) 8000d10: 781a ldrb r2, [r3, #0] 8000d12: 4b25 ldr r3, [pc, #148] @ (8000da8 ) 8000d14: 781b ldrb r3, [r3, #0] 8000d16: 429a cmp r2, r3 8000d18: d3e7 bcc.n 8000cea } rx_len = 0x00; 8000d1a: 4b23 ldr r3, [pc, #140] @ (8000da8 ) 8000d1c: 2200 movs r2, #0 8000d1e: 701a strb r2, [r3, #0] rx_len_counter = 0x00; 8000d20: 4b22 ldr r3, [pc, #136] @ (8000dac ) 8000d22: 2200 movs r2, #0 8000d24: 701a strb r2, [r3, #0] rx_checksum = ~rx_checksum; 8000d26: 4b26 ldr r3, [pc, #152] @ (8000dc0 ) 8000d28: 881b ldrh r3, [r3, #0] 8000d2a: 43db mvns r3, r3 8000d2c: b29a uxth r2, r3 8000d2e: 4b24 ldr r3, [pc, #144] @ (8000dc0 ) 8000d30: 801a strh r2, [r3, #0] /* If checksum calculated equals the received checksum of packet then we got a good packet */ if (rx_checksum == rx_checksum_hold) 8000d32: 4b23 ldr r3, [pc, #140] @ (8000dc0 ) 8000d34: 881a ldrh r2, [r3, #0] 8000d36: 4b21 ldr r3, [pc, #132] @ (8000dbc ) 8000d38: 881b ldrh r3, [r3, #0] 8000d3a: 429a cmp r2, r3 8000d3c: d11b bne.n 8000d76 { /* Rx is finished, so reset count to wait for another first sync byte (also act on command/data)*/ rx_counter = 0x00; 8000d3e: 4b18 ldr r3, [pc, #96] @ (8000da0 ) 8000d40: 2200 movs r2, #0 8000d42: 701a strb r2, [r3, #0] command = rx_buffer[0]; 8000d44: 4b1a ldr r3, [pc, #104] @ (8000db0 ) 8000d46: 781a ldrb r2, [r3, #0] 8000d48: 4b1e ldr r3, [pc, #120] @ (8000dc4 ) 8000d4a: 701a strb r2, [r3, #0] switch (command) 8000d4c: 4b1d ldr r3, [pc, #116] @ (8000dc4 ) 8000d4e: 781b ldrb r3, [r3, #0] 8000d50: 2b53 cmp r3, #83 @ 0x53 8000d52: d002 beq.n 8000d5a 8000d54: 2b56 cmp r3, #86 @ 0x56 8000d56: d00a beq.n 8000d6e case 0x56: adc_task_flag = 0xff; break; default: break; 8000d58: e011 b.n 8000d7e power_state_value = rx_buffer[1]; 8000d5a: 4b15 ldr r3, [pc, #84] @ (8000db0 ) 8000d5c: 785a ldrb r2, [r3, #1] 8000d5e: 4b1a ldr r3, [pc, #104] @ (8000dc8 ) 8000d60: 701a strb r2, [r3, #0] power_switch(power_state_value); 8000d62: 4b19 ldr r3, [pc, #100] @ (8000dc8 ) 8000d64: 781b ldrb r3, [r3, #0] 8000d66: 4618 mov r0, r3 8000d68: f7ff fefc bl 8000b64 break; 8000d6c: e007 b.n 8000d7e adc_task_flag = 0xff; 8000d6e: 4b17 ldr r3, [pc, #92] @ (8000dcc ) 8000d70: 22ff movs r2, #255 @ 0xff 8000d72: 701a strb r2, [r3, #0] break; 8000d74: e003 b.n 8000d7e /* Bad packet received */ else { /* Rx is finished, so reset count to wait for another first sync byte (bad packet so no flag)*/ rx_counter = 0x00; 8000d76: 4b0a ldr r3, [pc, #40] @ (8000da0 ) 8000d78: 2200 movs r2, #0 8000d7a: 701a strb r2, [r3, #0] } break; 8000d7c: e005 b.n 8000d8a 8000d7e: e004 b.n 8000d8a /* Default case - NOT USED!*/ default: break; 8000d80: bf00 nop 8000d82: e002 b.n 8000d8a break; 8000d84: bf00 nop 8000d86: e000 b.n 8000d8a break; 8000d88: bf00 nop } /* Reset interrupts */ HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1); 8000d8a: 2201 movs r2, #1 8000d8c: 4905 ldr r1, [pc, #20] @ (8000da4 ) 8000d8e: 4810 ldr r0, [pc, #64] @ (8000dd0 ) 8000d90: f003 ff66 bl 8004c60 } } 8000d94: bf00 nop 8000d96: 3708 adds r7, #8 8000d98: 46bd mov sp, r7 8000d9a: bd80 pop {r7, pc} 8000d9c: 40004400 .word 0x40004400 8000da0: 20000225 .word 0x20000225 8000da4: 200001e0 .word 0x200001e0 8000da8: 20000226 .word 0x20000226 8000dac: 20000227 .word 0x20000227 8000db0: 200001e4 .word 0x200001e4 8000db4: 2000022a .word 0x2000022a 8000db8: 2000022b .word 0x2000022b 8000dbc: 2000022c .word 0x2000022c 8000dc0: 20000228 .word 0x20000228 8000dc4: 2000022f .word 0x2000022f 8000dc8: 2000022e .word 0x2000022e 8000dcc: 20000230 .word 0x20000230 8000dd0: 2000014c .word 0x2000014c 08000dd4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000dd4: b480 push {r7} 8000dd6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000dd8: b672 cpsid i } 8000dda: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000ddc: bf00 nop 8000dde: e7fd b.n 8000ddc 08000de0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000de0: b580 push {r7, lr} 8000de2: b082 sub sp, #8 8000de4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000de6: 4b0f ldr r3, [pc, #60] @ (8000e24 ) 8000de8: 6e1b ldr r3, [r3, #96] @ 0x60 8000dea: 4a0e ldr r2, [pc, #56] @ (8000e24 ) 8000dec: f043 0301 orr.w r3, r3, #1 8000df0: 6613 str r3, [r2, #96] @ 0x60 8000df2: 4b0c ldr r3, [pc, #48] @ (8000e24 ) 8000df4: 6e1b ldr r3, [r3, #96] @ 0x60 8000df6: f003 0301 and.w r3, r3, #1 8000dfa: 607b str r3, [r7, #4] 8000dfc: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000dfe: 4b09 ldr r3, [pc, #36] @ (8000e24 ) 8000e00: 6d9b ldr r3, [r3, #88] @ 0x58 8000e02: 4a08 ldr r2, [pc, #32] @ (8000e24 ) 8000e04: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000e08: 6593 str r3, [r2, #88] @ 0x58 8000e0a: 4b06 ldr r3, [pc, #24] @ (8000e24 ) 8000e0c: 6d9b ldr r3, [r3, #88] @ 0x58 8000e0e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000e12: 603b str r3, [r7, #0] 8000e14: 683b ldr r3, [r7, #0] /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); 8000e16: f002 fa45 bl 80032a4 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e1a: bf00 nop 8000e1c: 3708 adds r7, #8 8000e1e: 46bd mov sp, r7 8000e20: bd80 pop {r7, pc} 8000e22: bf00 nop 8000e24: 40021000 .word 0x40021000 08000e28 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8000e28: b580 push {r7, lr} 8000e2a: b09c sub sp, #112 @ 0x70 8000e2c: af00 add r7, sp, #0 8000e2e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e30: f107 035c add.w r3, r7, #92 @ 0x5c 8000e34: 2200 movs r2, #0 8000e36: 601a str r2, [r3, #0] 8000e38: 605a str r2, [r3, #4] 8000e3a: 609a str r2, [r3, #8] 8000e3c: 60da str r2, [r3, #12] 8000e3e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000e40: f107 0318 add.w r3, r7, #24 8000e44: 2244 movs r2, #68 @ 0x44 8000e46: 2100 movs r1, #0 8000e48: 4618 mov r0, r3 8000e4a: f005 ff3b bl 8006cc4 if(hadc->Instance==ADC1) 8000e4e: 687b ldr r3, [r7, #4] 8000e50: 681b ldr r3, [r3, #0] 8000e52: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8000e56: d125 bne.n 8000ea4 /* USER CODE END ADC1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8000e58: f44f 4300 mov.w r3, #32768 @ 0x8000 8000e5c: 61bb str r3, [r7, #24] PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8000e5e: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8000e62: 657b str r3, [r7, #84] @ 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000e64: f107 0318 add.w r3, r7, #24 8000e68: 4618 mov r0, r3 8000e6a: f002 ff59 bl 8003d20 8000e6e: 4603 mov r3, r0 8000e70: 2b00 cmp r3, #0 8000e72: d001 beq.n 8000e78 { Error_Handler(); 8000e74: f7ff ffae bl 8000dd4 } /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8000e78: 4b2e ldr r3, [pc, #184] @ (8000f34 ) 8000e7a: 681b ldr r3, [r3, #0] 8000e7c: 3301 adds r3, #1 8000e7e: 4a2d ldr r2, [pc, #180] @ (8000f34 ) 8000e80: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8000e82: 4b2c ldr r3, [pc, #176] @ (8000f34 ) 8000e84: 681b ldr r3, [r3, #0] 8000e86: 2b01 cmp r3, #1 8000e88: d14f bne.n 8000f2a __HAL_RCC_ADC12_CLK_ENABLE(); 8000e8a: 4b2b ldr r3, [pc, #172] @ (8000f38 ) 8000e8c: 6cdb ldr r3, [r3, #76] @ 0x4c 8000e8e: 4a2a ldr r2, [pc, #168] @ (8000f38 ) 8000e90: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8000e94: 64d3 str r3, [r2, #76] @ 0x4c 8000e96: 4b28 ldr r3, [pc, #160] @ (8000f38 ) 8000e98: 6cdb ldr r3, [r3, #76] @ 0x4c 8000e9a: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000e9e: 617b str r3, [r7, #20] 8000ea0: 697b ldr r3, [r7, #20] /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } 8000ea2: e042 b.n 8000f2a else if(hadc->Instance==ADC2) 8000ea4: 687b ldr r3, [r7, #4] 8000ea6: 681b ldr r3, [r3, #0] 8000ea8: 4a24 ldr r2, [pc, #144] @ (8000f3c ) 8000eaa: 4293 cmp r3, r2 8000eac: d13d bne.n 8000f2a PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; 8000eae: f44f 4300 mov.w r3, #32768 @ 0x8000 8000eb2: 61bb str r3, [r7, #24] PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; 8000eb4: f04f 5300 mov.w r3, #536870912 @ 0x20000000 8000eb8: 657b str r3, [r7, #84] @ 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000eba: f107 0318 add.w r3, r7, #24 8000ebe: 4618 mov r0, r3 8000ec0: f002 ff2e bl 8003d20 8000ec4: 4603 mov r3, r0 8000ec6: 2b00 cmp r3, #0 8000ec8: d001 beq.n 8000ece Error_Handler(); 8000eca: f7ff ff83 bl 8000dd4 HAL_RCC_ADC12_CLK_ENABLED++; 8000ece: 4b19 ldr r3, [pc, #100] @ (8000f34 ) 8000ed0: 681b ldr r3, [r3, #0] 8000ed2: 3301 adds r3, #1 8000ed4: 4a17 ldr r2, [pc, #92] @ (8000f34 ) 8000ed6: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8000ed8: 4b16 ldr r3, [pc, #88] @ (8000f34 ) 8000eda: 681b ldr r3, [r3, #0] 8000edc: 2b01 cmp r3, #1 8000ede: d10b bne.n 8000ef8 __HAL_RCC_ADC12_CLK_ENABLE(); 8000ee0: 4b15 ldr r3, [pc, #84] @ (8000f38 ) 8000ee2: 6cdb ldr r3, [r3, #76] @ 0x4c 8000ee4: 4a14 ldr r2, [pc, #80] @ (8000f38 ) 8000ee6: f443 5300 orr.w r3, r3, #8192 @ 0x2000 8000eea: 64d3 str r3, [r2, #76] @ 0x4c 8000eec: 4b12 ldr r3, [pc, #72] @ (8000f38 ) 8000eee: 6cdb ldr r3, [r3, #76] @ 0x4c 8000ef0: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000ef4: 613b str r3, [r7, #16] 8000ef6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000ef8: 4b0f ldr r3, [pc, #60] @ (8000f38 ) 8000efa: 6cdb ldr r3, [r3, #76] @ 0x4c 8000efc: 4a0e ldr r2, [pc, #56] @ (8000f38 ) 8000efe: f043 0301 orr.w r3, r3, #1 8000f02: 64d3 str r3, [r2, #76] @ 0x4c 8000f04: 4b0c ldr r3, [pc, #48] @ (8000f38 ) 8000f06: 6cdb ldr r3, [r3, #76] @ 0x4c 8000f08: f003 0301 and.w r3, r3, #1 8000f0c: 60fb str r3, [r7, #12] 8000f0e: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = VIN_Pin|VOUT_Pin; 8000f10: 23c0 movs r3, #192 @ 0xc0 8000f12: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000f14: 2303 movs r3, #3 8000f16: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f18: 2300 movs r3, #0 8000f1a: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f1c: f107 035c add.w r3, r7, #92 @ 0x5c 8000f20: 4619 mov r1, r3 8000f22: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8000f26: f001 ff7f bl 8002e28 } 8000f2a: bf00 nop 8000f2c: 3770 adds r7, #112 @ 0x70 8000f2e: 46bd mov sp, r7 8000f30: bd80 pop {r7, pc} 8000f32: bf00 nop 8000f34: 2000023c .word 0x2000023c 8000f38: 40021000 .word 0x40021000 8000f3c: 50000100 .word 0x50000100 08000f40 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8000f40: b580 push {r7, lr} 8000f42: b084 sub sp, #16 8000f44: af00 add r7, sp, #0 8000f46: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM2) 8000f48: 687b ldr r3, [r7, #4] 8000f4a: 681b ldr r3, [r3, #0] 8000f4c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8000f50: d113 bne.n 8000f7a { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8000f52: 4b0c ldr r3, [pc, #48] @ (8000f84 ) 8000f54: 6d9b ldr r3, [r3, #88] @ 0x58 8000f56: 4a0b ldr r2, [pc, #44] @ (8000f84 ) 8000f58: f043 0301 orr.w r3, r3, #1 8000f5c: 6593 str r3, [r2, #88] @ 0x58 8000f5e: 4b09 ldr r3, [pc, #36] @ (8000f84 ) 8000f60: 6d9b ldr r3, [r3, #88] @ 0x58 8000f62: f003 0301 and.w r3, r3, #1 8000f66: 60fb str r3, [r7, #12] 8000f68: 68fb ldr r3, [r7, #12] /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); 8000f6a: 2200 movs r2, #0 8000f6c: 2100 movs r1, #0 8000f6e: 201c movs r0, #28 8000f70: f001 fe65 bl 8002c3e HAL_NVIC_EnableIRQ(TIM2_IRQn); 8000f74: 201c movs r0, #28 8000f76: f001 fe7c bl 8002c72 /* USER CODE END TIM2_MspInit 1 */ } } 8000f7a: bf00 nop 8000f7c: 3710 adds r7, #16 8000f7e: 46bd mov sp, r7 8000f80: bd80 pop {r7, pc} 8000f82: bf00 nop 8000f84: 40021000 .word 0x40021000 08000f88 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8000f88: b580 push {r7, lr} 8000f8a: b09a sub sp, #104 @ 0x68 8000f8c: af00 add r7, sp, #0 8000f8e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f90: f107 0354 add.w r3, r7, #84 @ 0x54 8000f94: 2200 movs r2, #0 8000f96: 601a str r2, [r3, #0] 8000f98: 605a str r2, [r3, #4] 8000f9a: 609a str r2, [r3, #8] 8000f9c: 60da str r2, [r3, #12] 8000f9e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000fa0: f107 0310 add.w r3, r7, #16 8000fa4: 2244 movs r2, #68 @ 0x44 8000fa6: 2100 movs r1, #0 8000fa8: 4618 mov r0, r3 8000faa: f005 fe8b bl 8006cc4 if(huart->Instance==USART2) 8000fae: 687b ldr r3, [r7, #4] 8000fb0: 681b ldr r3, [r3, #0] 8000fb2: 4a23 ldr r2, [pc, #140] @ (8001040 ) 8000fb4: 4293 cmp r3, r2 8000fb6: d13e bne.n 8001036 /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; 8000fb8: 2302 movs r3, #2 8000fba: 613b str r3, [r7, #16] PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; 8000fbc: 2300 movs r3, #0 8000fbe: 61bb str r3, [r7, #24] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000fc0: f107 0310 add.w r3, r7, #16 8000fc4: 4618 mov r0, r3 8000fc6: f002 feab bl 8003d20 8000fca: 4603 mov r3, r0 8000fcc: 2b00 cmp r3, #0 8000fce: d001 beq.n 8000fd4 { Error_Handler(); 8000fd0: f7ff ff00 bl 8000dd4 } /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000fd4: 4b1b ldr r3, [pc, #108] @ (8001044 ) 8000fd6: 6d9b ldr r3, [r3, #88] @ 0x58 8000fd8: 4a1a ldr r2, [pc, #104] @ (8001044 ) 8000fda: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000fde: 6593 str r3, [r2, #88] @ 0x58 8000fe0: 4b18 ldr r3, [pc, #96] @ (8001044 ) 8000fe2: 6d9b ldr r3, [r3, #88] @ 0x58 8000fe4: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000fe8: 60fb str r3, [r7, #12] 8000fea: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000fec: 4b15 ldr r3, [pc, #84] @ (8001044 ) 8000fee: 6cdb ldr r3, [r3, #76] @ 0x4c 8000ff0: 4a14 ldr r2, [pc, #80] @ (8001044 ) 8000ff2: f043 0301 orr.w r3, r3, #1 8000ff6: 64d3 str r3, [r2, #76] @ 0x4c 8000ff8: 4b12 ldr r3, [pc, #72] @ (8001044 ) 8000ffa: 6cdb ldr r3, [r3, #76] @ 0x4c 8000ffc: f003 0301 and.w r3, r3, #1 8001000: 60bb str r3, [r7, #8] 8001002: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin; 8001004: 230c movs r3, #12 8001006: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001008: 2302 movs r3, #2 800100a: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 800100c: 2300 movs r3, #0 800100e: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001010: 2300 movs r3, #0 8001012: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; 8001014: 2307 movs r3, #7 8001016: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001018: f107 0354 add.w r3, r7, #84 @ 0x54 800101c: 4619 mov r1, r3 800101e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 8001022: f001 ff01 bl 8002e28 /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); 8001026: 2200 movs r2, #0 8001028: 2100 movs r1, #0 800102a: 2026 movs r0, #38 @ 0x26 800102c: f001 fe07 bl 8002c3e HAL_NVIC_EnableIRQ(USART2_IRQn); 8001030: 2026 movs r0, #38 @ 0x26 8001032: f001 fe1e bl 8002c72 /* USER CODE END USART2_MspInit 1 */ } } 8001036: bf00 nop 8001038: 3768 adds r7, #104 @ 0x68 800103a: 46bd mov sp, r7 800103c: bd80 pop {r7, pc} 800103e: bf00 nop 8001040: 40004400 .word 0x40004400 8001044: 40021000 .word 0x40021000 08001048 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001048: b480 push {r7} 800104a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800104c: bf00 nop 800104e: e7fd b.n 800104c 08001050 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001050: b480 push {r7} 8001052: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001054: bf00 nop 8001056: e7fd b.n 8001054 08001058 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001058: b480 push {r7} 800105a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800105c: bf00 nop 800105e: e7fd b.n 800105c 08001060 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8001060: b480 push {r7} 8001062: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001064: bf00 nop 8001066: e7fd b.n 8001064 08001068 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001068: b480 push {r7} 800106a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800106c: bf00 nop 800106e: e7fd b.n 800106c 08001070 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001070: b480 push {r7} 8001072: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001074: bf00 nop 8001076: 46bd mov sp, r7 8001078: f85d 7b04 ldr.w r7, [sp], #4 800107c: 4770 bx lr 0800107e : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800107e: b480 push {r7} 8001080: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001082: bf00 nop 8001084: 46bd mov sp, r7 8001086: f85d 7b04 ldr.w r7, [sp], #4 800108a: 4770 bx lr 0800108c : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800108c: b480 push {r7} 800108e: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001090: bf00 nop 8001092: 46bd mov sp, r7 8001094: f85d 7b04 ldr.w r7, [sp], #4 8001098: 4770 bx lr 0800109a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800109a: b580 push {r7, lr} 800109c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800109e: f000 f8a5 bl 80011ec /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80010a2: bf00 nop 80010a4: bd80 pop {r7, pc} ... 080010a8 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 80010a8: b580 push {r7, lr} 80010aa: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 80010ac: 4802 ldr r0, [pc, #8] @ (80010b8 ) 80010ae: f003 f87e bl 80041ae /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 80010b2: bf00 nop 80010b4: bd80 pop {r7, pc} 80010b6: bf00 nop 80010b8: 20000100 .word 0x20000100 080010bc : /** * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26. */ void USART2_IRQHandler(void) { 80010bc: b580 push {r7, lr} 80010be: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); 80010c0: 4802 ldr r0, [pc, #8] @ (80010cc ) 80010c2: f003 fe19 bl 8004cf8 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } 80010c6: bf00 nop 80010c8: bd80 pop {r7, pc} 80010ca: bf00 nop 80010cc: 2000014c .word 0x2000014c 080010d0 : * @param None * @retval None */ void SystemInit(void) { 80010d0: b480 push {r7} 80010d2: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 80010d4: 4b06 ldr r3, [pc, #24] @ (80010f0 ) 80010d6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80010da: 4a05 ldr r2, [pc, #20] @ (80010f0 ) 80010dc: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80010e0: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 80010e4: bf00 nop 80010e6: 46bd mov sp, r7 80010e8: f85d 7b04 ldr.w r7, [sp], #4 80010ec: 4770 bx lr 80010ee: bf00 nop 80010f0: e000ed00 .word 0xe000ed00 080010f4 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 80010f4: 480d ldr r0, [pc, #52] @ (800112c ) mov sp, r0 /* set stack pointer */ 80010f6: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 80010f8: f7ff ffea bl 80010d0 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80010fc: 480c ldr r0, [pc, #48] @ (8001130 ) ldr r1, =_edata 80010fe: 490d ldr r1, [pc, #52] @ (8001134 ) ldr r2, =_sidata 8001100: 4a0d ldr r2, [pc, #52] @ (8001138 ) movs r3, #0 8001102: 2300 movs r3, #0 b LoopCopyDataInit 8001104: e002 b.n 800110c 08001106 : CopyDataInit: ldr r4, [r2, r3] 8001106: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001108: 50c4 str r4, [r0, r3] adds r3, r3, #4 800110a: 3304 adds r3, #4 0800110c : LoopCopyDataInit: adds r4, r0, r3 800110c: 18c4 adds r4, r0, r3 cmp r4, r1 800110e: 428c cmp r4, r1 bcc CopyDataInit 8001110: d3f9 bcc.n 8001106 /* Zero fill the bss segment. */ ldr r2, =_sbss 8001112: 4a0a ldr r2, [pc, #40] @ (800113c ) ldr r4, =_ebss 8001114: 4c0a ldr r4, [pc, #40] @ (8001140 ) movs r3, #0 8001116: 2300 movs r3, #0 b LoopFillZerobss 8001118: e001 b.n 800111e 0800111a : FillZerobss: str r3, [r2] 800111a: 6013 str r3, [r2, #0] adds r2, r2, #4 800111c: 3204 adds r2, #4 0800111e : LoopFillZerobss: cmp r2, r4 800111e: 42a2 cmp r2, r4 bcc FillZerobss 8001120: d3fb bcc.n 800111a /* Call static constructors */ bl __libc_init_array 8001122: f005 fdd7 bl 8006cd4 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001126: f7ff fa0d bl 8000544
0800112a : LoopForever: b LoopForever 800112a: e7fe b.n 800112a ldr r0, =_estack 800112c: 20008000 .word 0x20008000 ldr r0, =_sdata 8001130: 20000000 .word 0x20000000 ldr r1, =_edata 8001134: 2000000c .word 0x2000000c ldr r2, =_sidata 8001138: 08006d84 .word 0x08006d84 ldr r2, =_sbss 800113c: 2000000c .word 0x2000000c ldr r4, =_ebss 8001140: 20000244 .word 0x20000244 08001144 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001144: e7fe b.n 8001144 08001146 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001146: b580 push {r7, lr} 8001148: b082 sub sp, #8 800114a: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 800114c: 2300 movs r3, #0 800114e: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001150: 2003 movs r0, #3 8001152: f001 fd69 bl 8002c28 /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8001156: 2000 movs r0, #0 8001158: f000 f80e bl 8001178 800115c: 4603 mov r3, r0 800115e: 2b00 cmp r3, #0 8001160: d002 beq.n 8001168 { status = HAL_ERROR; 8001162: 2301 movs r3, #1 8001164: 71fb strb r3, [r7, #7] 8001166: e001 b.n 800116c } else { /* Init the low level hardware */ HAL_MspInit(); 8001168: f7ff fe3a bl 8000de0 } /* Return function status */ return status; 800116c: 79fb ldrb r3, [r7, #7] } 800116e: 4618 mov r0, r3 8001170: 3708 adds r7, #8 8001172: 46bd mov sp, r7 8001174: bd80 pop {r7, pc} ... 08001178 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001178: b580 push {r7, lr} 800117a: b084 sub sp, #16 800117c: af00 add r7, sp, #0 800117e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8001180: 2300 movs r3, #0 8001182: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) 8001184: 4b16 ldr r3, [pc, #88] @ (80011e0 ) 8001186: 681b ldr r3, [r3, #0] 8001188: 2b00 cmp r3, #0 800118a: d022 beq.n 80011d2 { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 800118c: 4b15 ldr r3, [pc, #84] @ (80011e4 ) 800118e: 681a ldr r2, [r3, #0] 8001190: 4b13 ldr r3, [pc, #76] @ (80011e0 ) 8001192: 681b ldr r3, [r3, #0] 8001194: f44f 717a mov.w r1, #1000 @ 0x3e8 8001198: fbb1 f3f3 udiv r3, r1, r3 800119c: fbb2 f3f3 udiv r3, r2, r3 80011a0: 4618 mov r0, r3 80011a2: f001 fd74 bl 8002c8e 80011a6: 4603 mov r3, r0 80011a8: 2b00 cmp r3, #0 80011aa: d10f bne.n 80011cc { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80011ac: 687b ldr r3, [r7, #4] 80011ae: 2b0f cmp r3, #15 80011b0: d809 bhi.n 80011c6 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80011b2: 2200 movs r2, #0 80011b4: 6879 ldr r1, [r7, #4] 80011b6: f04f 30ff mov.w r0, #4294967295 80011ba: f001 fd40 bl 8002c3e uwTickPrio = TickPriority; 80011be: 4a0a ldr r2, [pc, #40] @ (80011e8 ) 80011c0: 687b ldr r3, [r7, #4] 80011c2: 6013 str r3, [r2, #0] 80011c4: e007 b.n 80011d6 } else { status = HAL_ERROR; 80011c6: 2301 movs r3, #1 80011c8: 73fb strb r3, [r7, #15] 80011ca: e004 b.n 80011d6 } } else { status = HAL_ERROR; 80011cc: 2301 movs r3, #1 80011ce: 73fb strb r3, [r7, #15] 80011d0: e001 b.n 80011d6 } } else { status = HAL_ERROR; 80011d2: 2301 movs r3, #1 80011d4: 73fb strb r3, [r7, #15] } /* Return function status */ return status; 80011d6: 7bfb ldrb r3, [r7, #15] } 80011d8: 4618 mov r0, r3 80011da: 3710 adds r7, #16 80011dc: 46bd mov sp, r7 80011de: bd80 pop {r7, pc} 80011e0: 20000008 .word 0x20000008 80011e4: 20000000 .word 0x20000000 80011e8: 20000004 .word 0x20000004 080011ec : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80011ec: b480 push {r7} 80011ee: af00 add r7, sp, #0 uwTick += uwTickFreq; 80011f0: 4b05 ldr r3, [pc, #20] @ (8001208 ) 80011f2: 681a ldr r2, [r3, #0] 80011f4: 4b05 ldr r3, [pc, #20] @ (800120c ) 80011f6: 681b ldr r3, [r3, #0] 80011f8: 4413 add r3, r2 80011fa: 4a03 ldr r2, [pc, #12] @ (8001208 ) 80011fc: 6013 str r3, [r2, #0] } 80011fe: bf00 nop 8001200: 46bd mov sp, r7 8001202: f85d 7b04 ldr.w r7, [sp], #4 8001206: 4770 bx lr 8001208: 20000240 .word 0x20000240 800120c: 20000008 .word 0x20000008 08001210 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001210: b480 push {r7} 8001212: af00 add r7, sp, #0 return uwTick; 8001214: 4b03 ldr r3, [pc, #12] @ (8001224 ) 8001216: 681b ldr r3, [r3, #0] } 8001218: 4618 mov r0, r3 800121a: 46bd mov sp, r7 800121c: f85d 7b04 ldr.w r7, [sp], #4 8001220: 4770 bx lr 8001222: bf00 nop 8001224: 20000240 .word 0x20000240 08001228 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8001228: b480 push {r7} 800122a: b083 sub sp, #12 800122c: af00 add r7, sp, #0 800122e: 6078 str r0, [r7, #4] 8001230: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8001232: 687b ldr r3, [r7, #4] 8001234: 689b ldr r3, [r3, #8] 8001236: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 800123a: 683b ldr r3, [r7, #0] 800123c: 431a orrs r2, r3 800123e: 687b ldr r3, [r7, #4] 8001240: 609a str r2, [r3, #8] } 8001242: bf00 nop 8001244: 370c adds r7, #12 8001246: 46bd mov sp, r7 8001248: f85d 7b04 ldr.w r7, [sp], #4 800124c: 4770 bx lr 0800124e : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 800124e: b480 push {r7} 8001250: b083 sub sp, #12 8001252: af00 add r7, sp, #0 8001254: 6078 str r0, [r7, #4] 8001256: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); 8001258: 687b ldr r3, [r7, #4] 800125a: 689b ldr r3, [r3, #8] 800125c: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8001260: 683b ldr r3, [r7, #0] 8001262: 431a orrs r2, r3 8001264: 687b ldr r3, [r7, #4] 8001266: 609a str r2, [r3, #8] } 8001268: bf00 nop 800126a: 370c adds r7, #12 800126c: 46bd mov sp, r7 800126e: f85d 7b04 ldr.w r7, [sp], #4 8001272: 4770 bx lr 08001274 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { 8001274: b480 push {r7} 8001276: b083 sub sp, #12 8001278: af00 add r7, sp, #0 800127a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); 800127c: 687b ldr r3, [r7, #4] 800127e: 689b ldr r3, [r3, #8] 8001280: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8001284: 4618 mov r0, r3 8001286: 370c adds r7, #12 8001288: 46bd mov sp, r7 800128a: f85d 7b04 ldr.w r7, [sp], #4 800128e: 4770 bx lr 08001290 : * (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8001290: b480 push {r7} 8001292: b087 sub sp, #28 8001294: af00 add r7, sp, #0 8001296: 60f8 str r0, [r7, #12] 8001298: 60b9 str r1, [r7, #8] 800129a: 607a str r2, [r7, #4] 800129c: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800129e: 68fb ldr r3, [r7, #12] 80012a0: 3360 adds r3, #96 @ 0x60 80012a2: 461a mov r2, r3 80012a4: 68bb ldr r3, [r7, #8] 80012a6: 009b lsls r3, r3, #2 80012a8: 4413 add r3, r2 80012aa: 617b str r3, [r7, #20] MODIFY_REG(*preg, 80012ac: 697b ldr r3, [r7, #20] 80012ae: 681a ldr r2, [r3, #0] 80012b0: 4b08 ldr r3, [pc, #32] @ (80012d4 ) 80012b2: 4013 ands r3, r2 80012b4: 687a ldr r2, [r7, #4] 80012b6: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000 80012ba: 683a ldr r2, [r7, #0] 80012bc: 430a orrs r2, r1 80012be: 4313 orrs r3, r2 80012c0: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80012c4: 697b ldr r3, [r7, #20] 80012c6: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } 80012c8: bf00 nop 80012ca: 371c adds r7, #28 80012cc: 46bd mov sp, r7 80012ce: f85d 7b04 ldr.w r7, [sp], #4 80012d2: 4770 bx lr 80012d4: 03fff000 .word 0x03fff000 080012d8 : * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { 80012d8: b480 push {r7} 80012da: b085 sub sp, #20 80012dc: af00 add r7, sp, #0 80012de: 6078 str r0, [r7, #4] 80012e0: 6039 str r1, [r7, #0] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80012e2: 687b ldr r3, [r7, #4] 80012e4: 3360 adds r3, #96 @ 0x60 80012e6: 461a mov r2, r3 80012e8: 683b ldr r3, [r7, #0] 80012ea: 009b lsls r3, r3, #2 80012ec: 4413 add r3, r2 80012ee: 60fb str r3, [r7, #12] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); 80012f0: 68fb ldr r3, [r7, #12] 80012f2: 681b ldr r3, [r3, #0] 80012f4: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 } 80012f8: 4618 mov r0, r3 80012fa: 3714 adds r7, #20 80012fc: 46bd mov sp, r7 80012fe: f85d 7b04 ldr.w r7, [sp], #4 8001302: 4770 bx lr 08001304 : * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { 8001304: b480 push {r7} 8001306: b087 sub sp, #28 8001308: af00 add r7, sp, #0 800130a: 60f8 str r0, [r7, #12] 800130c: 60b9 str r1, [r7, #8] 800130e: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001310: 68fb ldr r3, [r7, #12] 8001312: 3360 adds r3, #96 @ 0x60 8001314: 461a mov r2, r3 8001316: 68bb ldr r3, [r7, #8] 8001318: 009b lsls r3, r3, #2 800131a: 4413 add r3, r2 800131c: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800131e: 697b ldr r3, [r7, #20] 8001320: 681b ldr r3, [r3, #0] 8001322: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8001326: 687b ldr r3, [r7, #4] 8001328: 431a orrs r2, r3 800132a: 697b ldr r3, [r7, #20] 800132c: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN, OffsetState); } 800132e: bf00 nop 8001330: 371c adds r7, #28 8001332: 46bd mov sp, r7 8001334: f85d 7b04 ldr.w r7, [sp], #4 8001338: 4770 bx lr 0800133a : * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { 800133a: b480 push {r7} 800133c: b087 sub sp, #28 800133e: af00 add r7, sp, #0 8001340: 60f8 str r0, [r7, #12] 8001342: 60b9 str r1, [r7, #8] 8001344: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8001346: 68fb ldr r3, [r7, #12] 8001348: 3360 adds r3, #96 @ 0x60 800134a: 461a mov r2, r3 800134c: 68bb ldr r3, [r7, #8] 800134e: 009b lsls r3, r3, #2 8001350: 4413 add r3, r2 8001352: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8001354: 697b ldr r3, [r7, #20] 8001356: 681b ldr r3, [r3, #0] 8001358: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 800135c: 687b ldr r3, [r7, #4] 800135e: 431a orrs r2, r3 8001360: 697b ldr r3, [r7, #20] 8001362: 601a str r2, [r3, #0] ADC_OFR1_OFFSETPOS, OffsetSign); } 8001364: bf00 nop 8001366: 371c adds r7, #28 8001368: 46bd mov sp, r7 800136a: f85d 7b04 ldr.w r7, [sp], #4 800136e: 4770 bx lr 08001370 : * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { 8001370: b480 push {r7} 8001372: b087 sub sp, #28 8001374: af00 add r7, sp, #0 8001376: 60f8 str r0, [r7, #12] 8001378: 60b9 str r1, [r7, #8] 800137a: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 800137c: 68fb ldr r3, [r7, #12] 800137e: 3360 adds r3, #96 @ 0x60 8001380: 461a mov r2, r3 8001382: 68bb ldr r3, [r7, #8] 8001384: 009b lsls r3, r3, #2 8001386: 4413 add r3, r2 8001388: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800138a: 697b ldr r3, [r7, #20] 800138c: 681b ldr r3, [r3, #0] 800138e: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 8001392: 687b ldr r3, [r7, #4] 8001394: 431a orrs r2, r3 8001396: 697b ldr r3, [r7, #20] 8001398: 601a str r2, [r3, #0] ADC_OFR1_SATEN, OffsetSaturation); } 800139a: bf00 nop 800139c: 371c adds r7, #28 800139e: 46bd mov sp, r7 80013a0: f85d 7b04 ldr.w r7, [sp], #4 80013a4: 4770 bx lr 080013a6 : * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) { 80013a6: b480 push {r7} 80013a8: b083 sub sp, #12 80013aa: af00 add r7, sp, #0 80013ac: 6078 str r0, [r7, #4] 80013ae: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); 80013b0: 687b ldr r3, [r7, #4] 80013b2: 695b ldr r3, [r3, #20] 80013b4: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 80013b8: 683b ldr r3, [r7, #0] 80013ba: 431a orrs r2, r3 80013bc: 687b ldr r3, [r7, #4] 80013be: 615a str r2, [r3, #20] } 80013c0: bf00 nop 80013c2: 370c adds r7, #12 80013c4: 46bd mov sp, r7 80013c6: f85d 7b04 ldr.w r7, [sp], #4 80013ca: 4770 bx lr 080013cc : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { 80013cc: b480 push {r7} 80013ce: b083 sub sp, #12 80013d0: af00 add r7, sp, #0 80013d2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 80013d4: 687b ldr r3, [r7, #4] 80013d6: 68db ldr r3, [r3, #12] 80013d8: f403 6340 and.w r3, r3, #3072 @ 0xc00 80013dc: 2b00 cmp r3, #0 80013de: d101 bne.n 80013e4 80013e0: 2301 movs r3, #1 80013e2: e000 b.n 80013e6 80013e4: 2300 movs r3, #0 } 80013e6: 4618 mov r0, r3 80013e8: 370c adds r7, #12 80013ea: 46bd mov sp, r7 80013ec: f85d 7b04 ldr.w r7, [sp], #4 80013f0: 4770 bx lr 080013f2 : * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 80013f2: b480 push {r7} 80013f4: b087 sub sp, #28 80013f6: af00 add r7, sp, #0 80013f8: 60f8 str r0, [r7, #12] 80013fa: 60b9 str r1, [r7, #8] 80013fc: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, 80013fe: 68fb ldr r3, [r7, #12] 8001400: 3330 adds r3, #48 @ 0x30 8001402: 461a mov r2, r3 8001404: 68bb ldr r3, [r7, #8] 8001406: 0a1b lsrs r3, r3, #8 8001408: 009b lsls r3, r3, #2 800140a: f003 030c and.w r3, r3, #12 800140e: 4413 add r3, r2 8001410: 617b str r3, [r7, #20] ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, 8001412: 697b ldr r3, [r7, #20] 8001414: 681a ldr r2, [r3, #0] 8001416: 68bb ldr r3, [r7, #8] 8001418: f003 031f and.w r3, r3, #31 800141c: 211f movs r1, #31 800141e: fa01 f303 lsl.w r3, r1, r3 8001422: 43db mvns r3, r3 8001424: 401a ands r2, r3 8001426: 687b ldr r3, [r7, #4] 8001428: 0e9b lsrs r3, r3, #26 800142a: f003 011f and.w r1, r3, #31 800142e: 68bb ldr r3, [r7, #8] 8001430: f003 031f and.w r3, r3, #31 8001434: fa01 f303 lsl.w r3, r1, r3 8001438: 431a orrs r2, r3 800143a: 697b ldr r3, [r7, #20] 800143c: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 800143e: bf00 nop 8001440: 371c adds r7, #28 8001442: 46bd mov sp, r7 8001444: f85d 7b04 ldr.w r7, [sp], #4 8001448: 4770 bx lr 0800144a : * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 800144a: b480 push {r7} 800144c: b087 sub sp, #28 800144e: af00 add r7, sp, #0 8001450: 60f8 str r0, [r7, #12] 8001452: 60b9 str r1, [r7, #8] 8001454: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, 8001456: 68fb ldr r3, [r7, #12] 8001458: 3314 adds r3, #20 800145a: 461a mov r2, r3 800145c: 68bb ldr r3, [r7, #8] 800145e: 0e5b lsrs r3, r3, #25 8001460: 009b lsls r3, r3, #2 8001462: f003 0304 and.w r3, r3, #4 8001466: 4413 add r3, r2 8001468: 617b str r3, [r7, #20] ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, 800146a: 697b ldr r3, [r7, #20] 800146c: 681a ldr r2, [r3, #0] 800146e: 68bb ldr r3, [r7, #8] 8001470: 0d1b lsrs r3, r3, #20 8001472: f003 031f and.w r3, r3, #31 8001476: 2107 movs r1, #7 8001478: fa01 f303 lsl.w r3, r1, r3 800147c: 43db mvns r3, r3 800147e: 401a ands r2, r3 8001480: 68bb ldr r3, [r7, #8] 8001482: 0d1b lsrs r3, r3, #20 8001484: f003 031f and.w r3, r3, #31 8001488: 6879 ldr r1, [r7, #4] 800148a: fa01 f303 lsl.w r3, r1, r3 800148e: 431a orrs r2, r3 8001490: 697b ldr r3, [r7, #20] 8001492: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 8001494: bf00 nop 8001496: 371c adds r7, #28 8001498: 46bd mov sp, r7 800149a: f85d 7b04 ldr.w r7, [sp], #4 800149e: 4770 bx lr 080014a0 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 80014a0: b480 push {r7} 80014a2: b085 sub sp, #20 80014a4: af00 add r7, sp, #0 80014a6: 60f8 str r0, [r7, #12] 80014a8: 60b9 str r1, [r7, #8] 80014aa: 607a str r2, [r7, #4] /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 80014ac: 68fb ldr r3, [r7, #12] 80014ae: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0 80014b2: 68bb ldr r3, [r7, #8] 80014b4: f3c3 0312 ubfx r3, r3, #0, #19 80014b8: 43db mvns r3, r3 80014ba: 401a ands r2, r3 80014bc: 687b ldr r3, [r7, #4] 80014be: f003 0318 and.w r3, r3, #24 80014c2: 4908 ldr r1, [pc, #32] @ (80014e4 ) 80014c4: 40d9 lsrs r1, r3 80014c6: 68bb ldr r3, [r7, #8] 80014c8: 400b ands r3, r1 80014ca: f3c3 0312 ubfx r3, r3, #0, #19 80014ce: 431a orrs r2, r3 80014d0: 68fb ldr r3, [r7, #12] 80014d2: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } 80014d6: bf00 nop 80014d8: 3714 adds r7, #20 80014da: 46bd mov sp, r7 80014dc: f85d 7b04 ldr.w r7, [sp], #4 80014e0: 4770 bx lr 80014e2: bf00 nop 80014e4: 0007ffff .word 0x0007ffff 080014e8 : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { 80014e8: b480 push {r7} 80014ea: b083 sub sp, #12 80014ec: af00 add r7, sp, #0 80014ee: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 80014f0: 687b ldr r3, [r7, #4] 80014f2: 689b ldr r3, [r3, #8] 80014f4: f003 031f and.w r3, r3, #31 } 80014f8: 4618 mov r0, r3 80014fa: 370c adds r7, #12 80014fc: 46bd mov sp, r7 80014fe: f85d 7b04 ldr.w r7, [sp], #4 8001502: 4770 bx lr 08001504 : * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B */ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { 8001504: b480 push {r7} 8001506: b083 sub sp, #12 8001508: af00 add r7, sp, #0 800150a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); 800150c: 687b ldr r3, [r7, #4] 800150e: 689b ldr r3, [r3, #8] 8001510: f403 4360 and.w r3, r3, #57344 @ 0xe000 } 8001514: 4618 mov r0, r3 8001516: 370c adds r7, #12 8001518: 46bd mov sp, r7 800151a: f85d 7b04 ldr.w r7, [sp], #4 800151e: 4770 bx lr 08001520 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8001520: b480 push {r7} 8001522: b083 sub sp, #12 8001524: af00 add r7, sp, #0 8001526: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8001528: 687b ldr r3, [r7, #4] 800152a: 689b ldr r3, [r3, #8] 800152c: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000 8001530: f023 033f bic.w r3, r3, #63 @ 0x3f 8001534: 687a ldr r2, [r7, #4] 8001536: 6093 str r3, [r2, #8] } 8001538: bf00 nop 800153a: 370c adds r7, #12 800153c: 46bd mov sp, r7 800153e: f85d 7b04 ldr.w r7, [sp], #4 8001542: 4770 bx lr 08001544 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { 8001544: b480 push {r7} 8001546: b083 sub sp, #12 8001548: af00 add r7, sp, #0 800154a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 800154c: 687b ldr r3, [r7, #4] 800154e: 689b ldr r3, [r3, #8] 8001550: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8001554: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8001558: d101 bne.n 800155e 800155a: 2301 movs r3, #1 800155c: e000 b.n 8001560 800155e: 2300 movs r3, #0 } 8001560: 4618 mov r0, r3 8001562: 370c adds r7, #12 8001564: 46bd mov sp, r7 8001566: f85d 7b04 ldr.w r7, [sp], #4 800156a: 4770 bx lr 0800156c : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 800156c: b480 push {r7} 800156e: b083 sub sp, #12 8001570: af00 add r7, sp, #0 8001572: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001574: 687b ldr r3, [r7, #4] 8001576: 689b ldr r3, [r3, #8] 8001578: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000 800157c: f023 033f bic.w r3, r3, #63 @ 0x3f 8001580: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8001584: 687b ldr r3, [r7, #4] 8001586: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8001588: bf00 nop 800158a: 370c adds r7, #12 800158c: 46bd mov sp, r7 800158e: f85d 7b04 ldr.w r7, [sp], #4 8001592: 4770 bx lr 08001594 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { 8001594: b480 push {r7} 8001596: b083 sub sp, #12 8001598: af00 add r7, sp, #0 800159a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 800159c: 687b ldr r3, [r7, #4] 800159e: 689b ldr r3, [r3, #8] 80015a0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80015a4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80015a8: d101 bne.n 80015ae 80015aa: 2301 movs r3, #1 80015ac: e000 b.n 80015b0 80015ae: 2300 movs r3, #0 } 80015b0: 4618 mov r0, r3 80015b2: 370c adds r7, #12 80015b4: 46bd mov sp, r7 80015b6: f85d 7b04 ldr.w r7, [sp], #4 80015ba: 4770 bx lr 080015bc : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 80015bc: b480 push {r7} 80015be: b083 sub sp, #12 80015c0: af00 add r7, sp, #0 80015c2: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80015c4: 687b ldr r3, [r7, #4] 80015c6: 689b ldr r3, [r3, #8] 80015c8: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 80015cc: f023 033f bic.w r3, r3, #63 @ 0x3f 80015d0: f043 0201 orr.w r2, r3, #1 80015d4: 687b ldr r3, [r7, #4] 80015d6: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 80015d8: bf00 nop 80015da: 370c adds r7, #12 80015dc: 46bd mov sp, r7 80015de: f85d 7b04 ldr.w r7, [sp], #4 80015e2: 4770 bx lr 080015e4 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 80015e4: b480 push {r7} 80015e6: b083 sub sp, #12 80015e8: af00 add r7, sp, #0 80015ea: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80015ec: 687b ldr r3, [r7, #4] 80015ee: 689b ldr r3, [r3, #8] 80015f0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 80015f4: f023 033f bic.w r3, r3, #63 @ 0x3f 80015f8: f043 0202 orr.w r2, r3, #2 80015fc: 687b ldr r3, [r7, #4] 80015fe: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8001600: bf00 nop 8001602: 370c adds r7, #12 8001604: 46bd mov sp, r7 8001606: f85d 7b04 ldr.w r7, [sp], #4 800160a: 4770 bx lr 0800160c : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { 800160c: b480 push {r7} 800160e: b083 sub sp, #12 8001610: af00 add r7, sp, #0 8001612: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8001614: 687b ldr r3, [r7, #4] 8001616: 689b ldr r3, [r3, #8] 8001618: f003 0301 and.w r3, r3, #1 800161c: 2b01 cmp r3, #1 800161e: d101 bne.n 8001624 8001620: 2301 movs r3, #1 8001622: e000 b.n 8001626 8001624: 2300 movs r3, #0 } 8001626: 4618 mov r0, r3 8001628: 370c adds r7, #12 800162a: 46bd mov sp, r7 800162c: f85d 7b04 ldr.w r7, [sp], #4 8001630: 4770 bx lr 08001632 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { 8001632: b480 push {r7} 8001634: b083 sub sp, #12 8001636: af00 add r7, sp, #0 8001638: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 800163a: 687b ldr r3, [r7, #4] 800163c: 689b ldr r3, [r3, #8] 800163e: f003 0302 and.w r3, r3, #2 8001642: 2b02 cmp r3, #2 8001644: d101 bne.n 800164a 8001646: 2301 movs r3, #1 8001648: e000 b.n 800164c 800164a: 2300 movs r3, #0 } 800164c: 4618 mov r0, r3 800164e: 370c adds r7, #12 8001650: 46bd mov sp, r7 8001652: f85d 7b04 ldr.w r7, [sp], #4 8001656: 4770 bx lr 08001658 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8001658: b480 push {r7} 800165a: b083 sub sp, #12 800165c: af00 add r7, sp, #0 800165e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001660: 687b ldr r3, [r7, #4] 8001662: 689b ldr r3, [r3, #8] 8001664: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8001668: f023 033f bic.w r3, r3, #63 @ 0x3f 800166c: f043 0204 orr.w r2, r3, #4 8001670: 687b ldr r3, [r7, #4] 8001672: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8001674: bf00 nop 8001676: 370c adds r7, #12 8001678: 46bd mov sp, r7 800167a: f85d 7b04 ldr.w r7, [sp], #4 800167e: 4770 bx lr 08001680 : * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) { 8001680: b480 push {r7} 8001682: b083 sub sp, #12 8001684: af00 add r7, sp, #0 8001686: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8001688: 687b ldr r3, [r7, #4] 800168a: 689b ldr r3, [r3, #8] 800168c: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8001690: f023 033f bic.w r3, r3, #63 @ 0x3f 8001694: f043 0210 orr.w r2, r3, #16 8001698: 687b ldr r3, [r7, #4] 800169a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP); } 800169c: bf00 nop 800169e: 370c adds r7, #12 80016a0: 46bd mov sp, r7 80016a2: f85d 7b04 ldr.w r7, [sp], #4 80016a6: 4770 bx lr 080016a8 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { 80016a8: b480 push {r7} 80016aa: b083 sub sp, #12 80016ac: af00 add r7, sp, #0 80016ae: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80016b0: 687b ldr r3, [r7, #4] 80016b2: 689b ldr r3, [r3, #8] 80016b4: f003 0304 and.w r3, r3, #4 80016b8: 2b04 cmp r3, #4 80016ba: d101 bne.n 80016c0 80016bc: 2301 movs r3, #1 80016be: e000 b.n 80016c2 80016c0: 2300 movs r3, #0 } 80016c2: 4618 mov r0, r3 80016c4: 370c adds r7, #12 80016c6: 46bd mov sp, r7 80016c8: f85d 7b04 ldr.w r7, [sp], #4 80016cc: 4770 bx lr 080016ce : * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) { 80016ce: b480 push {r7} 80016d0: b083 sub sp, #12 80016d2: af00 add r7, sp, #0 80016d4: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80016d6: 687b ldr r3, [r7, #4] 80016d8: 689b ldr r3, [r3, #8] 80016da: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 80016de: f023 033f bic.w r3, r3, #63 @ 0x3f 80016e2: f043 0220 orr.w r2, r3, #32 80016e6: 687b ldr r3, [r7, #4] 80016e8: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP); } 80016ea: bf00 nop 80016ec: 370c adds r7, #12 80016ee: 46bd mov sp, r7 80016f0: f85d 7b04 ldr.w r7, [sp], #4 80016f4: 4770 bx lr 080016f6 : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { 80016f6: b480 push {r7} 80016f8: b083 sub sp, #12 80016fa: af00 add r7, sp, #0 80016fc: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 80016fe: 687b ldr r3, [r7, #4] 8001700: 689b ldr r3, [r3, #8] 8001702: f003 0308 and.w r3, r3, #8 8001706: 2b08 cmp r3, #8 8001708: d101 bne.n 800170e 800170a: 2301 movs r3, #1 800170c: e000 b.n 8001710 800170e: 2300 movs r3, #0 } 8001710: 4618 mov r0, r3 8001712: 370c adds r7, #12 8001714: 46bd mov sp, r7 8001716: f85d 7b04 ldr.w r7, [sp], #4 800171a: 4770 bx lr 0800171c : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 800171c: b590 push {r4, r7, lr} 800171e: b089 sub sp, #36 @ 0x24 8001720: af00 add r7, sp, #0 8001722: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001724: 2300 movs r3, #0 8001726: 77fb strb r3, [r7, #31] uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0UL; 8001728: 2300 movs r3, #0 800172a: 60fb str r3, [r7, #12] /* Check ADC handle */ if (hadc == NULL) 800172c: 687b ldr r3, [r7, #4] 800172e: 2b00 cmp r3, #0 8001730: d101 bne.n 8001736 { return HAL_ERROR; 8001732: 2301 movs r3, #1 8001734: e167 b.n 8001a06 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 8001736: 687b ldr r3, [r7, #4] 8001738: 695b ldr r3, [r3, #20] 800173a: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 800173c: 687b ldr r3, [r7, #4] 800173e: 6ddb ldr r3, [r3, #92] @ 0x5c 8001740: 2b00 cmp r3, #0 8001742: d109 bne.n 8001758 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8001744: 6878 ldr r0, [r7, #4] 8001746: f7ff fb6f bl 8000e28 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800174a: 687b ldr r3, [r7, #4] 800174c: 2200 movs r2, #0 800174e: 661a str r2, [r3, #96] @ 0x60 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8001750: 687b ldr r3, [r7, #4] 8001752: 2200 movs r2, #0 8001754: f883 2058 strb.w r2, [r3, #88] @ 0x58 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8001758: 687b ldr r3, [r7, #4] 800175a: 681b ldr r3, [r3, #0] 800175c: 4618 mov r0, r3 800175e: f7ff fef1 bl 8001544 8001762: 4603 mov r3, r0 8001764: 2b00 cmp r3, #0 8001766: d004 beq.n 8001772 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8001768: 687b ldr r3, [r7, #4] 800176a: 681b ldr r3, [r3, #0] 800176c: 4618 mov r0, r3 800176e: f7ff fed7 bl 8001520 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8001772: 687b ldr r3, [r7, #4] 8001774: 681b ldr r3, [r3, #0] 8001776: 4618 mov r0, r3 8001778: f7ff ff0c bl 8001594 800177c: 4603 mov r3, r0 800177e: 2b00 cmp r3, #0 8001780: d115 bne.n 80017ae { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8001782: 687b ldr r3, [r7, #4] 8001784: 681b ldr r3, [r3, #0] 8001786: 4618 mov r0, r3 8001788: f7ff fef0 bl 800156c /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800178c: 4ba0 ldr r3, [pc, #640] @ (8001a10 ) 800178e: 681b ldr r3, [r3, #0] 8001790: 099b lsrs r3, r3, #6 8001792: 4aa0 ldr r2, [pc, #640] @ (8001a14 ) 8001794: fba2 2303 umull r2, r3, r2, r3 8001798: 099b lsrs r3, r3, #6 800179a: 3301 adds r3, #1 800179c: 005b lsls r3, r3, #1 800179e: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 80017a0: e002 b.n 80017a8 { wait_loop_index--; 80017a2: 68fb ldr r3, [r7, #12] 80017a4: 3b01 subs r3, #1 80017a6: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 80017a8: 68fb ldr r3, [r7, #12] 80017aa: 2b00 cmp r3, #0 80017ac: d1f9 bne.n 80017a2 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 80017ae: 687b ldr r3, [r7, #4] 80017b0: 681b ldr r3, [r3, #0] 80017b2: 4618 mov r0, r3 80017b4: f7ff feee bl 8001594 80017b8: 4603 mov r3, r0 80017ba: 2b00 cmp r3, #0 80017bc: d10d bne.n 80017da { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80017be: 687b ldr r3, [r7, #4] 80017c0: 6ddb ldr r3, [r3, #92] @ 0x5c 80017c2: f043 0210 orr.w r2, r3, #16 80017c6: 687b ldr r3, [r7, #4] 80017c8: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80017ca: 687b ldr r3, [r7, #4] 80017cc: 6e1b ldr r3, [r3, #96] @ 0x60 80017ce: f043 0201 orr.w r2, r3, #1 80017d2: 687b ldr r3, [r7, #4] 80017d4: 661a str r2, [r3, #96] @ 0x60 tmp_hal_status = HAL_ERROR; 80017d6: 2301 movs r3, #1 80017d8: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80017da: 687b ldr r3, [r7, #4] 80017dc: 681b ldr r3, [r3, #0] 80017de: 4618 mov r0, r3 80017e0: f7ff ff62 bl 80016a8 80017e4: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 80017e6: 687b ldr r3, [r7, #4] 80017e8: 6ddb ldr r3, [r3, #92] @ 0x5c 80017ea: f003 0310 and.w r3, r3, #16 80017ee: 2b00 cmp r3, #0 80017f0: f040 8100 bne.w 80019f4 && (tmp_adc_is_conversion_on_going_regular == 0UL) 80017f4: 697b ldr r3, [r7, #20] 80017f6: 2b00 cmp r3, #0 80017f8: f040 80fc bne.w 80019f4 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80017fc: 687b ldr r3, [r7, #4] 80017fe: 6ddb ldr r3, [r3, #92] @ 0x5c 8001800: f423 7381 bic.w r3, r3, #258 @ 0x102 8001804: f043 0202 orr.w r2, r3, #2 8001808: 687b ldr r3, [r7, #4] 800180a: 65da str r2, [r3, #92] @ 0x5c /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 800180c: 687b ldr r3, [r7, #4] 800180e: 681b ldr r3, [r3, #0] 8001810: 4618 mov r0, r3 8001812: f7ff fefb bl 800160c 8001816: 4603 mov r3, r0 8001818: 2b00 cmp r3, #0 800181a: d111 bne.n 8001840 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800181c: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 8001820: f7ff fef4 bl 800160c 8001824: 4604 mov r4, r0 8001826: 487c ldr r0, [pc, #496] @ (8001a18 ) 8001828: f7ff fef0 bl 800160c 800182c: 4603 mov r3, r0 800182e: 4323 orrs r3, r4 8001830: 2b00 cmp r3, #0 8001832: d105 bne.n 8001840 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8001834: 687b ldr r3, [r7, #4] 8001836: 685b ldr r3, [r3, #4] 8001838: 4619 mov r1, r3 800183a: 4878 ldr r0, [pc, #480] @ (8001a1c ) 800183c: f7ff fcf4 bl 8001228 /* - external trigger polarity Init.ExternalTrigConvEdge */ /* - continuous conversion mode Init.ContinuousConvMode */ /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001840: 687b ldr r3, [r7, #4] 8001842: 7f5b ldrb r3, [r3, #29] 8001844: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8001846: 687b ldr r3, [r7, #4] 8001848: 6bdb ldr r3, [r3, #60] @ 0x3c tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800184a: 431a orrs r2, r3 hadc->Init.DataAlign | 800184c: 687b ldr r3, [r7, #4] 800184e: 68db ldr r3, [r3, #12] hadc->Init.Overrun | 8001850: 431a orrs r2, r3 hadc->Init.Resolution | 8001852: 687b ldr r3, [r7, #4] 8001854: 689b ldr r3, [r3, #8] hadc->Init.DataAlign | 8001856: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8001858: 687b ldr r3, [r7, #4] 800185a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800185e: 041b lsls r3, r3, #16 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8001860: 4313 orrs r3, r2 8001862: 61bb str r3, [r7, #24] if (hadc->Init.DiscontinuousConvMode == ENABLE) 8001864: 687b ldr r3, [r7, #4] 8001866: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 800186a: 2b01 cmp r3, #1 800186c: d106 bne.n 800187c { tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 800186e: 687b ldr r3, [r7, #4] 8001870: 6a9b ldr r3, [r3, #40] @ 0x28 8001872: 3b01 subs r3, #1 8001874: 045b lsls r3, r3, #17 8001876: 69ba ldr r2, [r7, #24] 8001878: 4313 orrs r3, r2 800187a: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 800187c: 687b ldr r3, [r7, #4] 800187e: 6adb ldr r3, [r3, #44] @ 0x2c 8001880: 2b00 cmp r3, #0 8001882: d009 beq.n 8001898 { tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001884: 687b ldr r3, [r7, #4] 8001886: 6adb ldr r3, [r3, #44] @ 0x2c 8001888: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 800188c: 687b ldr r3, [r7, #4] 800188e: 6b1b ldr r3, [r3, #48] @ 0x30 8001890: 4313 orrs r3, r2 tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8001892: 69ba ldr r2, [r7, #24] 8001894: 4313 orrs r3, r2 8001896: 61bb str r3, [r7, #24] ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); 8001898: 687b ldr r3, [r7, #4] 800189a: 681b ldr r3, [r3, #0] 800189c: 68da ldr r2, [r3, #12] 800189e: 4b60 ldr r3, [pc, #384] @ (8001a20 ) 80018a0: 4013 ands r3, r2 80018a2: 687a ldr r2, [r7, #4] 80018a4: 6812 ldr r2, [r2, #0] 80018a6: 69b9 ldr r1, [r7, #24] 80018a8: 430b orrs r3, r1 80018aa: 60d3 str r3, [r2, #12] /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); 80018ac: 687b ldr r3, [r7, #4] 80018ae: 681b ldr r3, [r3, #0] 80018b0: 691b ldr r3, [r3, #16] 80018b2: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000 80018b6: 687b ldr r3, [r7, #4] 80018b8: 6b5a ldr r2, [r3, #52] @ 0x34 80018ba: 687b ldr r3, [r7, #4] 80018bc: 681b ldr r3, [r3, #0] 80018be: 430a orrs r2, r1 80018c0: 611a str r2, [r3, #16] /* conversion on going on regular and injected groups: */ /* - Gain Compensation Init.GainCompensation */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80018c2: 687b ldr r3, [r7, #4] 80018c4: 681b ldr r3, [r3, #0] 80018c6: 4618 mov r0, r3 80018c8: f7ff ff15 bl 80016f6 80018cc: 6138 str r0, [r7, #16] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80018ce: 697b ldr r3, [r7, #20] 80018d0: 2b00 cmp r3, #0 80018d2: d16d bne.n 80019b0 && (tmp_adc_is_conversion_on_going_injected == 0UL) 80018d4: 693b ldr r3, [r7, #16] 80018d6: 2b00 cmp r3, #0 80018d8: d16a bne.n 80019b0 ) { tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 80018da: 687b ldr r3, [r7, #4] 80018dc: 7f1b ldrb r3, [r3, #28] tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | 80018de: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); 80018e0: 687b ldr r3, [r7, #4] 80018e2: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 80018e6: 005b lsls r3, r3, #1 tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | 80018e8: 4313 orrs r3, r2 80018ea: 61bb str r3, [r7, #24] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); 80018ec: 687b ldr r3, [r7, #4] 80018ee: 681b ldr r3, [r3, #0] 80018f0: 68db ldr r3, [r3, #12] 80018f2: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80018f6: f023 0302 bic.w r3, r3, #2 80018fa: 687a ldr r2, [r7, #4] 80018fc: 6812 ldr r2, [r2, #0] 80018fe: 69b9 ldr r1, [r7, #24] 8001900: 430b orrs r3, r1 8001902: 60d3 str r3, [r2, #12] if (hadc->Init.GainCompensation != 0UL) 8001904: 687b ldr r3, [r7, #4] 8001906: 691b ldr r3, [r3, #16] 8001908: 2b00 cmp r3, #0 800190a: d017 beq.n 800193c { SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 800190c: 687b ldr r3, [r7, #4] 800190e: 681b ldr r3, [r3, #0] 8001910: 691a ldr r2, [r3, #16] 8001912: 687b ldr r3, [r7, #4] 8001914: 681b ldr r3, [r3, #0] 8001916: f442 3280 orr.w r2, r2, #65536 @ 0x10000 800191a: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); 800191c: 687b ldr r3, [r7, #4] 800191e: 681b ldr r3, [r3, #0] 8001920: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 8001924: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 8001928: f023 033f bic.w r3, r3, #63 @ 0x3f 800192c: 687a ldr r2, [r7, #4] 800192e: 6911 ldr r1, [r2, #16] 8001930: 687a ldr r2, [r7, #4] 8001932: 6812 ldr r2, [r2, #0] 8001934: 430b orrs r3, r1 8001936: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 800193a: e013 b.n 8001964 } else { CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); 800193c: 687b ldr r3, [r7, #4] 800193e: 681b ldr r3, [r3, #0] 8001940: 691a ldr r2, [r3, #16] 8001942: 687b ldr r3, [r7, #4] 8001944: 681b ldr r3, [r3, #0] 8001946: f422 3280 bic.w r2, r2, #65536 @ 0x10000 800194a: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); 800194c: 687b ldr r3, [r7, #4] 800194e: 681b ldr r3, [r3, #0] 8001950: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 8001954: 687a ldr r2, [r7, #4] 8001956: 6812 ldr r2, [r2, #0] 8001958: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800195c: f023 033f bic.w r3, r3, #63 @ 0x3f 8001960: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 } if (hadc->Init.OversamplingMode == ENABLE) 8001964: 687b ldr r3, [r7, #4] 8001966: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800196a: 2b01 cmp r3, #1 800196c: d118 bne.n 80019a0 /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, 800196e: 687b ldr r3, [r7, #4] 8001970: 681b ldr r3, [r3, #0] 8001972: 691b ldr r3, [r3, #16] 8001974: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 8001978: f023 0304 bic.w r3, r3, #4 800197c: 687a ldr r2, [r7, #4] 800197e: 6c51 ldr r1, [r2, #68] @ 0x44 8001980: 687a ldr r2, [r7, #4] 8001982: 6c92 ldr r2, [r2, #72] @ 0x48 8001984: 4311 orrs r1, r2 8001986: 687a ldr r2, [r7, #4] 8001988: 6cd2 ldr r2, [r2, #76] @ 0x4c 800198a: 4311 orrs r1, r2 800198c: 687a ldr r2, [r7, #4] 800198e: 6d12 ldr r2, [r2, #80] @ 0x50 8001990: 430a orrs r2, r1 8001992: 431a orrs r2, r3 8001994: 687b ldr r3, [r7, #4] 8001996: 681b ldr r3, [r3, #0] 8001998: f042 0201 orr.w r2, r2, #1 800199c: 611a str r2, [r3, #16] 800199e: e007 b.n 80019b0 ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 80019a0: 687b ldr r3, [r7, #4] 80019a2: 681b ldr r3, [r3, #0] 80019a4: 691a ldr r2, [r3, #16] 80019a6: 687b ldr r3, [r7, #4] 80019a8: 681b ldr r3, [r3, #0] 80019aa: f022 0201 bic.w r2, r2, #1 80019ae: 611a str r2, [r3, #16] /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80019b0: 687b ldr r3, [r7, #4] 80019b2: 695b ldr r3, [r3, #20] 80019b4: 2b01 cmp r3, #1 80019b6: d10c bne.n 80019d2 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 80019b8: 687b ldr r3, [r7, #4] 80019ba: 681b ldr r3, [r3, #0] 80019bc: 6b1b ldr r3, [r3, #48] @ 0x30 80019be: f023 010f bic.w r1, r3, #15 80019c2: 687b ldr r3, [r7, #4] 80019c4: 6a1b ldr r3, [r3, #32] 80019c6: 1e5a subs r2, r3, #1 80019c8: 687b ldr r3, [r7, #4] 80019ca: 681b ldr r3, [r3, #0] 80019cc: 430a orrs r2, r1 80019ce: 631a str r2, [r3, #48] @ 0x30 80019d0: e007 b.n 80019e2 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80019d2: 687b ldr r3, [r7, #4] 80019d4: 681b ldr r3, [r3, #0] 80019d6: 6b1a ldr r2, [r3, #48] @ 0x30 80019d8: 687b ldr r3, [r7, #4] 80019da: 681b ldr r3, [r3, #0] 80019dc: f022 020f bic.w r2, r2, #15 80019e0: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80019e2: 687b ldr r3, [r7, #4] 80019e4: 6ddb ldr r3, [r3, #92] @ 0x5c 80019e6: f023 0303 bic.w r3, r3, #3 80019ea: f043 0201 orr.w r2, r3, #1 80019ee: 687b ldr r3, [r7, #4] 80019f0: 65da str r2, [r3, #92] @ 0x5c 80019f2: e007 b.n 8001a04 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80019f4: 687b ldr r3, [r7, #4] 80019f6: 6ddb ldr r3, [r3, #92] @ 0x5c 80019f8: f043 0210 orr.w r2, r3, #16 80019fc: 687b ldr r3, [r7, #4] 80019fe: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 8001a00: 2301 movs r3, #1 8001a02: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 8001a04: 7ffb ldrb r3, [r7, #31] } 8001a06: 4618 mov r0, r3 8001a08: 3724 adds r7, #36 @ 0x24 8001a0a: 46bd mov sp, r7 8001a0c: bd90 pop {r4, r7, pc} 8001a0e: bf00 nop 8001a10: 20000000 .word 0x20000000 8001a14: 053e2d63 .word 0x053e2d63 8001a18: 50000100 .word 0x50000100 8001a1c: 50000300 .word 0x50000300 8001a20: fff04007 .word 0xfff04007 08001a24 : * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { 8001a24: b580 push {r7, lr} 8001a26: b086 sub sp, #24 8001a28: af00 add r7, sp, #0 8001a2a: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8001a2c: 4859 ldr r0, [pc, #356] @ (8001b94 ) 8001a2e: f7ff fd5b bl 80014e8 8001a32: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8001a34: 687b ldr r3, [r7, #4] 8001a36: 681b ldr r3, [r3, #0] 8001a38: 4618 mov r0, r3 8001a3a: f7ff fe35 bl 80016a8 8001a3e: 4603 mov r3, r0 8001a40: 2b00 cmp r3, #0 8001a42: f040 809f bne.w 8001b84 { /* Process locked */ __HAL_LOCK(hadc); 8001a46: 687b ldr r3, [r7, #4] 8001a48: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8001a4c: 2b01 cmp r3, #1 8001a4e: d101 bne.n 8001a54 8001a50: 2302 movs r3, #2 8001a52: e09a b.n 8001b8a 8001a54: 687b ldr r3, [r7, #4] 8001a56: 2201 movs r2, #1 8001a58: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8001a5c: 6878 ldr r0, [r7, #4] 8001a5e: f000 fe63 bl 8002728 8001a62: 4603 mov r3, r0 8001a64: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8001a66: 7dfb ldrb r3, [r7, #23] 8001a68: 2b00 cmp r3, #0 8001a6a: f040 8086 bne.w 8001b7a { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8001a6e: 687b ldr r3, [r7, #4] 8001a70: 6ddb ldr r3, [r3, #92] @ 0x5c 8001a72: f423 6370 bic.w r3, r3, #3840 @ 0xf00 8001a76: f023 0301 bic.w r3, r3, #1 8001a7a: f443 7280 orr.w r2, r3, #256 @ 0x100 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 65da str r2, [r3, #92] @ 0x5c #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8001a82: 687b ldr r3, [r7, #4] 8001a84: 681b ldr r3, [r3, #0] 8001a86: 4a44 ldr r2, [pc, #272] @ (8001b98 ) 8001a88: 4293 cmp r3, r2 8001a8a: d002 beq.n 8001a92 8001a8c: 687b ldr r3, [r7, #4] 8001a8e: 681b ldr r3, [r3, #0] 8001a90: e001 b.n 8001a96 8001a92: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8001a96: 687a ldr r2, [r7, #4] 8001a98: 6812 ldr r2, [r2, #0] 8001a9a: 4293 cmp r3, r2 8001a9c: d002 beq.n 8001aa4 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8001a9e: 693b ldr r3, [r7, #16] 8001aa0: 2b00 cmp r3, #0 8001aa2: d105 bne.n 8001ab0 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001aa4: 687b ldr r3, [r7, #4] 8001aa6: 6ddb ldr r3, [r3, #92] @ 0x5c 8001aa8: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8001aac: 687b ldr r3, [r7, #4] 8001aae: 65da str r2, [r3, #92] @ 0x5c } #endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 8001ab0: 687b ldr r3, [r7, #4] 8001ab2: 6ddb ldr r3, [r3, #92] @ 0x5c 8001ab4: f403 5380 and.w r3, r3, #4096 @ 0x1000 8001ab8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8001abc: d106 bne.n 8001acc { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8001abe: 687b ldr r3, [r7, #4] 8001ac0: 6e1b ldr r3, [r3, #96] @ 0x60 8001ac2: f023 0206 bic.w r2, r3, #6 8001ac6: 687b ldr r3, [r7, #4] 8001ac8: 661a str r2, [r3, #96] @ 0x60 8001aca: e002 b.n 8001ad2 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8001acc: 687b ldr r3, [r7, #4] 8001ace: 2200 movs r2, #0 8001ad0: 661a str r2, [r3, #96] @ 0x60 } /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8001ad2: 687b ldr r3, [r7, #4] 8001ad4: 681b ldr r3, [r3, #0] 8001ad6: 221c movs r2, #28 8001ad8: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8001ada: 687b ldr r3, [r7, #4] 8001adc: 2200 movs r2, #0 8001ade: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8001ae2: 687b ldr r3, [r7, #4] 8001ae4: 681b ldr r3, [r3, #0] 8001ae6: 4a2c ldr r2, [pc, #176] @ (8001b98 ) 8001ae8: 4293 cmp r3, r2 8001aea: d002 beq.n 8001af2 8001aec: 687b ldr r3, [r7, #4] 8001aee: 681b ldr r3, [r3, #0] 8001af0: e001 b.n 8001af6 8001af2: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8001af6: 687a ldr r2, [r7, #4] 8001af8: 6812 ldr r2, [r2, #0] 8001afa: 4293 cmp r3, r2 8001afc: d008 beq.n 8001b10 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8001afe: 693b ldr r3, [r7, #16] 8001b00: 2b00 cmp r3, #0 8001b02: d005 beq.n 8001b10 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8001b04: 693b ldr r3, [r7, #16] 8001b06: 2b05 cmp r3, #5 8001b08: d002 beq.n 8001b10 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8001b0a: 693b ldr r3, [r7, #16] 8001b0c: 2b09 cmp r3, #9 8001b0e: d114 bne.n 8001b3a ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) 8001b10: 687b ldr r3, [r7, #4] 8001b12: 681b ldr r3, [r3, #0] 8001b14: 68db ldr r3, [r3, #12] 8001b16: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001b1a: 2b00 cmp r3, #0 8001b1c: d007 beq.n 8001b2e { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001b1e: 687b ldr r3, [r7, #4] 8001b20: 6ddb ldr r3, [r3, #92] @ 0x5c 8001b22: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8001b26: f443 5280 orr.w r2, r3, #4096 @ 0x1000 8001b2a: 687b ldr r3, [r7, #4] 8001b2c: 65da str r2, [r3, #92] @ 0x5c } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 8001b2e: 687b ldr r3, [r7, #4] 8001b30: 681b ldr r3, [r3, #0] 8001b32: 4618 mov r0, r3 8001b34: f7ff fd90 bl 8001658 8001b38: e026 b.n 8001b88 } else { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8001b3a: 687b ldr r3, [r7, #4] 8001b3c: 6ddb ldr r3, [r3, #92] @ 0x5c 8001b3e: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 8001b42: 687b ldr r3, [r7, #4] 8001b44: 65da str r2, [r3, #92] @ 0x5c /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); 8001b46: 687b ldr r3, [r7, #4] 8001b48: 681b ldr r3, [r3, #0] 8001b4a: 4a13 ldr r2, [pc, #76] @ (8001b98 ) 8001b4c: 4293 cmp r3, r2 8001b4e: d002 beq.n 8001b56 8001b50: 687b ldr r3, [r7, #4] 8001b52: 681b ldr r3, [r3, #0] 8001b54: e001 b.n 8001b5a 8001b56: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8001b5a: 60fb str r3, [r7, #12] if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) 8001b5c: 68fb ldr r3, [r7, #12] 8001b5e: 68db ldr r3, [r3, #12] 8001b60: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001b64: 2b00 cmp r3, #0 8001b66: d00f beq.n 8001b88 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 8001b68: 687b ldr r3, [r7, #4] 8001b6a: 6ddb ldr r3, [r3, #92] @ 0x5c 8001b6c: f423 5340 bic.w r3, r3, #12288 @ 0x3000 8001b70: f443 5280 orr.w r2, r3, #4096 @ 0x1000 8001b74: 687b ldr r3, [r7, #4] 8001b76: 65da str r2, [r3, #92] @ 0x5c 8001b78: e006 b.n 8001b88 #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8001b7a: 687b ldr r3, [r7, #4] 8001b7c: 2200 movs r2, #0 8001b7e: f883 2058 strb.w r2, [r3, #88] @ 0x58 8001b82: e001 b.n 8001b88 } } else { tmp_hal_status = HAL_BUSY; 8001b84: 2302 movs r3, #2 8001b86: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8001b88: 7dfb ldrb r3, [r7, #23] } 8001b8a: 4618 mov r0, r3 8001b8c: 3718 adds r7, #24 8001b8e: 46bd mov sp, r7 8001b90: bd80 pop {r7, pc} 8001b92: bf00 nop 8001b94: 50000300 .word 0x50000300 8001b98: 50000100 .word 0x50000100 08001b9c : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { 8001b9c: b580 push {r7, lr} 8001b9e: b084 sub sp, #16 8001ba0: af00 add r7, sp, #0 8001ba2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); 8001ba4: 687b ldr r3, [r7, #4] 8001ba6: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8001baa: 2b01 cmp r3, #1 8001bac: d101 bne.n 8001bb2 8001bae: 2302 movs r3, #2 8001bb0: e023 b.n 8001bfa 8001bb2: 687b ldr r3, [r7, #4] 8001bb4: 2201 movs r2, #1 8001bb6: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); 8001bba: 2103 movs r1, #3 8001bbc: 6878 ldr r0, [r7, #4] 8001bbe: f000 fcf7 bl 80025b0 8001bc2: 4603 mov r3, r0 8001bc4: 73fb strb r3, [r7, #15] /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) 8001bc6: 7bfb ldrb r3, [r7, #15] 8001bc8: 2b00 cmp r3, #0 8001bca: d111 bne.n 8001bf0 { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); 8001bcc: 6878 ldr r0, [r7, #4] 8001bce: f000 fe31 bl 8002834 8001bd2: 4603 mov r3, r0 8001bd4: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8001bd6: 7bfb ldrb r3, [r7, #15] 8001bd8: 2b00 cmp r3, #0 8001bda: d109 bne.n 8001bf0 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8001bdc: 687b ldr r3, [r7, #4] 8001bde: 6ddb ldr r3, [r3, #92] @ 0x5c 8001be0: f423 5388 bic.w r3, r3, #4352 @ 0x1100 8001be4: f023 0301 bic.w r3, r3, #1 8001be8: f043 0201 orr.w r2, r3, #1 8001bec: 687b ldr r3, [r7, #4] 8001bee: 65da str r2, [r3, #92] @ 0x5c HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); 8001bf0: 687b ldr r3, [r7, #4] 8001bf2: 2200 movs r2, #0 8001bf4: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; 8001bf8: 7bfb ldrb r3, [r7, #15] } 8001bfa: 4618 mov r0, r3 8001bfc: 3710 adds r7, #16 8001bfe: 46bd mov sp, r7 8001c00: bd80 pop {r7, pc} ... 08001c04 : * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { 8001c04: b580 push {r7, lr} 8001c06: b088 sub sp, #32 8001c08: af00 add r7, sp, #0 8001c0a: 6078 str r0, [r7, #4] 8001c0c: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8001c0e: 4867 ldr r0, [pc, #412] @ (8001dac ) 8001c10: f7ff fc6a bl 80014e8 8001c14: 6178 str r0, [r7, #20] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) 8001c16: 687b ldr r3, [r7, #4] 8001c18: 699b ldr r3, [r3, #24] 8001c1a: 2b08 cmp r3, #8 8001c1c: d102 bne.n 8001c24 { tmp_Flag_End = ADC_FLAG_EOS; 8001c1e: 2308 movs r3, #8 8001c20: 61fb str r3, [r7, #28] 8001c22: e02a b.n 8001c7a /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8001c24: 697b ldr r3, [r7, #20] 8001c26: 2b00 cmp r3, #0 8001c28: d005 beq.n 8001c36 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8001c2a: 697b ldr r3, [r7, #20] 8001c2c: 2b05 cmp r3, #5 8001c2e: d002 beq.n 8001c36 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8001c30: 697b ldr r3, [r7, #20] 8001c32: 2b09 cmp r3, #9 8001c34: d111 bne.n 8001c5a ) { /* Check ADC DMA mode in independent mode on ADC group regular */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) 8001c36: 687b ldr r3, [r7, #4] 8001c38: 681b ldr r3, [r3, #0] 8001c3a: 68db ldr r3, [r3, #12] 8001c3c: f003 0301 and.w r3, r3, #1 8001c40: 2b00 cmp r3, #0 8001c42: d007 beq.n 8001c54 { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001c44: 687b ldr r3, [r7, #4] 8001c46: 6ddb ldr r3, [r3, #92] @ 0x5c 8001c48: f043 0220 orr.w r2, r3, #32 8001c4c: 687b ldr r3, [r7, #4] 8001c4e: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 8001c50: 2301 movs r3, #1 8001c52: e0a6 b.n 8001da2 } else { tmp_Flag_End = (ADC_FLAG_EOC); 8001c54: 2304 movs r3, #4 8001c56: 61fb str r3, [r7, #28] if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) 8001c58: e00f b.n 8001c7a } } else { /* Check ADC DMA mode in multimode on ADC group regular */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) 8001c5a: 4854 ldr r0, [pc, #336] @ (8001dac ) 8001c5c: f7ff fc52 bl 8001504 8001c60: 4603 mov r3, r0 8001c62: 2b00 cmp r3, #0 8001c64: d007 beq.n 8001c76 { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8001c66: 687b ldr r3, [r7, #4] 8001c68: 6ddb ldr r3, [r3, #92] @ 0x5c 8001c6a: f043 0220 orr.w r2, r3, #32 8001c6e: 687b ldr r3, [r7, #4] 8001c70: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; 8001c72: 2301 movs r3, #1 8001c74: e095 b.n 8001da2 } else { tmp_Flag_End = (ADC_FLAG_EOC); 8001c76: 2304 movs r3, #4 8001c78: 61fb str r3, [r7, #28] } #endif /* ADC_MULTIMODE_SUPPORT */ } /* Get tick count */ tickstart = HAL_GetTick(); 8001c7a: f7ff fac9 bl 8001210 8001c7e: 6138 str r0, [r7, #16] /* Wait until End of unitary conversion or sequence conversions flag is raised */ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) 8001c80: e021 b.n 8001cc6 { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) 8001c82: 683b ldr r3, [r7, #0] 8001c84: f1b3 3fff cmp.w r3, #4294967295 8001c88: d01d beq.n 8001cc6 { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) 8001c8a: f7ff fac1 bl 8001210 8001c8e: 4602 mov r2, r0 8001c90: 693b ldr r3, [r7, #16] 8001c92: 1ad3 subs r3, r2, r3 8001c94: 683a ldr r2, [r7, #0] 8001c96: 429a cmp r2, r3 8001c98: d302 bcc.n 8001ca0 8001c9a: 683b ldr r3, [r7, #0] 8001c9c: 2b00 cmp r3, #0 8001c9e: d112 bne.n 8001cc6 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) 8001ca0: 687b ldr r3, [r7, #4] 8001ca2: 681b ldr r3, [r3, #0] 8001ca4: 681a ldr r2, [r3, #0] 8001ca6: 69fb ldr r3, [r7, #28] 8001ca8: 4013 ands r3, r2 8001caa: 2b00 cmp r3, #0 8001cac: d10b bne.n 8001cc6 { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 8001cae: 687b ldr r3, [r7, #4] 8001cb0: 6ddb ldr r3, [r3, #92] @ 0x5c 8001cb2: f043 0204 orr.w r2, r3, #4 8001cb6: 687b ldr r3, [r7, #4] 8001cb8: 65da str r2, [r3, #92] @ 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); 8001cba: 687b ldr r3, [r7, #4] 8001cbc: 2200 movs r2, #0 8001cbe: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_TIMEOUT; 8001cc2: 2303 movs r3, #3 8001cc4: e06d b.n 8001da2 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) 8001cc6: 687b ldr r3, [r7, #4] 8001cc8: 681b ldr r3, [r3, #0] 8001cca: 681a ldr r2, [r3, #0] 8001ccc: 69fb ldr r3, [r7, #28] 8001cce: 4013 ands r3, r2 8001cd0: 2b00 cmp r3, #0 8001cd2: d0d6 beq.n 8001c82 } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8001cd4: 687b ldr r3, [r7, #4] 8001cd6: 6ddb ldr r3, [r3, #92] @ 0x5c 8001cd8: f443 7200 orr.w r2, r3, #512 @ 0x200 8001cdc: 687b ldr r3, [r7, #4] 8001cde: 65da str r2, [r3, #92] @ 0x5c /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8001ce0: 687b ldr r3, [r7, #4] 8001ce2: 681b ldr r3, [r3, #0] 8001ce4: 4618 mov r0, r3 8001ce6: f7ff fb71 bl 80013cc 8001cea: 4603 mov r3, r0 8001cec: 2b00 cmp r3, #0 8001cee: d01c beq.n 8001d2a && (hadc->Init.ContinuousConvMode == DISABLE) 8001cf0: 687b ldr r3, [r7, #4] 8001cf2: 7f5b ldrb r3, [r3, #29] 8001cf4: 2b00 cmp r3, #0 8001cf6: d118 bne.n 8001d2a ) { /* Check whether end of sequence is reached */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) 8001cf8: 687b ldr r3, [r7, #4] 8001cfa: 681b ldr r3, [r3, #0] 8001cfc: 681b ldr r3, [r3, #0] 8001cfe: f003 0308 and.w r3, r3, #8 8001d02: 2b08 cmp r3, #8 8001d04: d111 bne.n 8001d2a { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8001d06: 687b ldr r3, [r7, #4] 8001d08: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d0a: f423 7280 bic.w r2, r3, #256 @ 0x100 8001d0e: 687b ldr r3, [r7, #4] 8001d10: 65da str r2, [r3, #92] @ 0x5c if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8001d12: 687b ldr r3, [r7, #4] 8001d14: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d16: f403 5380 and.w r3, r3, #4096 @ 0x1000 8001d1a: 2b00 cmp r3, #0 8001d1c: d105 bne.n 8001d2a { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8001d1e: 687b ldr r3, [r7, #4] 8001d20: 6ddb ldr r3, [r3, #92] @ 0x5c 8001d22: f043 0201 orr.w r2, r3, #1 8001d26: 687b ldr r3, [r7, #4] 8001d28: 65da str r2, [r3, #92] @ 0x5c /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8001d2a: 687b ldr r3, [r7, #4] 8001d2c: 681b ldr r3, [r3, #0] 8001d2e: 4a20 ldr r2, [pc, #128] @ (8001db0 ) 8001d30: 4293 cmp r3, r2 8001d32: d002 beq.n 8001d3a 8001d34: 687b ldr r3, [r7, #4] 8001d36: 681b ldr r3, [r3, #0] 8001d38: e001 b.n 8001d3e 8001d3a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8001d3e: 687a ldr r2, [r7, #4] 8001d40: 6812 ldr r2, [r2, #0] 8001d42: 4293 cmp r3, r2 8001d44: d008 beq.n 8001d58 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8001d46: 697b ldr r3, [r7, #20] 8001d48: 2b00 cmp r3, #0 8001d4a: d005 beq.n 8001d58 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8001d4c: 697b ldr r3, [r7, #20] 8001d4e: 2b05 cmp r3, #5 8001d50: d002 beq.n 8001d58 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8001d52: 697b ldr r3, [r7, #20] 8001d54: 2b09 cmp r3, #9 8001d56: d104 bne.n 8001d62 ) { /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); 8001d58: 687b ldr r3, [r7, #4] 8001d5a: 681b ldr r3, [r3, #0] 8001d5c: 68db ldr r3, [r3, #12] 8001d5e: 61bb str r3, [r7, #24] 8001d60: e00d b.n 8001d7e } else { /* Retrieve Master ADC CFGR register */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); 8001d62: 687b ldr r3, [r7, #4] 8001d64: 681b ldr r3, [r3, #0] 8001d66: 4a12 ldr r2, [pc, #72] @ (8001db0 ) 8001d68: 4293 cmp r3, r2 8001d6a: d002 beq.n 8001d72 8001d6c: 687b ldr r3, [r7, #4] 8001d6e: 681b ldr r3, [r3, #0] 8001d70: e001 b.n 8001d76 8001d72: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 8001d76: 60fb str r3, [r7, #12] tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 8001d78: 68fb ldr r3, [r7, #12] 8001d7a: 68db ldr r3, [r3, #12] 8001d7c: 61bb str r3, [r7, #24] /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* ADC_MULTIMODE_SUPPORT */ /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) 8001d7e: 69fb ldr r3, [r7, #28] 8001d80: 2b08 cmp r3, #8 8001d82: d104 bne.n 8001d8e { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); 8001d84: 687b ldr r3, [r7, #4] 8001d86: 681b ldr r3, [r3, #0] 8001d88: 2208 movs r2, #8 8001d8a: 601a str r2, [r3, #0] 8001d8c: e008 b.n 8001da0 else { /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) 8001d8e: 69bb ldr r3, [r7, #24] 8001d90: f403 4380 and.w r3, r3, #16384 @ 0x4000 8001d94: 2b00 cmp r3, #0 8001d96: d103 bne.n 8001da0 { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); 8001d98: 687b ldr r3, [r7, #4] 8001d9a: 681b ldr r3, [r3, #0] 8001d9c: 220c movs r2, #12 8001d9e: 601a str r2, [r3, #0] } } /* Return function status */ return HAL_OK; 8001da0: 2300 movs r3, #0 } 8001da2: 4618 mov r0, r3 8001da4: 3720 adds r7, #32 8001da6: 46bd mov sp, r7 8001da8: bd80 pop {r7, pc} 8001daa: bf00 nop 8001dac: 50000300 .word 0x50000300 8001db0: 50000100 .word 0x50000100 08001db4 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { 8001db4: b480 push {r7} 8001db6: b083 sub sp, #12 8001db8: af00 add r7, sp, #0 8001dba: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 681b ldr r3, [r3, #0] 8001dc0: 6c1b ldr r3, [r3, #64] @ 0x40 } 8001dc2: 4618 mov r0, r3 8001dc4: 370c adds r7, #12 8001dc6: 46bd mov sp, r7 8001dc8: f85d 7b04 ldr.w r7, [sp], #4 8001dcc: 4770 bx lr ... 08001dd0 : * @param hadc ADC handle * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { 8001dd0: b580 push {r7, lr} 8001dd2: b0b6 sub sp, #216 @ 0xd8 8001dd4: af00 add r7, sp, #0 8001dd6: 6078 str r0, [r7, #4] 8001dd8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8001dda: 2300 movs r3, #0 8001ddc: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; 8001de0: 2300 movs r3, #0 8001de2: 60fb str r3, [r7, #12] { assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); 8001de4: 687b ldr r3, [r7, #4] 8001de6: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8001dea: 2b01 cmp r3, #1 8001dec: d101 bne.n 8001df2 8001dee: 2302 movs r3, #2 8001df0: e3c8 b.n 8002584 8001df2: 687b ldr r3, [r7, #4] 8001df4: 2201 movs r2, #1 8001df6: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8001dfa: 687b ldr r3, [r7, #4] 8001dfc: 681b ldr r3, [r3, #0] 8001dfe: 4618 mov r0, r3 8001e00: f7ff fc52 bl 80016a8 8001e04: 4603 mov r3, r0 8001e06: 2b00 cmp r3, #0 8001e08: f040 83ad bne.w 8002566 { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); 8001e0c: 687b ldr r3, [r7, #4] 8001e0e: 6818 ldr r0, [r3, #0] 8001e10: 683b ldr r3, [r7, #0] 8001e12: 6859 ldr r1, [r3, #4] 8001e14: 683b ldr r3, [r7, #0] 8001e16: 681b ldr r3, [r3, #0] 8001e18: 461a mov r2, r3 8001e1a: f7ff faea bl 80013f2 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8001e1e: 687b ldr r3, [r7, #4] 8001e20: 681b ldr r3, [r3, #0] 8001e22: 4618 mov r0, r3 8001e24: f7ff fc40 bl 80016a8 8001e28: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8001e2c: 687b ldr r3, [r7, #4] 8001e2e: 681b ldr r3, [r3, #0] 8001e30: 4618 mov r0, r3 8001e32: f7ff fc60 bl 80016f6 8001e36: f8c7 00cc str.w r0, [r7, #204] @ 0xcc if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8001e3a: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 8001e3e: 2b00 cmp r3, #0 8001e40: f040 81d9 bne.w 80021f6 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8001e44: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 8001e48: 2b00 cmp r3, #0 8001e4a: f040 81d4 bne.w 80021f6 ) { /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 8001e4e: 683b ldr r3, [r7, #0] 8001e50: 689b ldr r3, [r3, #8] 8001e52: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8001e56: d10f bne.n 8001e78 { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); 8001e58: 687b ldr r3, [r7, #4] 8001e5a: 6818 ldr r0, [r3, #0] 8001e5c: 683b ldr r3, [r7, #0] 8001e5e: 681b ldr r3, [r3, #0] 8001e60: 2200 movs r2, #0 8001e62: 4619 mov r1, r3 8001e64: f7ff faf1 bl 800144a /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: f04f 4100 mov.w r1, #2147483648 @ 0x80000000 8001e70: 4618 mov r0, r3 8001e72: f7ff fa98 bl 80013a6 8001e76: e00e b.n 8001e96 } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); 8001e78: 687b ldr r3, [r7, #4] 8001e7a: 6818 ldr r0, [r3, #0] 8001e7c: 683b ldr r3, [r7, #0] 8001e7e: 6819 ldr r1, [r3, #0] 8001e80: 683b ldr r3, [r7, #0] 8001e82: 689b ldr r3, [r3, #8] 8001e84: 461a mov r2, r3 8001e86: f7ff fae0 bl 800144a /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 681b ldr r3, [r3, #0] 8001e8e: 2100 movs r1, #0 8001e90: 4618 mov r0, r3 8001e92: f7ff fa88 bl 80013a6 /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); 8001e96: 683b ldr r3, [r7, #0] 8001e98: 695a ldr r2, [r3, #20] 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 681b ldr r3, [r3, #0] 8001e9e: 68db ldr r3, [r3, #12] 8001ea0: 08db lsrs r3, r3, #3 8001ea2: f003 0303 and.w r3, r3, #3 8001ea6: 005b lsls r3, r3, #1 8001ea8: fa02 f303 lsl.w r3, r2, r3 8001eac: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 if (pConfig->OffsetNumber != ADC_OFFSET_NONE) 8001eb0: 683b ldr r3, [r7, #0] 8001eb2: 691b ldr r3, [r3, #16] 8001eb4: 2b04 cmp r3, #4 8001eb6: d022 beq.n 8001efe { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); 8001eb8: 687b ldr r3, [r7, #4] 8001eba: 6818 ldr r0, [r3, #0] 8001ebc: 683b ldr r3, [r7, #0] 8001ebe: 6919 ldr r1, [r3, #16] 8001ec0: 683b ldr r3, [r7, #0] 8001ec2: 681a ldr r2, [r3, #0] 8001ec4: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8001ec8: f7ff f9e2 bl 8001290 assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); 8001ecc: 687b ldr r3, [r7, #4] 8001ece: 6818 ldr r0, [r3, #0] 8001ed0: 683b ldr r3, [r7, #0] 8001ed2: 6919 ldr r1, [r3, #16] 8001ed4: 683b ldr r3, [r7, #0] 8001ed6: 699b ldr r3, [r3, #24] 8001ed8: 461a mov r2, r3 8001eda: f7ff fa2e bl 800133a LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 6818 ldr r0, [r3, #0] 8001ee2: 683b ldr r3, [r7, #0] 8001ee4: 6919 ldr r1, [r3, #16] (pConfig->OffsetSaturation == ENABLE) ? 8001ee6: 683b ldr r3, [r7, #0] 8001ee8: 7f1b ldrb r3, [r3, #28] LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, 8001eea: 2b01 cmp r3, #1 8001eec: d102 bne.n 8001ef4 8001eee: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8001ef2: e000 b.n 8001ef6 8001ef4: 2300 movs r3, #0 8001ef6: 461a mov r2, r3 8001ef8: f7ff fa3a bl 8001370 8001efc: e17b b.n 80021f6 } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8001efe: 687b ldr r3, [r7, #4] 8001f00: 681b ldr r3, [r3, #0] 8001f02: 2100 movs r1, #0 8001f04: 4618 mov r0, r3 8001f06: f7ff f9e7 bl 80012d8 8001f0a: 4603 mov r3, r0 8001f0c: f3c3 0312 ubfx r3, r3, #0, #19 8001f10: 2b00 cmp r3, #0 8001f12: d10a bne.n 8001f2a 8001f14: 687b ldr r3, [r7, #4] 8001f16: 681b ldr r3, [r3, #0] 8001f18: 2100 movs r1, #0 8001f1a: 4618 mov r0, r3 8001f1c: f7ff f9dc bl 80012d8 8001f20: 4603 mov r3, r0 8001f22: 0e9b lsrs r3, r3, #26 8001f24: f003 021f and.w r2, r3, #31 8001f28: e01e b.n 8001f68 8001f2a: 687b ldr r3, [r7, #4] 8001f2c: 681b ldr r3, [r3, #0] 8001f2e: 2100 movs r1, #0 8001f30: 4618 mov r0, r3 8001f32: f7ff f9d1 bl 80012d8 8001f36: 4603 mov r3, r0 8001f38: f8c7 30bc str.w r3, [r7, #188] @ 0xbc uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001f3c: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc 8001f40: fa93 f3a3 rbit r3, r3 8001f44: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8001f48: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8001f4c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8001f50: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8001f54: 2b00 cmp r3, #0 8001f56: d101 bne.n 8001f5c { return 32U; 8001f58: 2320 movs r3, #32 8001f5a: e004 b.n 8001f66 } return __builtin_clz(value); 8001f5c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8001f60: fab3 f383 clz r3, r3 8001f64: b2db uxtb r3, r3 8001f66: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 8001f68: 683b ldr r3, [r7, #0] 8001f6a: 681b ldr r3, [r3, #0] 8001f6c: f3c3 0312 ubfx r3, r3, #0, #19 8001f70: 2b00 cmp r3, #0 8001f72: d105 bne.n 8001f80 8001f74: 683b ldr r3, [r7, #0] 8001f76: 681b ldr r3, [r3, #0] 8001f78: 0e9b lsrs r3, r3, #26 8001f7a: f003 031f and.w r3, r3, #31 8001f7e: e018 b.n 8001fb2 8001f80: 683b ldr r3, [r7, #0] 8001f82: 681b ldr r3, [r3, #0] 8001f84: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001f88: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 8001f8c: fa93 f3a3 rbit r3, r3 8001f90: f8c7 30ac str.w r3, [r7, #172] @ 0xac return result; 8001f94: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8001f98: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 if (value == 0U) 8001f9c: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8001fa0: 2b00 cmp r3, #0 8001fa2: d101 bne.n 8001fa8 return 32U; 8001fa4: 2320 movs r3, #32 8001fa6: e004 b.n 8001fb2 return __builtin_clz(value); 8001fa8: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8001fac: fab3 f383 clz r3, r3 8001fb0: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) 8001fb2: 429a cmp r2, r3 8001fb4: d106 bne.n 8001fc4 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); 8001fb6: 687b ldr r3, [r7, #4] 8001fb8: 681b ldr r3, [r3, #0] 8001fba: 2200 movs r2, #0 8001fbc: 2100 movs r1, #0 8001fbe: 4618 mov r0, r3 8001fc0: f7ff f9a0 bl 8001304 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8001fc4: 687b ldr r3, [r7, #4] 8001fc6: 681b ldr r3, [r3, #0] 8001fc8: 2101 movs r1, #1 8001fca: 4618 mov r0, r3 8001fcc: f7ff f984 bl 80012d8 8001fd0: 4603 mov r3, r0 8001fd2: f3c3 0312 ubfx r3, r3, #0, #19 8001fd6: 2b00 cmp r3, #0 8001fd8: d10a bne.n 8001ff0 8001fda: 687b ldr r3, [r7, #4] 8001fdc: 681b ldr r3, [r3, #0] 8001fde: 2101 movs r1, #1 8001fe0: 4618 mov r0, r3 8001fe2: f7ff f979 bl 80012d8 8001fe6: 4603 mov r3, r0 8001fe8: 0e9b lsrs r3, r3, #26 8001fea: f003 021f and.w r2, r3, #31 8001fee: e01e b.n 800202e 8001ff0: 687b ldr r3, [r7, #4] 8001ff2: 681b ldr r3, [r3, #0] 8001ff4: 2101 movs r1, #1 8001ff6: 4618 mov r0, r3 8001ff8: f7ff f96e bl 80012d8 8001ffc: 4603 mov r3, r0 8001ffe: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002002: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8002006: fa93 f3a3 rbit r3, r3 800200a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return result; 800200e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8002012: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 if (value == 0U) 8002016: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800201a: 2b00 cmp r3, #0 800201c: d101 bne.n 8002022 return 32U; 800201e: 2320 movs r3, #32 8002020: e004 b.n 800202c return __builtin_clz(value); 8002022: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8002026: fab3 f383 clz r3, r3 800202a: b2db uxtb r3, r3 800202c: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 800202e: 683b ldr r3, [r7, #0] 8002030: 681b ldr r3, [r3, #0] 8002032: f3c3 0312 ubfx r3, r3, #0, #19 8002036: 2b00 cmp r3, #0 8002038: d105 bne.n 8002046 800203a: 683b ldr r3, [r7, #0] 800203c: 681b ldr r3, [r3, #0] 800203e: 0e9b lsrs r3, r3, #26 8002040: f003 031f and.w r3, r3, #31 8002044: e018 b.n 8002078 8002046: 683b ldr r3, [r7, #0] 8002048: 681b ldr r3, [r3, #0] 800204a: f8c7 3098 str.w r3, [r7, #152] @ 0x98 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800204e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8002052: fa93 f3a3 rbit r3, r3 8002056: f8c7 3094 str.w r3, [r7, #148] @ 0x94 return result; 800205a: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800205e: f8c7 309c str.w r3, [r7, #156] @ 0x9c if (value == 0U) 8002062: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8002066: 2b00 cmp r3, #0 8002068: d101 bne.n 800206e return 32U; 800206a: 2320 movs r3, #32 800206c: e004 b.n 8002078 return __builtin_clz(value); 800206e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8002072: fab3 f383 clz r3, r3 8002076: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) 8002078: 429a cmp r2, r3 800207a: d106 bne.n 800208a { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); 800207c: 687b ldr r3, [r7, #4] 800207e: 681b ldr r3, [r3, #0] 8002080: 2200 movs r2, #0 8002082: 2101 movs r1, #1 8002084: 4618 mov r0, r3 8002086: f7ff f93d bl 8001304 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 800208a: 687b ldr r3, [r7, #4] 800208c: 681b ldr r3, [r3, #0] 800208e: 2102 movs r1, #2 8002090: 4618 mov r0, r3 8002092: f7ff f921 bl 80012d8 8002096: 4603 mov r3, r0 8002098: f3c3 0312 ubfx r3, r3, #0, #19 800209c: 2b00 cmp r3, #0 800209e: d10a bne.n 80020b6 80020a0: 687b ldr r3, [r7, #4] 80020a2: 681b ldr r3, [r3, #0] 80020a4: 2102 movs r1, #2 80020a6: 4618 mov r0, r3 80020a8: f7ff f916 bl 80012d8 80020ac: 4603 mov r3, r0 80020ae: 0e9b lsrs r3, r3, #26 80020b0: f003 021f and.w r2, r3, #31 80020b4: e01e b.n 80020f4 80020b6: 687b ldr r3, [r7, #4] 80020b8: 681b ldr r3, [r3, #0] 80020ba: 2102 movs r1, #2 80020bc: 4618 mov r0, r3 80020be: f7ff f90b bl 80012d8 80020c2: 4603 mov r3, r0 80020c4: f8c7 308c str.w r3, [r7, #140] @ 0x8c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80020c8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80020cc: fa93 f3a3 rbit r3, r3 80020d0: f8c7 3088 str.w r3, [r7, #136] @ 0x88 return result; 80020d4: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80020d8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (value == 0U) 80020dc: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80020e0: 2b00 cmp r3, #0 80020e2: d101 bne.n 80020e8 return 32U; 80020e4: 2320 movs r3, #32 80020e6: e004 b.n 80020f2 return __builtin_clz(value); 80020e8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80020ec: fab3 f383 clz r3, r3 80020f0: b2db uxtb r3, r3 80020f2: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 80020f4: 683b ldr r3, [r7, #0] 80020f6: 681b ldr r3, [r3, #0] 80020f8: f3c3 0312 ubfx r3, r3, #0, #19 80020fc: 2b00 cmp r3, #0 80020fe: d105 bne.n 800210c 8002100: 683b ldr r3, [r7, #0] 8002102: 681b ldr r3, [r3, #0] 8002104: 0e9b lsrs r3, r3, #26 8002106: f003 031f and.w r3, r3, #31 800210a: e016 b.n 800213a 800210c: 683b ldr r3, [r7, #0] 800210e: 681b ldr r3, [r3, #0] 8002110: f8c7 3080 str.w r3, [r7, #128] @ 0x80 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002114: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8002118: fa93 f3a3 rbit r3, r3 800211c: 67fb str r3, [r7, #124] @ 0x7c return result; 800211e: 6ffb ldr r3, [r7, #124] @ 0x7c 8002120: f8c7 3084 str.w r3, [r7, #132] @ 0x84 if (value == 0U) 8002124: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8002128: 2b00 cmp r3, #0 800212a: d101 bne.n 8002130 return 32U; 800212c: 2320 movs r3, #32 800212e: e004 b.n 800213a return __builtin_clz(value); 8002130: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8002134: fab3 f383 clz r3, r3 8002138: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) 800213a: 429a cmp r2, r3 800213c: d106 bne.n 800214c { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); 800213e: 687b ldr r3, [r7, #4] 8002140: 681b ldr r3, [r3, #0] 8002142: 2200 movs r2, #0 8002144: 2102 movs r1, #2 8002146: 4618 mov r0, r3 8002148: f7ff f8dc bl 8001304 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 800214c: 687b ldr r3, [r7, #4] 800214e: 681b ldr r3, [r3, #0] 8002150: 2103 movs r1, #3 8002152: 4618 mov r0, r3 8002154: f7ff f8c0 bl 80012d8 8002158: 4603 mov r3, r0 800215a: f3c3 0312 ubfx r3, r3, #0, #19 800215e: 2b00 cmp r3, #0 8002160: d10a bne.n 8002178 8002162: 687b ldr r3, [r7, #4] 8002164: 681b ldr r3, [r3, #0] 8002166: 2103 movs r1, #3 8002168: 4618 mov r0, r3 800216a: f7ff f8b5 bl 80012d8 800216e: 4603 mov r3, r0 8002170: 0e9b lsrs r3, r3, #26 8002172: f003 021f and.w r2, r3, #31 8002176: e017 b.n 80021a8 8002178: 687b ldr r3, [r7, #4] 800217a: 681b ldr r3, [r3, #0] 800217c: 2103 movs r1, #3 800217e: 4618 mov r0, r3 8002180: f7ff f8aa bl 80012d8 8002184: 4603 mov r3, r0 8002186: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002188: 6f7b ldr r3, [r7, #116] @ 0x74 800218a: fa93 f3a3 rbit r3, r3 800218e: 673b str r3, [r7, #112] @ 0x70 return result; 8002190: 6f3b ldr r3, [r7, #112] @ 0x70 8002192: 67bb str r3, [r7, #120] @ 0x78 if (value == 0U) 8002194: 6fbb ldr r3, [r7, #120] @ 0x78 8002196: 2b00 cmp r3, #0 8002198: d101 bne.n 800219e return 32U; 800219a: 2320 movs r3, #32 800219c: e003 b.n 80021a6 return __builtin_clz(value); 800219e: 6fbb ldr r3, [r7, #120] @ 0x78 80021a0: fab3 f383 clz r3, r3 80021a4: b2db uxtb r3, r3 80021a6: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) 80021a8: 683b ldr r3, [r7, #0] 80021aa: 681b ldr r3, [r3, #0] 80021ac: f3c3 0312 ubfx r3, r3, #0, #19 80021b0: 2b00 cmp r3, #0 80021b2: d105 bne.n 80021c0 80021b4: 683b ldr r3, [r7, #0] 80021b6: 681b ldr r3, [r3, #0] 80021b8: 0e9b lsrs r3, r3, #26 80021ba: f003 031f and.w r3, r3, #31 80021be: e011 b.n 80021e4 80021c0: 683b ldr r3, [r7, #0] 80021c2: 681b ldr r3, [r3, #0] 80021c4: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80021c6: 6ebb ldr r3, [r7, #104] @ 0x68 80021c8: fa93 f3a3 rbit r3, r3 80021cc: 667b str r3, [r7, #100] @ 0x64 return result; 80021ce: 6e7b ldr r3, [r7, #100] @ 0x64 80021d0: 66fb str r3, [r7, #108] @ 0x6c if (value == 0U) 80021d2: 6efb ldr r3, [r7, #108] @ 0x6c 80021d4: 2b00 cmp r3, #0 80021d6: d101 bne.n 80021dc return 32U; 80021d8: 2320 movs r3, #32 80021da: e003 b.n 80021e4 return __builtin_clz(value); 80021dc: 6efb ldr r3, [r7, #108] @ 0x6c 80021de: fab3 f383 clz r3, r3 80021e2: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) 80021e4: 429a cmp r2, r3 80021e6: d106 bne.n 80021f6 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); 80021e8: 687b ldr r3, [r7, #4] 80021ea: 681b ldr r3, [r3, #0] 80021ec: 2200 movs r2, #0 80021ee: 2103 movs r1, #3 80021f0: 4618 mov r0, r3 80021f2: f7ff f887 bl 8001304 } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80021f6: 687b ldr r3, [r7, #4] 80021f8: 681b ldr r3, [r3, #0] 80021fa: 4618 mov r0, r3 80021fc: f7ff fa06 bl 800160c 8002200: 4603 mov r3, r0 8002202: 2b00 cmp r3, #0 8002204: f040 8140 bne.w 8002488 { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); 8002208: 687b ldr r3, [r7, #4] 800220a: 6818 ldr r0, [r3, #0] 800220c: 683b ldr r3, [r7, #0] 800220e: 6819 ldr r1, [r3, #0] 8002210: 683b ldr r3, [r7, #0] 8002212: 68db ldr r3, [r3, #12] 8002214: 461a mov r2, r3 8002216: f7ff f943 bl 80014a0 /* Configuration of differential mode */ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 800221a: 683b ldr r3, [r7, #0] 800221c: 68db ldr r3, [r3, #12] 800221e: 4a8f ldr r2, [pc, #572] @ (800245c ) 8002220: 4293 cmp r3, r2 8002222: f040 8131 bne.w 8002488 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002226: 687b ldr r3, [r7, #4] 8002228: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 800222a: 683b ldr r3, [r7, #0] 800222c: 681b ldr r3, [r3, #0] 800222e: f3c3 0312 ubfx r3, r3, #0, #19 8002232: 2b00 cmp r3, #0 8002234: d10b bne.n 800224e 8002236: 683b ldr r3, [r7, #0] 8002238: 681b ldr r3, [r3, #0] 800223a: 0e9b lsrs r3, r3, #26 800223c: 3301 adds r3, #1 800223e: f003 031f and.w r3, r3, #31 8002242: 2b09 cmp r3, #9 8002244: bf94 ite ls 8002246: 2301 movls r3, #1 8002248: 2300 movhi r3, #0 800224a: b2db uxtb r3, r3 800224c: e019 b.n 8002282 800224e: 683b ldr r3, [r7, #0] 8002250: 681b ldr r3, [r3, #0] 8002252: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002254: 6dfb ldr r3, [r7, #92] @ 0x5c 8002256: fa93 f3a3 rbit r3, r3 800225a: 65bb str r3, [r7, #88] @ 0x58 return result; 800225c: 6dbb ldr r3, [r7, #88] @ 0x58 800225e: 663b str r3, [r7, #96] @ 0x60 if (value == 0U) 8002260: 6e3b ldr r3, [r7, #96] @ 0x60 8002262: 2b00 cmp r3, #0 8002264: d101 bne.n 800226a return 32U; 8002266: 2320 movs r3, #32 8002268: e003 b.n 8002272 return __builtin_clz(value); 800226a: 6e3b ldr r3, [r7, #96] @ 0x60 800226c: fab3 f383 clz r3, r3 8002270: b2db uxtb r3, r3 8002272: 3301 adds r3, #1 8002274: f003 031f and.w r3, r3, #31 8002278: 2b09 cmp r3, #9 800227a: bf94 ite ls 800227c: 2301 movls r3, #1 800227e: 2300 movhi r3, #0 8002280: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002282: 2b00 cmp r3, #0 8002284: d079 beq.n 800237a (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 8002286: 683b ldr r3, [r7, #0] 8002288: 681b ldr r3, [r3, #0] 800228a: f3c3 0312 ubfx r3, r3, #0, #19 800228e: 2b00 cmp r3, #0 8002290: d107 bne.n 80022a2 8002292: 683b ldr r3, [r7, #0] 8002294: 681b ldr r3, [r3, #0] 8002296: 0e9b lsrs r3, r3, #26 8002298: 3301 adds r3, #1 800229a: 069b lsls r3, r3, #26 800229c: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80022a0: e015 b.n 80022ce 80022a2: 683b ldr r3, [r7, #0] 80022a4: 681b ldr r3, [r3, #0] 80022a6: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80022a8: 6d3b ldr r3, [r7, #80] @ 0x50 80022aa: fa93 f3a3 rbit r3, r3 80022ae: 64fb str r3, [r7, #76] @ 0x4c return result; 80022b0: 6cfb ldr r3, [r7, #76] @ 0x4c 80022b2: 657b str r3, [r7, #84] @ 0x54 if (value == 0U) 80022b4: 6d7b ldr r3, [r7, #84] @ 0x54 80022b6: 2b00 cmp r3, #0 80022b8: d101 bne.n 80022be return 32U; 80022ba: 2320 movs r3, #32 80022bc: e003 b.n 80022c6 return __builtin_clz(value); 80022be: 6d7b ldr r3, [r7, #84] @ 0x54 80022c0: fab3 f383 clz r3, r3 80022c4: b2db uxtb r3, r3 80022c6: 3301 adds r3, #1 80022c8: 069b lsls r3, r3, #26 80022ca: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80022ce: 683b ldr r3, [r7, #0] 80022d0: 681b ldr r3, [r3, #0] 80022d2: f3c3 0312 ubfx r3, r3, #0, #19 80022d6: 2b00 cmp r3, #0 80022d8: d109 bne.n 80022ee 80022da: 683b ldr r3, [r7, #0] 80022dc: 681b ldr r3, [r3, #0] 80022de: 0e9b lsrs r3, r3, #26 80022e0: 3301 adds r3, #1 80022e2: f003 031f and.w r3, r3, #31 80022e6: 2101 movs r1, #1 80022e8: fa01 f303 lsl.w r3, r1, r3 80022ec: e017 b.n 800231e 80022ee: 683b ldr r3, [r7, #0] 80022f0: 681b ldr r3, [r3, #0] 80022f2: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80022f4: 6c7b ldr r3, [r7, #68] @ 0x44 80022f6: fa93 f3a3 rbit r3, r3 80022fa: 643b str r3, [r7, #64] @ 0x40 return result; 80022fc: 6c3b ldr r3, [r7, #64] @ 0x40 80022fe: 64bb str r3, [r7, #72] @ 0x48 if (value == 0U) 8002300: 6cbb ldr r3, [r7, #72] @ 0x48 8002302: 2b00 cmp r3, #0 8002304: d101 bne.n 800230a return 32U; 8002306: 2320 movs r3, #32 8002308: e003 b.n 8002312 return __builtin_clz(value); 800230a: 6cbb ldr r3, [r7, #72] @ 0x48 800230c: fab3 f383 clz r3, r3 8002310: b2db uxtb r3, r3 8002312: 3301 adds r3, #1 8002314: f003 031f and.w r3, r3, #31 8002318: 2101 movs r1, #1 800231a: fa01 f303 lsl.w r3, r1, r3 800231e: ea42 0103 orr.w r1, r2, r3 8002322: 683b ldr r3, [r7, #0] 8002324: 681b ldr r3, [r3, #0] 8002326: f3c3 0312 ubfx r3, r3, #0, #19 800232a: 2b00 cmp r3, #0 800232c: d10a bne.n 8002344 800232e: 683b ldr r3, [r7, #0] 8002330: 681b ldr r3, [r3, #0] 8002332: 0e9b lsrs r3, r3, #26 8002334: 3301 adds r3, #1 8002336: f003 021f and.w r2, r3, #31 800233a: 4613 mov r3, r2 800233c: 005b lsls r3, r3, #1 800233e: 4413 add r3, r2 8002340: 051b lsls r3, r3, #20 8002342: e018 b.n 8002376 8002344: 683b ldr r3, [r7, #0] 8002346: 681b ldr r3, [r3, #0] 8002348: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800234a: 6bbb ldr r3, [r7, #56] @ 0x38 800234c: fa93 f3a3 rbit r3, r3 8002350: 637b str r3, [r7, #52] @ 0x34 return result; 8002352: 6b7b ldr r3, [r7, #52] @ 0x34 8002354: 63fb str r3, [r7, #60] @ 0x3c if (value == 0U) 8002356: 6bfb ldr r3, [r7, #60] @ 0x3c 8002358: 2b00 cmp r3, #0 800235a: d101 bne.n 8002360 return 32U; 800235c: 2320 movs r3, #32 800235e: e003 b.n 8002368 return __builtin_clz(value); 8002360: 6bfb ldr r3, [r7, #60] @ 0x3c 8002362: fab3 f383 clz r3, r3 8002366: b2db uxtb r3, r3 8002368: 3301 adds r3, #1 800236a: f003 021f and.w r2, r3, #31 800236e: 4613 mov r3, r2 8002370: 005b lsls r3, r3, #1 8002372: 4413 add r3, r2 8002374: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002376: 430b orrs r3, r1 8002378: e081 b.n 800247e (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( 800237a: 683b ldr r3, [r7, #0] 800237c: 681b ldr r3, [r3, #0] 800237e: f3c3 0312 ubfx r3, r3, #0, #19 8002382: 2b00 cmp r3, #0 8002384: d107 bne.n 8002396 8002386: 683b ldr r3, [r7, #0] 8002388: 681b ldr r3, [r3, #0] 800238a: 0e9b lsrs r3, r3, #26 800238c: 3301 adds r3, #1 800238e: 069b lsls r3, r3, #26 8002390: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002394: e015 b.n 80023c2 8002396: 683b ldr r3, [r7, #0] 8002398: 681b ldr r3, [r3, #0] 800239a: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800239c: 6afb ldr r3, [r7, #44] @ 0x2c 800239e: fa93 f3a3 rbit r3, r3 80023a2: 62bb str r3, [r7, #40] @ 0x28 return result; 80023a4: 6abb ldr r3, [r7, #40] @ 0x28 80023a6: 633b str r3, [r7, #48] @ 0x30 if (value == 0U) 80023a8: 6b3b ldr r3, [r7, #48] @ 0x30 80023aa: 2b00 cmp r3, #0 80023ac: d101 bne.n 80023b2 return 32U; 80023ae: 2320 movs r3, #32 80023b0: e003 b.n 80023ba return __builtin_clz(value); 80023b2: 6b3b ldr r3, [r7, #48] @ 0x30 80023b4: fab3 f383 clz r3, r3 80023b8: b2db uxtb r3, r3 80023ba: 3301 adds r3, #1 80023bc: 069b lsls r3, r3, #26 80023be: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80023c2: 683b ldr r3, [r7, #0] 80023c4: 681b ldr r3, [r3, #0] 80023c6: f3c3 0312 ubfx r3, r3, #0, #19 80023ca: 2b00 cmp r3, #0 80023cc: d109 bne.n 80023e2 80023ce: 683b ldr r3, [r7, #0] 80023d0: 681b ldr r3, [r3, #0] 80023d2: 0e9b lsrs r3, r3, #26 80023d4: 3301 adds r3, #1 80023d6: f003 031f and.w r3, r3, #31 80023da: 2101 movs r1, #1 80023dc: fa01 f303 lsl.w r3, r1, r3 80023e0: e017 b.n 8002412 80023e2: 683b ldr r3, [r7, #0] 80023e4: 681b ldr r3, [r3, #0] 80023e6: 623b str r3, [r7, #32] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80023e8: 6a3b ldr r3, [r7, #32] 80023ea: fa93 f3a3 rbit r3, r3 80023ee: 61fb str r3, [r7, #28] return result; 80023f0: 69fb ldr r3, [r7, #28] 80023f2: 627b str r3, [r7, #36] @ 0x24 if (value == 0U) 80023f4: 6a7b ldr r3, [r7, #36] @ 0x24 80023f6: 2b00 cmp r3, #0 80023f8: d101 bne.n 80023fe return 32U; 80023fa: 2320 movs r3, #32 80023fc: e003 b.n 8002406 return __builtin_clz(value); 80023fe: 6a7b ldr r3, [r7, #36] @ 0x24 8002400: fab3 f383 clz r3, r3 8002404: b2db uxtb r3, r3 8002406: 3301 adds r3, #1 8002408: f003 031f and.w r3, r3, #31 800240c: 2101 movs r1, #1 800240e: fa01 f303 lsl.w r3, r1, r3 8002412: ea42 0103 orr.w r1, r2, r3 8002416: 683b ldr r3, [r7, #0] 8002418: 681b ldr r3, [r3, #0] 800241a: f3c3 0312 ubfx r3, r3, #0, #19 800241e: 2b00 cmp r3, #0 8002420: d10d bne.n 800243e 8002422: 683b ldr r3, [r7, #0] 8002424: 681b ldr r3, [r3, #0] 8002426: 0e9b lsrs r3, r3, #26 8002428: 3301 adds r3, #1 800242a: f003 021f and.w r2, r3, #31 800242e: 4613 mov r3, r2 8002430: 005b lsls r3, r3, #1 8002432: 4413 add r3, r2 8002434: 3b1e subs r3, #30 8002436: 051b lsls r3, r3, #20 8002438: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800243c: e01e b.n 800247c 800243e: 683b ldr r3, [r7, #0] 8002440: 681b ldr r3, [r3, #0] 8002442: 617b str r3, [r7, #20] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8002444: 697b ldr r3, [r7, #20] 8002446: fa93 f3a3 rbit r3, r3 800244a: 613b str r3, [r7, #16] return result; 800244c: 693b ldr r3, [r7, #16] 800244e: 61bb str r3, [r7, #24] if (value == 0U) 8002450: 69bb ldr r3, [r7, #24] 8002452: 2b00 cmp r3, #0 8002454: d104 bne.n 8002460 return 32U; 8002456: 2320 movs r3, #32 8002458: e006 b.n 8002468 800245a: bf00 nop 800245c: 407f0000 .word 0x407f0000 return __builtin_clz(value); 8002460: 69bb ldr r3, [r7, #24] 8002462: fab3 f383 clz r3, r3 8002466: b2db uxtb r3, r3 8002468: 3301 adds r3, #1 800246a: f003 021f and.w r2, r3, #31 800246e: 4613 mov r3, r2 8002470: 005b lsls r3, r3, #1 8002472: 4413 add r3, r2 8002474: 3b1e subs r3, #30 8002476: 051b lsls r3, r3, #20 8002478: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 800247c: 430b orrs r3, r1 (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)), pConfig->SamplingTime); 800247e: 683a ldr r2, [r7, #0] 8002480: 6892 ldr r2, [r2, #8] LL_ADC_SetChannelSamplingTime(hadc->Instance, 8002482: 4619 mov r1, r3 8002484: f7fe ffe1 bl 800144a /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) 8002488: 683b ldr r3, [r7, #0] 800248a: 681a ldr r2, [r3, #0] 800248c: 4b3f ldr r3, [pc, #252] @ (800258c ) 800248e: 4013 ands r3, r2 8002490: 2b00 cmp r3, #0 8002492: d071 beq.n 8002578 { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8002494: 483e ldr r0, [pc, #248] @ (8002590 ) 8002496: f7fe feed bl 8001274 800249a: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4 /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) 800249e: 683b ldr r3, [r7, #0] 80024a0: 681b ldr r3, [r3, #0] 80024a2: 4a3c ldr r2, [pc, #240] @ (8002594 ) 80024a4: 4293 cmp r3, r2 80024a6: d004 beq.n 80024b2 80024a8: 683b ldr r3, [r7, #0] 80024aa: 681b ldr r3, [r3, #0] 80024ac: 4a3a ldr r2, [pc, #232] @ (8002598 ) 80024ae: 4293 cmp r3, r2 80024b0: d127 bne.n 8002502 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 80024b2: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 80024b6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80024ba: 2b00 cmp r3, #0 80024bc: d121 bne.n 8002502 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80024be: 687b ldr r3, [r7, #4] 80024c0: 681b ldr r3, [r3, #0] 80024c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 80024c6: d157 bne.n 8002578 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 80024c8: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 80024cc: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80024d0: 4619 mov r1, r3 80024d2: 482f ldr r0, [pc, #188] @ (8002590 ) 80024d4: f7fe febb bl 800124e /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80024d8: 4b30 ldr r3, [pc, #192] @ (800259c ) 80024da: 681b ldr r3, [r3, #0] 80024dc: 099b lsrs r3, r3, #6 80024de: 4a30 ldr r2, [pc, #192] @ (80025a0 ) 80024e0: fba2 2303 umull r2, r3, r2, r3 80024e4: 099b lsrs r3, r3, #6 80024e6: 1c5a adds r2, r3, #1 80024e8: 4613 mov r3, r2 80024ea: 005b lsls r3, r3, #1 80024ec: 4413 add r3, r2 80024ee: 009b lsls r3, r3, #2 80024f0: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 80024f2: e002 b.n 80024fa { wait_loop_index--; 80024f4: 68fb ldr r3, [r7, #12] 80024f6: 3b01 subs r3, #1 80024f8: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) 80024fa: 68fb ldr r3, [r7, #12] 80024fc: 2b00 cmp r3, #0 80024fe: d1f9 bne.n 80024f4 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8002500: e03a b.n 8002578 } } } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) 8002502: 683b ldr r3, [r7, #0] 8002504: 681b ldr r3, [r3, #0] 8002506: 4a27 ldr r2, [pc, #156] @ (80025a4 ) 8002508: 4293 cmp r3, r2 800250a: d113 bne.n 8002534 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 800250c: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002510: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002514: 2b00 cmp r3, #0 8002516: d10d bne.n 8002534 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8002518: 687b ldr r3, [r7, #4] 800251a: 681b ldr r3, [r3, #0] 800251c: 4a22 ldr r2, [pc, #136] @ (80025a8 ) 800251e: 4293 cmp r3, r2 8002520: d02a beq.n 8002578 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002522: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002526: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800252a: 4619 mov r1, r3 800252c: 4818 ldr r0, [pc, #96] @ (8002590 ) 800252e: f7fe fe8e bl 800124e if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8002532: e021 b.n 8002578 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) 8002534: 683b ldr r3, [r7, #0] 8002536: 681b ldr r3, [r3, #0] 8002538: 4a1c ldr r2, [pc, #112] @ (80025ac ) 800253a: 4293 cmp r3, r2 800253c: d11c bne.n 8002578 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 800253e: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002542: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8002546: 2b00 cmp r3, #0 8002548: d116 bne.n 8002578 { if (ADC_VREFINT_INSTANCE(hadc)) 800254a: 687b ldr r3, [r7, #4] 800254c: 681b ldr r3, [r3, #0] 800254e: 4a16 ldr r2, [pc, #88] @ (80025a8 ) 8002550: 4293 cmp r3, r2 8002552: d011 beq.n 8002578 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), 8002554: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 8002558: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800255c: 4619 mov r1, r3 800255e: 480c ldr r0, [pc, #48] @ (8002590 ) 8002560: f7fe fe75 bl 800124e 8002564: e008 b.n 8002578 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002566: 687b ldr r3, [r7, #4] 8002568: 6ddb ldr r3, [r3, #92] @ 0x5c 800256a: f043 0220 orr.w r2, r3, #32 800256e: 687b ldr r3, [r7, #4] 8002570: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 8002572: 2301 movs r3, #1 8002574: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002578: 687b ldr r3, [r7, #4] 800257a: 2200 movs r2, #0 800257c: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; 8002580: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7 } 8002584: 4618 mov r0, r3 8002586: 37d8 adds r7, #216 @ 0xd8 8002588: 46bd mov sp, r7 800258a: bd80 pop {r7, pc} 800258c: 80080000 .word 0x80080000 8002590: 50000300 .word 0x50000300 8002594: c3210000 .word 0xc3210000 8002598: 90c00010 .word 0x90c00010 800259c: 20000000 .word 0x20000000 80025a0: 053e2d63 .word 0x053e2d63 80025a4: c7520000 .word 0xc7520000 80025a8: 50000100 .word 0x50000100 80025ac: cb840000 .word 0xcb840000 080025b0 : * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { 80025b0: b580 push {r7, lr} 80025b2: b088 sub sp, #32 80025b4: af00 add r7, sp, #0 80025b6: 6078 str r0, [r7, #4] 80025b8: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; 80025ba: 2300 movs r3, #0 80025bc: 61fb str r3, [r7, #28] uint32_t conversion_group_reassigned = ConversionGroup; 80025be: 683b ldr r3, [r7, #0] 80025c0: 61bb str r3, [r7, #24] assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80025c2: 687b ldr r3, [r7, #4] 80025c4: 681b ldr r3, [r3, #0] 80025c6: 4618 mov r0, r3 80025c8: f7ff f86e bl 80016a8 80025cc: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80025ce: 687b ldr r3, [r7, #4] 80025d0: 681b ldr r3, [r3, #0] 80025d2: 4618 mov r0, r3 80025d4: f7ff f88f bl 80016f6 80025d8: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular != 0UL) 80025da: 693b ldr r3, [r7, #16] 80025dc: 2b00 cmp r3, #0 80025de: d103 bne.n 80025e8 || (tmp_adc_is_conversion_on_going_injected != 0UL) 80025e0: 68fb ldr r3, [r7, #12] 80025e2: 2b00 cmp r3, #0 80025e4: f000 8098 beq.w 8002718 /* auto-delay mode. */ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) 80025e8: 687b ldr r3, [r7, #4] 80025ea: 681b ldr r3, [r3, #0] 80025ec: 68db ldr r3, [r3, #12] 80025ee: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80025f2: 2b00 cmp r3, #0 80025f4: d02a beq.n 800264c && (hadc->Init.ContinuousConvMode == ENABLE) 80025f6: 687b ldr r3, [r7, #4] 80025f8: 7f5b ldrb r3, [r3, #29] 80025fa: 2b01 cmp r3, #1 80025fc: d126 bne.n 800264c && (hadc->Init.LowPowerAutoWait == ENABLE) 80025fe: 687b ldr r3, [r7, #4] 8002600: 7f1b ldrb r3, [r3, #28] 8002602: 2b01 cmp r3, #1 8002604: d122 bne.n 800264c ) { /* Use stop of regular group */ conversion_group_reassigned = ADC_REGULAR_GROUP; 8002606: 2301 movs r3, #1 8002608: 61bb str r3, [r7, #24] /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) 800260a: e014 b.n 8002636 { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) 800260c: 69fb ldr r3, [r7, #28] 800260e: 4a45 ldr r2, [pc, #276] @ (8002724 ) 8002610: 4293 cmp r3, r2 8002612: d90d bls.n 8002630 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002614: 687b ldr r3, [r7, #4] 8002616: 6ddb ldr r3, [r3, #92] @ 0x5c 8002618: f043 0210 orr.w r2, r3, #16 800261c: 687b ldr r3, [r7, #4] 800261e: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002620: 687b ldr r3, [r7, #4] 8002622: 6e1b ldr r3, [r3, #96] @ 0x60 8002624: f043 0201 orr.w r2, r3, #1 8002628: 687b ldr r3, [r7, #4] 800262a: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 800262c: 2301 movs r3, #1 800262e: e074 b.n 800271a } Conversion_Timeout_CPU_cycles ++; 8002630: 69fb ldr r3, [r7, #28] 8002632: 3301 adds r3, #1 8002634: 61fb str r3, [r7, #28] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) 8002636: 687b ldr r3, [r7, #4] 8002638: 681b ldr r3, [r3, #0] 800263a: 681b ldr r3, [r3, #0] 800263c: f003 0340 and.w r3, r3, #64 @ 0x40 8002640: 2b40 cmp r3, #64 @ 0x40 8002642: d1e3 bne.n 800260c } /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); 8002644: 687b ldr r3, [r7, #4] 8002646: 681b ldr r3, [r3, #0] 8002648: 2240 movs r2, #64 @ 0x40 800264a: 601a str r2, [r3, #0] } /* Stop potential conversion on going on ADC group regular */ if (conversion_group_reassigned != ADC_INJECTED_GROUP) 800264c: 69bb ldr r3, [r7, #24] 800264e: 2b02 cmp r3, #2 8002650: d014 beq.n 800267c { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) 8002652: 687b ldr r3, [r7, #4] 8002654: 681b ldr r3, [r3, #0] 8002656: 4618 mov r0, r3 8002658: f7ff f826 bl 80016a8 800265c: 4603 mov r3, r0 800265e: 2b00 cmp r3, #0 8002660: d00c beq.n 800267c { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) 8002662: 687b ldr r3, [r7, #4] 8002664: 681b ldr r3, [r3, #0] 8002666: 4618 mov r0, r3 8002668: f7fe ffe3 bl 8001632 800266c: 4603 mov r3, r0 800266e: 2b00 cmp r3, #0 8002670: d104 bne.n 800267c { /* Stop ADC group regular conversion */ LL_ADC_REG_StopConversion(hadc->Instance); 8002672: 687b ldr r3, [r7, #4] 8002674: 681b ldr r3, [r3, #0] 8002676: 4618 mov r0, r3 8002678: f7ff f802 bl 8001680 } } } /* Stop potential conversion on going on ADC group injected */ if (conversion_group_reassigned != ADC_REGULAR_GROUP) 800267c: 69bb ldr r3, [r7, #24] 800267e: 2b01 cmp r3, #1 8002680: d014 beq.n 80026ac { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) 8002682: 687b ldr r3, [r7, #4] 8002684: 681b ldr r3, [r3, #0] 8002686: 4618 mov r0, r3 8002688: f7ff f835 bl 80016f6 800268c: 4603 mov r3, r0 800268e: 2b00 cmp r3, #0 8002690: d00c beq.n 80026ac { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) 8002692: 687b ldr r3, [r7, #4] 8002694: 681b ldr r3, [r3, #0] 8002696: 4618 mov r0, r3 8002698: f7fe ffcb bl 8001632 800269c: 4603 mov r3, r0 800269e: 2b00 cmp r3, #0 80026a0: d104 bne.n 80026ac { /* Stop ADC group injected conversion */ LL_ADC_INJ_StopConversion(hadc->Instance); 80026a2: 687b ldr r3, [r7, #4] 80026a4: 681b ldr r3, [r3, #0] 80026a6: 4618 mov r0, r3 80026a8: f7ff f811 bl 80016ce } } } /* Selection of start and stop bits with respect to the regular or injected group */ switch (conversion_group_reassigned) 80026ac: 69bb ldr r3, [r7, #24] 80026ae: 2b02 cmp r3, #2 80026b0: d005 beq.n 80026be 80026b2: 69bb ldr r3, [r7, #24] 80026b4: 2b03 cmp r3, #3 80026b6: d105 bne.n 80026c4 { case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); 80026b8: 230c movs r3, #12 80026ba: 617b str r3, [r7, #20] break; 80026bc: e005 b.n 80026ca case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; 80026be: 2308 movs r3, #8 80026c0: 617b str r3, [r7, #20] break; 80026c2: e002 b.n 80026ca /* Case ADC_REGULAR_GROUP only*/ default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; 80026c4: 2304 movs r3, #4 80026c6: 617b str r3, [r7, #20] break; 80026c8: bf00 nop } /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); 80026ca: f7fe fda1 bl 8001210 80026ce: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) 80026d0: e01b b.n 800270a { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 80026d2: f7fe fd9d bl 8001210 80026d6: 4602 mov r2, r0 80026d8: 68bb ldr r3, [r7, #8] 80026da: 1ad3 subs r3, r2, r3 80026dc: 2b05 cmp r3, #5 80026de: d914 bls.n 800270a { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) 80026e0: 687b ldr r3, [r7, #4] 80026e2: 681b ldr r3, [r3, #0] 80026e4: 689a ldr r2, [r3, #8] 80026e6: 697b ldr r3, [r7, #20] 80026e8: 4013 ands r3, r2 80026ea: 2b00 cmp r3, #0 80026ec: d00d beq.n 800270a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80026ee: 687b ldr r3, [r7, #4] 80026f0: 6ddb ldr r3, [r3, #92] @ 0x5c 80026f2: f043 0210 orr.w r2, r3, #16 80026f6: 687b ldr r3, [r7, #4] 80026f8: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80026fa: 687b ldr r3, [r7, #4] 80026fc: 6e1b ldr r3, [r3, #96] @ 0x60 80026fe: f043 0201 orr.w r2, r3, #1 8002702: 687b ldr r3, [r7, #4] 8002704: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 8002706: 2301 movs r3, #1 8002708: e007 b.n 800271a while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) 800270a: 687b ldr r3, [r7, #4] 800270c: 681b ldr r3, [r3, #0] 800270e: 689a ldr r2, [r3, #8] 8002710: 697b ldr r3, [r7, #20] 8002712: 4013 ands r3, r2 8002714: 2b00 cmp r3, #0 8002716: d1dc bne.n 80026d2 } } /* Return HAL status */ return HAL_OK; 8002718: 2300 movs r3, #0 } 800271a: 4618 mov r0, r3 800271c: 3720 adds r7, #32 800271e: 46bd mov sp, r7 8002720: bd80 pop {r7, pc} 8002722: bf00 nop 8002724: a33fffff .word 0xa33fffff 08002728 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8002728: b580 push {r7, lr} 800272a: b084 sub sp, #16 800272c: af00 add r7, sp, #0 800272e: 6078 str r0, [r7, #4] uint32_t tickstart; __IO uint32_t wait_loop_index = 0UL; 8002730: 2300 movs r3, #0 8002732: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8002734: 687b ldr r3, [r7, #4] 8002736: 681b ldr r3, [r3, #0] 8002738: 4618 mov r0, r3 800273a: f7fe ff67 bl 800160c 800273e: 4603 mov r3, r0 8002740: 2b00 cmp r3, #0 8002742: d169 bne.n 8002818 { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART 8002744: 687b ldr r3, [r7, #4] 8002746: 681b ldr r3, [r3, #0] 8002748: 689a ldr r2, [r3, #8] 800274a: 4b36 ldr r3, [pc, #216] @ (8002824 ) 800274c: 4013 ands r3, r2 800274e: 2b00 cmp r3, #0 8002750: d00d beq.n 800276e | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002752: 687b ldr r3, [r7, #4] 8002754: 6ddb ldr r3, [r3, #92] @ 0x5c 8002756: f043 0210 orr.w r2, r3, #16 800275a: 687b ldr r3, [r7, #4] 800275c: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800275e: 687b ldr r3, [r7, #4] 8002760: 6e1b ldr r3, [r3, #96] @ 0x60 8002762: f043 0201 orr.w r2, r3, #1 8002766: 687b ldr r3, [r7, #4] 8002768: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 800276a: 2301 movs r3, #1 800276c: e055 b.n 800281a } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 800276e: 687b ldr r3, [r7, #4] 8002770: 681b ldr r3, [r3, #0] 8002772: 4618 mov r0, r3 8002774: f7fe ff22 bl 80015bc if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) 8002778: 482b ldr r0, [pc, #172] @ (8002828 ) 800277a: f7fe fd7b bl 8001274 800277e: 4603 mov r3, r0 & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) 8002780: f403 0300 and.w r3, r3, #8388608 @ 0x800000 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) 8002784: 2b00 cmp r3, #0 8002786: d013 beq.n 80027b0 /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8002788: 4b28 ldr r3, [pc, #160] @ (800282c ) 800278a: 681b ldr r3, [r3, #0] 800278c: 099b lsrs r3, r3, #6 800278e: 4a28 ldr r2, [pc, #160] @ (8002830 ) 8002790: fba2 2303 umull r2, r3, r2, r3 8002794: 099b lsrs r3, r3, #6 8002796: 1c5a adds r2, r3, #1 8002798: 4613 mov r3, r2 800279a: 005b lsls r3, r3, #1 800279c: 4413 add r3, r2 800279e: 009b lsls r3, r3, #2 80027a0: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80027a2: e002 b.n 80027aa { wait_loop_index--; 80027a4: 68bb ldr r3, [r7, #8] 80027a6: 3b01 subs r3, #1 80027a8: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 80027aa: 68bb ldr r3, [r7, #8] 80027ac: 2b00 cmp r3, #0 80027ae: d1f9 bne.n 80027a4 } } /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 80027b0: f7fe fd2e bl 8001210 80027b4: 60f8 str r0, [r7, #12] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 80027b6: e028 b.n 800280a The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80027b8: 687b ldr r3, [r7, #4] 80027ba: 681b ldr r3, [r3, #0] 80027bc: 4618 mov r0, r3 80027be: f7fe ff25 bl 800160c 80027c2: 4603 mov r3, r0 80027c4: 2b00 cmp r3, #0 80027c6: d104 bne.n 80027d2 { LL_ADC_Enable(hadc->Instance); 80027c8: 687b ldr r3, [r7, #4] 80027ca: 681b ldr r3, [r3, #0] 80027cc: 4618 mov r0, r3 80027ce: f7fe fef5 bl 80015bc } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80027d2: f7fe fd1d bl 8001210 80027d6: 4602 mov r2, r0 80027d8: 68fb ldr r3, [r7, #12] 80027da: 1ad3 subs r3, r2, r3 80027dc: 2b02 cmp r3, #2 80027de: d914 bls.n 800280a { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 80027e0: 687b ldr r3, [r7, #4] 80027e2: 681b ldr r3, [r3, #0] 80027e4: 681b ldr r3, [r3, #0] 80027e6: f003 0301 and.w r3, r3, #1 80027ea: 2b01 cmp r3, #1 80027ec: d00d beq.n 800280a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80027ee: 687b ldr r3, [r7, #4] 80027f0: 6ddb ldr r3, [r3, #92] @ 0x5c 80027f2: f043 0210 orr.w r2, r3, #16 80027f6: 687b ldr r3, [r7, #4] 80027f8: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80027fa: 687b ldr r3, [r7, #4] 80027fc: 6e1b ldr r3, [r3, #96] @ 0x60 80027fe: f043 0201 orr.w r2, r3, #1 8002802: 687b ldr r3, [r7, #4] 8002804: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 8002806: 2301 movs r3, #1 8002808: e007 b.n 800281a while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 800280a: 687b ldr r3, [r7, #4] 800280c: 681b ldr r3, [r3, #0] 800280e: 681b ldr r3, [r3, #0] 8002810: f003 0301 and.w r3, r3, #1 8002814: 2b01 cmp r3, #1 8002816: d1cf bne.n 80027b8 } } } /* Return HAL status */ return HAL_OK; 8002818: 2300 movs r3, #0 } 800281a: 4618 mov r0, r3 800281c: 3710 adds r7, #16 800281e: 46bd mov sp, r7 8002820: bd80 pop {r7, pc} 8002822: bf00 nop 8002824: 8000003f .word 0x8000003f 8002828: 50000300 .word 0x50000300 800282c: 20000000 .word 0x20000000 8002830: 053e2d63 .word 0x053e2d63 08002834 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8002834: b580 push {r7, lr} 8002836: b084 sub sp, #16 8002838: af00 add r7, sp, #0 800283a: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 800283c: 687b ldr r3, [r7, #4] 800283e: 681b ldr r3, [r3, #0] 8002840: 4618 mov r0, r3 8002842: f7fe fef6 bl 8001632 8002846: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8002848: 687b ldr r3, [r7, #4] 800284a: 681b ldr r3, [r3, #0] 800284c: 4618 mov r0, r3 800284e: f7fe fedd bl 800160c 8002852: 4603 mov r3, r0 8002854: 2b00 cmp r3, #0 8002856: d047 beq.n 80028e8 && (tmp_adc_is_disable_on_going == 0UL) 8002858: 68fb ldr r3, [r7, #12] 800285a: 2b00 cmp r3, #0 800285c: d144 bne.n 80028e8 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 800285e: 687b ldr r3, [r7, #4] 8002860: 681b ldr r3, [r3, #0] 8002862: 689b ldr r3, [r3, #8] 8002864: f003 030d and.w r3, r3, #13 8002868: 2b01 cmp r3, #1 800286a: d10c bne.n 8002886 { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 800286c: 687b ldr r3, [r7, #4] 800286e: 681b ldr r3, [r3, #0] 8002870: 4618 mov r0, r3 8002872: f7fe feb7 bl 80015e4 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8002876: 687b ldr r3, [r7, #4] 8002878: 681b ldr r3, [r3, #0] 800287a: 2203 movs r2, #3 800287c: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 800287e: f7fe fcc7 bl 8001210 8002882: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8002884: e029 b.n 80028da SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8002886: 687b ldr r3, [r7, #4] 8002888: 6ddb ldr r3, [r3, #92] @ 0x5c 800288a: f043 0210 orr.w r2, r3, #16 800288e: 687b ldr r3, [r7, #4] 8002890: 65da str r2, [r3, #92] @ 0x5c SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8002892: 687b ldr r3, [r7, #4] 8002894: 6e1b ldr r3, [r3, #96] @ 0x60 8002896: f043 0201 orr.w r2, r3, #1 800289a: 687b ldr r3, [r7, #4] 800289c: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 800289e: 2301 movs r3, #1 80028a0: e023 b.n 80028ea { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 80028a2: f7fe fcb5 bl 8001210 80028a6: 4602 mov r2, r0 80028a8: 68bb ldr r3, [r7, #8] 80028aa: 1ad3 subs r3, r2, r3 80028ac: 2b02 cmp r3, #2 80028ae: d914 bls.n 80028da { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80028b0: 687b ldr r3, [r7, #4] 80028b2: 681b ldr r3, [r3, #0] 80028b4: 689b ldr r3, [r3, #8] 80028b6: f003 0301 and.w r3, r3, #1 80028ba: 2b00 cmp r3, #0 80028bc: d00d beq.n 80028da { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80028be: 687b ldr r3, [r7, #4] 80028c0: 6ddb ldr r3, [r3, #92] @ 0x5c 80028c2: f043 0210 orr.w r2, r3, #16 80028c6: 687b ldr r3, [r7, #4] 80028c8: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80028ca: 687b ldr r3, [r7, #4] 80028cc: 6e1b ldr r3, [r3, #96] @ 0x60 80028ce: f043 0201 orr.w r2, r3, #1 80028d2: 687b ldr r3, [r7, #4] 80028d4: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; 80028d6: 2301 movs r3, #1 80028d8: e007 b.n 80028ea while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80028da: 687b ldr r3, [r7, #4] 80028dc: 681b ldr r3, [r3, #0] 80028de: 689b ldr r3, [r3, #8] 80028e0: f003 0301 and.w r3, r3, #1 80028e4: 2b00 cmp r3, #0 80028e6: d1dc bne.n 80028a2 } } } /* Return HAL status */ return HAL_OK; 80028e8: 2300 movs r3, #0 } 80028ea: 4618 mov r0, r3 80028ec: 3710 adds r7, #16 80028ee: 46bd mov sp, r7 80028f0: bd80 pop {r7, pc} 080028f2 : { 80028f2: b480 push {r7} 80028f4: b083 sub sp, #12 80028f6: af00 add r7, sp, #0 80028f8: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80028fa: 687b ldr r3, [r7, #4] 80028fc: 689b ldr r3, [r3, #8] 80028fe: f003 0301 and.w r3, r3, #1 8002902: 2b01 cmp r3, #1 8002904: d101 bne.n 800290a 8002906: 2301 movs r3, #1 8002908: e000 b.n 800290c 800290a: 2300 movs r3, #0 } 800290c: 4618 mov r0, r3 800290e: 370c adds r7, #12 8002910: 46bd mov sp, r7 8002912: f85d 7b04 ldr.w r7, [sp], #4 8002916: 4770 bx lr 08002918 : { 8002918: b480 push {r7} 800291a: b083 sub sp, #12 800291c: af00 add r7, sp, #0 800291e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8002920: 687b ldr r3, [r7, #4] 8002922: 689b ldr r3, [r3, #8] 8002924: f003 0304 and.w r3, r3, #4 8002928: 2b04 cmp r3, #4 800292a: d101 bne.n 8002930 800292c: 2301 movs r3, #1 800292e: e000 b.n 8002932 8002930: 2300 movs r3, #0 } 8002932: 4618 mov r0, r3 8002934: 370c adds r7, #12 8002936: 46bd mov sp, r7 8002938: f85d 7b04 ldr.w r7, [sp], #4 800293c: 4770 bx lr ... 08002940 : * @param hadc Master ADC handle * @param pMultimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) { 8002940: b590 push {r4, r7, lr} 8002942: b0a1 sub sp, #132 @ 0x84 8002944: af00 add r7, sp, #0 8002946: 6078 str r0, [r7, #4] 8002948: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800294a: 2300 movs r3, #0 800294c: f887 307f strb.w r3, [r7, #127] @ 0x7f assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8002950: 687b ldr r3, [r7, #4] 8002952: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 8002956: 2b01 cmp r3, #1 8002958: d101 bne.n 800295e 800295a: 2302 movs r3, #2 800295c: e08b b.n 8002a76 800295e: 687b ldr r3, [r7, #4] 8002960: 2201 movs r2, #1 8002962: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); 8002966: 2300 movs r3, #0 8002968: 667b str r3, [r7, #100] @ 0x64 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); 800296a: 2300 movs r3, #0 800296c: 66bb str r3, [r7, #104] @ 0x68 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); 800296e: 687b ldr r3, [r7, #4] 8002970: 681b ldr r3, [r3, #0] 8002972: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8002976: d102 bne.n 800297e 8002978: 4b41 ldr r3, [pc, #260] @ (8002a80 ) 800297a: 60bb str r3, [r7, #8] 800297c: e001 b.n 8002982 800297e: 2300 movs r3, #0 8002980: 60bb str r3, [r7, #8] if (tmp_hadc_slave.Instance == NULL) 8002982: 68bb ldr r3, [r7, #8] 8002984: 2b00 cmp r3, #0 8002986: d10b bne.n 80029a0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002988: 687b ldr r3, [r7, #4] 800298a: 6ddb ldr r3, [r3, #92] @ 0x5c 800298c: f043 0220 orr.w r2, r3, #32 8002990: 687b ldr r3, [r7, #4] 8002992: 65da str r2, [r3, #92] @ 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); 8002994: 687b ldr r3, [r7, #4] 8002996: 2200 movs r2, #0 8002998: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_ERROR; 800299c: 2301 movs r3, #1 800299e: e06a b.n 8002a76 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); 80029a0: 68bb ldr r3, [r7, #8] 80029a2: 4618 mov r0, r3 80029a4: f7ff ffb8 bl 8002918 80029a8: 67b8 str r0, [r7, #120] @ 0x78 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80029aa: 687b ldr r3, [r7, #4] 80029ac: 681b ldr r3, [r3, #0] 80029ae: 4618 mov r0, r3 80029b0: f7ff ffb2 bl 8002918 80029b4: 4603 mov r3, r0 80029b6: 2b00 cmp r3, #0 80029b8: d14c bne.n 8002a54 && (tmp_hadc_slave_conversion_on_going == 0UL)) 80029ba: 6fbb ldr r3, [r7, #120] @ 0x78 80029bc: 2b00 cmp r3, #0 80029be: d149 bne.n 8002a54 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 80029c0: 4b30 ldr r3, [pc, #192] @ (8002a84 ) 80029c2: 677b str r3, [r7, #116] @ 0x74 /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 80029c4: 683b ldr r3, [r7, #0] 80029c6: 681b ldr r3, [r3, #0] 80029c8: 2b00 cmp r3, #0 80029ca: d028 beq.n 8002a1e { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 80029cc: 6f7b ldr r3, [r7, #116] @ 0x74 80029ce: 689b ldr r3, [r3, #8] 80029d0: f423 4260 bic.w r2, r3, #57344 @ 0xe000 80029d4: 683b ldr r3, [r7, #0] 80029d6: 6859 ldr r1, [r3, #4] 80029d8: 687b ldr r3, [r7, #4] 80029da: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 80029de: 035b lsls r3, r3, #13 80029e0: 430b orrs r3, r1 80029e2: 431a orrs r2, r3 80029e4: 6f7b ldr r3, [r7, #116] @ 0x74 80029e6: 609a str r2, [r3, #8] /* from 1 to 10 clock cycles for 10 bits, */ /* from 1 to 8 clock cycles for 8 bits */ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80029e8: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 80029ec: f7ff ff81 bl 80028f2 80029f0: 4604 mov r4, r0 80029f2: 4823 ldr r0, [pc, #140] @ (8002a80 ) 80029f4: f7ff ff7d bl 80028f2 80029f8: 4603 mov r3, r0 80029fa: 4323 orrs r3, r4 80029fc: 2b00 cmp r3, #0 80029fe: d133 bne.n 8002a68 { MODIFY_REG(tmpADC_Common->CCR, 8002a00: 6f7b ldr r3, [r7, #116] @ 0x74 8002a02: 689b ldr r3, [r3, #8] 8002a04: f423 6371 bic.w r3, r3, #3856 @ 0xf10 8002a08: f023 030f bic.w r3, r3, #15 8002a0c: 683a ldr r2, [r7, #0] 8002a0e: 6811 ldr r1, [r2, #0] 8002a10: 683a ldr r2, [r7, #0] 8002a12: 6892 ldr r2, [r2, #8] 8002a14: 430a orrs r2, r1 8002a16: 431a orrs r2, r3 8002a18: 6f7b ldr r3, [r7, #116] @ 0x74 8002a1a: 609a str r2, [r3, #8] if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002a1c: e024 b.n 8002a68 ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); 8002a1e: 6f7b ldr r3, [r7, #116] @ 0x74 8002a20: 689b ldr r3, [r3, #8] 8002a22: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8002a26: 6f7b ldr r3, [r7, #116] @ 0x74 8002a28: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8002a2a: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 8002a2e: f7ff ff60 bl 80028f2 8002a32: 4604 mov r4, r0 8002a34: 4812 ldr r0, [pc, #72] @ (8002a80 ) 8002a36: f7ff ff5c bl 80028f2 8002a3a: 4603 mov r3, r0 8002a3c: 4323 orrs r3, r4 8002a3e: 2b00 cmp r3, #0 8002a40: d112 bne.n 8002a68 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8002a42: 6f7b ldr r3, [r7, #116] @ 0x74 8002a44: 689b ldr r3, [r3, #8] 8002a46: f423 6371 bic.w r3, r3, #3856 @ 0xf10 8002a4a: f023 030f bic.w r3, r3, #15 8002a4e: 6f7a ldr r2, [r7, #116] @ 0x74 8002a50: 6093 str r3, [r2, #8] if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002a52: e009 b.n 8002a68 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8002a54: 687b ldr r3, [r7, #4] 8002a56: 6ddb ldr r3, [r3, #92] @ 0x5c 8002a58: f043 0220 orr.w r2, r3, #32 8002a5c: 687b ldr r3, [r7, #4] 8002a5e: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; 8002a60: 2301 movs r3, #1 8002a62: f887 307f strb.w r3, [r7, #127] @ 0x7f 8002a66: e000 b.n 8002a6a if (pMultimode->Mode != ADC_MODE_INDEPENDENT) 8002a68: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 8002a6a: 687b ldr r3, [r7, #4] 8002a6c: 2200 movs r2, #0 8002a6e: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; 8002a72: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8002a76: 4618 mov r0, r3 8002a78: 3784 adds r7, #132 @ 0x84 8002a7a: 46bd mov sp, r7 8002a7c: bd90 pop {r4, r7, pc} 8002a7e: bf00 nop 8002a80: 50000100 .word 0x50000100 8002a84: 50000300 .word 0x50000300 08002a88 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002a88: b480 push {r7} 8002a8a: b085 sub sp, #20 8002a8c: af00 add r7, sp, #0 8002a8e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002a90: 687b ldr r3, [r7, #4] 8002a92: f003 0307 and.w r3, r3, #7 8002a96: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8002a98: 4b0c ldr r3, [pc, #48] @ (8002acc <__NVIC_SetPriorityGrouping+0x44>) 8002a9a: 68db ldr r3, [r3, #12] 8002a9c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8002a9e: 68ba ldr r2, [r7, #8] 8002aa0: f64f 03ff movw r3, #63743 @ 0xf8ff 8002aa4: 4013 ands r3, r2 8002aa6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8002aa8: 68fb ldr r3, [r7, #12] 8002aaa: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8002aac: 68bb ldr r3, [r7, #8] 8002aae: 4313 orrs r3, r2 reg_value = (reg_value | 8002ab0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8002ab4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8002ab8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8002aba: 4a04 ldr r2, [pc, #16] @ (8002acc <__NVIC_SetPriorityGrouping+0x44>) 8002abc: 68bb ldr r3, [r7, #8] 8002abe: 60d3 str r3, [r2, #12] } 8002ac0: bf00 nop 8002ac2: 3714 adds r7, #20 8002ac4: 46bd mov sp, r7 8002ac6: f85d 7b04 ldr.w r7, [sp], #4 8002aca: 4770 bx lr 8002acc: e000ed00 .word 0xe000ed00 08002ad0 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8002ad0: b480 push {r7} 8002ad2: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8002ad4: 4b04 ldr r3, [pc, #16] @ (8002ae8 <__NVIC_GetPriorityGrouping+0x18>) 8002ad6: 68db ldr r3, [r3, #12] 8002ad8: 0a1b lsrs r3, r3, #8 8002ada: f003 0307 and.w r3, r3, #7 } 8002ade: 4618 mov r0, r3 8002ae0: 46bd mov sp, r7 8002ae2: f85d 7b04 ldr.w r7, [sp], #4 8002ae6: 4770 bx lr 8002ae8: e000ed00 .word 0xe000ed00 08002aec <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8002aec: b480 push {r7} 8002aee: b083 sub sp, #12 8002af0: af00 add r7, sp, #0 8002af2: 4603 mov r3, r0 8002af4: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002af6: f997 3007 ldrsb.w r3, [r7, #7] 8002afa: 2b00 cmp r3, #0 8002afc: db0b blt.n 8002b16 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002afe: 79fb ldrb r3, [r7, #7] 8002b00: f003 021f and.w r2, r3, #31 8002b04: 4907 ldr r1, [pc, #28] @ (8002b24 <__NVIC_EnableIRQ+0x38>) 8002b06: f997 3007 ldrsb.w r3, [r7, #7] 8002b0a: 095b lsrs r3, r3, #5 8002b0c: 2001 movs r0, #1 8002b0e: fa00 f202 lsl.w r2, r0, r2 8002b12: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8002b16: bf00 nop 8002b18: 370c adds r7, #12 8002b1a: 46bd mov sp, r7 8002b1c: f85d 7b04 ldr.w r7, [sp], #4 8002b20: 4770 bx lr 8002b22: bf00 nop 8002b24: e000e100 .word 0xe000e100 08002b28 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8002b28: b480 push {r7} 8002b2a: b083 sub sp, #12 8002b2c: af00 add r7, sp, #0 8002b2e: 4603 mov r3, r0 8002b30: 6039 str r1, [r7, #0] 8002b32: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8002b34: f997 3007 ldrsb.w r3, [r7, #7] 8002b38: 2b00 cmp r3, #0 8002b3a: db0a blt.n 8002b52 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002b3c: 683b ldr r3, [r7, #0] 8002b3e: b2da uxtb r2, r3 8002b40: 490c ldr r1, [pc, #48] @ (8002b74 <__NVIC_SetPriority+0x4c>) 8002b42: f997 3007 ldrsb.w r3, [r7, #7] 8002b46: 0112 lsls r2, r2, #4 8002b48: b2d2 uxtb r2, r2 8002b4a: 440b add r3, r1 8002b4c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8002b50: e00a b.n 8002b68 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002b52: 683b ldr r3, [r7, #0] 8002b54: b2da uxtb r2, r3 8002b56: 4908 ldr r1, [pc, #32] @ (8002b78 <__NVIC_SetPriority+0x50>) 8002b58: 79fb ldrb r3, [r7, #7] 8002b5a: f003 030f and.w r3, r3, #15 8002b5e: 3b04 subs r3, #4 8002b60: 0112 lsls r2, r2, #4 8002b62: b2d2 uxtb r2, r2 8002b64: 440b add r3, r1 8002b66: 761a strb r2, [r3, #24] } 8002b68: bf00 nop 8002b6a: 370c adds r7, #12 8002b6c: 46bd mov sp, r7 8002b6e: f85d 7b04 ldr.w r7, [sp], #4 8002b72: 4770 bx lr 8002b74: e000e100 .word 0xe000e100 8002b78: e000ed00 .word 0xe000ed00 08002b7c : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8002b7c: b480 push {r7} 8002b7e: b089 sub sp, #36 @ 0x24 8002b80: af00 add r7, sp, #0 8002b82: 60f8 str r0, [r7, #12] 8002b84: 60b9 str r1, [r7, #8] 8002b86: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002b88: 68fb ldr r3, [r7, #12] 8002b8a: f003 0307 and.w r3, r3, #7 8002b8e: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002b90: 69fb ldr r3, [r7, #28] 8002b92: f1c3 0307 rsb r3, r3, #7 8002b96: 2b04 cmp r3, #4 8002b98: bf28 it cs 8002b9a: 2304 movcs r3, #4 8002b9c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8002b9e: 69fb ldr r3, [r7, #28] 8002ba0: 3304 adds r3, #4 8002ba2: 2b06 cmp r3, #6 8002ba4: d902 bls.n 8002bac 8002ba6: 69fb ldr r3, [r7, #28] 8002ba8: 3b03 subs r3, #3 8002baa: e000 b.n 8002bae 8002bac: 2300 movs r3, #0 8002bae: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002bb0: f04f 32ff mov.w r2, #4294967295 8002bb4: 69bb ldr r3, [r7, #24] 8002bb6: fa02 f303 lsl.w r3, r2, r3 8002bba: 43da mvns r2, r3 8002bbc: 68bb ldr r3, [r7, #8] 8002bbe: 401a ands r2, r3 8002bc0: 697b ldr r3, [r7, #20] 8002bc2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8002bc4: f04f 31ff mov.w r1, #4294967295 8002bc8: 697b ldr r3, [r7, #20] 8002bca: fa01 f303 lsl.w r3, r1, r3 8002bce: 43d9 mvns r1, r3 8002bd0: 687b ldr r3, [r7, #4] 8002bd2: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8002bd4: 4313 orrs r3, r2 ); } 8002bd6: 4618 mov r0, r3 8002bd8: 3724 adds r7, #36 @ 0x24 8002bda: 46bd mov sp, r7 8002bdc: f85d 7b04 ldr.w r7, [sp], #4 8002be0: 4770 bx lr ... 08002be4 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8002be4: b580 push {r7, lr} 8002be6: b082 sub sp, #8 8002be8: af00 add r7, sp, #0 8002bea: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8002bec: 687b ldr r3, [r7, #4] 8002bee: 3b01 subs r3, #1 8002bf0: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002bf4: d301 bcc.n 8002bfa { return (1UL); /* Reload value impossible */ 8002bf6: 2301 movs r3, #1 8002bf8: e00f b.n 8002c1a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8002bfa: 4a0a ldr r2, [pc, #40] @ (8002c24 ) 8002bfc: 687b ldr r3, [r7, #4] 8002bfe: 3b01 subs r3, #1 8002c00: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8002c02: 210f movs r1, #15 8002c04: f04f 30ff mov.w r0, #4294967295 8002c08: f7ff ff8e bl 8002b28 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8002c0c: 4b05 ldr r3, [pc, #20] @ (8002c24 ) 8002c0e: 2200 movs r2, #0 8002c10: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8002c12: 4b04 ldr r3, [pc, #16] @ (8002c24 ) 8002c14: 2207 movs r2, #7 8002c16: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8002c18: 2300 movs r3, #0 } 8002c1a: 4618 mov r0, r3 8002c1c: 3708 adds r7, #8 8002c1e: 46bd mov sp, r7 8002c20: bd80 pop {r7, pc} 8002c22: bf00 nop 8002c24: e000e010 .word 0xe000e010 08002c28 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8002c28: b580 push {r7, lr} 8002c2a: b082 sub sp, #8 8002c2c: af00 add r7, sp, #0 8002c2e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8002c30: 6878 ldr r0, [r7, #4] 8002c32: f7ff ff29 bl 8002a88 <__NVIC_SetPriorityGrouping> } 8002c36: bf00 nop 8002c38: 3708 adds r7, #8 8002c3a: 46bd mov sp, r7 8002c3c: bd80 pop {r7, pc} 08002c3e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002c3e: b580 push {r7, lr} 8002c40: b086 sub sp, #24 8002c42: af00 add r7, sp, #0 8002c44: 4603 mov r3, r0 8002c46: 60b9 str r1, [r7, #8] 8002c48: 607a str r2, [r7, #4] 8002c4a: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8002c4c: f7ff ff40 bl 8002ad0 <__NVIC_GetPriorityGrouping> 8002c50: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002c52: 687a ldr r2, [r7, #4] 8002c54: 68b9 ldr r1, [r7, #8] 8002c56: 6978 ldr r0, [r7, #20] 8002c58: f7ff ff90 bl 8002b7c 8002c5c: 4602 mov r2, r0 8002c5e: f997 300f ldrsb.w r3, [r7, #15] 8002c62: 4611 mov r1, r2 8002c64: 4618 mov r0, r3 8002c66: f7ff ff5f bl 8002b28 <__NVIC_SetPriority> } 8002c6a: bf00 nop 8002c6c: 3718 adds r7, #24 8002c6e: 46bd mov sp, r7 8002c70: bd80 pop {r7, pc} 08002c72 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002c72: b580 push {r7, lr} 8002c74: b082 sub sp, #8 8002c76: af00 add r7, sp, #0 8002c78: 4603 mov r3, r0 8002c7a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8002c7c: f997 3007 ldrsb.w r3, [r7, #7] 8002c80: 4618 mov r0, r3 8002c82: f7ff ff33 bl 8002aec <__NVIC_EnableIRQ> } 8002c86: bf00 nop 8002c88: 3708 adds r7, #8 8002c8a: 46bd mov sp, r7 8002c8c: bd80 pop {r7, pc} 08002c8e : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8002c8e: b580 push {r7, lr} 8002c90: b082 sub sp, #8 8002c92: af00 add r7, sp, #0 8002c94: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8002c96: 6878 ldr r0, [r7, #4] 8002c98: f7ff ffa4 bl 8002be4 8002c9c: 4603 mov r3, r0 } 8002c9e: 4618 mov r0, r3 8002ca0: 3708 adds r7, #8 8002ca2: 46bd mov sp, r7 8002ca4: bd80 pop {r7, pc} 08002ca6 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8002ca6: b480 push {r7} 8002ca8: b085 sub sp, #20 8002caa: af00 add r7, sp, #0 8002cac: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002cae: 2300 movs r3, #0 8002cb0: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) 8002cb2: 687b ldr r3, [r7, #4] 8002cb4: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8002cb8: b2db uxtb r3, r3 8002cba: 2b02 cmp r3, #2 8002cbc: d005 beq.n 8002cca { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002cbe: 687b ldr r3, [r7, #4] 8002cc0: 2204 movs r2, #4 8002cc2: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 8002cc4: 2301 movs r3, #1 8002cc6: 73fb strb r3, [r7, #15] 8002cc8: e037 b.n 8002d3a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002cca: 687b ldr r3, [r7, #4] 8002ccc: 681b ldr r3, [r3, #0] 8002cce: 681a ldr r2, [r3, #0] 8002cd0: 687b ldr r3, [r7, #4] 8002cd2: 681b ldr r3, [r3, #0] 8002cd4: f022 020e bic.w r2, r2, #14 8002cd8: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8002cda: 687b ldr r3, [r7, #4] 8002cdc: 6c9b ldr r3, [r3, #72] @ 0x48 8002cde: 681a ldr r2, [r3, #0] 8002ce0: 687b ldr r3, [r7, #4] 8002ce2: 6c9b ldr r3, [r3, #72] @ 0x48 8002ce4: f422 7280 bic.w r2, r2, #256 @ 0x100 8002ce8: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002cea: 687b ldr r3, [r7, #4] 8002cec: 681b ldr r3, [r3, #0] 8002cee: 681a ldr r2, [r3, #0] 8002cf0: 687b ldr r3, [r7, #4] 8002cf2: 681b ldr r3, [r3, #0] 8002cf4: f022 0201 bic.w r2, r2, #1 8002cf8: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 8002cfa: 687b ldr r3, [r7, #4] 8002cfc: 6c5b ldr r3, [r3, #68] @ 0x44 8002cfe: f003 021f and.w r2, r3, #31 8002d02: 687b ldr r3, [r7, #4] 8002d04: 6c1b ldr r3, [r3, #64] @ 0x40 8002d06: 2101 movs r1, #1 8002d08: fa01 f202 lsl.w r2, r1, r2 8002d0c: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002d0e: 687b ldr r3, [r7, #4] 8002d10: 6cdb ldr r3, [r3, #76] @ 0x4c 8002d12: 687a ldr r2, [r7, #4] 8002d14: 6d12 ldr r2, [r2, #80] @ 0x50 8002d16: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8002d18: 687b ldr r3, [r7, #4] 8002d1a: 6d5b ldr r3, [r3, #84] @ 0x54 8002d1c: 2b00 cmp r3, #0 8002d1e: d00c beq.n 8002d3a { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8002d20: 687b ldr r3, [r7, #4] 8002d22: 6d5b ldr r3, [r3, #84] @ 0x54 8002d24: 681a ldr r2, [r3, #0] 8002d26: 687b ldr r3, [r7, #4] 8002d28: 6d5b ldr r3, [r3, #84] @ 0x54 8002d2a: f422 7280 bic.w r2, r2, #256 @ 0x100 8002d2e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002d30: 687b ldr r3, [r7, #4] 8002d32: 6d9b ldr r3, [r3, #88] @ 0x58 8002d34: 687a ldr r2, [r7, #4] 8002d36: 6dd2 ldr r2, [r2, #92] @ 0x5c 8002d38: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002d3a: 687b ldr r3, [r7, #4] 8002d3c: 2201 movs r2, #1 8002d3e: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d42: 687b ldr r3, [r7, #4] 8002d44: 2200 movs r2, #0 8002d46: f883 2024 strb.w r2, [r3, #36] @ 0x24 return status; 8002d4a: 7bfb ldrb r3, [r7, #15] } 8002d4c: 4618 mov r0, r3 8002d4e: 3714 adds r7, #20 8002d50: 46bd mov sp, r7 8002d52: f85d 7b04 ldr.w r7, [sp], #4 8002d56: 4770 bx lr 08002d58 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8002d58: b580 push {r7, lr} 8002d5a: b084 sub sp, #16 8002d5c: af00 add r7, sp, #0 8002d5e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002d60: 2300 movs r3, #0 8002d62: 73fb strb r3, [r7, #15] if (HAL_DMA_STATE_BUSY != hdma->State) 8002d64: 687b ldr r3, [r7, #4] 8002d66: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8002d6a: b2db uxtb r3, r3 8002d6c: 2b02 cmp r3, #2 8002d6e: d00d beq.n 8002d8c { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8002d70: 687b ldr r3, [r7, #4] 8002d72: 2204 movs r2, #4 8002d74: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002d76: 687b ldr r3, [r7, #4] 8002d78: 2201 movs r2, #1 8002d7a: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002d7e: 687b ldr r3, [r7, #4] 8002d80: 2200 movs r2, #0 8002d82: f883 2024 strb.w r2, [r3, #36] @ 0x24 status = HAL_ERROR; 8002d86: 2301 movs r3, #1 8002d88: 73fb strb r3, [r7, #15] 8002d8a: e047 b.n 8002e1c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 681b ldr r3, [r3, #0] 8002d90: 681a ldr r2, [r3, #0] 8002d92: 687b ldr r3, [r7, #4] 8002d94: 681b ldr r3, [r3, #0] 8002d96: f022 020e bic.w r2, r2, #14 8002d9a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8002d9c: 687b ldr r3, [r7, #4] 8002d9e: 681b ldr r3, [r3, #0] 8002da0: 681a ldr r2, [r3, #0] 8002da2: 687b ldr r3, [r7, #4] 8002da4: 681b ldr r3, [r3, #0] 8002da6: f022 0201 bic.w r2, r2, #1 8002daa: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8002dac: 687b ldr r3, [r7, #4] 8002dae: 6c9b ldr r3, [r3, #72] @ 0x48 8002db0: 681a ldr r2, [r3, #0] 8002db2: 687b ldr r3, [r7, #4] 8002db4: 6c9b ldr r3, [r3, #72] @ 0x48 8002db6: f422 7280 bic.w r2, r2, #256 @ 0x100 8002dba: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); 8002dbc: 687b ldr r3, [r7, #4] 8002dbe: 6c5b ldr r3, [r3, #68] @ 0x44 8002dc0: f003 021f and.w r2, r3, #31 8002dc4: 687b ldr r3, [r7, #4] 8002dc6: 6c1b ldr r3, [r3, #64] @ 0x40 8002dc8: 2101 movs r1, #1 8002dca: fa01 f202 lsl.w r2, r1, r2 8002dce: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8002dd0: 687b ldr r3, [r7, #4] 8002dd2: 6cdb ldr r3, [r3, #76] @ 0x4c 8002dd4: 687a ldr r2, [r7, #4] 8002dd6: 6d12 ldr r2, [r2, #80] @ 0x50 8002dd8: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 8002dda: 687b ldr r3, [r7, #4] 8002ddc: 6d5b ldr r3, [r3, #84] @ 0x54 8002dde: 2b00 cmp r3, #0 8002de0: d00c beq.n 8002dfc { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8002de2: 687b ldr r3, [r7, #4] 8002de4: 6d5b ldr r3, [r3, #84] @ 0x54 8002de6: 681a ldr r2, [r3, #0] 8002de8: 687b ldr r3, [r7, #4] 8002dea: 6d5b ldr r3, [r3, #84] @ 0x54 8002dec: f422 7280 bic.w r2, r2, #256 @ 0x100 8002df0: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8002df2: 687b ldr r3, [r7, #4] 8002df4: 6d9b ldr r3, [r3, #88] @ 0x58 8002df6: 687a ldr r2, [r7, #4] 8002df8: 6dd2 ldr r2, [r2, #92] @ 0x5c 8002dfa: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8002dfc: 687b ldr r3, [r7, #4] 8002dfe: 2201 movs r2, #1 8002e00: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8002e04: 687b ldr r3, [r7, #4] 8002e06: 2200 movs r2, #0 8002e08: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 8002e0c: 687b ldr r3, [r7, #4] 8002e0e: 6b9b ldr r3, [r3, #56] @ 0x38 8002e10: 2b00 cmp r3, #0 8002e12: d003 beq.n 8002e1c { hdma->XferAbortCallback(hdma); 8002e14: 687b ldr r3, [r7, #4] 8002e16: 6b9b ldr r3, [r3, #56] @ 0x38 8002e18: 6878 ldr r0, [r7, #4] 8002e1a: 4798 blx r3 } } return status; 8002e1c: 7bfb ldrb r3, [r7, #15] } 8002e1e: 4618 mov r0, r3 8002e20: 3710 adds r7, #16 8002e22: 46bd mov sp, r7 8002e24: bd80 pop {r7, pc} ... 08002e28 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002e28: b480 push {r7} 8002e2a: b087 sub sp, #28 8002e2c: af00 add r7, sp, #0 8002e2e: 6078 str r0, [r7, #4] 8002e30: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8002e32: 2300 movs r3, #0 8002e34: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) 8002e36: e15a b.n 80030ee { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8002e38: 683b ldr r3, [r7, #0] 8002e3a: 681a ldr r2, [r3, #0] 8002e3c: 2101 movs r1, #1 8002e3e: 697b ldr r3, [r7, #20] 8002e40: fa01 f303 lsl.w r3, r1, r3 8002e44: 4013 ands r3, r2 8002e46: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8002e48: 68fb ldr r3, [r7, #12] 8002e4a: 2b00 cmp r3, #0 8002e4c: f000 814c beq.w 80030e8 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8002e50: 683b ldr r3, [r7, #0] 8002e52: 685b ldr r3, [r3, #4] 8002e54: f003 0303 and.w r3, r3, #3 8002e58: 2b01 cmp r3, #1 8002e5a: d005 beq.n 8002e68 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8002e5c: 683b ldr r3, [r7, #0] 8002e5e: 685b ldr r3, [r3, #4] 8002e60: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || 8002e64: 2b02 cmp r3, #2 8002e66: d130 bne.n 8002eca { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002e68: 687b ldr r3, [r7, #4] 8002e6a: 689b ldr r3, [r3, #8] 8002e6c: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8002e6e: 697b ldr r3, [r7, #20] 8002e70: 005b lsls r3, r3, #1 8002e72: 2203 movs r2, #3 8002e74: fa02 f303 lsl.w r3, r2, r3 8002e78: 43db mvns r3, r3 8002e7a: 693a ldr r2, [r7, #16] 8002e7c: 4013 ands r3, r2 8002e7e: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2U)); 8002e80: 683b ldr r3, [r7, #0] 8002e82: 68da ldr r2, [r3, #12] 8002e84: 697b ldr r3, [r7, #20] 8002e86: 005b lsls r3, r3, #1 8002e88: fa02 f303 lsl.w r3, r2, r3 8002e8c: 693a ldr r2, [r7, #16] 8002e8e: 4313 orrs r3, r2 8002e90: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8002e92: 687b ldr r3, [r7, #4] 8002e94: 693a ldr r2, [r7, #16] 8002e96: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002e98: 687b ldr r3, [r7, #4] 8002e9a: 685b ldr r3, [r3, #4] 8002e9c: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8002e9e: 2201 movs r2, #1 8002ea0: 697b ldr r3, [r7, #20] 8002ea2: fa02 f303 lsl.w r3, r2, r3 8002ea6: 43db mvns r3, r3 8002ea8: 693a ldr r2, [r7, #16] 8002eaa: 4013 ands r3, r2 8002eac: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002eae: 683b ldr r3, [r7, #0] 8002eb0: 685b ldr r3, [r3, #4] 8002eb2: 091b lsrs r3, r3, #4 8002eb4: f003 0201 and.w r2, r3, #1 8002eb8: 697b ldr r3, [r7, #20] 8002eba: fa02 f303 lsl.w r3, r2, r3 8002ebe: 693a ldr r2, [r7, #16] 8002ec0: 4313 orrs r3, r2 8002ec2: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8002ec4: 687b ldr r3, [r7, #4] 8002ec6: 693a ldr r2, [r7, #16] 8002ec8: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002eca: 683b ldr r3, [r7, #0] 8002ecc: 685b ldr r3, [r3, #4] 8002ece: f003 0303 and.w r3, r3, #3 8002ed2: 2b03 cmp r3, #3 8002ed4: d017 beq.n 8002f06 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002ed6: 687b ldr r3, [r7, #4] 8002ed8: 68db ldr r3, [r3, #12] 8002eda: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8002edc: 697b ldr r3, [r7, #20] 8002ede: 005b lsls r3, r3, #1 8002ee0: 2203 movs r2, #3 8002ee2: fa02 f303 lsl.w r3, r2, r3 8002ee6: 43db mvns r3, r3 8002ee8: 693a ldr r2, [r7, #16] 8002eea: 4013 ands r3, r2 8002eec: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002eee: 683b ldr r3, [r7, #0] 8002ef0: 689a ldr r2, [r3, #8] 8002ef2: 697b ldr r3, [r7, #20] 8002ef4: 005b lsls r3, r3, #1 8002ef6: fa02 f303 lsl.w r3, r2, r3 8002efa: 693a ldr r2, [r7, #16] 8002efc: 4313 orrs r3, r2 8002efe: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8002f00: 687b ldr r3, [r7, #4] 8002f02: 693a ldr r2, [r7, #16] 8002f04: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002f06: 683b ldr r3, [r7, #0] 8002f08: 685b ldr r3, [r3, #4] 8002f0a: f003 0303 and.w r3, r3, #3 8002f0e: 2b02 cmp r3, #2 8002f10: d123 bne.n 8002f5a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002f12: 697b ldr r3, [r7, #20] 8002f14: 08da lsrs r2, r3, #3 8002f16: 687b ldr r3, [r7, #4] 8002f18: 3208 adds r2, #8 8002f1a: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002f1e: 613b str r3, [r7, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8002f20: 697b ldr r3, [r7, #20] 8002f22: f003 0307 and.w r3, r3, #7 8002f26: 009b lsls r3, r3, #2 8002f28: 220f movs r2, #15 8002f2a: fa02 f303 lsl.w r3, r2, r3 8002f2e: 43db mvns r3, r3 8002f30: 693a ldr r2, [r7, #16] 8002f32: 4013 ands r3, r2 8002f34: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8002f36: 683b ldr r3, [r7, #0] 8002f38: 691a ldr r2, [r3, #16] 8002f3a: 697b ldr r3, [r7, #20] 8002f3c: f003 0307 and.w r3, r3, #7 8002f40: 009b lsls r3, r3, #2 8002f42: fa02 f303 lsl.w r3, r2, r3 8002f46: 693a ldr r2, [r7, #16] 8002f48: 4313 orrs r3, r2 8002f4a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3U] = temp; 8002f4c: 697b ldr r3, [r7, #20] 8002f4e: 08da lsrs r2, r3, #3 8002f50: 687b ldr r3, [r7, #4] 8002f52: 3208 adds r2, #8 8002f54: 6939 ldr r1, [r7, #16] 8002f56: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002f5a: 687b ldr r3, [r7, #4] 8002f5c: 681b ldr r3, [r3, #0] 8002f5e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8002f60: 697b ldr r3, [r7, #20] 8002f62: 005b lsls r3, r3, #1 8002f64: 2203 movs r2, #3 8002f66: fa02 f303 lsl.w r3, r2, r3 8002f6a: 43db mvns r3, r3 8002f6c: 693a ldr r2, [r7, #16] 8002f6e: 4013 ands r3, r2 8002f70: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002f72: 683b ldr r3, [r7, #0] 8002f74: 685b ldr r3, [r3, #4] 8002f76: f003 0203 and.w r2, r3, #3 8002f7a: 697b ldr r3, [r7, #20] 8002f7c: 005b lsls r3, r3, #1 8002f7e: fa02 f303 lsl.w r3, r2, r3 8002f82: 693a ldr r2, [r7, #16] 8002f84: 4313 orrs r3, r2 8002f86: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8002f88: 687b ldr r3, [r7, #4] 8002f8a: 693a ldr r2, [r7, #16] 8002f8c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8002f8e: 683b ldr r3, [r7, #0] 8002f90: 685b ldr r3, [r3, #4] 8002f92: f403 3340 and.w r3, r3, #196608 @ 0x30000 8002f96: 2b00 cmp r3, #0 8002f98: f000 80a6 beq.w 80030e8 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002f9c: 4b5b ldr r3, [pc, #364] @ (800310c ) 8002f9e: 6e1b ldr r3, [r3, #96] @ 0x60 8002fa0: 4a5a ldr r2, [pc, #360] @ (800310c ) 8002fa2: f043 0301 orr.w r3, r3, #1 8002fa6: 6613 str r3, [r2, #96] @ 0x60 8002fa8: 4b58 ldr r3, [pc, #352] @ (800310c ) 8002faa: 6e1b ldr r3, [r3, #96] @ 0x60 8002fac: f003 0301 and.w r3, r3, #1 8002fb0: 60bb str r3, [r7, #8] 8002fb2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2U]; 8002fb4: 4a56 ldr r2, [pc, #344] @ (8003110 ) 8002fb6: 697b ldr r3, [r7, #20] 8002fb8: 089b lsrs r3, r3, #2 8002fba: 3302 adds r3, #2 8002fbc: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002fc0: 613b str r3, [r7, #16] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8002fc2: 697b ldr r3, [r7, #20] 8002fc4: f003 0303 and.w r3, r3, #3 8002fc8: 009b lsls r3, r3, #2 8002fca: 220f movs r2, #15 8002fcc: fa02 f303 lsl.w r3, r2, r3 8002fd0: 43db mvns r3, r3 8002fd2: 693a ldr r2, [r7, #16] 8002fd4: 4013 ands r3, r2 8002fd6: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8002fd8: 687b ldr r3, [r7, #4] 8002fda: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 8002fde: d01f beq.n 8003020 8002fe0: 687b ldr r3, [r7, #4] 8002fe2: 4a4c ldr r2, [pc, #304] @ (8003114 ) 8002fe4: 4293 cmp r3, r2 8002fe6: d019 beq.n 800301c 8002fe8: 687b ldr r3, [r7, #4] 8002fea: 4a4b ldr r2, [pc, #300] @ (8003118 ) 8002fec: 4293 cmp r3, r2 8002fee: d013 beq.n 8003018 8002ff0: 687b ldr r3, [r7, #4] 8002ff2: 4a4a ldr r2, [pc, #296] @ (800311c ) 8002ff4: 4293 cmp r3, r2 8002ff6: d00d beq.n 8003014 8002ff8: 687b ldr r3, [r7, #4] 8002ffa: 4a49 ldr r2, [pc, #292] @ (8003120 ) 8002ffc: 4293 cmp r3, r2 8002ffe: d007 beq.n 8003010 8003000: 687b ldr r3, [r7, #4] 8003002: 4a48 ldr r2, [pc, #288] @ (8003124 ) 8003004: 4293 cmp r3, r2 8003006: d101 bne.n 800300c 8003008: 2305 movs r3, #5 800300a: e00a b.n 8003022 800300c: 2306 movs r3, #6 800300e: e008 b.n 8003022 8003010: 2304 movs r3, #4 8003012: e006 b.n 8003022 8003014: 2303 movs r3, #3 8003016: e004 b.n 8003022 8003018: 2302 movs r3, #2 800301a: e002 b.n 8003022 800301c: 2301 movs r3, #1 800301e: e000 b.n 8003022 8003020: 2300 movs r3, #0 8003022: 697a ldr r2, [r7, #20] 8003024: f002 0203 and.w r2, r2, #3 8003028: 0092 lsls r2, r2, #2 800302a: 4093 lsls r3, r2 800302c: 693a ldr r2, [r7, #16] 800302e: 4313 orrs r3, r2 8003030: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2U] = temp; 8003032: 4937 ldr r1, [pc, #220] @ (8003110 ) 8003034: 697b ldr r3, [r7, #20] 8003036: 089b lsrs r3, r3, #2 8003038: 3302 adds r3, #2 800303a: 693a ldr r2, [r7, #16] 800303c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8003040: 4b39 ldr r3, [pc, #228] @ (8003128 ) 8003042: 689b ldr r3, [r3, #8] 8003044: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003046: 68fb ldr r3, [r7, #12] 8003048: 43db mvns r3, r3 800304a: 693a ldr r2, [r7, #16] 800304c: 4013 ands r3, r2 800304e: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8003050: 683b ldr r3, [r7, #0] 8003052: 685b ldr r3, [r3, #4] 8003054: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8003058: 2b00 cmp r3, #0 800305a: d003 beq.n 8003064 { temp |= iocurrent; 800305c: 693a ldr r2, [r7, #16] 800305e: 68fb ldr r3, [r7, #12] 8003060: 4313 orrs r3, r2 8003062: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8003064: 4a30 ldr r2, [pc, #192] @ (8003128 ) 8003066: 693b ldr r3, [r7, #16] 8003068: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; 800306a: 4b2f ldr r3, [pc, #188] @ (8003128 ) 800306c: 68db ldr r3, [r3, #12] 800306e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8003070: 68fb ldr r3, [r7, #12] 8003072: 43db mvns r3, r3 8003074: 693a ldr r2, [r7, #16] 8003076: 4013 ands r3, r2 8003078: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800307a: 683b ldr r3, [r7, #0] 800307c: 685b ldr r3, [r3, #4] 800307e: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8003082: 2b00 cmp r3, #0 8003084: d003 beq.n 800308e { temp |= iocurrent; 8003086: 693a ldr r2, [r7, #16] 8003088: 68fb ldr r3, [r7, #12] 800308a: 4313 orrs r3, r2 800308c: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 800308e: 4a26 ldr r2, [pc, #152] @ (8003128 ) 8003090: 693b ldr r3, [r7, #16] 8003092: 60d3 str r3, [r2, #12] temp = EXTI->EMR1; 8003094: 4b24 ldr r3, [pc, #144] @ (8003128 ) 8003096: 685b ldr r3, [r3, #4] 8003098: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800309a: 68fb ldr r3, [r7, #12] 800309c: 43db mvns r3, r3 800309e: 693a ldr r2, [r7, #16] 80030a0: 4013 ands r3, r2 80030a2: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 80030a4: 683b ldr r3, [r7, #0] 80030a6: 685b ldr r3, [r3, #4] 80030a8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80030ac: 2b00 cmp r3, #0 80030ae: d003 beq.n 80030b8 { temp |= iocurrent; 80030b0: 693a ldr r2, [r7, #16] 80030b2: 68fb ldr r3, [r7, #12] 80030b4: 4313 orrs r3, r2 80030b6: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 80030b8: 4a1b ldr r2, [pc, #108] @ (8003128 ) 80030ba: 693b ldr r3, [r7, #16] 80030bc: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 80030be: 4b1a ldr r3, [pc, #104] @ (8003128 ) 80030c0: 681b ldr r3, [r3, #0] 80030c2: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80030c4: 68fb ldr r3, [r7, #12] 80030c6: 43db mvns r3, r3 80030c8: 693a ldr r2, [r7, #16] 80030ca: 4013 ands r3, r2 80030cc: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 80030ce: 683b ldr r3, [r7, #0] 80030d0: 685b ldr r3, [r3, #4] 80030d2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80030d6: 2b00 cmp r3, #0 80030d8: d003 beq.n 80030e2 { temp |= iocurrent; 80030da: 693a ldr r2, [r7, #16] 80030dc: 68fb ldr r3, [r7, #12] 80030de: 4313 orrs r3, r2 80030e0: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 80030e2: 4a11 ldr r2, [pc, #68] @ (8003128 ) 80030e4: 693b ldr r3, [r7, #16] 80030e6: 6013 str r3, [r2, #0] } } position++; 80030e8: 697b ldr r3, [r7, #20] 80030ea: 3301 adds r3, #1 80030ec: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0U) 80030ee: 683b ldr r3, [r7, #0] 80030f0: 681a ldr r2, [r3, #0] 80030f2: 697b ldr r3, [r7, #20] 80030f4: fa22 f303 lsr.w r3, r2, r3 80030f8: 2b00 cmp r3, #0 80030fa: f47f ae9d bne.w 8002e38 } } 80030fe: bf00 nop 8003100: bf00 nop 8003102: 371c adds r7, #28 8003104: 46bd mov sp, r7 8003106: f85d 7b04 ldr.w r7, [sp], #4 800310a: 4770 bx lr 800310c: 40021000 .word 0x40021000 8003110: 40010000 .word 0x40010000 8003114: 48000400 .word 0x48000400 8003118: 48000800 .word 0x48000800 800311c: 48000c00 .word 0x48000c00 8003120: 48001000 .word 0x48001000 8003124: 48001400 .word 0x48001400 8003128: 40010400 .word 0x40010400 0800312c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800312c: b480 push {r7} 800312e: b083 sub sp, #12 8003130: af00 add r7, sp, #0 8003132: 6078 str r0, [r7, #4] 8003134: 460b mov r3, r1 8003136: 807b strh r3, [r7, #2] 8003138: 4613 mov r3, r2 800313a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800313c: 787b ldrb r3, [r7, #1] 800313e: 2b00 cmp r3, #0 8003140: d003 beq.n 800314a { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8003142: 887a ldrh r2, [r7, #2] 8003144: 687b ldr r3, [r7, #4] 8003146: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8003148: e002 b.n 8003150 GPIOx->BRR = (uint32_t)GPIO_Pin; 800314a: 887a ldrh r2, [r7, #2] 800314c: 687b ldr r3, [r7, #4] 800314e: 629a str r2, [r3, #40] @ 0x28 } 8003150: bf00 nop 8003152: 370c adds r7, #12 8003154: 46bd mov sp, r7 8003156: f85d 7b04 ldr.w r7, [sp], #4 800315a: 4770 bx lr 0800315c : * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 800315c: b480 push {r7} 800315e: b085 sub sp, #20 8003160: af00 add r7, sp, #0 8003162: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) 8003164: 687b ldr r3, [r7, #4] 8003166: 2b00 cmp r3, #0 8003168: d141 bne.n 80031ee { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 800316a: 4b4b ldr r3, [pc, #300] @ (8003298 ) 800316c: 681b ldr r3, [r3, #0] 800316e: f403 63c0 and.w r3, r3, #1536 @ 0x600 8003172: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003176: d131 bne.n 80031dc { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003178: 4b47 ldr r3, [pc, #284] @ (8003298 ) 800317a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800317e: 4a46 ldr r2, [pc, #280] @ (8003298 ) 8003180: f423 7380 bic.w r3, r3, #256 @ 0x100 8003184: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8003188: 4b43 ldr r3, [pc, #268] @ (8003298 ) 800318a: 681b ldr r3, [r3, #0] 800318c: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8003190: 4a41 ldr r2, [pc, #260] @ (8003298 ) 8003192: f443 7300 orr.w r3, r3, #512 @ 0x200 8003196: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003198: 4b40 ldr r3, [pc, #256] @ (800329c ) 800319a: 681b ldr r3, [r3, #0] 800319c: 2232 movs r2, #50 @ 0x32 800319e: fb02 f303 mul.w r3, r2, r3 80031a2: 4a3f ldr r2, [pc, #252] @ (80032a0 ) 80031a4: fba2 2303 umull r2, r3, r2, r3 80031a8: 0c9b lsrs r3, r3, #18 80031aa: 3301 adds r3, #1 80031ac: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80031ae: e002 b.n 80031b6 { wait_loop_index--; 80031b0: 68fb ldr r3, [r7, #12] 80031b2: 3b01 subs r3, #1 80031b4: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 80031b6: 4b38 ldr r3, [pc, #224] @ (8003298 ) 80031b8: 695b ldr r3, [r3, #20] 80031ba: f403 6380 and.w r3, r3, #1024 @ 0x400 80031be: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80031c2: d102 bne.n 80031ca 80031c4: 68fb ldr r3, [r7, #12] 80031c6: 2b00 cmp r3, #0 80031c8: d1f2 bne.n 80031b0 } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80031ca: 4b33 ldr r3, [pc, #204] @ (8003298 ) 80031cc: 695b ldr r3, [r3, #20] 80031ce: f403 6380 and.w r3, r3, #1024 @ 0x400 80031d2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80031d6: d158 bne.n 800328a { return HAL_TIMEOUT; 80031d8: 2303 movs r3, #3 80031da: e057 b.n 800328c } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 80031dc: 4b2e ldr r3, [pc, #184] @ (8003298 ) 80031de: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80031e2: 4a2d ldr r2, [pc, #180] @ (8003298 ) 80031e4: f423 7380 bic.w r3, r3, #256 @ 0x100 80031e8: f8c2 3080 str.w r3, [r2, #128] @ 0x80 80031ec: e04d b.n 800328a } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 80031ee: 687b ldr r3, [r7, #4] 80031f0: f5b3 7f00 cmp.w r3, #512 @ 0x200 80031f4: d141 bne.n 800327a { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 80031f6: 4b28 ldr r3, [pc, #160] @ (8003298 ) 80031f8: 681b ldr r3, [r3, #0] 80031fa: f403 63c0 and.w r3, r3, #1536 @ 0x600 80031fe: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003202: d131 bne.n 8003268 { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003204: 4b24 ldr r3, [pc, #144] @ (8003298 ) 8003206: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800320a: 4a23 ldr r2, [pc, #140] @ (8003298 ) 800320c: f443 7380 orr.w r3, r3, #256 @ 0x100 8003210: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8003214: 4b20 ldr r3, [pc, #128] @ (8003298 ) 8003216: 681b ldr r3, [r3, #0] 8003218: f423 63c0 bic.w r3, r3, #1536 @ 0x600 800321c: 4a1e ldr r2, [pc, #120] @ (8003298 ) 800321e: f443 7300 orr.w r3, r3, #512 @ 0x200 8003222: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; 8003224: 4b1d ldr r3, [pc, #116] @ (800329c ) 8003226: 681b ldr r3, [r3, #0] 8003228: 2232 movs r2, #50 @ 0x32 800322a: fb02 f303 mul.w r3, r2, r3 800322e: 4a1c ldr r2, [pc, #112] @ (80032a0 ) 8003230: fba2 2303 umull r2, r3, r2, r3 8003234: 0c9b lsrs r3, r3, #18 8003236: 3301 adds r3, #1 8003238: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 800323a: e002 b.n 8003242 { wait_loop_index--; 800323c: 68fb ldr r3, [r7, #12] 800323e: 3b01 subs r3, #1 8003240: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) 8003242: 4b15 ldr r3, [pc, #84] @ (8003298 ) 8003244: 695b ldr r3, [r3, #20] 8003246: f403 6380 and.w r3, r3, #1024 @ 0x400 800324a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800324e: d102 bne.n 8003256 8003250: 68fb ldr r3, [r7, #12] 8003252: 2b00 cmp r3, #0 8003254: d1f2 bne.n 800323c } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8003256: 4b10 ldr r3, [pc, #64] @ (8003298 ) 8003258: 695b ldr r3, [r3, #20] 800325a: f403 6380 and.w r3, r3, #1024 @ 0x400 800325e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8003262: d112 bne.n 800328a { return HAL_TIMEOUT; 8003264: 2303 movs r3, #3 8003266: e011 b.n 800328c } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 8003268: 4b0b ldr r3, [pc, #44] @ (8003298 ) 800326a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800326e: 4a0a ldr r2, [pc, #40] @ (8003298 ) 8003270: f443 7380 orr.w r3, r3, #256 @ 0x100 8003274: f8c2 3080 str.w r3, [r2, #128] @ 0x80 8003278: e007 b.n 800328a } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 800327a: 4b07 ldr r3, [pc, #28] @ (8003298 ) 800327c: 681b ldr r3, [r3, #0] 800327e: f423 63c0 bic.w r3, r3, #1536 @ 0x600 8003282: 4a05 ldr r2, [pc, #20] @ (8003298 ) 8003284: f443 6380 orr.w r3, r3, #1024 @ 0x400 8003288: 6013 str r3, [r2, #0] /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; 800328a: 2300 movs r3, #0 } 800328c: 4618 mov r0, r3 800328e: 3714 adds r7, #20 8003290: 46bd mov sp, r7 8003292: f85d 7b04 ldr.w r7, [sp], #4 8003296: 4770 bx lr 8003298: 40007000 .word 0x40007000 800329c: 20000000 .word 0x20000000 80032a0: 431bde83 .word 0x431bde83 080032a4 : * or to hand over control to the UCPD (which should therefore be * initialized before doing the disable). * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { 80032a4: b480 push {r7} 80032a6: af00 add r7, sp, #0 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); 80032a8: 4b05 ldr r3, [pc, #20] @ (80032c0 ) 80032aa: 689b ldr r3, [r3, #8] 80032ac: 4a04 ldr r2, [pc, #16] @ (80032c0 ) 80032ae: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80032b2: 6093 str r3, [r2, #8] } 80032b4: bf00 nop 80032b6: 46bd mov sp, r7 80032b8: f85d 7b04 ldr.w r7, [sp], #4 80032bc: 4770 bx lr 80032be: bf00 nop 80032c0: 40007000 .word 0x40007000 080032c4 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80032c4: b580 push {r7, lr} 80032c6: b088 sub sp, #32 80032c8: af00 add r7, sp, #0 80032ca: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 80032cc: 687b ldr r3, [r7, #4] 80032ce: 2b00 cmp r3, #0 80032d0: d101 bne.n 80032d6 { return HAL_ERROR; 80032d2: 2301 movs r3, #1 80032d4: e2fe b.n 80038d4 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80032d6: 687b ldr r3, [r7, #4] 80032d8: 681b ldr r3, [r3, #0] 80032da: f003 0301 and.w r3, r3, #1 80032de: 2b00 cmp r3, #0 80032e0: d075 beq.n 80033ce { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80032e2: 4b97 ldr r3, [pc, #604] @ (8003540 ) 80032e4: 689b ldr r3, [r3, #8] 80032e6: f003 030c and.w r3, r3, #12 80032ea: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 80032ec: 4b94 ldr r3, [pc, #592] @ (8003540 ) 80032ee: 68db ldr r3, [r3, #12] 80032f0: f003 0303 and.w r3, r3, #3 80032f4: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) 80032f6: 69bb ldr r3, [r7, #24] 80032f8: 2b0c cmp r3, #12 80032fa: d102 bne.n 8003302 80032fc: 697b ldr r3, [r7, #20] 80032fe: 2b03 cmp r3, #3 8003300: d002 beq.n 8003308 8003302: 69bb ldr r3, [r7, #24] 8003304: 2b08 cmp r3, #8 8003306: d10b bne.n 8003320 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003308: 4b8d ldr r3, [pc, #564] @ (8003540 ) 800330a: 681b ldr r3, [r3, #0] 800330c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8003310: 2b00 cmp r3, #0 8003312: d05b beq.n 80033cc 8003314: 687b ldr r3, [r7, #4] 8003316: 685b ldr r3, [r3, #4] 8003318: 2b00 cmp r3, #0 800331a: d157 bne.n 80033cc { return HAL_ERROR; 800331c: 2301 movs r3, #1 800331e: e2d9 b.n 80038d4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8003320: 687b ldr r3, [r7, #4] 8003322: 685b ldr r3, [r3, #4] 8003324: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8003328: d106 bne.n 8003338 800332a: 4b85 ldr r3, [pc, #532] @ (8003540 ) 800332c: 681b ldr r3, [r3, #0] 800332e: 4a84 ldr r2, [pc, #528] @ (8003540 ) 8003330: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003334: 6013 str r3, [r2, #0] 8003336: e01d b.n 8003374 8003338: 687b ldr r3, [r7, #4] 800333a: 685b ldr r3, [r3, #4] 800333c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8003340: d10c bne.n 800335c 8003342: 4b7f ldr r3, [pc, #508] @ (8003540 ) 8003344: 681b ldr r3, [r3, #0] 8003346: 4a7e ldr r2, [pc, #504] @ (8003540 ) 8003348: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800334c: 6013 str r3, [r2, #0] 800334e: 4b7c ldr r3, [pc, #496] @ (8003540 ) 8003350: 681b ldr r3, [r3, #0] 8003352: 4a7b ldr r2, [pc, #492] @ (8003540 ) 8003354: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003358: 6013 str r3, [r2, #0] 800335a: e00b b.n 8003374 800335c: 4b78 ldr r3, [pc, #480] @ (8003540 ) 800335e: 681b ldr r3, [r3, #0] 8003360: 4a77 ldr r2, [pc, #476] @ (8003540 ) 8003362: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8003366: 6013 str r3, [r2, #0] 8003368: 4b75 ldr r3, [pc, #468] @ (8003540 ) 800336a: 681b ldr r3, [r3, #0] 800336c: 4a74 ldr r2, [pc, #464] @ (8003540 ) 800336e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8003372: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003374: 687b ldr r3, [r7, #4] 8003376: 685b ldr r3, [r3, #4] 8003378: 2b00 cmp r3, #0 800337a: d013 beq.n 80033a4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800337c: f7fd ff48 bl 8001210 8003380: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003382: e008 b.n 8003396 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003384: f7fd ff44 bl 8001210 8003388: 4602 mov r2, r0 800338a: 693b ldr r3, [r7, #16] 800338c: 1ad3 subs r3, r2, r3 800338e: 2b64 cmp r3, #100 @ 0x64 8003390: d901 bls.n 8003396 { return HAL_TIMEOUT; 8003392: 2303 movs r3, #3 8003394: e29e b.n 80038d4 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003396: 4b6a ldr r3, [pc, #424] @ (8003540 ) 8003398: 681b ldr r3, [r3, #0] 800339a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800339e: 2b00 cmp r3, #0 80033a0: d0f0 beq.n 8003384 80033a2: e014 b.n 80033ce } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80033a4: f7fd ff34 bl 8001210 80033a8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80033aa: e008 b.n 80033be { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80033ac: f7fd ff30 bl 8001210 80033b0: 4602 mov r2, r0 80033b2: 693b ldr r3, [r7, #16] 80033b4: 1ad3 subs r3, r2, r3 80033b6: 2b64 cmp r3, #100 @ 0x64 80033b8: d901 bls.n 80033be { return HAL_TIMEOUT; 80033ba: 2303 movs r3, #3 80033bc: e28a b.n 80038d4 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80033be: 4b60 ldr r3, [pc, #384] @ (8003540 ) 80033c0: 681b ldr r3, [r3, #0] 80033c2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80033c6: 2b00 cmp r3, #0 80033c8: d1f0 bne.n 80033ac 80033ca: e000 b.n 80033ce if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80033cc: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80033ce: 687b ldr r3, [r7, #4] 80033d0: 681b ldr r3, [r3, #0] 80033d2: f003 0302 and.w r3, r3, #2 80033d6: 2b00 cmp r3, #0 80033d8: d075 beq.n 80034c6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80033da: 4b59 ldr r3, [pc, #356] @ (8003540 ) 80033dc: 689b ldr r3, [r3, #8] 80033de: f003 030c and.w r3, r3, #12 80033e2: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 80033e4: 4b56 ldr r3, [pc, #344] @ (8003540 ) 80033e6: 68db ldr r3, [r3, #12] 80033e8: f003 0303 and.w r3, r3, #3 80033ec: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) 80033ee: 69bb ldr r3, [r7, #24] 80033f0: 2b0c cmp r3, #12 80033f2: d102 bne.n 80033fa 80033f4: 697b ldr r3, [r7, #20] 80033f6: 2b02 cmp r3, #2 80033f8: d002 beq.n 8003400 80033fa: 69bb ldr r3, [r7, #24] 80033fc: 2b04 cmp r3, #4 80033fe: d11f bne.n 8003440 { /* When HSI is used as system clock it will not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003400: 4b4f ldr r3, [pc, #316] @ (8003540 ) 8003402: 681b ldr r3, [r3, #0] 8003404: f403 6380 and.w r3, r3, #1024 @ 0x400 8003408: 2b00 cmp r3, #0 800340a: d005 beq.n 8003418 800340c: 687b ldr r3, [r7, #4] 800340e: 68db ldr r3, [r3, #12] 8003410: 2b00 cmp r3, #0 8003412: d101 bne.n 8003418 { return HAL_ERROR; 8003414: 2301 movs r3, #1 8003416: e25d b.n 80038d4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003418: 4b49 ldr r3, [pc, #292] @ (8003540 ) 800341a: 685b ldr r3, [r3, #4] 800341c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8003420: 687b ldr r3, [r7, #4] 8003422: 691b ldr r3, [r3, #16] 8003424: 061b lsls r3, r3, #24 8003426: 4946 ldr r1, [pc, #280] @ (8003540 ) 8003428: 4313 orrs r3, r2 800342a: 604b str r3, [r1, #4] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 800342c: 4b45 ldr r3, [pc, #276] @ (8003544 ) 800342e: 681b ldr r3, [r3, #0] 8003430: 4618 mov r0, r3 8003432: f7fd fea1 bl 8001178 8003436: 4603 mov r3, r0 8003438: 2b00 cmp r3, #0 800343a: d043 beq.n 80034c4 { return HAL_ERROR; 800343c: 2301 movs r3, #1 800343e: e249 b.n 80038d4 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8003440: 687b ldr r3, [r7, #4] 8003442: 68db ldr r3, [r3, #12] 8003444: 2b00 cmp r3, #0 8003446: d023 beq.n 8003490 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8003448: 4b3d ldr r3, [pc, #244] @ (8003540 ) 800344a: 681b ldr r3, [r3, #0] 800344c: 4a3c ldr r2, [pc, #240] @ (8003540 ) 800344e: f443 7380 orr.w r3, r3, #256 @ 0x100 8003452: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003454: f7fd fedc bl 8001210 8003458: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 800345a: e008 b.n 800346e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800345c: f7fd fed8 bl 8001210 8003460: 4602 mov r2, r0 8003462: 693b ldr r3, [r7, #16] 8003464: 1ad3 subs r3, r2, r3 8003466: 2b02 cmp r3, #2 8003468: d901 bls.n 800346e { return HAL_TIMEOUT; 800346a: 2303 movs r3, #3 800346c: e232 b.n 80038d4 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 800346e: 4b34 ldr r3, [pc, #208] @ (8003540 ) 8003470: 681b ldr r3, [r3, #0] 8003472: f403 6380 and.w r3, r3, #1024 @ 0x400 8003476: 2b00 cmp r3, #0 8003478: d0f0 beq.n 800345c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800347a: 4b31 ldr r3, [pc, #196] @ (8003540 ) 800347c: 685b ldr r3, [r3, #4] 800347e: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8003482: 687b ldr r3, [r7, #4] 8003484: 691b ldr r3, [r3, #16] 8003486: 061b lsls r3, r3, #24 8003488: 492d ldr r1, [pc, #180] @ (8003540 ) 800348a: 4313 orrs r3, r2 800348c: 604b str r3, [r1, #4] 800348e: e01a b.n 80034c6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003490: 4b2b ldr r3, [pc, #172] @ (8003540 ) 8003492: 681b ldr r3, [r3, #0] 8003494: 4a2a ldr r2, [pc, #168] @ (8003540 ) 8003496: f423 7380 bic.w r3, r3, #256 @ 0x100 800349a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800349c: f7fd feb8 bl 8001210 80034a0: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80034a2: e008 b.n 80034b6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80034a4: f7fd feb4 bl 8001210 80034a8: 4602 mov r2, r0 80034aa: 693b ldr r3, [r7, #16] 80034ac: 1ad3 subs r3, r2, r3 80034ae: 2b02 cmp r3, #2 80034b0: d901 bls.n 80034b6 { return HAL_TIMEOUT; 80034b2: 2303 movs r3, #3 80034b4: e20e b.n 80038d4 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80034b6: 4b22 ldr r3, [pc, #136] @ (8003540 ) 80034b8: 681b ldr r3, [r3, #0] 80034ba: f403 6380 and.w r3, r3, #1024 @ 0x400 80034be: 2b00 cmp r3, #0 80034c0: d1f0 bne.n 80034a4 80034c2: e000 b.n 80034c6 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80034c4: bf00 nop } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80034c6: 687b ldr r3, [r7, #4] 80034c8: 681b ldr r3, [r3, #0] 80034ca: f003 0308 and.w r3, r3, #8 80034ce: 2b00 cmp r3, #0 80034d0: d041 beq.n 8003556 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 80034d2: 687b ldr r3, [r7, #4] 80034d4: 695b ldr r3, [r3, #20] 80034d6: 2b00 cmp r3, #0 80034d8: d01c beq.n 8003514 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80034da: 4b19 ldr r3, [pc, #100] @ (8003540 ) 80034dc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80034e0: 4a17 ldr r2, [pc, #92] @ (8003540 ) 80034e2: f043 0301 orr.w r3, r3, #1 80034e6: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80034ea: f7fd fe91 bl 8001210 80034ee: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 80034f0: e008 b.n 8003504 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80034f2: f7fd fe8d bl 8001210 80034f6: 4602 mov r2, r0 80034f8: 693b ldr r3, [r7, #16] 80034fa: 1ad3 subs r3, r2, r3 80034fc: 2b02 cmp r3, #2 80034fe: d901 bls.n 8003504 { return HAL_TIMEOUT; 8003500: 2303 movs r3, #3 8003502: e1e7 b.n 80038d4 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003504: 4b0e ldr r3, [pc, #56] @ (8003540 ) 8003506: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800350a: f003 0302 and.w r3, r3, #2 800350e: 2b00 cmp r3, #0 8003510: d0ef beq.n 80034f2 8003512: e020 b.n 8003556 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003514: 4b0a ldr r3, [pc, #40] @ (8003540 ) 8003516: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800351a: 4a09 ldr r2, [pc, #36] @ (8003540 ) 800351c: f023 0301 bic.w r3, r3, #1 8003520: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003524: f7fd fe74 bl 8001210 8003528: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 800352a: e00d b.n 8003548 { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800352c: f7fd fe70 bl 8001210 8003530: 4602 mov r2, r0 8003532: 693b ldr r3, [r7, #16] 8003534: 1ad3 subs r3, r2, r3 8003536: 2b02 cmp r3, #2 8003538: d906 bls.n 8003548 { return HAL_TIMEOUT; 800353a: 2303 movs r3, #3 800353c: e1ca b.n 80038d4 800353e: bf00 nop 8003540: 40021000 .word 0x40021000 8003544: 20000004 .word 0x20000004 while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8003548: 4b8c ldr r3, [pc, #560] @ (800377c ) 800354a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800354e: f003 0302 and.w r3, r3, #2 8003552: 2b00 cmp r3, #0 8003554: d1ea bne.n 800352c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003556: 687b ldr r3, [r7, #4] 8003558: 681b ldr r3, [r3, #0] 800355a: f003 0304 and.w r3, r3, #4 800355e: 2b00 cmp r3, #0 8003560: f000 80a6 beq.w 80036b0 { FlagStatus pwrclkchanged = RESET; 8003564: 2300 movs r3, #0 8003566: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8003568: 4b84 ldr r3, [pc, #528] @ (800377c ) 800356a: 6d9b ldr r3, [r3, #88] @ 0x58 800356c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003570: 2b00 cmp r3, #0 8003572: d101 bne.n 8003578 8003574: 2301 movs r3, #1 8003576: e000 b.n 800357a 8003578: 2300 movs r3, #0 800357a: 2b00 cmp r3, #0 800357c: d00d beq.n 800359a { __HAL_RCC_PWR_CLK_ENABLE(); 800357e: 4b7f ldr r3, [pc, #508] @ (800377c ) 8003580: 6d9b ldr r3, [r3, #88] @ 0x58 8003582: 4a7e ldr r2, [pc, #504] @ (800377c ) 8003584: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003588: 6593 str r3, [r2, #88] @ 0x58 800358a: 4b7c ldr r3, [pc, #496] @ (800377c ) 800358c: 6d9b ldr r3, [r3, #88] @ 0x58 800358e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003592: 60fb str r3, [r7, #12] 8003594: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8003596: 2301 movs r3, #1 8003598: 77fb strb r3, [r7, #31] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800359a: 4b79 ldr r3, [pc, #484] @ (8003780 ) 800359c: 681b ldr r3, [r3, #0] 800359e: f403 7380 and.w r3, r3, #256 @ 0x100 80035a2: 2b00 cmp r3, #0 80035a4: d118 bne.n 80035d8 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 80035a6: 4b76 ldr r3, [pc, #472] @ (8003780 ) 80035a8: 681b ldr r3, [r3, #0] 80035aa: 4a75 ldr r2, [pc, #468] @ (8003780 ) 80035ac: f443 7380 orr.w r3, r3, #256 @ 0x100 80035b0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80035b2: f7fd fe2d bl 8001210 80035b6: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80035b8: e008 b.n 80035cc { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80035ba: f7fd fe29 bl 8001210 80035be: 4602 mov r2, r0 80035c0: 693b ldr r3, [r7, #16] 80035c2: 1ad3 subs r3, r2, r3 80035c4: 2b02 cmp r3, #2 80035c6: d901 bls.n 80035cc { return HAL_TIMEOUT; 80035c8: 2303 movs r3, #3 80035ca: e183 b.n 80038d4 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 80035cc: 4b6c ldr r3, [pc, #432] @ (8003780 ) 80035ce: 681b ldr r3, [r3, #0] 80035d0: f403 7380 and.w r3, r3, #256 @ 0x100 80035d4: 2b00 cmp r3, #0 80035d6: d0f0 beq.n 80035ba } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 80035d8: 687b ldr r3, [r7, #4] 80035da: 689b ldr r3, [r3, #8] 80035dc: 2b01 cmp r3, #1 80035de: d108 bne.n 80035f2 80035e0: 4b66 ldr r3, [pc, #408] @ (800377c ) 80035e2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80035e6: 4a65 ldr r2, [pc, #404] @ (800377c ) 80035e8: f043 0301 orr.w r3, r3, #1 80035ec: f8c2 3090 str.w r3, [r2, #144] @ 0x90 80035f0: e024 b.n 800363c 80035f2: 687b ldr r3, [r7, #4] 80035f4: 689b ldr r3, [r3, #8] 80035f6: 2b05 cmp r3, #5 80035f8: d110 bne.n 800361c 80035fa: 4b60 ldr r3, [pc, #384] @ (800377c ) 80035fc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003600: 4a5e ldr r2, [pc, #376] @ (800377c ) 8003602: f043 0304 orr.w r3, r3, #4 8003606: f8c2 3090 str.w r3, [r2, #144] @ 0x90 800360a: 4b5c ldr r3, [pc, #368] @ (800377c ) 800360c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003610: 4a5a ldr r2, [pc, #360] @ (800377c ) 8003612: f043 0301 orr.w r3, r3, #1 8003616: f8c2 3090 str.w r3, [r2, #144] @ 0x90 800361a: e00f b.n 800363c 800361c: 4b57 ldr r3, [pc, #348] @ (800377c ) 800361e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003622: 4a56 ldr r2, [pc, #344] @ (800377c ) 8003624: f023 0301 bic.w r3, r3, #1 8003628: f8c2 3090 str.w r3, [r2, #144] @ 0x90 800362c: 4b53 ldr r3, [pc, #332] @ (800377c ) 800362e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003632: 4a52 ldr r2, [pc, #328] @ (800377c ) 8003634: f023 0304 bic.w r3, r3, #4 8003638: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 800363c: 687b ldr r3, [r7, #4] 800363e: 689b ldr r3, [r3, #8] 8003640: 2b00 cmp r3, #0 8003642: d016 beq.n 8003672 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003644: f7fd fde4 bl 8001210 8003648: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800364a: e00a b.n 8003662 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800364c: f7fd fde0 bl 8001210 8003650: 4602 mov r2, r0 8003652: 693b ldr r3, [r7, #16] 8003654: 1ad3 subs r3, r2, r3 8003656: f241 3288 movw r2, #5000 @ 0x1388 800365a: 4293 cmp r3, r2 800365c: d901 bls.n 8003662 { return HAL_TIMEOUT; 800365e: 2303 movs r3, #3 8003660: e138 b.n 80038d4 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003662: 4b46 ldr r3, [pc, #280] @ (800377c ) 8003664: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003668: f003 0302 and.w r3, r3, #2 800366c: 2b00 cmp r3, #0 800366e: d0ed beq.n 800364c 8003670: e015 b.n 800369e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003672: f7fd fdcd bl 8001210 8003676: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003678: e00a b.n 8003690 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800367a: f7fd fdc9 bl 8001210 800367e: 4602 mov r2, r0 8003680: 693b ldr r3, [r7, #16] 8003682: 1ad3 subs r3, r2, r3 8003684: f241 3288 movw r2, #5000 @ 0x1388 8003688: 4293 cmp r3, r2 800368a: d901 bls.n 8003690 { return HAL_TIMEOUT; 800368c: 2303 movs r3, #3 800368e: e121 b.n 80038d4 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 8003690: 4b3a ldr r3, [pc, #232] @ (800377c ) 8003692: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003696: f003 0302 and.w r3, r3, #2 800369a: 2b00 cmp r3, #0 800369c: d1ed bne.n 800367a } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800369e: 7ffb ldrb r3, [r7, #31] 80036a0: 2b01 cmp r3, #1 80036a2: d105 bne.n 80036b0 { __HAL_RCC_PWR_CLK_DISABLE(); 80036a4: 4b35 ldr r3, [pc, #212] @ (800377c ) 80036a6: 6d9b ldr r3, [r3, #88] @ 0x58 80036a8: 4a34 ldr r2, [pc, #208] @ (800377c ) 80036aa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80036ae: 6593 str r3, [r2, #88] @ 0x58 } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80036b0: 687b ldr r3, [r7, #4] 80036b2: 681b ldr r3, [r3, #0] 80036b4: f003 0320 and.w r3, r3, #32 80036b8: 2b00 cmp r3, #0 80036ba: d03c beq.n 8003736 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 80036bc: 687b ldr r3, [r7, #4] 80036be: 699b ldr r3, [r3, #24] 80036c0: 2b00 cmp r3, #0 80036c2: d01c beq.n 80036fe { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 80036c4: 4b2d ldr r3, [pc, #180] @ (800377c ) 80036c6: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 80036ca: 4a2c ldr r2, [pc, #176] @ (800377c ) 80036cc: f043 0301 orr.w r3, r3, #1 80036d0: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80036d4: f7fd fd9c bl 8001210 80036d8: 6138 str r0, [r7, #16] /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 80036da: e008 b.n 80036ee { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 80036dc: f7fd fd98 bl 8001210 80036e0: 4602 mov r2, r0 80036e2: 693b ldr r3, [r7, #16] 80036e4: 1ad3 subs r3, r2, r3 80036e6: 2b02 cmp r3, #2 80036e8: d901 bls.n 80036ee { return HAL_TIMEOUT; 80036ea: 2303 movs r3, #3 80036ec: e0f2 b.n 80038d4 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) 80036ee: 4b23 ldr r3, [pc, #140] @ (800377c ) 80036f0: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 80036f4: f003 0302 and.w r3, r3, #2 80036f8: 2b00 cmp r3, #0 80036fa: d0ef beq.n 80036dc 80036fc: e01b b.n 8003736 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 80036fe: 4b1f ldr r3, [pc, #124] @ (800377c ) 8003700: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8003704: 4a1d ldr r2, [pc, #116] @ (800377c ) 8003706: f023 0301 bic.w r3, r3, #1 800370a: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800370e: f7fd fd7f bl 8001210 8003712: 6138 str r0, [r7, #16] /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8003714: e008 b.n 8003728 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8003716: f7fd fd7b bl 8001210 800371a: 4602 mov r2, r0 800371c: 693b ldr r3, [r7, #16] 800371e: 1ad3 subs r3, r2, r3 8003720: 2b02 cmp r3, #2 8003722: d901 bls.n 8003728 { return HAL_TIMEOUT; 8003724: 2303 movs r3, #3 8003726: e0d5 b.n 80038d4 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) 8003728: 4b14 ldr r3, [pc, #80] @ (800377c ) 800372a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800372e: f003 0302 and.w r3, r3, #2 8003732: 2b00 cmp r3, #0 8003734: d1ef bne.n 8003716 /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8003736: 687b ldr r3, [r7, #4] 8003738: 69db ldr r3, [r3, #28] 800373a: 2b00 cmp r3, #0 800373c: f000 80c9 beq.w 80038d2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8003740: 4b0e ldr r3, [pc, #56] @ (800377c ) 8003742: 689b ldr r3, [r3, #8] 8003744: f003 030c and.w r3, r3, #12 8003748: 2b0c cmp r3, #12 800374a: f000 8083 beq.w 8003854 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 800374e: 687b ldr r3, [r7, #4] 8003750: 69db ldr r3, [r3, #28] 8003752: 2b02 cmp r3, #2 8003754: d15e bne.n 8003814 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003756: 4b09 ldr r3, [pc, #36] @ (800377c ) 8003758: 681b ldr r3, [r3, #0] 800375a: 4a08 ldr r2, [pc, #32] @ (800377c ) 800375c: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8003760: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003762: f7fd fd55 bl 8001210 8003766: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003768: e00c b.n 8003784 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800376a: f7fd fd51 bl 8001210 800376e: 4602 mov r2, r0 8003770: 693b ldr r3, [r7, #16] 8003772: 1ad3 subs r3, r2, r3 8003774: 2b02 cmp r3, #2 8003776: d905 bls.n 8003784 { return HAL_TIMEOUT; 8003778: 2303 movs r3, #3 800377a: e0ab b.n 80038d4 800377c: 40021000 .word 0x40021000 8003780: 40007000 .word 0x40007000 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003784: 4b55 ldr r3, [pc, #340] @ (80038dc ) 8003786: 681b ldr r3, [r3, #0] 8003788: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800378c: 2b00 cmp r3, #0 800378e: d1ec bne.n 800376a } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003790: 4b52 ldr r3, [pc, #328] @ (80038dc ) 8003792: 68da ldr r2, [r3, #12] 8003794: 4b52 ldr r3, [pc, #328] @ (80038e0 ) 8003796: 4013 ands r3, r2 8003798: 687a ldr r2, [r7, #4] 800379a: 6a11 ldr r1, [r2, #32] 800379c: 687a ldr r2, [r7, #4] 800379e: 6a52 ldr r2, [r2, #36] @ 0x24 80037a0: 3a01 subs r2, #1 80037a2: 0112 lsls r2, r2, #4 80037a4: 4311 orrs r1, r2 80037a6: 687a ldr r2, [r7, #4] 80037a8: 6a92 ldr r2, [r2, #40] @ 0x28 80037aa: 0212 lsls r2, r2, #8 80037ac: 4311 orrs r1, r2 80037ae: 687a ldr r2, [r7, #4] 80037b0: 6b12 ldr r2, [r2, #48] @ 0x30 80037b2: 0852 lsrs r2, r2, #1 80037b4: 3a01 subs r2, #1 80037b6: 0552 lsls r2, r2, #21 80037b8: 4311 orrs r1, r2 80037ba: 687a ldr r2, [r7, #4] 80037bc: 6b52 ldr r2, [r2, #52] @ 0x34 80037be: 0852 lsrs r2, r2, #1 80037c0: 3a01 subs r2, #1 80037c2: 0652 lsls r2, r2, #25 80037c4: 4311 orrs r1, r2 80037c6: 687a ldr r2, [r7, #4] 80037c8: 6ad2 ldr r2, [r2, #44] @ 0x2c 80037ca: 06d2 lsls r2, r2, #27 80037cc: 430a orrs r2, r1 80037ce: 4943 ldr r1, [pc, #268] @ (80038dc ) 80037d0: 4313 orrs r3, r2 80037d2: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80037d4: 4b41 ldr r3, [pc, #260] @ (80038dc ) 80037d6: 681b ldr r3, [r3, #0] 80037d8: 4a40 ldr r2, [pc, #256] @ (80038dc ) 80037da: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 80037de: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 80037e0: 4b3e ldr r3, [pc, #248] @ (80038dc ) 80037e2: 68db ldr r3, [r3, #12] 80037e4: 4a3d ldr r2, [pc, #244] @ (80038dc ) 80037e6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 80037ea: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80037ec: f7fd fd10 bl 8001210 80037f0: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 80037f2: e008 b.n 8003806 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80037f4: f7fd fd0c bl 8001210 80037f8: 4602 mov r2, r0 80037fa: 693b ldr r3, [r7, #16] 80037fc: 1ad3 subs r3, r2, r3 80037fe: 2b02 cmp r3, #2 8003800: d901 bls.n 8003806 { return HAL_TIMEOUT; 8003802: 2303 movs r3, #3 8003804: e066 b.n 80038d4 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003806: 4b35 ldr r3, [pc, #212] @ (80038dc ) 8003808: 681b ldr r3, [r3, #0] 800380a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800380e: 2b00 cmp r3, #0 8003810: d0f0 beq.n 80037f4 8003812: e05e b.n 80038d2 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003814: 4b31 ldr r3, [pc, #196] @ (80038dc ) 8003816: 681b ldr r3, [r3, #0] 8003818: 4a30 ldr r2, [pc, #192] @ (80038dc ) 800381a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800381e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003820: f7fd fcf6 bl 8001210 8003824: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003826: e008 b.n 800383a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003828: f7fd fcf2 bl 8001210 800382c: 4602 mov r2, r0 800382e: 693b ldr r3, [r7, #16] 8003830: 1ad3 subs r3, r2, r3 8003832: 2b02 cmp r3, #2 8003834: d901 bls.n 800383a { return HAL_TIMEOUT; 8003836: 2303 movs r3, #3 8003838: e04c b.n 80038d4 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800383a: 4b28 ldr r3, [pc, #160] @ (80038dc ) 800383c: 681b ldr r3, [r3, #0] 800383e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8003842: 2b00 cmp r3, #0 8003844: d1f0 bne.n 8003828 } } /* Unselect PLL clock source and disable outputs to save power */ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); 8003846: 4b25 ldr r3, [pc, #148] @ (80038dc ) 8003848: 68da ldr r2, [r3, #12] 800384a: 4924 ldr r1, [pc, #144] @ (80038dc ) 800384c: 4b25 ldr r3, [pc, #148] @ (80038e4 ) 800384e: 4013 ands r3, r2 8003850: 60cb str r3, [r1, #12] 8003852: e03e b.n 80038d2 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003854: 687b ldr r3, [r7, #4] 8003856: 69db ldr r3, [r3, #28] 8003858: 2b01 cmp r3, #1 800385a: d101 bne.n 8003860 { return HAL_ERROR; 800385c: 2301 movs r3, #1 800385e: e039 b.n 80038d4 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 8003860: 4b1e ldr r3, [pc, #120] @ (80038dc ) 8003862: 68db ldr r3, [r3, #12] 8003864: 617b str r3, [r7, #20] if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003866: 697b ldr r3, [r7, #20] 8003868: f003 0203 and.w r2, r3, #3 800386c: 687b ldr r3, [r7, #4] 800386e: 6a1b ldr r3, [r3, #32] 8003870: 429a cmp r2, r3 8003872: d12c bne.n 80038ce (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8003874: 697b ldr r3, [r7, #20] 8003876: f003 02f0 and.w r2, r3, #240 @ 0xf0 800387a: 687b ldr r3, [r7, #4] 800387c: 6a5b ldr r3, [r3, #36] @ 0x24 800387e: 3b01 subs r3, #1 8003880: 011b lsls r3, r3, #4 if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003882: 429a cmp r2, r3 8003884: d123 bne.n 80038ce (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 8003886: 697b ldr r3, [r7, #20] 8003888: f403 42fe and.w r2, r3, #32512 @ 0x7f00 800388c: 687b ldr r3, [r7, #4] 800388e: 6a9b ldr r3, [r3, #40] @ 0x28 8003890: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || 8003892: 429a cmp r2, r3 8003894: d11b bne.n 80038ce (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 8003896: 697b ldr r3, [r7, #20] 8003898: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000 800389c: 687b ldr r3, [r7, #4] 800389e: 6adb ldr r3, [r3, #44] @ 0x2c 80038a0: 06db lsls r3, r3, #27 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || 80038a2: 429a cmp r2, r3 80038a4: d113 bne.n 80038ce (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 80038a6: 697b ldr r3, [r7, #20] 80038a8: f403 02c0 and.w r2, r3, #6291456 @ 0x600000 80038ac: 687b ldr r3, [r7, #4] 80038ae: 6b1b ldr r3, [r3, #48] @ 0x30 80038b0: 085b lsrs r3, r3, #1 80038b2: 3b01 subs r3, #1 80038b4: 055b lsls r3, r3, #21 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || 80038b6: 429a cmp r2, r3 80038b8: d109 bne.n 80038ce (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) 80038ba: 697b ldr r3, [r7, #20] 80038bc: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000 80038c0: 687b ldr r3, [r7, #4] 80038c2: 6b5b ldr r3, [r3, #52] @ 0x34 80038c4: 085b lsrs r3, r3, #1 80038c6: 3b01 subs r3, #1 80038c8: 065b lsls r3, r3, #25 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || 80038ca: 429a cmp r2, r3 80038cc: d001 beq.n 80038d2 { return HAL_ERROR; 80038ce: 2301 movs r3, #1 80038d0: e000 b.n 80038d4 } } } } return HAL_OK; 80038d2: 2300 movs r3, #0 } 80038d4: 4618 mov r0, r3 80038d6: 3720 adds r7, #32 80038d8: 46bd mov sp, r7 80038da: bd80 pop {r7, pc} 80038dc: 40021000 .word 0x40021000 80038e0: 019f800c .word 0x019f800c 80038e4: feeefffc .word 0xfeeefffc 080038e8 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 80038e8: b580 push {r7, lr} 80038ea: b086 sub sp, #24 80038ec: af00 add r7, sp, #0 80038ee: 6078 str r0, [r7, #4] 80038f0: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t pllfreq; uint32_t hpre = RCC_SYSCLK_DIV1; 80038f2: 2300 movs r3, #0 80038f4: 617b str r3, [r7, #20] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 80038f6: 687b ldr r3, [r7, #4] 80038f8: 2b00 cmp r3, #0 80038fa: d101 bne.n 8003900 { return HAL_ERROR; 80038fc: 2301 movs r3, #1 80038fe: e11e b.n 8003b3e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003900: 4b91 ldr r3, [pc, #580] @ (8003b48 ) 8003902: 681b ldr r3, [r3, #0] 8003904: f003 030f and.w r3, r3, #15 8003908: 683a ldr r2, [r7, #0] 800390a: 429a cmp r2, r3 800390c: d910 bls.n 8003930 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800390e: 4b8e ldr r3, [pc, #568] @ (8003b48 ) 8003910: 681b ldr r3, [r3, #0] 8003912: f023 020f bic.w r2, r3, #15 8003916: 498c ldr r1, [pc, #560] @ (8003b48 ) 8003918: 683b ldr r3, [r7, #0] 800391a: 4313 orrs r3, r2 800391c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800391e: 4b8a ldr r3, [pc, #552] @ (8003b48 ) 8003920: 681b ldr r3, [r3, #0] 8003922: f003 030f and.w r3, r3, #15 8003926: 683a ldr r2, [r7, #0] 8003928: 429a cmp r2, r3 800392a: d001 beq.n 8003930 { return HAL_ERROR; 800392c: 2301 movs r3, #1 800392e: e106 b.n 8003b3e } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003930: 687b ldr r3, [r7, #4] 8003932: 681b ldr r3, [r3, #0] 8003934: f003 0301 and.w r3, r3, #1 8003938: 2b00 cmp r3, #0 800393a: d073 beq.n 8003a24 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800393c: 687b ldr r3, [r7, #4] 800393e: 685b ldr r3, [r3, #4] 8003940: 2b03 cmp r3, #3 8003942: d129 bne.n 8003998 { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003944: 4b81 ldr r3, [pc, #516] @ (8003b4c ) 8003946: 681b ldr r3, [r3, #0] 8003948: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800394c: 2b00 cmp r3, #0 800394e: d101 bne.n 8003954 { return HAL_ERROR; 8003950: 2301 movs r3, #1 8003952: e0f4 b.n 8003b3e } /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); 8003954: f000 f99e bl 8003c94 8003958: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ if(pllfreq > 80000000U) 800395a: 693b ldr r3, [r7, #16] 800395c: 4a7c ldr r2, [pc, #496] @ (8003b50 ) 800395e: 4293 cmp r3, r2 8003960: d93f bls.n 80039e2 { if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 8003962: 4b7a ldr r3, [pc, #488] @ (8003b4c ) 8003964: 689b ldr r3, [r3, #8] 8003966: f003 03f0 and.w r3, r3, #240 @ 0xf0 800396a: 2b00 cmp r3, #0 800396c: d009 beq.n 8003982 (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 800396e: 687b ldr r3, [r7, #4] 8003970: 681b ldr r3, [r3, #0] 8003972: f003 0302 and.w r3, r3, #2 if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || 8003976: 2b00 cmp r3, #0 8003978: d033 beq.n 80039e2 (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) 800397a: 687b ldr r3, [r7, #4] 800397c: 689b ldr r3, [r3, #8] (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && 800397e: 2b00 cmp r3, #0 8003980: d12f bne.n 80039e2 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 8003982: 4b72 ldr r3, [pc, #456] @ (8003b4c ) 8003984: 689b ldr r3, [r3, #8] 8003986: f023 03f0 bic.w r3, r3, #240 @ 0xf0 800398a: 4a70 ldr r2, [pc, #448] @ (8003b4c ) 800398c: f043 0380 orr.w r3, r3, #128 @ 0x80 8003990: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 8003992: 2380 movs r3, #128 @ 0x80 8003994: 617b str r3, [r7, #20] 8003996: e024 b.n 80039e2 } } else { /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003998: 687b ldr r3, [r7, #4] 800399a: 685b ldr r3, [r3, #4] 800399c: 2b02 cmp r3, #2 800399e: d107 bne.n 80039b0 { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 80039a0: 4b6a ldr r3, [pc, #424] @ (8003b4c ) 80039a2: 681b ldr r3, [r3, #0] 80039a4: f403 3300 and.w r3, r3, #131072 @ 0x20000 80039a8: 2b00 cmp r3, #0 80039aa: d109 bne.n 80039c0 { return HAL_ERROR; 80039ac: 2301 movs r3, #1 80039ae: e0c6 b.n 8003b3e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 80039b0: 4b66 ldr r3, [pc, #408] @ (8003b4c ) 80039b2: 681b ldr r3, [r3, #0] 80039b4: f403 6380 and.w r3, r3, #1024 @ 0x400 80039b8: 2b00 cmp r3, #0 80039ba: d101 bne.n 80039c0 { return HAL_ERROR; 80039bc: 2301 movs r3, #1 80039be: e0be b.n 8003b3e } } /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); 80039c0: f000 f8ce bl 8003b60 80039c4: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) 80039c6: 693b ldr r3, [r7, #16] 80039c8: 4a61 ldr r2, [pc, #388] @ (8003b50 ) 80039ca: 4293 cmp r3, r2 80039cc: d909 bls.n 80039e2 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); 80039ce: 4b5f ldr r3, [pc, #380] @ (8003b4c ) 80039d0: 689b ldr r3, [r3, #8] 80039d2: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80039d6: 4a5d ldr r2, [pc, #372] @ (8003b4c ) 80039d8: f043 0380 orr.w r3, r3, #128 @ 0x80 80039dc: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; 80039de: 2380 movs r3, #128 @ 0x80 80039e0: 617b str r3, [r7, #20] } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 80039e2: 4b5a ldr r3, [pc, #360] @ (8003b4c ) 80039e4: 689b ldr r3, [r3, #8] 80039e6: f023 0203 bic.w r2, r3, #3 80039ea: 687b ldr r3, [r7, #4] 80039ec: 685b ldr r3, [r3, #4] 80039ee: 4957 ldr r1, [pc, #348] @ (8003b4c ) 80039f0: 4313 orrs r3, r2 80039f2: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039f4: f7fd fc0c bl 8001210 80039f8: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80039fa: e00a b.n 8003a12 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80039fc: f7fd fc08 bl 8001210 8003a00: 4602 mov r2, r0 8003a02: 68fb ldr r3, [r7, #12] 8003a04: 1ad3 subs r3, r2, r3 8003a06: f241 3288 movw r2, #5000 @ 0x1388 8003a0a: 4293 cmp r3, r2 8003a0c: d901 bls.n 8003a12 { return HAL_TIMEOUT; 8003a0e: 2303 movs r3, #3 8003a10: e095 b.n 8003b3e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003a12: 4b4e ldr r3, [pc, #312] @ (8003b4c ) 8003a14: 689b ldr r3, [r3, #8] 8003a16: f003 020c and.w r2, r3, #12 8003a1a: 687b ldr r3, [r7, #4] 8003a1c: 685b ldr r3, [r3, #4] 8003a1e: 009b lsls r3, r3, #2 8003a20: 429a cmp r2, r3 8003a22: d1eb bne.n 80039fc } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003a24: 687b ldr r3, [r7, #4] 8003a26: 681b ldr r3, [r3, #0] 8003a28: f003 0302 and.w r3, r3, #2 8003a2c: 2b00 cmp r3, #0 8003a2e: d023 beq.n 8003a78 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003a30: 687b ldr r3, [r7, #4] 8003a32: 681b ldr r3, [r3, #0] 8003a34: f003 0304 and.w r3, r3, #4 8003a38: 2b00 cmp r3, #0 8003a3a: d005 beq.n 8003a48 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8003a3c: 4b43 ldr r3, [pc, #268] @ (8003b4c ) 8003a3e: 689b ldr r3, [r3, #8] 8003a40: 4a42 ldr r2, [pc, #264] @ (8003b4c ) 8003a42: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8003a46: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003a48: 687b ldr r3, [r7, #4] 8003a4a: 681b ldr r3, [r3, #0] 8003a4c: f003 0308 and.w r3, r3, #8 8003a50: 2b00 cmp r3, #0 8003a52: d007 beq.n 8003a64 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); 8003a54: 4b3d ldr r3, [pc, #244] @ (8003b4c ) 8003a56: 689b ldr r3, [r3, #8] 8003a58: f423 537c bic.w r3, r3, #16128 @ 0x3f00 8003a5c: 4a3b ldr r2, [pc, #236] @ (8003b4c ) 8003a5e: f443 63e0 orr.w r3, r3, #1792 @ 0x700 8003a62: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003a64: 4b39 ldr r3, [pc, #228] @ (8003b4c ) 8003a66: 689b ldr r3, [r3, #8] 8003a68: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8003a6c: 687b ldr r3, [r7, #4] 8003a6e: 689b ldr r3, [r3, #8] 8003a70: 4936 ldr r1, [pc, #216] @ (8003b4c ) 8003a72: 4313 orrs r3, r2 8003a74: 608b str r3, [r1, #8] 8003a76: e008 b.n 8003a8a } else { /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ if(hpre == RCC_SYSCLK_DIV2) 8003a78: 697b ldr r3, [r7, #20] 8003a7a: 2b80 cmp r3, #128 @ 0x80 8003a7c: d105 bne.n 8003a8a { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); 8003a7e: 4b33 ldr r3, [pc, #204] @ (8003b4c ) 8003a80: 689b ldr r3, [r3, #8] 8003a82: 4a32 ldr r2, [pc, #200] @ (8003b4c ) 8003a84: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8003a88: 6093 str r3, [r2, #8] } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003a8a: 4b2f ldr r3, [pc, #188] @ (8003b48 ) 8003a8c: 681b ldr r3, [r3, #0] 8003a8e: f003 030f and.w r3, r3, #15 8003a92: 683a ldr r2, [r7, #0] 8003a94: 429a cmp r2, r3 8003a96: d21d bcs.n 8003ad4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003a98: 4b2b ldr r3, [pc, #172] @ (8003b48 ) 8003a9a: 681b ldr r3, [r3, #0] 8003a9c: f023 020f bic.w r2, r3, #15 8003aa0: 4929 ldr r1, [pc, #164] @ (8003b48 ) 8003aa2: 683b ldr r3, [r7, #0] 8003aa4: 4313 orrs r3, r2 8003aa6: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8003aa8: f7fd fbb2 bl 8001210 8003aac: 60f8 str r0, [r7, #12] while (__HAL_FLASH_GET_LATENCY() != FLatency) 8003aae: e00a b.n 8003ac6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003ab0: f7fd fbae bl 8001210 8003ab4: 4602 mov r2, r0 8003ab6: 68fb ldr r3, [r7, #12] 8003ab8: 1ad3 subs r3, r2, r3 8003aba: f241 3288 movw r2, #5000 @ 0x1388 8003abe: 4293 cmp r3, r2 8003ac0: d901 bls.n 8003ac6 { return HAL_TIMEOUT; 8003ac2: 2303 movs r3, #3 8003ac4: e03b b.n 8003b3e while (__HAL_FLASH_GET_LATENCY() != FLatency) 8003ac6: 4b20 ldr r3, [pc, #128] @ (8003b48 ) 8003ac8: 681b ldr r3, [r3, #0] 8003aca: f003 030f and.w r3, r3, #15 8003ace: 683a ldr r2, [r7, #0] 8003ad0: 429a cmp r2, r3 8003ad2: d1ed bne.n 8003ab0 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003ad4: 687b ldr r3, [r7, #4] 8003ad6: 681b ldr r3, [r3, #0] 8003ad8: f003 0304 and.w r3, r3, #4 8003adc: 2b00 cmp r3, #0 8003ade: d008 beq.n 8003af2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8003ae0: 4b1a ldr r3, [pc, #104] @ (8003b4c ) 8003ae2: 689b ldr r3, [r3, #8] 8003ae4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8003ae8: 687b ldr r3, [r7, #4] 8003aea: 68db ldr r3, [r3, #12] 8003aec: 4917 ldr r1, [pc, #92] @ (8003b4c ) 8003aee: 4313 orrs r3, r2 8003af0: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003af2: 687b ldr r3, [r7, #4] 8003af4: 681b ldr r3, [r3, #0] 8003af6: f003 0308 and.w r3, r3, #8 8003afa: 2b00 cmp r3, #0 8003afc: d009 beq.n 8003b12 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8003afe: 4b13 ldr r3, [pc, #76] @ (8003b4c ) 8003b00: 689b ldr r3, [r3, #8] 8003b02: f423 5260 bic.w r2, r3, #14336 @ 0x3800 8003b06: 687b ldr r3, [r7, #4] 8003b08: 691b ldr r3, [r3, #16] 8003b0a: 00db lsls r3, r3, #3 8003b0c: 490f ldr r1, [pc, #60] @ (8003b4c ) 8003b0e: 4313 orrs r3, r2 8003b10: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); 8003b12: f000 f825 bl 8003b60 8003b16: 4602 mov r2, r0 8003b18: 4b0c ldr r3, [pc, #48] @ (8003b4c ) 8003b1a: 689b ldr r3, [r3, #8] 8003b1c: 091b lsrs r3, r3, #4 8003b1e: f003 030f and.w r3, r3, #15 8003b22: 490c ldr r1, [pc, #48] @ (8003b54 ) 8003b24: 5ccb ldrb r3, [r1, r3] 8003b26: f003 031f and.w r3, r3, #31 8003b2a: fa22 f303 lsr.w r3, r2, r3 8003b2e: 4a0a ldr r2, [pc, #40] @ (8003b58 ) 8003b30: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8003b32: 4b0a ldr r3, [pc, #40] @ (8003b5c ) 8003b34: 681b ldr r3, [r3, #0] 8003b36: 4618 mov r0, r3 8003b38: f7fd fb1e bl 8001178 8003b3c: 4603 mov r3, r0 } 8003b3e: 4618 mov r0, r3 8003b40: 3718 adds r7, #24 8003b42: 46bd mov sp, r7 8003b44: bd80 pop {r7, pc} 8003b46: bf00 nop 8003b48: 40022000 .word 0x40022000 8003b4c: 40021000 .word 0x40021000 8003b50: 04c4b400 .word 0x04c4b400 8003b54: 08006d34 .word 0x08006d34 8003b58: 20000000 .word 0x20000000 8003b5c: 20000004 .word 0x20000004 08003b60 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003b60: b480 push {r7} 8003b62: b087 sub sp, #28 8003b64: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8003b66: 4b2c ldr r3, [pc, #176] @ (8003c18 ) 8003b68: 689b ldr r3, [r3, #8] 8003b6a: f003 030c and.w r3, r3, #12 8003b6e: 2b04 cmp r3, #4 8003b70: d102 bne.n 8003b78 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 8003b72: 4b2a ldr r3, [pc, #168] @ (8003c1c ) 8003b74: 613b str r3, [r7, #16] 8003b76: e047 b.n 8003c08 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8003b78: 4b27 ldr r3, [pc, #156] @ (8003c18 ) 8003b7a: 689b ldr r3, [r3, #8] 8003b7c: f003 030c and.w r3, r3, #12 8003b80: 2b08 cmp r3, #8 8003b82: d102 bne.n 8003b8a { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8003b84: 4b26 ldr r3, [pc, #152] @ (8003c20 ) 8003b86: 613b str r3, [r7, #16] 8003b88: e03e b.n 8003c08 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) 8003b8a: 4b23 ldr r3, [pc, #140] @ (8003c18 ) 8003b8c: 689b ldr r3, [r3, #8] 8003b8e: f003 030c and.w r3, r3, #12 8003b92: 2b0c cmp r3, #12 8003b94: d136 bne.n 8003c04 /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8003b96: 4b20 ldr r3, [pc, #128] @ (8003c18 ) 8003b98: 68db ldr r3, [r3, #12] 8003b9a: f003 0303 and.w r3, r3, #3 8003b9e: 60fb str r3, [r7, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8003ba0: 4b1d ldr r3, [pc, #116] @ (8003c18 ) 8003ba2: 68db ldr r3, [r3, #12] 8003ba4: 091b lsrs r3, r3, #4 8003ba6: f003 030f and.w r3, r3, #15 8003baa: 3301 adds r3, #1 8003bac: 60bb str r3, [r7, #8] switch (pllsource) 8003bae: 68fb ldr r3, [r7, #12] 8003bb0: 2b03 cmp r3, #3 8003bb2: d10c bne.n 8003bce { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8003bb4: 4a1a ldr r2, [pc, #104] @ (8003c20 ) 8003bb6: 68bb ldr r3, [r7, #8] 8003bb8: fbb2 f3f3 udiv r3, r2, r3 8003bbc: 4a16 ldr r2, [pc, #88] @ (8003c18 ) 8003bbe: 68d2 ldr r2, [r2, #12] 8003bc0: 0a12 lsrs r2, r2, #8 8003bc2: f002 027f and.w r2, r2, #127 @ 0x7f 8003bc6: fb02 f303 mul.w r3, r2, r3 8003bca: 617b str r3, [r7, #20] break; 8003bcc: e00c b.n 8003be8 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8003bce: 4a13 ldr r2, [pc, #76] @ (8003c1c ) 8003bd0: 68bb ldr r3, [r7, #8] 8003bd2: fbb2 f3f3 udiv r3, r2, r3 8003bd6: 4a10 ldr r2, [pc, #64] @ (8003c18 ) 8003bd8: 68d2 ldr r2, [r2, #12] 8003bda: 0a12 lsrs r2, r2, #8 8003bdc: f002 027f and.w r2, r2, #127 @ 0x7f 8003be0: fb02 f303 mul.w r3, r2, r3 8003be4: 617b str r3, [r7, #20] break; 8003be6: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8003be8: 4b0b ldr r3, [pc, #44] @ (8003c18 ) 8003bea: 68db ldr r3, [r3, #12] 8003bec: 0e5b lsrs r3, r3, #25 8003bee: f003 0303 and.w r3, r3, #3 8003bf2: 3301 adds r3, #1 8003bf4: 005b lsls r3, r3, #1 8003bf6: 607b str r3, [r7, #4] sysclockfreq = pllvco/pllr; 8003bf8: 697a ldr r2, [r7, #20] 8003bfa: 687b ldr r3, [r7, #4] 8003bfc: fbb2 f3f3 udiv r3, r2, r3 8003c00: 613b str r3, [r7, #16] 8003c02: e001 b.n 8003c08 } else { sysclockfreq = 0U; 8003c04: 2300 movs r3, #0 8003c06: 613b str r3, [r7, #16] } return sysclockfreq; 8003c08: 693b ldr r3, [r7, #16] } 8003c0a: 4618 mov r0, r3 8003c0c: 371c adds r7, #28 8003c0e: 46bd mov sp, r7 8003c10: f85d 7b04 ldr.w r7, [sp], #4 8003c14: 4770 bx lr 8003c16: bf00 nop 8003c18: 40021000 .word 0x40021000 8003c1c: 00f42400 .word 0x00f42400 8003c20: 007a1200 .word 0x007a1200 08003c24 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003c24: b480 push {r7} 8003c26: af00 add r7, sp, #0 return SystemCoreClock; 8003c28: 4b03 ldr r3, [pc, #12] @ (8003c38 ) 8003c2a: 681b ldr r3, [r3, #0] } 8003c2c: 4618 mov r0, r3 8003c2e: 46bd mov sp, r7 8003c30: f85d 7b04 ldr.w r7, [sp], #4 8003c34: 4770 bx lr 8003c36: bf00 nop 8003c38: 20000000 .word 0x20000000 08003c3c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003c3c: b580 push {r7, lr} 8003c3e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); 8003c40: f7ff fff0 bl 8003c24 8003c44: 4602 mov r2, r0 8003c46: 4b06 ldr r3, [pc, #24] @ (8003c60 ) 8003c48: 689b ldr r3, [r3, #8] 8003c4a: 0a1b lsrs r3, r3, #8 8003c4c: f003 0307 and.w r3, r3, #7 8003c50: 4904 ldr r1, [pc, #16] @ (8003c64 ) 8003c52: 5ccb ldrb r3, [r1, r3] 8003c54: f003 031f and.w r3, r3, #31 8003c58: fa22 f303 lsr.w r3, r2, r3 } 8003c5c: 4618 mov r0, r3 8003c5e: bd80 pop {r7, pc} 8003c60: 40021000 .word 0x40021000 8003c64: 08006d44 .word 0x08006d44 08003c68 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8003c68: b580 push {r7, lr} 8003c6a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); 8003c6c: f7ff ffda bl 8003c24 8003c70: 4602 mov r2, r0 8003c72: 4b06 ldr r3, [pc, #24] @ (8003c8c ) 8003c74: 689b ldr r3, [r3, #8] 8003c76: 0adb lsrs r3, r3, #11 8003c78: f003 0307 and.w r3, r3, #7 8003c7c: 4904 ldr r1, [pc, #16] @ (8003c90 ) 8003c7e: 5ccb ldrb r3, [r1, r3] 8003c80: f003 031f and.w r3, r3, #31 8003c84: fa22 f303 lsr.w r3, r2, r3 } 8003c88: 4618 mov r0, r3 8003c8a: bd80 pop {r7, pc} 8003c8c: 40021000 .word 0x40021000 8003c90: 08006d44 .word 0x08006d44 08003c94 : /** * @brief Compute SYSCLK frequency based on PLL SYSCLK source. * @retval SYSCLK frequency */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { 8003c94: b480 push {r7} 8003c96: b087 sub sp, #28 8003c98: af00 add r7, sp, #0 uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 8003c9a: 4b1e ldr r3, [pc, #120] @ (8003d14 ) 8003c9c: 68db ldr r3, [r3, #12] 8003c9e: f003 0303 and.w r3, r3, #3 8003ca2: 613b str r3, [r7, #16] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8003ca4: 4b1b ldr r3, [pc, #108] @ (8003d14 ) 8003ca6: 68db ldr r3, [r3, #12] 8003ca8: 091b lsrs r3, r3, #4 8003caa: f003 030f and.w r3, r3, #15 8003cae: 3301 adds r3, #1 8003cb0: 60fb str r3, [r7, #12] switch (pllsource) 8003cb2: 693b ldr r3, [r7, #16] 8003cb4: 2b03 cmp r3, #3 8003cb6: d10c bne.n 8003cd2 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8003cb8: 4a17 ldr r2, [pc, #92] @ (8003d18 ) 8003cba: 68fb ldr r3, [r7, #12] 8003cbc: fbb2 f3f3 udiv r3, r2, r3 8003cc0: 4a14 ldr r2, [pc, #80] @ (8003d14 ) 8003cc2: 68d2 ldr r2, [r2, #12] 8003cc4: 0a12 lsrs r2, r2, #8 8003cc6: f002 027f and.w r2, r2, #127 @ 0x7f 8003cca: fb02 f303 mul.w r3, r2, r3 8003cce: 617b str r3, [r7, #20] break; 8003cd0: e00c b.n 8003cec case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8003cd2: 4a12 ldr r2, [pc, #72] @ (8003d1c ) 8003cd4: 68fb ldr r3, [r7, #12] 8003cd6: fbb2 f3f3 udiv r3, r2, r3 8003cda: 4a0e ldr r2, [pc, #56] @ (8003d14 ) 8003cdc: 68d2 ldr r2, [r2, #12] 8003cde: 0a12 lsrs r2, r2, #8 8003ce0: f002 027f and.w r2, r2, #127 @ 0x7f 8003ce4: fb02 f303 mul.w r3, r2, r3 8003ce8: 617b str r3, [r7, #20] break; 8003cea: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; 8003cec: 4b09 ldr r3, [pc, #36] @ (8003d14 ) 8003cee: 68db ldr r3, [r3, #12] 8003cf0: 0e5b lsrs r3, r3, #25 8003cf2: f003 0303 and.w r3, r3, #3 8003cf6: 3301 adds r3, #1 8003cf8: 005b lsls r3, r3, #1 8003cfa: 60bb str r3, [r7, #8] sysclockfreq = pllvco/pllr; 8003cfc: 697a ldr r2, [r7, #20] 8003cfe: 68bb ldr r3, [r7, #8] 8003d00: fbb2 f3f3 udiv r3, r2, r3 8003d04: 607b str r3, [r7, #4] return sysclockfreq; 8003d06: 687b ldr r3, [r7, #4] } 8003d08: 4618 mov r0, r3 8003d0a: 371c adds r7, #28 8003d0c: 46bd mov sp, r7 8003d0e: f85d 7b04 ldr.w r7, [sp], #4 8003d12: 4770 bx lr 8003d14: 40021000 .word 0x40021000 8003d18: 007a1200 .word 0x007a1200 8003d1c: 00f42400 .word 0x00f42400 08003d20 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003d20: b580 push {r7, lr} 8003d22: b086 sub sp, #24 8003d24: af00 add r7, sp, #0 8003d26: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003d28: 2300 movs r3, #0 8003d2a: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003d2c: 2300 movs r3, #0 8003d2e: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8003d30: 687b ldr r3, [r7, #4] 8003d32: 681b ldr r3, [r3, #0] 8003d34: f403 2300 and.w r3, r3, #524288 @ 0x80000 8003d38: 2b00 cmp r3, #0 8003d3a: f000 8098 beq.w 8003e6e { FlagStatus pwrclkchanged = RESET; 8003d3e: 2300 movs r3, #0 8003d40: 747b strb r3, [r7, #17] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003d42: 4b43 ldr r3, [pc, #268] @ (8003e50 ) 8003d44: 6d9b ldr r3, [r3, #88] @ 0x58 8003d46: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003d4a: 2b00 cmp r3, #0 8003d4c: d10d bne.n 8003d6a { __HAL_RCC_PWR_CLK_ENABLE(); 8003d4e: 4b40 ldr r3, [pc, #256] @ (8003e50 ) 8003d50: 6d9b ldr r3, [r3, #88] @ 0x58 8003d52: 4a3f ldr r2, [pc, #252] @ (8003e50 ) 8003d54: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8003d58: 6593 str r3, [r2, #88] @ 0x58 8003d5a: 4b3d ldr r3, [pc, #244] @ (8003e50 ) 8003d5c: 6d9b ldr r3, [r3, #88] @ 0x58 8003d5e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8003d62: 60bb str r3, [r7, #8] 8003d64: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003d66: 2301 movs r3, #1 8003d68: 747b strb r3, [r7, #17] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003d6a: 4b3a ldr r3, [pc, #232] @ (8003e54 ) 8003d6c: 681b ldr r3, [r3, #0] 8003d6e: 4a39 ldr r2, [pc, #228] @ (8003e54 ) 8003d70: f443 7380 orr.w r3, r3, #256 @ 0x100 8003d74: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003d76: f7fd fa4b bl 8001210 8003d7a: 60f8 str r0, [r7, #12] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003d7c: e009 b.n 8003d92 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003d7e: f7fd fa47 bl 8001210 8003d82: 4602 mov r2, r0 8003d84: 68fb ldr r3, [r7, #12] 8003d86: 1ad3 subs r3, r2, r3 8003d88: 2b02 cmp r3, #2 8003d8a: d902 bls.n 8003d92 { ret = HAL_TIMEOUT; 8003d8c: 2303 movs r3, #3 8003d8e: 74fb strb r3, [r7, #19] break; 8003d90: e005 b.n 8003d9e while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003d92: 4b30 ldr r3, [pc, #192] @ (8003e54 ) 8003d94: 681b ldr r3, [r3, #0] 8003d96: f403 7380 and.w r3, r3, #256 @ 0x100 8003d9a: 2b00 cmp r3, #0 8003d9c: d0ef beq.n 8003d7e } } if(ret == HAL_OK) 8003d9e: 7cfb ldrb r3, [r7, #19] 8003da0: 2b00 cmp r3, #0 8003da2: d159 bne.n 8003e58 { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8003da4: 4b2a ldr r3, [pc, #168] @ (8003e50 ) 8003da6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003daa: f403 7340 and.w r3, r3, #768 @ 0x300 8003dae: 617b str r3, [r7, #20] if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 8003db0: 697b ldr r3, [r7, #20] 8003db2: 2b00 cmp r3, #0 8003db4: d01e beq.n 8003df4 8003db6: 687b ldr r3, [r7, #4] 8003db8: 6c1b ldr r3, [r3, #64] @ 0x40 8003dba: 697a ldr r2, [r7, #20] 8003dbc: 429a cmp r2, r3 8003dbe: d019 beq.n 8003df4 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 8003dc0: 4b23 ldr r3, [pc, #140] @ (8003e50 ) 8003dc2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003dc6: f423 7340 bic.w r3, r3, #768 @ 0x300 8003dca: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003dcc: 4b20 ldr r3, [pc, #128] @ (8003e50 ) 8003dce: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003dd2: 4a1f ldr r2, [pc, #124] @ (8003e50 ) 8003dd4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8003dd8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 8003ddc: 4b1c ldr r3, [pc, #112] @ (8003e50 ) 8003dde: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003de2: 4a1b ldr r2, [pc, #108] @ (8003e50 ) 8003de4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8003de8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 8003dec: 4a18 ldr r2, [pc, #96] @ (8003e50 ) 8003dee: 697b ldr r3, [r7, #20] 8003df0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 8003df4: 697b ldr r3, [r7, #20] 8003df6: f003 0301 and.w r3, r3, #1 8003dfa: 2b00 cmp r3, #0 8003dfc: d016 beq.n 8003e2c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003dfe: f7fd fa07 bl 8001210 8003e02: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003e04: e00b b.n 8003e1e { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003e06: f7fd fa03 bl 8001210 8003e0a: 4602 mov r2, r0 8003e0c: 68fb ldr r3, [r7, #12] 8003e0e: 1ad3 subs r3, r2, r3 8003e10: f241 3288 movw r2, #5000 @ 0x1388 8003e14: 4293 cmp r3, r2 8003e16: d902 bls.n 8003e1e { ret = HAL_TIMEOUT; 8003e18: 2303 movs r3, #3 8003e1a: 74fb strb r3, [r7, #19] break; 8003e1c: e006 b.n 8003e2c while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003e1e: 4b0c ldr r3, [pc, #48] @ (8003e50 ) 8003e20: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003e24: f003 0302 and.w r3, r3, #2 8003e28: 2b00 cmp r3, #0 8003e2a: d0ec beq.n 8003e06 } } } if(ret == HAL_OK) 8003e2c: 7cfb ldrb r3, [r7, #19] 8003e2e: 2b00 cmp r3, #0 8003e30: d10b bne.n 8003e4a { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003e32: 4b07 ldr r3, [pc, #28] @ (8003e50 ) 8003e34: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8003e38: f423 7240 bic.w r2, r3, #768 @ 0x300 8003e3c: 687b ldr r3, [r7, #4] 8003e3e: 6c1b ldr r3, [r3, #64] @ 0x40 8003e40: 4903 ldr r1, [pc, #12] @ (8003e50 ) 8003e42: 4313 orrs r3, r2 8003e44: f8c1 3090 str.w r3, [r1, #144] @ 0x90 8003e48: e008 b.n 8003e5c } else { /* set overall return value */ status = ret; 8003e4a: 7cfb ldrb r3, [r7, #19] 8003e4c: 74bb strb r3, [r7, #18] 8003e4e: e005 b.n 8003e5c 8003e50: 40021000 .word 0x40021000 8003e54: 40007000 .word 0x40007000 } } else { /* set overall return value */ status = ret; 8003e58: 7cfb ldrb r3, [r7, #19] 8003e5a: 74bb strb r3, [r7, #18] } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8003e5c: 7c7b ldrb r3, [r7, #17] 8003e5e: 2b01 cmp r3, #1 8003e60: d105 bne.n 8003e6e { __HAL_RCC_PWR_CLK_DISABLE(); 8003e62: 4ba6 ldr r3, [pc, #664] @ (80040fc ) 8003e64: 6d9b ldr r3, [r3, #88] @ 0x58 8003e66: 4aa5 ldr r2, [pc, #660] @ (80040fc ) 8003e68: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8003e6c: 6593 str r3, [r2, #88] @ 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8003e6e: 687b ldr r3, [r7, #4] 8003e70: 681b ldr r3, [r3, #0] 8003e72: f003 0301 and.w r3, r3, #1 8003e76: 2b00 cmp r3, #0 8003e78: d00a beq.n 8003e90 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8003e7a: 4ba0 ldr r3, [pc, #640] @ (80040fc ) 8003e7c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003e80: f023 0203 bic.w r2, r3, #3 8003e84: 687b ldr r3, [r7, #4] 8003e86: 685b ldr r3, [r3, #4] 8003e88: 499c ldr r1, [pc, #624] @ (80040fc ) 8003e8a: 4313 orrs r3, r2 8003e8c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8003e90: 687b ldr r3, [r7, #4] 8003e92: 681b ldr r3, [r3, #0] 8003e94: f003 0302 and.w r3, r3, #2 8003e98: 2b00 cmp r3, #0 8003e9a: d00a beq.n 8003eb2 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8003e9c: 4b97 ldr r3, [pc, #604] @ (80040fc ) 8003e9e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003ea2: f023 020c bic.w r2, r3, #12 8003ea6: 687b ldr r3, [r7, #4] 8003ea8: 689b ldr r3, [r3, #8] 8003eaa: 4994 ldr r1, [pc, #592] @ (80040fc ) 8003eac: 4313 orrs r3, r2 8003eae: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(USART3) /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) 8003eb2: 687b ldr r3, [r7, #4] 8003eb4: 681b ldr r3, [r3, #0] 8003eb6: f003 0304 and.w r3, r3, #4 8003eba: 2b00 cmp r3, #0 8003ebc: d00a beq.n 8003ed4 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); 8003ebe: 4b8f ldr r3, [pc, #572] @ (80040fc ) 8003ec0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003ec4: f023 0230 bic.w r2, r3, #48 @ 0x30 8003ec8: 687b ldr r3, [r7, #4] 8003eca: 68db ldr r3, [r3, #12] 8003ecc: 498b ldr r1, [pc, #556] @ (80040fc ) 8003ece: 4313 orrs r3, r2 8003ed0: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* USART3 */ #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) 8003ed4: 687b ldr r3, [r7, #4] 8003ed6: 681b ldr r3, [r3, #0] 8003ed8: f003 0308 and.w r3, r3, #8 8003edc: 2b00 cmp r3, #0 8003ede: d00a beq.n 8003ef6 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); 8003ee0: 4b86 ldr r3, [pc, #536] @ (80040fc ) 8003ee2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003ee6: f023 02c0 bic.w r2, r3, #192 @ 0xc0 8003eea: 687b ldr r3, [r7, #4] 8003eec: 691b ldr r3, [r3, #16] 8003eee: 4983 ldr r1, [pc, #524] @ (80040fc ) 8003ef0: 4313 orrs r3, r2 8003ef2: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8003ef6: 687b ldr r3, [r7, #4] 8003ef8: 681b ldr r3, [r3, #0] 8003efa: f003 0320 and.w r3, r3, #32 8003efe: 2b00 cmp r3, #0 8003f00: d00a beq.n 8003f18 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8003f02: 4b7e ldr r3, [pc, #504] @ (80040fc ) 8003f04: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003f08: f423 6240 bic.w r2, r3, #3072 @ 0xc00 8003f0c: 687b ldr r3, [r7, #4] 8003f0e: 695b ldr r3, [r3, #20] 8003f10: 497a ldr r1, [pc, #488] @ (80040fc ) 8003f12: 4313 orrs r3, r2 8003f14: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8003f18: 687b ldr r3, [r7, #4] 8003f1a: 681b ldr r3, [r3, #0] 8003f1c: f003 0340 and.w r3, r3, #64 @ 0x40 8003f20: 2b00 cmp r3, #0 8003f22: d00a beq.n 8003f3a { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8003f24: 4b75 ldr r3, [pc, #468] @ (80040fc ) 8003f26: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003f2a: f423 5240 bic.w r2, r3, #12288 @ 0x3000 8003f2e: 687b ldr r3, [r7, #4] 8003f30: 699b ldr r3, [r3, #24] 8003f32: 4972 ldr r1, [pc, #456] @ (80040fc ) 8003f34: 4313 orrs r3, r2 8003f36: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) 8003f3a: 687b ldr r3, [r7, #4] 8003f3c: 681b ldr r3, [r3, #0] 8003f3e: f003 0380 and.w r3, r3, #128 @ 0x80 8003f42: 2b00 cmp r3, #0 8003f44: d00a beq.n 8003f5c { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); 8003f46: 4b6d ldr r3, [pc, #436] @ (80040fc ) 8003f48: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003f4c: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8003f50: 687b ldr r3, [r7, #4] 8003f52: 69db ldr r3, [r3, #28] 8003f54: 4969 ldr r1, [pc, #420] @ (80040fc ) 8003f56: 4313 orrs r3, r2 8003f58: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 8003f5c: 687b ldr r3, [r7, #4] 8003f5e: 681b ldr r3, [r3, #0] 8003f60: f403 7380 and.w r3, r3, #256 @ 0x100 8003f64: 2b00 cmp r3, #0 8003f66: d00a beq.n 8003f7e { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 8003f68: 4b64 ldr r3, [pc, #400] @ (80040fc ) 8003f6a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003f6e: f423 3240 bic.w r2, r3, #196608 @ 0x30000 8003f72: 687b ldr r3, [r7, #4] 8003f74: 6a1b ldr r3, [r3, #32] 8003f76: 4961 ldr r1, [pc, #388] @ (80040fc ) 8003f78: 4313 orrs r3, r2 8003f7a: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8003f7e: 687b ldr r3, [r7, #4] 8003f80: 681b ldr r3, [r3, #0] 8003f82: f403 7300 and.w r3, r3, #512 @ 0x200 8003f86: 2b00 cmp r3, #0 8003f88: d00a beq.n 8003fa0 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8003f8a: 4b5c ldr r3, [pc, #368] @ (80040fc ) 8003f8c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003f90: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 8003f94: 687b ldr r3, [r7, #4] 8003f96: 6a5b ldr r3, [r3, #36] @ 0x24 8003f98: 4958 ldr r1, [pc, #352] @ (80040fc ) 8003f9a: 4313 orrs r3, r2 8003f9c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8003fa0: 687b ldr r3, [r7, #4] 8003fa2: 681b ldr r3, [r3, #0] 8003fa4: f403 6380 and.w r3, r3, #1024 @ 0x400 8003fa8: 2b00 cmp r3, #0 8003faa: d015 beq.n 8003fd8 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8003fac: 4b53 ldr r3, [pc, #332] @ (80040fc ) 8003fae: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003fb2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 8003fb6: 687b ldr r3, [r7, #4] 8003fb8: 6a9b ldr r3, [r3, #40] @ 0x28 8003fba: 4950 ldr r1, [pc, #320] @ (80040fc ) 8003fbc: 4313 orrs r3, r2 8003fbe: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) 8003fc2: 687b ldr r3, [r7, #4] 8003fc4: 6a9b ldr r3, [r3, #40] @ 0x28 8003fc6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8003fca: d105 bne.n 8003fd8 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8003fcc: 4b4b ldr r3, [pc, #300] @ (80040fc ) 8003fce: 68db ldr r3, [r3, #12] 8003fd0: 4a4a ldr r2, [pc, #296] @ (80040fc ) 8003fd2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8003fd6: 60d3 str r3, [r2, #12] #endif /* SAI1 */ #if defined(SPI_I2S_SUPPORT) /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) 8003fd8: 687b ldr r3, [r7, #4] 8003fda: 681b ldr r3, [r3, #0] 8003fdc: f403 6300 and.w r3, r3, #2048 @ 0x800 8003fe0: 2b00 cmp r3, #0 8003fe2: d015 beq.n 8004010 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); 8003fe4: 4b45 ldr r3, [pc, #276] @ (80040fc ) 8003fe6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8003fea: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 8003fee: 687b ldr r3, [r7, #4] 8003ff0: 6adb ldr r3, [r3, #44] @ 0x2c 8003ff2: 4942 ldr r1, [pc, #264] @ (80040fc ) 8003ff4: 4313 orrs r3, r2 8003ff6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 6adb ldr r3, [r3, #44] @ 0x2c 8003ffe: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004002: d105 bne.n 8004010 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8004004: 4b3d ldr r3, [pc, #244] @ (80040fc ) 8004006: 68db ldr r3, [r3, #12] 8004008: 4a3c ldr r2, [pc, #240] @ (80040fc ) 800400a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800400e: 60d3 str r3, [r2, #12] #endif /* SPI_I2S_SUPPORT */ #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8004010: 687b ldr r3, [r7, #4] 8004012: 681b ldr r3, [r3, #0] 8004014: f403 5380 and.w r3, r3, #4096 @ 0x1000 8004018: 2b00 cmp r3, #0 800401a: d015 beq.n 8004048 { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800401c: 4b37 ldr r3, [pc, #220] @ (80040fc ) 800401e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004022: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 8004026: 687b ldr r3, [r7, #4] 8004028: 6b1b ldr r3, [r3, #48] @ 0x30 800402a: 4934 ldr r1, [pc, #208] @ (80040fc ) 800402c: 4313 orrs r3, r2 800402e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) 8004032: 687b ldr r3, [r7, #4] 8004034: 6b1b ldr r3, [r3, #48] @ 0x30 8004036: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800403a: d105 bne.n 8004048 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800403c: 4b2f ldr r3, [pc, #188] @ (80040fc ) 800403e: 68db ldr r3, [r3, #12] 8004040: 4a2e ldr r2, [pc, #184] @ (80040fc ) 8004042: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8004046: 60d3 str r3, [r2, #12] #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 8004048: 687b ldr r3, [r7, #4] 800404a: 681b ldr r3, [r3, #0] 800404c: f403 5300 and.w r3, r3, #8192 @ 0x2000 8004050: 2b00 cmp r3, #0 8004052: d015 beq.n 8004080 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8004054: 4b29 ldr r3, [pc, #164] @ (80040fc ) 8004056: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800405a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 800405e: 687b ldr r3, [r7, #4] 8004060: 6b5b ldr r3, [r3, #52] @ 0x34 8004062: 4926 ldr r1, [pc, #152] @ (80040fc ) 8004064: 4313 orrs r3, r2 8004066: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 800406a: 687b ldr r3, [r7, #4] 800406c: 6b5b ldr r3, [r3, #52] @ 0x34 800406e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 8004072: d105 bne.n 8004080 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 8004074: 4b21 ldr r3, [pc, #132] @ (80040fc ) 8004076: 68db ldr r3, [r3, #12] 8004078: 4a20 ldr r2, [pc, #128] @ (80040fc ) 800407a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800407e: 60d3 str r3, [r2, #12] } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 8004080: 687b ldr r3, [r7, #4] 8004082: 681b ldr r3, [r3, #0] 8004084: f403 4380 and.w r3, r3, #16384 @ 0x4000 8004088: 2b00 cmp r3, #0 800408a: d015 beq.n 80040b8 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800408c: 4b1b ldr r3, [pc, #108] @ (80040fc ) 800408e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004092: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 8004096: 687b ldr r3, [r7, #4] 8004098: 6b9b ldr r3, [r3, #56] @ 0x38 800409a: 4918 ldr r1, [pc, #96] @ (80040fc ) 800409c: 4313 orrs r3, r2 800409e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 80040a2: 687b ldr r3, [r7, #4] 80040a4: 6b9b ldr r3, [r3, #56] @ 0x38 80040a6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 80040aa: d105 bne.n 80040b8 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80040ac: 4b13 ldr r3, [pc, #76] @ (80040fc ) 80040ae: 68db ldr r3, [r3, #12] 80040b0: 4a12 ldr r2, [pc, #72] @ (80040fc ) 80040b2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 80040b6: 60d3 str r3, [r2, #12] } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) 80040b8: 687b ldr r3, [r7, #4] 80040ba: 681b ldr r3, [r3, #0] 80040bc: f403 4300 and.w r3, r3, #32768 @ 0x8000 80040c0: 2b00 cmp r3, #0 80040c2: d015 beq.n 80040f0 { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); 80040c4: 4b0d ldr r3, [pc, #52] @ (80040fc ) 80040c6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80040ca: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 80040ce: 687b ldr r3, [r7, #4] 80040d0: 6bdb ldr r3, [r3, #60] @ 0x3c 80040d2: 490a ldr r1, [pc, #40] @ (80040fc ) 80040d4: 4313 orrs r3, r2 80040d6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) 80040da: 687b ldr r3, [r7, #4] 80040dc: 6bdb ldr r3, [r3, #60] @ 0x3c 80040de: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80040e2: d105 bne.n 80040f0 { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); 80040e4: 4b05 ldr r3, [pc, #20] @ (80040fc ) 80040e6: 68db ldr r3, [r3, #12] 80040e8: 4a04 ldr r2, [pc, #16] @ (80040fc ) 80040ea: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80040ee: 60d3 str r3, [r2, #12] } } #endif /* QUADSPI */ return status; 80040f0: 7cbb ldrb r3, [r7, #18] } 80040f2: 4618 mov r0, r3 80040f4: 3718 adds r7, #24 80040f6: 46bd mov sp, r7 80040f8: bd80 pop {r7, pc} 80040fa: bf00 nop 80040fc: 40021000 .word 0x40021000 08004100 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8004100: b580 push {r7, lr} 8004102: b082 sub sp, #8 8004104: af00 add r7, sp, #0 8004106: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8004108: 687b ldr r3, [r7, #4] 800410a: 2b00 cmp r3, #0 800410c: d101 bne.n 8004112 { return HAL_ERROR; 800410e: 2301 movs r3, #1 8004110: e049 b.n 80041a6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8004112: 687b ldr r3, [r7, #4] 8004114: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8004118: b2db uxtb r3, r3 800411a: 2b00 cmp r3, #0 800411c: d106 bne.n 800412c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800411e: 687b ldr r3, [r7, #4] 8004120: 2200 movs r2, #0 8004122: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8004126: 6878 ldr r0, [r7, #4] 8004128: f7fc ff0a bl 8000f40 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800412c: 687b ldr r3, [r7, #4] 800412e: 2202 movs r2, #2 8004130: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8004134: 687b ldr r3, [r7, #4] 8004136: 681a ldr r2, [r3, #0] 8004138: 687b ldr r3, [r7, #4] 800413a: 3304 adds r3, #4 800413c: 4619 mov r1, r3 800413e: 4610 mov r0, r2 8004140: f000 fab0 bl 80046a4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8004144: 687b ldr r3, [r7, #4] 8004146: 2201 movs r2, #1 8004148: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800414c: 687b ldr r3, [r7, #4] 800414e: 2201 movs r2, #1 8004150: f883 203e strb.w r2, [r3, #62] @ 0x3e 8004154: 687b ldr r3, [r7, #4] 8004156: 2201 movs r2, #1 8004158: f883 203f strb.w r2, [r3, #63] @ 0x3f 800415c: 687b ldr r3, [r7, #4] 800415e: 2201 movs r2, #1 8004160: f883 2040 strb.w r2, [r3, #64] @ 0x40 8004164: 687b ldr r3, [r7, #4] 8004166: 2201 movs r2, #1 8004168: f883 2041 strb.w r2, [r3, #65] @ 0x41 800416c: 687b ldr r3, [r7, #4] 800416e: 2201 movs r2, #1 8004170: f883 2042 strb.w r2, [r3, #66] @ 0x42 8004174: 687b ldr r3, [r7, #4] 8004176: 2201 movs r2, #1 8004178: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800417c: 687b ldr r3, [r7, #4] 800417e: 2201 movs r2, #1 8004180: f883 2044 strb.w r2, [r3, #68] @ 0x44 8004184: 687b ldr r3, [r7, #4] 8004186: 2201 movs r2, #1 8004188: f883 2045 strb.w r2, [r3, #69] @ 0x45 800418c: 687b ldr r3, [r7, #4] 800418e: 2201 movs r2, #1 8004190: f883 2046 strb.w r2, [r3, #70] @ 0x46 8004194: 687b ldr r3, [r7, #4] 8004196: 2201 movs r2, #1 8004198: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800419c: 687b ldr r3, [r7, #4] 800419e: 2201 movs r2, #1 80041a0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 80041a4: 2300 movs r3, #0 } 80041a6: 4618 mov r0, r3 80041a8: 3708 adds r7, #8 80041aa: 46bd mov sp, r7 80041ac: bd80 pop {r7, pc} 080041ae : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 80041ae: b580 push {r7, lr} 80041b0: b084 sub sp, #16 80041b2: af00 add r7, sp, #0 80041b4: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 80041b6: 687b ldr r3, [r7, #4] 80041b8: 681b ldr r3, [r3, #0] 80041ba: 68db ldr r3, [r3, #12] 80041bc: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 80041be: 687b ldr r3, [r7, #4] 80041c0: 681b ldr r3, [r3, #0] 80041c2: 691b ldr r3, [r3, #16] 80041c4: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 80041c6: 68bb ldr r3, [r7, #8] 80041c8: f003 0302 and.w r3, r3, #2 80041cc: 2b00 cmp r3, #0 80041ce: d020 beq.n 8004212 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80041d0: 68fb ldr r3, [r7, #12] 80041d2: f003 0302 and.w r3, r3, #2 80041d6: 2b00 cmp r3, #0 80041d8: d01b beq.n 8004212 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80041da: 687b ldr r3, [r7, #4] 80041dc: 681b ldr r3, [r3, #0] 80041de: f06f 0202 mvn.w r2, #2 80041e2: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80041e4: 687b ldr r3, [r7, #4] 80041e6: 2201 movs r2, #1 80041e8: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80041ea: 687b ldr r3, [r7, #4] 80041ec: 681b ldr r3, [r3, #0] 80041ee: 699b ldr r3, [r3, #24] 80041f0: f003 0303 and.w r3, r3, #3 80041f4: 2b00 cmp r3, #0 80041f6: d003 beq.n 8004200 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80041f8: 6878 ldr r0, [r7, #4] 80041fa: f000 fa35 bl 8004668 80041fe: e005 b.n 800420c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8004200: 6878 ldr r0, [r7, #4] 8004202: f000 fa27 bl 8004654 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004206: 6878 ldr r0, [r7, #4] 8004208: f000 fa38 bl 800467c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800420c: 687b ldr r3, [r7, #4] 800420e: 2200 movs r2, #0 8004210: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8004212: 68bb ldr r3, [r7, #8] 8004214: f003 0304 and.w r3, r3, #4 8004218: 2b00 cmp r3, #0 800421a: d020 beq.n 800425e { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800421c: 68fb ldr r3, [r7, #12] 800421e: f003 0304 and.w r3, r3, #4 8004222: 2b00 cmp r3, #0 8004224: d01b beq.n 800425e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8004226: 687b ldr r3, [r7, #4] 8004228: 681b ldr r3, [r3, #0] 800422a: f06f 0204 mvn.w r2, #4 800422e: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8004230: 687b ldr r3, [r7, #4] 8004232: 2202 movs r2, #2 8004234: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8004236: 687b ldr r3, [r7, #4] 8004238: 681b ldr r3, [r3, #0] 800423a: 699b ldr r3, [r3, #24] 800423c: f403 7340 and.w r3, r3, #768 @ 0x300 8004240: 2b00 cmp r3, #0 8004242: d003 beq.n 800424c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004244: 6878 ldr r0, [r7, #4] 8004246: f000 fa0f bl 8004668 800424a: e005 b.n 8004258 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800424c: 6878 ldr r0, [r7, #4] 800424e: f000 fa01 bl 8004654 HAL_TIM_PWM_PulseFinishedCallback(htim); 8004252: 6878 ldr r0, [r7, #4] 8004254: f000 fa12 bl 800467c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8004258: 687b ldr r3, [r7, #4] 800425a: 2200 movs r2, #0 800425c: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800425e: 68bb ldr r3, [r7, #8] 8004260: f003 0308 and.w r3, r3, #8 8004264: 2b00 cmp r3, #0 8004266: d020 beq.n 80042aa { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8004268: 68fb ldr r3, [r7, #12] 800426a: f003 0308 and.w r3, r3, #8 800426e: 2b00 cmp r3, #0 8004270: d01b beq.n 80042aa { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8004272: 687b ldr r3, [r7, #4] 8004274: 681b ldr r3, [r3, #0] 8004276: f06f 0208 mvn.w r2, #8 800427a: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800427c: 687b ldr r3, [r7, #4] 800427e: 2204 movs r2, #4 8004280: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8004282: 687b ldr r3, [r7, #4] 8004284: 681b ldr r3, [r3, #0] 8004286: 69db ldr r3, [r3, #28] 8004288: f003 0303 and.w r3, r3, #3 800428c: 2b00 cmp r3, #0 800428e: d003 beq.n 8004298 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8004290: 6878 ldr r0, [r7, #4] 8004292: f000 f9e9 bl 8004668 8004296: e005 b.n 80042a4 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8004298: 6878 ldr r0, [r7, #4] 800429a: f000 f9db bl 8004654 HAL_TIM_PWM_PulseFinishedCallback(htim); 800429e: 6878 ldr r0, [r7, #4] 80042a0: f000 f9ec bl 800467c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80042a4: 687b ldr r3, [r7, #4] 80042a6: 2200 movs r2, #0 80042a8: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 80042aa: 68bb ldr r3, [r7, #8] 80042ac: f003 0310 and.w r3, r3, #16 80042b0: 2b00 cmp r3, #0 80042b2: d020 beq.n 80042f6 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 80042b4: 68fb ldr r3, [r7, #12] 80042b6: f003 0310 and.w r3, r3, #16 80042ba: 2b00 cmp r3, #0 80042bc: d01b beq.n 80042f6 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 80042be: 687b ldr r3, [r7, #4] 80042c0: 681b ldr r3, [r3, #0] 80042c2: f06f 0210 mvn.w r2, #16 80042c6: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80042c8: 687b ldr r3, [r7, #4] 80042ca: 2208 movs r2, #8 80042cc: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80042ce: 687b ldr r3, [r7, #4] 80042d0: 681b ldr r3, [r3, #0] 80042d2: 69db ldr r3, [r3, #28] 80042d4: f403 7340 and.w r3, r3, #768 @ 0x300 80042d8: 2b00 cmp r3, #0 80042da: d003 beq.n 80042e4 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80042dc: 6878 ldr r0, [r7, #4] 80042de: f000 f9c3 bl 8004668 80042e2: e005 b.n 80042f0 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80042e4: 6878 ldr r0, [r7, #4] 80042e6: f000 f9b5 bl 8004654 HAL_TIM_PWM_PulseFinishedCallback(htim); 80042ea: 6878 ldr r0, [r7, #4] 80042ec: f000 f9c6 bl 800467c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80042f0: 687b ldr r3, [r7, #4] 80042f2: 2200 movs r2, #0 80042f4: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 80042f6: 68bb ldr r3, [r7, #8] 80042f8: f003 0301 and.w r3, r3, #1 80042fc: 2b00 cmp r3, #0 80042fe: d00c beq.n 800431a { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8004300: 68fb ldr r3, [r7, #12] 8004302: f003 0301 and.w r3, r3, #1 8004306: 2b00 cmp r3, #0 8004308: d007 beq.n 800431a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800430a: 687b ldr r3, [r7, #4] 800430c: 681b ldr r3, [r3, #0] 800430e: f06f 0201 mvn.w r2, #1 8004312: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8004314: 6878 ldr r0, [r7, #4] 8004316: f000 f993 bl 8004640 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800431a: 68bb ldr r3, [r7, #8] 800431c: f003 0380 and.w r3, r3, #128 @ 0x80 8004320: 2b00 cmp r3, #0 8004322: d104 bne.n 800432e ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 8004324: 68bb ldr r3, [r7, #8] 8004326: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800432a: 2b00 cmp r3, #0 800432c: d00c beq.n 8004348 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800432e: 68fb ldr r3, [r7, #12] 8004330: f003 0380 and.w r3, r3, #128 @ 0x80 8004334: 2b00 cmp r3, #0 8004336: d007 beq.n 8004348 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 8004338: 687b ldr r3, [r7, #4] 800433a: 681b ldr r3, [r3, #0] 800433c: f46f 5202 mvn.w r2, #8320 @ 0x2080 8004340: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8004342: 6878 ldr r0, [r7, #4] 8004344: f000 fb72 bl 8004a2c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 8004348: 68bb ldr r3, [r7, #8] 800434a: f403 7380 and.w r3, r3, #256 @ 0x100 800434e: 2b00 cmp r3, #0 8004350: d00c beq.n 800436c { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8004352: 68fb ldr r3, [r7, #12] 8004354: f003 0380 and.w r3, r3, #128 @ 0x80 8004358: 2b00 cmp r3, #0 800435a: d007 beq.n 800436c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800435c: 687b ldr r3, [r7, #4] 800435e: 681b ldr r3, [r3, #0] 8004360: f46f 7280 mvn.w r2, #256 @ 0x100 8004364: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8004366: 6878 ldr r0, [r7, #4] 8004368: f000 fb6a bl 8004a40 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800436c: 68bb ldr r3, [r7, #8] 800436e: f003 0340 and.w r3, r3, #64 @ 0x40 8004372: 2b00 cmp r3, #0 8004374: d00c beq.n 8004390 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8004376: 68fb ldr r3, [r7, #12] 8004378: f003 0340 and.w r3, r3, #64 @ 0x40 800437c: 2b00 cmp r3, #0 800437e: d007 beq.n 8004390 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8004380: 687b ldr r3, [r7, #4] 8004382: 681b ldr r3, [r3, #0] 8004384: f06f 0240 mvn.w r2, #64 @ 0x40 8004388: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800438a: 6878 ldr r0, [r7, #4] 800438c: f000 f980 bl 8004690 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8004390: 68bb ldr r3, [r7, #8] 8004392: f003 0320 and.w r3, r3, #32 8004396: 2b00 cmp r3, #0 8004398: d00c beq.n 80043b4 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800439a: 68fb ldr r3, [r7, #12] 800439c: f003 0320 and.w r3, r3, #32 80043a0: 2b00 cmp r3, #0 80043a2: d007 beq.n 80043b4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 80043a4: 687b ldr r3, [r7, #4] 80043a6: 681b ldr r3, [r3, #0] 80043a8: f06f 0220 mvn.w r2, #32 80043ac: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 80043ae: 6878 ldr r0, [r7, #4] 80043b0: f000 fb32 bl 8004a18 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Encoder index event */ if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) 80043b4: 68bb ldr r3, [r7, #8] 80043b6: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80043ba: 2b00 cmp r3, #0 80043bc: d00c beq.n 80043d8 { if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) 80043be: 68fb ldr r3, [r7, #12] 80043c0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80043c4: 2b00 cmp r3, #0 80043c6: d007 beq.n 80043d8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); 80043c8: 687b ldr r3, [r7, #4] 80043ca: 681b ldr r3, [r3, #0] 80043cc: f46f 1280 mvn.w r2, #1048576 @ 0x100000 80043d0: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else HAL_TIMEx_EncoderIndexCallback(htim); 80043d2: 6878 ldr r0, [r7, #4] 80043d4: f000 fb3e bl 8004a54 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Direction change event */ if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) 80043d8: 68bb ldr r3, [r7, #8] 80043da: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80043de: 2b00 cmp r3, #0 80043e0: d00c beq.n 80043fc { if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) 80043e2: 68fb ldr r3, [r7, #12] 80043e4: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80043e8: 2b00 cmp r3, #0 80043ea: d007 beq.n 80043fc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); 80043ec: 687b ldr r3, [r7, #4] 80043ee: 681b ldr r3, [r3, #0] 80043f0: f46f 1200 mvn.w r2, #2097152 @ 0x200000 80043f4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else HAL_TIMEx_DirectionChangeCallback(htim); 80043f6: 6878 ldr r0, [r7, #4] 80043f8: f000 fb36 bl 8004a68 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Index error event */ if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) 80043fc: 68bb ldr r3, [r7, #8] 80043fe: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004402: 2b00 cmp r3, #0 8004404: d00c beq.n 8004420 { if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) 8004406: 68fb ldr r3, [r7, #12] 8004408: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800440c: 2b00 cmp r3, #0 800440e: d007 beq.n 8004420 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); 8004410: 687b ldr r3, [r7, #4] 8004412: 681b ldr r3, [r3, #0] 8004414: f46f 0280 mvn.w r2, #4194304 @ 0x400000 8004418: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else HAL_TIMEx_IndexErrorCallback(htim); 800441a: 6878 ldr r0, [r7, #4] 800441c: f000 fb2e bl 8004a7c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Transition error event */ if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) 8004420: 68bb ldr r3, [r7, #8] 8004422: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8004426: 2b00 cmp r3, #0 8004428: d00c beq.n 8004444 { if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) 800442a: 68fb ldr r3, [r7, #12] 800442c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8004430: 2b00 cmp r3, #0 8004432: d007 beq.n 8004444 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); 8004434: 687b ldr r3, [r7, #4] 8004436: 681b ldr r3, [r3, #0] 8004438: f46f 0200 mvn.w r2, #8388608 @ 0x800000 800443c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else HAL_TIMEx_TransitionErrorCallback(htim); 800443e: 6878 ldr r0, [r7, #4] 8004440: f000 fb26 bl 8004a90 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8004444: bf00 nop 8004446: 3710 adds r7, #16 8004448: 46bd mov sp, r7 800444a: bd80 pop {r7, pc} 0800444c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 800444c: b580 push {r7, lr} 800444e: b084 sub sp, #16 8004450: af00 add r7, sp, #0 8004452: 6078 str r0, [r7, #4] 8004454: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8004456: 2300 movs r3, #0 8004458: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800445a: 687b ldr r3, [r7, #4] 800445c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8004460: 2b01 cmp r3, #1 8004462: d101 bne.n 8004468 8004464: 2302 movs r3, #2 8004466: e0de b.n 8004626 8004468: 687b ldr r3, [r7, #4] 800446a: 2201 movs r2, #1 800446c: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8004470: 687b ldr r3, [r7, #4] 8004472: 2202 movs r2, #2 8004474: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8004478: 687b ldr r3, [r7, #4] 800447a: 681b ldr r3, [r3, #0] 800447c: 689b ldr r3, [r3, #8] 800447e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8004480: 68bb ldr r3, [r7, #8] 8004482: f423 1344 bic.w r3, r3, #3211264 @ 0x310000 8004486: f023 0377 bic.w r3, r3, #119 @ 0x77 800448a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800448c: 68bb ldr r3, [r7, #8] 800448e: f423 437f bic.w r3, r3, #65280 @ 0xff00 8004492: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8004494: 687b ldr r3, [r7, #4] 8004496: 681b ldr r3, [r3, #0] 8004498: 68ba ldr r2, [r7, #8] 800449a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800449c: 683b ldr r3, [r7, #0] 800449e: 681b ldr r3, [r3, #0] 80044a0: 4a63 ldr r2, [pc, #396] @ (8004630 ) 80044a2: 4293 cmp r3, r2 80044a4: f000 80a9 beq.w 80045fa 80044a8: 4a61 ldr r2, [pc, #388] @ (8004630 ) 80044aa: 4293 cmp r3, r2 80044ac: f200 80ae bhi.w 800460c 80044b0: 4a60 ldr r2, [pc, #384] @ (8004634 ) 80044b2: 4293 cmp r3, r2 80044b4: f000 80a1 beq.w 80045fa 80044b8: 4a5e ldr r2, [pc, #376] @ (8004634 ) 80044ba: 4293 cmp r3, r2 80044bc: f200 80a6 bhi.w 800460c 80044c0: 4a5d ldr r2, [pc, #372] @ (8004638 ) 80044c2: 4293 cmp r3, r2 80044c4: f000 8099 beq.w 80045fa 80044c8: 4a5b ldr r2, [pc, #364] @ (8004638 ) 80044ca: 4293 cmp r3, r2 80044cc: f200 809e bhi.w 800460c 80044d0: 4a5a ldr r2, [pc, #360] @ (800463c ) 80044d2: 4293 cmp r3, r2 80044d4: f000 8091 beq.w 80045fa 80044d8: 4a58 ldr r2, [pc, #352] @ (800463c ) 80044da: 4293 cmp r3, r2 80044dc: f200 8096 bhi.w 800460c 80044e0: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80044e4: f000 8089 beq.w 80045fa 80044e8: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80044ec: f200 808e bhi.w 800460c 80044f0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80044f4: d03e beq.n 8004574 80044f6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80044fa: f200 8087 bhi.w 800460c 80044fe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004502: f000 8086 beq.w 8004612 8004506: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800450a: d87f bhi.n 800460c 800450c: 2b70 cmp r3, #112 @ 0x70 800450e: d01a beq.n 8004546 8004510: 2b70 cmp r3, #112 @ 0x70 8004512: d87b bhi.n 800460c 8004514: 2b60 cmp r3, #96 @ 0x60 8004516: d050 beq.n 80045ba 8004518: 2b60 cmp r3, #96 @ 0x60 800451a: d877 bhi.n 800460c 800451c: 2b50 cmp r3, #80 @ 0x50 800451e: d03c beq.n 800459a 8004520: 2b50 cmp r3, #80 @ 0x50 8004522: d873 bhi.n 800460c 8004524: 2b40 cmp r3, #64 @ 0x40 8004526: d058 beq.n 80045da 8004528: 2b40 cmp r3, #64 @ 0x40 800452a: d86f bhi.n 800460c 800452c: 2b30 cmp r3, #48 @ 0x30 800452e: d064 beq.n 80045fa 8004530: 2b30 cmp r3, #48 @ 0x30 8004532: d86b bhi.n 800460c 8004534: 2b20 cmp r3, #32 8004536: d060 beq.n 80045fa 8004538: 2b20 cmp r3, #32 800453a: d867 bhi.n 800460c 800453c: 2b00 cmp r3, #0 800453e: d05c beq.n 80045fa 8004540: 2b10 cmp r3, #16 8004542: d05a beq.n 80045fa 8004544: e062 b.n 800460c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8004546: 687b ldr r3, [r7, #4] 8004548: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800454a: 683b ldr r3, [r7, #0] 800454c: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800454e: 683b ldr r3, [r7, #0] 8004550: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8004552: 683b ldr r3, [r7, #0] 8004554: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8004556: f000 f9bd bl 80048d4 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800455a: 687b ldr r3, [r7, #4] 800455c: 681b ldr r3, [r3, #0] 800455e: 689b ldr r3, [r3, #8] 8004560: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8004562: 68bb ldr r3, [r7, #8] 8004564: f043 0377 orr.w r3, r3, #119 @ 0x77 8004568: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800456a: 687b ldr r3, [r7, #4] 800456c: 681b ldr r3, [r3, #0] 800456e: 68ba ldr r2, [r7, #8] 8004570: 609a str r2, [r3, #8] break; 8004572: e04f b.n 8004614 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8004574: 687b ldr r3, [r7, #4] 8004576: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8004578: 683b ldr r3, [r7, #0] 800457a: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800457c: 683b ldr r3, [r7, #0] 800457e: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8004580: 683b ldr r3, [r7, #0] 8004582: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8004584: f000 f9a6 bl 80048d4 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8004588: 687b ldr r3, [r7, #4] 800458a: 681b ldr r3, [r3, #0] 800458c: 689a ldr r2, [r3, #8] 800458e: 687b ldr r3, [r7, #4] 8004590: 681b ldr r3, [r3, #0] 8004592: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8004596: 609a str r2, [r3, #8] break; 8004598: e03c b.n 8004614 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800459a: 687b ldr r3, [r7, #4] 800459c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800459e: 683b ldr r3, [r7, #0] 80045a0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80045a2: 683b ldr r3, [r7, #0] 80045a4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80045a6: 461a mov r2, r3 80045a8: f000 f918 bl 80047dc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80045ac: 687b ldr r3, [r7, #4] 80045ae: 681b ldr r3, [r3, #0] 80045b0: 2150 movs r1, #80 @ 0x50 80045b2: 4618 mov r0, r3 80045b4: f000 f971 bl 800489a break; 80045b8: e02c b.n 8004614 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80045ba: 687b ldr r3, [r7, #4] 80045bc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80045be: 683b ldr r3, [r7, #0] 80045c0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80045c2: 683b ldr r3, [r7, #0] 80045c4: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80045c6: 461a mov r2, r3 80045c8: f000 f937 bl 800483a TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80045cc: 687b ldr r3, [r7, #4] 80045ce: 681b ldr r3, [r3, #0] 80045d0: 2160 movs r1, #96 @ 0x60 80045d2: 4618 mov r0, r3 80045d4: f000 f961 bl 800489a break; 80045d8: e01c b.n 8004614 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80045da: 687b ldr r3, [r7, #4] 80045dc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80045de: 683b ldr r3, [r7, #0] 80045e0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80045e2: 683b ldr r3, [r7, #0] 80045e4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80045e6: 461a mov r2, r3 80045e8: f000 f8f8 bl 80047dc TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80045ec: 687b ldr r3, [r7, #4] 80045ee: 681b ldr r3, [r3, #0] 80045f0: 2140 movs r1, #64 @ 0x40 80045f2: 4618 mov r0, r3 80045f4: f000 f951 bl 800489a break; 80045f8: e00c b.n 8004614 case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80045fa: 687b ldr r3, [r7, #4] 80045fc: 681a ldr r2, [r3, #0] 80045fe: 683b ldr r3, [r7, #0] 8004600: 681b ldr r3, [r3, #0] 8004602: 4619 mov r1, r3 8004604: 4610 mov r0, r2 8004606: f000 f948 bl 800489a break; 800460a: e003 b.n 8004614 } default: status = HAL_ERROR; 800460c: 2301 movs r3, #1 800460e: 73fb strb r3, [r7, #15] break; 8004610: e000 b.n 8004614 break; 8004612: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8004614: 687b ldr r3, [r7, #4] 8004616: 2201 movs r2, #1 8004618: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800461c: 687b ldr r3, [r7, #4] 800461e: 2200 movs r2, #0 8004620: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8004624: 7bfb ldrb r3, [r7, #15] } 8004626: 4618 mov r0, r3 8004628: 3710 adds r7, #16 800462a: 46bd mov sp, r7 800462c: bd80 pop {r7, pc} 800462e: bf00 nop 8004630: 00100070 .word 0x00100070 8004634: 00100040 .word 0x00100040 8004638: 00100030 .word 0x00100030 800463c: 00100020 .word 0x00100020 08004640 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8004640: b480 push {r7} 8004642: b083 sub sp, #12 8004644: af00 add r7, sp, #0 8004646: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8004648: bf00 nop 800464a: 370c adds r7, #12 800464c: 46bd mov sp, r7 800464e: f85d 7b04 ldr.w r7, [sp], #4 8004652: 4770 bx lr 08004654 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8004654: b480 push {r7} 8004656: b083 sub sp, #12 8004658: af00 add r7, sp, #0 800465a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800465c: bf00 nop 800465e: 370c adds r7, #12 8004660: 46bd mov sp, r7 8004662: f85d 7b04 ldr.w r7, [sp], #4 8004666: 4770 bx lr 08004668 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8004668: b480 push {r7} 800466a: b083 sub sp, #12 800466c: af00 add r7, sp, #0 800466e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8004670: bf00 nop 8004672: 370c adds r7, #12 8004674: 46bd mov sp, r7 8004676: f85d 7b04 ldr.w r7, [sp], #4 800467a: 4770 bx lr 0800467c : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800467c: b480 push {r7} 800467e: b083 sub sp, #12 8004680: af00 add r7, sp, #0 8004682: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8004684: bf00 nop 8004686: 370c adds r7, #12 8004688: 46bd mov sp, r7 800468a: f85d 7b04 ldr.w r7, [sp], #4 800468e: 4770 bx lr 08004690 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8004690: b480 push {r7} 8004692: b083 sub sp, #12 8004694: af00 add r7, sp, #0 8004696: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8004698: bf00 nop 800469a: 370c adds r7, #12 800469c: 46bd mov sp, r7 800469e: f85d 7b04 ldr.w r7, [sp], #4 80046a2: 4770 bx lr 080046a4 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80046a4: b480 push {r7} 80046a6: b085 sub sp, #20 80046a8: af00 add r7, sp, #0 80046aa: 6078 str r0, [r7, #4] 80046ac: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80046ae: 687b ldr r3, [r7, #4] 80046b0: 681b ldr r3, [r3, #0] 80046b2: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80046b4: 687b ldr r3, [r7, #4] 80046b6: 4a42 ldr r2, [pc, #264] @ (80047c0 ) 80046b8: 4293 cmp r3, r2 80046ba: d00f beq.n 80046dc 80046bc: 687b ldr r3, [r7, #4] 80046be: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80046c2: d00b beq.n 80046dc 80046c4: 687b ldr r3, [r7, #4] 80046c6: 4a3f ldr r2, [pc, #252] @ (80047c4 ) 80046c8: 4293 cmp r3, r2 80046ca: d007 beq.n 80046dc 80046cc: 687b ldr r3, [r7, #4] 80046ce: 4a3e ldr r2, [pc, #248] @ (80047c8 ) 80046d0: 4293 cmp r3, r2 80046d2: d003 beq.n 80046dc 80046d4: 687b ldr r3, [r7, #4] 80046d6: 4a3d ldr r2, [pc, #244] @ (80047cc ) 80046d8: 4293 cmp r3, r2 80046da: d108 bne.n 80046ee { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80046dc: 68fb ldr r3, [r7, #12] 80046de: f023 0370 bic.w r3, r3, #112 @ 0x70 80046e2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80046e4: 683b ldr r3, [r7, #0] 80046e6: 685b ldr r3, [r3, #4] 80046e8: 68fa ldr r2, [r7, #12] 80046ea: 4313 orrs r3, r2 80046ec: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80046ee: 687b ldr r3, [r7, #4] 80046f0: 4a33 ldr r2, [pc, #204] @ (80047c0 ) 80046f2: 4293 cmp r3, r2 80046f4: d01b beq.n 800472e 80046f6: 687b ldr r3, [r7, #4] 80046f8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80046fc: d017 beq.n 800472e 80046fe: 687b ldr r3, [r7, #4] 8004700: 4a30 ldr r2, [pc, #192] @ (80047c4 ) 8004702: 4293 cmp r3, r2 8004704: d013 beq.n 800472e 8004706: 687b ldr r3, [r7, #4] 8004708: 4a2f ldr r2, [pc, #188] @ (80047c8 ) 800470a: 4293 cmp r3, r2 800470c: d00f beq.n 800472e 800470e: 687b ldr r3, [r7, #4] 8004710: 4a2e ldr r2, [pc, #184] @ (80047cc ) 8004712: 4293 cmp r3, r2 8004714: d00b beq.n 800472e 8004716: 687b ldr r3, [r7, #4] 8004718: 4a2d ldr r2, [pc, #180] @ (80047d0 ) 800471a: 4293 cmp r3, r2 800471c: d007 beq.n 800472e 800471e: 687b ldr r3, [r7, #4] 8004720: 4a2c ldr r2, [pc, #176] @ (80047d4 ) 8004722: 4293 cmp r3, r2 8004724: d003 beq.n 800472e 8004726: 687b ldr r3, [r7, #4] 8004728: 4a2b ldr r2, [pc, #172] @ (80047d8 ) 800472a: 4293 cmp r3, r2 800472c: d108 bne.n 8004740 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800472e: 68fb ldr r3, [r7, #12] 8004730: f423 7340 bic.w r3, r3, #768 @ 0x300 8004734: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8004736: 683b ldr r3, [r7, #0] 8004738: 68db ldr r3, [r3, #12] 800473a: 68fa ldr r2, [r7, #12] 800473c: 4313 orrs r3, r2 800473e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8004740: 68fb ldr r3, [r7, #12] 8004742: f023 0280 bic.w r2, r3, #128 @ 0x80 8004746: 683b ldr r3, [r7, #0] 8004748: 695b ldr r3, [r3, #20] 800474a: 4313 orrs r3, r2 800474c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800474e: 687b ldr r3, [r7, #4] 8004750: 68fa ldr r2, [r7, #12] 8004752: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8004754: 683b ldr r3, [r7, #0] 8004756: 689a ldr r2, [r3, #8] 8004758: 687b ldr r3, [r7, #4] 800475a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800475c: 683b ldr r3, [r7, #0] 800475e: 681a ldr r2, [r3, #0] 8004760: 687b ldr r3, [r7, #4] 8004762: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8004764: 687b ldr r3, [r7, #4] 8004766: 4a16 ldr r2, [pc, #88] @ (80047c0 ) 8004768: 4293 cmp r3, r2 800476a: d00f beq.n 800478c 800476c: 687b ldr r3, [r7, #4] 800476e: 4a17 ldr r2, [pc, #92] @ (80047cc ) 8004770: 4293 cmp r3, r2 8004772: d00b beq.n 800478c 8004774: 687b ldr r3, [r7, #4] 8004776: 4a16 ldr r2, [pc, #88] @ (80047d0 ) 8004778: 4293 cmp r3, r2 800477a: d007 beq.n 800478c 800477c: 687b ldr r3, [r7, #4] 800477e: 4a15 ldr r2, [pc, #84] @ (80047d4 ) 8004780: 4293 cmp r3, r2 8004782: d003 beq.n 800478c 8004784: 687b ldr r3, [r7, #4] 8004786: 4a14 ldr r2, [pc, #80] @ (80047d8 ) 8004788: 4293 cmp r3, r2 800478a: d103 bne.n 8004794 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800478c: 683b ldr r3, [r7, #0] 800478e: 691a ldr r2, [r3, #16] 8004790: 687b ldr r3, [r7, #4] 8004792: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8004794: 687b ldr r3, [r7, #4] 8004796: 2201 movs r2, #1 8004798: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 800479a: 687b ldr r3, [r7, #4] 800479c: 691b ldr r3, [r3, #16] 800479e: f003 0301 and.w r3, r3, #1 80047a2: 2b01 cmp r3, #1 80047a4: d105 bne.n 80047b2 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80047a6: 687b ldr r3, [r7, #4] 80047a8: 691b ldr r3, [r3, #16] 80047aa: f023 0201 bic.w r2, r3, #1 80047ae: 687b ldr r3, [r7, #4] 80047b0: 611a str r2, [r3, #16] } } 80047b2: bf00 nop 80047b4: 3714 adds r7, #20 80047b6: 46bd mov sp, r7 80047b8: f85d 7b04 ldr.w r7, [sp], #4 80047bc: 4770 bx lr 80047be: bf00 nop 80047c0: 40012c00 .word 0x40012c00 80047c4: 40000400 .word 0x40000400 80047c8: 40000800 .word 0x40000800 80047cc: 40013400 .word 0x40013400 80047d0: 40014000 .word 0x40014000 80047d4: 40014400 .word 0x40014400 80047d8: 40014800 .word 0x40014800 080047dc : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 80047dc: b480 push {r7} 80047de: b087 sub sp, #28 80047e0: af00 add r7, sp, #0 80047e2: 60f8 str r0, [r7, #12] 80047e4: 60b9 str r1, [r7, #8] 80047e6: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 80047e8: 68fb ldr r3, [r7, #12] 80047ea: 6a1b ldr r3, [r3, #32] 80047ec: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 80047ee: 68fb ldr r3, [r7, #12] 80047f0: 6a1b ldr r3, [r3, #32] 80047f2: f023 0201 bic.w r2, r3, #1 80047f6: 68fb ldr r3, [r7, #12] 80047f8: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80047fa: 68fb ldr r3, [r7, #12] 80047fc: 699b ldr r3, [r3, #24] 80047fe: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8004800: 693b ldr r3, [r7, #16] 8004802: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8004806: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8004808: 687b ldr r3, [r7, #4] 800480a: 011b lsls r3, r3, #4 800480c: 693a ldr r2, [r7, #16] 800480e: 4313 orrs r3, r2 8004810: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8004812: 697b ldr r3, [r7, #20] 8004814: f023 030a bic.w r3, r3, #10 8004818: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 800481a: 697a ldr r2, [r7, #20] 800481c: 68bb ldr r3, [r7, #8] 800481e: 4313 orrs r3, r2 8004820: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8004822: 68fb ldr r3, [r7, #12] 8004824: 693a ldr r2, [r7, #16] 8004826: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8004828: 68fb ldr r3, [r7, #12] 800482a: 697a ldr r2, [r7, #20] 800482c: 621a str r2, [r3, #32] } 800482e: bf00 nop 8004830: 371c adds r7, #28 8004832: 46bd mov sp, r7 8004834: f85d 7b04 ldr.w r7, [sp], #4 8004838: 4770 bx lr 0800483a : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 800483a: b480 push {r7} 800483c: b087 sub sp, #28 800483e: af00 add r7, sp, #0 8004840: 60f8 str r0, [r7, #12] 8004842: 60b9 str r1, [r7, #8] 8004844: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8004846: 68fb ldr r3, [r7, #12] 8004848: 6a1b ldr r3, [r3, #32] 800484a: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 800484c: 68fb ldr r3, [r7, #12] 800484e: 6a1b ldr r3, [r3, #32] 8004850: f023 0210 bic.w r2, r3, #16 8004854: 68fb ldr r3, [r7, #12] 8004856: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8004858: 68fb ldr r3, [r7, #12] 800485a: 699b ldr r3, [r3, #24] 800485c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 800485e: 693b ldr r3, [r7, #16] 8004860: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8004864: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8004866: 687b ldr r3, [r7, #4] 8004868: 031b lsls r3, r3, #12 800486a: 693a ldr r2, [r7, #16] 800486c: 4313 orrs r3, r2 800486e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8004870: 697b ldr r3, [r7, #20] 8004872: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8004876: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8004878: 68bb ldr r3, [r7, #8] 800487a: 011b lsls r3, r3, #4 800487c: 697a ldr r2, [r7, #20] 800487e: 4313 orrs r3, r2 8004880: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8004882: 68fb ldr r3, [r7, #12] 8004884: 693a ldr r2, [r7, #16] 8004886: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8004888: 68fb ldr r3, [r7, #12] 800488a: 697a ldr r2, [r7, #20] 800488c: 621a str r2, [r3, #32] } 800488e: bf00 nop 8004890: 371c adds r7, #28 8004892: 46bd mov sp, r7 8004894: f85d 7b04 ldr.w r7, [sp], #4 8004898: 4770 bx lr 0800489a : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 800489a: b480 push {r7} 800489c: b085 sub sp, #20 800489e: af00 add r7, sp, #0 80048a0: 6078 str r0, [r7, #4] 80048a2: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80048a4: 687b ldr r3, [r7, #4] 80048a6: 689b ldr r3, [r3, #8] 80048a8: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80048aa: 68fb ldr r3, [r7, #12] 80048ac: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 80048b0: f023 0370 bic.w r3, r3, #112 @ 0x70 80048b4: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80048b6: 683a ldr r2, [r7, #0] 80048b8: 68fb ldr r3, [r7, #12] 80048ba: 4313 orrs r3, r2 80048bc: f043 0307 orr.w r3, r3, #7 80048c0: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80048c2: 687b ldr r3, [r7, #4] 80048c4: 68fa ldr r2, [r7, #12] 80048c6: 609a str r2, [r3, #8] } 80048c8: bf00 nop 80048ca: 3714 adds r7, #20 80048cc: 46bd mov sp, r7 80048ce: f85d 7b04 ldr.w r7, [sp], #4 80048d2: 4770 bx lr 080048d4 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80048d4: b480 push {r7} 80048d6: b087 sub sp, #28 80048d8: af00 add r7, sp, #0 80048da: 60f8 str r0, [r7, #12] 80048dc: 60b9 str r1, [r7, #8] 80048de: 607a str r2, [r7, #4] 80048e0: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80048e2: 68fb ldr r3, [r7, #12] 80048e4: 689b ldr r3, [r3, #8] 80048e6: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80048e8: 697b ldr r3, [r7, #20] 80048ea: f423 437f bic.w r3, r3, #65280 @ 0xff00 80048ee: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80048f0: 683b ldr r3, [r7, #0] 80048f2: 021a lsls r2, r3, #8 80048f4: 687b ldr r3, [r7, #4] 80048f6: 431a orrs r2, r3 80048f8: 68bb ldr r3, [r7, #8] 80048fa: 4313 orrs r3, r2 80048fc: 697a ldr r2, [r7, #20] 80048fe: 4313 orrs r3, r2 8004900: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8004902: 68fb ldr r3, [r7, #12] 8004904: 697a ldr r2, [r7, #20] 8004906: 609a str r2, [r3, #8] } 8004908: bf00 nop 800490a: 371c adds r7, #28 800490c: 46bd mov sp, r7 800490e: f85d 7b04 ldr.w r7, [sp], #4 8004912: 4770 bx lr 08004914 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8004914: b480 push {r7} 8004916: b085 sub sp, #20 8004918: af00 add r7, sp, #0 800491a: 6078 str r0, [r7, #4] 800491c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800491e: 687b ldr r3, [r7, #4] 8004920: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8004924: 2b01 cmp r3, #1 8004926: d101 bne.n 800492c 8004928: 2302 movs r3, #2 800492a: e065 b.n 80049f8 800492c: 687b ldr r3, [r7, #4] 800492e: 2201 movs r2, #1 8004930: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8004934: 687b ldr r3, [r7, #4] 8004936: 2202 movs r2, #2 8004938: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800493c: 687b ldr r3, [r7, #4] 800493e: 681b ldr r3, [r3, #0] 8004940: 685b ldr r3, [r3, #4] 8004942: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8004944: 687b ldr r3, [r7, #4] 8004946: 681b ldr r3, [r3, #0] 8004948: 689b ldr r3, [r3, #8] 800494a: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800494c: 687b ldr r3, [r7, #4] 800494e: 681b ldr r3, [r3, #0] 8004950: 4a2c ldr r2, [pc, #176] @ (8004a04 ) 8004952: 4293 cmp r3, r2 8004954: d004 beq.n 8004960 8004956: 687b ldr r3, [r7, #4] 8004958: 681b ldr r3, [r3, #0] 800495a: 4a2b ldr r2, [pc, #172] @ (8004a08 ) 800495c: 4293 cmp r3, r2 800495e: d108 bne.n 8004972 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 8004960: 68fb ldr r3, [r7, #12] 8004962: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8004966: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8004968: 683b ldr r3, [r7, #0] 800496a: 685b ldr r3, [r3, #4] 800496c: 68fa ldr r2, [r7, #12] 800496e: 4313 orrs r3, r2 8004970: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8004972: 68fb ldr r3, [r7, #12] 8004974: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000 8004978: f023 0370 bic.w r3, r3, #112 @ 0x70 800497c: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800497e: 683b ldr r3, [r7, #0] 8004980: 681b ldr r3, [r3, #0] 8004982: 68fa ldr r2, [r7, #12] 8004984: 4313 orrs r3, r2 8004986: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8004988: 687b ldr r3, [r7, #4] 800498a: 681b ldr r3, [r3, #0] 800498c: 68fa ldr r2, [r7, #12] 800498e: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8004990: 687b ldr r3, [r7, #4] 8004992: 681b ldr r3, [r3, #0] 8004994: 4a1b ldr r2, [pc, #108] @ (8004a04 ) 8004996: 4293 cmp r3, r2 8004998: d018 beq.n 80049cc 800499a: 687b ldr r3, [r7, #4] 800499c: 681b ldr r3, [r3, #0] 800499e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80049a2: d013 beq.n 80049cc 80049a4: 687b ldr r3, [r7, #4] 80049a6: 681b ldr r3, [r3, #0] 80049a8: 4a18 ldr r2, [pc, #96] @ (8004a0c ) 80049aa: 4293 cmp r3, r2 80049ac: d00e beq.n 80049cc 80049ae: 687b ldr r3, [r7, #4] 80049b0: 681b ldr r3, [r3, #0] 80049b2: 4a17 ldr r2, [pc, #92] @ (8004a10 ) 80049b4: 4293 cmp r3, r2 80049b6: d009 beq.n 80049cc 80049b8: 687b ldr r3, [r7, #4] 80049ba: 681b ldr r3, [r3, #0] 80049bc: 4a12 ldr r2, [pc, #72] @ (8004a08 ) 80049be: 4293 cmp r3, r2 80049c0: d004 beq.n 80049cc 80049c2: 687b ldr r3, [r7, #4] 80049c4: 681b ldr r3, [r3, #0] 80049c6: 4a13 ldr r2, [pc, #76] @ (8004a14 ) 80049c8: 4293 cmp r3, r2 80049ca: d10c bne.n 80049e6 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 80049cc: 68bb ldr r3, [r7, #8] 80049ce: f023 0380 bic.w r3, r3, #128 @ 0x80 80049d2: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 80049d4: 683b ldr r3, [r7, #0] 80049d6: 689b ldr r3, [r3, #8] 80049d8: 68ba ldr r2, [r7, #8] 80049da: 4313 orrs r3, r2 80049dc: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80049de: 687b ldr r3, [r7, #4] 80049e0: 681b ldr r3, [r3, #0] 80049e2: 68ba ldr r2, [r7, #8] 80049e4: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 80049e6: 687b ldr r3, [r7, #4] 80049e8: 2201 movs r2, #1 80049ea: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80049ee: 687b ldr r3, [r7, #4] 80049f0: 2200 movs r2, #0 80049f2: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 80049f6: 2300 movs r3, #0 } 80049f8: 4618 mov r0, r3 80049fa: 3714 adds r7, #20 80049fc: 46bd mov sp, r7 80049fe: f85d 7b04 ldr.w r7, [sp], #4 8004a02: 4770 bx lr 8004a04: 40012c00 .word 0x40012c00 8004a08: 40013400 .word 0x40013400 8004a0c: 40000400 .word 0x40000400 8004a10: 40000800 .word 0x40000800 8004a14: 40014000 .word 0x40014000 08004a18 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8004a18: b480 push {r7} 8004a1a: b083 sub sp, #12 8004a1c: af00 add r7, sp, #0 8004a1e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8004a20: bf00 nop 8004a22: 370c adds r7, #12 8004a24: 46bd mov sp, r7 8004a26: f85d 7b04 ldr.w r7, [sp], #4 8004a2a: 4770 bx lr 08004a2c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8004a2c: b480 push {r7} 8004a2e: b083 sub sp, #12 8004a30: af00 add r7, sp, #0 8004a32: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8004a34: bf00 nop 8004a36: 370c adds r7, #12 8004a38: 46bd mov sp, r7 8004a3a: f85d 7b04 ldr.w r7, [sp], #4 8004a3e: 4770 bx lr 08004a40 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8004a40: b480 push {r7} 8004a42: b083 sub sp, #12 8004a44: af00 add r7, sp, #0 8004a46: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8004a48: bf00 nop 8004a4a: 370c adds r7, #12 8004a4c: 46bd mov sp, r7 8004a4e: f85d 7b04 ldr.w r7, [sp], #4 8004a52: 4770 bx lr 08004a54 : * @brief Encoder index callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) { 8004a54: b480 push {r7} 8004a56: b083 sub sp, #12 8004a58: af00 add r7, sp, #0 8004a5a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file */ } 8004a5c: bf00 nop 8004a5e: 370c adds r7, #12 8004a60: 46bd mov sp, r7 8004a62: f85d 7b04 ldr.w r7, [sp], #4 8004a66: 4770 bx lr 08004a68 : * @brief Direction change callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) { 8004a68: b480 push {r7} 8004a6a: b083 sub sp, #12 8004a6c: af00 add r7, sp, #0 8004a6e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file */ } 8004a70: bf00 nop 8004a72: 370c adds r7, #12 8004a74: 46bd mov sp, r7 8004a76: f85d 7b04 ldr.w r7, [sp], #4 8004a7a: 4770 bx lr 08004a7c : * @brief Index error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) { 8004a7c: b480 push {r7} 8004a7e: b083 sub sp, #12 8004a80: af00 add r7, sp, #0 8004a82: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_IndexErrorCallback could be implemented in the user file */ } 8004a84: bf00 nop 8004a86: 370c adds r7, #12 8004a88: 46bd mov sp, r7 8004a8a: f85d 7b04 ldr.w r7, [sp], #4 8004a8e: 4770 bx lr 08004a90 : * @brief Transition error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) { 8004a90: b480 push {r7} 8004a92: b083 sub sp, #12 8004a94: af00 add r7, sp, #0 8004a96: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file */ } 8004a98: bf00 nop 8004a9a: 370c adds r7, #12 8004a9c: 46bd mov sp, r7 8004a9e: f85d 7b04 ldr.w r7, [sp], #4 8004aa2: 4770 bx lr 08004aa4 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8004aa4: b580 push {r7, lr} 8004aa6: b082 sub sp, #8 8004aa8: af00 add r7, sp, #0 8004aaa: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8004aac: 687b ldr r3, [r7, #4] 8004aae: 2b00 cmp r3, #0 8004ab0: d101 bne.n 8004ab6 { return HAL_ERROR; 8004ab2: 2301 movs r3, #1 8004ab4: e042 b.n 8004b3c { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8004ab6: 687b ldr r3, [r7, #4] 8004ab8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004abc: 2b00 cmp r3, #0 8004abe: d106 bne.n 8004ace { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8004ac0: 687b ldr r3, [r7, #4] 8004ac2: 2200 movs r2, #0 8004ac4: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8004ac8: 6878 ldr r0, [r7, #4] 8004aca: f7fc fa5d bl 8000f88 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8004ace: 687b ldr r3, [r7, #4] 8004ad0: 2224 movs r2, #36 @ 0x24 8004ad2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 8004ad6: 687b ldr r3, [r7, #4] 8004ad8: 681b ldr r3, [r3, #0] 8004ada: 681a ldr r2, [r3, #0] 8004adc: 687b ldr r3, [r7, #4] 8004ade: 681b ldr r3, [r3, #0] 8004ae0: f022 0201 bic.w r2, r2, #1 8004ae4: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8004ae6: 687b ldr r3, [r7, #4] 8004ae8: 6a9b ldr r3, [r3, #40] @ 0x28 8004aea: 2b00 cmp r3, #0 8004aec: d002 beq.n 8004af4 { UART_AdvFeatureConfig(huart); 8004aee: 6878 ldr r0, [r7, #4] 8004af0: f000 ff26 bl 8005940 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8004af4: 6878 ldr r0, [r7, #4] 8004af6: f000 fc57 bl 80053a8 8004afa: 4603 mov r3, r0 8004afc: 2b01 cmp r3, #1 8004afe: d101 bne.n 8004b04 { return HAL_ERROR; 8004b00: 2301 movs r3, #1 8004b02: e01b b.n 8004b3c } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8004b04: 687b ldr r3, [r7, #4] 8004b06: 681b ldr r3, [r3, #0] 8004b08: 685a ldr r2, [r3, #4] 8004b0a: 687b ldr r3, [r7, #4] 8004b0c: 681b ldr r3, [r3, #0] 8004b0e: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8004b12: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8004b14: 687b ldr r3, [r7, #4] 8004b16: 681b ldr r3, [r3, #0] 8004b18: 689a ldr r2, [r3, #8] 8004b1a: 687b ldr r3, [r7, #4] 8004b1c: 681b ldr r3, [r3, #0] 8004b1e: f022 022a bic.w r2, r2, #42 @ 0x2a 8004b22: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 8004b24: 687b ldr r3, [r7, #4] 8004b26: 681b ldr r3, [r3, #0] 8004b28: 681a ldr r2, [r3, #0] 8004b2a: 687b ldr r3, [r7, #4] 8004b2c: 681b ldr r3, [r3, #0] 8004b2e: f042 0201 orr.w r2, r2, #1 8004b32: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 8004b34: 6878 ldr r0, [r7, #4] 8004b36: f000 ffa5 bl 8005a84 8004b3a: 4603 mov r3, r0 } 8004b3c: 4618 mov r0, r3 8004b3e: 3708 adds r7, #8 8004b40: 46bd mov sp, r7 8004b42: bd80 pop {r7, pc} 08004b44 : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004b44: b580 push {r7, lr} 8004b46: b08a sub sp, #40 @ 0x28 8004b48: af02 add r7, sp, #8 8004b4a: 60f8 str r0, [r7, #12] 8004b4c: 60b9 str r1, [r7, #8] 8004b4e: 603b str r3, [r7, #0] 8004b50: 4613 mov r3, r2 8004b52: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8004b54: 68fb ldr r3, [r7, #12] 8004b56: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004b5a: 2b20 cmp r3, #32 8004b5c: d17b bne.n 8004c56 { if ((pData == NULL) || (Size == 0U)) 8004b5e: 68bb ldr r3, [r7, #8] 8004b60: 2b00 cmp r3, #0 8004b62: d002 beq.n 8004b6a 8004b64: 88fb ldrh r3, [r7, #6] 8004b66: 2b00 cmp r3, #0 8004b68: d101 bne.n 8004b6e { return HAL_ERROR; 8004b6a: 2301 movs r3, #1 8004b6c: e074 b.n 8004c58 } huart->ErrorCode = HAL_UART_ERROR_NONE; 8004b6e: 68fb ldr r3, [r7, #12] 8004b70: 2200 movs r2, #0 8004b72: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8004b76: 68fb ldr r3, [r7, #12] 8004b78: 2221 movs r2, #33 @ 0x21 8004b7a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8004b7e: f7fc fb47 bl 8001210 8004b82: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 8004b84: 68fb ldr r3, [r7, #12] 8004b86: 88fa ldrh r2, [r7, #6] 8004b88: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8004b8c: 68fb ldr r3, [r7, #12] 8004b8e: 88fa ldrh r2, [r7, #6] 8004b90: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8004b94: 68fb ldr r3, [r7, #12] 8004b96: 689b ldr r3, [r3, #8] 8004b98: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8004b9c: d108 bne.n 8004bb0 8004b9e: 68fb ldr r3, [r7, #12] 8004ba0: 691b ldr r3, [r3, #16] 8004ba2: 2b00 cmp r3, #0 8004ba4: d104 bne.n 8004bb0 { pdata8bits = NULL; 8004ba6: 2300 movs r3, #0 8004ba8: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8004baa: 68bb ldr r3, [r7, #8] 8004bac: 61bb str r3, [r7, #24] 8004bae: e003 b.n 8004bb8 } else { pdata8bits = pData; 8004bb0: 68bb ldr r3, [r7, #8] 8004bb2: 61fb str r3, [r7, #28] pdata16bits = NULL; 8004bb4: 2300 movs r3, #0 8004bb6: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8004bb8: e030 b.n 8004c1c { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8004bba: 683b ldr r3, [r7, #0] 8004bbc: 9300 str r3, [sp, #0] 8004bbe: 697b ldr r3, [r7, #20] 8004bc0: 2200 movs r2, #0 8004bc2: 2180 movs r1, #128 @ 0x80 8004bc4: 68f8 ldr r0, [r7, #12] 8004bc6: f001 f807 bl 8005bd8 8004bca: 4603 mov r3, r0 8004bcc: 2b00 cmp r3, #0 8004bce: d005 beq.n 8004bdc { huart->gState = HAL_UART_STATE_READY; 8004bd0: 68fb ldr r3, [r7, #12] 8004bd2: 2220 movs r2, #32 8004bd4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 8004bd8: 2303 movs r3, #3 8004bda: e03d b.n 8004c58 } if (pdata8bits == NULL) 8004bdc: 69fb ldr r3, [r7, #28] 8004bde: 2b00 cmp r3, #0 8004be0: d10b bne.n 8004bfa { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 8004be2: 69bb ldr r3, [r7, #24] 8004be4: 881b ldrh r3, [r3, #0] 8004be6: 461a mov r2, r3 8004be8: 68fb ldr r3, [r7, #12] 8004bea: 681b ldr r3, [r3, #0] 8004bec: f3c2 0208 ubfx r2, r2, #0, #9 8004bf0: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 8004bf2: 69bb ldr r3, [r7, #24] 8004bf4: 3302 adds r3, #2 8004bf6: 61bb str r3, [r7, #24] 8004bf8: e007 b.n 8004c0a } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 8004bfa: 69fb ldr r3, [r7, #28] 8004bfc: 781a ldrb r2, [r3, #0] 8004bfe: 68fb ldr r3, [r7, #12] 8004c00: 681b ldr r3, [r3, #0] 8004c02: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 8004c04: 69fb ldr r3, [r7, #28] 8004c06: 3301 adds r3, #1 8004c08: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8004c0a: 68fb ldr r3, [r7, #12] 8004c0c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8004c10: b29b uxth r3, r3 8004c12: 3b01 subs r3, #1 8004c14: b29a uxth r2, r3 8004c16: 68fb ldr r3, [r7, #12] 8004c18: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 while (huart->TxXferCount > 0U) 8004c1c: 68fb ldr r3, [r7, #12] 8004c1e: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8004c22: b29b uxth r3, r3 8004c24: 2b00 cmp r3, #0 8004c26: d1c8 bne.n 8004bba } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8004c28: 683b ldr r3, [r7, #0] 8004c2a: 9300 str r3, [sp, #0] 8004c2c: 697b ldr r3, [r7, #20] 8004c2e: 2200 movs r2, #0 8004c30: 2140 movs r1, #64 @ 0x40 8004c32: 68f8 ldr r0, [r7, #12] 8004c34: f000 ffd0 bl 8005bd8 8004c38: 4603 mov r3, r0 8004c3a: 2b00 cmp r3, #0 8004c3c: d005 beq.n 8004c4a { huart->gState = HAL_UART_STATE_READY; 8004c3e: 68fb ldr r3, [r7, #12] 8004c40: 2220 movs r2, #32 8004c42: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 8004c46: 2303 movs r3, #3 8004c48: e006 b.n 8004c58 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004c4a: 68fb ldr r3, [r7, #12] 8004c4c: 2220 movs r2, #32 8004c4e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_OK; 8004c52: 2300 movs r3, #0 8004c54: e000 b.n 8004c58 } else { return HAL_BUSY; 8004c56: 2302 movs r3, #2 } } 8004c58: 4618 mov r0, r3 8004c5a: 3720 adds r7, #32 8004c5c: 46bd mov sp, r7 8004c5e: bd80 pop {r7, pc} 08004c60 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8004c60: b580 push {r7, lr} 8004c62: b08a sub sp, #40 @ 0x28 8004c64: af00 add r7, sp, #0 8004c66: 60f8 str r0, [r7, #12] 8004c68: 60b9 str r1, [r7, #8] 8004c6a: 4613 mov r3, r2 8004c6c: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8004c6e: 68fb ldr r3, [r7, #12] 8004c70: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004c74: 2b20 cmp r3, #32 8004c76: d137 bne.n 8004ce8 { if ((pData == NULL) || (Size == 0U)) 8004c78: 68bb ldr r3, [r7, #8] 8004c7a: 2b00 cmp r3, #0 8004c7c: d002 beq.n 8004c84 8004c7e: 88fb ldrh r3, [r7, #6] 8004c80: 2b00 cmp r3, #0 8004c82: d101 bne.n 8004c88 { return HAL_ERROR; 8004c84: 2301 movs r3, #1 8004c86: e030 b.n 8004cea } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004c88: 68fb ldr r3, [r7, #12] 8004c8a: 2200 movs r2, #0 8004c8c: 66da str r2, [r3, #108] @ 0x6c if (!(IS_LPUART_INSTANCE(huart->Instance))) 8004c8e: 68fb ldr r3, [r7, #12] 8004c90: 681b ldr r3, [r3, #0] 8004c92: 4a18 ldr r2, [pc, #96] @ (8004cf4 ) 8004c94: 4293 cmp r3, r2 8004c96: d01f beq.n 8004cd8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8004c98: 68fb ldr r3, [r7, #12] 8004c9a: 681b ldr r3, [r3, #0] 8004c9c: 685b ldr r3, [r3, #4] 8004c9e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8004ca2: 2b00 cmp r3, #0 8004ca4: d018 beq.n 8004cd8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8004ca6: 68fb ldr r3, [r7, #12] 8004ca8: 681b ldr r3, [r3, #0] 8004caa: 617b str r3, [r7, #20] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004cac: 697b ldr r3, [r7, #20] 8004cae: e853 3f00 ldrex r3, [r3] 8004cb2: 613b str r3, [r7, #16] return(result); 8004cb4: 693b ldr r3, [r7, #16] 8004cb6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8004cba: 627b str r3, [r7, #36] @ 0x24 8004cbc: 68fb ldr r3, [r7, #12] 8004cbe: 681b ldr r3, [r3, #0] 8004cc0: 461a mov r2, r3 8004cc2: 6a7b ldr r3, [r7, #36] @ 0x24 8004cc4: 623b str r3, [r7, #32] 8004cc6: 61fa str r2, [r7, #28] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004cc8: 69f9 ldr r1, [r7, #28] 8004cca: 6a3a ldr r2, [r7, #32] 8004ccc: e841 2300 strex r3, r2, [r1] 8004cd0: 61bb str r3, [r7, #24] return(result); 8004cd2: 69bb ldr r3, [r7, #24] 8004cd4: 2b00 cmp r3, #0 8004cd6: d1e6 bne.n 8004ca6 } } return (UART_Start_Receive_IT(huart, pData, Size)); 8004cd8: 88fb ldrh r3, [r7, #6] 8004cda: 461a mov r2, r3 8004cdc: 68b9 ldr r1, [r7, #8] 8004cde: 68f8 ldr r0, [r7, #12] 8004ce0: f000 ffe8 bl 8005cb4 8004ce4: 4603 mov r3, r0 8004ce6: e000 b.n 8004cea } else { return HAL_BUSY; 8004ce8: 2302 movs r3, #2 } } 8004cea: 4618 mov r0, r3 8004cec: 3728 adds r7, #40 @ 0x28 8004cee: 46bd mov sp, r7 8004cf0: bd80 pop {r7, pc} 8004cf2: bf00 nop 8004cf4: 40008000 .word 0x40008000 08004cf8 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8004cf8: b580 push {r7, lr} 8004cfa: b0ba sub sp, #232 @ 0xe8 8004cfc: af00 add r7, sp, #0 8004cfe: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8004d00: 687b ldr r3, [r7, #4] 8004d02: 681b ldr r3, [r3, #0] 8004d04: 69db ldr r3, [r3, #28] 8004d06: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8004d0a: 687b ldr r3, [r7, #4] 8004d0c: 681b ldr r3, [r3, #0] 8004d0e: 681b ldr r3, [r3, #0] 8004d10: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8004d14: 687b ldr r3, [r7, #4] 8004d16: 681b ldr r3, [r3, #0] 8004d18: 689b ldr r3, [r3, #8] 8004d1a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 8004d1e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 8004d22: f640 030f movw r3, #2063 @ 0x80f 8004d26: 4013 ands r3, r2 8004d28: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8004d2c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8004d30: 2b00 cmp r3, #0 8004d32: d11b bne.n 8004d6c { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8004d34: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004d38: f003 0320 and.w r3, r3, #32 8004d3c: 2b00 cmp r3, #0 8004d3e: d015 beq.n 8004d6c && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8004d40: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8004d44: f003 0320 and.w r3, r3, #32 8004d48: 2b00 cmp r3, #0 8004d4a: d105 bne.n 8004d58 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8004d4c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8004d50: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004d54: 2b00 cmp r3, #0 8004d56: d009 beq.n 8004d6c { if (huart->RxISR != NULL) 8004d58: 687b ldr r3, [r7, #4] 8004d5a: 6f5b ldr r3, [r3, #116] @ 0x74 8004d5c: 2b00 cmp r3, #0 8004d5e: f000 8300 beq.w 8005362 { huart->RxISR(huart); 8004d62: 687b ldr r3, [r7, #4] 8004d64: 6f5b ldr r3, [r3, #116] @ 0x74 8004d66: 6878 ldr r0, [r7, #4] 8004d68: 4798 blx r3 } return; 8004d6a: e2fa b.n 8005362 } } /* If some errors occur */ if ((errorflags != 0U) 8004d6c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8004d70: 2b00 cmp r3, #0 8004d72: f000 8123 beq.w 8004fbc && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8004d76: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8004d7a: 4b8d ldr r3, [pc, #564] @ (8004fb0 ) 8004d7c: 4013 ands r3, r2 8004d7e: 2b00 cmp r3, #0 8004d80: d106 bne.n 8004d90 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8004d82: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8004d86: 4b8b ldr r3, [pc, #556] @ (8004fb4 ) 8004d88: 4013 ands r3, r2 8004d8a: 2b00 cmp r3, #0 8004d8c: f000 8116 beq.w 8004fbc { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8004d90: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004d94: f003 0301 and.w r3, r3, #1 8004d98: 2b00 cmp r3, #0 8004d9a: d011 beq.n 8004dc0 8004d9c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8004da0: f403 7380 and.w r3, r3, #256 @ 0x100 8004da4: 2b00 cmp r3, #0 8004da6: d00b beq.n 8004dc0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8004da8: 687b ldr r3, [r7, #4] 8004daa: 681b ldr r3, [r3, #0] 8004dac: 2201 movs r2, #1 8004dae: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8004db0: 687b ldr r3, [r7, #4] 8004db2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004db6: f043 0201 orr.w r2, r3, #1 8004dba: 687b ldr r3, [r7, #4] 8004dbc: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004dc0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004dc4: f003 0302 and.w r3, r3, #2 8004dc8: 2b00 cmp r3, #0 8004dca: d011 beq.n 8004df0 8004dcc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8004dd0: f003 0301 and.w r3, r3, #1 8004dd4: 2b00 cmp r3, #0 8004dd6: d00b beq.n 8004df0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8004dd8: 687b ldr r3, [r7, #4] 8004dda: 681b ldr r3, [r3, #0] 8004ddc: 2202 movs r2, #2 8004dde: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8004de0: 687b ldr r3, [r7, #4] 8004de2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004de6: f043 0204 orr.w r2, r3, #4 8004dea: 687b ldr r3, [r7, #4] 8004dec: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8004df0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004df4: f003 0304 and.w r3, r3, #4 8004df8: 2b00 cmp r3, #0 8004dfa: d011 beq.n 8004e20 8004dfc: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8004e00: f003 0301 and.w r3, r3, #1 8004e04: 2b00 cmp r3, #0 8004e06: d00b beq.n 8004e20 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8004e08: 687b ldr r3, [r7, #4] 8004e0a: 681b ldr r3, [r3, #0] 8004e0c: 2204 movs r2, #4 8004e0e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8004e10: 687b ldr r3, [r7, #4] 8004e12: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004e16: f043 0202 orr.w r2, r3, #2 8004e1a: 687b ldr r3, [r7, #4] 8004e1c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 8004e20: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004e24: f003 0308 and.w r3, r3, #8 8004e28: 2b00 cmp r3, #0 8004e2a: d017 beq.n 8004e5c && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8004e2c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8004e30: f003 0320 and.w r3, r3, #32 8004e34: 2b00 cmp r3, #0 8004e36: d105 bne.n 8004e44 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 8004e38: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8004e3c: 4b5c ldr r3, [pc, #368] @ (8004fb0 ) 8004e3e: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8004e40: 2b00 cmp r3, #0 8004e42: d00b beq.n 8004e5c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8004e44: 687b ldr r3, [r7, #4] 8004e46: 681b ldr r3, [r3, #0] 8004e48: 2208 movs r2, #8 8004e4a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 8004e4c: 687b ldr r3, [r7, #4] 8004e4e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004e52: f043 0208 orr.w r2, r3, #8 8004e56: 687b ldr r3, [r7, #4] 8004e58: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 8004e5c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004e60: f403 6300 and.w r3, r3, #2048 @ 0x800 8004e64: 2b00 cmp r3, #0 8004e66: d012 beq.n 8004e8e 8004e68: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8004e6c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8004e70: 2b00 cmp r3, #0 8004e72: d00c beq.n 8004e8e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8004e74: 687b ldr r3, [r7, #4] 8004e76: 681b ldr r3, [r3, #0] 8004e78: f44f 6200 mov.w r2, #2048 @ 0x800 8004e7c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8004e7e: 687b ldr r3, [r7, #4] 8004e80: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004e84: f043 0220 orr.w r2, r3, #32 8004e88: 687b ldr r3, [r7, #4] 8004e8a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8004e8e: 687b ldr r3, [r7, #4] 8004e90: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004e94: 2b00 cmp r3, #0 8004e96: f000 8266 beq.w 8005366 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8004e9a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004e9e: f003 0320 and.w r3, r3, #32 8004ea2: 2b00 cmp r3, #0 8004ea4: d013 beq.n 8004ece && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8004ea6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8004eaa: f003 0320 and.w r3, r3, #32 8004eae: 2b00 cmp r3, #0 8004eb0: d105 bne.n 8004ebe || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8004eb2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8004eb6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8004eba: 2b00 cmp r3, #0 8004ebc: d007 beq.n 8004ece { if (huart->RxISR != NULL) 8004ebe: 687b ldr r3, [r7, #4] 8004ec0: 6f5b ldr r3, [r3, #116] @ 0x74 8004ec2: 2b00 cmp r3, #0 8004ec4: d003 beq.n 8004ece { huart->RxISR(huart); 8004ec6: 687b ldr r3, [r7, #4] 8004ec8: 6f5b ldr r3, [r3, #116] @ 0x74 8004eca: 6878 ldr r0, [r7, #4] 8004ecc: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8004ece: 687b ldr r3, [r7, #4] 8004ed0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8004ed4: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8004ed8: 687b ldr r3, [r7, #4] 8004eda: 681b ldr r3, [r3, #0] 8004edc: 689b ldr r3, [r3, #8] 8004ede: f003 0340 and.w r3, r3, #64 @ 0x40 8004ee2: 2b40 cmp r3, #64 @ 0x40 8004ee4: d005 beq.n 8004ef2 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8004ee6: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8004eea: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8004eee: 2b00 cmp r3, #0 8004ef0: d054 beq.n 8004f9c { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8004ef2: 6878 ldr r0, [r7, #4] 8004ef4: f001 f800 bl 8005ef8 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004ef8: 687b ldr r3, [r7, #4] 8004efa: 681b ldr r3, [r3, #0] 8004efc: 689b ldr r3, [r3, #8] 8004efe: f003 0340 and.w r3, r3, #64 @ 0x40 8004f02: 2b40 cmp r3, #64 @ 0x40 8004f04: d146 bne.n 8004f94 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8004f06: 687b ldr r3, [r7, #4] 8004f08: 681b ldr r3, [r3, #0] 8004f0a: 3308 adds r3, #8 8004f0c: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8004f10: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8004f14: e853 3f00 ldrex r3, [r3] 8004f18: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8004f1c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8004f20: f023 0340 bic.w r3, r3, #64 @ 0x40 8004f24: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8004f28: 687b ldr r3, [r7, #4] 8004f2a: 681b ldr r3, [r3, #0] 8004f2c: 3308 adds r3, #8 8004f2e: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8004f32: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8004f36: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8004f3a: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8004f3e: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8004f42: e841 2300 strex r3, r2, [r1] 8004f46: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8004f4a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8004f4e: 2b00 cmp r3, #0 8004f50: d1d9 bne.n 8004f06 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8004f52: 687b ldr r3, [r7, #4] 8004f54: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8004f58: 2b00 cmp r3, #0 8004f5a: d017 beq.n 8004f8c { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8004f5c: 687b ldr r3, [r7, #4] 8004f5e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8004f62: 4a15 ldr r2, [pc, #84] @ (8004fb8 ) 8004f64: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8004f66: 687b ldr r3, [r7, #4] 8004f68: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8004f6c: 4618 mov r0, r3 8004f6e: f7fd fef3 bl 8002d58 8004f72: 4603 mov r3, r0 8004f74: 2b00 cmp r3, #0 8004f76: d019 beq.n 8004fac { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8004f78: 687b ldr r3, [r7, #4] 8004f7a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8004f7e: 6b9b ldr r3, [r3, #56] @ 0x38 8004f80: 687a ldr r2, [r7, #4] 8004f82: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8004f86: 4610 mov r0, r2 8004f88: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004f8a: e00f b.n 8004fac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004f8c: 6878 ldr r0, [r7, #4] 8004f8e: f000 f9f5 bl 800537c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004f92: e00b b.n 8004fac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004f94: 6878 ldr r0, [r7, #4] 8004f96: f000 f9f1 bl 800537c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004f9a: e007 b.n 8004fac #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8004f9c: 6878 ldr r0, [r7, #4] 8004f9e: f000 f9ed bl 800537c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004fa2: 687b ldr r3, [r7, #4] 8004fa4: 2200 movs r2, #0 8004fa6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8004faa: e1dc b.n 8005366 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004fac: bf00 nop return; 8004fae: e1da b.n 8005366 8004fb0: 10000001 .word 0x10000001 8004fb4: 04000120 .word 0x04000120 8004fb8: 08005fc5 .word 0x08005fc5 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004fbc: 687b ldr r3, [r7, #4] 8004fbe: 6edb ldr r3, [r3, #108] @ 0x6c 8004fc0: 2b01 cmp r3, #1 8004fc2: f040 8170 bne.w 80052a6 && ((isrflags & USART_ISR_IDLE) != 0U) 8004fc6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8004fca: f003 0310 and.w r3, r3, #16 8004fce: 2b00 cmp r3, #0 8004fd0: f000 8169 beq.w 80052a6 && ((cr1its & USART_ISR_IDLE) != 0U)) 8004fd4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8004fd8: f003 0310 and.w r3, r3, #16 8004fdc: 2b00 cmp r3, #0 8004fde: f000 8162 beq.w 80052a6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8004fe2: 687b ldr r3, [r7, #4] 8004fe4: 681b ldr r3, [r3, #0] 8004fe6: 2210 movs r2, #16 8004fe8: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8004fea: 687b ldr r3, [r7, #4] 8004fec: 681b ldr r3, [r3, #0] 8004fee: 689b ldr r3, [r3, #8] 8004ff0: f003 0340 and.w r3, r3, #64 @ 0x40 8004ff4: 2b40 cmp r3, #64 @ 0x40 8004ff6: f040 80d8 bne.w 80051aa { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8004ffa: 687b ldr r3, [r7, #4] 8004ffc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005000: 681b ldr r3, [r3, #0] 8005002: 685b ldr r3, [r3, #4] 8005004: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8005008: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 800500c: 2b00 cmp r3, #0 800500e: f000 80af beq.w 8005170 && (nb_remaining_rx_data < huart->RxXferSize)) 8005012: 687b ldr r3, [r7, #4] 8005014: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8005018: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800501c: 429a cmp r2, r3 800501e: f080 80a7 bcs.w 8005170 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8005022: 687b ldr r3, [r7, #4] 8005024: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8005028: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) 800502c: 687b ldr r3, [r7, #4] 800502e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005032: 681b ldr r3, [r3, #0] 8005034: 681b ldr r3, [r3, #0] 8005036: f003 0320 and.w r3, r3, #32 800503a: 2b00 cmp r3, #0 800503c: f040 8087 bne.w 800514e { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005040: 687b ldr r3, [r7, #4] 8005042: 681b ldr r3, [r3, #0] 8005044: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005048: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800504c: e853 3f00 ldrex r3, [r3] 8005050: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8005054: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005058: f423 7380 bic.w r3, r3, #256 @ 0x100 800505c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005060: 687b ldr r3, [r7, #4] 8005062: 681b ldr r3, [r3, #0] 8005064: 461a mov r2, r3 8005066: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 800506a: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800506e: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005072: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8005076: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800507a: e841 2300 strex r3, r2, [r1] 800507e: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8005082: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005086: 2b00 cmp r3, #0 8005088: d1da bne.n 8005040 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800508a: 687b ldr r3, [r7, #4] 800508c: 681b ldr r3, [r3, #0] 800508e: 3308 adds r3, #8 8005090: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005092: 6f7b ldr r3, [r7, #116] @ 0x74 8005094: e853 3f00 ldrex r3, [r3] 8005098: 673b str r3, [r7, #112] @ 0x70 return(result); 800509a: 6f3b ldr r3, [r7, #112] @ 0x70 800509c: f023 0301 bic.w r3, r3, #1 80050a0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 80050a4: 687b ldr r3, [r7, #4] 80050a6: 681b ldr r3, [r3, #0] 80050a8: 3308 adds r3, #8 80050aa: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 80050ae: f8c7 2080 str.w r2, [r7, #128] @ 0x80 80050b2: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80050b4: 6ff9 ldr r1, [r7, #124] @ 0x7c 80050b6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 80050ba: e841 2300 strex r3, r2, [r1] 80050be: 67bb str r3, [r7, #120] @ 0x78 return(result); 80050c0: 6fbb ldr r3, [r7, #120] @ 0x78 80050c2: 2b00 cmp r3, #0 80050c4: d1e1 bne.n 800508a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80050c6: 687b ldr r3, [r7, #4] 80050c8: 681b ldr r3, [r3, #0] 80050ca: 3308 adds r3, #8 80050cc: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80050ce: 6e3b ldr r3, [r7, #96] @ 0x60 80050d0: e853 3f00 ldrex r3, [r3] 80050d4: 65fb str r3, [r7, #92] @ 0x5c return(result); 80050d6: 6dfb ldr r3, [r7, #92] @ 0x5c 80050d8: f023 0340 bic.w r3, r3, #64 @ 0x40 80050dc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 80050e0: 687b ldr r3, [r7, #4] 80050e2: 681b ldr r3, [r3, #0] 80050e4: 3308 adds r3, #8 80050e6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 80050ea: 66fa str r2, [r7, #108] @ 0x6c 80050ec: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80050ee: 6eb9 ldr r1, [r7, #104] @ 0x68 80050f0: 6efa ldr r2, [r7, #108] @ 0x6c 80050f2: e841 2300 strex r3, r2, [r1] 80050f6: 667b str r3, [r7, #100] @ 0x64 return(result); 80050f8: 6e7b ldr r3, [r7, #100] @ 0x64 80050fa: 2b00 cmp r3, #0 80050fc: d1e3 bne.n 80050c6 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80050fe: 687b ldr r3, [r7, #4] 8005100: 2220 movs r2, #32 8005102: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005106: 687b ldr r3, [r7, #4] 8005108: 2200 movs r2, #0 800510a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800510c: 687b ldr r3, [r7, #4] 800510e: 681b ldr r3, [r3, #0] 8005110: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005112: 6cfb ldr r3, [r7, #76] @ 0x4c 8005114: e853 3f00 ldrex r3, [r3] 8005118: 64bb str r3, [r7, #72] @ 0x48 return(result); 800511a: 6cbb ldr r3, [r7, #72] @ 0x48 800511c: f023 0310 bic.w r3, r3, #16 8005120: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8005124: 687b ldr r3, [r7, #4] 8005126: 681b ldr r3, [r3, #0] 8005128: 461a mov r2, r3 800512a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800512e: 65bb str r3, [r7, #88] @ 0x58 8005130: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005132: 6d79 ldr r1, [r7, #84] @ 0x54 8005134: 6dba ldr r2, [r7, #88] @ 0x58 8005136: e841 2300 strex r3, r2, [r1] 800513a: 653b str r3, [r7, #80] @ 0x50 return(result); 800513c: 6d3b ldr r3, [r7, #80] @ 0x50 800513e: 2b00 cmp r3, #0 8005140: d1e4 bne.n 800510c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8005142: 687b ldr r3, [r7, #4] 8005144: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005148: 4618 mov r0, r3 800514a: f7fd fdac bl 8002ca6 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800514e: 687b ldr r3, [r7, #4] 8005150: 2202 movs r2, #2 8005152: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8005154: 687b ldr r3, [r7, #4] 8005156: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 800515a: 687b ldr r3, [r7, #4] 800515c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8005160: b29b uxth r3, r3 8005162: 1ad3 subs r3, r2, r3 8005164: b29b uxth r3, r3 8005166: 4619 mov r1, r3 8005168: 6878 ldr r0, [r7, #4] 800516a: f000 f911 bl 8005390 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; 800516e: e0fc b.n 800536a if (nb_remaining_rx_data == huart->RxXferSize) 8005170: 687b ldr r3, [r7, #4] 8005172: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8005176: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 800517a: 429a cmp r2, r3 800517c: f040 80f5 bne.w 800536a if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) 8005180: 687b ldr r3, [r7, #4] 8005182: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8005186: 681b ldr r3, [r3, #0] 8005188: 681b ldr r3, [r3, #0] 800518a: f003 0320 and.w r3, r3, #32 800518e: 2b20 cmp r3, #32 8005190: f040 80eb bne.w 800536a huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005194: 687b ldr r3, [r7, #4] 8005196: 2202 movs r2, #2 8005198: 671a str r2, [r3, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800519a: 687b ldr r3, [r7, #4] 800519c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80051a0: 4619 mov r1, r3 80051a2: 6878 ldr r0, [r7, #4] 80051a4: f000 f8f4 bl 8005390 return; 80051a8: e0df b.n 800536a else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 80051aa: 687b ldr r3, [r7, #4] 80051ac: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 80051b0: 687b ldr r3, [r7, #4] 80051b2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80051b6: b29b uxth r3, r3 80051b8: 1ad3 subs r3, r2, r3 80051ba: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 80051be: 687b ldr r3, [r7, #4] 80051c0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80051c4: b29b uxth r3, r3 80051c6: 2b00 cmp r3, #0 80051c8: f000 80d1 beq.w 800536e && (nb_rx_data > 0U)) 80051cc: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 80051d0: 2b00 cmp r3, #0 80051d2: f000 80cc beq.w 800536e { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80051d6: 687b ldr r3, [r7, #4] 80051d8: 681b ldr r3, [r3, #0] 80051da: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80051dc: 6bbb ldr r3, [r7, #56] @ 0x38 80051de: e853 3f00 ldrex r3, [r3] 80051e2: 637b str r3, [r7, #52] @ 0x34 return(result); 80051e4: 6b7b ldr r3, [r7, #52] @ 0x34 80051e6: f423 7390 bic.w r3, r3, #288 @ 0x120 80051ea: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 80051ee: 687b ldr r3, [r7, #4] 80051f0: 681b ldr r3, [r3, #0] 80051f2: 461a mov r2, r3 80051f4: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 80051f8: 647b str r3, [r7, #68] @ 0x44 80051fa: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80051fc: 6c39 ldr r1, [r7, #64] @ 0x40 80051fe: 6c7a ldr r2, [r7, #68] @ 0x44 8005200: e841 2300 strex r3, r2, [r1] 8005204: 63fb str r3, [r7, #60] @ 0x3c return(result); 8005206: 6bfb ldr r3, [r7, #60] @ 0x3c 8005208: 2b00 cmp r3, #0 800520a: d1e4 bne.n 80051d6 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800520c: 687b ldr r3, [r7, #4] 800520e: 681b ldr r3, [r3, #0] 8005210: 3308 adds r3, #8 8005212: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005214: 6a7b ldr r3, [r7, #36] @ 0x24 8005216: e853 3f00 ldrex r3, [r3] 800521a: 623b str r3, [r7, #32] return(result); 800521c: 6a3b ldr r3, [r7, #32] 800521e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005222: f023 0301 bic.w r3, r3, #1 8005226: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800522a: 687b ldr r3, [r7, #4] 800522c: 681b ldr r3, [r3, #0] 800522e: 3308 adds r3, #8 8005230: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8005234: 633a str r2, [r7, #48] @ 0x30 8005236: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005238: 6af9 ldr r1, [r7, #44] @ 0x2c 800523a: 6b3a ldr r2, [r7, #48] @ 0x30 800523c: e841 2300 strex r3, r2, [r1] 8005240: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005242: 6abb ldr r3, [r7, #40] @ 0x28 8005244: 2b00 cmp r3, #0 8005246: d1e1 bne.n 800520c /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005248: 687b ldr r3, [r7, #4] 800524a: 2220 movs r2, #32 800524c: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005250: 687b ldr r3, [r7, #4] 8005252: 2200 movs r2, #0 8005254: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8005256: 687b ldr r3, [r7, #4] 8005258: 2200 movs r2, #0 800525a: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800525c: 687b ldr r3, [r7, #4] 800525e: 681b ldr r3, [r3, #0] 8005260: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005262: 693b ldr r3, [r7, #16] 8005264: e853 3f00 ldrex r3, [r3] 8005268: 60fb str r3, [r7, #12] return(result); 800526a: 68fb ldr r3, [r7, #12] 800526c: f023 0310 bic.w r3, r3, #16 8005270: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8005274: 687b ldr r3, [r7, #4] 8005276: 681b ldr r3, [r3, #0] 8005278: 461a mov r2, r3 800527a: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 800527e: 61fb str r3, [r7, #28] 8005280: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005282: 69b9 ldr r1, [r7, #24] 8005284: 69fa ldr r2, [r7, #28] 8005286: e841 2300 strex r3, r2, [r1] 800528a: 617b str r3, [r7, #20] return(result); 800528c: 697b ldr r3, [r7, #20] 800528e: 2b00 cmp r3, #0 8005290: d1e4 bne.n 800525c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8005292: 687b ldr r3, [r7, #4] 8005294: 2202 movs r2, #2 8005296: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8005298: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 800529c: 4619 mov r1, r3 800529e: 6878 ldr r0, [r7, #4] 80052a0: f000 f876 bl 8005390 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 80052a4: e063 b.n 800536e } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 80052a6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80052aa: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80052ae: 2b00 cmp r3, #0 80052b0: d00e beq.n 80052d0 80052b2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80052b6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80052ba: 2b00 cmp r3, #0 80052bc: d008 beq.n 80052d0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 80052be: 687b ldr r3, [r7, #4] 80052c0: 681b ldr r3, [r3, #0] 80052c2: f44f 1280 mov.w r2, #1048576 @ 0x100000 80052c6: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 80052c8: 6878 ldr r0, [r7, #4] 80052ca: f001 fbd9 bl 8006a80 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80052ce: e051 b.n 8005374 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 80052d0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80052d4: f003 0380 and.w r3, r3, #128 @ 0x80 80052d8: 2b00 cmp r3, #0 80052da: d014 beq.n 8005306 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 80052dc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80052e0: f003 0380 and.w r3, r3, #128 @ 0x80 80052e4: 2b00 cmp r3, #0 80052e6: d105 bne.n 80052f4 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 80052e8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80052ec: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80052f0: 2b00 cmp r3, #0 80052f2: d008 beq.n 8005306 { if (huart->TxISR != NULL) 80052f4: 687b ldr r3, [r7, #4] 80052f6: 6f9b ldr r3, [r3, #120] @ 0x78 80052f8: 2b00 cmp r3, #0 80052fa: d03a beq.n 8005372 { huart->TxISR(huart); 80052fc: 687b ldr r3, [r7, #4] 80052fe: 6f9b ldr r3, [r3, #120] @ 0x78 8005300: 6878 ldr r0, [r7, #4] 8005302: 4798 blx r3 } return; 8005304: e035 b.n 8005372 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8005306: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800530a: f003 0340 and.w r3, r3, #64 @ 0x40 800530e: 2b00 cmp r3, #0 8005310: d009 beq.n 8005326 8005312: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005316: f003 0340 and.w r3, r3, #64 @ 0x40 800531a: 2b00 cmp r3, #0 800531c: d003 beq.n 8005326 { UART_EndTransmit_IT(huart); 800531e: 6878 ldr r0, [r7, #4] 8005320: f000 fe62 bl 8005fe8 return; 8005324: e026 b.n 8005374 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8005326: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800532a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800532e: 2b00 cmp r3, #0 8005330: d009 beq.n 8005346 8005332: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005336: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 800533a: 2b00 cmp r3, #0 800533c: d003 beq.n 8005346 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 800533e: 6878 ldr r0, [r7, #4] 8005340: f001 fbb2 bl 8006aa8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8005344: e016 b.n 8005374 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8005346: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 800534a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800534e: 2b00 cmp r3, #0 8005350: d010 beq.n 8005374 8005352: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8005356: 2b00 cmp r3, #0 8005358: da0c bge.n 8005374 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 800535a: 6878 ldr r0, [r7, #4] 800535c: f001 fb9a bl 8006a94 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8005360: e008 b.n 8005374 return; 8005362: bf00 nop 8005364: e006 b.n 8005374 return; 8005366: bf00 nop 8005368: e004 b.n 8005374 return; 800536a: bf00 nop 800536c: e002 b.n 8005374 return; 800536e: bf00 nop 8005370: e000 b.n 8005374 return; 8005372: bf00 nop } } 8005374: 37e8 adds r7, #232 @ 0xe8 8005376: 46bd mov sp, r7 8005378: bd80 pop {r7, pc} 800537a: bf00 nop 0800537c : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 800537c: b480 push {r7} 800537e: b083 sub sp, #12 8005380: af00 add r7, sp, #0 8005382: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8005384: bf00 nop 8005386: 370c adds r7, #12 8005388: 46bd mov sp, r7 800538a: f85d 7b04 ldr.w r7, [sp], #4 800538e: 4770 bx lr 08005390 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8005390: b480 push {r7} 8005392: b083 sub sp, #12 8005394: af00 add r7, sp, #0 8005396: 6078 str r0, [r7, #4] 8005398: 460b mov r3, r1 800539a: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } 800539c: bf00 nop 800539e: 370c adds r7, #12 80053a0: 46bd mov sp, r7 80053a2: f85d 7b04 ldr.w r7, [sp], #4 80053a6: 4770 bx lr 080053a8 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 80053a8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80053ac: b08c sub sp, #48 @ 0x30 80053ae: af00 add r7, sp, #0 80053b0: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 80053b2: 2300 movs r3, #0 80053b4: f887 302a strb.w r3, [r7, #42] @ 0x2a * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 80053b8: 697b ldr r3, [r7, #20] 80053ba: 689a ldr r2, [r3, #8] 80053bc: 697b ldr r3, [r7, #20] 80053be: 691b ldr r3, [r3, #16] 80053c0: 431a orrs r2, r3 80053c2: 697b ldr r3, [r7, #20] 80053c4: 695b ldr r3, [r3, #20] 80053c6: 431a orrs r2, r3 80053c8: 697b ldr r3, [r7, #20] 80053ca: 69db ldr r3, [r3, #28] 80053cc: 4313 orrs r3, r2 80053ce: 62fb str r3, [r7, #44] @ 0x2c MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 80053d0: 697b ldr r3, [r7, #20] 80053d2: 681b ldr r3, [r3, #0] 80053d4: 681a ldr r2, [r3, #0] 80053d6: 4bab ldr r3, [pc, #684] @ (8005684 ) 80053d8: 4013 ands r3, r2 80053da: 697a ldr r2, [r7, #20] 80053dc: 6812 ldr r2, [r2, #0] 80053de: 6af9 ldr r1, [r7, #44] @ 0x2c 80053e0: 430b orrs r3, r1 80053e2: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80053e4: 697b ldr r3, [r7, #20] 80053e6: 681b ldr r3, [r3, #0] 80053e8: 685b ldr r3, [r3, #4] 80053ea: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80053ee: 697b ldr r3, [r7, #20] 80053f0: 68da ldr r2, [r3, #12] 80053f2: 697b ldr r3, [r7, #20] 80053f4: 681b ldr r3, [r3, #0] 80053f6: 430a orrs r2, r1 80053f8: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 80053fa: 697b ldr r3, [r7, #20] 80053fc: 699b ldr r3, [r3, #24] 80053fe: 62fb str r3, [r7, #44] @ 0x2c if (!(UART_INSTANCE_LOWPOWER(huart))) 8005400: 697b ldr r3, [r7, #20] 8005402: 681b ldr r3, [r3, #0] 8005404: 4aa0 ldr r2, [pc, #640] @ (8005688 ) 8005406: 4293 cmp r3, r2 8005408: d004 beq.n 8005414 { tmpreg |= huart->Init.OneBitSampling; 800540a: 697b ldr r3, [r7, #20] 800540c: 6a1b ldr r3, [r3, #32] 800540e: 6afa ldr r2, [r7, #44] @ 0x2c 8005410: 4313 orrs r3, r2 8005412: 62fb str r3, [r7, #44] @ 0x2c } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8005414: 697b ldr r3, [r7, #20] 8005416: 681b ldr r3, [r3, #0] 8005418: 689b ldr r3, [r3, #8] 800541a: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 800541e: f423 6330 bic.w r3, r3, #2816 @ 0xb00 8005422: 697a ldr r2, [r7, #20] 8005424: 6812 ldr r2, [r2, #0] 8005426: 6af9 ldr r1, [r7, #44] @ 0x2c 8005428: 430b orrs r3, r1 800542a: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800542c: 697b ldr r3, [r7, #20] 800542e: 681b ldr r3, [r3, #0] 8005430: 6adb ldr r3, [r3, #44] @ 0x2c 8005432: f023 010f bic.w r1, r3, #15 8005436: 697b ldr r3, [r7, #20] 8005438: 6a5a ldr r2, [r3, #36] @ 0x24 800543a: 697b ldr r3, [r7, #20] 800543c: 681b ldr r3, [r3, #0] 800543e: 430a orrs r2, r1 8005440: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8005442: 697b ldr r3, [r7, #20] 8005444: 681b ldr r3, [r3, #0] 8005446: 4a91 ldr r2, [pc, #580] @ (800568c ) 8005448: 4293 cmp r3, r2 800544a: d125 bne.n 8005498 800544c: 4b90 ldr r3, [pc, #576] @ (8005690 ) 800544e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005452: f003 0303 and.w r3, r3, #3 8005456: 2b03 cmp r3, #3 8005458: d81a bhi.n 8005490 800545a: a201 add r2, pc, #4 @ (adr r2, 8005460 ) 800545c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005460: 08005471 .word 0x08005471 8005464: 08005481 .word 0x08005481 8005468: 08005479 .word 0x08005479 800546c: 08005489 .word 0x08005489 8005470: 2301 movs r3, #1 8005472: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005476: e0d6 b.n 8005626 8005478: 2302 movs r3, #2 800547a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800547e: e0d2 b.n 8005626 8005480: 2304 movs r3, #4 8005482: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005486: e0ce b.n 8005626 8005488: 2308 movs r3, #8 800548a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800548e: e0ca b.n 8005626 8005490: 2310 movs r3, #16 8005492: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005496: e0c6 b.n 8005626 8005498: 697b ldr r3, [r7, #20] 800549a: 681b ldr r3, [r3, #0] 800549c: 4a7d ldr r2, [pc, #500] @ (8005694 ) 800549e: 4293 cmp r3, r2 80054a0: d138 bne.n 8005514 80054a2: 4b7b ldr r3, [pc, #492] @ (8005690 ) 80054a4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80054a8: f003 030c and.w r3, r3, #12 80054ac: 2b0c cmp r3, #12 80054ae: d82d bhi.n 800550c 80054b0: a201 add r2, pc, #4 @ (adr r2, 80054b8 ) 80054b2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80054b6: bf00 nop 80054b8: 080054ed .word 0x080054ed 80054bc: 0800550d .word 0x0800550d 80054c0: 0800550d .word 0x0800550d 80054c4: 0800550d .word 0x0800550d 80054c8: 080054fd .word 0x080054fd 80054cc: 0800550d .word 0x0800550d 80054d0: 0800550d .word 0x0800550d 80054d4: 0800550d .word 0x0800550d 80054d8: 080054f5 .word 0x080054f5 80054dc: 0800550d .word 0x0800550d 80054e0: 0800550d .word 0x0800550d 80054e4: 0800550d .word 0x0800550d 80054e8: 08005505 .word 0x08005505 80054ec: 2300 movs r3, #0 80054ee: f887 302b strb.w r3, [r7, #43] @ 0x2b 80054f2: e098 b.n 8005626 80054f4: 2302 movs r3, #2 80054f6: f887 302b strb.w r3, [r7, #43] @ 0x2b 80054fa: e094 b.n 8005626 80054fc: 2304 movs r3, #4 80054fe: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005502: e090 b.n 8005626 8005504: 2308 movs r3, #8 8005506: f887 302b strb.w r3, [r7, #43] @ 0x2b 800550a: e08c b.n 8005626 800550c: 2310 movs r3, #16 800550e: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005512: e088 b.n 8005626 8005514: 697b ldr r3, [r7, #20] 8005516: 681b ldr r3, [r3, #0] 8005518: 4a5f ldr r2, [pc, #380] @ (8005698 ) 800551a: 4293 cmp r3, r2 800551c: d125 bne.n 800556a 800551e: 4b5c ldr r3, [pc, #368] @ (8005690 ) 8005520: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005524: f003 0330 and.w r3, r3, #48 @ 0x30 8005528: 2b30 cmp r3, #48 @ 0x30 800552a: d016 beq.n 800555a 800552c: 2b30 cmp r3, #48 @ 0x30 800552e: d818 bhi.n 8005562 8005530: 2b20 cmp r3, #32 8005532: d00a beq.n 800554a 8005534: 2b20 cmp r3, #32 8005536: d814 bhi.n 8005562 8005538: 2b00 cmp r3, #0 800553a: d002 beq.n 8005542 800553c: 2b10 cmp r3, #16 800553e: d008 beq.n 8005552 8005540: e00f b.n 8005562 8005542: 2300 movs r3, #0 8005544: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005548: e06d b.n 8005626 800554a: 2302 movs r3, #2 800554c: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005550: e069 b.n 8005626 8005552: 2304 movs r3, #4 8005554: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005558: e065 b.n 8005626 800555a: 2308 movs r3, #8 800555c: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005560: e061 b.n 8005626 8005562: 2310 movs r3, #16 8005564: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005568: e05d b.n 8005626 800556a: 697b ldr r3, [r7, #20] 800556c: 681b ldr r3, [r3, #0] 800556e: 4a4b ldr r2, [pc, #300] @ (800569c ) 8005570: 4293 cmp r3, r2 8005572: d125 bne.n 80055c0 8005574: 4b46 ldr r3, [pc, #280] @ (8005690 ) 8005576: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800557a: f003 03c0 and.w r3, r3, #192 @ 0xc0 800557e: 2bc0 cmp r3, #192 @ 0xc0 8005580: d016 beq.n 80055b0 8005582: 2bc0 cmp r3, #192 @ 0xc0 8005584: d818 bhi.n 80055b8 8005586: 2b80 cmp r3, #128 @ 0x80 8005588: d00a beq.n 80055a0 800558a: 2b80 cmp r3, #128 @ 0x80 800558c: d814 bhi.n 80055b8 800558e: 2b00 cmp r3, #0 8005590: d002 beq.n 8005598 8005592: 2b40 cmp r3, #64 @ 0x40 8005594: d008 beq.n 80055a8 8005596: e00f b.n 80055b8 8005598: 2300 movs r3, #0 800559a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800559e: e042 b.n 8005626 80055a0: 2302 movs r3, #2 80055a2: f887 302b strb.w r3, [r7, #43] @ 0x2b 80055a6: e03e b.n 8005626 80055a8: 2304 movs r3, #4 80055aa: f887 302b strb.w r3, [r7, #43] @ 0x2b 80055ae: e03a b.n 8005626 80055b0: 2308 movs r3, #8 80055b2: f887 302b strb.w r3, [r7, #43] @ 0x2b 80055b6: e036 b.n 8005626 80055b8: 2310 movs r3, #16 80055ba: f887 302b strb.w r3, [r7, #43] @ 0x2b 80055be: e032 b.n 8005626 80055c0: 697b ldr r3, [r7, #20] 80055c2: 681b ldr r3, [r3, #0] 80055c4: 4a30 ldr r2, [pc, #192] @ (8005688 ) 80055c6: 4293 cmp r3, r2 80055c8: d12a bne.n 8005620 80055ca: 4b31 ldr r3, [pc, #196] @ (8005690 ) 80055cc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80055d0: f403 6340 and.w r3, r3, #3072 @ 0xc00 80055d4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 80055d8: d01a beq.n 8005610 80055da: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 80055de: d81b bhi.n 8005618 80055e0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80055e4: d00c beq.n 8005600 80055e6: f5b3 6f00 cmp.w r3, #2048 @ 0x800 80055ea: d815 bhi.n 8005618 80055ec: 2b00 cmp r3, #0 80055ee: d003 beq.n 80055f8 80055f0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80055f4: d008 beq.n 8005608 80055f6: e00f b.n 8005618 80055f8: 2300 movs r3, #0 80055fa: f887 302b strb.w r3, [r7, #43] @ 0x2b 80055fe: e012 b.n 8005626 8005600: 2302 movs r3, #2 8005602: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005606: e00e b.n 8005626 8005608: 2304 movs r3, #4 800560a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800560e: e00a b.n 8005626 8005610: 2308 movs r3, #8 8005612: f887 302b strb.w r3, [r7, #43] @ 0x2b 8005616: e006 b.n 8005626 8005618: 2310 movs r3, #16 800561a: f887 302b strb.w r3, [r7, #43] @ 0x2b 800561e: e002 b.n 8005626 8005620: 2310 movs r3, #16 8005622: f887 302b strb.w r3, [r7, #43] @ 0x2b /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8005626: 697b ldr r3, [r7, #20] 8005628: 681b ldr r3, [r3, #0] 800562a: 4a17 ldr r2, [pc, #92] @ (8005688 ) 800562c: 4293 cmp r3, r2 800562e: f040 80a8 bne.w 8005782 { /* Retrieve frequency clock */ switch (clocksource) 8005632: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8005636: 2b08 cmp r3, #8 8005638: d834 bhi.n 80056a4 800563a: a201 add r2, pc, #4 @ (adr r2, 8005640 ) 800563c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005640: 08005665 .word 0x08005665 8005644: 080056a5 .word 0x080056a5 8005648: 0800566d .word 0x0800566d 800564c: 080056a5 .word 0x080056a5 8005650: 08005673 .word 0x08005673 8005654: 080056a5 .word 0x080056a5 8005658: 080056a5 .word 0x080056a5 800565c: 080056a5 .word 0x080056a5 8005660: 0800567b .word 0x0800567b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8005664: f7fe faea bl 8003c3c 8005668: 6278 str r0, [r7, #36] @ 0x24 break; 800566a: e021 b.n 80056b0 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 800566c: 4b0c ldr r3, [pc, #48] @ (80056a0 ) 800566e: 627b str r3, [r7, #36] @ 0x24 break; 8005670: e01e b.n 80056b0 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8005672: f7fe fa75 bl 8003b60 8005676: 6278 str r0, [r7, #36] @ 0x24 break; 8005678: e01a b.n 80056b0 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 800567a: f44f 4300 mov.w r3, #32768 @ 0x8000 800567e: 627b str r3, [r7, #36] @ 0x24 break; 8005680: e016 b.n 80056b0 8005682: bf00 nop 8005684: cfff69f3 .word 0xcfff69f3 8005688: 40008000 .word 0x40008000 800568c: 40013800 .word 0x40013800 8005690: 40021000 .word 0x40021000 8005694: 40004400 .word 0x40004400 8005698: 40004800 .word 0x40004800 800569c: 40004c00 .word 0x40004c00 80056a0: 00f42400 .word 0x00f42400 default: pclk = 0U; 80056a4: 2300 movs r3, #0 80056a6: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 80056a8: 2301 movs r3, #1 80056aa: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 80056ae: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80056b0: 6a7b ldr r3, [r7, #36] @ 0x24 80056b2: 2b00 cmp r3, #0 80056b4: f000 812a beq.w 800590c { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 80056b8: 697b ldr r3, [r7, #20] 80056ba: 6a5b ldr r3, [r3, #36] @ 0x24 80056bc: 4a9e ldr r2, [pc, #632] @ (8005938 ) 80056be: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80056c2: 461a mov r2, r3 80056c4: 6a7b ldr r3, [r7, #36] @ 0x24 80056c6: fbb3 f3f2 udiv r3, r3, r2 80056ca: 61bb str r3, [r7, #24] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80056cc: 697b ldr r3, [r7, #20] 80056ce: 685a ldr r2, [r3, #4] 80056d0: 4613 mov r3, r2 80056d2: 005b lsls r3, r3, #1 80056d4: 4413 add r3, r2 80056d6: 69ba ldr r2, [r7, #24] 80056d8: 429a cmp r2, r3 80056da: d305 bcc.n 80056e8 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 80056dc: 697b ldr r3, [r7, #20] 80056de: 685b ldr r3, [r3, #4] 80056e0: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80056e2: 69ba ldr r2, [r7, #24] 80056e4: 429a cmp r2, r3 80056e6: d903 bls.n 80056f0 { ret = HAL_ERROR; 80056e8: 2301 movs r3, #1 80056ea: f887 302a strb.w r3, [r7, #42] @ 0x2a 80056ee: e10d b.n 800590c } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80056f0: 6a7b ldr r3, [r7, #36] @ 0x24 80056f2: 2200 movs r2, #0 80056f4: 60bb str r3, [r7, #8] 80056f6: 60fa str r2, [r7, #12] 80056f8: 697b ldr r3, [r7, #20] 80056fa: 6a5b ldr r3, [r3, #36] @ 0x24 80056fc: 4a8e ldr r2, [pc, #568] @ (8005938 ) 80056fe: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8005702: b29b uxth r3, r3 8005704: 2200 movs r2, #0 8005706: 603b str r3, [r7, #0] 8005708: 607a str r2, [r7, #4] 800570a: e9d7 2300 ldrd r2, r3, [r7] 800570e: e9d7 0102 ldrd r0, r1, [r7, #8] 8005712: f7fa fd81 bl 8000218 <__aeabi_uldivmod> 8005716: 4602 mov r2, r0 8005718: 460b mov r3, r1 800571a: 4610 mov r0, r2 800571c: 4619 mov r1, r3 800571e: f04f 0200 mov.w r2, #0 8005722: f04f 0300 mov.w r3, #0 8005726: 020b lsls r3, r1, #8 8005728: ea43 6310 orr.w r3, r3, r0, lsr #24 800572c: 0202 lsls r2, r0, #8 800572e: 6979 ldr r1, [r7, #20] 8005730: 6849 ldr r1, [r1, #4] 8005732: 0849 lsrs r1, r1, #1 8005734: 2000 movs r0, #0 8005736: 460c mov r4, r1 8005738: 4605 mov r5, r0 800573a: eb12 0804 adds.w r8, r2, r4 800573e: eb43 0905 adc.w r9, r3, r5 8005742: 697b ldr r3, [r7, #20] 8005744: 685b ldr r3, [r3, #4] 8005746: 2200 movs r2, #0 8005748: 469a mov sl, r3 800574a: 4693 mov fp, r2 800574c: 4652 mov r2, sl 800574e: 465b mov r3, fp 8005750: 4640 mov r0, r8 8005752: 4649 mov r1, r9 8005754: f7fa fd60 bl 8000218 <__aeabi_uldivmod> 8005758: 4602 mov r2, r0 800575a: 460b mov r3, r1 800575c: 4613 mov r3, r2 800575e: 623b str r3, [r7, #32] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8005760: 6a3b ldr r3, [r7, #32] 8005762: f5b3 7f40 cmp.w r3, #768 @ 0x300 8005766: d308 bcc.n 800577a 8005768: 6a3b ldr r3, [r7, #32] 800576a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800576e: d204 bcs.n 800577a { huart->Instance->BRR = usartdiv; 8005770: 697b ldr r3, [r7, #20] 8005772: 681b ldr r3, [r3, #0] 8005774: 6a3a ldr r2, [r7, #32] 8005776: 60da str r2, [r3, #12] 8005778: e0c8 b.n 800590c } else { ret = HAL_ERROR; 800577a: 2301 movs r3, #1 800577c: f887 302a strb.w r3, [r7, #42] @ 0x2a 8005780: e0c4 b.n 800590c } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8005782: 697b ldr r3, [r7, #20] 8005784: 69db ldr r3, [r3, #28] 8005786: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800578a: d167 bne.n 800585c { switch (clocksource) 800578c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8005790: 2b08 cmp r3, #8 8005792: d828 bhi.n 80057e6 8005794: a201 add r2, pc, #4 @ (adr r2, 800579c ) 8005796: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800579a: bf00 nop 800579c: 080057c1 .word 0x080057c1 80057a0: 080057c9 .word 0x080057c9 80057a4: 080057d1 .word 0x080057d1 80057a8: 080057e7 .word 0x080057e7 80057ac: 080057d7 .word 0x080057d7 80057b0: 080057e7 .word 0x080057e7 80057b4: 080057e7 .word 0x080057e7 80057b8: 080057e7 .word 0x080057e7 80057bc: 080057df .word 0x080057df { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80057c0: f7fe fa3c bl 8003c3c 80057c4: 6278 str r0, [r7, #36] @ 0x24 break; 80057c6: e014 b.n 80057f2 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80057c8: f7fe fa4e bl 8003c68 80057cc: 6278 str r0, [r7, #36] @ 0x24 break; 80057ce: e010 b.n 80057f2 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 80057d0: 4b5a ldr r3, [pc, #360] @ (800593c ) 80057d2: 627b str r3, [r7, #36] @ 0x24 break; 80057d4: e00d b.n 80057f2 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 80057d6: f7fe f9c3 bl 8003b60 80057da: 6278 str r0, [r7, #36] @ 0x24 break; 80057dc: e009 b.n 80057f2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80057de: f44f 4300 mov.w r3, #32768 @ 0x8000 80057e2: 627b str r3, [r7, #36] @ 0x24 break; 80057e4: e005 b.n 80057f2 default: pclk = 0U; 80057e6: 2300 movs r3, #0 80057e8: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 80057ea: 2301 movs r3, #1 80057ec: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 80057f0: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80057f2: 6a7b ldr r3, [r7, #36] @ 0x24 80057f4: 2b00 cmp r3, #0 80057f6: f000 8089 beq.w 800590c { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80057fa: 697b ldr r3, [r7, #20] 80057fc: 6a5b ldr r3, [r3, #36] @ 0x24 80057fe: 4a4e ldr r2, [pc, #312] @ (8005938 ) 8005800: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8005804: 461a mov r2, r3 8005806: 6a7b ldr r3, [r7, #36] @ 0x24 8005808: fbb3 f3f2 udiv r3, r3, r2 800580c: 005a lsls r2, r3, #1 800580e: 697b ldr r3, [r7, #20] 8005810: 685b ldr r3, [r3, #4] 8005812: 085b lsrs r3, r3, #1 8005814: 441a add r2, r3 8005816: 697b ldr r3, [r7, #20] 8005818: 685b ldr r3, [r3, #4] 800581a: fbb2 f3f3 udiv r3, r2, r3 800581e: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8005820: 6a3b ldr r3, [r7, #32] 8005822: 2b0f cmp r3, #15 8005824: d916 bls.n 8005854 8005826: 6a3b ldr r3, [r7, #32] 8005828: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800582c: d212 bcs.n 8005854 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800582e: 6a3b ldr r3, [r7, #32] 8005830: b29b uxth r3, r3 8005832: f023 030f bic.w r3, r3, #15 8005836: 83fb strh r3, [r7, #30] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8005838: 6a3b ldr r3, [r7, #32] 800583a: 085b lsrs r3, r3, #1 800583c: b29b uxth r3, r3 800583e: f003 0307 and.w r3, r3, #7 8005842: b29a uxth r2, r3 8005844: 8bfb ldrh r3, [r7, #30] 8005846: 4313 orrs r3, r2 8005848: 83fb strh r3, [r7, #30] huart->Instance->BRR = brrtemp; 800584a: 697b ldr r3, [r7, #20] 800584c: 681b ldr r3, [r3, #0] 800584e: 8bfa ldrh r2, [r7, #30] 8005850: 60da str r2, [r3, #12] 8005852: e05b b.n 800590c } else { ret = HAL_ERROR; 8005854: 2301 movs r3, #1 8005856: f887 302a strb.w r3, [r7, #42] @ 0x2a 800585a: e057 b.n 800590c } } } else { switch (clocksource) 800585c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8005860: 2b08 cmp r3, #8 8005862: d828 bhi.n 80058b6 8005864: a201 add r2, pc, #4 @ (adr r2, 800586c ) 8005866: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800586a: bf00 nop 800586c: 08005891 .word 0x08005891 8005870: 08005899 .word 0x08005899 8005874: 080058a1 .word 0x080058a1 8005878: 080058b7 .word 0x080058b7 800587c: 080058a7 .word 0x080058a7 8005880: 080058b7 .word 0x080058b7 8005884: 080058b7 .word 0x080058b7 8005888: 080058b7 .word 0x080058b7 800588c: 080058af .word 0x080058af { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8005890: f7fe f9d4 bl 8003c3c 8005894: 6278 str r0, [r7, #36] @ 0x24 break; 8005896: e014 b.n 80058c2 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8005898: f7fe f9e6 bl 8003c68 800589c: 6278 str r0, [r7, #36] @ 0x24 break; 800589e: e010 b.n 80058c2 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 80058a0: 4b26 ldr r3, [pc, #152] @ (800593c ) 80058a2: 627b str r3, [r7, #36] @ 0x24 break; 80058a4: e00d b.n 80058c2 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 80058a6: f7fe f95b bl 8003b60 80058aa: 6278 str r0, [r7, #36] @ 0x24 break; 80058ac: e009 b.n 80058c2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80058ae: f44f 4300 mov.w r3, #32768 @ 0x8000 80058b2: 627b str r3, [r7, #36] @ 0x24 break; 80058b4: e005 b.n 80058c2 default: pclk = 0U; 80058b6: 2300 movs r3, #0 80058b8: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; 80058ba: 2301 movs r3, #1 80058bc: f887 302a strb.w r3, [r7, #42] @ 0x2a break; 80058c0: bf00 nop } if (pclk != 0U) 80058c2: 6a7b ldr r3, [r7, #36] @ 0x24 80058c4: 2b00 cmp r3, #0 80058c6: d021 beq.n 800590c { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80058c8: 697b ldr r3, [r7, #20] 80058ca: 6a5b ldr r3, [r3, #36] @ 0x24 80058cc: 4a1a ldr r2, [pc, #104] @ (8005938 ) 80058ce: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80058d2: 461a mov r2, r3 80058d4: 6a7b ldr r3, [r7, #36] @ 0x24 80058d6: fbb3 f2f2 udiv r2, r3, r2 80058da: 697b ldr r3, [r7, #20] 80058dc: 685b ldr r3, [r3, #4] 80058de: 085b lsrs r3, r3, #1 80058e0: 441a add r2, r3 80058e2: 697b ldr r3, [r7, #20] 80058e4: 685b ldr r3, [r3, #4] 80058e6: fbb2 f3f3 udiv r3, r2, r3 80058ea: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80058ec: 6a3b ldr r3, [r7, #32] 80058ee: 2b0f cmp r3, #15 80058f0: d909 bls.n 8005906 80058f2: 6a3b ldr r3, [r7, #32] 80058f4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80058f8: d205 bcs.n 8005906 { huart->Instance->BRR = (uint16_t)usartdiv; 80058fa: 6a3b ldr r3, [r7, #32] 80058fc: b29a uxth r2, r3 80058fe: 697b ldr r3, [r7, #20] 8005900: 681b ldr r3, [r3, #0] 8005902: 60da str r2, [r3, #12] 8005904: e002 b.n 800590c } else { ret = HAL_ERROR; 8005906: 2301 movs r3, #1 8005908: f887 302a strb.w r3, [r7, #42] @ 0x2a } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 800590c: 697b ldr r3, [r7, #20] 800590e: 2201 movs r2, #1 8005910: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8005914: 697b ldr r3, [r7, #20] 8005916: 2201 movs r2, #1 8005918: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 800591c: 697b ldr r3, [r7, #20] 800591e: 2200 movs r2, #0 8005920: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8005922: 697b ldr r3, [r7, #20] 8005924: 2200 movs r2, #0 8005926: 679a str r2, [r3, #120] @ 0x78 return ret; 8005928: f897 302a ldrb.w r3, [r7, #42] @ 0x2a } 800592c: 4618 mov r0, r3 800592e: 3730 adds r7, #48 @ 0x30 8005930: 46bd mov sp, r7 8005932: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8005936: bf00 nop 8005938: 08006d4c .word 0x08006d4c 800593c: 00f42400 .word 0x00f42400 08005940 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8005940: b480 push {r7} 8005942: b083 sub sp, #12 8005944: af00 add r7, sp, #0 8005946: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8005948: 687b ldr r3, [r7, #4] 800594a: 6a9b ldr r3, [r3, #40] @ 0x28 800594c: f003 0308 and.w r3, r3, #8 8005950: 2b00 cmp r3, #0 8005952: d00a beq.n 800596a { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8005954: 687b ldr r3, [r7, #4] 8005956: 681b ldr r3, [r3, #0] 8005958: 685b ldr r3, [r3, #4] 800595a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 800595e: 687b ldr r3, [r7, #4] 8005960: 6b9a ldr r2, [r3, #56] @ 0x38 8005962: 687b ldr r3, [r7, #4] 8005964: 681b ldr r3, [r3, #0] 8005966: 430a orrs r2, r1 8005968: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800596a: 687b ldr r3, [r7, #4] 800596c: 6a9b ldr r3, [r3, #40] @ 0x28 800596e: f003 0301 and.w r3, r3, #1 8005972: 2b00 cmp r3, #0 8005974: d00a beq.n 800598c { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8005976: 687b ldr r3, [r7, #4] 8005978: 681b ldr r3, [r3, #0] 800597a: 685b ldr r3, [r3, #4] 800597c: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8005980: 687b ldr r3, [r7, #4] 8005982: 6ada ldr r2, [r3, #44] @ 0x2c 8005984: 687b ldr r3, [r7, #4] 8005986: 681b ldr r3, [r3, #0] 8005988: 430a orrs r2, r1 800598a: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800598c: 687b ldr r3, [r7, #4] 800598e: 6a9b ldr r3, [r3, #40] @ 0x28 8005990: f003 0302 and.w r3, r3, #2 8005994: 2b00 cmp r3, #0 8005996: d00a beq.n 80059ae { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8005998: 687b ldr r3, [r7, #4] 800599a: 681b ldr r3, [r3, #0] 800599c: 685b ldr r3, [r3, #4] 800599e: f423 3180 bic.w r1, r3, #65536 @ 0x10000 80059a2: 687b ldr r3, [r7, #4] 80059a4: 6b1a ldr r2, [r3, #48] @ 0x30 80059a6: 687b ldr r3, [r7, #4] 80059a8: 681b ldr r3, [r3, #0] 80059aa: 430a orrs r2, r1 80059ac: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 80059ae: 687b ldr r3, [r7, #4] 80059b0: 6a9b ldr r3, [r3, #40] @ 0x28 80059b2: f003 0304 and.w r3, r3, #4 80059b6: 2b00 cmp r3, #0 80059b8: d00a beq.n 80059d0 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 80059ba: 687b ldr r3, [r7, #4] 80059bc: 681b ldr r3, [r3, #0] 80059be: 685b ldr r3, [r3, #4] 80059c0: f423 2180 bic.w r1, r3, #262144 @ 0x40000 80059c4: 687b ldr r3, [r7, #4] 80059c6: 6b5a ldr r2, [r3, #52] @ 0x34 80059c8: 687b ldr r3, [r7, #4] 80059ca: 681b ldr r3, [r3, #0] 80059cc: 430a orrs r2, r1 80059ce: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 80059d0: 687b ldr r3, [r7, #4] 80059d2: 6a9b ldr r3, [r3, #40] @ 0x28 80059d4: f003 0310 and.w r3, r3, #16 80059d8: 2b00 cmp r3, #0 80059da: d00a beq.n 80059f2 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 80059dc: 687b ldr r3, [r7, #4] 80059de: 681b ldr r3, [r3, #0] 80059e0: 689b ldr r3, [r3, #8] 80059e2: f423 5180 bic.w r1, r3, #4096 @ 0x1000 80059e6: 687b ldr r3, [r7, #4] 80059e8: 6bda ldr r2, [r3, #60] @ 0x3c 80059ea: 687b ldr r3, [r7, #4] 80059ec: 681b ldr r3, [r3, #0] 80059ee: 430a orrs r2, r1 80059f0: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 80059f2: 687b ldr r3, [r7, #4] 80059f4: 6a9b ldr r3, [r3, #40] @ 0x28 80059f6: f003 0320 and.w r3, r3, #32 80059fa: 2b00 cmp r3, #0 80059fc: d00a beq.n 8005a14 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 80059fe: 687b ldr r3, [r7, #4] 8005a00: 681b ldr r3, [r3, #0] 8005a02: 689b ldr r3, [r3, #8] 8005a04: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8005a08: 687b ldr r3, [r7, #4] 8005a0a: 6c1a ldr r2, [r3, #64] @ 0x40 8005a0c: 687b ldr r3, [r7, #4] 8005a0e: 681b ldr r3, [r3, #0] 8005a10: 430a orrs r2, r1 8005a12: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8005a14: 687b ldr r3, [r7, #4] 8005a16: 6a9b ldr r3, [r3, #40] @ 0x28 8005a18: f003 0340 and.w r3, r3, #64 @ 0x40 8005a1c: 2b00 cmp r3, #0 8005a1e: d01a beq.n 8005a56 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8005a20: 687b ldr r3, [r7, #4] 8005a22: 681b ldr r3, [r3, #0] 8005a24: 685b ldr r3, [r3, #4] 8005a26: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8005a2a: 687b ldr r3, [r7, #4] 8005a2c: 6c5a ldr r2, [r3, #68] @ 0x44 8005a2e: 687b ldr r3, [r7, #4] 8005a30: 681b ldr r3, [r3, #0] 8005a32: 430a orrs r2, r1 8005a34: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8005a36: 687b ldr r3, [r7, #4] 8005a38: 6c5b ldr r3, [r3, #68] @ 0x44 8005a3a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8005a3e: d10a bne.n 8005a56 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8005a40: 687b ldr r3, [r7, #4] 8005a42: 681b ldr r3, [r3, #0] 8005a44: 685b ldr r3, [r3, #4] 8005a46: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8005a4a: 687b ldr r3, [r7, #4] 8005a4c: 6c9a ldr r2, [r3, #72] @ 0x48 8005a4e: 687b ldr r3, [r7, #4] 8005a50: 681b ldr r3, [r3, #0] 8005a52: 430a orrs r2, r1 8005a54: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8005a56: 687b ldr r3, [r7, #4] 8005a58: 6a9b ldr r3, [r3, #40] @ 0x28 8005a5a: f003 0380 and.w r3, r3, #128 @ 0x80 8005a5e: 2b00 cmp r3, #0 8005a60: d00a beq.n 8005a78 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8005a62: 687b ldr r3, [r7, #4] 8005a64: 681b ldr r3, [r3, #0] 8005a66: 685b ldr r3, [r3, #4] 8005a68: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8005a6c: 687b ldr r3, [r7, #4] 8005a6e: 6cda ldr r2, [r3, #76] @ 0x4c 8005a70: 687b ldr r3, [r7, #4] 8005a72: 681b ldr r3, [r3, #0] 8005a74: 430a orrs r2, r1 8005a76: 605a str r2, [r3, #4] } } 8005a78: bf00 nop 8005a7a: 370c adds r7, #12 8005a7c: 46bd mov sp, r7 8005a7e: f85d 7b04 ldr.w r7, [sp], #4 8005a82: 4770 bx lr 08005a84 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8005a84: b580 push {r7, lr} 8005a86: b098 sub sp, #96 @ 0x60 8005a88: af02 add r7, sp, #8 8005a8a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005a8c: 687b ldr r3, [r7, #4] 8005a8e: 2200 movs r2, #0 8005a90: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8005a94: f7fb fbbc bl 8001210 8005a98: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8005a9a: 687b ldr r3, [r7, #4] 8005a9c: 681b ldr r3, [r3, #0] 8005a9e: 681b ldr r3, [r3, #0] 8005aa0: f003 0308 and.w r3, r3, #8 8005aa4: 2b08 cmp r3, #8 8005aa6: d12f bne.n 8005b08 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8005aa8: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8005aac: 9300 str r3, [sp, #0] 8005aae: 6d7b ldr r3, [r7, #84] @ 0x54 8005ab0: 2200 movs r2, #0 8005ab2: f44f 1100 mov.w r1, #2097152 @ 0x200000 8005ab6: 6878 ldr r0, [r7, #4] 8005ab8: f000 f88e bl 8005bd8 8005abc: 4603 mov r3, r0 8005abe: 2b00 cmp r3, #0 8005ac0: d022 beq.n 8005b08 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8005ac2: 687b ldr r3, [r7, #4] 8005ac4: 681b ldr r3, [r3, #0] 8005ac6: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005ac8: 6bbb ldr r3, [r7, #56] @ 0x38 8005aca: e853 3f00 ldrex r3, [r3] 8005ace: 637b str r3, [r7, #52] @ 0x34 return(result); 8005ad0: 6b7b ldr r3, [r7, #52] @ 0x34 8005ad2: f023 0380 bic.w r3, r3, #128 @ 0x80 8005ad6: 653b str r3, [r7, #80] @ 0x50 8005ad8: 687b ldr r3, [r7, #4] 8005ada: 681b ldr r3, [r3, #0] 8005adc: 461a mov r2, r3 8005ade: 6d3b ldr r3, [r7, #80] @ 0x50 8005ae0: 647b str r3, [r7, #68] @ 0x44 8005ae2: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ae4: 6c39 ldr r1, [r7, #64] @ 0x40 8005ae6: 6c7a ldr r2, [r7, #68] @ 0x44 8005ae8: e841 2300 strex r3, r2, [r1] 8005aec: 63fb str r3, [r7, #60] @ 0x3c return(result); 8005aee: 6bfb ldr r3, [r7, #60] @ 0x3c 8005af0: 2b00 cmp r3, #0 8005af2: d1e6 bne.n 8005ac2 huart->gState = HAL_UART_STATE_READY; 8005af4: 687b ldr r3, [r7, #4] 8005af6: 2220 movs r2, #32 8005af8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8005afc: 687b ldr r3, [r7, #4] 8005afe: 2200 movs r2, #0 8005b00: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8005b04: 2303 movs r3, #3 8005b06: e063 b.n 8005bd0 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8005b08: 687b ldr r3, [r7, #4] 8005b0a: 681b ldr r3, [r3, #0] 8005b0c: 681b ldr r3, [r3, #0] 8005b0e: f003 0304 and.w r3, r3, #4 8005b12: 2b04 cmp r3, #4 8005b14: d149 bne.n 8005baa { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8005b16: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8005b1a: 9300 str r3, [sp, #0] 8005b1c: 6d7b ldr r3, [r7, #84] @ 0x54 8005b1e: 2200 movs r2, #0 8005b20: f44f 0180 mov.w r1, #4194304 @ 0x400000 8005b24: 6878 ldr r0, [r7, #4] 8005b26: f000 f857 bl 8005bd8 8005b2a: 4603 mov r3, r0 8005b2c: 2b00 cmp r3, #0 8005b2e: d03c beq.n 8005baa { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8005b30: 687b ldr r3, [r7, #4] 8005b32: 681b ldr r3, [r3, #0] 8005b34: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b36: 6a7b ldr r3, [r7, #36] @ 0x24 8005b38: e853 3f00 ldrex r3, [r3] 8005b3c: 623b str r3, [r7, #32] return(result); 8005b3e: 6a3b ldr r3, [r7, #32] 8005b40: f423 7390 bic.w r3, r3, #288 @ 0x120 8005b44: 64fb str r3, [r7, #76] @ 0x4c 8005b46: 687b ldr r3, [r7, #4] 8005b48: 681b ldr r3, [r3, #0] 8005b4a: 461a mov r2, r3 8005b4c: 6cfb ldr r3, [r7, #76] @ 0x4c 8005b4e: 633b str r3, [r7, #48] @ 0x30 8005b50: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005b52: 6af9 ldr r1, [r7, #44] @ 0x2c 8005b54: 6b3a ldr r2, [r7, #48] @ 0x30 8005b56: e841 2300 strex r3, r2, [r1] 8005b5a: 62bb str r3, [r7, #40] @ 0x28 return(result); 8005b5c: 6abb ldr r3, [r7, #40] @ 0x28 8005b5e: 2b00 cmp r3, #0 8005b60: d1e6 bne.n 8005b30 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005b62: 687b ldr r3, [r7, #4] 8005b64: 681b ldr r3, [r3, #0] 8005b66: 3308 adds r3, #8 8005b68: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005b6a: 693b ldr r3, [r7, #16] 8005b6c: e853 3f00 ldrex r3, [r3] 8005b70: 60fb str r3, [r7, #12] return(result); 8005b72: 68fb ldr r3, [r7, #12] 8005b74: f023 0301 bic.w r3, r3, #1 8005b78: 64bb str r3, [r7, #72] @ 0x48 8005b7a: 687b ldr r3, [r7, #4] 8005b7c: 681b ldr r3, [r3, #0] 8005b7e: 3308 adds r3, #8 8005b80: 6cba ldr r2, [r7, #72] @ 0x48 8005b82: 61fa str r2, [r7, #28] 8005b84: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005b86: 69b9 ldr r1, [r7, #24] 8005b88: 69fa ldr r2, [r7, #28] 8005b8a: e841 2300 strex r3, r2, [r1] 8005b8e: 617b str r3, [r7, #20] return(result); 8005b90: 697b ldr r3, [r7, #20] 8005b92: 2b00 cmp r3, #0 8005b94: d1e5 bne.n 8005b62 huart->RxState = HAL_UART_STATE_READY; 8005b96: 687b ldr r3, [r7, #4] 8005b98: 2220 movs r2, #32 8005b9a: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8005b9e: 687b ldr r3, [r7, #4] 8005ba0: 2200 movs r2, #0 8005ba2: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8005ba6: 2303 movs r3, #3 8005ba8: e012 b.n 8005bd0 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8005baa: 687b ldr r3, [r7, #4] 8005bac: 2220 movs r2, #32 8005bae: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8005bb2: 687b ldr r3, [r7, #4] 8005bb4: 2220 movs r2, #32 8005bb6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005bba: 687b ldr r3, [r7, #4] 8005bbc: 2200 movs r2, #0 8005bbe: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8005bc0: 687b ldr r3, [r7, #4] 8005bc2: 2200 movs r2, #0 8005bc4: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8005bc6: 687b ldr r3, [r7, #4] 8005bc8: 2200 movs r2, #0 8005bca: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8005bce: 2300 movs r3, #0 } 8005bd0: 4618 mov r0, r3 8005bd2: 3758 adds r7, #88 @ 0x58 8005bd4: 46bd mov sp, r7 8005bd6: bd80 pop {r7, pc} 08005bd8 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8005bd8: b580 push {r7, lr} 8005bda: b084 sub sp, #16 8005bdc: af00 add r7, sp, #0 8005bde: 60f8 str r0, [r7, #12] 8005be0: 60b9 str r1, [r7, #8] 8005be2: 603b str r3, [r7, #0] 8005be4: 4613 mov r3, r2 8005be6: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8005be8: e04f b.n 8005c8a { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8005bea: 69bb ldr r3, [r7, #24] 8005bec: f1b3 3fff cmp.w r3, #4294967295 8005bf0: d04b beq.n 8005c8a { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8005bf2: f7fb fb0d bl 8001210 8005bf6: 4602 mov r2, r0 8005bf8: 683b ldr r3, [r7, #0] 8005bfa: 1ad3 subs r3, r2, r3 8005bfc: 69ba ldr r2, [r7, #24] 8005bfe: 429a cmp r2, r3 8005c00: d302 bcc.n 8005c08 8005c02: 69bb ldr r3, [r7, #24] 8005c04: 2b00 cmp r3, #0 8005c06: d101 bne.n 8005c0c { return HAL_TIMEOUT; 8005c08: 2303 movs r3, #3 8005c0a: e04e b.n 8005caa } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8005c0c: 68fb ldr r3, [r7, #12] 8005c0e: 681b ldr r3, [r3, #0] 8005c10: 681b ldr r3, [r3, #0] 8005c12: f003 0304 and.w r3, r3, #4 8005c16: 2b00 cmp r3, #0 8005c18: d037 beq.n 8005c8a 8005c1a: 68bb ldr r3, [r7, #8] 8005c1c: 2b80 cmp r3, #128 @ 0x80 8005c1e: d034 beq.n 8005c8a 8005c20: 68bb ldr r3, [r7, #8] 8005c22: 2b40 cmp r3, #64 @ 0x40 8005c24: d031 beq.n 8005c8a { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8005c26: 68fb ldr r3, [r7, #12] 8005c28: 681b ldr r3, [r3, #0] 8005c2a: 69db ldr r3, [r3, #28] 8005c2c: f003 0308 and.w r3, r3, #8 8005c30: 2b08 cmp r3, #8 8005c32: d110 bne.n 8005c56 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8005c34: 68fb ldr r3, [r7, #12] 8005c36: 681b ldr r3, [r3, #0] 8005c38: 2208 movs r2, #8 8005c3a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8005c3c: 68f8 ldr r0, [r7, #12] 8005c3e: f000 f95b bl 8005ef8 huart->ErrorCode = HAL_UART_ERROR_ORE; 8005c42: 68fb ldr r3, [r7, #12] 8005c44: 2208 movs r2, #8 8005c46: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8005c4a: 68fb ldr r3, [r7, #12] 8005c4c: 2200 movs r2, #0 8005c4e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8005c52: 2301 movs r3, #1 8005c54: e029 b.n 8005caa } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8005c56: 68fb ldr r3, [r7, #12] 8005c58: 681b ldr r3, [r3, #0] 8005c5a: 69db ldr r3, [r3, #28] 8005c5c: f403 6300 and.w r3, r3, #2048 @ 0x800 8005c60: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8005c64: d111 bne.n 8005c8a { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8005c66: 68fb ldr r3, [r7, #12] 8005c68: 681b ldr r3, [r3, #0] 8005c6a: f44f 6200 mov.w r2, #2048 @ 0x800 8005c6e: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8005c70: 68f8 ldr r0, [r7, #12] 8005c72: f000 f941 bl 8005ef8 huart->ErrorCode = HAL_UART_ERROR_RTO; 8005c76: 68fb ldr r3, [r7, #12] 8005c78: 2220 movs r2, #32 8005c7a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8005c7e: 68fb ldr r3, [r7, #12] 8005c80: 2200 movs r2, #0 8005c82: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8005c86: 2303 movs r3, #3 8005c88: e00f b.n 8005caa while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8005c8a: 68fb ldr r3, [r7, #12] 8005c8c: 681b ldr r3, [r3, #0] 8005c8e: 69da ldr r2, [r3, #28] 8005c90: 68bb ldr r3, [r7, #8] 8005c92: 4013 ands r3, r2 8005c94: 68ba ldr r2, [r7, #8] 8005c96: 429a cmp r2, r3 8005c98: bf0c ite eq 8005c9a: 2301 moveq r3, #1 8005c9c: 2300 movne r3, #0 8005c9e: b2db uxtb r3, r3 8005ca0: 461a mov r2, r3 8005ca2: 79fb ldrb r3, [r7, #7] 8005ca4: 429a cmp r2, r3 8005ca6: d0a0 beq.n 8005bea } } } } return HAL_OK; 8005ca8: 2300 movs r3, #0 } 8005caa: 4618 mov r0, r3 8005cac: 3710 adds r7, #16 8005cae: 46bd mov sp, r7 8005cb0: bd80 pop {r7, pc} ... 08005cb4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8005cb4: b480 push {r7} 8005cb6: b0a3 sub sp, #140 @ 0x8c 8005cb8: af00 add r7, sp, #0 8005cba: 60f8 str r0, [r7, #12] 8005cbc: 60b9 str r1, [r7, #8] 8005cbe: 4613 mov r3, r2 8005cc0: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8005cc2: 68fb ldr r3, [r7, #12] 8005cc4: 68ba ldr r2, [r7, #8] 8005cc6: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8005cc8: 68fb ldr r3, [r7, #12] 8005cca: 88fa ldrh r2, [r7, #6] 8005ccc: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8005cd0: 68fb ldr r3, [r7, #12] 8005cd2: 88fa ldrh r2, [r7, #6] 8005cd4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8005cd8: 68fb ldr r3, [r7, #12] 8005cda: 2200 movs r2, #0 8005cdc: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8005cde: 68fb ldr r3, [r7, #12] 8005ce0: 689b ldr r3, [r3, #8] 8005ce2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005ce6: d10e bne.n 8005d06 8005ce8: 68fb ldr r3, [r7, #12] 8005cea: 691b ldr r3, [r3, #16] 8005cec: 2b00 cmp r3, #0 8005cee: d105 bne.n 8005cfc 8005cf0: 68fb ldr r3, [r7, #12] 8005cf2: f240 12ff movw r2, #511 @ 0x1ff 8005cf6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8005cfa: e02d b.n 8005d58 8005cfc: 68fb ldr r3, [r7, #12] 8005cfe: 22ff movs r2, #255 @ 0xff 8005d00: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8005d04: e028 b.n 8005d58 8005d06: 68fb ldr r3, [r7, #12] 8005d08: 689b ldr r3, [r3, #8] 8005d0a: 2b00 cmp r3, #0 8005d0c: d10d bne.n 8005d2a 8005d0e: 68fb ldr r3, [r7, #12] 8005d10: 691b ldr r3, [r3, #16] 8005d12: 2b00 cmp r3, #0 8005d14: d104 bne.n 8005d20 8005d16: 68fb ldr r3, [r7, #12] 8005d18: 22ff movs r2, #255 @ 0xff 8005d1a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8005d1e: e01b b.n 8005d58 8005d20: 68fb ldr r3, [r7, #12] 8005d22: 227f movs r2, #127 @ 0x7f 8005d24: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8005d28: e016 b.n 8005d58 8005d2a: 68fb ldr r3, [r7, #12] 8005d2c: 689b ldr r3, [r3, #8] 8005d2e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005d32: d10d bne.n 8005d50 8005d34: 68fb ldr r3, [r7, #12] 8005d36: 691b ldr r3, [r3, #16] 8005d38: 2b00 cmp r3, #0 8005d3a: d104 bne.n 8005d46 8005d3c: 68fb ldr r3, [r7, #12] 8005d3e: 227f movs r2, #127 @ 0x7f 8005d40: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8005d44: e008 b.n 8005d58 8005d46: 68fb ldr r3, [r7, #12] 8005d48: 223f movs r2, #63 @ 0x3f 8005d4a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8005d4e: e003 b.n 8005d58 8005d50: 68fb ldr r3, [r7, #12] 8005d52: 2200 movs r2, #0 8005d54: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8005d58: 68fb ldr r3, [r7, #12] 8005d5a: 2200 movs r2, #0 8005d5c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8005d60: 68fb ldr r3, [r7, #12] 8005d62: 2222 movs r2, #34 @ 0x22 8005d64: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8005d68: 68fb ldr r3, [r7, #12] 8005d6a: 681b ldr r3, [r3, #0] 8005d6c: 3308 adds r3, #8 8005d6e: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005d70: 6e7b ldr r3, [r7, #100] @ 0x64 8005d72: e853 3f00 ldrex r3, [r3] 8005d76: 663b str r3, [r7, #96] @ 0x60 return(result); 8005d78: 6e3b ldr r3, [r7, #96] @ 0x60 8005d7a: f043 0301 orr.w r3, r3, #1 8005d7e: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005d82: 68fb ldr r3, [r7, #12] 8005d84: 681b ldr r3, [r3, #0] 8005d86: 3308 adds r3, #8 8005d88: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8005d8c: 673a str r2, [r7, #112] @ 0x70 8005d8e: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005d90: 6ef9 ldr r1, [r7, #108] @ 0x6c 8005d92: 6f3a ldr r2, [r7, #112] @ 0x70 8005d94: e841 2300 strex r3, r2, [r1] 8005d98: 66bb str r3, [r7, #104] @ 0x68 return(result); 8005d9a: 6ebb ldr r3, [r7, #104] @ 0x68 8005d9c: 2b00 cmp r3, #0 8005d9e: d1e3 bne.n 8005d68 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8005da0: 68fb ldr r3, [r7, #12] 8005da2: 6e5b ldr r3, [r3, #100] @ 0x64 8005da4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005da8: d14f bne.n 8005e4a 8005daa: 68fb ldr r3, [r7, #12] 8005dac: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8005db0: 88fa ldrh r2, [r7, #6] 8005db2: 429a cmp r2, r3 8005db4: d349 bcc.n 8005e4a { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8005db6: 68fb ldr r3, [r7, #12] 8005db8: 689b ldr r3, [r3, #8] 8005dba: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005dbe: d107 bne.n 8005dd0 8005dc0: 68fb ldr r3, [r7, #12] 8005dc2: 691b ldr r3, [r3, #16] 8005dc4: 2b00 cmp r3, #0 8005dc6: d103 bne.n 8005dd0 { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8005dc8: 68fb ldr r3, [r7, #12] 8005dca: 4a47 ldr r2, [pc, #284] @ (8005ee8 ) 8005dcc: 675a str r2, [r3, #116] @ 0x74 8005dce: e002 b.n 8005dd6 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8005dd0: 68fb ldr r3, [r7, #12] 8005dd2: 4a46 ldr r2, [pc, #280] @ (8005eec ) 8005dd4: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8005dd6: 68fb ldr r3, [r7, #12] 8005dd8: 691b ldr r3, [r3, #16] 8005dda: 2b00 cmp r3, #0 8005ddc: d01a beq.n 8005e14 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8005dde: 68fb ldr r3, [r7, #12] 8005de0: 681b ldr r3, [r3, #0] 8005de2: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005de4: 6d3b ldr r3, [r7, #80] @ 0x50 8005de6: e853 3f00 ldrex r3, [r3] 8005dea: 64fb str r3, [r7, #76] @ 0x4c return(result); 8005dec: 6cfb ldr r3, [r7, #76] @ 0x4c 8005dee: f443 7380 orr.w r3, r3, #256 @ 0x100 8005df2: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8005df6: 68fb ldr r3, [r7, #12] 8005df8: 681b ldr r3, [r3, #0] 8005dfa: 461a mov r2, r3 8005dfc: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8005e00: 65fb str r3, [r7, #92] @ 0x5c 8005e02: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005e04: 6db9 ldr r1, [r7, #88] @ 0x58 8005e06: 6dfa ldr r2, [r7, #92] @ 0x5c 8005e08: e841 2300 strex r3, r2, [r1] 8005e0c: 657b str r3, [r7, #84] @ 0x54 return(result); 8005e0e: 6d7b ldr r3, [r7, #84] @ 0x54 8005e10: 2b00 cmp r3, #0 8005e12: d1e4 bne.n 8005dde } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8005e14: 68fb ldr r3, [r7, #12] 8005e16: 681b ldr r3, [r3, #0] 8005e18: 3308 adds r3, #8 8005e1a: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005e1c: 6bfb ldr r3, [r7, #60] @ 0x3c 8005e1e: e853 3f00 ldrex r3, [r3] 8005e22: 63bb str r3, [r7, #56] @ 0x38 return(result); 8005e24: 6bbb ldr r3, [r7, #56] @ 0x38 8005e26: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8005e2a: 67fb str r3, [r7, #124] @ 0x7c 8005e2c: 68fb ldr r3, [r7, #12] 8005e2e: 681b ldr r3, [r3, #0] 8005e30: 3308 adds r3, #8 8005e32: 6ffa ldr r2, [r7, #124] @ 0x7c 8005e34: 64ba str r2, [r7, #72] @ 0x48 8005e36: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005e38: 6c79 ldr r1, [r7, #68] @ 0x44 8005e3a: 6cba ldr r2, [r7, #72] @ 0x48 8005e3c: e841 2300 strex r3, r2, [r1] 8005e40: 643b str r3, [r7, #64] @ 0x40 return(result); 8005e42: 6c3b ldr r3, [r7, #64] @ 0x40 8005e44: 2b00 cmp r3, #0 8005e46: d1e5 bne.n 8005e14 8005e48: e046 b.n 8005ed8 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8005e4a: 68fb ldr r3, [r7, #12] 8005e4c: 689b ldr r3, [r3, #8] 8005e4e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005e52: d107 bne.n 8005e64 8005e54: 68fb ldr r3, [r7, #12] 8005e56: 691b ldr r3, [r3, #16] 8005e58: 2b00 cmp r3, #0 8005e5a: d103 bne.n 8005e64 { huart->RxISR = UART_RxISR_16BIT; 8005e5c: 68fb ldr r3, [r7, #12] 8005e5e: 4a24 ldr r2, [pc, #144] @ (8005ef0 ) 8005e60: 675a str r2, [r3, #116] @ 0x74 8005e62: e002 b.n 8005e6a } else { huart->RxISR = UART_RxISR_8BIT; 8005e64: 68fb ldr r3, [r7, #12] 8005e66: 4a23 ldr r2, [pc, #140] @ (8005ef4 ) 8005e68: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8005e6a: 68fb ldr r3, [r7, #12] 8005e6c: 691b ldr r3, [r3, #16] 8005e6e: 2b00 cmp r3, #0 8005e70: d019 beq.n 8005ea6 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8005e72: 68fb ldr r3, [r7, #12] 8005e74: 681b ldr r3, [r3, #0] 8005e76: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005e78: 6abb ldr r3, [r7, #40] @ 0x28 8005e7a: e853 3f00 ldrex r3, [r3] 8005e7e: 627b str r3, [r7, #36] @ 0x24 return(result); 8005e80: 6a7b ldr r3, [r7, #36] @ 0x24 8005e82: f443 7390 orr.w r3, r3, #288 @ 0x120 8005e86: 677b str r3, [r7, #116] @ 0x74 8005e88: 68fb ldr r3, [r7, #12] 8005e8a: 681b ldr r3, [r3, #0] 8005e8c: 461a mov r2, r3 8005e8e: 6f7b ldr r3, [r7, #116] @ 0x74 8005e90: 637b str r3, [r7, #52] @ 0x34 8005e92: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005e94: 6b39 ldr r1, [r7, #48] @ 0x30 8005e96: 6b7a ldr r2, [r7, #52] @ 0x34 8005e98: e841 2300 strex r3, r2, [r1] 8005e9c: 62fb str r3, [r7, #44] @ 0x2c return(result); 8005e9e: 6afb ldr r3, [r7, #44] @ 0x2c 8005ea0: 2b00 cmp r3, #0 8005ea2: d1e6 bne.n 8005e72 8005ea4: e018 b.n 8005ed8 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8005ea6: 68fb ldr r3, [r7, #12] 8005ea8: 681b ldr r3, [r3, #0] 8005eaa: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005eac: 697b ldr r3, [r7, #20] 8005eae: e853 3f00 ldrex r3, [r3] 8005eb2: 613b str r3, [r7, #16] return(result); 8005eb4: 693b ldr r3, [r7, #16] 8005eb6: f043 0320 orr.w r3, r3, #32 8005eba: 67bb str r3, [r7, #120] @ 0x78 8005ebc: 68fb ldr r3, [r7, #12] 8005ebe: 681b ldr r3, [r3, #0] 8005ec0: 461a mov r2, r3 8005ec2: 6fbb ldr r3, [r7, #120] @ 0x78 8005ec4: 623b str r3, [r7, #32] 8005ec6: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005ec8: 69f9 ldr r1, [r7, #28] 8005eca: 6a3a ldr r2, [r7, #32] 8005ecc: e841 2300 strex r3, r2, [r1] 8005ed0: 61bb str r3, [r7, #24] return(result); 8005ed2: 69bb ldr r3, [r7, #24] 8005ed4: 2b00 cmp r3, #0 8005ed6: d1e6 bne.n 8005ea6 } } return HAL_OK; 8005ed8: 2300 movs r3, #0 } 8005eda: 4618 mov r0, r3 8005edc: 378c adds r7, #140 @ 0x8c 8005ede: 46bd mov sp, r7 8005ee0: f85d 7b04 ldr.w r7, [sp], #4 8005ee4: 4770 bx lr 8005ee6: bf00 nop 8005ee8: 08006715 .word 0x08006715 8005eec: 080063b1 .word 0x080063b1 8005ef0: 080061f9 .word 0x080061f9 8005ef4: 08006041 .word 0x08006041 08005ef8 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8005ef8: b480 push {r7} 8005efa: b095 sub sp, #84 @ 0x54 8005efc: af00 add r7, sp, #0 8005efe: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8005f00: 687b ldr r3, [r7, #4] 8005f02: 681b ldr r3, [r3, #0] 8005f04: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f06: 6b7b ldr r3, [r7, #52] @ 0x34 8005f08: e853 3f00 ldrex r3, [r3] 8005f0c: 633b str r3, [r7, #48] @ 0x30 return(result); 8005f0e: 6b3b ldr r3, [r7, #48] @ 0x30 8005f10: f423 7390 bic.w r3, r3, #288 @ 0x120 8005f14: 64fb str r3, [r7, #76] @ 0x4c 8005f16: 687b ldr r3, [r7, #4] 8005f18: 681b ldr r3, [r3, #0] 8005f1a: 461a mov r2, r3 8005f1c: 6cfb ldr r3, [r7, #76] @ 0x4c 8005f1e: 643b str r3, [r7, #64] @ 0x40 8005f20: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f22: 6bf9 ldr r1, [r7, #60] @ 0x3c 8005f24: 6c3a ldr r2, [r7, #64] @ 0x40 8005f26: e841 2300 strex r3, r2, [r1] 8005f2a: 63bb str r3, [r7, #56] @ 0x38 return(result); 8005f2c: 6bbb ldr r3, [r7, #56] @ 0x38 8005f2e: 2b00 cmp r3, #0 8005f30: d1e6 bne.n 8005f00 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8005f32: 687b ldr r3, [r7, #4] 8005f34: 681b ldr r3, [r3, #0] 8005f36: 3308 adds r3, #8 8005f38: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f3a: 6a3b ldr r3, [r7, #32] 8005f3c: e853 3f00 ldrex r3, [r3] 8005f40: 61fb str r3, [r7, #28] return(result); 8005f42: 69fb ldr r3, [r7, #28] 8005f44: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8005f48: f023 0301 bic.w r3, r3, #1 8005f4c: 64bb str r3, [r7, #72] @ 0x48 8005f4e: 687b ldr r3, [r7, #4] 8005f50: 681b ldr r3, [r3, #0] 8005f52: 3308 adds r3, #8 8005f54: 6cba ldr r2, [r7, #72] @ 0x48 8005f56: 62fa str r2, [r7, #44] @ 0x2c 8005f58: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f5a: 6ab9 ldr r1, [r7, #40] @ 0x28 8005f5c: 6afa ldr r2, [r7, #44] @ 0x2c 8005f5e: e841 2300 strex r3, r2, [r1] 8005f62: 627b str r3, [r7, #36] @ 0x24 return(result); 8005f64: 6a7b ldr r3, [r7, #36] @ 0x24 8005f66: 2b00 cmp r3, #0 8005f68: d1e3 bne.n 8005f32 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8005f6a: 687b ldr r3, [r7, #4] 8005f6c: 6edb ldr r3, [r3, #108] @ 0x6c 8005f6e: 2b01 cmp r3, #1 8005f70: d118 bne.n 8005fa4 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8005f72: 687b ldr r3, [r7, #4] 8005f74: 681b ldr r3, [r3, #0] 8005f76: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005f78: 68fb ldr r3, [r7, #12] 8005f7a: e853 3f00 ldrex r3, [r3] 8005f7e: 60bb str r3, [r7, #8] return(result); 8005f80: 68bb ldr r3, [r7, #8] 8005f82: f023 0310 bic.w r3, r3, #16 8005f86: 647b str r3, [r7, #68] @ 0x44 8005f88: 687b ldr r3, [r7, #4] 8005f8a: 681b ldr r3, [r3, #0] 8005f8c: 461a mov r2, r3 8005f8e: 6c7b ldr r3, [r7, #68] @ 0x44 8005f90: 61bb str r3, [r7, #24] 8005f92: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8005f94: 6979 ldr r1, [r7, #20] 8005f96: 69ba ldr r2, [r7, #24] 8005f98: e841 2300 strex r3, r2, [r1] 8005f9c: 613b str r3, [r7, #16] return(result); 8005f9e: 693b ldr r3, [r7, #16] 8005fa0: 2b00 cmp r3, #0 8005fa2: d1e6 bne.n 8005f72 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005fa4: 687b ldr r3, [r7, #4] 8005fa6: 2220 movs r2, #32 8005fa8: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8005fac: 687b ldr r3, [r7, #4] 8005fae: 2200 movs r2, #0 8005fb0: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8005fb2: 687b ldr r3, [r7, #4] 8005fb4: 2200 movs r2, #0 8005fb6: 675a str r2, [r3, #116] @ 0x74 } 8005fb8: bf00 nop 8005fba: 3754 adds r7, #84 @ 0x54 8005fbc: 46bd mov sp, r7 8005fbe: f85d 7b04 ldr.w r7, [sp], #4 8005fc2: 4770 bx lr 08005fc4 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8005fc4: b580 push {r7, lr} 8005fc6: b084 sub sp, #16 8005fc8: af00 add r7, sp, #0 8005fca: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8005fcc: 687b ldr r3, [r7, #4] 8005fce: 6a9b ldr r3, [r3, #40] @ 0x28 8005fd0: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 8005fd2: 68fb ldr r3, [r7, #12] 8005fd4: 2200 movs r2, #0 8005fd6: f8a3 205e strh.w r2, [r3, #94] @ 0x5e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8005fda: 68f8 ldr r0, [r7, #12] 8005fdc: f7ff f9ce bl 800537c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8005fe0: bf00 nop 8005fe2: 3710 adds r7, #16 8005fe4: 46bd mov sp, r7 8005fe6: bd80 pop {r7, pc} 08005fe8 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 8005fe8: b580 push {r7, lr} 8005fea: b088 sub sp, #32 8005fec: af00 add r7, sp, #0 8005fee: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8005ff0: 687b ldr r3, [r7, #4] 8005ff2: 681b ldr r3, [r3, #0] 8005ff4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8005ff6: 68fb ldr r3, [r7, #12] 8005ff8: e853 3f00 ldrex r3, [r3] 8005ffc: 60bb str r3, [r7, #8] return(result); 8005ffe: 68bb ldr r3, [r7, #8] 8006000: f023 0340 bic.w r3, r3, #64 @ 0x40 8006004: 61fb str r3, [r7, #28] 8006006: 687b ldr r3, [r7, #4] 8006008: 681b ldr r3, [r3, #0] 800600a: 461a mov r2, r3 800600c: 69fb ldr r3, [r7, #28] 800600e: 61bb str r3, [r7, #24] 8006010: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006012: 6979 ldr r1, [r7, #20] 8006014: 69ba ldr r2, [r7, #24] 8006016: e841 2300 strex r3, r2, [r1] 800601a: 613b str r3, [r7, #16] return(result); 800601c: 693b ldr r3, [r7, #16] 800601e: 2b00 cmp r3, #0 8006020: d1e6 bne.n 8005ff0 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006022: 687b ldr r3, [r7, #4] 8006024: 2220 movs r2, #32 8006026: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 800602a: 687b ldr r3, [r7, #4] 800602c: 2200 movs r2, #0 800602e: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8006030: 6878 ldr r0, [r7, #4] 8006032: f7fa fdc1 bl 8000bb8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8006036: bf00 nop 8006038: 3720 adds r7, #32 800603a: 46bd mov sp, r7 800603c: bd80 pop {r7, pc} ... 08006040 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8006040: b580 push {r7, lr} 8006042: b09c sub sp, #112 @ 0x70 8006044: af00 add r7, sp, #0 8006046: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8006048: 687b ldr r3, [r7, #4] 800604a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 800604e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006052: 687b ldr r3, [r7, #4] 8006054: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8006058: 2b22 cmp r3, #34 @ 0x22 800605a: f040 80be bne.w 80061da { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800605e: 687b ldr r3, [r7, #4] 8006060: 681b ldr r3, [r3, #0] 8006062: 6a5b ldr r3, [r3, #36] @ 0x24 8006064: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8006068: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 800606c: b2d9 uxtb r1, r3 800606e: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8006072: b2da uxtb r2, r3 8006074: 687b ldr r3, [r7, #4] 8006076: 6d9b ldr r3, [r3, #88] @ 0x58 8006078: 400a ands r2, r1 800607a: b2d2 uxtb r2, r2 800607c: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 800607e: 687b ldr r3, [r7, #4] 8006080: 6d9b ldr r3, [r3, #88] @ 0x58 8006082: 1c5a adds r2, r3, #1 8006084: 687b ldr r3, [r7, #4] 8006086: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8006088: 687b ldr r3, [r7, #4] 800608a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800608e: b29b uxth r3, r3 8006090: 3b01 subs r3, #1 8006092: b29a uxth r2, r3 8006094: 687b ldr r3, [r7, #4] 8006096: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 800609a: 687b ldr r3, [r7, #4] 800609c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80060a0: b29b uxth r3, r3 80060a2: 2b00 cmp r3, #0 80060a4: f040 80a1 bne.w 80061ea { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80060a8: 687b ldr r3, [r7, #4] 80060aa: 681b ldr r3, [r3, #0] 80060ac: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060ae: 6cfb ldr r3, [r7, #76] @ 0x4c 80060b0: e853 3f00 ldrex r3, [r3] 80060b4: 64bb str r3, [r7, #72] @ 0x48 return(result); 80060b6: 6cbb ldr r3, [r7, #72] @ 0x48 80060b8: f423 7390 bic.w r3, r3, #288 @ 0x120 80060bc: 66bb str r3, [r7, #104] @ 0x68 80060be: 687b ldr r3, [r7, #4] 80060c0: 681b ldr r3, [r3, #0] 80060c2: 461a mov r2, r3 80060c4: 6ebb ldr r3, [r7, #104] @ 0x68 80060c6: 65bb str r3, [r7, #88] @ 0x58 80060c8: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80060ca: 6d79 ldr r1, [r7, #84] @ 0x54 80060cc: 6dba ldr r2, [r7, #88] @ 0x58 80060ce: e841 2300 strex r3, r2, [r1] 80060d2: 653b str r3, [r7, #80] @ 0x50 return(result); 80060d4: 6d3b ldr r3, [r7, #80] @ 0x50 80060d6: 2b00 cmp r3, #0 80060d8: d1e6 bne.n 80060a8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80060da: 687b ldr r3, [r7, #4] 80060dc: 681b ldr r3, [r3, #0] 80060de: 3308 adds r3, #8 80060e0: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80060e2: 6bbb ldr r3, [r7, #56] @ 0x38 80060e4: e853 3f00 ldrex r3, [r3] 80060e8: 637b str r3, [r7, #52] @ 0x34 return(result); 80060ea: 6b7b ldr r3, [r7, #52] @ 0x34 80060ec: f023 0301 bic.w r3, r3, #1 80060f0: 667b str r3, [r7, #100] @ 0x64 80060f2: 687b ldr r3, [r7, #4] 80060f4: 681b ldr r3, [r3, #0] 80060f6: 3308 adds r3, #8 80060f8: 6e7a ldr r2, [r7, #100] @ 0x64 80060fa: 647a str r2, [r7, #68] @ 0x44 80060fc: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80060fe: 6c39 ldr r1, [r7, #64] @ 0x40 8006100: 6c7a ldr r2, [r7, #68] @ 0x44 8006102: e841 2300 strex r3, r2, [r1] 8006106: 63fb str r3, [r7, #60] @ 0x3c return(result); 8006108: 6bfb ldr r3, [r7, #60] @ 0x3c 800610a: 2b00 cmp r3, #0 800610c: d1e5 bne.n 80060da /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800610e: 687b ldr r3, [r7, #4] 8006110: 2220 movs r2, #32 8006112: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8006116: 687b ldr r3, [r7, #4] 8006118: 2200 movs r2, #0 800611a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800611c: 687b ldr r3, [r7, #4] 800611e: 2200 movs r2, #0 8006120: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8006122: 687b ldr r3, [r7, #4] 8006124: 681b ldr r3, [r3, #0] 8006126: 4a33 ldr r2, [pc, #204] @ (80061f4 ) 8006128: 4293 cmp r3, r2 800612a: d01f beq.n 800616c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800612c: 687b ldr r3, [r7, #4] 800612e: 681b ldr r3, [r3, #0] 8006130: 685b ldr r3, [r3, #4] 8006132: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006136: 2b00 cmp r3, #0 8006138: d018 beq.n 800616c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800613a: 687b ldr r3, [r7, #4] 800613c: 681b ldr r3, [r3, #0] 800613e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006140: 6a7b ldr r3, [r7, #36] @ 0x24 8006142: e853 3f00 ldrex r3, [r3] 8006146: 623b str r3, [r7, #32] return(result); 8006148: 6a3b ldr r3, [r7, #32] 800614a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800614e: 663b str r3, [r7, #96] @ 0x60 8006150: 687b ldr r3, [r7, #4] 8006152: 681b ldr r3, [r3, #0] 8006154: 461a mov r2, r3 8006156: 6e3b ldr r3, [r7, #96] @ 0x60 8006158: 633b str r3, [r7, #48] @ 0x30 800615a: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800615c: 6af9 ldr r1, [r7, #44] @ 0x2c 800615e: 6b3a ldr r2, [r7, #48] @ 0x30 8006160: e841 2300 strex r3, r2, [r1] 8006164: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006166: 6abb ldr r3, [r7, #40] @ 0x28 8006168: 2b00 cmp r3, #0 800616a: d1e6 bne.n 800613a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800616c: 687b ldr r3, [r7, #4] 800616e: 6edb ldr r3, [r3, #108] @ 0x6c 8006170: 2b01 cmp r3, #1 8006172: d12e bne.n 80061d2 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006174: 687b ldr r3, [r7, #4] 8006176: 2200 movs r2, #0 8006178: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800617a: 687b ldr r3, [r7, #4] 800617c: 681b ldr r3, [r3, #0] 800617e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006180: 693b ldr r3, [r7, #16] 8006182: e853 3f00 ldrex r3, [r3] 8006186: 60fb str r3, [r7, #12] return(result); 8006188: 68fb ldr r3, [r7, #12] 800618a: f023 0310 bic.w r3, r3, #16 800618e: 65fb str r3, [r7, #92] @ 0x5c 8006190: 687b ldr r3, [r7, #4] 8006192: 681b ldr r3, [r3, #0] 8006194: 461a mov r2, r3 8006196: 6dfb ldr r3, [r7, #92] @ 0x5c 8006198: 61fb str r3, [r7, #28] 800619a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800619c: 69b9 ldr r1, [r7, #24] 800619e: 69fa ldr r2, [r7, #28] 80061a0: e841 2300 strex r3, r2, [r1] 80061a4: 617b str r3, [r7, #20] return(result); 80061a6: 697b ldr r3, [r7, #20] 80061a8: 2b00 cmp r3, #0 80061aa: d1e6 bne.n 800617a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80061ac: 687b ldr r3, [r7, #4] 80061ae: 681b ldr r3, [r3, #0] 80061b0: 69db ldr r3, [r3, #28] 80061b2: f003 0310 and.w r3, r3, #16 80061b6: 2b10 cmp r3, #16 80061b8: d103 bne.n 80061c2 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80061ba: 687b ldr r3, [r7, #4] 80061bc: 681b ldr r3, [r3, #0] 80061be: 2210 movs r2, #16 80061c0: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80061c2: 687b ldr r3, [r7, #4] 80061c4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80061c8: 4619 mov r1, r3 80061ca: 6878 ldr r0, [r7, #4] 80061cc: f7ff f8e0 bl 8005390 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80061d0: e00b b.n 80061ea HAL_UART_RxCpltCallback(huart); 80061d2: 6878 ldr r0, [r7, #4] 80061d4: f7fa fcfa bl 8000bcc } 80061d8: e007 b.n 80061ea __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80061da: 687b ldr r3, [r7, #4] 80061dc: 681b ldr r3, [r3, #0] 80061de: 699a ldr r2, [r3, #24] 80061e0: 687b ldr r3, [r7, #4] 80061e2: 681b ldr r3, [r3, #0] 80061e4: f042 0208 orr.w r2, r2, #8 80061e8: 619a str r2, [r3, #24] } 80061ea: bf00 nop 80061ec: 3770 adds r7, #112 @ 0x70 80061ee: 46bd mov sp, r7 80061f0: bd80 pop {r7, pc} 80061f2: bf00 nop 80061f4: 40008000 .word 0x40008000 080061f8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 80061f8: b580 push {r7, lr} 80061fa: b09c sub sp, #112 @ 0x70 80061fc: af00 add r7, sp, #0 80061fe: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8006200: 687b ldr r3, [r7, #4] 8006202: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8006206: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800620a: 687b ldr r3, [r7, #4] 800620c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8006210: 2b22 cmp r3, #34 @ 0x22 8006212: f040 80be bne.w 8006392 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8006216: 687b ldr r3, [r7, #4] 8006218: 681b ldr r3, [r3, #0] 800621a: 6a5b ldr r3, [r3, #36] @ 0x24 800621c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8006220: 687b ldr r3, [r7, #4] 8006222: 6d9b ldr r3, [r3, #88] @ 0x58 8006224: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 8006226: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 800622a: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 800622e: 4013 ands r3, r2 8006230: b29a uxth r2, r3 8006232: 6ebb ldr r3, [r7, #104] @ 0x68 8006234: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006236: 687b ldr r3, [r7, #4] 8006238: 6d9b ldr r3, [r3, #88] @ 0x58 800623a: 1c9a adds r2, r3, #2 800623c: 687b ldr r3, [r7, #4] 800623e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8006240: 687b ldr r3, [r7, #4] 8006242: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006246: b29b uxth r3, r3 8006248: 3b01 subs r3, #1 800624a: b29a uxth r2, r3 800624c: 687b ldr r3, [r7, #4] 800624e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8006252: 687b ldr r3, [r7, #4] 8006254: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006258: b29b uxth r3, r3 800625a: 2b00 cmp r3, #0 800625c: f040 80a1 bne.w 80063a2 { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8006260: 687b ldr r3, [r7, #4] 8006262: 681b ldr r3, [r3, #0] 8006264: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006266: 6cbb ldr r3, [r7, #72] @ 0x48 8006268: e853 3f00 ldrex r3, [r3] 800626c: 647b str r3, [r7, #68] @ 0x44 return(result); 800626e: 6c7b ldr r3, [r7, #68] @ 0x44 8006270: f423 7390 bic.w r3, r3, #288 @ 0x120 8006274: 667b str r3, [r7, #100] @ 0x64 8006276: 687b ldr r3, [r7, #4] 8006278: 681b ldr r3, [r3, #0] 800627a: 461a mov r2, r3 800627c: 6e7b ldr r3, [r7, #100] @ 0x64 800627e: 657b str r3, [r7, #84] @ 0x54 8006280: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006282: 6d39 ldr r1, [r7, #80] @ 0x50 8006284: 6d7a ldr r2, [r7, #84] @ 0x54 8006286: e841 2300 strex r3, r2, [r1] 800628a: 64fb str r3, [r7, #76] @ 0x4c return(result); 800628c: 6cfb ldr r3, [r7, #76] @ 0x4c 800628e: 2b00 cmp r3, #0 8006290: d1e6 bne.n 8006260 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8006292: 687b ldr r3, [r7, #4] 8006294: 681b ldr r3, [r3, #0] 8006296: 3308 adds r3, #8 8006298: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800629a: 6b7b ldr r3, [r7, #52] @ 0x34 800629c: e853 3f00 ldrex r3, [r3] 80062a0: 633b str r3, [r7, #48] @ 0x30 return(result); 80062a2: 6b3b ldr r3, [r7, #48] @ 0x30 80062a4: f023 0301 bic.w r3, r3, #1 80062a8: 663b str r3, [r7, #96] @ 0x60 80062aa: 687b ldr r3, [r7, #4] 80062ac: 681b ldr r3, [r3, #0] 80062ae: 3308 adds r3, #8 80062b0: 6e3a ldr r2, [r7, #96] @ 0x60 80062b2: 643a str r2, [r7, #64] @ 0x40 80062b4: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80062b6: 6bf9 ldr r1, [r7, #60] @ 0x3c 80062b8: 6c3a ldr r2, [r7, #64] @ 0x40 80062ba: e841 2300 strex r3, r2, [r1] 80062be: 63bb str r3, [r7, #56] @ 0x38 return(result); 80062c0: 6bbb ldr r3, [r7, #56] @ 0x38 80062c2: 2b00 cmp r3, #0 80062c4: d1e5 bne.n 8006292 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80062c6: 687b ldr r3, [r7, #4] 80062c8: 2220 movs r2, #32 80062ca: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80062ce: 687b ldr r3, [r7, #4] 80062d0: 2200 movs r2, #0 80062d2: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80062d4: 687b ldr r3, [r7, #4] 80062d6: 2200 movs r2, #0 80062d8: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80062da: 687b ldr r3, [r7, #4] 80062dc: 681b ldr r3, [r3, #0] 80062de: 4a33 ldr r2, [pc, #204] @ (80063ac ) 80062e0: 4293 cmp r3, r2 80062e2: d01f beq.n 8006324 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80062e4: 687b ldr r3, [r7, #4] 80062e6: 681b ldr r3, [r3, #0] 80062e8: 685b ldr r3, [r3, #4] 80062ea: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80062ee: 2b00 cmp r3, #0 80062f0: d018 beq.n 8006324 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80062f2: 687b ldr r3, [r7, #4] 80062f4: 681b ldr r3, [r3, #0] 80062f6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80062f8: 6a3b ldr r3, [r7, #32] 80062fa: e853 3f00 ldrex r3, [r3] 80062fe: 61fb str r3, [r7, #28] return(result); 8006300: 69fb ldr r3, [r7, #28] 8006302: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8006306: 65fb str r3, [r7, #92] @ 0x5c 8006308: 687b ldr r3, [r7, #4] 800630a: 681b ldr r3, [r3, #0] 800630c: 461a mov r2, r3 800630e: 6dfb ldr r3, [r7, #92] @ 0x5c 8006310: 62fb str r3, [r7, #44] @ 0x2c 8006312: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006314: 6ab9 ldr r1, [r7, #40] @ 0x28 8006316: 6afa ldr r2, [r7, #44] @ 0x2c 8006318: e841 2300 strex r3, r2, [r1] 800631c: 627b str r3, [r7, #36] @ 0x24 return(result); 800631e: 6a7b ldr r3, [r7, #36] @ 0x24 8006320: 2b00 cmp r3, #0 8006322: d1e6 bne.n 80062f2 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006324: 687b ldr r3, [r7, #4] 8006326: 6edb ldr r3, [r3, #108] @ 0x6c 8006328: 2b01 cmp r3, #1 800632a: d12e bne.n 800638a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800632c: 687b ldr r3, [r7, #4] 800632e: 2200 movs r2, #0 8006330: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8006332: 687b ldr r3, [r7, #4] 8006334: 681b ldr r3, [r3, #0] 8006336: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006338: 68fb ldr r3, [r7, #12] 800633a: e853 3f00 ldrex r3, [r3] 800633e: 60bb str r3, [r7, #8] return(result); 8006340: 68bb ldr r3, [r7, #8] 8006342: f023 0310 bic.w r3, r3, #16 8006346: 65bb str r3, [r7, #88] @ 0x58 8006348: 687b ldr r3, [r7, #4] 800634a: 681b ldr r3, [r3, #0] 800634c: 461a mov r2, r3 800634e: 6dbb ldr r3, [r7, #88] @ 0x58 8006350: 61bb str r3, [r7, #24] 8006352: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006354: 6979 ldr r1, [r7, #20] 8006356: 69ba ldr r2, [r7, #24] 8006358: e841 2300 strex r3, r2, [r1] 800635c: 613b str r3, [r7, #16] return(result); 800635e: 693b ldr r3, [r7, #16] 8006360: 2b00 cmp r3, #0 8006362: d1e6 bne.n 8006332 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006364: 687b ldr r3, [r7, #4] 8006366: 681b ldr r3, [r3, #0] 8006368: 69db ldr r3, [r3, #28] 800636a: f003 0310 and.w r3, r3, #16 800636e: 2b10 cmp r3, #16 8006370: d103 bne.n 800637a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006372: 687b ldr r3, [r7, #4] 8006374: 681b ldr r3, [r3, #0] 8006376: 2210 movs r2, #16 8006378: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800637a: 687b ldr r3, [r7, #4] 800637c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8006380: 4619 mov r1, r3 8006382: 6878 ldr r0, [r7, #4] 8006384: f7ff f804 bl 8005390 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006388: e00b b.n 80063a2 HAL_UART_RxCpltCallback(huart); 800638a: 6878 ldr r0, [r7, #4] 800638c: f7fa fc1e bl 8000bcc } 8006390: e007 b.n 80063a2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8006392: 687b ldr r3, [r7, #4] 8006394: 681b ldr r3, [r3, #0] 8006396: 699a ldr r2, [r3, #24] 8006398: 687b ldr r3, [r7, #4] 800639a: 681b ldr r3, [r3, #0] 800639c: f042 0208 orr.w r2, r2, #8 80063a0: 619a str r2, [r3, #24] } 80063a2: bf00 nop 80063a4: 3770 adds r7, #112 @ 0x70 80063a6: 46bd mov sp, r7 80063a8: bd80 pop {r7, pc} 80063aa: bf00 nop 80063ac: 40008000 .word 0x40008000 080063b0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 80063b0: b580 push {r7, lr} 80063b2: b0ac sub sp, #176 @ 0xb0 80063b4: af00 add r7, sp, #0 80063b6: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80063b8: 687b ldr r3, [r7, #4] 80063ba: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80063be: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 80063c2: 687b ldr r3, [r7, #4] 80063c4: 681b ldr r3, [r3, #0] 80063c6: 69db ldr r3, [r3, #28] 80063c8: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 80063cc: 687b ldr r3, [r7, #4] 80063ce: 681b ldr r3, [r3, #0] 80063d0: 681b ldr r3, [r3, #0] 80063d2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80063d6: 687b ldr r3, [r7, #4] 80063d8: 681b ldr r3, [r3, #0] 80063da: 689b ldr r3, [r3, #8] 80063dc: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80063e0: 687b ldr r3, [r7, #4] 80063e2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80063e6: 2b22 cmp r3, #34 @ 0x22 80063e8: f040 8183 bne.w 80066f2 { nb_rx_data = huart->NbRxDataToProcess; 80063ec: 687b ldr r3, [r7, #4] 80063ee: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80063f2: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80063f6: e126 b.n 8006646 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80063f8: 687b ldr r3, [r7, #4] 80063fa: 681b ldr r3, [r3, #0] 80063fc: 6a5b ldr r3, [r3, #36] @ 0x24 80063fe: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8006402: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8006406: b2d9 uxtb r1, r3 8006408: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 800640c: b2da uxtb r2, r3 800640e: 687b ldr r3, [r7, #4] 8006410: 6d9b ldr r3, [r3, #88] @ 0x58 8006412: 400a ands r2, r1 8006414: b2d2 uxtb r2, r2 8006416: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8006418: 687b ldr r3, [r7, #4] 800641a: 6d9b ldr r3, [r3, #88] @ 0x58 800641c: 1c5a adds r2, r3, #1 800641e: 687b ldr r3, [r7, #4] 8006420: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8006422: 687b ldr r3, [r7, #4] 8006424: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006428: b29b uxth r3, r3 800642a: 3b01 subs r3, #1 800642c: b29a uxth r2, r3 800642e: 687b ldr r3, [r7, #4] 8006430: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8006434: 687b ldr r3, [r7, #4] 8006436: 681b ldr r3, [r3, #0] 8006438: 69db ldr r3, [r3, #28] 800643a: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 800643e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8006442: f003 0307 and.w r3, r3, #7 8006446: 2b00 cmp r3, #0 8006448: d053 beq.n 80064f2 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800644a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800644e: f003 0301 and.w r3, r3, #1 8006452: 2b00 cmp r3, #0 8006454: d011 beq.n 800647a 8006456: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800645a: f403 7380 and.w r3, r3, #256 @ 0x100 800645e: 2b00 cmp r3, #0 8006460: d00b beq.n 800647a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8006462: 687b ldr r3, [r7, #4] 8006464: 681b ldr r3, [r3, #0] 8006466: 2201 movs r2, #1 8006468: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800646a: 687b ldr r3, [r7, #4] 800646c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006470: f043 0201 orr.w r2, r3, #1 8006474: 687b ldr r3, [r7, #4] 8006476: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800647a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800647e: f003 0302 and.w r3, r3, #2 8006482: 2b00 cmp r3, #0 8006484: d011 beq.n 80064aa 8006486: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800648a: f003 0301 and.w r3, r3, #1 800648e: 2b00 cmp r3, #0 8006490: d00b beq.n 80064aa { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8006492: 687b ldr r3, [r7, #4] 8006494: 681b ldr r3, [r3, #0] 8006496: 2202 movs r2, #2 8006498: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800649a: 687b ldr r3, [r7, #4] 800649c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80064a0: f043 0204 orr.w r2, r3, #4 80064a4: 687b ldr r3, [r7, #4] 80064a6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80064aa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80064ae: f003 0304 and.w r3, r3, #4 80064b2: 2b00 cmp r3, #0 80064b4: d011 beq.n 80064da 80064b6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80064ba: f003 0301 and.w r3, r3, #1 80064be: 2b00 cmp r3, #0 80064c0: d00b beq.n 80064da { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 80064c2: 687b ldr r3, [r7, #4] 80064c4: 681b ldr r3, [r3, #0] 80064c6: 2204 movs r2, #4 80064c8: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80064ca: 687b ldr r3, [r7, #4] 80064cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80064d0: f043 0202 orr.w r2, r3, #2 80064d4: 687b ldr r3, [r7, #4] 80064d6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80064da: 687b ldr r3, [r7, #4] 80064dc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80064e0: 2b00 cmp r3, #0 80064e2: d006 beq.n 80064f2 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80064e4: 6878 ldr r0, [r7, #4] 80064e6: f7fe ff49 bl 800537c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80064ea: 687b ldr r3, [r7, #4] 80064ec: 2200 movs r2, #0 80064ee: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 80064f2: 687b ldr r3, [r7, #4] 80064f4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80064f8: b29b uxth r3, r3 80064fa: 2b00 cmp r3, #0 80064fc: f040 80a3 bne.w 8006646 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006500: 687b ldr r3, [r7, #4] 8006502: 681b ldr r3, [r3, #0] 8006504: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006506: 6f3b ldr r3, [r7, #112] @ 0x70 8006508: e853 3f00 ldrex r3, [r3] 800650c: 66fb str r3, [r7, #108] @ 0x6c return(result); 800650e: 6efb ldr r3, [r7, #108] @ 0x6c 8006510: f423 7380 bic.w r3, r3, #256 @ 0x100 8006514: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006518: 687b ldr r3, [r7, #4] 800651a: 681b ldr r3, [r3, #0] 800651c: 461a mov r2, r3 800651e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8006522: 67fb str r3, [r7, #124] @ 0x7c 8006524: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006526: 6fb9 ldr r1, [r7, #120] @ 0x78 8006528: 6ffa ldr r2, [r7, #124] @ 0x7c 800652a: e841 2300 strex r3, r2, [r1] 800652e: 677b str r3, [r7, #116] @ 0x74 return(result); 8006530: 6f7b ldr r3, [r7, #116] @ 0x74 8006532: 2b00 cmp r3, #0 8006534: d1e4 bne.n 8006500 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8006536: 687b ldr r3, [r7, #4] 8006538: 681b ldr r3, [r3, #0] 800653a: 3308 adds r3, #8 800653c: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800653e: 6dfb ldr r3, [r7, #92] @ 0x5c 8006540: e853 3f00 ldrex r3, [r3] 8006544: 65bb str r3, [r7, #88] @ 0x58 return(result); 8006546: 6dbb ldr r3, [r7, #88] @ 0x58 8006548: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800654c: f023 0301 bic.w r3, r3, #1 8006550: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8006554: 687b ldr r3, [r7, #4] 8006556: 681b ldr r3, [r3, #0] 8006558: 3308 adds r3, #8 800655a: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800655e: 66ba str r2, [r7, #104] @ 0x68 8006560: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006562: 6e79 ldr r1, [r7, #100] @ 0x64 8006564: 6eba ldr r2, [r7, #104] @ 0x68 8006566: e841 2300 strex r3, r2, [r1] 800656a: 663b str r3, [r7, #96] @ 0x60 return(result); 800656c: 6e3b ldr r3, [r7, #96] @ 0x60 800656e: 2b00 cmp r3, #0 8006570: d1e1 bne.n 8006536 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8006572: 687b ldr r3, [r7, #4] 8006574: 2220 movs r2, #32 8006576: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 800657a: 687b ldr r3, [r7, #4] 800657c: 2200 movs r2, #0 800657e: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8006580: 687b ldr r3, [r7, #4] 8006582: 2200 movs r2, #0 8006584: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8006586: 687b ldr r3, [r7, #4] 8006588: 681b ldr r3, [r3, #0] 800658a: 4a60 ldr r2, [pc, #384] @ (800670c ) 800658c: 4293 cmp r3, r2 800658e: d021 beq.n 80065d4 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8006590: 687b ldr r3, [r7, #4] 8006592: 681b ldr r3, [r3, #0] 8006594: 685b ldr r3, [r3, #4] 8006596: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800659a: 2b00 cmp r3, #0 800659c: d01a beq.n 80065d4 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800659e: 687b ldr r3, [r7, #4] 80065a0: 681b ldr r3, [r3, #0] 80065a2: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80065a4: 6cbb ldr r3, [r7, #72] @ 0x48 80065a6: e853 3f00 ldrex r3, [r3] 80065aa: 647b str r3, [r7, #68] @ 0x44 return(result); 80065ac: 6c7b ldr r3, [r7, #68] @ 0x44 80065ae: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80065b2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80065b6: 687b ldr r3, [r7, #4] 80065b8: 681b ldr r3, [r3, #0] 80065ba: 461a mov r2, r3 80065bc: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80065c0: 657b str r3, [r7, #84] @ 0x54 80065c2: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80065c4: 6d39 ldr r1, [r7, #80] @ 0x50 80065c6: 6d7a ldr r2, [r7, #84] @ 0x54 80065c8: e841 2300 strex r3, r2, [r1] 80065cc: 64fb str r3, [r7, #76] @ 0x4c return(result); 80065ce: 6cfb ldr r3, [r7, #76] @ 0x4c 80065d0: 2b00 cmp r3, #0 80065d2: d1e4 bne.n 800659e } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80065d4: 687b ldr r3, [r7, #4] 80065d6: 6edb ldr r3, [r3, #108] @ 0x6c 80065d8: 2b01 cmp r3, #1 80065da: d130 bne.n 800663e { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80065dc: 687b ldr r3, [r7, #4] 80065de: 2200 movs r2, #0 80065e0: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80065e2: 687b ldr r3, [r7, #4] 80065e4: 681b ldr r3, [r3, #0] 80065e6: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80065e8: 6b7b ldr r3, [r7, #52] @ 0x34 80065ea: e853 3f00 ldrex r3, [r3] 80065ee: 633b str r3, [r7, #48] @ 0x30 return(result); 80065f0: 6b3b ldr r3, [r7, #48] @ 0x30 80065f2: f023 0310 bic.w r3, r3, #16 80065f6: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80065fa: 687b ldr r3, [r7, #4] 80065fc: 681b ldr r3, [r3, #0] 80065fe: 461a mov r2, r3 8006600: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8006604: 643b str r3, [r7, #64] @ 0x40 8006606: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006608: 6bf9 ldr r1, [r7, #60] @ 0x3c 800660a: 6c3a ldr r2, [r7, #64] @ 0x40 800660c: e841 2300 strex r3, r2, [r1] 8006610: 63bb str r3, [r7, #56] @ 0x38 return(result); 8006612: 6bbb ldr r3, [r7, #56] @ 0x38 8006614: 2b00 cmp r3, #0 8006616: d1e4 bne.n 80065e2 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006618: 687b ldr r3, [r7, #4] 800661a: 681b ldr r3, [r3, #0] 800661c: 69db ldr r3, [r3, #28] 800661e: f003 0310 and.w r3, r3, #16 8006622: 2b10 cmp r3, #16 8006624: d103 bne.n 800662e { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006626: 687b ldr r3, [r7, #4] 8006628: 681b ldr r3, [r3, #0] 800662a: 2210 movs r2, #16 800662c: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800662e: 687b ldr r3, [r7, #4] 8006630: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8006634: 4619 mov r1, r3 8006636: 6878 ldr r0, [r7, #4] 8006638: f7fe feaa bl 8005390 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; 800663c: e00e b.n 800665c HAL_UART_RxCpltCallback(huart); 800663e: 6878 ldr r0, [r7, #4] 8006640: f7fa fac4 bl 8000bcc break; 8006644: e00a b.n 800665c while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8006646: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 800664a: 2b00 cmp r3, #0 800664c: d006 beq.n 800665c 800664e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8006652: f003 0320 and.w r3, r3, #32 8006656: 2b00 cmp r3, #0 8006658: f47f aece bne.w 80063f8 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 800665c: 687b ldr r3, [r7, #4] 800665e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006662: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8006666: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 800666a: 2b00 cmp r3, #0 800666c: d049 beq.n 8006702 800666e: 687b ldr r3, [r7, #4] 8006670: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8006674: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8006678: 429a cmp r2, r3 800667a: d242 bcs.n 8006702 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800667c: 687b ldr r3, [r7, #4] 800667e: 681b ldr r3, [r3, #0] 8006680: 3308 adds r3, #8 8006682: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006684: 6a3b ldr r3, [r7, #32] 8006686: e853 3f00 ldrex r3, [r3] 800668a: 61fb str r3, [r7, #28] return(result); 800668c: 69fb ldr r3, [r7, #28] 800668e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8006692: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006696: 687b ldr r3, [r7, #4] 8006698: 681b ldr r3, [r3, #0] 800669a: 3308 adds r3, #8 800669c: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 80066a0: 62fa str r2, [r7, #44] @ 0x2c 80066a2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066a4: 6ab9 ldr r1, [r7, #40] @ 0x28 80066a6: 6afa ldr r2, [r7, #44] @ 0x2c 80066a8: e841 2300 strex r3, r2, [r1] 80066ac: 627b str r3, [r7, #36] @ 0x24 return(result); 80066ae: 6a7b ldr r3, [r7, #36] @ 0x24 80066b0: 2b00 cmp r3, #0 80066b2: d1e3 bne.n 800667c /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 80066b4: 687b ldr r3, [r7, #4] 80066b6: 4a16 ldr r2, [pc, #88] @ (8006710 ) 80066b8: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 80066ba: 687b ldr r3, [r7, #4] 80066bc: 681b ldr r3, [r3, #0] 80066be: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80066c0: 68fb ldr r3, [r7, #12] 80066c2: e853 3f00 ldrex r3, [r3] 80066c6: 60bb str r3, [r7, #8] return(result); 80066c8: 68bb ldr r3, [r7, #8] 80066ca: f043 0320 orr.w r3, r3, #32 80066ce: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80066d2: 687b ldr r3, [r7, #4] 80066d4: 681b ldr r3, [r3, #0] 80066d6: 461a mov r2, r3 80066d8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80066dc: 61bb str r3, [r7, #24] 80066de: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80066e0: 6979 ldr r1, [r7, #20] 80066e2: 69ba ldr r2, [r7, #24] 80066e4: e841 2300 strex r3, r2, [r1] 80066e8: 613b str r3, [r7, #16] return(result); 80066ea: 693b ldr r3, [r7, #16] 80066ec: 2b00 cmp r3, #0 80066ee: d1e4 bne.n 80066ba else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80066f0: e007 b.n 8006702 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80066f2: 687b ldr r3, [r7, #4] 80066f4: 681b ldr r3, [r3, #0] 80066f6: 699a ldr r2, [r3, #24] 80066f8: 687b ldr r3, [r7, #4] 80066fa: 681b ldr r3, [r3, #0] 80066fc: f042 0208 orr.w r2, r2, #8 8006700: 619a str r2, [r3, #24] } 8006702: bf00 nop 8006704: 37b0 adds r7, #176 @ 0xb0 8006706: 46bd mov sp, r7 8006708: bd80 pop {r7, pc} 800670a: bf00 nop 800670c: 40008000 .word 0x40008000 8006710: 08006041 .word 0x08006041 08006714 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8006714: b580 push {r7, lr} 8006716: b0ae sub sp, #184 @ 0xb8 8006718: af00 add r7, sp, #0 800671a: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 800671c: 687b ldr r3, [r7, #4] 800671e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8006722: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8006726: 687b ldr r3, [r7, #4] 8006728: 681b ldr r3, [r3, #0] 800672a: 69db ldr r3, [r3, #28] 800672c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8006730: 687b ldr r3, [r7, #4] 8006732: 681b ldr r3, [r3, #0] 8006734: 681b ldr r3, [r3, #0] 8006736: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 800673a: 687b ldr r3, [r7, #4] 800673c: 681b ldr r3, [r3, #0] 800673e: 689b ldr r3, [r3, #8] 8006740: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8006744: 687b ldr r3, [r7, #4] 8006746: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800674a: 2b22 cmp r3, #34 @ 0x22 800674c: f040 8187 bne.w 8006a5e { nb_rx_data = huart->NbRxDataToProcess; 8006750: 687b ldr r3, [r7, #4] 8006752: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8006756: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800675a: e12a b.n 80069b2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800675c: 687b ldr r3, [r7, #4] 800675e: 681b ldr r3, [r3, #0] 8006760: 6a5b ldr r3, [r3, #36] @ 0x24 8006762: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8006766: 687b ldr r3, [r7, #4] 8006768: 6d9b ldr r3, [r3, #88] @ 0x58 800676a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 800676e: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8006772: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8006776: 4013 ands r3, r2 8006778: b29a uxth r2, r3 800677a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800677e: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8006780: 687b ldr r3, [r7, #4] 8006782: 6d9b ldr r3, [r3, #88] @ 0x58 8006784: 1c9a adds r2, r3, #2 8006786: 687b ldr r3, [r7, #4] 8006788: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 800678a: 687b ldr r3, [r7, #4] 800678c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006790: b29b uxth r3, r3 8006792: 3b01 subs r3, #1 8006794: b29a uxth r2, r3 8006796: 687b ldr r3, [r7, #4] 8006798: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 800679c: 687b ldr r3, [r7, #4] 800679e: 681b ldr r3, [r3, #0] 80067a0: 69db ldr r3, [r3, #28] 80067a2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 80067a6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80067aa: f003 0307 and.w r3, r3, #7 80067ae: 2b00 cmp r3, #0 80067b0: d053 beq.n 800685a { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 80067b2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80067b6: f003 0301 and.w r3, r3, #1 80067ba: 2b00 cmp r3, #0 80067bc: d011 beq.n 80067e2 80067be: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80067c2: f403 7380 and.w r3, r3, #256 @ 0x100 80067c6: 2b00 cmp r3, #0 80067c8: d00b beq.n 80067e2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 80067ca: 687b ldr r3, [r7, #4] 80067cc: 681b ldr r3, [r3, #0] 80067ce: 2201 movs r2, #1 80067d0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 80067d2: 687b ldr r3, [r7, #4] 80067d4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80067d8: f043 0201 orr.w r2, r3, #1 80067dc: 687b ldr r3, [r7, #4] 80067de: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80067e2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80067e6: f003 0302 and.w r3, r3, #2 80067ea: 2b00 cmp r3, #0 80067ec: d011 beq.n 8006812 80067ee: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80067f2: f003 0301 and.w r3, r3, #1 80067f6: 2b00 cmp r3, #0 80067f8: d00b beq.n 8006812 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 80067fa: 687b ldr r3, [r7, #4] 80067fc: 681b ldr r3, [r3, #0] 80067fe: 2202 movs r2, #2 8006800: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8006802: 687b ldr r3, [r7, #4] 8006804: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006808: f043 0204 orr.w r2, r3, #4 800680c: 687b ldr r3, [r7, #4] 800680e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8006812: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8006816: f003 0304 and.w r3, r3, #4 800681a: 2b00 cmp r3, #0 800681c: d011 beq.n 8006842 800681e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8006822: f003 0301 and.w r3, r3, #1 8006826: 2b00 cmp r3, #0 8006828: d00b beq.n 8006842 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800682a: 687b ldr r3, [r7, #4] 800682c: 681b ldr r3, [r3, #0] 800682e: 2204 movs r2, #4 8006830: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8006832: 687b ldr r3, [r7, #4] 8006834: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006838: f043 0202 orr.w r2, r3, #2 800683c: 687b ldr r3, [r7, #4] 800683e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8006842: 687b ldr r3, [r7, #4] 8006844: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8006848: 2b00 cmp r3, #0 800684a: d006 beq.n 800685a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800684c: 6878 ldr r0, [r7, #4] 800684e: f7fe fd95 bl 800537c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8006852: 687b ldr r3, [r7, #4] 8006854: 2200 movs r2, #0 8006856: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 800685a: 687b ldr r3, [r7, #4] 800685c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8006860: b29b uxth r3, r3 8006862: 2b00 cmp r3, #0 8006864: f040 80a5 bne.w 80069b2 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8006868: 687b ldr r3, [r7, #4] 800686a: 681b ldr r3, [r3, #0] 800686c: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800686e: 6f7b ldr r3, [r7, #116] @ 0x74 8006870: e853 3f00 ldrex r3, [r3] 8006874: 673b str r3, [r7, #112] @ 0x70 return(result); 8006876: 6f3b ldr r3, [r7, #112] @ 0x70 8006878: f423 7380 bic.w r3, r3, #256 @ 0x100 800687c: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8006880: 687b ldr r3, [r7, #4] 8006882: 681b ldr r3, [r3, #0] 8006884: 461a mov r2, r3 8006886: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800688a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800688e: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006890: 6ff9 ldr r1, [r7, #124] @ 0x7c 8006892: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8006896: e841 2300 strex r3, r2, [r1] 800689a: 67bb str r3, [r7, #120] @ 0x78 return(result); 800689c: 6fbb ldr r3, [r7, #120] @ 0x78 800689e: 2b00 cmp r3, #0 80068a0: d1e2 bne.n 8006868 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80068a2: 687b ldr r3, [r7, #4] 80068a4: 681b ldr r3, [r3, #0] 80068a6: 3308 adds r3, #8 80068a8: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80068aa: 6e3b ldr r3, [r7, #96] @ 0x60 80068ac: e853 3f00 ldrex r3, [r3] 80068b0: 65fb str r3, [r7, #92] @ 0x5c return(result); 80068b2: 6dfb ldr r3, [r7, #92] @ 0x5c 80068b4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80068b8: f023 0301 bic.w r3, r3, #1 80068bc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80068c0: 687b ldr r3, [r7, #4] 80068c2: 681b ldr r3, [r3, #0] 80068c4: 3308 adds r3, #8 80068c6: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 80068ca: 66fa str r2, [r7, #108] @ 0x6c 80068cc: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80068ce: 6eb9 ldr r1, [r7, #104] @ 0x68 80068d0: 6efa ldr r2, [r7, #108] @ 0x6c 80068d2: e841 2300 strex r3, r2, [r1] 80068d6: 667b str r3, [r7, #100] @ 0x64 return(result); 80068d8: 6e7b ldr r3, [r7, #100] @ 0x64 80068da: 2b00 cmp r3, #0 80068dc: d1e1 bne.n 80068a2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80068de: 687b ldr r3, [r7, #4] 80068e0: 2220 movs r2, #32 80068e2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80068e6: 687b ldr r3, [r7, #4] 80068e8: 2200 movs r2, #0 80068ea: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80068ec: 687b ldr r3, [r7, #4] 80068ee: 2200 movs r2, #0 80068f0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80068f2: 687b ldr r3, [r7, #4] 80068f4: 681b ldr r3, [r3, #0] 80068f6: 4a60 ldr r2, [pc, #384] @ (8006a78 ) 80068f8: 4293 cmp r3, r2 80068fa: d021 beq.n 8006940 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80068fc: 687b ldr r3, [r7, #4] 80068fe: 681b ldr r3, [r3, #0] 8006900: 685b ldr r3, [r3, #4] 8006902: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006906: 2b00 cmp r3, #0 8006908: d01a beq.n 8006940 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800690a: 687b ldr r3, [r7, #4] 800690c: 681b ldr r3, [r3, #0] 800690e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006910: 6cfb ldr r3, [r7, #76] @ 0x4c 8006912: e853 3f00 ldrex r3, [r3] 8006916: 64bb str r3, [r7, #72] @ 0x48 return(result); 8006918: 6cbb ldr r3, [r7, #72] @ 0x48 800691a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800691e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8006922: 687b ldr r3, [r7, #4] 8006924: 681b ldr r3, [r3, #0] 8006926: 461a mov r2, r3 8006928: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800692c: 65bb str r3, [r7, #88] @ 0x58 800692e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006930: 6d79 ldr r1, [r7, #84] @ 0x54 8006932: 6dba ldr r2, [r7, #88] @ 0x58 8006934: e841 2300 strex r3, r2, [r1] 8006938: 653b str r3, [r7, #80] @ 0x50 return(result); 800693a: 6d3b ldr r3, [r7, #80] @ 0x50 800693c: 2b00 cmp r3, #0 800693e: d1e4 bne.n 800690a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8006940: 687b ldr r3, [r7, #4] 8006942: 6edb ldr r3, [r3, #108] @ 0x6c 8006944: 2b01 cmp r3, #1 8006946: d130 bne.n 80069aa { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8006948: 687b ldr r3, [r7, #4] 800694a: 2200 movs r2, #0 800694c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800694e: 687b ldr r3, [r7, #4] 8006950: 681b ldr r3, [r3, #0] 8006952: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006954: 6bbb ldr r3, [r7, #56] @ 0x38 8006956: e853 3f00 ldrex r3, [r3] 800695a: 637b str r3, [r7, #52] @ 0x34 return(result); 800695c: 6b7b ldr r3, [r7, #52] @ 0x34 800695e: f023 0310 bic.w r3, r3, #16 8006962: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006966: 687b ldr r3, [r7, #4] 8006968: 681b ldr r3, [r3, #0] 800696a: 461a mov r2, r3 800696c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8006970: 647b str r3, [r7, #68] @ 0x44 8006972: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006974: 6c39 ldr r1, [r7, #64] @ 0x40 8006976: 6c7a ldr r2, [r7, #68] @ 0x44 8006978: e841 2300 strex r3, r2, [r1] 800697c: 63fb str r3, [r7, #60] @ 0x3c return(result); 800697e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006980: 2b00 cmp r3, #0 8006982: d1e4 bne.n 800694e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8006984: 687b ldr r3, [r7, #4] 8006986: 681b ldr r3, [r3, #0] 8006988: 69db ldr r3, [r3, #28] 800698a: f003 0310 and.w r3, r3, #16 800698e: 2b10 cmp r3, #16 8006990: d103 bne.n 800699a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8006992: 687b ldr r3, [r7, #4] 8006994: 681b ldr r3, [r3, #0] 8006996: 2210 movs r2, #16 8006998: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800699a: 687b ldr r3, [r7, #4] 800699c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80069a0: 4619 mov r1, r3 80069a2: 6878 ldr r0, [r7, #4] 80069a4: f7fe fcf4 bl 8005390 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; 80069a8: e00e b.n 80069c8 HAL_UART_RxCpltCallback(huart); 80069aa: 6878 ldr r0, [r7, #4] 80069ac: f7fa f90e bl 8000bcc break; 80069b0: e00a b.n 80069c8 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80069b2: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 80069b6: 2b00 cmp r3, #0 80069b8: d006 beq.n 80069c8 80069ba: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80069be: f003 0320 and.w r3, r3, #32 80069c2: 2b00 cmp r3, #0 80069c4: f47f aeca bne.w 800675c /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 80069c8: 687b ldr r3, [r7, #4] 80069ca: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80069ce: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 80069d2: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 80069d6: 2b00 cmp r3, #0 80069d8: d049 beq.n 8006a6e 80069da: 687b ldr r3, [r7, #4] 80069dc: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80069e0: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 80069e4: 429a cmp r2, r3 80069e6: d242 bcs.n 8006a6e { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80069e8: 687b ldr r3, [r7, #4] 80069ea: 681b ldr r3, [r3, #0] 80069ec: 3308 adds r3, #8 80069ee: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80069f0: 6a7b ldr r3, [r7, #36] @ 0x24 80069f2: e853 3f00 ldrex r3, [r3] 80069f6: 623b str r3, [r7, #32] return(result); 80069f8: 6a3b ldr r3, [r7, #32] 80069fa: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80069fe: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8006a02: 687b ldr r3, [r7, #4] 8006a04: 681b ldr r3, [r3, #0] 8006a06: 3308 adds r3, #8 8006a08: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8006a0c: 633a str r2, [r7, #48] @ 0x30 8006a0e: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a10: 6af9 ldr r1, [r7, #44] @ 0x2c 8006a12: 6b3a ldr r2, [r7, #48] @ 0x30 8006a14: e841 2300 strex r3, r2, [r1] 8006a18: 62bb str r3, [r7, #40] @ 0x28 return(result); 8006a1a: 6abb ldr r3, [r7, #40] @ 0x28 8006a1c: 2b00 cmp r3, #0 8006a1e: d1e3 bne.n 80069e8 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8006a20: 687b ldr r3, [r7, #4] 8006a22: 4a16 ldr r2, [pc, #88] @ (8006a7c ) 8006a24: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8006a26: 687b ldr r3, [r7, #4] 8006a28: 681b ldr r3, [r3, #0] 8006a2a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8006a2c: 693b ldr r3, [r7, #16] 8006a2e: e853 3f00 ldrex r3, [r3] 8006a32: 60fb str r3, [r7, #12] return(result); 8006a34: 68fb ldr r3, [r7, #12] 8006a36: f043 0320 orr.w r3, r3, #32 8006a3a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006a3e: 687b ldr r3, [r7, #4] 8006a40: 681b ldr r3, [r3, #0] 8006a42: 461a mov r2, r3 8006a44: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8006a48: 61fb str r3, [r7, #28] 8006a4a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8006a4c: 69b9 ldr r1, [r7, #24] 8006a4e: 69fa ldr r2, [r7, #28] 8006a50: e841 2300 strex r3, r2, [r1] 8006a54: 617b str r3, [r7, #20] return(result); 8006a56: 697b ldr r3, [r7, #20] 8006a58: 2b00 cmp r3, #0 8006a5a: d1e4 bne.n 8006a26 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8006a5c: e007 b.n 8006a6e __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8006a5e: 687b ldr r3, [r7, #4] 8006a60: 681b ldr r3, [r3, #0] 8006a62: 699a ldr r2, [r3, #24] 8006a64: 687b ldr r3, [r7, #4] 8006a66: 681b ldr r3, [r3, #0] 8006a68: f042 0208 orr.w r2, r2, #8 8006a6c: 619a str r2, [r3, #24] } 8006a6e: bf00 nop 8006a70: 37b8 adds r7, #184 @ 0xb8 8006a72: 46bd mov sp, r7 8006a74: bd80 pop {r7, pc} 8006a76: bf00 nop 8006a78: 40008000 .word 0x40008000 8006a7c: 080061f9 .word 0x080061f9 08006a80 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8006a80: b480 push {r7} 8006a82: b083 sub sp, #12 8006a84: af00 add r7, sp, #0 8006a86: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8006a88: bf00 nop 8006a8a: 370c adds r7, #12 8006a8c: 46bd mov sp, r7 8006a8e: f85d 7b04 ldr.w r7, [sp], #4 8006a92: 4770 bx lr 08006a94 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8006a94: b480 push {r7} 8006a96: b083 sub sp, #12 8006a98: af00 add r7, sp, #0 8006a9a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8006a9c: bf00 nop 8006a9e: 370c adds r7, #12 8006aa0: 46bd mov sp, r7 8006aa2: f85d 7b04 ldr.w r7, [sp], #4 8006aa6: 4770 bx lr 08006aa8 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8006aa8: b480 push {r7} 8006aaa: b083 sub sp, #12 8006aac: af00 add r7, sp, #0 8006aae: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8006ab0: bf00 nop 8006ab2: 370c adds r7, #12 8006ab4: 46bd mov sp, r7 8006ab6: f85d 7b04 ldr.w r7, [sp], #4 8006aba: 4770 bx lr 08006abc : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8006abc: b480 push {r7} 8006abe: b085 sub sp, #20 8006ac0: af00 add r7, sp, #0 8006ac2: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8006ac4: 687b ldr r3, [r7, #4] 8006ac6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8006aca: 2b01 cmp r3, #1 8006acc: d101 bne.n 8006ad2 8006ace: 2302 movs r3, #2 8006ad0: e027 b.n 8006b22 8006ad2: 687b ldr r3, [r7, #4] 8006ad4: 2201 movs r2, #1 8006ad6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8006ada: 687b ldr r3, [r7, #4] 8006adc: 2224 movs r2, #36 @ 0x24 8006ade: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8006ae2: 687b ldr r3, [r7, #4] 8006ae4: 681b ldr r3, [r3, #0] 8006ae6: 681b ldr r3, [r3, #0] 8006ae8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8006aea: 687b ldr r3, [r7, #4] 8006aec: 681b ldr r3, [r3, #0] 8006aee: 681a ldr r2, [r3, #0] 8006af0: 687b ldr r3, [r7, #4] 8006af2: 681b ldr r3, [r3, #0] 8006af4: f022 0201 bic.w r2, r2, #1 8006af8: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8006afa: 68fb ldr r3, [r7, #12] 8006afc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8006b00: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8006b02: 687b ldr r3, [r7, #4] 8006b04: 2200 movs r2, #0 8006b06: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8006b08: 687b ldr r3, [r7, #4] 8006b0a: 681b ldr r3, [r3, #0] 8006b0c: 68fa ldr r2, [r7, #12] 8006b0e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8006b10: 687b ldr r3, [r7, #4] 8006b12: 2220 movs r2, #32 8006b14: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8006b18: 687b ldr r3, [r7, #4] 8006b1a: 2200 movs r2, #0 8006b1c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8006b20: 2300 movs r3, #0 } 8006b22: 4618 mov r0, r3 8006b24: 3714 adds r7, #20 8006b26: 46bd mov sp, r7 8006b28: f85d 7b04 ldr.w r7, [sp], #4 8006b2c: 4770 bx lr 08006b2e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8006b2e: b580 push {r7, lr} 8006b30: b084 sub sp, #16 8006b32: af00 add r7, sp, #0 8006b34: 6078 str r0, [r7, #4] 8006b36: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8006b38: 687b ldr r3, [r7, #4] 8006b3a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8006b3e: 2b01 cmp r3, #1 8006b40: d101 bne.n 8006b46 8006b42: 2302 movs r3, #2 8006b44: e02d b.n 8006ba2 8006b46: 687b ldr r3, [r7, #4] 8006b48: 2201 movs r2, #1 8006b4a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8006b4e: 687b ldr r3, [r7, #4] 8006b50: 2224 movs r2, #36 @ 0x24 8006b52: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8006b56: 687b ldr r3, [r7, #4] 8006b58: 681b ldr r3, [r3, #0] 8006b5a: 681b ldr r3, [r3, #0] 8006b5c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8006b5e: 687b ldr r3, [r7, #4] 8006b60: 681b ldr r3, [r3, #0] 8006b62: 681a ldr r2, [r3, #0] 8006b64: 687b ldr r3, [r7, #4] 8006b66: 681b ldr r3, [r3, #0] 8006b68: f022 0201 bic.w r2, r2, #1 8006b6c: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8006b6e: 687b ldr r3, [r7, #4] 8006b70: 681b ldr r3, [r3, #0] 8006b72: 689b ldr r3, [r3, #8] 8006b74: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8006b78: 687b ldr r3, [r7, #4] 8006b7a: 681b ldr r3, [r3, #0] 8006b7c: 683a ldr r2, [r7, #0] 8006b7e: 430a orrs r2, r1 8006b80: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8006b82: 6878 ldr r0, [r7, #4] 8006b84: f000 f850 bl 8006c28 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8006b88: 687b ldr r3, [r7, #4] 8006b8a: 681b ldr r3, [r3, #0] 8006b8c: 68fa ldr r2, [r7, #12] 8006b8e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8006b90: 687b ldr r3, [r7, #4] 8006b92: 2220 movs r2, #32 8006b94: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8006b98: 687b ldr r3, [r7, #4] 8006b9a: 2200 movs r2, #0 8006b9c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8006ba0: 2300 movs r3, #0 } 8006ba2: 4618 mov r0, r3 8006ba4: 3710 adds r7, #16 8006ba6: 46bd mov sp, r7 8006ba8: bd80 pop {r7, pc} 08006baa : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8006baa: b580 push {r7, lr} 8006bac: b084 sub sp, #16 8006bae: af00 add r7, sp, #0 8006bb0: 6078 str r0, [r7, #4] 8006bb2: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8006bb4: 687b ldr r3, [r7, #4] 8006bb6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8006bba: 2b01 cmp r3, #1 8006bbc: d101 bne.n 8006bc2 8006bbe: 2302 movs r3, #2 8006bc0: e02d b.n 8006c1e 8006bc2: 687b ldr r3, [r7, #4] 8006bc4: 2201 movs r2, #1 8006bc6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8006bca: 687b ldr r3, [r7, #4] 8006bcc: 2224 movs r2, #36 @ 0x24 8006bce: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8006bd2: 687b ldr r3, [r7, #4] 8006bd4: 681b ldr r3, [r3, #0] 8006bd6: 681b ldr r3, [r3, #0] 8006bd8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8006bda: 687b ldr r3, [r7, #4] 8006bdc: 681b ldr r3, [r3, #0] 8006bde: 681a ldr r2, [r3, #0] 8006be0: 687b ldr r3, [r7, #4] 8006be2: 681b ldr r3, [r3, #0] 8006be4: f022 0201 bic.w r2, r2, #1 8006be8: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8006bea: 687b ldr r3, [r7, #4] 8006bec: 681b ldr r3, [r3, #0] 8006bee: 689b ldr r3, [r3, #8] 8006bf0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8006bf4: 687b ldr r3, [r7, #4] 8006bf6: 681b ldr r3, [r3, #0] 8006bf8: 683a ldr r2, [r7, #0] 8006bfa: 430a orrs r2, r1 8006bfc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8006bfe: 6878 ldr r0, [r7, #4] 8006c00: f000 f812 bl 8006c28 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8006c04: 687b ldr r3, [r7, #4] 8006c06: 681b ldr r3, [r3, #0] 8006c08: 68fa ldr r2, [r7, #12] 8006c0a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8006c0c: 687b ldr r3, [r7, #4] 8006c0e: 2220 movs r2, #32 8006c10: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8006c14: 687b ldr r3, [r7, #4] 8006c16: 2200 movs r2, #0 8006c18: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8006c1c: 2300 movs r3, #0 } 8006c1e: 4618 mov r0, r3 8006c20: 3710 adds r7, #16 8006c22: 46bd mov sp, r7 8006c24: bd80 pop {r7, pc} ... 08006c28 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8006c28: b480 push {r7} 8006c2a: b085 sub sp, #20 8006c2c: af00 add r7, sp, #0 8006c2e: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8006c30: 687b ldr r3, [r7, #4] 8006c32: 6e5b ldr r3, [r3, #100] @ 0x64 8006c34: 2b00 cmp r3, #0 8006c36: d108 bne.n 8006c4a { huart->NbTxDataToProcess = 1U; 8006c38: 687b ldr r3, [r7, #4] 8006c3a: 2201 movs r2, #1 8006c3c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8006c40: 687b ldr r3, [r7, #4] 8006c42: 2201 movs r2, #1 8006c44: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8006c48: e031 b.n 8006cae rx_fifo_depth = RX_FIFO_DEPTH; 8006c4a: 2308 movs r3, #8 8006c4c: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8006c4e: 2308 movs r3, #8 8006c50: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8006c52: 687b ldr r3, [r7, #4] 8006c54: 681b ldr r3, [r3, #0] 8006c56: 689b ldr r3, [r3, #8] 8006c58: 0e5b lsrs r3, r3, #25 8006c5a: b2db uxtb r3, r3 8006c5c: f003 0307 and.w r3, r3, #7 8006c60: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8006c62: 687b ldr r3, [r7, #4] 8006c64: 681b ldr r3, [r3, #0] 8006c66: 689b ldr r3, [r3, #8] 8006c68: 0f5b lsrs r3, r3, #29 8006c6a: b2db uxtb r3, r3 8006c6c: f003 0307 and.w r3, r3, #7 8006c70: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8006c72: 7bbb ldrb r3, [r7, #14] 8006c74: 7b3a ldrb r2, [r7, #12] 8006c76: 4911 ldr r1, [pc, #68] @ (8006cbc ) 8006c78: 5c8a ldrb r2, [r1, r2] 8006c7a: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8006c7e: 7b3a ldrb r2, [r7, #12] 8006c80: 490f ldr r1, [pc, #60] @ (8006cc0 ) 8006c82: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8006c84: fb93 f3f2 sdiv r3, r3, r2 8006c88: b29a uxth r2, r3 8006c8a: 687b ldr r3, [r7, #4] 8006c8c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8006c90: 7bfb ldrb r3, [r7, #15] 8006c92: 7b7a ldrb r2, [r7, #13] 8006c94: 4909 ldr r1, [pc, #36] @ (8006cbc ) 8006c96: 5c8a ldrb r2, [r1, r2] 8006c98: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8006c9c: 7b7a ldrb r2, [r7, #13] 8006c9e: 4908 ldr r1, [pc, #32] @ (8006cc0 ) 8006ca0: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8006ca2: fb93 f3f2 sdiv r3, r3, r2 8006ca6: b29a uxth r2, r3 8006ca8: 687b ldr r3, [r7, #4] 8006caa: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 8006cae: bf00 nop 8006cb0: 3714 adds r7, #20 8006cb2: 46bd mov sp, r7 8006cb4: f85d 7b04 ldr.w r7, [sp], #4 8006cb8: 4770 bx lr 8006cba: bf00 nop 8006cbc: 08006d64 .word 0x08006d64 8006cc0: 08006d6c .word 0x08006d6c 08006cc4 : 8006cc4: 4402 add r2, r0 8006cc6: 4603 mov r3, r0 8006cc8: 4293 cmp r3, r2 8006cca: d100 bne.n 8006cce 8006ccc: 4770 bx lr 8006cce: f803 1b01 strb.w r1, [r3], #1 8006cd2: e7f9 b.n 8006cc8 08006cd4 <__libc_init_array>: 8006cd4: b570 push {r4, r5, r6, lr} 8006cd6: 4d0d ldr r5, [pc, #52] @ (8006d0c <__libc_init_array+0x38>) 8006cd8: 4c0d ldr r4, [pc, #52] @ (8006d10 <__libc_init_array+0x3c>) 8006cda: 1b64 subs r4, r4, r5 8006cdc: 10a4 asrs r4, r4, #2 8006cde: 2600 movs r6, #0 8006ce0: 42a6 cmp r6, r4 8006ce2: d109 bne.n 8006cf8 <__libc_init_array+0x24> 8006ce4: 4d0b ldr r5, [pc, #44] @ (8006d14 <__libc_init_array+0x40>) 8006ce6: 4c0c ldr r4, [pc, #48] @ (8006d18 <__libc_init_array+0x44>) 8006ce8: f000 f818 bl 8006d1c <_init> 8006cec: 1b64 subs r4, r4, r5 8006cee: 10a4 asrs r4, r4, #2 8006cf0: 2600 movs r6, #0 8006cf2: 42a6 cmp r6, r4 8006cf4: d105 bne.n 8006d02 <__libc_init_array+0x2e> 8006cf6: bd70 pop {r4, r5, r6, pc} 8006cf8: f855 3b04 ldr.w r3, [r5], #4 8006cfc: 4798 blx r3 8006cfe: 3601 adds r6, #1 8006d00: e7ee b.n 8006ce0 <__libc_init_array+0xc> 8006d02: f855 3b04 ldr.w r3, [r5], #4 8006d06: 4798 blx r3 8006d08: 3601 adds r6, #1 8006d0a: e7f2 b.n 8006cf2 <__libc_init_array+0x1e> 8006d0c: 08006d7c .word 0x08006d7c 8006d10: 08006d7c .word 0x08006d7c 8006d14: 08006d7c .word 0x08006d7c 8006d18: 08006d80 .word 0x08006d80 08006d1c <_init>: 8006d1c: b5f8 push {r3, r4, r5, r6, r7, lr} 8006d1e: bf00 nop 8006d20: bcf8 pop {r3, r4, r5, r6, r7} 8006d22: bc08 pop {r3} 8006d24: 469e mov lr, r3 8006d26: 4770 bx lr 08006d28 <_fini>: 8006d28: b5f8 push {r3, r4, r5, r6, r7, lr} 8006d2a: bf00 nop 8006d2c: bcf8 pop {r3, r4, r5, r6, r7} 8006d2e: bc08 pop {r3} 8006d30: 469e mov lr, r3 8006d32: 4770 bx lr