diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml index f8fcf52..c0174a7 100644 --- a/.settings/language.settings.xml +++ b/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/Core/Src/main.c b/Core/Src/main.c index 76ebf1e..1d62312 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -6,12 +6,11 @@ ****************************************************************************** * @attention * - * Copyright (c) 2025 STMicroelectronics. - * All rights reserved. + * Copyright (c) 2026 Arrive. + * Author: D. Rice + * + * Version: 0.1 * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -51,7 +50,8 @@ TIM_HandleTypeDef htim2; UART_HandleTypeDef huart2; /* USER CODE BEGIN PV */ - +uint8_t fw_rev_h = 0; +uint8_t fw_rev_l = 1; uint8_t rx_hold_buffer[2]; uint8_t rx_buffer[32]; uint8_t tx_buffer[32]; @@ -589,13 +589,19 @@ void serial_number_task (void) tx_buffer[0] = IN_SYNC_BYTE_1; tx_buffer[1] = IN_SYNC_BYTE_2; - tx_buffer[2] = tx_len; for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++) { tx_buffer[tx_len_counter + 3] = serial_number[tx_len_counter]; } + tx_buffer[tx_len + 3] = 0x3A; + tx_buffer[tx_len + 4] = fw_rev_h + 0x30; + tx_buffer[tx_len + 5] = fw_rev_l + 0x30; + + tx_len = 0x16; + tx_buffer[2] = tx_len; + tx_checksum = 0x00; /* Need to apply checksum to all data bits */ @@ -606,10 +612,10 @@ void serial_number_task (void) tx_checksum = ~tx_checksum; - tx_buffer[22] = (uint8_t)((tx_checksum >> 8) & 0xFF); - tx_buffer[23] = (uint8_t)(tx_checksum & 0xFF); + tx_buffer[tx_len + 3] = (uint8_t)((tx_checksum >> 8) & 0xFF); + tx_buffer[tx_len + 4] = (uint8_t)(tx_checksum & 0xFF); - tx_len = 0x18; + tx_len = 0x1B; HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100); } diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo index d2c5d3c..ac17b78 100644 --- a/Debug/Core/Src/main.cyclo +++ b/Debug/Core/Src/main.cyclo @@ -9,8 +9,8 @@ ../Core/Src/main.c:535:10:get_divider_input_mv 1 ../Core/Src/main.c:548:6:voltage_conversion_task 2 ../Core/Src/main.c:586:6:serial_number_task 3 -../Core/Src/main.c:618:6:adc_task 1 -../Core/Src/main.c:632:6:power_switch 2 -../Core/Src/main.c:648:6:HAL_UART_TxCpltCallback 1 -../Core/Src/main.c:654:6:HAL_UART_RxCpltCallback 18 -../Core/Src/main.c:805:6:Error_Handler 1 +../Core/Src/main.c:624:6:adc_task 1 +../Core/Src/main.c:638:6:power_switch 2 +../Core/Src/main.c:654:6:HAL_UART_TxCpltCallback 1 +../Core/Src/main.c:660:6:HAL_UART_RxCpltCallback 18 +../Core/Src/main.c:811:6:Error_Handler 1 diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o index 80fc303..061dcd4 100644 Binary files a/Debug/Core/Src/main.o and b/Debug/Core/Src/main.o differ diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su index 10c8966..4f17450 100644 --- a/Debug/Core/Src/main.su +++ b/Debug/Core/Src/main.su @@ -9,8 +9,8 @@ ../Core/Src/main.c:535:10:get_divider_input_mv 48 static ../Core/Src/main.c:548:6:voltage_conversion_task 8 static ../Core/Src/main.c:586:6:serial_number_task 8 static -../Core/Src/main.c:618:6:adc_task 8 static -../Core/Src/main.c:632:6:power_switch 16 static -../Core/Src/main.c:648:6:HAL_UART_TxCpltCallback 16 static -../Core/Src/main.c:654:6:HAL_UART_RxCpltCallback 16 static -../Core/Src/main.c:805:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:624:6:adc_task 8 static +../Core/Src/main.c:638:6:power_switch 16 static +../Core/Src/main.c:654:6:HAL_UART_TxCpltCallback 16 static +../Core/Src/main.c:660:6:HAL_UART_RxCpltCallback 16 static +../Core/Src/main.c:811:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Debug/POWER_SWITCH.elf b/Debug/POWER_SWITCH.elf index dab5e82..451465c 100644 Binary files a/Debug/POWER_SWITCH.elf and b/Debug/POWER_SWITCH.elf differ diff --git a/Debug/POWER_SWITCH.list b/Debug/POWER_SWITCH.list index 1157650..d3adfdf 100644 --- a/Debug/POWER_SWITCH.list +++ b/Debug/POWER_SWITCH.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001d8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00007554 080001d8 080001d8 000011d8 2**3 + 1 .text 0000759c 080001d8 080001d8 000011d8 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000040 0800772c 0800772c 0000872c 2**2 + 2 .rodata 00000040 08007774 08007774 00008774 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 0800776c 0800776c 00009020 2**0 + 3 .ARM.extab 00000000 080077b4 080077b4 00009024 2**0 CONTENTS, READONLY - 4 .ARM 00000008 0800776c 0800776c 0000876c 2**2 + 4 .ARM 00000008 080077b4 080077b4 000087b4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08007774 08007774 00009020 2**0 + 5 .preinit_array 00000000 080077bc 080077bc 00009024 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08007774 08007774 00008774 2**2 + 6 .init_array 00000004 080077bc 080077bc 000087bc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 7 .fini_array 00000004 08007778 08007778 00008778 2**2 + 7 .fini_array 00000004 080077c0 080077c0 000087c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 8 .data 00000020 20000000 0800777c 00009000 2**2 + 8 .data 00000024 20000000 080077c4 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00000248 20000020 0800779c 00009020 2**2 + 9 .bss 0000024c 20000024 080077e8 00009024 2**2 ALLOC - 10 ._user_heap_stack 00000600 20000268 0800779c 00009268 2**0 + 10 ._user_heap_stack 00000600 20000270 080077e8 00009270 2**0 ALLOC - 11 .ARM.attributes 00000030 00000000 00000000 00009020 2**0 + 11 .ARM.attributes 00000030 00000000 00000000 00009024 2**0 CONTENTS, READONLY - 12 .debug_info 000170b0 00000000 00000000 00009050 2**0 + 12 .debug_info 000170d2 00000000 00000000 00009054 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 00002a3f 00000000 00000000 00020100 2**0 + 13 .debug_abbrev 00002a3f 00000000 00000000 00020126 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 000014a0 00000000 00000000 00022b40 2**3 + 14 .debug_aranges 000014a0 00000000 00000000 00022b68 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_rnglists 00001021 00000000 00000000 00023fe0 2**0 + 15 .debug_rnglists 00001021 00000000 00000000 00024008 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 00020407 00000000 00000000 00025001 2**0 + 16 .debug_macro 00020407 00000000 00000000 00025029 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 000168d9 00000000 00000000 00045408 2**0 + 17 .debug_line 00016908 00000000 00000000 00045430 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000db63e 00000000 00000000 0005bce1 2**0 + 18 .debug_str 000db650 00000000 00000000 0005bd38 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000043 00000000 00000000 0013731f 2**0 + 19 .comment 00000043 00000000 00000000 00137388 2**0 CONTENTS, READONLY - 20 .debug_frame 00005a98 00000000 00000000 00137364 2**2 + 20 .debug_frame 00005a98 00000000 00000000 001373cc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 0000006d 00000000 00000000 0013cdfc 2**0 + 21 .debug_line_str 0000006d 00000000 00000000 0013ce64 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -62,9 +62,9 @@ Disassembly of section .text: 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} - 80001f0: 20000020 .word 0x20000020 + 80001f0: 20000024 .word 0x20000024 80001f4: 00000000 .word 0x00000000 - 80001f8: 08007714 .word 0x08007714 + 80001f8: 0800775c .word 0x0800775c 080001fc : 80001fc: b508 push {r3, lr} @@ -75,8 +75,8 @@ Disassembly of section .text: 8000206: f3af 8000 nop.w 800020a: bd08 pop {r3, pc} 800020c: 00000000 .word 0x00000000 - 8000210: 20000024 .word 0x20000024 - 8000214: 08007714 .word 0x08007714 + 8000210: 20000028 .word 0x20000028 + 8000214: 0800775c .word 0x0800775c 08000218 <__aeabi_dmul>: 8000218: b570 push {r4, r5, r6, lr} @@ -891,7 +891,7 @@ int main(void) /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 8000b54: f000 ff65 bl 8001a22 + 8000b54: f000 ff89 bl 8001a6a /* USER CODE BEGIN Init */ /* USER CODE END Init */ @@ -921,22 +921,22 @@ int main(void) 8000b70: 2200 movs r2, #0 8000b72: f44f 7180 mov.w r1, #256 @ 0x100 8000b76: 4830 ldr r0, [pc, #192] @ (8000c38 ) - 8000b78: f002 ffd4 bl 8003b24 + 8000b78: f002 fff8 bl 8003b6c HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); 8000b7c: 2200 movs r2, #0 8000b7e: f44f 5180 mov.w r1, #4096 @ 0x1000 8000b82: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8000b86: f002 ffcd bl 8003b24 + 8000b86: f002 fff1 bl 8003b6c /* Run ADC calibration */ HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED); 8000b8a: 217f movs r1, #127 @ 0x7f 8000b8c: 482b ldr r0, [pc, #172] @ (8000c3c ) - 8000b8e: f002 fb71 bl 8003274 + 8000b8e: f002 fb95 bl 80032bc HAL_ADCEx_Calibration_Start(&hadc2, ADC_SINGLE_ENDED); 8000b92: 217f movs r1, #127 @ 0x7f 8000b94: 482a ldr r0, [pc, #168] @ (8000c40 ) - 8000b96: f002 fb6d bl 8003274 + 8000b96: f002 fb91 bl 80032bc /* Setup UART interrupts */ /* Make sure UART Rx counters and flags are reset */ @@ -961,7 +961,7 @@ int main(void) 8000bb2: 2201 movs r2, #1 8000bb4: 4927 ldr r1, [pc, #156] @ (8000c54 ) 8000bb6: 4828 ldr r0, [pc, #160] @ (8000c58 ) - 8000bb8: f004 fd4e bl 8005658 + 8000bb8: f004 fd72 bl 80056a0 /* Get real VDDA value */ vdd_ref = get_actual_vdda(&hadc1); @@ -1011,7 +1011,7 @@ int main(void) 8000c02: 2364 movs r3, #100 @ 0x64 8000c04: 4916 ldr r1, [pc, #88] @ (8000c60 ) 8000c06: 4814 ldr r0, [pc, #80] @ (8000c58 ) - 8000c08: f004 fc98 bl 800553c + 8000c08: f004 fcbc bl 8005584 /* Infinite loop */ /* USER CODE BEGIN WHILE */ @@ -1028,7 +1028,7 @@ int main(void) 8000c16: 2200 movs r2, #0 8000c18: 701a strb r2, [r3, #0] adc_task(); - 8000c1a: f000 fbd9 bl 80013d0 + 8000c1a: f000 fbfd bl 8001418 voltage_conversion_task(); 8000c1e: f000 fabf bl 80011a0 } @@ -1049,18 +1049,18 @@ int main(void) 8000c34: e7ea b.n 8000c0c 8000c36: bf00 nop 8000c38: 48000400 .word 0x48000400 - 8000c3c: 2000003c .word 0x2000003c - 8000c40: 200000a8 .word 0x200000a8 - 8000c44: 2000023a .word 0x2000023a - 8000c48: 2000023b .word 0x2000023b - 8000c4c: 2000023c .word 0x2000023c - 8000c50: 20000248 .word 0x20000248 - 8000c54: 200001f4 .word 0x200001f4 - 8000c58: 20000160 .word 0x20000160 - 8000c5c: 20000250 .word 0x20000250 - 8000c60: 20000218 .word 0x20000218 - 8000c64: 20000238 .word 0x20000238 - 8000c68: 2000025c .word 0x2000025c + 8000c3c: 20000040 .word 0x20000040 + 8000c40: 200000ac .word 0x200000ac + 8000c44: 20000242 .word 0x20000242 + 8000c48: 20000243 .word 0x20000243 + 8000c4c: 20000244 .word 0x20000244 + 8000c50: 20000250 .word 0x20000250 + 8000c54: 200001fc .word 0x200001fc + 8000c58: 20000164 .word 0x20000164 + 8000c5c: 20000258 .word 0x20000258 + 8000c60: 20000220 .word 0x20000220 + 8000c64: 20000240 .word 0x20000240 + 8000c68: 20000264 .word 0x20000264 08000c6c : /** @@ -1077,7 +1077,7 @@ void SystemClock_Config(void) 8000c76: 2238 movs r2, #56 @ 0x38 8000c78: 2100 movs r1, #0 8000c7a: 4618 mov r0, r3 - 8000c7c: f006 fd1e bl 80076bc + 8000c7c: f006 fd42 bl 8007704 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000c80: 1d3b adds r3, r7, #4 8000c82: 2200 movs r2, #0 @@ -1091,7 +1091,7 @@ void SystemClock_Config(void) */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8000c8e: f44f 7000 mov.w r0, #512 @ 0x200 - 8000c92: f002 ff5f bl 8003b54 + 8000c92: f002 ff83 bl 8003b9c /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. @@ -1129,13 +1129,13 @@ void SystemClock_Config(void) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000cc0: f107 0318 add.w r3, r7, #24 8000cc4: 4618 mov r0, r3 - 8000cc6: f002 fff9 bl 8003cbc + 8000cc6: f003 f81d bl 8003d04 8000cca: 4603 mov r3, r0 8000ccc: 2b00 cmp r3, #0 8000cce: d001 beq.n 8000cd4 { Error_Handler(); - 8000cd0: f000 fcee bl 80016b0 + 8000cd0: f000 fd12 bl 80016f8 } /** Initializes the CPU, AHB and APB buses clocks @@ -1161,13 +1161,13 @@ void SystemClock_Config(void) 8000ce8: 1d3b adds r3, r7, #4 8000cea: 2104 movs r1, #4 8000cec: 4618 mov r0, r3 - 8000cee: f003 faf7 bl 80042e0 + 8000cee: f003 fb1b bl 8004328 8000cf2: 4603 mov r3, r0 8000cf4: 2b00 cmp r3, #0 8000cf6: d001 beq.n 8000cfc { Error_Handler(); - 8000cf8: f000 fcda bl 80016b0 + 8000cf8: f000 fcfe bl 80016f8 } } 8000cfc: bf00 nop @@ -1201,7 +1201,7 @@ static void MX_ADC1_Init(void) 8000d18: 2220 movs r2, #32 8000d1a: 2100 movs r1, #0 8000d1c: 4618 mov r0, r3 - 8000d1e: f006 fccd bl 80076bc + 8000d1e: f006 fcf1 bl 8007704 /* USER CODE END ADC1_Init 1 */ @@ -1273,13 +1273,13 @@ static void MX_ADC1_Init(void) 8000d88: f883 2040 strb.w r2, [r3, #64] @ 0x40 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000d8c: 4817 ldr r0, [pc, #92] @ (8000dec ) - 8000d8e: f001 f933 bl 8001ff8 + 8000d8e: f001 f957 bl 8002040 8000d92: 4603 mov r3, r0 8000d94: 2b00 cmp r3, #0 8000d96: d001 beq.n 8000d9c { Error_Handler(); - 8000d98: f000 fc8a bl 80016b0 + 8000d98: f000 fcae bl 80016f8 } /** Configure the ADC multi-mode @@ -1291,13 +1291,13 @@ static void MX_ADC1_Init(void) 8000da0: f107 0324 add.w r3, r7, #36 @ 0x24 8000da4: 4619 mov r1, r3 8000da6: 4811 ldr r0, [pc, #68] @ (8000dec ) - 8000da8: f002 fac6 bl 8003338 + 8000da8: f002 faea bl 8003380 8000dac: 4603 mov r3, r0 8000dae: 2b00 cmp r3, #0 8000db0: d001 beq.n 8000db6 { Error_Handler(); - 8000db2: f000 fc7d bl 80016b0 + 8000db2: f000 fca1 bl 80016f8 } /** Configure Regular Channel @@ -1324,13 +1324,13 @@ static void MX_ADC1_Init(void) 8000dce: 1d3b adds r3, r7, #4 8000dd0: 4619 mov r1, r3 8000dd2: 4806 ldr r0, [pc, #24] @ (8000dec ) - 8000dd4: f001 fc6a bl 80026ac + 8000dd4: f001 fc8e bl 80026f4 8000dd8: 4603 mov r3, r0 8000dda: 2b00 cmp r3, #0 8000ddc: d001 beq.n 8000de2 { Error_Handler(); - 8000dde: f000 fc67 bl 80016b0 + 8000dde: f000 fc8b bl 80016f8 } /* USER CODE BEGIN ADC1_Init 2 */ @@ -1342,7 +1342,7 @@ static void MX_ADC1_Init(void) 8000de6: 46bd mov sp, r7 8000de8: bd80 pop {r7, pc} 8000dea: bf00 nop - 8000dec: 2000003c .word 0x2000003c + 8000dec: 20000040 .word 0x20000040 8000df0: cb840000 .word 0xcb840000 08000df4 : @@ -1365,7 +1365,7 @@ static void MX_ADC2_Init(void) 8000dfc: 2220 movs r2, #32 8000dfe: 2100 movs r1, #0 8000e00: 4618 mov r0, r3 - 8000e02: f006 fc5b bl 80076bc + 8000e02: f006 fc7f bl 8007704 /* USER CODE END ADC2_Init 1 */ @@ -1437,13 +1437,13 @@ static void MX_ADC2_Init(void) 8000e6a: f883 2040 strb.w r2, [r3, #64] @ 0x40 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000e6e: 4818 ldr r0, [pc, #96] @ (8000ed0 ) - 8000e70: f001 f8c2 bl 8001ff8 + 8000e70: f001 f8e6 bl 8002040 8000e74: 4603 mov r3, r0 8000e76: 2b00 cmp r3, #0 8000e78: d001 beq.n 8000e7e { Error_Handler(); - 8000e7a: f000 fc19 bl 80016b0 + 8000e7a: f000 fc3d bl 80016f8 } /** Configure Regular Channel @@ -1470,13 +1470,13 @@ static void MX_ADC2_Init(void) 8000e96: 463b mov r3, r7 8000e98: 4619 mov r1, r3 8000e9a: 480d ldr r0, [pc, #52] @ (8000ed0 ) - 8000e9c: f001 fc06 bl 80026ac + 8000e9c: f001 fc2a bl 80026f4 8000ea0: 4603 mov r3, r0 8000ea2: 2b00 cmp r3, #0 8000ea4: d001 beq.n 8000eaa { Error_Handler(); - 8000ea6: f000 fc03 bl 80016b0 + 8000ea6: f000 fc27 bl 80016f8 } /** Configure Regular Channel @@ -1491,13 +1491,13 @@ static void MX_ADC2_Init(void) 8000eb2: 463b mov r3, r7 8000eb4: 4619 mov r1, r3 8000eb6: 4806 ldr r0, [pc, #24] @ (8000ed0 ) - 8000eb8: f001 fbf8 bl 80026ac + 8000eb8: f001 fc1c bl 80026f4 8000ebc: 4603 mov r3, r0 8000ebe: 2b00 cmp r3, #0 8000ec0: d001 beq.n 8000ec6 { Error_Handler(); - 8000ec2: f000 fbf5 bl 80016b0 + 8000ec2: f000 fc19 bl 80016f8 } /* USER CODE BEGIN ADC2_Init 2 */ @@ -1509,7 +1509,7 @@ static void MX_ADC2_Init(void) 8000eca: 46bd mov sp, r7 8000ecc: bd80 pop {r7, pc} 8000ece: bf00 nop - 8000ed0: 200000a8 .word 0x200000a8 + 8000ed0: 200000ac .word 0x200000ac 8000ed4: 50000100 .word 0x50000100 8000ed8: 0c900008 .word 0x0c900008 8000edc: 10c00010 .word 0x10c00010 @@ -1572,13 +1572,13 @@ static void MX_TIM2_Init(void) 8000f22: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8000f24: 4813 ldr r0, [pc, #76] @ (8000f74 ) - 8000f26: f003 fde7 bl 8004af8 + 8000f26: f003 fe0b bl 8004b40 8000f2a: 4603 mov r3, r0 8000f2c: 2b00 cmp r3, #0 8000f2e: d001 beq.n 8000f34 { Error_Handler(); - 8000f30: f000 fbbe bl 80016b0 + 8000f30: f000 fbe2 bl 80016f8 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000f34: f44f 5380 mov.w r3, #4096 @ 0x1000 @@ -1587,13 +1587,13 @@ static void MX_TIM2_Init(void) 8000f3a: f107 0310 add.w r3, r7, #16 8000f3e: 4619 mov r1, r3 8000f40: 480c ldr r0, [pc, #48] @ (8000f74 ) - 8000f42: f003 ff7f bl 8004e44 + 8000f42: f003 ffa3 bl 8004e8c 8000f46: 4603 mov r3, r0 8000f48: 2b00 cmp r3, #0 8000f4a: d001 beq.n 8000f50 { Error_Handler(); - 8000f4c: f000 fbb0 bl 80016b0 + 8000f4c: f000 fbd4 bl 80016f8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000f50: 2300 movs r3, #0 @@ -1605,13 +1605,13 @@ static void MX_TIM2_Init(void) 8000f58: 1d3b adds r3, r7, #4 8000f5a: 4619 mov r1, r3 8000f5c: 4805 ldr r0, [pc, #20] @ (8000f74 ) - 8000f5e: f004 f9d5 bl 800530c + 8000f5e: f004 f9f9 bl 8005354 8000f62: 4603 mov r3, r0 8000f64: 2b00 cmp r3, #0 8000f66: d001 beq.n 8000f6c { Error_Handler(); - 8000f68: f000 fba2 bl 80016b0 + 8000f68: f000 fbc6 bl 80016f8 } /* USER CODE BEGIN TIM2_Init 2 */ @@ -1622,7 +1622,7 @@ static void MX_TIM2_Init(void) 8000f6e: 3720 adds r7, #32 8000f70: 46bd mov sp, r7 8000f72: bd80 pop {r7, pc} - 8000f74: 20000114 .word 0x20000114 + 8000f74: 20000118 .word 0x20000118 8000f78: 0001f7e7 .word 0x0001f7e7 08000f7c : @@ -1685,45 +1685,45 @@ static void MX_USART2_UART_Init(void) 8000fc2: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8000fc4: 4811 ldr r0, [pc, #68] @ (800100c ) - 8000fc6: f004 fa69 bl 800549c + 8000fc6: f004 fa8d bl 80054e4 8000fca: 4603 mov r3, r0 8000fcc: 2b00 cmp r3, #0 8000fce: d001 beq.n 8000fd4 { Error_Handler(); - 8000fd0: f000 fb6e bl 80016b0 + 8000fd0: f000 fb92 bl 80016f8 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000fd4: 2100 movs r1, #0 8000fd6: 480d ldr r0, [pc, #52] @ (800100c ) - 8000fd8: f006 faa5 bl 8007526 + 8000fd8: f006 fac9 bl 800756e 8000fdc: 4603 mov r3, r0 8000fde: 2b00 cmp r3, #0 8000fe0: d001 beq.n 8000fe6 { Error_Handler(); - 8000fe2: f000 fb65 bl 80016b0 + 8000fe2: f000 fb89 bl 80016f8 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000fe6: 2100 movs r1, #0 8000fe8: 4808 ldr r0, [pc, #32] @ (800100c ) - 8000fea: f006 fada bl 80075a2 + 8000fea: f006 fafe bl 80075ea 8000fee: 4603 mov r3, r0 8000ff0: 2b00 cmp r3, #0 8000ff2: d001 beq.n 8000ff8 { Error_Handler(); - 8000ff4: f000 fb5c bl 80016b0 + 8000ff4: f000 fb80 bl 80016f8 } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 8000ff8: 4804 ldr r0, [pc, #16] @ (800100c ) - 8000ffa: f006 fa5b bl 80074b4 + 8000ffa: f006 fa7f bl 80074fc 8000ffe: 4603 mov r3, r0 8001000: 2b00 cmp r3, #0 8001002: d001 beq.n 8001008 { Error_Handler(); - 8001004: f000 fb54 bl 80016b0 + 8001004: f000 fb78 bl 80016f8 } /* USER CODE BEGIN USART2_Init 2 */ @@ -1732,7 +1732,7 @@ static void MX_USART2_UART_Init(void) } 8001008: bf00 nop 800100a: bd80 pop {r7, pc} - 800100c: 20000160 .word 0x20000160 + 800100c: 20000164 .word 0x20000164 8001010: 40004400 .word 0x40004400 08001014 : @@ -1786,14 +1786,14 @@ static void MX_GPIO_Init(void) 800105a: 2200 movs r2, #0 800105c: f44f 5180 mov.w r1, #4096 @ 0x1000 8001060: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001064: f002 fd5e bl 8003b24 + 8001064: f002 fd82 bl 8003b6c /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 8001068: 2200 movs r2, #0 800106a: f44f 7180 mov.w r1, #256 @ 0x100 800106e: 4814 ldr r0, [pc, #80] @ (80010c0 ) - 8001070: f002 fd58 bl 8003b24 + 8001070: f002 fd7c bl 8003b6c /*Configure GPIO pin : POWER_SWITCH_Pin */ GPIO_InitStruct.Pin = POWER_SWITCH_Pin; @@ -1812,7 +1812,7 @@ static void MX_GPIO_Init(void) 8001086: f107 030c add.w r3, r7, #12 800108a: 4619 mov r1, r3 800108c: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001090: f002 fbc6 bl 8003820 + 8001090: f002 fbea bl 8003868 /*Configure GPIO pin : LD2_Pin */ GPIO_InitStruct.Pin = LD2_Pin; @@ -1831,7 +1831,7 @@ static void MX_GPIO_Init(void) 80010a6: f107 030c add.w r3, r7, #12 80010aa: 4619 mov r1, r3 80010ac: 4804 ldr r0, [pc, #16] @ (80010c0 ) - 80010ae: f002 fbb7 bl 8003820 + 80010ae: f002 fbdb bl 8003868 /* USER CODE BEGIN MX_GPIO_Init_2 */ @@ -1861,24 +1861,24 @@ uint32_t get_actual_vdda(ADC_HandleTypeDef *hadc) /* Perform ADC reading of the VREFINT channel */ HAL_ADC_Start(hadc); 80010d0: 6878 ldr r0, [r7, #4] - 80010d2: f001 f915 bl 8002300 + 80010d2: f001 f939 bl 8002348 if (HAL_ADC_PollForConversion(hadc, 10) == HAL_OK) { 80010d6: 210a movs r1, #10 80010d8: 6878 ldr r0, [r7, #4] - 80010da: f001 fa01 bl 80024e0 + 80010da: f001 fa25 bl 8002528 80010de: 4603 mov r3, r0 80010e0: 2b00 cmp r3, #0 80010e2: d103 bne.n 80010ec vrefint_raw = HAL_ADC_GetValue(hadc); 80010e4: 6878 ldr r0, [r7, #4] - 80010e6: f001 fad3 bl 8002690 + 80010e6: f001 faf7 bl 80026d8 80010ea: 60f8 str r0, [r7, #12] } HAL_ADC_Stop(hadc); 80010ec: 6878 ldr r0, [r7, #4] - 80010ee: f001 f9c3 bl 8002478 + 80010ee: f001 f9e7 bl 80024c0 if (vrefint_raw == 0) return 0; /* Avoid division by zero */ 80010f2: 68fb ldr r3, [r7, #12] @@ -2148,20 +2148,20 @@ void voltage_conversion_task(void) 80012b2: 2364 movs r3, #100 @ 0x64 80012b4: 4908 ldr r1, [pc, #32] @ (80012d8 ) 80012b6: 480b ldr r0, [pc, #44] @ (80012e4 ) - 80012b8: f004 f940 bl 800553c + 80012b8: f004 f964 bl 8005584 } 80012bc: bf00 nop 80012be: bd80 pop {r7, pc} - 80012c0: 2000024a .word 0x2000024a - 80012c4: 20000250 .word 0x20000250 - 80012c8: 20000254 .word 0x20000254 - 80012cc: 2000024c .word 0x2000024c - 80012d0: 20000258 .word 0x20000258 - 80012d4: 20000238 .word 0x20000238 - 80012d8: 20000218 .word 0x20000218 - 80012dc: 20000239 .word 0x20000239 - 80012e0: 20000240 .word 0x20000240 - 80012e4: 20000160 .word 0x20000160 + 80012c0: 20000252 .word 0x20000252 + 80012c4: 20000258 .word 0x20000258 + 80012c8: 2000025c .word 0x2000025c + 80012cc: 20000254 .word 0x20000254 + 80012d0: 20000260 .word 0x20000260 + 80012d4: 20000240 .word 0x20000240 + 80012d8: 20000220 .word 0x20000220 + 80012dc: 20000241 .word 0x20000241 + 80012e0: 20000248 .word 0x20000248 + 80012e4: 20000164 .word 0x20000164 080012e8 : @@ -2170,17173 +2170,17213 @@ void serial_number_task (void) 80012e8: b580 push {r7, lr} 80012ea: af00 add r7, sp, #0 tx_len = 0x13; - 80012ec: 4b32 ldr r3, [pc, #200] @ (80013b8 ) + 80012ec: 4b42 ldr r3, [pc, #264] @ (80013f8 ) 80012ee: 2213 movs r2, #19 80012f0: 701a strb r2, [r3, #0] tx_buffer[0] = IN_SYNC_BYTE_1; - 80012f2: 4b32 ldr r3, [pc, #200] @ (80013bc ) + 80012f2: 4b42 ldr r3, [pc, #264] @ (80013fc ) 80012f4: 2241 movs r2, #65 @ 0x41 80012f6: 701a strb r2, [r3, #0] tx_buffer[1] = IN_SYNC_BYTE_2; - 80012f8: 4b30 ldr r3, [pc, #192] @ (80013bc ) + 80012f8: 4b40 ldr r3, [pc, #256] @ (80013fc ) 80012fa: 2252 movs r2, #82 @ 0x52 80012fc: 705a strb r2, [r3, #1] - tx_buffer[2] = tx_len; - 80012fe: 4b2e ldr r3, [pc, #184] @ (80013b8 ) - 8001300: 781a ldrb r2, [r3, #0] - 8001302: 4b2e ldr r3, [pc, #184] @ (80013bc ) - 8001304: 709a strb r2, [r3, #2] for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++) - 8001306: 4b2e ldr r3, [pc, #184] @ (80013c0 ) - 8001308: 2200 movs r2, #0 - 800130a: 701a strb r2, [r3, #0] - 800130c: e00f b.n 800132e + 80012fe: 4b40 ldr r3, [pc, #256] @ (8001400 ) + 8001300: 2200 movs r2, #0 + 8001302: 701a strb r2, [r3, #0] + 8001304: e00f b.n 8001326 { tx_buffer[tx_len_counter + 3] = serial_number[tx_len_counter]; - 800130e: 4b2c ldr r3, [pc, #176] @ (80013c0 ) - 8001310: 781b ldrb r3, [r3, #0] - 8001312: 4619 mov r1, r3 - 8001314: 4b2a ldr r3, [pc, #168] @ (80013c0 ) - 8001316: 781b ldrb r3, [r3, #0] - 8001318: 3303 adds r3, #3 - 800131a: 4a2a ldr r2, [pc, #168] @ (80013c4 ) - 800131c: 5c51 ldrb r1, [r2, r1] - 800131e: 4a27 ldr r2, [pc, #156] @ (80013bc ) - 8001320: 54d1 strb r1, [r2, r3] + 8001306: 4b3e ldr r3, [pc, #248] @ (8001400 ) + 8001308: 781b ldrb r3, [r3, #0] + 800130a: 4619 mov r1, r3 + 800130c: 4b3c ldr r3, [pc, #240] @ (8001400 ) + 800130e: 781b ldrb r3, [r3, #0] + 8001310: 3303 adds r3, #3 + 8001312: 4a3c ldr r2, [pc, #240] @ (8001404 ) + 8001314: 5c51 ldrb r1, [r2, r1] + 8001316: 4a39 ldr r2, [pc, #228] @ (80013fc ) + 8001318: 54d1 strb r1, [r2, r3] for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++) - 8001322: 4b27 ldr r3, [pc, #156] @ (80013c0 ) - 8001324: 781b ldrb r3, [r3, #0] - 8001326: 3301 adds r3, #1 - 8001328: b2da uxtb r2, r3 - 800132a: 4b25 ldr r3, [pc, #148] @ (80013c0 ) - 800132c: 701a strb r2, [r3, #0] - 800132e: 4b24 ldr r3, [pc, #144] @ (80013c0 ) - 8001330: 781a ldrb r2, [r3, #0] - 8001332: 4b21 ldr r3, [pc, #132] @ (80013b8 ) - 8001334: 781b ldrb r3, [r3, #0] - 8001336: 429a cmp r2, r3 - 8001338: d3e9 bcc.n 800130e + 800131a: 4b39 ldr r3, [pc, #228] @ (8001400 ) + 800131c: 781b ldrb r3, [r3, #0] + 800131e: 3301 adds r3, #1 + 8001320: b2da uxtb r2, r3 + 8001322: 4b37 ldr r3, [pc, #220] @ (8001400 ) + 8001324: 701a strb r2, [r3, #0] + 8001326: 4b36 ldr r3, [pc, #216] @ (8001400 ) + 8001328: 781a ldrb r2, [r3, #0] + 800132a: 4b33 ldr r3, [pc, #204] @ (80013f8 ) + 800132c: 781b ldrb r3, [r3, #0] + 800132e: 429a cmp r2, r3 + 8001330: d3e9 bcc.n 8001306 } + tx_buffer[tx_len + 3] = 0x3A; + 8001332: 4b31 ldr r3, [pc, #196] @ (80013f8 ) + 8001334: 781b ldrb r3, [r3, #0] + 8001336: 3303 adds r3, #3 + 8001338: 4a30 ldr r2, [pc, #192] @ (80013fc ) + 800133a: 213a movs r1, #58 @ 0x3a + 800133c: 54d1 strb r1, [r2, r3] + tx_buffer[tx_len + 4] = fw_rev_h + 0x30; + 800133e: 4b32 ldr r3, [pc, #200] @ (8001408 ) + 8001340: 781a ldrb r2, [r3, #0] + 8001342: 4b2d ldr r3, [pc, #180] @ (80013f8 ) + 8001344: 781b ldrb r3, [r3, #0] + 8001346: 3304 adds r3, #4 + 8001348: 3230 adds r2, #48 @ 0x30 + 800134a: b2d1 uxtb r1, r2 + 800134c: 4a2b ldr r2, [pc, #172] @ (80013fc ) + 800134e: 54d1 strb r1, [r2, r3] + tx_buffer[tx_len + 5] = fw_rev_l + 0x30; + 8001350: 4b2e ldr r3, [pc, #184] @ (800140c ) + 8001352: 781a ldrb r2, [r3, #0] + 8001354: 4b28 ldr r3, [pc, #160] @ (80013f8 ) + 8001356: 781b ldrb r3, [r3, #0] + 8001358: 3305 adds r3, #5 + 800135a: 3230 adds r2, #48 @ 0x30 + 800135c: b2d1 uxtb r1, r2 + 800135e: 4a27 ldr r2, [pc, #156] @ (80013fc ) + 8001360: 54d1 strb r1, [r2, r3] + + tx_len = 0x16; + 8001362: 4b25 ldr r3, [pc, #148] @ (80013f8 ) + 8001364: 2216 movs r2, #22 + 8001366: 701a strb r2, [r3, #0] + tx_buffer[2] = tx_len; + 8001368: 4b23 ldr r3, [pc, #140] @ (80013f8 ) + 800136a: 781a ldrb r2, [r3, #0] + 800136c: 4b23 ldr r3, [pc, #140] @ (80013fc ) + 800136e: 709a strb r2, [r3, #2] + tx_checksum = 0x00; - 800133a: 4b23 ldr r3, [pc, #140] @ (80013c8 ) - 800133c: 2200 movs r2, #0 - 800133e: 801a strh r2, [r3, #0] + 8001370: 4b27 ldr r3, [pc, #156] @ (8001410 ) + 8001372: 2200 movs r2, #0 + 8001374: 801a strh r2, [r3, #0] /* Need to apply checksum to all data bits */ for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++) - 8001340: 4b1f ldr r3, [pc, #124] @ (80013c0 ) - 8001342: 2200 movs r2, #0 - 8001344: 701a strb r2, [r3, #0] - 8001346: e011 b.n 800136c + 8001376: 4b22 ldr r3, [pc, #136] @ (8001400 ) + 8001378: 2200 movs r2, #0 + 800137a: 701a strb r2, [r3, #0] + 800137c: e011 b.n 80013a2 { tx_checksum += tx_buffer[tx_len_counter + 3]; - 8001348: 4b1d ldr r3, [pc, #116] @ (80013c0 ) - 800134a: 781b ldrb r3, [r3, #0] - 800134c: 3303 adds r3, #3 - 800134e: 4a1b ldr r2, [pc, #108] @ (80013bc ) - 8001350: 5cd3 ldrb r3, [r2, r3] - 8001352: 461a mov r2, r3 - 8001354: 4b1c ldr r3, [pc, #112] @ (80013c8 ) - 8001356: 881b ldrh r3, [r3, #0] - 8001358: 4413 add r3, r2 - 800135a: b29a uxth r2, r3 - 800135c: 4b1a ldr r3, [pc, #104] @ (80013c8 ) - 800135e: 801a strh r2, [r3, #0] + 800137e: 4b20 ldr r3, [pc, #128] @ (8001400 ) + 8001380: 781b ldrb r3, [r3, #0] + 8001382: 3303 adds r3, #3 + 8001384: 4a1d ldr r2, [pc, #116] @ (80013fc ) + 8001386: 5cd3 ldrb r3, [r2, r3] + 8001388: 461a mov r2, r3 + 800138a: 4b21 ldr r3, [pc, #132] @ (8001410 ) + 800138c: 881b ldrh r3, [r3, #0] + 800138e: 4413 add r3, r2 + 8001390: b29a uxth r2, r3 + 8001392: 4b1f ldr r3, [pc, #124] @ (8001410 ) + 8001394: 801a strh r2, [r3, #0] for (tx_len_counter = 0x00; tx_len_counter < tx_len; tx_len_counter++) - 8001360: 4b17 ldr r3, [pc, #92] @ (80013c0 ) - 8001362: 781b ldrb r3, [r3, #0] - 8001364: 3301 adds r3, #1 - 8001366: b2da uxtb r2, r3 - 8001368: 4b15 ldr r3, [pc, #84] @ (80013c0 ) - 800136a: 701a strb r2, [r3, #0] - 800136c: 4b14 ldr r3, [pc, #80] @ (80013c0 ) - 800136e: 781a ldrb r2, [r3, #0] - 8001370: 4b11 ldr r3, [pc, #68] @ (80013b8 ) - 8001372: 781b ldrb r3, [r3, #0] - 8001374: 429a cmp r2, r3 - 8001376: d3e7 bcc.n 8001348 + 8001396: 4b1a ldr r3, [pc, #104] @ (8001400 ) + 8001398: 781b ldrb r3, [r3, #0] + 800139a: 3301 adds r3, #1 + 800139c: b2da uxtb r2, r3 + 800139e: 4b18 ldr r3, [pc, #96] @ (8001400 ) + 80013a0: 701a strb r2, [r3, #0] + 80013a2: 4b17 ldr r3, [pc, #92] @ (8001400 ) + 80013a4: 781a ldrb r2, [r3, #0] + 80013a6: 4b14 ldr r3, [pc, #80] @ (80013f8 ) + 80013a8: 781b ldrb r3, [r3, #0] + 80013aa: 429a cmp r2, r3 + 80013ac: d3e7 bcc.n 800137e } tx_checksum = ~tx_checksum; - 8001378: 4b13 ldr r3, [pc, #76] @ (80013c8 ) - 800137a: 881b ldrh r3, [r3, #0] - 800137c: 43db mvns r3, r3 - 800137e: b29a uxth r2, r3 - 8001380: 4b11 ldr r3, [pc, #68] @ (80013c8 ) - 8001382: 801a strh r2, [r3, #0] + 80013ae: 4b18 ldr r3, [pc, #96] @ (8001410 ) + 80013b0: 881b ldrh r3, [r3, #0] + 80013b2: 43db mvns r3, r3 + 80013b4: b29a uxth r2, r3 + 80013b6: 4b16 ldr r3, [pc, #88] @ (8001410 ) + 80013b8: 801a strh r2, [r3, #0] - tx_buffer[22] = (uint8_t)((tx_checksum >> 8) & 0xFF); - 8001384: 4b10 ldr r3, [pc, #64] @ (80013c8 ) - 8001386: 881b ldrh r3, [r3, #0] - 8001388: 0a1b lsrs r3, r3, #8 - 800138a: b29b uxth r3, r3 - 800138c: b2da uxtb r2, r3 - 800138e: 4b0b ldr r3, [pc, #44] @ (80013bc ) - 8001390: 759a strb r2, [r3, #22] - tx_buffer[23] = (uint8_t)(tx_checksum & 0xFF); - 8001392: 4b0d ldr r3, [pc, #52] @ (80013c8 ) - 8001394: 881b ldrh r3, [r3, #0] - 8001396: b2da uxtb r2, r3 - 8001398: 4b08 ldr r3, [pc, #32] @ (80013bc ) - 800139a: 75da strb r2, [r3, #23] + tx_buffer[tx_len + 3] = (uint8_t)((tx_checksum >> 8) & 0xFF); + 80013ba: 4b15 ldr r3, [pc, #84] @ (8001410 ) + 80013bc: 881b ldrh r3, [r3, #0] + 80013be: 0a1b lsrs r3, r3, #8 + 80013c0: b29a uxth r2, r3 + 80013c2: 4b0d ldr r3, [pc, #52] @ (80013f8 ) + 80013c4: 781b ldrb r3, [r3, #0] + 80013c6: 3303 adds r3, #3 + 80013c8: b2d1 uxtb r1, r2 + 80013ca: 4a0c ldr r2, [pc, #48] @ (80013fc ) + 80013cc: 54d1 strb r1, [r2, r3] + tx_buffer[tx_len + 4] = (uint8_t)(tx_checksum & 0xFF); + 80013ce: 4b10 ldr r3, [pc, #64] @ (8001410 ) + 80013d0: 881a ldrh r2, [r3, #0] + 80013d2: 4b09 ldr r3, [pc, #36] @ (80013f8 ) + 80013d4: 781b ldrb r3, [r3, #0] + 80013d6: 3304 adds r3, #4 + 80013d8: b2d1 uxtb r1, r2 + 80013da: 4a08 ldr r2, [pc, #32] @ (80013fc ) + 80013dc: 54d1 strb r1, [r2, r3] - tx_len = 0x18; - 800139c: 4b06 ldr r3, [pc, #24] @ (80013b8 ) - 800139e: 2218 movs r2, #24 - 80013a0: 701a strb r2, [r3, #0] + tx_len = 0x1B; + 80013de: 4b06 ldr r3, [pc, #24] @ (80013f8 ) + 80013e0: 221b movs r2, #27 + 80013e2: 701a strb r2, [r3, #0] HAL_UART_Transmit(&huart2, tx_buffer, tx_len, 100); - 80013a2: 4b05 ldr r3, [pc, #20] @ (80013b8 ) - 80013a4: 781b ldrb r3, [r3, #0] - 80013a6: 461a mov r2, r3 - 80013a8: 2364 movs r3, #100 @ 0x64 - 80013aa: 4904 ldr r1, [pc, #16] @ (80013bc ) - 80013ac: 4807 ldr r0, [pc, #28] @ (80013cc ) - 80013ae: f004 f8c5 bl 800553c + 80013e4: 4b04 ldr r3, [pc, #16] @ (80013f8 ) + 80013e6: 781b ldrb r3, [r3, #0] + 80013e8: 461a mov r2, r3 + 80013ea: 2364 movs r3, #100 @ 0x64 + 80013ec: 4903 ldr r1, [pc, #12] @ (80013fc ) + 80013ee: 4809 ldr r0, [pc, #36] @ (8001414 ) + 80013f0: f004 f8c8 bl 8005584 } - 80013b2: bf00 nop - 80013b4: bd80 pop {r7, pc} - 80013b6: bf00 nop - 80013b8: 20000238 .word 0x20000238 - 80013bc: 20000218 .word 0x20000218 - 80013c0: 20000239 .word 0x20000239 - 80013c4: 20000000 .word 0x20000000 - 80013c8: 20000240 .word 0x20000240 - 80013cc: 20000160 .word 0x20000160 + 80013f4: bf00 nop + 80013f6: bd80 pop {r7, pc} + 80013f8: 20000240 .word 0x20000240 + 80013fc: 20000220 .word 0x20000220 + 8001400: 20000241 .word 0x20000241 + 8001404: 20000004 .word 0x20000004 + 8001408: 200001f8 .word 0x200001f8 + 800140c: 20000000 .word 0x20000000 + 8001410: 20000248 .word 0x20000248 + 8001414: 20000164 .word 0x20000164 -080013d0 : +08001418 : /* ADC task */ void adc_task (void) { - 80013d0: b580 push {r7, lr} - 80013d2: af00 add r7, sp, #0 + 8001418: b580 push {r7, lr} + 800141a: af00 add r7, sp, #0 HAL_ADC_Start(&hadc2); - 80013d4: 4811 ldr r0, [pc, #68] @ (800141c ) - 80013d6: f000 ff93 bl 8002300 + 800141c: 4811 ldr r0, [pc, #68] @ (8001464 ) + 800141e: f000 ff93 bl 8002348 HAL_ADC_PollForConversion(&hadc2, 500); - 80013da: f44f 71fa mov.w r1, #500 @ 0x1f4 - 80013de: 480f ldr r0, [pc, #60] @ (800141c ) - 80013e0: f001 f87e bl 80024e0 + 8001422: f44f 71fa mov.w r1, #500 @ 0x1f4 + 8001426: 480f ldr r0, [pc, #60] @ (8001464 ) + 8001428: f001 f87e bl 8002528 vout_adc_val = HAL_ADC_GetValue(&hadc2); - 80013e4: 480d ldr r0, [pc, #52] @ (800141c ) - 80013e6: f001 f953 bl 8002690 - 80013ea: 4603 mov r3, r0 - 80013ec: b29a uxth r2, r3 - 80013ee: 4b0c ldr r3, [pc, #48] @ (8001420 ) - 80013f0: 801a strh r2, [r3, #0] + 800142c: 480d ldr r0, [pc, #52] @ (8001464 ) + 800142e: f001 f953 bl 80026d8 + 8001432: 4603 mov r3, r0 + 8001434: b29a uxth r2, r3 + 8001436: 4b0c ldr r3, [pc, #48] @ (8001468 ) + 8001438: 801a strh r2, [r3, #0] HAL_ADC_Start(&hadc2); - 80013f2: 480a ldr r0, [pc, #40] @ (800141c ) - 80013f4: f000 ff84 bl 8002300 + 800143a: 480a ldr r0, [pc, #40] @ (8001464 ) + 800143c: f000 ff84 bl 8002348 HAL_ADC_PollForConversion(&hadc2, 500); - 80013f8: f44f 71fa mov.w r1, #500 @ 0x1f4 - 80013fc: 4807 ldr r0, [pc, #28] @ (800141c ) - 80013fe: f001 f86f bl 80024e0 + 8001440: f44f 71fa mov.w r1, #500 @ 0x1f4 + 8001444: 4807 ldr r0, [pc, #28] @ (8001464 ) + 8001446: f001 f86f bl 8002528 vin_adc_val = HAL_ADC_GetValue(&hadc2); - 8001402: 4806 ldr r0, [pc, #24] @ (800141c ) - 8001404: f001 f944 bl 8002690 - 8001408: 4603 mov r3, r0 - 800140a: b29a uxth r2, r3 - 800140c: 4b05 ldr r3, [pc, #20] @ (8001424 ) - 800140e: 801a strh r2, [r3, #0] + 800144a: 4806 ldr r0, [pc, #24] @ (8001464 ) + 800144c: f001 f944 bl 80026d8 + 8001450: 4603 mov r3, r0 + 8001452: b29a uxth r2, r3 + 8001454: 4b05 ldr r3, [pc, #20] @ (800146c ) + 8001456: 801a strh r2, [r3, #0] HAL_ADC_Stop(&hadc2); - 8001410: 4802 ldr r0, [pc, #8] @ (800141c ) - 8001412: f001 f831 bl 8002478 + 8001458: 4802 ldr r0, [pc, #8] @ (8001464 ) + 800145a: f001 f831 bl 80024c0 } - 8001416: bf00 nop - 8001418: bd80 pop {r7, pc} - 800141a: bf00 nop - 800141c: 200000a8 .word 0x200000a8 - 8001420: 2000024c .word 0x2000024c - 8001424: 2000024a .word 0x2000024a + 800145e: bf00 nop + 8001460: bd80 pop {r7, pc} + 8001462: bf00 nop + 8001464: 200000ac .word 0x200000ac + 8001468: 20000254 .word 0x20000254 + 800146c: 20000252 .word 0x20000252 -08001428 : +08001470 : /* Power switch function */ void power_switch (uint8_t state) { - 8001428: b580 push {r7, lr} - 800142a: b082 sub sp, #8 - 800142c: af00 add r7, sp, #0 - 800142e: 4603 mov r3, r0 - 8001430: 71fb strb r3, [r7, #7] + 8001470: b580 push {r7, lr} + 8001472: b082 sub sp, #8 + 8001474: af00 add r7, sp, #0 + 8001476: 4603 mov r3, r0 + 8001478: 71fb strb r3, [r7, #7] if (state == 1) - 8001432: 79fb ldrb r3, [r7, #7] - 8001434: 2b01 cmp r3, #1 - 8001436: d10d bne.n 8001454 + 800147a: 79fb ldrb r3, [r7, #7] + 800147c: 2b01 cmp r3, #1 + 800147e: d10d bne.n 800149c { HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_SET); - 8001438: 2201 movs r2, #1 - 800143a: f44f 5180 mov.w r1, #4096 @ 0x1000 - 800143e: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001442: f002 fb6f bl 8003b24 + 8001480: 2201 movs r2, #1 + 8001482: f44f 5180 mov.w r1, #4096 @ 0x1000 + 8001486: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800148a: f002 fb6f bl 8003b6c HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_SET); - 8001446: 2201 movs r2, #1 - 8001448: f44f 7180 mov.w r1, #256 @ 0x100 - 800144c: 480a ldr r0, [pc, #40] @ (8001478 ) - 800144e: f002 fb69 bl 8003b24 + 800148e: 2201 movs r2, #1 + 8001490: f44f 7180 mov.w r1, #256 @ 0x100 + 8001494: 480a ldr r0, [pc, #40] @ (80014c0 ) + 8001496: f002 fb69 bl 8003b6c else { HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); } } - 8001452: e00c b.n 800146e + 800149a: e00c b.n 80014b6 HAL_GPIO_WritePin(POWER_SWITCH_GPIO_Port, POWER_SWITCH_Pin, GPIO_PIN_RESET); - 8001454: 2200 movs r2, #0 - 8001456: f44f 5180 mov.w r1, #4096 @ 0x1000 - 800145a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 800145e: f002 fb61 bl 8003b24 + 800149c: 2200 movs r2, #0 + 800149e: f44f 5180 mov.w r1, #4096 @ 0x1000 + 80014a2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 80014a6: f002 fb61 bl 8003b6c HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); - 8001462: 2200 movs r2, #0 - 8001464: f44f 7180 mov.w r1, #256 @ 0x100 - 8001468: 4803 ldr r0, [pc, #12] @ (8001478 ) - 800146a: f002 fb5b bl 8003b24 + 80014aa: 2200 movs r2, #0 + 80014ac: f44f 7180 mov.w r1, #256 @ 0x100 + 80014b0: 4803 ldr r0, [pc, #12] @ (80014c0 ) + 80014b2: f002 fb5b bl 8003b6c } - 800146e: bf00 nop - 8001470: 3708 adds r7, #8 - 8001472: 46bd mov sp, r7 - 8001474: bd80 pop {r7, pc} - 8001476: bf00 nop - 8001478: 48000400 .word 0x48000400 + 80014b6: bf00 nop + 80014b8: 3708 adds r7, #8 + 80014ba: 46bd mov sp, r7 + 80014bc: bd80 pop {r7, pc} + 80014be: bf00 nop + 80014c0: 48000400 .word 0x48000400 -0800147c : +080014c4 : /* UART Tx callback */ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { - 800147c: b480 push {r7} - 800147e: b083 sub sp, #12 - 8001480: af00 add r7, sp, #0 - 8001482: 6078 str r0, [r7, #4] + 80014c4: b480 push {r7} + 80014c6: b083 sub sp, #12 + 80014c8: af00 add r7, sp, #0 + 80014ca: 6078 str r0, [r7, #4] /* Do nothing here for now */ } - 8001484: bf00 nop - 8001486: 370c adds r7, #12 - 8001488: 46bd mov sp, r7 - 800148a: f85d 7b04 ldr.w r7, [sp], #4 - 800148e: 4770 bx lr + 80014cc: bf00 nop + 80014ce: 370c adds r7, #12 + 80014d0: 46bd mov sp, r7 + 80014d2: f85d 7b04 ldr.w r7, [sp], #4 + 80014d6: 4770 bx lr -08001490 : +080014d8 : /* UART Rx callback */ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { - 8001490: b580 push {r7, lr} - 8001492: b082 sub sp, #8 - 8001494: af00 add r7, sp, #0 - 8001496: 6078 str r0, [r7, #4] + 80014d8: b580 push {r7, lr} + 80014da: b082 sub sp, #8 + 80014dc: af00 add r7, sp, #0 + 80014de: 6078 str r0, [r7, #4] /* If data received on UART */ if(huart->Instance==USART2) - 8001498: 687b ldr r3, [r7, #4] - 800149a: 681b ldr r3, [r3, #0] - 800149c: 4a75 ldr r2, [pc, #468] @ (8001674 ) - 800149e: 4293 cmp r3, r2 - 80014a0: f040 80e3 bne.w 800166a + 80014e0: 687b ldr r3, [r7, #4] + 80014e2: 681b ldr r3, [r3, #0] + 80014e4: 4a75 ldr r2, [pc, #468] @ (80016bc ) + 80014e6: 4293 cmp r3, r2 + 80014e8: f040 80e3 bne.w 80016b2 { /* Act on received data */ switch (rx_counter) - 80014a4: 4b74 ldr r3, [pc, #464] @ (8001678 ) - 80014a6: 781b ldrb r3, [r3, #0] - 80014a8: 2b05 cmp r3, #5 - 80014aa: f200 80d4 bhi.w 8001656 - 80014ae: a201 add r2, pc, #4 @ (adr r2, 80014b4 ) - 80014b0: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80014b4: 080014cd .word 0x080014cd - 80014b8: 080014e5 .word 0x080014e5 - 80014bc: 08001513 .word 0x08001513 - 80014c0: 0800152f .word 0x0800152f - 80014c4: 0800156b .word 0x0800156b - 80014c8: 08001581 .word 0x08001581 + 80014ec: 4b74 ldr r3, [pc, #464] @ (80016c0 ) + 80014ee: 781b ldrb r3, [r3, #0] + 80014f0: 2b05 cmp r3, #5 + 80014f2: f200 80d4 bhi.w 800169e + 80014f6: a201 add r2, pc, #4 @ (adr r2, 80014fc ) + 80014f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80014fc: 08001515 .word 0x08001515 + 8001500: 0800152d .word 0x0800152d + 8001504: 0800155b .word 0x0800155b + 8001508: 08001577 .word 0x08001577 + 800150c: 080015b3 .word 0x080015b3 + 8001510: 080015c9 .word 0x080015c9 { case 0x00: /* Check to see if first sync byte has been received */ if (rx_hold_buffer[0] == IN_SYNC_BYTE_1) - 80014cc: 4b6b ldr r3, [pc, #428] @ (800167c ) - 80014ce: 781b ldrb r3, [r3, #0] - 80014d0: 2b41 cmp r3, #65 @ 0x41 - 80014d2: f040 80c2 bne.w 800165a + 8001514: 4b6b ldr r3, [pc, #428] @ (80016c4 ) + 8001516: 781b ldrb r3, [r3, #0] + 8001518: 2b41 cmp r3, #65 @ 0x41 + 800151a: f040 80c2 bne.w 80016a2 { /* Got it, so now wait for the second sync byte */ rx_counter++; - 80014d6: 4b68 ldr r3, [pc, #416] @ (8001678 ) - 80014d8: 781b ldrb r3, [r3, #0] - 80014da: 3301 adds r3, #1 - 80014dc: b2da uxtb r2, r3 - 80014de: 4b66 ldr r3, [pc, #408] @ (8001678 ) - 80014e0: 701a strb r2, [r3, #0] + 800151e: 4b68 ldr r3, [pc, #416] @ (80016c0 ) + 8001520: 781b ldrb r3, [r3, #0] + 8001522: 3301 adds r3, #1 + 8001524: b2da uxtb r2, r3 + 8001526: 4b66 ldr r3, [pc, #408] @ (80016c0 ) + 8001528: 701a strb r2, [r3, #0] } break; - 80014e2: e0ba b.n 800165a + 800152a: e0ba b.n 80016a2 case 0x01: /* Check to see if second sync byte has been received */ if (rx_hold_buffer[0] == IN_SYNC_BYTE_2) - 80014e4: 4b65 ldr r3, [pc, #404] @ (800167c ) - 80014e6: 781b ldrb r3, [r3, #0] - 80014e8: 2b52 cmp r3, #82 @ 0x52 - 80014ea: d106 bne.n 80014fa + 800152c: 4b65 ldr r3, [pc, #404] @ (80016c4 ) + 800152e: 781b ldrb r3, [r3, #0] + 8001530: 2b52 cmp r3, #82 @ 0x52 + 8001532: d106 bne.n 8001542 { /* Got it, so now wait for the data byte */ rx_counter++; - 80014ec: 4b62 ldr r3, [pc, #392] @ (8001678 ) - 80014ee: 781b ldrb r3, [r3, #0] - 80014f0: 3301 adds r3, #1 - 80014f2: b2da uxtb r2, r3 - 80014f4: 4b60 ldr r3, [pc, #384] @ (8001678 ) - 80014f6: 701a strb r2, [r3, #0] + 8001534: 4b62 ldr r3, [pc, #392] @ (80016c0 ) + 8001536: 781b ldrb r3, [r3, #0] + 8001538: 3301 adds r3, #1 + 800153a: b2da uxtb r2, r3 + 800153c: 4b60 ldr r3, [pc, #384] @ (80016c0 ) + 800153e: 701a strb r2, [r3, #0] { rx_counter = 0x00; } } break; - 80014f8: e0b2 b.n 8001660 + 8001540: e0b2 b.n 80016a8 if (rx_hold_buffer[0] == IN_SYNC_BYTE_1) - 80014fa: 4b60 ldr r3, [pc, #384] @ (800167c ) - 80014fc: 781b ldrb r3, [r3, #0] - 80014fe: 2b41 cmp r3, #65 @ 0x41 - 8001500: d103 bne.n 800150a + 8001542: 4b60 ldr r3, [pc, #384] @ (80016c4 ) + 8001544: 781b ldrb r3, [r3, #0] + 8001546: 2b41 cmp r3, #65 @ 0x41 + 8001548: d103 bne.n 8001552 rx_counter = 0x01; - 8001502: 4b5d ldr r3, [pc, #372] @ (8001678 ) - 8001504: 2201 movs r2, #1 - 8001506: 701a strb r2, [r3, #0] + 800154a: 4b5d ldr r3, [pc, #372] @ (80016c0 ) + 800154c: 2201 movs r2, #1 + 800154e: 701a strb r2, [r3, #0] break; - 8001508: e0aa b.n 8001660 + 8001550: e0aa b.n 80016a8 rx_counter = 0x00; - 800150a: 4b5b ldr r3, [pc, #364] @ (8001678 ) - 800150c: 2200 movs r2, #0 - 800150e: 701a strb r2, [r3, #0] + 8001552: 4b5b ldr r3, [pc, #364] @ (80016c0 ) + 8001554: 2200 movs r2, #0 + 8001556: 701a strb r2, [r3, #0] break; - 8001510: e0a6 b.n 8001660 + 8001558: e0a6 b.n 80016a8 case 0x02: /* Get rx length and reset counter */ rx_len = rx_hold_buffer[0]; - 8001512: 4b5a ldr r3, [pc, #360] @ (800167c ) - 8001514: 781a ldrb r2, [r3, #0] - 8001516: 4b5a ldr r3, [pc, #360] @ (8001680 ) - 8001518: 701a strb r2, [r3, #0] + 800155a: 4b5a ldr r3, [pc, #360] @ (80016c4 ) + 800155c: 781a ldrb r2, [r3, #0] + 800155e: 4b5a ldr r3, [pc, #360] @ (80016c8 ) + 8001560: 701a strb r2, [r3, #0] rx_len_counter = 0x00; - 800151a: 4b5a ldr r3, [pc, #360] @ (8001684 ) - 800151c: 2200 movs r2, #0 - 800151e: 701a strb r2, [r3, #0] + 8001562: 4b5a ldr r3, [pc, #360] @ (80016cc ) + 8001564: 2200 movs r2, #0 + 8001566: 701a strb r2, [r3, #0] rx_counter++; - 8001520: 4b55 ldr r3, [pc, #340] @ (8001678 ) - 8001522: 781b ldrb r3, [r3, #0] - 8001524: 3301 adds r3, #1 - 8001526: b2da uxtb r2, r3 - 8001528: 4b53 ldr r3, [pc, #332] @ (8001678 ) - 800152a: 701a strb r2, [r3, #0] + 8001568: 4b55 ldr r3, [pc, #340] @ (80016c0 ) + 800156a: 781b ldrb r3, [r3, #0] + 800156c: 3301 adds r3, #1 + 800156e: b2da uxtb r2, r3 + 8001570: 4b53 ldr r3, [pc, #332] @ (80016c0 ) + 8001572: 701a strb r2, [r3, #0] break; - 800152c: e098 b.n 8001660 + 8001574: e098 b.n 80016a8 case 0x03: /* Store entire length of Data bytes */ /* Increase count */ rx_len_counter++; - 800152e: 4b55 ldr r3, [pc, #340] @ (8001684 ) - 8001530: 781b ldrb r3, [r3, #0] - 8001532: 3301 adds r3, #1 - 8001534: b2da uxtb r2, r3 - 8001536: 4b53 ldr r3, [pc, #332] @ (8001684 ) - 8001538: 701a strb r2, [r3, #0] + 8001576: 4b55 ldr r3, [pc, #340] @ (80016cc ) + 8001578: 781b ldrb r3, [r3, #0] + 800157a: 3301 adds r3, #1 + 800157c: b2da uxtb r2, r3 + 800157e: 4b53 ldr r3, [pc, #332] @ (80016cc ) + 8001580: 701a strb r2, [r3, #0] /* Store data */ rx_buffer[rx_len_counter - 1] = rx_hold_buffer[0]; - 800153a: 4b52 ldr r3, [pc, #328] @ (8001684 ) - 800153c: 781b ldrb r3, [r3, #0] - 800153e: 3b01 subs r3, #1 - 8001540: 4a4e ldr r2, [pc, #312] @ (800167c ) - 8001542: 7811 ldrb r1, [r2, #0] - 8001544: 4a50 ldr r2, [pc, #320] @ (8001688 ) - 8001546: 54d1 strb r1, [r2, r3] + 8001582: 4b52 ldr r3, [pc, #328] @ (80016cc ) + 8001584: 781b ldrb r3, [r3, #0] + 8001586: 3b01 subs r3, #1 + 8001588: 4a4e ldr r2, [pc, #312] @ (80016c4 ) + 800158a: 7811 ldrb r1, [r2, #0] + 800158c: 4a50 ldr r2, [pc, #320] @ (80016d0 ) + 800158e: 54d1 strb r1, [r2, r3] /* Check to see if we have all the expected data bytes */ /* If so, then move on the CRC */ if (rx_len_counter == rx_len) - 8001548: 4b4e ldr r3, [pc, #312] @ (8001684 ) - 800154a: 781a ldrb r2, [r3, #0] - 800154c: 4b4c ldr r3, [pc, #304] @ (8001680 ) - 800154e: 781b ldrb r3, [r3, #0] - 8001550: 429a cmp r2, r3 - 8001552: f040 8084 bne.w 800165e + 8001590: 4b4e ldr r3, [pc, #312] @ (80016cc ) + 8001592: 781a ldrb r2, [r3, #0] + 8001594: 4b4c ldr r3, [pc, #304] @ (80016c8 ) + 8001596: 781b ldrb r3, [r3, #0] + 8001598: 429a cmp r2, r3 + 800159a: f040 8084 bne.w 80016a6 { rx_counter++; - 8001556: 4b48 ldr r3, [pc, #288] @ (8001678 ) - 8001558: 781b ldrb r3, [r3, #0] - 800155a: 3301 adds r3, #1 - 800155c: b2da uxtb r2, r3 - 800155e: 4b46 ldr r3, [pc, #280] @ (8001678 ) - 8001560: 701a strb r2, [r3, #0] + 800159e: 4b48 ldr r3, [pc, #288] @ (80016c0 ) + 80015a0: 781b ldrb r3, [r3, #0] + 80015a2: 3301 adds r3, #1 + 80015a4: b2da uxtb r2, r3 + 80015a6: 4b46 ldr r3, [pc, #280] @ (80016c0 ) + 80015a8: 701a strb r2, [r3, #0] rx_len_counter = 0x00; - 8001562: 4b48 ldr r3, [pc, #288] @ (8001684 ) - 8001564: 2200 movs r2, #0 - 8001566: 701a strb r2, [r3, #0] + 80015aa: 4b48 ldr r3, [pc, #288] @ (80016cc ) + 80015ac: 2200 movs r2, #0 + 80015ae: 701a strb r2, [r3, #0] } break; - 8001568: e079 b.n 800165e + 80015b0: e079 b.n 80016a6 case 0x04: /* Store Rx checksum byte #1 */ rx_checksum_hold_1 = rx_hold_buffer[0]; - 800156a: 4b44 ldr r3, [pc, #272] @ (800167c ) - 800156c: 781a ldrb r2, [r3, #0] - 800156e: 4b47 ldr r3, [pc, #284] @ (800168c ) - 8001570: 701a strb r2, [r3, #0] + 80015b2: 4b44 ldr r3, [pc, #272] @ (80016c4 ) + 80015b4: 781a ldrb r2, [r3, #0] + 80015b6: 4b47 ldr r3, [pc, #284] @ (80016d4 ) + 80015b8: 701a strb r2, [r3, #0] rx_counter++; - 8001572: 4b41 ldr r3, [pc, #260] @ (8001678 ) - 8001574: 781b ldrb r3, [r3, #0] - 8001576: 3301 adds r3, #1 - 8001578: b2da uxtb r2, r3 - 800157a: 4b3f ldr r3, [pc, #252] @ (8001678 ) - 800157c: 701a strb r2, [r3, #0] + 80015ba: 4b41 ldr r3, [pc, #260] @ (80016c0 ) + 80015bc: 781b ldrb r3, [r3, #0] + 80015be: 3301 adds r3, #1 + 80015c0: b2da uxtb r2, r3 + 80015c2: 4b3f ldr r3, [pc, #252] @ (80016c0 ) + 80015c4: 701a strb r2, [r3, #0] break; - 800157e: e06f b.n 8001660 + 80015c6: e06f b.n 80016a8 case 0x05: /* Store Rx checksum byte #2, reset and calculate checksum */ rx_checksum_hold_2 = rx_hold_buffer[0]; - 8001580: 4b3e ldr r3, [pc, #248] @ (800167c ) - 8001582: 781a ldrb r2, [r3, #0] - 8001584: 4b42 ldr r3, [pc, #264] @ (8001690 ) - 8001586: 701a strb r2, [r3, #0] + 80015c8: 4b3e ldr r3, [pc, #248] @ (80016c4 ) + 80015ca: 781a ldrb r2, [r3, #0] + 80015cc: 4b42 ldr r3, [pc, #264] @ (80016d8 ) + 80015ce: 701a strb r2, [r3, #0] rx_checksum_hold = (rx_checksum_hold_1 << 8) | rx_checksum_hold_2; - 8001588: 4b40 ldr r3, [pc, #256] @ (800168c ) - 800158a: 781b ldrb r3, [r3, #0] - 800158c: b21b sxth r3, r3 - 800158e: 021b lsls r3, r3, #8 - 8001590: b21a sxth r2, r3 - 8001592: 4b3f ldr r3, [pc, #252] @ (8001690 ) - 8001594: 781b ldrb r3, [r3, #0] - 8001596: b21b sxth r3, r3 - 8001598: 4313 orrs r3, r2 - 800159a: b21b sxth r3, r3 - 800159c: b29a uxth r2, r3 - 800159e: 4b3d ldr r3, [pc, #244] @ (8001694 ) - 80015a0: 801a strh r2, [r3, #0] + 80015d0: 4b40 ldr r3, [pc, #256] @ (80016d4 ) + 80015d2: 781b ldrb r3, [r3, #0] + 80015d4: b21b sxth r3, r3 + 80015d6: 021b lsls r3, r3, #8 + 80015d8: b21a sxth r2, r3 + 80015da: 4b3f ldr r3, [pc, #252] @ (80016d8 ) + 80015dc: 781b ldrb r3, [r3, #0] + 80015de: b21b sxth r3, r3 + 80015e0: 4313 orrs r3, r2 + 80015e2: b21b sxth r3, r3 + 80015e4: b29a uxth r2, r3 + 80015e6: 4b3d ldr r3, [pc, #244] @ (80016dc ) + 80015e8: 801a strh r2, [r3, #0] rx_checksum = 0; - 80015a2: 4b3d ldr r3, [pc, #244] @ (8001698 ) - 80015a4: 2200 movs r2, #0 - 80015a6: 801a strh r2, [r3, #0] + 80015ea: 4b3d ldr r3, [pc, #244] @ (80016e0 ) + 80015ec: 2200 movs r2, #0 + 80015ee: 801a strh r2, [r3, #0] /* Need to apply to all data bits */ for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++) - 80015a8: 4b36 ldr r3, [pc, #216] @ (8001684 ) - 80015aa: 2200 movs r2, #0 - 80015ac: 701a strb r2, [r3, #0] - 80015ae: e011 b.n 80015d4 + 80015f0: 4b36 ldr r3, [pc, #216] @ (80016cc ) + 80015f2: 2200 movs r2, #0 + 80015f4: 701a strb r2, [r3, #0] + 80015f6: e011 b.n 800161c { rx_checksum += rx_buffer[rx_len_counter]; - 80015b0: 4b34 ldr r3, [pc, #208] @ (8001684 ) - 80015b2: 781b ldrb r3, [r3, #0] - 80015b4: 461a mov r2, r3 - 80015b6: 4b34 ldr r3, [pc, #208] @ (8001688 ) - 80015b8: 5c9b ldrb r3, [r3, r2] - 80015ba: 461a mov r2, r3 - 80015bc: 4b36 ldr r3, [pc, #216] @ (8001698 ) - 80015be: 881b ldrh r3, [r3, #0] - 80015c0: 4413 add r3, r2 - 80015c2: b29a uxth r2, r3 - 80015c4: 4b34 ldr r3, [pc, #208] @ (8001698 ) - 80015c6: 801a strh r2, [r3, #0] + 80015f8: 4b34 ldr r3, [pc, #208] @ (80016cc ) + 80015fa: 781b ldrb r3, [r3, #0] + 80015fc: 461a mov r2, r3 + 80015fe: 4b34 ldr r3, [pc, #208] @ (80016d0 ) + 8001600: 5c9b ldrb r3, [r3, r2] + 8001602: 461a mov r2, r3 + 8001604: 4b36 ldr r3, [pc, #216] @ (80016e0 ) + 8001606: 881b ldrh r3, [r3, #0] + 8001608: 4413 add r3, r2 + 800160a: b29a uxth r2, r3 + 800160c: 4b34 ldr r3, [pc, #208] @ (80016e0 ) + 800160e: 801a strh r2, [r3, #0] for (rx_len_counter = 0x00; rx_len_counter < rx_len; rx_len_counter++) - 80015c8: 4b2e ldr r3, [pc, #184] @ (8001684 ) - 80015ca: 781b ldrb r3, [r3, #0] - 80015cc: 3301 adds r3, #1 - 80015ce: b2da uxtb r2, r3 - 80015d0: 4b2c ldr r3, [pc, #176] @ (8001684 ) - 80015d2: 701a strb r2, [r3, #0] - 80015d4: 4b2b ldr r3, [pc, #172] @ (8001684 ) - 80015d6: 781a ldrb r2, [r3, #0] - 80015d8: 4b29 ldr r3, [pc, #164] @ (8001680 ) - 80015da: 781b ldrb r3, [r3, #0] - 80015dc: 429a cmp r2, r3 - 80015de: d3e7 bcc.n 80015b0 + 8001610: 4b2e ldr r3, [pc, #184] @ (80016cc ) + 8001612: 781b ldrb r3, [r3, #0] + 8001614: 3301 adds r3, #1 + 8001616: b2da uxtb r2, r3 + 8001618: 4b2c ldr r3, [pc, #176] @ (80016cc ) + 800161a: 701a strb r2, [r3, #0] + 800161c: 4b2b ldr r3, [pc, #172] @ (80016cc ) + 800161e: 781a ldrb r2, [r3, #0] + 8001620: 4b29 ldr r3, [pc, #164] @ (80016c8 ) + 8001622: 781b ldrb r3, [r3, #0] + 8001624: 429a cmp r2, r3 + 8001626: d3e7 bcc.n 80015f8 } rx_len = 0x00; - 80015e0: 4b27 ldr r3, [pc, #156] @ (8001680 ) - 80015e2: 2200 movs r2, #0 - 80015e4: 701a strb r2, [r3, #0] + 8001628: 4b27 ldr r3, [pc, #156] @ (80016c8 ) + 800162a: 2200 movs r2, #0 + 800162c: 701a strb r2, [r3, #0] rx_len_counter = 0x00; - 80015e6: 4b27 ldr r3, [pc, #156] @ (8001684 ) - 80015e8: 2200 movs r2, #0 - 80015ea: 701a strb r2, [r3, #0] + 800162e: 4b27 ldr r3, [pc, #156] @ (80016cc ) + 8001630: 2200 movs r2, #0 + 8001632: 701a strb r2, [r3, #0] rx_checksum = ~rx_checksum; - 80015ec: 4b2a ldr r3, [pc, #168] @ (8001698 ) - 80015ee: 881b ldrh r3, [r3, #0] - 80015f0: 43db mvns r3, r3 - 80015f2: b29a uxth r2, r3 - 80015f4: 4b28 ldr r3, [pc, #160] @ (8001698 ) - 80015f6: 801a strh r2, [r3, #0] + 8001634: 4b2a ldr r3, [pc, #168] @ (80016e0 ) + 8001636: 881b ldrh r3, [r3, #0] + 8001638: 43db mvns r3, r3 + 800163a: b29a uxth r2, r3 + 800163c: 4b28 ldr r3, [pc, #160] @ (80016e0 ) + 800163e: 801a strh r2, [r3, #0] /* If checksum calculated equals the received checksum of packet then we got a good packet */ if (rx_checksum == rx_checksum_hold) - 80015f8: 4b27 ldr r3, [pc, #156] @ (8001698 ) - 80015fa: 881a ldrh r2, [r3, #0] - 80015fc: 4b25 ldr r3, [pc, #148] @ (8001694 ) - 80015fe: 881b ldrh r3, [r3, #0] - 8001600: 429a cmp r2, r3 - 8001602: d122 bne.n 800164a + 8001640: 4b27 ldr r3, [pc, #156] @ (80016e0 ) + 8001642: 881a ldrh r2, [r3, #0] + 8001644: 4b25 ldr r3, [pc, #148] @ (80016dc ) + 8001646: 881b ldrh r3, [r3, #0] + 8001648: 429a cmp r2, r3 + 800164a: d122 bne.n 8001692 { /* Rx is finished, so reset count to wait for another first sync byte (also act on command/data)*/ rx_counter = 0x00; - 8001604: 4b1c ldr r3, [pc, #112] @ (8001678 ) - 8001606: 2200 movs r2, #0 - 8001608: 701a strb r2, [r3, #0] + 800164c: 4b1c ldr r3, [pc, #112] @ (80016c0 ) + 800164e: 2200 movs r2, #0 + 8001650: 701a strb r2, [r3, #0] command = rx_buffer[0]; - 800160a: 4b1f ldr r3, [pc, #124] @ (8001688 ) - 800160c: 781a ldrb r2, [r3, #0] - 800160e: 4b23 ldr r3, [pc, #140] @ (800169c ) - 8001610: 701a strb r2, [r3, #0] + 8001652: 4b1f ldr r3, [pc, #124] @ (80016d0 ) + 8001654: 781a ldrb r2, [r3, #0] + 8001656: 4b23 ldr r3, [pc, #140] @ (80016e4 ) + 8001658: 701a strb r2, [r3, #0] switch (command) - 8001612: 4b22 ldr r3, [pc, #136] @ (800169c ) - 8001614: 781b ldrb r3, [r3, #0] - 8001616: 2b56 cmp r3, #86 @ 0x56 - 8001618: d00f beq.n 800163a - 800161a: 2b56 cmp r3, #86 @ 0x56 - 800161c: dc19 bgt.n 8001652 - 800161e: 2b49 cmp r3, #73 @ 0x49 - 8001620: d00f beq.n 8001642 - 8001622: 2b53 cmp r3, #83 @ 0x53 - 8001624: d115 bne.n 8001652 + 800165a: 4b22 ldr r3, [pc, #136] @ (80016e4 ) + 800165c: 781b ldrb r3, [r3, #0] + 800165e: 2b56 cmp r3, #86 @ 0x56 + 8001660: d00f beq.n 8001682 + 8001662: 2b56 cmp r3, #86 @ 0x56 + 8001664: dc19 bgt.n 800169a + 8001666: 2b49 cmp r3, #73 @ 0x49 + 8001668: d00f beq.n 800168a + 800166a: 2b53 cmp r3, #83 @ 0x53 + 800166c: d115 bne.n 800169a { /* 'S' - Set power output state */ case 0x53: power_state_value = rx_buffer[1]; - 8001626: 4b18 ldr r3, [pc, #96] @ (8001688 ) - 8001628: 785a ldrb r2, [r3, #1] - 800162a: 4b1d ldr r3, [pc, #116] @ (80016a0 ) - 800162c: 701a strb r2, [r3, #0] + 800166e: 4b18 ldr r3, [pc, #96] @ (80016d0 ) + 8001670: 785a ldrb r2, [r3, #1] + 8001672: 4b1d ldr r3, [pc, #116] @ (80016e8 ) + 8001674: 701a strb r2, [r3, #0] power_switch(power_state_value); - 800162e: 4b1c ldr r3, [pc, #112] @ (80016a0 ) - 8001630: 781b ldrb r3, [r3, #0] - 8001632: 4618 mov r0, r3 - 8001634: f7ff fef8 bl 8001428 + 8001676: 4b1c ldr r3, [pc, #112] @ (80016e8 ) + 8001678: 781b ldrb r3, [r3, #0] + 800167a: 4618 mov r0, r3 + 800167c: f7ff fef8 bl 8001470 break; - 8001638: e00c b.n 8001654 + 8001680: e00c b.n 800169c /* 'V' - Get voltages (both input and output) */ case 0x56: adc_task_flag = 0xff; - 800163a: 4b1a ldr r3, [pc, #104] @ (80016a4 ) - 800163c: 22ff movs r2, #255 @ 0xff - 800163e: 701a strb r2, [r3, #0] + 8001682: 4b1a ldr r3, [pc, #104] @ (80016ec ) + 8001684: 22ff movs r2, #255 @ 0xff + 8001686: 701a strb r2, [r3, #0] break; - 8001640: e008 b.n 8001654 + 8001688: e008 b.n 800169c /* 'I' - Get serial number information */ case 0x49: serial_number_flag = 0xff; - 8001642: 4b19 ldr r3, [pc, #100] @ (80016a8 ) - 8001644: 22ff movs r2, #255 @ 0xff - 8001646: 701a strb r2, [r3, #0] + 800168a: 4b19 ldr r3, [pc, #100] @ (80016f0 ) + 800168c: 22ff movs r2, #255 @ 0xff + 800168e: 701a strb r2, [r3, #0] break; - 8001648: e004 b.n 8001654 + 8001690: e004 b.n 800169c /* Bad packet received */ else { /* Rx is finished, so reset count to wait for another first sync byte (bad packet so no flag)*/ rx_counter = 0x00; - 800164a: 4b0b ldr r3, [pc, #44] @ (8001678 ) - 800164c: 2200 movs r2, #0 - 800164e: 701a strb r2, [r3, #0] + 8001692: 4b0b ldr r3, [pc, #44] @ (80016c0 ) + 8001694: 2200 movs r2, #0 + 8001696: 701a strb r2, [r3, #0] } break; - 8001650: e006 b.n 8001660 + 8001698: e006 b.n 80016a8 break; - 8001652: bf00 nop + 800169a: bf00 nop break; - 8001654: e004 b.n 8001660 + 800169c: e004 b.n 80016a8 /* Default case - NOT USED!*/ default: break; - 8001656: bf00 nop - 8001658: e002 b.n 8001660 + 800169e: bf00 nop + 80016a0: e002 b.n 80016a8 break; - 800165a: bf00 nop - 800165c: e000 b.n 8001660 + 80016a2: bf00 nop + 80016a4: e000 b.n 80016a8 break; - 800165e: bf00 nop + 80016a6: bf00 nop } /* Reset interrupts */ HAL_UART_Receive_IT(&huart2, rx_hold_buffer, 1); - 8001660: 2201 movs r2, #1 - 8001662: 4906 ldr r1, [pc, #24] @ (800167c ) - 8001664: 4811 ldr r0, [pc, #68] @ (80016ac ) - 8001666: f003 fff7 bl 8005658 + 80016a8: 2201 movs r2, #1 + 80016aa: 4906 ldr r1, [pc, #24] @ (80016c4 ) + 80016ac: 4811 ldr r0, [pc, #68] @ (80016f4 ) + 80016ae: f003 fff7 bl 80056a0 } } - 800166a: bf00 nop - 800166c: 3708 adds r7, #8 - 800166e: 46bd mov sp, r7 - 8001670: bd80 pop {r7, pc} - 8001672: bf00 nop - 8001674: 40004400 .word 0x40004400 - 8001678: 2000023a .word 0x2000023a - 800167c: 200001f4 .word 0x200001f4 - 8001680: 2000023b .word 0x2000023b - 8001684: 2000023c .word 0x2000023c - 8001688: 200001f8 .word 0x200001f8 - 800168c: 20000242 .word 0x20000242 - 8001690: 20000243 .word 0x20000243 - 8001694: 20000244 .word 0x20000244 - 8001698: 2000023e .word 0x2000023e - 800169c: 20000247 .word 0x20000247 - 80016a0: 20000246 .word 0x20000246 - 80016a4: 20000248 .word 0x20000248 - 80016a8: 2000025c .word 0x2000025c - 80016ac: 20000160 .word 0x20000160 + 80016b2: bf00 nop + 80016b4: 3708 adds r7, #8 + 80016b6: 46bd mov sp, r7 + 80016b8: bd80 pop {r7, pc} + 80016ba: bf00 nop + 80016bc: 40004400 .word 0x40004400 + 80016c0: 20000242 .word 0x20000242 + 80016c4: 200001fc .word 0x200001fc + 80016c8: 20000243 .word 0x20000243 + 80016cc: 20000244 .word 0x20000244 + 80016d0: 20000200 .word 0x20000200 + 80016d4: 2000024a .word 0x2000024a + 80016d8: 2000024b .word 0x2000024b + 80016dc: 2000024c .word 0x2000024c + 80016e0: 20000246 .word 0x20000246 + 80016e4: 2000024f .word 0x2000024f + 80016e8: 2000024e .word 0x2000024e + 80016ec: 20000250 .word 0x20000250 + 80016f0: 20000264 .word 0x20000264 + 80016f4: 20000164 .word 0x20000164 -080016b0 : +080016f8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 80016b0: b480 push {r7} - 80016b2: af00 add r7, sp, #0 + 80016f8: b480 push {r7} + 80016fa: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 80016b4: b672 cpsid i + 80016fc: b672 cpsid i } - 80016b6: bf00 nop + 80016fe: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 80016b8: bf00 nop - 80016ba: e7fd b.n 80016b8 + 8001700: bf00 nop + 8001702: e7fd b.n 8001700 -080016bc : +08001704 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 80016bc: b580 push {r7, lr} - 80016be: b082 sub sp, #8 - 80016c0: af00 add r7, sp, #0 + 8001704: b580 push {r7, lr} + 8001706: b082 sub sp, #8 + 8001708: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 80016c2: 4b0f ldr r3, [pc, #60] @ (8001700 ) - 80016c4: 6e1b ldr r3, [r3, #96] @ 0x60 - 80016c6: 4a0e ldr r2, [pc, #56] @ (8001700 ) - 80016c8: f043 0301 orr.w r3, r3, #1 - 80016cc: 6613 str r3, [r2, #96] @ 0x60 - 80016ce: 4b0c ldr r3, [pc, #48] @ (8001700 ) - 80016d0: 6e1b ldr r3, [r3, #96] @ 0x60 - 80016d2: f003 0301 and.w r3, r3, #1 - 80016d6: 607b str r3, [r7, #4] - 80016d8: 687b ldr r3, [r7, #4] + 800170a: 4b0f ldr r3, [pc, #60] @ (8001748 ) + 800170c: 6e1b ldr r3, [r3, #96] @ 0x60 + 800170e: 4a0e ldr r2, [pc, #56] @ (8001748 ) + 8001710: f043 0301 orr.w r3, r3, #1 + 8001714: 6613 str r3, [r2, #96] @ 0x60 + 8001716: 4b0c ldr r3, [pc, #48] @ (8001748 ) + 8001718: 6e1b ldr r3, [r3, #96] @ 0x60 + 800171a: f003 0301 and.w r3, r3, #1 + 800171e: 607b str r3, [r7, #4] + 8001720: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 80016da: 4b09 ldr r3, [pc, #36] @ (8001700 ) - 80016dc: 6d9b ldr r3, [r3, #88] @ 0x58 - 80016de: 4a08 ldr r2, [pc, #32] @ (8001700 ) - 80016e0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 80016e4: 6593 str r3, [r2, #88] @ 0x58 - 80016e6: 4b06 ldr r3, [pc, #24] @ (8001700 ) - 80016e8: 6d9b ldr r3, [r3, #88] @ 0x58 - 80016ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80016ee: 603b str r3, [r7, #0] - 80016f0: 683b ldr r3, [r7, #0] + 8001722: 4b09 ldr r3, [pc, #36] @ (8001748 ) + 8001724: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001726: 4a08 ldr r2, [pc, #32] @ (8001748 ) + 8001728: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800172c: 6593 str r3, [r2, #88] @ 0x58 + 800172e: 4b06 ldr r3, [pc, #24] @ (8001748 ) + 8001730: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001732: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001736: 603b str r3, [r7, #0] + 8001738: 683b ldr r3, [r7, #0] /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_PWREx_DisableUCPDDeadBattery(); - 80016f2: f002 fad3 bl 8003c9c + 800173a: f002 fad3 bl 8003ce4 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 80016f6: bf00 nop - 80016f8: 3708 adds r7, #8 - 80016fa: 46bd mov sp, r7 - 80016fc: bd80 pop {r7, pc} - 80016fe: bf00 nop - 8001700: 40021000 .word 0x40021000 + 800173e: bf00 nop + 8001740: 3708 adds r7, #8 + 8001742: 46bd mov sp, r7 + 8001744: bd80 pop {r7, pc} + 8001746: bf00 nop + 8001748: 40021000 .word 0x40021000 -08001704 : +0800174c : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { - 8001704: b580 push {r7, lr} - 8001706: b09c sub sp, #112 @ 0x70 - 8001708: af00 add r7, sp, #0 - 800170a: 6078 str r0, [r7, #4] + 800174c: b580 push {r7, lr} + 800174e: b09c sub sp, #112 @ 0x70 + 8001750: af00 add r7, sp, #0 + 8001752: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800170c: f107 035c add.w r3, r7, #92 @ 0x5c - 8001710: 2200 movs r2, #0 - 8001712: 601a str r2, [r3, #0] - 8001714: 605a str r2, [r3, #4] - 8001716: 609a str r2, [r3, #8] - 8001718: 60da str r2, [r3, #12] - 800171a: 611a str r2, [r3, #16] + 8001754: f107 035c add.w r3, r7, #92 @ 0x5c + 8001758: 2200 movs r2, #0 + 800175a: 601a str r2, [r3, #0] + 800175c: 605a str r2, [r3, #4] + 800175e: 609a str r2, [r3, #8] + 8001760: 60da str r2, [r3, #12] + 8001762: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 800171c: f107 0318 add.w r3, r7, #24 - 8001720: 2244 movs r2, #68 @ 0x44 - 8001722: 2100 movs r1, #0 - 8001724: 4618 mov r0, r3 - 8001726: f005 ffc9 bl 80076bc + 8001764: f107 0318 add.w r3, r7, #24 + 8001768: 2244 movs r2, #68 @ 0x44 + 800176a: 2100 movs r1, #0 + 800176c: 4618 mov r0, r3 + 800176e: f005 ffc9 bl 8007704 if(hadc->Instance==ADC1) - 800172a: 687b ldr r3, [r7, #4] - 800172c: 681b ldr r3, [r3, #0] - 800172e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8001732: d125 bne.n 8001780 + 8001772: 687b ldr r3, [r7, #4] + 8001774: 681b ldr r3, [r3, #0] + 8001776: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 800177a: d125 bne.n 80017c8 /* USER CODE END ADC1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; - 8001734: f44f 4300 mov.w r3, #32768 @ 0x8000 - 8001738: 61bb str r3, [r7, #24] + 800177c: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8001780: 61bb str r3, [r7, #24] PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; - 800173a: f04f 5300 mov.w r3, #536870912 @ 0x20000000 - 800173e: 657b str r3, [r7, #84] @ 0x54 + 8001782: f04f 5300 mov.w r3, #536870912 @ 0x20000000 + 8001786: 657b str r3, [r7, #84] @ 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8001740: f107 0318 add.w r3, r7, #24 - 8001744: 4618 mov r0, r3 - 8001746: f002 ffe7 bl 8004718 - 800174a: 4603 mov r3, r0 - 800174c: 2b00 cmp r3, #0 - 800174e: d001 beq.n 8001754 + 8001788: f107 0318 add.w r3, r7, #24 + 800178c: 4618 mov r0, r3 + 800178e: f002 ffe7 bl 8004760 + 8001792: 4603 mov r3, r0 + 8001794: 2b00 cmp r3, #0 + 8001796: d001 beq.n 800179c { Error_Handler(); - 8001750: f7ff ffae bl 80016b0 + 8001798: f7ff ffae bl 80016f8 } /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; - 8001754: 4b2e ldr r3, [pc, #184] @ (8001810 ) - 8001756: 681b ldr r3, [r3, #0] - 8001758: 3301 adds r3, #1 - 800175a: 4a2d ldr r2, [pc, #180] @ (8001810 ) - 800175c: 6013 str r3, [r2, #0] + 800179c: 4b2e ldr r3, [pc, #184] @ (8001858 ) + 800179e: 681b ldr r3, [r3, #0] + 80017a0: 3301 adds r3, #1 + 80017a2: 4a2d ldr r2, [pc, #180] @ (8001858 ) + 80017a4: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ - 800175e: 4b2c ldr r3, [pc, #176] @ (8001810 ) - 8001760: 681b ldr r3, [r3, #0] - 8001762: 2b01 cmp r3, #1 - 8001764: d14f bne.n 8001806 + 80017a6: 4b2c ldr r3, [pc, #176] @ (8001858 ) + 80017a8: 681b ldr r3, [r3, #0] + 80017aa: 2b01 cmp r3, #1 + 80017ac: d14f bne.n 800184e __HAL_RCC_ADC12_CLK_ENABLE(); - 8001766: 4b2b ldr r3, [pc, #172] @ (8001814 ) - 8001768: 6cdb ldr r3, [r3, #76] @ 0x4c - 800176a: 4a2a ldr r2, [pc, #168] @ (8001814 ) - 800176c: f443 5300 orr.w r3, r3, #8192 @ 0x2000 - 8001770: 64d3 str r3, [r2, #76] @ 0x4c - 8001772: 4b28 ldr r3, [pc, #160] @ (8001814 ) - 8001774: 6cdb ldr r3, [r3, #76] @ 0x4c - 8001776: f403 5300 and.w r3, r3, #8192 @ 0x2000 - 800177a: 617b str r3, [r7, #20] - 800177c: 697b ldr r3, [r7, #20] + 80017ae: 4b2b ldr r3, [pc, #172] @ (800185c ) + 80017b0: 6cdb ldr r3, [r3, #76] @ 0x4c + 80017b2: 4a2a ldr r2, [pc, #168] @ (800185c ) + 80017b4: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 80017b8: 64d3 str r3, [r2, #76] @ 0x4c + 80017ba: 4b28 ldr r3, [pc, #160] @ (800185c ) + 80017bc: 6cdb ldr r3, [r3, #76] @ 0x4c + 80017be: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 80017c2: 617b str r3, [r7, #20] + 80017c4: 697b ldr r3, [r7, #20] /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } } - 800177e: e042 b.n 8001806 + 80017c6: e042 b.n 800184e else if(hadc->Instance==ADC2) - 8001780: 687b ldr r3, [r7, #4] - 8001782: 681b ldr r3, [r3, #0] - 8001784: 4a24 ldr r2, [pc, #144] @ (8001818 ) - 8001786: 4293 cmp r3, r2 - 8001788: d13d bne.n 8001806 + 80017c8: 687b ldr r3, [r7, #4] + 80017ca: 681b ldr r3, [r3, #0] + 80017cc: 4a24 ldr r2, [pc, #144] @ (8001860 ) + 80017ce: 4293 cmp r3, r2 + 80017d0: d13d bne.n 800184e PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC12; - 800178a: f44f 4300 mov.w r3, #32768 @ 0x8000 - 800178e: 61bb str r3, [r7, #24] + 80017d2: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80017d6: 61bb str r3, [r7, #24] PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; - 8001790: f04f 5300 mov.w r3, #536870912 @ 0x20000000 - 8001794: 657b str r3, [r7, #84] @ 0x54 + 80017d8: f04f 5300 mov.w r3, #536870912 @ 0x20000000 + 80017dc: 657b str r3, [r7, #84] @ 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 8001796: f107 0318 add.w r3, r7, #24 - 800179a: 4618 mov r0, r3 - 800179c: f002 ffbc bl 8004718 - 80017a0: 4603 mov r3, r0 - 80017a2: 2b00 cmp r3, #0 - 80017a4: d001 beq.n 80017aa + 80017de: f107 0318 add.w r3, r7, #24 + 80017e2: 4618 mov r0, r3 + 80017e4: f002 ffbc bl 8004760 + 80017e8: 4603 mov r3, r0 + 80017ea: 2b00 cmp r3, #0 + 80017ec: d001 beq.n 80017f2 Error_Handler(); - 80017a6: f7ff ff83 bl 80016b0 + 80017ee: f7ff ff83 bl 80016f8 HAL_RCC_ADC12_CLK_ENABLED++; - 80017aa: 4b19 ldr r3, [pc, #100] @ (8001810 ) - 80017ac: 681b ldr r3, [r3, #0] - 80017ae: 3301 adds r3, #1 - 80017b0: 4a17 ldr r2, [pc, #92] @ (8001810 ) - 80017b2: 6013 str r3, [r2, #0] + 80017f2: 4b19 ldr r3, [pc, #100] @ (8001858 ) + 80017f4: 681b ldr r3, [r3, #0] + 80017f6: 3301 adds r3, #1 + 80017f8: 4a17 ldr r2, [pc, #92] @ (8001858 ) + 80017fa: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ - 80017b4: 4b16 ldr r3, [pc, #88] @ (8001810 ) - 80017b6: 681b ldr r3, [r3, #0] - 80017b8: 2b01 cmp r3, #1 - 80017ba: d10b bne.n 80017d4 + 80017fc: 4b16 ldr r3, [pc, #88] @ (8001858 ) + 80017fe: 681b ldr r3, [r3, #0] + 8001800: 2b01 cmp r3, #1 + 8001802: d10b bne.n 800181c __HAL_RCC_ADC12_CLK_ENABLE(); - 80017bc: 4b15 ldr r3, [pc, #84] @ (8001814 ) - 80017be: 6cdb ldr r3, [r3, #76] @ 0x4c - 80017c0: 4a14 ldr r2, [pc, #80] @ (8001814 ) - 80017c2: f443 5300 orr.w r3, r3, #8192 @ 0x2000 - 80017c6: 64d3 str r3, [r2, #76] @ 0x4c - 80017c8: 4b12 ldr r3, [pc, #72] @ (8001814 ) - 80017ca: 6cdb ldr r3, [r3, #76] @ 0x4c - 80017cc: f403 5300 and.w r3, r3, #8192 @ 0x2000 - 80017d0: 613b str r3, [r7, #16] - 80017d2: 693b ldr r3, [r7, #16] + 8001804: 4b15 ldr r3, [pc, #84] @ (800185c ) + 8001806: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001808: 4a14 ldr r2, [pc, #80] @ (800185c ) + 800180a: f443 5300 orr.w r3, r3, #8192 @ 0x2000 + 800180e: 64d3 str r3, [r2, #76] @ 0x4c + 8001810: 4b12 ldr r3, [pc, #72] @ (800185c ) + 8001812: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001814: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8001818: 613b str r3, [r7, #16] + 800181a: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 80017d4: 4b0f ldr r3, [pc, #60] @ (8001814 ) - 80017d6: 6cdb ldr r3, [r3, #76] @ 0x4c - 80017d8: 4a0e ldr r2, [pc, #56] @ (8001814 ) - 80017da: f043 0301 orr.w r3, r3, #1 - 80017de: 64d3 str r3, [r2, #76] @ 0x4c - 80017e0: 4b0c ldr r3, [pc, #48] @ (8001814 ) - 80017e2: 6cdb ldr r3, [r3, #76] @ 0x4c - 80017e4: f003 0301 and.w r3, r3, #1 - 80017e8: 60fb str r3, [r7, #12] - 80017ea: 68fb ldr r3, [r7, #12] + 800181c: 4b0f ldr r3, [pc, #60] @ (800185c ) + 800181e: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001820: 4a0e ldr r2, [pc, #56] @ (800185c ) + 8001822: f043 0301 orr.w r3, r3, #1 + 8001826: 64d3 str r3, [r2, #76] @ 0x4c + 8001828: 4b0c ldr r3, [pc, #48] @ (800185c ) + 800182a: 6cdb ldr r3, [r3, #76] @ 0x4c + 800182c: f003 0301 and.w r3, r3, #1 + 8001830: 60fb str r3, [r7, #12] + 8001832: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = VIN_Pin|VOUT_Pin; - 80017ec: 23c0 movs r3, #192 @ 0xc0 - 80017ee: 65fb str r3, [r7, #92] @ 0x5c + 8001834: 23c0 movs r3, #192 @ 0xc0 + 8001836: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - 80017f0: 2303 movs r3, #3 - 80017f2: 663b str r3, [r7, #96] @ 0x60 + 8001838: 2303 movs r3, #3 + 800183a: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Pull = GPIO_NOPULL; - 80017f4: 2300 movs r3, #0 - 80017f6: 667b str r3, [r7, #100] @ 0x64 + 800183c: 2300 movs r3, #0 + 800183e: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80017f8: f107 035c add.w r3, r7, #92 @ 0x5c - 80017fc: 4619 mov r1, r3 - 80017fe: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 8001802: f002 f80d bl 8003820 + 8001840: f107 035c add.w r3, r7, #92 @ 0x5c + 8001844: 4619 mov r1, r3 + 8001846: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 800184a: f002 f80d bl 8003868 } - 8001806: bf00 nop - 8001808: 3770 adds r7, #112 @ 0x70 - 800180a: 46bd mov sp, r7 - 800180c: bd80 pop {r7, pc} - 800180e: bf00 nop - 8001810: 20000260 .word 0x20000260 - 8001814: 40021000 .word 0x40021000 - 8001818: 50000100 .word 0x50000100 + 800184e: bf00 nop + 8001850: 3770 adds r7, #112 @ 0x70 + 8001852: 46bd mov sp, r7 + 8001854: bd80 pop {r7, pc} + 8001856: bf00 nop + 8001858: 20000268 .word 0x20000268 + 800185c: 40021000 .word 0x40021000 + 8001860: 50000100 .word 0x50000100 -0800181c : +08001864 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { - 800181c: b580 push {r7, lr} - 800181e: b084 sub sp, #16 - 8001820: af00 add r7, sp, #0 - 8001822: 6078 str r0, [r7, #4] + 8001864: b580 push {r7, lr} + 8001866: b084 sub sp, #16 + 8001868: af00 add r7, sp, #0 + 800186a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM2) - 8001824: 687b ldr r3, [r7, #4] - 8001826: 681b ldr r3, [r3, #0] - 8001828: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 800182c: d113 bne.n 8001856 + 800186c: 687b ldr r3, [r7, #4] + 800186e: 681b ldr r3, [r3, #0] + 8001870: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8001874: d113 bne.n 800189e { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); - 800182e: 4b0c ldr r3, [pc, #48] @ (8001860 ) - 8001830: 6d9b ldr r3, [r3, #88] @ 0x58 - 8001832: 4a0b ldr r2, [pc, #44] @ (8001860 ) - 8001834: f043 0301 orr.w r3, r3, #1 - 8001838: 6593 str r3, [r2, #88] @ 0x58 - 800183a: 4b09 ldr r3, [pc, #36] @ (8001860 ) - 800183c: 6d9b ldr r3, [r3, #88] @ 0x58 - 800183e: f003 0301 and.w r3, r3, #1 - 8001842: 60fb str r3, [r7, #12] - 8001844: 68fb ldr r3, [r7, #12] + 8001876: 4b0c ldr r3, [pc, #48] @ (80018a8 ) + 8001878: 6d9b ldr r3, [r3, #88] @ 0x58 + 800187a: 4a0b ldr r2, [pc, #44] @ (80018a8 ) + 800187c: f043 0301 orr.w r3, r3, #1 + 8001880: 6593 str r3, [r2, #88] @ 0x58 + 8001882: 4b09 ldr r3, [pc, #36] @ (80018a8 ) + 8001884: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001886: f003 0301 and.w r3, r3, #1 + 800188a: 60fb str r3, [r7, #12] + 800188c: 68fb ldr r3, [r7, #12] /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0); - 8001846: 2200 movs r2, #0 - 8001848: 2100 movs r1, #0 - 800184a: 201c movs r0, #28 - 800184c: f001 fef3 bl 8003636 + 800188e: 2200 movs r2, #0 + 8001890: 2100 movs r1, #0 + 8001892: 201c movs r0, #28 + 8001894: f001 fef3 bl 800367e HAL_NVIC_EnableIRQ(TIM2_IRQn); - 8001850: 201c movs r0, #28 - 8001852: f001 ff0a bl 800366a + 8001898: 201c movs r0, #28 + 800189a: f001 ff0a bl 80036b2 /* USER CODE END TIM2_MspInit 1 */ } } - 8001856: bf00 nop - 8001858: 3710 adds r7, #16 - 800185a: 46bd mov sp, r7 - 800185c: bd80 pop {r7, pc} - 800185e: bf00 nop - 8001860: 40021000 .word 0x40021000 + 800189e: bf00 nop + 80018a0: 3710 adds r7, #16 + 80018a2: 46bd mov sp, r7 + 80018a4: bd80 pop {r7, pc} + 80018a6: bf00 nop + 80018a8: 40021000 .word 0x40021000 -08001864 : +080018ac : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8001864: b580 push {r7, lr} - 8001866: b09a sub sp, #104 @ 0x68 - 8001868: af00 add r7, sp, #0 - 800186a: 6078 str r0, [r7, #4] + 80018ac: b580 push {r7, lr} + 80018ae: b09a sub sp, #104 @ 0x68 + 80018b0: af00 add r7, sp, #0 + 80018b2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 800186c: f107 0354 add.w r3, r7, #84 @ 0x54 - 8001870: 2200 movs r2, #0 - 8001872: 601a str r2, [r3, #0] - 8001874: 605a str r2, [r3, #4] - 8001876: 609a str r2, [r3, #8] - 8001878: 60da str r2, [r3, #12] - 800187a: 611a str r2, [r3, #16] + 80018b4: f107 0354 add.w r3, r7, #84 @ 0x54 + 80018b8: 2200 movs r2, #0 + 80018ba: 601a str r2, [r3, #0] + 80018bc: 605a str r2, [r3, #4] + 80018be: 609a str r2, [r3, #8] + 80018c0: 60da str r2, [r3, #12] + 80018c2: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 800187c: f107 0310 add.w r3, r7, #16 - 8001880: 2244 movs r2, #68 @ 0x44 - 8001882: 2100 movs r1, #0 - 8001884: 4618 mov r0, r3 - 8001886: f005 ff19 bl 80076bc + 80018c4: f107 0310 add.w r3, r7, #16 + 80018c8: 2244 movs r2, #68 @ 0x44 + 80018ca: 2100 movs r1, #0 + 80018cc: 4618 mov r0, r3 + 80018ce: f005 ff19 bl 8007704 if(huart->Instance==USART2) - 800188a: 687b ldr r3, [r7, #4] - 800188c: 681b ldr r3, [r3, #0] - 800188e: 4a23 ldr r2, [pc, #140] @ (800191c ) - 8001890: 4293 cmp r3, r2 - 8001892: d13e bne.n 8001912 + 80018d2: 687b ldr r3, [r7, #4] + 80018d4: 681b ldr r3, [r3, #0] + 80018d6: 4a23 ldr r2, [pc, #140] @ (8001964 ) + 80018d8: 4293 cmp r3, r2 + 80018da: d13e bne.n 800195a /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; - 8001894: 2302 movs r3, #2 - 8001896: 613b str r3, [r7, #16] + 80018dc: 2302 movs r3, #2 + 80018de: 613b str r3, [r7, #16] PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - 8001898: 2300 movs r3, #0 - 800189a: 61bb str r3, [r7, #24] + 80018e0: 2300 movs r3, #0 + 80018e2: 61bb str r3, [r7, #24] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 800189c: f107 0310 add.w r3, r7, #16 - 80018a0: 4618 mov r0, r3 - 80018a2: f002 ff39 bl 8004718 - 80018a6: 4603 mov r3, r0 - 80018a8: 2b00 cmp r3, #0 - 80018aa: d001 beq.n 80018b0 + 80018e4: f107 0310 add.w r3, r7, #16 + 80018e8: 4618 mov r0, r3 + 80018ea: f002 ff39 bl 8004760 + 80018ee: 4603 mov r3, r0 + 80018f0: 2b00 cmp r3, #0 + 80018f2: d001 beq.n 80018f8 { Error_Handler(); - 80018ac: f7ff ff00 bl 80016b0 + 80018f4: f7ff ff00 bl 80016f8 } /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - 80018b0: 4b1b ldr r3, [pc, #108] @ (8001920 ) - 80018b2: 6d9b ldr r3, [r3, #88] @ 0x58 - 80018b4: 4a1a ldr r2, [pc, #104] @ (8001920 ) - 80018b6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 80018ba: 6593 str r3, [r2, #88] @ 0x58 - 80018bc: 4b18 ldr r3, [pc, #96] @ (8001920 ) - 80018be: 6d9b ldr r3, [r3, #88] @ 0x58 - 80018c0: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80018c4: 60fb str r3, [r7, #12] - 80018c6: 68fb ldr r3, [r7, #12] + 80018f8: 4b1b ldr r3, [pc, #108] @ (8001968 ) + 80018fa: 6d9b ldr r3, [r3, #88] @ 0x58 + 80018fc: 4a1a ldr r2, [pc, #104] @ (8001968 ) + 80018fe: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 8001902: 6593 str r3, [r2, #88] @ 0x58 + 8001904: 4b18 ldr r3, [pc, #96] @ (8001968 ) + 8001906: 6d9b ldr r3, [r3, #88] @ 0x58 + 8001908: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 800190c: 60fb str r3, [r7, #12] + 800190e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 80018c8: 4b15 ldr r3, [pc, #84] @ (8001920 ) - 80018ca: 6cdb ldr r3, [r3, #76] @ 0x4c - 80018cc: 4a14 ldr r2, [pc, #80] @ (8001920 ) - 80018ce: f043 0301 orr.w r3, r3, #1 - 80018d2: 64d3 str r3, [r2, #76] @ 0x4c - 80018d4: 4b12 ldr r3, [pc, #72] @ (8001920 ) - 80018d6: 6cdb ldr r3, [r3, #76] @ 0x4c - 80018d8: f003 0301 and.w r3, r3, #1 - 80018dc: 60bb str r3, [r7, #8] - 80018de: 68bb ldr r3, [r7, #8] + 8001910: 4b15 ldr r3, [pc, #84] @ (8001968 ) + 8001912: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001914: 4a14 ldr r2, [pc, #80] @ (8001968 ) + 8001916: f043 0301 orr.w r3, r3, #1 + 800191a: 64d3 str r3, [r2, #76] @ 0x4c + 800191c: 4b12 ldr r3, [pc, #72] @ (8001968 ) + 800191e: 6cdb ldr r3, [r3, #76] @ 0x4c + 8001920: f003 0301 and.w r3, r3, #1 + 8001924: 60bb str r3, [r7, #8] + 8001926: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART2_TX_Pin|USART2_RX_Pin; - 80018e0: 230c movs r3, #12 - 80018e2: 657b str r3, [r7, #84] @ 0x54 + 8001928: 230c movs r3, #12 + 800192a: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80018e4: 2302 movs r3, #2 - 80018e6: 65bb str r3, [r7, #88] @ 0x58 + 800192c: 2302 movs r3, #2 + 800192e: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; - 80018e8: 2300 movs r3, #0 - 80018ea: 65fb str r3, [r7, #92] @ 0x5c + 8001930: 2300 movs r3, #0 + 8001932: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80018ec: 2300 movs r3, #0 - 80018ee: 663b str r3, [r7, #96] @ 0x60 + 8001934: 2300 movs r3, #0 + 8001936: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - 80018f0: 2307 movs r3, #7 - 80018f2: 667b str r3, [r7, #100] @ 0x64 + 8001938: 2307 movs r3, #7 + 800193a: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80018f4: f107 0354 add.w r3, r7, #84 @ 0x54 - 80018f8: 4619 mov r1, r3 - 80018fa: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 - 80018fe: f001 ff8f bl 8003820 + 800193c: f107 0354 add.w r3, r7, #84 @ 0x54 + 8001940: 4619 mov r1, r3 + 8001942: f04f 4090 mov.w r0, #1207959552 @ 0x48000000 + 8001946: f001 ff8f bl 8003868 /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); - 8001902: 2200 movs r2, #0 - 8001904: 2100 movs r1, #0 - 8001906: 2026 movs r0, #38 @ 0x26 - 8001908: f001 fe95 bl 8003636 + 800194a: 2200 movs r2, #0 + 800194c: 2100 movs r1, #0 + 800194e: 2026 movs r0, #38 @ 0x26 + 8001950: f001 fe95 bl 800367e HAL_NVIC_EnableIRQ(USART2_IRQn); - 800190c: 2026 movs r0, #38 @ 0x26 - 800190e: f001 feac bl 800366a + 8001954: 2026 movs r0, #38 @ 0x26 + 8001956: f001 feac bl 80036b2 /* USER CODE END USART2_MspInit 1 */ } } - 8001912: bf00 nop - 8001914: 3768 adds r7, #104 @ 0x68 - 8001916: 46bd mov sp, r7 - 8001918: bd80 pop {r7, pc} - 800191a: bf00 nop - 800191c: 40004400 .word 0x40004400 - 8001920: 40021000 .word 0x40021000 + 800195a: bf00 nop + 800195c: 3768 adds r7, #104 @ 0x68 + 800195e: 46bd mov sp, r7 + 8001960: bd80 pop {r7, pc} + 8001962: bf00 nop + 8001964: 40004400 .word 0x40004400 + 8001968: 40021000 .word 0x40021000 -08001924 : +0800196c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8001924: b480 push {r7} - 8001926: af00 add r7, sp, #0 + 800196c: b480 push {r7} + 800196e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8001928: bf00 nop - 800192a: e7fd b.n 8001928 + 8001970: bf00 nop + 8001972: e7fd b.n 8001970 -0800192c : +08001974 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 800192c: b480 push {r7} - 800192e: af00 add r7, sp, #0 + 8001974: b480 push {r7} + 8001976: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8001930: bf00 nop - 8001932: e7fd b.n 8001930 + 8001978: bf00 nop + 800197a: e7fd b.n 8001978 -08001934 : +0800197c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8001934: b480 push {r7} - 8001936: af00 add r7, sp, #0 + 800197c: b480 push {r7} + 800197e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8001938: bf00 nop - 800193a: e7fd b.n 8001938 + 8001980: bf00 nop + 8001982: e7fd b.n 8001980 -0800193c : +08001984 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { - 800193c: b480 push {r7} - 800193e: af00 add r7, sp, #0 + 8001984: b480 push {r7} + 8001986: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8001940: bf00 nop - 8001942: e7fd b.n 8001940 + 8001988: bf00 nop + 800198a: e7fd b.n 8001988 -08001944 : +0800198c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8001944: b480 push {r7} - 8001946: af00 add r7, sp, #0 + 800198c: b480 push {r7} + 800198e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8001948: bf00 nop - 800194a: e7fd b.n 8001948 + 8001990: bf00 nop + 8001992: e7fd b.n 8001990 -0800194c : +08001994 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 800194c: b480 push {r7} - 800194e: af00 add r7, sp, #0 + 8001994: b480 push {r7} + 8001996: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8001950: bf00 nop - 8001952: 46bd mov sp, r7 - 8001954: f85d 7b04 ldr.w r7, [sp], #4 - 8001958: 4770 bx lr + 8001998: bf00 nop + 800199a: 46bd mov sp, r7 + 800199c: f85d 7b04 ldr.w r7, [sp], #4 + 80019a0: 4770 bx lr -0800195a : +080019a2 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 800195a: b480 push {r7} - 800195c: af00 add r7, sp, #0 + 80019a2: b480 push {r7} + 80019a4: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 800195e: bf00 nop - 8001960: 46bd mov sp, r7 - 8001962: f85d 7b04 ldr.w r7, [sp], #4 - 8001966: 4770 bx lr + 80019a6: bf00 nop + 80019a8: 46bd mov sp, r7 + 80019aa: f85d 7b04 ldr.w r7, [sp], #4 + 80019ae: 4770 bx lr -08001968 : +080019b0 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8001968: b480 push {r7} - 800196a: af00 add r7, sp, #0 + 80019b0: b480 push {r7} + 80019b2: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 800196c: bf00 nop - 800196e: 46bd mov sp, r7 - 8001970: f85d 7b04 ldr.w r7, [sp], #4 - 8001974: 4770 bx lr + 80019b4: bf00 nop + 80019b6: 46bd mov sp, r7 + 80019b8: f85d 7b04 ldr.w r7, [sp], #4 + 80019bc: 4770 bx lr -08001976 : +080019be : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8001976: b580 push {r7, lr} - 8001978: af00 add r7, sp, #0 + 80019be: b580 push {r7, lr} + 80019c0: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 800197a: f000 f8a5 bl 8001ac8 + 80019c2: f000 f8a5 bl 8001b10 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 800197e: bf00 nop - 8001980: bd80 pop {r7, pc} + 80019c6: bf00 nop + 80019c8: bd80 pop {r7, pc} ... -08001984 : +080019cc : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { - 8001984: b580 push {r7, lr} - 8001986: af00 add r7, sp, #0 + 80019cc: b580 push {r7, lr} + 80019ce: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); - 8001988: 4802 ldr r0, [pc, #8] @ (8001994 ) - 800198a: f003 f90c bl 8004ba6 + 80019d0: 4802 ldr r0, [pc, #8] @ (80019dc ) + 80019d2: f003 f90c bl 8004bee /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } - 800198e: bf00 nop - 8001990: bd80 pop {r7, pc} - 8001992: bf00 nop - 8001994: 20000114 .word 0x20000114 + 80019d6: bf00 nop + 80019d8: bd80 pop {r7, pc} + 80019da: bf00 nop + 80019dc: 20000118 .word 0x20000118 -08001998 : +080019e0 : /** * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26. */ void USART2_IRQHandler(void) { - 8001998: b580 push {r7, lr} - 800199a: af00 add r7, sp, #0 + 80019e0: b580 push {r7, lr} + 80019e2: af00 add r7, sp, #0 /* USER CODE BEGIN USART2_IRQn 0 */ /* USER CODE END USART2_IRQn 0 */ HAL_UART_IRQHandler(&huart2); - 800199c: 4802 ldr r0, [pc, #8] @ (80019a8 ) - 800199e: f003 fea7 bl 80056f0 + 80019e4: 4802 ldr r0, [pc, #8] @ (80019f0 ) + 80019e6: f003 fea7 bl 8005738 /* USER CODE BEGIN USART2_IRQn 1 */ /* USER CODE END USART2_IRQn 1 */ } - 80019a2: bf00 nop - 80019a4: bd80 pop {r7, pc} - 80019a6: bf00 nop - 80019a8: 20000160 .word 0x20000160 + 80019ea: bf00 nop + 80019ec: bd80 pop {r7, pc} + 80019ee: bf00 nop + 80019f0: 20000164 .word 0x20000164 -080019ac : +080019f4 : * @param None * @retval None */ void SystemInit(void) { - 80019ac: b480 push {r7} - 80019ae: af00 add r7, sp, #0 + 80019f4: b480 push {r7} + 80019f6: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ - 80019b0: 4b06 ldr r3, [pc, #24] @ (80019cc ) - 80019b2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80019b6: 4a05 ldr r2, [pc, #20] @ (80019cc ) - 80019b8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 - 80019bc: f8c2 3088 str.w r3, [r2, #136] @ 0x88 + 80019f8: 4b06 ldr r3, [pc, #24] @ (8001a14 ) + 80019fa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80019fe: 4a05 ldr r2, [pc, #20] @ (8001a14 ) + 8001a00: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 + 8001a04: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location add offset address ------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } - 80019c0: bf00 nop - 80019c2: 46bd mov sp, r7 - 80019c4: f85d 7b04 ldr.w r7, [sp], #4 - 80019c8: 4770 bx lr - 80019ca: bf00 nop - 80019cc: e000ed00 .word 0xe000ed00 + 8001a08: bf00 nop + 8001a0a: 46bd mov sp, r7 + 8001a0c: f85d 7b04 ldr.w r7, [sp], #4 + 8001a10: 4770 bx lr + 8001a12: bf00 nop + 8001a14: e000ed00 .word 0xe000ed00 -080019d0 : +08001a18 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack - 80019d0: 480d ldr r0, [pc, #52] @ (8001a08 ) + 8001a18: 480d ldr r0, [pc, #52] @ (8001a50 ) mov sp, r0 /* set stack pointer */ - 80019d2: 4685 mov sp, r0 + 8001a1a: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit - 80019d4: f7ff ffea bl 80019ac + 8001a1c: f7ff ffea bl 80019f4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 80019d8: 480c ldr r0, [pc, #48] @ (8001a0c ) + 8001a20: 480c ldr r0, [pc, #48] @ (8001a54 ) ldr r1, =_edata - 80019da: 490d ldr r1, [pc, #52] @ (8001a10 ) + 8001a22: 490d ldr r1, [pc, #52] @ (8001a58 ) ldr r2, =_sidata - 80019dc: 4a0d ldr r2, [pc, #52] @ (8001a14 ) + 8001a24: 4a0d ldr r2, [pc, #52] @ (8001a5c ) movs r3, #0 - 80019de: 2300 movs r3, #0 + 8001a26: 2300 movs r3, #0 b LoopCopyDataInit - 80019e0: e002 b.n 80019e8 + 8001a28: e002 b.n 8001a30 -080019e2 : +08001a2a : CopyDataInit: ldr r4, [r2, r3] - 80019e2: 58d4 ldr r4, [r2, r3] + 8001a2a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 80019e4: 50c4 str r4, [r0, r3] + 8001a2c: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 80019e6: 3304 adds r3, #4 + 8001a2e: 3304 adds r3, #4 -080019e8 : +08001a30 : LoopCopyDataInit: adds r4, r0, r3 - 80019e8: 18c4 adds r4, r0, r3 + 8001a30: 18c4 adds r4, r0, r3 cmp r4, r1 - 80019ea: 428c cmp r4, r1 + 8001a32: 428c cmp r4, r1 bcc CopyDataInit - 80019ec: d3f9 bcc.n 80019e2 + 8001a34: d3f9 bcc.n 8001a2a /* Zero fill the bss segment. */ ldr r2, =_sbss - 80019ee: 4a0a ldr r2, [pc, #40] @ (8001a18 ) + 8001a36: 4a0a ldr r2, [pc, #40] @ (8001a60 ) ldr r4, =_ebss - 80019f0: 4c0a ldr r4, [pc, #40] @ (8001a1c ) + 8001a38: 4c0a ldr r4, [pc, #40] @ (8001a64 ) movs r3, #0 - 80019f2: 2300 movs r3, #0 + 8001a3a: 2300 movs r3, #0 b LoopFillZerobss - 80019f4: e001 b.n 80019fa + 8001a3c: e001 b.n 8001a42 -080019f6 : +08001a3e : FillZerobss: str r3, [r2] - 80019f6: 6013 str r3, [r2, #0] + 8001a3e: 6013 str r3, [r2, #0] adds r2, r2, #4 - 80019f8: 3204 adds r2, #4 + 8001a40: 3204 adds r2, #4 -080019fa : +08001a42 : LoopFillZerobss: cmp r2, r4 - 80019fa: 42a2 cmp r2, r4 + 8001a42: 42a2 cmp r2, r4 bcc FillZerobss - 80019fc: d3fb bcc.n 80019f6 + 8001a44: d3fb bcc.n 8001a3e /* Call static constructors */ bl __libc_init_array - 80019fe: f005 fe65 bl 80076cc <__libc_init_array> + 8001a46: f005 fe65 bl 8007714 <__libc_init_array> /* Call the application's entry point.*/ bl main - 8001a02: f7ff f8a5 bl 8000b50
+ 8001a4a: f7ff f881 bl 8000b50
-08001a06 : +08001a4e : LoopForever: b LoopForever - 8001a06: e7fe b.n 8001a06 + 8001a4e: e7fe b.n 8001a4e ldr r0, =_estack - 8001a08: 20008000 .word 0x20008000 + 8001a50: 20008000 .word 0x20008000 ldr r0, =_sdata - 8001a0c: 20000000 .word 0x20000000 + 8001a54: 20000000 .word 0x20000000 ldr r1, =_edata - 8001a10: 20000020 .word 0x20000020 + 8001a58: 20000024 .word 0x20000024 ldr r2, =_sidata - 8001a14: 0800777c .word 0x0800777c + 8001a5c: 080077c4 .word 0x080077c4 ldr r2, =_sbss - 8001a18: 20000020 .word 0x20000020 + 8001a60: 20000024 .word 0x20000024 ldr r4, =_ebss - 8001a1c: 20000268 .word 0x20000268 + 8001a64: 20000270 .word 0x20000270 -08001a20 : +08001a68 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 8001a20: e7fe b.n 8001a20 + 8001a68: e7fe b.n 8001a68 -08001a22 : +08001a6a : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8001a22: b580 push {r7, lr} - 8001a24: b082 sub sp, #8 - 8001a26: af00 add r7, sp, #0 + 8001a6a: b580 push {r7, lr} + 8001a6c: b082 sub sp, #8 + 8001a6e: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 8001a28: 2300 movs r3, #0 - 8001a2a: 71fb strb r3, [r7, #7] + 8001a70: 2300 movs r3, #0 + 8001a72: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8001a2c: 2003 movs r0, #3 - 8001a2e: f001 fdf7 bl 8003620 + 8001a74: 2003 movs r0, #3 + 8001a76: f001 fdf7 bl 8003668 /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 8001a32: 2000 movs r0, #0 - 8001a34: f000 f80e bl 8001a54 - 8001a38: 4603 mov r3, r0 - 8001a3a: 2b00 cmp r3, #0 - 8001a3c: d002 beq.n 8001a44 + 8001a7a: 2000 movs r0, #0 + 8001a7c: f000 f80e bl 8001a9c + 8001a80: 4603 mov r3, r0 + 8001a82: 2b00 cmp r3, #0 + 8001a84: d002 beq.n 8001a8c { status = HAL_ERROR; - 8001a3e: 2301 movs r3, #1 - 8001a40: 71fb strb r3, [r7, #7] - 8001a42: e001 b.n 8001a48 + 8001a86: 2301 movs r3, #1 + 8001a88: 71fb strb r3, [r7, #7] + 8001a8a: e001 b.n 8001a90 } else { /* Init the low level hardware */ HAL_MspInit(); - 8001a44: f7ff fe3a bl 80016bc + 8001a8c: f7ff fe3a bl 8001704 } /* Return function status */ return status; - 8001a48: 79fb ldrb r3, [r7, #7] + 8001a90: 79fb ldrb r3, [r7, #7] } - 8001a4a: 4618 mov r0, r3 - 8001a4c: 3708 adds r7, #8 - 8001a4e: 46bd mov sp, r7 - 8001a50: bd80 pop {r7, pc} + 8001a92: 4618 mov r0, r3 + 8001a94: 3708 adds r7, #8 + 8001a96: 46bd mov sp, r7 + 8001a98: bd80 pop {r7, pc} ... -08001a54 : +08001a9c : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8001a54: b580 push {r7, lr} - 8001a56: b084 sub sp, #16 - 8001a58: af00 add r7, sp, #0 - 8001a5a: 6078 str r0, [r7, #4] + 8001a9c: b580 push {r7, lr} + 8001a9e: b084 sub sp, #16 + 8001aa0: af00 add r7, sp, #0 + 8001aa2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8001a5c: 2300 movs r3, #0 - 8001a5e: 73fb strb r3, [r7, #15] + 8001aa4: 2300 movs r3, #0 + 8001aa6: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) - 8001a60: 4b16 ldr r3, [pc, #88] @ (8001abc ) - 8001a62: 681b ldr r3, [r3, #0] - 8001a64: 2b00 cmp r3, #0 - 8001a66: d022 beq.n 8001aae + 8001aa8: 4b16 ldr r3, [pc, #88] @ (8001b04 ) + 8001aaa: 681b ldr r3, [r3, #0] + 8001aac: 2b00 cmp r3, #0 + 8001aae: d022 beq.n 8001af6 { /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) - 8001a68: 4b15 ldr r3, [pc, #84] @ (8001ac0 ) - 8001a6a: 681a ldr r2, [r3, #0] - 8001a6c: 4b13 ldr r3, [pc, #76] @ (8001abc ) - 8001a6e: 681b ldr r3, [r3, #0] - 8001a70: f44f 717a mov.w r1, #1000 @ 0x3e8 - 8001a74: fbb1 f3f3 udiv r3, r1, r3 - 8001a78: fbb2 f3f3 udiv r3, r2, r3 - 8001a7c: 4618 mov r0, r3 - 8001a7e: f001 fe02 bl 8003686 - 8001a82: 4603 mov r3, r0 - 8001a84: 2b00 cmp r3, #0 - 8001a86: d10f bne.n 8001aa8 + 8001ab0: 4b15 ldr r3, [pc, #84] @ (8001b08 ) + 8001ab2: 681a ldr r2, [r3, #0] + 8001ab4: 4b13 ldr r3, [pc, #76] @ (8001b04 ) + 8001ab6: 681b ldr r3, [r3, #0] + 8001ab8: f44f 717a mov.w r1, #1000 @ 0x3e8 + 8001abc: fbb1 f3f3 udiv r3, r1, r3 + 8001ac0: fbb2 f3f3 udiv r3, r2, r3 + 8001ac4: 4618 mov r0, r3 + 8001ac6: f001 fe02 bl 80036ce + 8001aca: 4603 mov r3, r0 + 8001acc: 2b00 cmp r3, #0 + 8001ace: d10f bne.n 8001af0 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 8001a88: 687b ldr r3, [r7, #4] - 8001a8a: 2b0f cmp r3, #15 - 8001a8c: d809 bhi.n 8001aa2 + 8001ad0: 687b ldr r3, [r7, #4] + 8001ad2: 2b0f cmp r3, #15 + 8001ad4: d809 bhi.n 8001aea { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8001a8e: 2200 movs r2, #0 - 8001a90: 6879 ldr r1, [r7, #4] - 8001a92: f04f 30ff mov.w r0, #4294967295 - 8001a96: f001 fdce bl 8003636 + 8001ad6: 2200 movs r2, #0 + 8001ad8: 6879 ldr r1, [r7, #4] + 8001ada: f04f 30ff mov.w r0, #4294967295 + 8001ade: f001 fdce bl 800367e uwTickPrio = TickPriority; - 8001a9a: 4a0a ldr r2, [pc, #40] @ (8001ac4 ) - 8001a9c: 687b ldr r3, [r7, #4] - 8001a9e: 6013 str r3, [r2, #0] - 8001aa0: e007 b.n 8001ab2 + 8001ae2: 4a0a ldr r2, [pc, #40] @ (8001b0c ) + 8001ae4: 687b ldr r3, [r7, #4] + 8001ae6: 6013 str r3, [r2, #0] + 8001ae8: e007 b.n 8001afa } else { status = HAL_ERROR; - 8001aa2: 2301 movs r3, #1 - 8001aa4: 73fb strb r3, [r7, #15] - 8001aa6: e004 b.n 8001ab2 + 8001aea: 2301 movs r3, #1 + 8001aec: 73fb strb r3, [r7, #15] + 8001aee: e004 b.n 8001afa } } else { status = HAL_ERROR; - 8001aa8: 2301 movs r3, #1 - 8001aaa: 73fb strb r3, [r7, #15] - 8001aac: e001 b.n 8001ab2 + 8001af0: 2301 movs r3, #1 + 8001af2: 73fb strb r3, [r7, #15] + 8001af4: e001 b.n 8001afa } } else { status = HAL_ERROR; - 8001aae: 2301 movs r3, #1 - 8001ab0: 73fb strb r3, [r7, #15] + 8001af6: 2301 movs r3, #1 + 8001af8: 73fb strb r3, [r7, #15] } /* Return function status */ return status; - 8001ab2: 7bfb ldrb r3, [r7, #15] + 8001afa: 7bfb ldrb r3, [r7, #15] } - 8001ab4: 4618 mov r0, r3 - 8001ab6: 3710 adds r7, #16 - 8001ab8: 46bd mov sp, r7 - 8001aba: bd80 pop {r7, pc} - 8001abc: 2000001c .word 0x2000001c - 8001ac0: 20000014 .word 0x20000014 - 8001ac4: 20000018 .word 0x20000018 + 8001afc: 4618 mov r0, r3 + 8001afe: 3710 adds r7, #16 + 8001b00: 46bd mov sp, r7 + 8001b02: bd80 pop {r7, pc} + 8001b04: 20000020 .word 0x20000020 + 8001b08: 20000018 .word 0x20000018 + 8001b0c: 2000001c .word 0x2000001c -08001ac8 : +08001b10 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8001ac8: b480 push {r7} - 8001aca: af00 add r7, sp, #0 + 8001b10: b480 push {r7} + 8001b12: af00 add r7, sp, #0 uwTick += uwTickFreq; - 8001acc: 4b05 ldr r3, [pc, #20] @ (8001ae4 ) - 8001ace: 681a ldr r2, [r3, #0] - 8001ad0: 4b05 ldr r3, [pc, #20] @ (8001ae8 ) - 8001ad2: 681b ldr r3, [r3, #0] - 8001ad4: 4413 add r3, r2 - 8001ad6: 4a03 ldr r2, [pc, #12] @ (8001ae4 ) - 8001ad8: 6013 str r3, [r2, #0] + 8001b14: 4b05 ldr r3, [pc, #20] @ (8001b2c ) + 8001b16: 681a ldr r2, [r3, #0] + 8001b18: 4b05 ldr r3, [pc, #20] @ (8001b30 ) + 8001b1a: 681b ldr r3, [r3, #0] + 8001b1c: 4413 add r3, r2 + 8001b1e: 4a03 ldr r2, [pc, #12] @ (8001b2c ) + 8001b20: 6013 str r3, [r2, #0] } - 8001ada: bf00 nop - 8001adc: 46bd mov sp, r7 - 8001ade: f85d 7b04 ldr.w r7, [sp], #4 - 8001ae2: 4770 bx lr - 8001ae4: 20000264 .word 0x20000264 - 8001ae8: 2000001c .word 0x2000001c + 8001b22: bf00 nop + 8001b24: 46bd mov sp, r7 + 8001b26: f85d 7b04 ldr.w r7, [sp], #4 + 8001b2a: 4770 bx lr + 8001b2c: 2000026c .word 0x2000026c + 8001b30: 20000020 .word 0x20000020 -08001aec : +08001b34 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8001aec: b480 push {r7} - 8001aee: af00 add r7, sp, #0 + 8001b34: b480 push {r7} + 8001b36: af00 add r7, sp, #0 return uwTick; - 8001af0: 4b03 ldr r3, [pc, #12] @ (8001b00 ) - 8001af2: 681b ldr r3, [r3, #0] + 8001b38: 4b03 ldr r3, [pc, #12] @ (8001b48 ) + 8001b3a: 681b ldr r3, [r3, #0] } - 8001af4: 4618 mov r0, r3 - 8001af6: 46bd mov sp, r7 - 8001af8: f85d 7b04 ldr.w r7, [sp], #4 - 8001afc: 4770 bx lr - 8001afe: bf00 nop - 8001b00: 20000264 .word 0x20000264 + 8001b3c: 4618 mov r0, r3 + 8001b3e: 46bd mov sp, r7 + 8001b40: f85d 7b04 ldr.w r7, [sp], #4 + 8001b44: 4770 bx lr + 8001b46: bf00 nop + 8001b48: 2000026c .word 0x2000026c -08001b04 : +08001b4c : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { - 8001b04: b480 push {r7} - 8001b06: b083 sub sp, #12 - 8001b08: af00 add r7, sp, #0 - 8001b0a: 6078 str r0, [r7, #4] - 8001b0c: 6039 str r1, [r7, #0] + 8001b4c: b480 push {r7} + 8001b4e: b083 sub sp, #12 + 8001b50: af00 add r7, sp, #0 + 8001b52: 6078 str r0, [r7, #4] + 8001b54: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); - 8001b0e: 687b ldr r3, [r7, #4] - 8001b10: 689b ldr r3, [r3, #8] - 8001b12: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 - 8001b16: 683b ldr r3, [r7, #0] - 8001b18: 431a orrs r2, r3 - 8001b1a: 687b ldr r3, [r7, #4] - 8001b1c: 609a str r2, [r3, #8] + 8001b56: 687b ldr r3, [r7, #4] + 8001b58: 689b ldr r3, [r3, #8] + 8001b5a: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 + 8001b5e: 683b ldr r3, [r7, #0] + 8001b60: 431a orrs r2, r3 + 8001b62: 687b ldr r3, [r7, #4] + 8001b64: 609a str r2, [r3, #8] } - 8001b1e: bf00 nop - 8001b20: 370c adds r7, #12 - 8001b22: 46bd mov sp, r7 - 8001b24: f85d 7b04 ldr.w r7, [sp], #4 - 8001b28: 4770 bx lr + 8001b66: bf00 nop + 8001b68: 370c adds r7, #12 + 8001b6a: 46bd mov sp, r7 + 8001b6c: f85d 7b04 ldr.w r7, [sp], #4 + 8001b70: 4770 bx lr -08001b2a : +08001b72 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { - 8001b2a: b480 push {r7} - 8001b2c: b083 sub sp, #12 - 8001b2e: af00 add r7, sp, #0 - 8001b30: 6078 str r0, [r7, #4] - 8001b32: 6039 str r1, [r7, #0] + 8001b72: b480 push {r7} + 8001b74: b083 sub sp, #12 + 8001b76: af00 add r7, sp, #0 + 8001b78: 6078 str r0, [r7, #4] + 8001b7a: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal); - 8001b34: 687b ldr r3, [r7, #4] - 8001b36: 689b ldr r3, [r3, #8] - 8001b38: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 - 8001b3c: 683b ldr r3, [r7, #0] - 8001b3e: 431a orrs r2, r3 - 8001b40: 687b ldr r3, [r7, #4] - 8001b42: 609a str r2, [r3, #8] + 8001b7c: 687b ldr r3, [r7, #4] + 8001b7e: 689b ldr r3, [r3, #8] + 8001b80: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 + 8001b84: 683b ldr r3, [r7, #0] + 8001b86: 431a orrs r2, r3 + 8001b88: 687b ldr r3, [r7, #4] + 8001b8a: 609a str r2, [r3, #8] } - 8001b44: bf00 nop - 8001b46: 370c adds r7, #12 - 8001b48: 46bd mov sp, r7 - 8001b4a: f85d 7b04 ldr.w r7, [sp], #4 - 8001b4e: 4770 bx lr + 8001b8c: bf00 nop + 8001b8e: 370c adds r7, #12 + 8001b90: 46bd mov sp, r7 + 8001b92: f85d 7b04 ldr.w r7, [sp], #4 + 8001b96: 4770 bx lr -08001b50 : +08001b98 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { - 8001b50: b480 push {r7} - 8001b52: b083 sub sp, #12 - 8001b54: af00 add r7, sp, #0 - 8001b56: 6078 str r0, [r7, #4] + 8001b98: b480 push {r7} + 8001b9a: b083 sub sp, #12 + 8001b9c: af00 add r7, sp, #0 + 8001b9e: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL)); - 8001b58: 687b ldr r3, [r7, #4] - 8001b5a: 689b ldr r3, [r3, #8] - 8001b5c: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 + 8001ba0: 687b ldr r3, [r7, #4] + 8001ba2: 689b ldr r3, [r3, #8] + 8001ba4: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } - 8001b60: 4618 mov r0, r3 - 8001b62: 370c adds r7, #12 - 8001b64: 46bd mov sp, r7 - 8001b66: f85d 7b04 ldr.w r7, [sp], #4 - 8001b6a: 4770 bx lr + 8001ba8: 4618 mov r0, r3 + 8001baa: 370c adds r7, #12 + 8001bac: 46bd mov sp, r7 + 8001bae: f85d 7b04 ldr.w r7, [sp], #4 + 8001bb2: 4770 bx lr -08001b6c : +08001bb4 : * (fADC) to convert in 12-bit resolution.\n * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { - 8001b6c: b480 push {r7} - 8001b6e: b087 sub sp, #28 - 8001b70: af00 add r7, sp, #0 - 8001b72: 60f8 str r0, [r7, #12] - 8001b74: 60b9 str r1, [r7, #8] - 8001b76: 607a str r2, [r7, #4] - 8001b78: 603b str r3, [r7, #0] + 8001bb4: b480 push {r7} + 8001bb6: b087 sub sp, #28 + 8001bb8: af00 add r7, sp, #0 + 8001bba: 60f8 str r0, [r7, #12] + 8001bbc: 60b9 str r1, [r7, #8] + 8001bbe: 607a str r2, [r7, #4] + 8001bc0: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8001b7a: 68fb ldr r3, [r7, #12] - 8001b7c: 3360 adds r3, #96 @ 0x60 - 8001b7e: 461a mov r2, r3 - 8001b80: 68bb ldr r3, [r7, #8] - 8001b82: 009b lsls r3, r3, #2 - 8001b84: 4413 add r3, r2 - 8001b86: 617b str r3, [r7, #20] + 8001bc2: 68fb ldr r3, [r7, #12] + 8001bc4: 3360 adds r3, #96 @ 0x60 + 8001bc6: 461a mov r2, r3 + 8001bc8: 68bb ldr r3, [r7, #8] + 8001bca: 009b lsls r3, r3, #2 + 8001bcc: 4413 add r3, r2 + 8001bce: 617b str r3, [r7, #20] MODIFY_REG(*preg, - 8001b88: 697b ldr r3, [r7, #20] - 8001b8a: 681a ldr r2, [r3, #0] - 8001b8c: 4b08 ldr r3, [pc, #32] @ (8001bb0 ) - 8001b8e: 4013 ands r3, r2 - 8001b90: 687a ldr r2, [r7, #4] - 8001b92: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000 - 8001b96: 683a ldr r2, [r7, #0] - 8001b98: 430a orrs r2, r1 - 8001b9a: 4313 orrs r3, r2 - 8001b9c: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 - 8001ba0: 697b ldr r3, [r7, #20] - 8001ba2: 601a str r2, [r3, #0] + 8001bd0: 697b ldr r3, [r7, #20] + 8001bd2: 681a ldr r2, [r3, #0] + 8001bd4: 4b08 ldr r3, [pc, #32] @ (8001bf8 ) + 8001bd6: 4013 ands r3, r2 + 8001bd8: 687a ldr r2, [r7, #4] + 8001bda: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000 + 8001bde: 683a ldr r2, [r7, #0] + 8001be0: 430a orrs r2, r1 + 8001be2: 4313 orrs r3, r2 + 8001be4: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 + 8001be8: 697b ldr r3, [r7, #20] + 8001bea: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } - 8001ba4: bf00 nop - 8001ba6: 371c adds r7, #28 - 8001ba8: 46bd mov sp, r7 - 8001baa: f85d 7b04 ldr.w r7, [sp], #4 - 8001bae: 4770 bx lr - 8001bb0: 03fff000 .word 0x03fff000 + 8001bec: bf00 nop + 8001bee: 371c adds r7, #28 + 8001bf0: 46bd mov sp, r7 + 8001bf2: f85d 7b04 ldr.w r7, [sp], #4 + 8001bf6: 4770 bx lr + 8001bf8: 03fff000 .word 0x03fff000 -08001bb4 : +08001bfc : * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register, * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { - 8001bb4: b480 push {r7} - 8001bb6: b085 sub sp, #20 - 8001bb8: af00 add r7, sp, #0 - 8001bba: 6078 str r0, [r7, #4] - 8001bbc: 6039 str r1, [r7, #0] + 8001bfc: b480 push {r7} + 8001bfe: b085 sub sp, #20 + 8001c00: af00 add r7, sp, #0 + 8001c02: 6078 str r0, [r7, #4] + 8001c04: 6039 str r1, [r7, #0] const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8001bbe: 687b ldr r3, [r7, #4] - 8001bc0: 3360 adds r3, #96 @ 0x60 - 8001bc2: 461a mov r2, r3 - 8001bc4: 683b ldr r3, [r7, #0] - 8001bc6: 009b lsls r3, r3, #2 - 8001bc8: 4413 add r3, r2 - 8001bca: 60fb str r3, [r7, #12] + 8001c06: 687b ldr r3, [r7, #4] + 8001c08: 3360 adds r3, #96 @ 0x60 + 8001c0a: 461a mov r2, r3 + 8001c0c: 683b ldr r3, [r7, #0] + 8001c0e: 009b lsls r3, r3, #2 + 8001c10: 4413 add r3, r2 + 8001c12: 60fb str r3, [r7, #12] return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); - 8001bcc: 68fb ldr r3, [r7, #12] - 8001bce: 681b ldr r3, [r3, #0] - 8001bd0: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 + 8001c14: 68fb ldr r3, [r7, #12] + 8001c16: 681b ldr r3, [r3, #0] + 8001c18: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000 } - 8001bd4: 4618 mov r0, r3 - 8001bd6: 3714 adds r7, #20 - 8001bd8: 46bd mov sp, r7 - 8001bda: f85d 7b04 ldr.w r7, [sp], #4 - 8001bde: 4770 bx lr + 8001c1c: 4618 mov r0, r3 + 8001c1e: 3714 adds r7, #20 + 8001c20: 46bd mov sp, r7 + 8001c22: f85d 7b04 ldr.w r7, [sp], #4 + 8001c26: 4770 bx lr -08001be0 : +08001c28 : * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState) { - 8001be0: b480 push {r7} - 8001be2: b087 sub sp, #28 - 8001be4: af00 add r7, sp, #0 - 8001be6: 60f8 str r0, [r7, #12] - 8001be8: 60b9 str r1, [r7, #8] - 8001bea: 607a str r2, [r7, #4] + 8001c28: b480 push {r7} + 8001c2a: b087 sub sp, #28 + 8001c2c: af00 add r7, sp, #0 + 8001c2e: 60f8 str r0, [r7, #12] + 8001c30: 60b9 str r1, [r7, #8] + 8001c32: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8001bec: 68fb ldr r3, [r7, #12] - 8001bee: 3360 adds r3, #96 @ 0x60 - 8001bf0: 461a mov r2, r3 - 8001bf2: 68bb ldr r3, [r7, #8] - 8001bf4: 009b lsls r3, r3, #2 - 8001bf6: 4413 add r3, r2 - 8001bf8: 617b str r3, [r7, #20] + 8001c34: 68fb ldr r3, [r7, #12] + 8001c36: 3360 adds r3, #96 @ 0x60 + 8001c38: 461a mov r2, r3 + 8001c3a: 68bb ldr r3, [r7, #8] + 8001c3c: 009b lsls r3, r3, #2 + 8001c3e: 4413 add r3, r2 + 8001c40: 617b str r3, [r7, #20] MODIFY_REG(*preg, - 8001bfa: 697b ldr r3, [r7, #20] - 8001bfc: 681b ldr r3, [r3, #0] - 8001bfe: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 - 8001c02: 687b ldr r3, [r7, #4] - 8001c04: 431a orrs r2, r3 - 8001c06: 697b ldr r3, [r7, #20] - 8001c08: 601a str r2, [r3, #0] + 8001c42: 697b ldr r3, [r7, #20] + 8001c44: 681b ldr r3, [r3, #0] + 8001c46: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 + 8001c4a: 687b ldr r3, [r7, #4] + 8001c4c: 431a orrs r2, r3 + 8001c4e: 697b ldr r3, [r7, #20] + 8001c50: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_EN, OffsetState); } - 8001c0a: bf00 nop - 8001c0c: 371c adds r7, #28 - 8001c0e: 46bd mov sp, r7 - 8001c10: f85d 7b04 ldr.w r7, [sp], #4 - 8001c14: 4770 bx lr + 8001c52: bf00 nop + 8001c54: 371c adds r7, #28 + 8001c56: 46bd mov sp, r7 + 8001c58: f85d 7b04 ldr.w r7, [sp], #4 + 8001c5c: 4770 bx lr -08001c16 : +08001c5e : * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign) { - 8001c16: b480 push {r7} - 8001c18: b087 sub sp, #28 - 8001c1a: af00 add r7, sp, #0 - 8001c1c: 60f8 str r0, [r7, #12] - 8001c1e: 60b9 str r1, [r7, #8] - 8001c20: 607a str r2, [r7, #4] + 8001c5e: b480 push {r7} + 8001c60: b087 sub sp, #28 + 8001c62: af00 add r7, sp, #0 + 8001c64: 60f8 str r0, [r7, #12] + 8001c66: 60b9 str r1, [r7, #8] + 8001c68: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8001c22: 68fb ldr r3, [r7, #12] - 8001c24: 3360 adds r3, #96 @ 0x60 - 8001c26: 461a mov r2, r3 - 8001c28: 68bb ldr r3, [r7, #8] - 8001c2a: 009b lsls r3, r3, #2 - 8001c2c: 4413 add r3, r2 - 8001c2e: 617b str r3, [r7, #20] + 8001c6a: 68fb ldr r3, [r7, #12] + 8001c6c: 3360 adds r3, #96 @ 0x60 + 8001c6e: 461a mov r2, r3 + 8001c70: 68bb ldr r3, [r7, #8] + 8001c72: 009b lsls r3, r3, #2 + 8001c74: 4413 add r3, r2 + 8001c76: 617b str r3, [r7, #20] MODIFY_REG(*preg, - 8001c30: 697b ldr r3, [r7, #20] - 8001c32: 681b ldr r3, [r3, #0] - 8001c34: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 - 8001c38: 687b ldr r3, [r7, #4] - 8001c3a: 431a orrs r2, r3 - 8001c3c: 697b ldr r3, [r7, #20] - 8001c3e: 601a str r2, [r3, #0] + 8001c78: 697b ldr r3, [r7, #20] + 8001c7a: 681b ldr r3, [r3, #0] + 8001c7c: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 + 8001c80: 687b ldr r3, [r7, #4] + 8001c82: 431a orrs r2, r3 + 8001c84: 697b ldr r3, [r7, #20] + 8001c86: 601a str r2, [r3, #0] ADC_OFR1_OFFSETPOS, OffsetSign); } - 8001c40: bf00 nop - 8001c42: 371c adds r7, #28 - 8001c44: 46bd mov sp, r7 - 8001c46: f85d 7b04 ldr.w r7, [sp], #4 - 8001c4a: 4770 bx lr + 8001c88: bf00 nop + 8001c8a: 371c adds r7, #28 + 8001c8c: 46bd mov sp, r7 + 8001c8e: f85d 7b04 ldr.w r7, [sp], #4 + 8001c92: 4770 bx lr -08001c4c : +08001c94 : * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE * @retval None */ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation) { - 8001c4c: b480 push {r7} - 8001c4e: b087 sub sp, #28 - 8001c50: af00 add r7, sp, #0 - 8001c52: 60f8 str r0, [r7, #12] - 8001c54: 60b9 str r1, [r7, #8] - 8001c56: 607a str r2, [r7, #4] + 8001c94: b480 push {r7} + 8001c96: b087 sub sp, #28 + 8001c98: af00 add r7, sp, #0 + 8001c9a: 60f8 str r0, [r7, #12] + 8001c9c: 60b9 str r1, [r7, #8] + 8001c9e: 607a str r2, [r7, #4] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - 8001c58: 68fb ldr r3, [r7, #12] - 8001c5a: 3360 adds r3, #96 @ 0x60 - 8001c5c: 461a mov r2, r3 - 8001c5e: 68bb ldr r3, [r7, #8] - 8001c60: 009b lsls r3, r3, #2 - 8001c62: 4413 add r3, r2 - 8001c64: 617b str r3, [r7, #20] + 8001ca0: 68fb ldr r3, [r7, #12] + 8001ca2: 3360 adds r3, #96 @ 0x60 + 8001ca4: 461a mov r2, r3 + 8001ca6: 68bb ldr r3, [r7, #8] + 8001ca8: 009b lsls r3, r3, #2 + 8001caa: 4413 add r3, r2 + 8001cac: 617b str r3, [r7, #20] MODIFY_REG(*preg, - 8001c66: 697b ldr r3, [r7, #20] - 8001c68: 681b ldr r3, [r3, #0] - 8001c6a: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 - 8001c6e: 687b ldr r3, [r7, #4] - 8001c70: 431a orrs r2, r3 - 8001c72: 697b ldr r3, [r7, #20] - 8001c74: 601a str r2, [r3, #0] + 8001cae: 697b ldr r3, [r7, #20] + 8001cb0: 681b ldr r3, [r3, #0] + 8001cb2: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 + 8001cb6: 687b ldr r3, [r7, #4] + 8001cb8: 431a orrs r2, r3 + 8001cba: 697b ldr r3, [r7, #20] + 8001cbc: 601a str r2, [r3, #0] ADC_OFR1_SATEN, OffsetSaturation); } - 8001c76: bf00 nop - 8001c78: 371c adds r7, #28 - 8001c7a: 46bd mov sp, r7 - 8001c7c: f85d 7b04 ldr.w r7, [sp], #4 - 8001c80: 4770 bx lr + 8001cbe: bf00 nop + 8001cc0: 371c adds r7, #28 + 8001cc2: 46bd mov sp, r7 + 8001cc4: f85d 7b04 ldr.w r7, [sp], #4 + 8001cc8: 4770 bx lr -08001c82 : +08001cca : * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 * @retval None */ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig) { - 8001c82: b480 push {r7} - 8001c84: b083 sub sp, #12 - 8001c86: af00 add r7, sp, #0 - 8001c88: 6078 str r0, [r7, #4] - 8001c8a: 6039 str r1, [r7, #0] + 8001cca: b480 push {r7} + 8001ccc: b083 sub sp, #12 + 8001cce: af00 add r7, sp, #0 + 8001cd0: 6078 str r0, [r7, #4] + 8001cd2: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig); - 8001c8c: 687b ldr r3, [r7, #4] - 8001c8e: 695b ldr r3, [r3, #20] - 8001c90: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 - 8001c94: 683b ldr r3, [r7, #0] - 8001c96: 431a orrs r2, r3 - 8001c98: 687b ldr r3, [r7, #4] - 8001c9a: 615a str r2, [r3, #20] + 8001cd4: 687b ldr r3, [r7, #4] + 8001cd6: 695b ldr r3, [r3, #20] + 8001cd8: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 + 8001cdc: 683b ldr r3, [r7, #0] + 8001cde: 431a orrs r2, r3 + 8001ce0: 687b ldr r3, [r7, #4] + 8001ce2: 615a str r2, [r3, #20] } - 8001c9c: bf00 nop - 8001c9e: 370c adds r7, #12 - 8001ca0: 46bd mov sp, r7 - 8001ca2: f85d 7b04 ldr.w r7, [sp], #4 - 8001ca6: 4770 bx lr + 8001ce4: bf00 nop + 8001ce6: 370c adds r7, #12 + 8001ce8: 46bd mov sp, r7 + 8001cea: f85d 7b04 ldr.w r7, [sp], #4 + 8001cee: 4770 bx lr -08001ca8 : +08001cf0 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { - 8001ca8: b480 push {r7} - 8001caa: b083 sub sp, #12 - 8001cac: af00 add r7, sp, #0 - 8001cae: 6078 str r0, [r7, #4] + 8001cf0: b480 push {r7} + 8001cf2: b083 sub sp, #12 + 8001cf4: af00 add r7, sp, #0 + 8001cf6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); - 8001cb0: 687b ldr r3, [r7, #4] - 8001cb2: 68db ldr r3, [r3, #12] - 8001cb4: f403 6340 and.w r3, r3, #3072 @ 0xc00 - 8001cb8: 2b00 cmp r3, #0 - 8001cba: d101 bne.n 8001cc0 - 8001cbc: 2301 movs r3, #1 - 8001cbe: e000 b.n 8001cc2 - 8001cc0: 2300 movs r3, #0 + 8001cf8: 687b ldr r3, [r7, #4] + 8001cfa: 68db ldr r3, [r3, #12] + 8001cfc: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 8001d00: 2b00 cmp r3, #0 + 8001d02: d101 bne.n 8001d08 + 8001d04: 2301 movs r3, #1 + 8001d06: e000 b.n 8001d0a + 8001d08: 2300 movs r3, #0 } - 8001cc2: 4618 mov r0, r3 - 8001cc4: 370c adds r7, #12 - 8001cc6: 46bd mov sp, r7 - 8001cc8: f85d 7b04 ldr.w r7, [sp], #4 - 8001ccc: 4770 bx lr + 8001d0a: 4618 mov r0, r3 + 8001d0c: 370c adds r7, #12 + 8001d0e: 46bd mov sp, r7 + 8001d10: f85d 7b04 ldr.w r7, [sp], #4 + 8001d14: 4770 bx lr -08001cce : +08001d16 : * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles * (fADC) to convert in 12-bit resolution.\n * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { - 8001cce: b480 push {r7} - 8001cd0: b087 sub sp, #28 - 8001cd2: af00 add r7, sp, #0 - 8001cd4: 60f8 str r0, [r7, #12] - 8001cd6: 60b9 str r1, [r7, #8] - 8001cd8: 607a str r2, [r7, #4] + 8001d16: b480 push {r7} + 8001d18: b087 sub sp, #28 + 8001d1a: af00 add r7, sp, #0 + 8001d1c: 60f8 str r0, [r7, #12] + 8001d1e: 60b9 str r1, [r7, #8] + 8001d20: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, - 8001cda: 68fb ldr r3, [r7, #12] - 8001cdc: 3330 adds r3, #48 @ 0x30 - 8001cde: 461a mov r2, r3 - 8001ce0: 68bb ldr r3, [r7, #8] - 8001ce2: 0a1b lsrs r3, r3, #8 - 8001ce4: 009b lsls r3, r3, #2 - 8001ce6: f003 030c and.w r3, r3, #12 - 8001cea: 4413 add r3, r2 - 8001cec: 617b str r3, [r7, #20] + 8001d22: 68fb ldr r3, [r7, #12] + 8001d24: 3330 adds r3, #48 @ 0x30 + 8001d26: 461a mov r2, r3 + 8001d28: 68bb ldr r3, [r7, #8] + 8001d2a: 0a1b lsrs r3, r3, #8 + 8001d2c: 009b lsls r3, r3, #2 + 8001d2e: f003 030c and.w r3, r3, #12 + 8001d32: 4413 add r3, r2 + 8001d34: 617b str r3, [r7, #20] ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); MODIFY_REG(*preg, - 8001cee: 697b ldr r3, [r7, #20] - 8001cf0: 681a ldr r2, [r3, #0] - 8001cf2: 68bb ldr r3, [r7, #8] - 8001cf4: f003 031f and.w r3, r3, #31 - 8001cf8: 211f movs r1, #31 - 8001cfa: fa01 f303 lsl.w r3, r1, r3 - 8001cfe: 43db mvns r3, r3 - 8001d00: 401a ands r2, r3 - 8001d02: 687b ldr r3, [r7, #4] - 8001d04: 0e9b lsrs r3, r3, #26 - 8001d06: f003 011f and.w r1, r3, #31 - 8001d0a: 68bb ldr r3, [r7, #8] - 8001d0c: f003 031f and.w r3, r3, #31 - 8001d10: fa01 f303 lsl.w r3, r1, r3 - 8001d14: 431a orrs r2, r3 - 8001d16: 697b ldr r3, [r7, #20] - 8001d18: 601a str r2, [r3, #0] + 8001d36: 697b ldr r3, [r7, #20] + 8001d38: 681a ldr r2, [r3, #0] + 8001d3a: 68bb ldr r3, [r7, #8] + 8001d3c: f003 031f and.w r3, r3, #31 + 8001d40: 211f movs r1, #31 + 8001d42: fa01 f303 lsl.w r3, r1, r3 + 8001d46: 43db mvns r3, r3 + 8001d48: 401a ands r2, r3 + 8001d4a: 687b ldr r3, [r7, #4] + 8001d4c: 0e9b lsrs r3, r3, #26 + 8001d4e: f003 011f and.w r1, r3, #31 + 8001d52: 68bb ldr r3, [r7, #8] + 8001d54: f003 031f and.w r3, r3, #31 + 8001d58: fa01 f303 lsl.w r3, r1, r3 + 8001d5c: 431a orrs r2, r3 + 8001d5e: 697b ldr r3, [r7, #20] + 8001d60: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } - 8001d1a: bf00 nop - 8001d1c: 371c adds r7, #28 - 8001d1e: 46bd mov sp, r7 - 8001d20: f85d 7b04 ldr.w r7, [sp], #4 - 8001d24: 4770 bx lr + 8001d62: bf00 nop + 8001d64: 371c adds r7, #28 + 8001d66: 46bd mov sp, r7 + 8001d68: f85d 7b04 ldr.w r7, [sp], #4 + 8001d6c: 4770 bx lr -08001d26 : +08001d6e : * can be replaced by 3.5 ADC clock cycles. * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig(). * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { - 8001d26: b480 push {r7} - 8001d28: b087 sub sp, #28 - 8001d2a: af00 add r7, sp, #0 - 8001d2c: 60f8 str r0, [r7, #12] - 8001d2e: 60b9 str r1, [r7, #8] - 8001d30: 607a str r2, [r7, #4] + 8001d6e: b480 push {r7} + 8001d70: b087 sub sp, #28 + 8001d72: af00 add r7, sp, #0 + 8001d74: 60f8 str r0, [r7, #12] + 8001d76: 60b9 str r1, [r7, #8] + 8001d78: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, - 8001d32: 68fb ldr r3, [r7, #12] - 8001d34: 3314 adds r3, #20 - 8001d36: 461a mov r2, r3 - 8001d38: 68bb ldr r3, [r7, #8] - 8001d3a: 0e5b lsrs r3, r3, #25 - 8001d3c: 009b lsls r3, r3, #2 - 8001d3e: f003 0304 and.w r3, r3, #4 - 8001d42: 4413 add r3, r2 - 8001d44: 617b str r3, [r7, #20] + 8001d7a: 68fb ldr r3, [r7, #12] + 8001d7c: 3314 adds r3, #20 + 8001d7e: 461a mov r2, r3 + 8001d80: 68bb ldr r3, [r7, #8] + 8001d82: 0e5b lsrs r3, r3, #25 + 8001d84: 009b lsls r3, r3, #2 + 8001d86: f003 0304 and.w r3, r3, #4 + 8001d8a: 4413 add r3, r2 + 8001d8c: 617b str r3, [r7, #20] ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); MODIFY_REG(*preg, - 8001d46: 697b ldr r3, [r7, #20] - 8001d48: 681a ldr r2, [r3, #0] - 8001d4a: 68bb ldr r3, [r7, #8] - 8001d4c: 0d1b lsrs r3, r3, #20 - 8001d4e: f003 031f and.w r3, r3, #31 - 8001d52: 2107 movs r1, #7 - 8001d54: fa01 f303 lsl.w r3, r1, r3 - 8001d58: 43db mvns r3, r3 - 8001d5a: 401a ands r2, r3 - 8001d5c: 68bb ldr r3, [r7, #8] - 8001d5e: 0d1b lsrs r3, r3, #20 - 8001d60: f003 031f and.w r3, r3, #31 - 8001d64: 6879 ldr r1, [r7, #4] - 8001d66: fa01 f303 lsl.w r3, r1, r3 - 8001d6a: 431a orrs r2, r3 - 8001d6c: 697b ldr r3, [r7, #20] - 8001d6e: 601a str r2, [r3, #0] + 8001d8e: 697b ldr r3, [r7, #20] + 8001d90: 681a ldr r2, [r3, #0] + 8001d92: 68bb ldr r3, [r7, #8] + 8001d94: 0d1b lsrs r3, r3, #20 + 8001d96: f003 031f and.w r3, r3, #31 + 8001d9a: 2107 movs r1, #7 + 8001d9c: fa01 f303 lsl.w r3, r1, r3 + 8001da0: 43db mvns r3, r3 + 8001da2: 401a ands r2, r3 + 8001da4: 68bb ldr r3, [r7, #8] + 8001da6: 0d1b lsrs r3, r3, #20 + 8001da8: f003 031f and.w r3, r3, #31 + 8001dac: 6879 ldr r1, [r7, #4] + 8001dae: fa01 f303 lsl.w r3, r1, r3 + 8001db2: 431a orrs r2, r3 + 8001db4: 697b ldr r3, [r7, #20] + 8001db6: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } - 8001d70: bf00 nop - 8001d72: 371c adds r7, #28 - 8001d74: 46bd mov sp, r7 - 8001d76: f85d 7b04 ldr.w r7, [sp], #4 - 8001d7a: 4770 bx lr + 8001db8: bf00 nop + 8001dba: 371c adds r7, #28 + 8001dbc: 46bd mov sp, r7 + 8001dbe: f85d 7b04 ldr.w r7, [sp], #4 + 8001dc2: 4770 bx lr -08001d7c : +08001dc4 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { - 8001d7c: b480 push {r7} - 8001d7e: b085 sub sp, #20 - 8001d80: af00 add r7, sp, #0 - 8001d82: 60f8 str r0, [r7, #12] - 8001d84: 60b9 str r1, [r7, #8] - 8001d86: 607a str r2, [r7, #4] + 8001dc4: b480 push {r7} + 8001dc6: b085 sub sp, #20 + 8001dc8: af00 add r7, sp, #0 + 8001dca: 60f8 str r0, [r7, #12] + 8001dcc: 60b9 str r1, [r7, #8] + 8001dce: 607a str r2, [r7, #4] /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, - 8001d88: 68fb ldr r3, [r7, #12] - 8001d8a: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0 - 8001d8e: 68bb ldr r3, [r7, #8] - 8001d90: f3c3 0312 ubfx r3, r3, #0, #19 - 8001d94: 43db mvns r3, r3 - 8001d96: 401a ands r2, r3 - 8001d98: 687b ldr r3, [r7, #4] - 8001d9a: f003 0318 and.w r3, r3, #24 - 8001d9e: 4908 ldr r1, [pc, #32] @ (8001dc0 ) - 8001da0: 40d9 lsrs r1, r3 - 8001da2: 68bb ldr r3, [r7, #8] - 8001da4: 400b ands r3, r1 - 8001da6: f3c3 0312 ubfx r3, r3, #0, #19 - 8001daa: 431a orrs r2, r3 - 8001dac: 68fb ldr r3, [r7, #12] - 8001dae: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 + 8001dd0: 68fb ldr r3, [r7, #12] + 8001dd2: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0 + 8001dd6: 68bb ldr r3, [r7, #8] + 8001dd8: f3c3 0312 ubfx r3, r3, #0, #19 + 8001ddc: 43db mvns r3, r3 + 8001dde: 401a ands r2, r3 + 8001de0: 687b ldr r3, [r7, #4] + 8001de2: f003 0318 and.w r3, r3, #24 + 8001de6: 4908 ldr r1, [pc, #32] @ (8001e08 ) + 8001de8: 40d9 lsrs r1, r3 + 8001dea: 68bb ldr r3, [r7, #8] + 8001dec: 400b ands r3, r1 + 8001dee: f3c3 0312 ubfx r3, r3, #0, #19 + 8001df2: 431a orrs r2, r3 + 8001df4: 68fb ldr r3, [r7, #12] + 8001df6: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); } - 8001db2: bf00 nop - 8001db4: 3714 adds r7, #20 - 8001db6: 46bd mov sp, r7 - 8001db8: f85d 7b04 ldr.w r7, [sp], #4 - 8001dbc: 4770 bx lr - 8001dbe: bf00 nop - 8001dc0: 0007ffff .word 0x0007ffff + 8001dfa: bf00 nop + 8001dfc: 3714 adds r7, #20 + 8001dfe: 46bd mov sp, r7 + 8001e00: f85d 7b04 ldr.w r7, [sp], #4 + 8001e04: 4770 bx lr + 8001e06: bf00 nop + 8001e08: 0007ffff .word 0x0007ffff -08001dc4 : +08001e0c : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { - 8001dc4: b480 push {r7} - 8001dc6: b083 sub sp, #12 - 8001dc8: af00 add r7, sp, #0 - 8001dca: 6078 str r0, [r7, #4] + 8001e0c: b480 push {r7} + 8001e0e: b083 sub sp, #12 + 8001e10: af00 add r7, sp, #0 + 8001e12: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); - 8001dcc: 687b ldr r3, [r7, #4] - 8001dce: 689b ldr r3, [r3, #8] - 8001dd0: f003 031f and.w r3, r3, #31 + 8001e14: 687b ldr r3, [r7, #4] + 8001e16: 689b ldr r3, [r3, #8] + 8001e18: f003 031f and.w r3, r3, #31 } - 8001dd4: 4618 mov r0, r3 - 8001dd6: 370c adds r7, #12 - 8001dd8: 46bd mov sp, r7 - 8001dda: f85d 7b04 ldr.w r7, [sp], #4 - 8001dde: 4770 bx lr + 8001e1c: 4618 mov r0, r3 + 8001e1e: 370c adds r7, #12 + 8001e20: 46bd mov sp, r7 + 8001e22: f85d 7b04 ldr.w r7, [sp], #4 + 8001e26: 4770 bx lr -08001de0 : +08001e28 : * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B */ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { - 8001de0: b480 push {r7} - 8001de2: b083 sub sp, #12 - 8001de4: af00 add r7, sp, #0 - 8001de6: 6078 str r0, [r7, #4] + 8001e28: b480 push {r7} + 8001e2a: b083 sub sp, #12 + 8001e2c: af00 add r7, sp, #0 + 8001e2e: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG)); - 8001de8: 687b ldr r3, [r7, #4] - 8001dea: 689b ldr r3, [r3, #8] - 8001dec: f403 4360 and.w r3, r3, #57344 @ 0xe000 + 8001e30: 687b ldr r3, [r7, #4] + 8001e32: 689b ldr r3, [r3, #8] + 8001e34: f403 4360 and.w r3, r3, #57344 @ 0xe000 } - 8001df0: 4618 mov r0, r3 - 8001df2: 370c adds r7, #12 - 8001df4: 46bd mov sp, r7 - 8001df6: f85d 7b04 ldr.w r7, [sp], #4 - 8001dfa: 4770 bx lr + 8001e38: 4618 mov r0, r3 + 8001e3a: 370c adds r7, #12 + 8001e3c: 46bd mov sp, r7 + 8001e3e: f85d 7b04 ldr.w r7, [sp], #4 + 8001e42: 4770 bx lr -08001dfc : +08001e44 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { - 8001dfc: b480 push {r7} - 8001dfe: b083 sub sp, #12 - 8001e00: af00 add r7, sp, #0 - 8001e02: 6078 str r0, [r7, #4] + 8001e44: b480 push {r7} + 8001e46: b083 sub sp, #12 + 8001e48: af00 add r7, sp, #0 + 8001e4a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); - 8001e04: 687b ldr r3, [r7, #4] - 8001e06: 689b ldr r3, [r3, #8] - 8001e08: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000 - 8001e0c: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001e10: 687a ldr r2, [r7, #4] - 8001e12: 6093 str r3, [r2, #8] + 8001e4c: 687b ldr r3, [r7, #4] + 8001e4e: 689b ldr r3, [r3, #8] + 8001e50: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000 + 8001e54: f023 033f bic.w r3, r3, #63 @ 0x3f + 8001e58: 687a ldr r2, [r7, #4] + 8001e5a: 6093 str r3, [r2, #8] } - 8001e14: bf00 nop - 8001e16: 370c adds r7, #12 - 8001e18: 46bd mov sp, r7 - 8001e1a: f85d 7b04 ldr.w r7, [sp], #4 - 8001e1e: 4770 bx lr + 8001e5c: bf00 nop + 8001e5e: 370c adds r7, #12 + 8001e60: 46bd mov sp, r7 + 8001e62: f85d 7b04 ldr.w r7, [sp], #4 + 8001e66: 4770 bx lr -08001e20 : +08001e68 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { - 8001e20: b480 push {r7} - 8001e22: b083 sub sp, #12 - 8001e24: af00 add r7, sp, #0 - 8001e26: 6078 str r0, [r7, #4] + 8001e68: b480 push {r7} + 8001e6a: b083 sub sp, #12 + 8001e6c: af00 add r7, sp, #0 + 8001e6e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); - 8001e28: 687b ldr r3, [r7, #4] - 8001e2a: 689b ldr r3, [r3, #8] - 8001e2c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 - 8001e30: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 - 8001e34: d101 bne.n 8001e3a - 8001e36: 2301 movs r3, #1 - 8001e38: e000 b.n 8001e3c - 8001e3a: 2300 movs r3, #0 + 8001e70: 687b ldr r3, [r7, #4] + 8001e72: 689b ldr r3, [r3, #8] + 8001e74: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 + 8001e78: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 8001e7c: d101 bne.n 8001e82 + 8001e7e: 2301 movs r3, #1 + 8001e80: e000 b.n 8001e84 + 8001e82: 2300 movs r3, #0 } - 8001e3c: 4618 mov r0, r3 - 8001e3e: 370c adds r7, #12 - 8001e40: 46bd mov sp, r7 - 8001e42: f85d 7b04 ldr.w r7, [sp], #4 - 8001e46: 4770 bx lr + 8001e84: 4618 mov r0, r3 + 8001e86: 370c adds r7, #12 + 8001e88: 46bd mov sp, r7 + 8001e8a: f85d 7b04 ldr.w r7, [sp], #4 + 8001e8e: 4770 bx lr -08001e48 : +08001e90 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { - 8001e48: b480 push {r7} - 8001e4a: b083 sub sp, #12 - 8001e4c: af00 add r7, sp, #0 - 8001e4e: 6078 str r0, [r7, #4] + 8001e90: b480 push {r7} + 8001e92: b083 sub sp, #12 + 8001e94: af00 add r7, sp, #0 + 8001e96: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8001e50: 687b ldr r3, [r7, #4] - 8001e52: 689b ldr r3, [r3, #8] - 8001e54: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000 - 8001e58: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001e5c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 - 8001e60: 687b ldr r3, [r7, #4] - 8001e62: 609a str r2, [r3, #8] + 8001e98: 687b ldr r3, [r7, #4] + 8001e9a: 689b ldr r3, [r3, #8] + 8001e9c: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000 + 8001ea0: f023 033f bic.w r3, r3, #63 @ 0x3f + 8001ea4: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 + 8001ea8: 687b ldr r3, [r7, #4] + 8001eaa: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } - 8001e64: bf00 nop - 8001e66: 370c adds r7, #12 - 8001e68: 46bd mov sp, r7 - 8001e6a: f85d 7b04 ldr.w r7, [sp], #4 - 8001e6e: 4770 bx lr + 8001eac: bf00 nop + 8001eae: 370c adds r7, #12 + 8001eb0: 46bd mov sp, r7 + 8001eb2: f85d 7b04 ldr.w r7, [sp], #4 + 8001eb6: 4770 bx lr -08001e70 : +08001eb8 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { - 8001e70: b480 push {r7} - 8001e72: b083 sub sp, #12 - 8001e74: af00 add r7, sp, #0 - 8001e76: 6078 str r0, [r7, #4] + 8001eb8: b480 push {r7} + 8001eba: b083 sub sp, #12 + 8001ebc: af00 add r7, sp, #0 + 8001ebe: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); - 8001e78: 687b ldr r3, [r7, #4] - 8001e7a: 689b ldr r3, [r3, #8] - 8001e7c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8001e80: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 - 8001e84: d101 bne.n 8001e8a - 8001e86: 2301 movs r3, #1 - 8001e88: e000 b.n 8001e8c - 8001e8a: 2300 movs r3, #0 + 8001ec0: 687b ldr r3, [r7, #4] + 8001ec2: 689b ldr r3, [r3, #8] + 8001ec4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8001ec8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 8001ecc: d101 bne.n 8001ed2 + 8001ece: 2301 movs r3, #1 + 8001ed0: e000 b.n 8001ed4 + 8001ed2: 2300 movs r3, #0 } - 8001e8c: 4618 mov r0, r3 - 8001e8e: 370c adds r7, #12 - 8001e90: 46bd mov sp, r7 - 8001e92: f85d 7b04 ldr.w r7, [sp], #4 - 8001e96: 4770 bx lr + 8001ed4: 4618 mov r0, r3 + 8001ed6: 370c adds r7, #12 + 8001ed8: 46bd mov sp, r7 + 8001eda: f85d 7b04 ldr.w r7, [sp], #4 + 8001ede: 4770 bx lr -08001e98 : +08001ee0 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { - 8001e98: b480 push {r7} - 8001e9a: b083 sub sp, #12 - 8001e9c: af00 add r7, sp, #0 - 8001e9e: 6078 str r0, [r7, #4] + 8001ee0: b480 push {r7} + 8001ee2: b083 sub sp, #12 + 8001ee4: af00 add r7, sp, #0 + 8001ee6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8001ea0: 687b ldr r3, [r7, #4] - 8001ea2: 689b ldr r3, [r3, #8] - 8001ea4: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 - 8001ea8: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001eac: f043 0201 orr.w r2, r3, #1 - 8001eb0: 687b ldr r3, [r7, #4] - 8001eb2: 609a str r2, [r3, #8] + 8001ee8: 687b ldr r3, [r7, #4] + 8001eea: 689b ldr r3, [r3, #8] + 8001eec: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8001ef0: f023 033f bic.w r3, r3, #63 @ 0x3f + 8001ef4: f043 0201 orr.w r2, r3, #1 + 8001ef8: 687b ldr r3, [r7, #4] + 8001efa: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } - 8001eb4: bf00 nop - 8001eb6: 370c adds r7, #12 - 8001eb8: 46bd mov sp, r7 - 8001eba: f85d 7b04 ldr.w r7, [sp], #4 - 8001ebe: 4770 bx lr + 8001efc: bf00 nop + 8001efe: 370c adds r7, #12 + 8001f00: 46bd mov sp, r7 + 8001f02: f85d 7b04 ldr.w r7, [sp], #4 + 8001f06: 4770 bx lr -08001ec0 : +08001f08 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { - 8001ec0: b480 push {r7} - 8001ec2: b083 sub sp, #12 - 8001ec4: af00 add r7, sp, #0 - 8001ec6: 6078 str r0, [r7, #4] + 8001f08: b480 push {r7} + 8001f0a: b083 sub sp, #12 + 8001f0c: af00 add r7, sp, #0 + 8001f0e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8001ec8: 687b ldr r3, [r7, #4] - 8001eca: 689b ldr r3, [r3, #8] - 8001ecc: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 - 8001ed0: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001ed4: f043 0202 orr.w r2, r3, #2 - 8001ed8: 687b ldr r3, [r7, #4] - 8001eda: 609a str r2, [r3, #8] + 8001f10: 687b ldr r3, [r7, #4] + 8001f12: 689b ldr r3, [r3, #8] + 8001f14: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8001f18: f023 033f bic.w r3, r3, #63 @ 0x3f + 8001f1c: f043 0202 orr.w r2, r3, #2 + 8001f20: 687b ldr r3, [r7, #4] + 8001f22: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } - 8001edc: bf00 nop - 8001ede: 370c adds r7, #12 - 8001ee0: 46bd mov sp, r7 - 8001ee2: f85d 7b04 ldr.w r7, [sp], #4 - 8001ee6: 4770 bx lr + 8001f24: bf00 nop + 8001f26: 370c adds r7, #12 + 8001f28: 46bd mov sp, r7 + 8001f2a: f85d 7b04 ldr.w r7, [sp], #4 + 8001f2e: 4770 bx lr -08001ee8 : +08001f30 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { - 8001ee8: b480 push {r7} - 8001eea: b083 sub sp, #12 - 8001eec: af00 add r7, sp, #0 - 8001eee: 6078 str r0, [r7, #4] + 8001f30: b480 push {r7} + 8001f32: b083 sub sp, #12 + 8001f34: af00 add r7, sp, #0 + 8001f36: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); - 8001ef0: 687b ldr r3, [r7, #4] - 8001ef2: 689b ldr r3, [r3, #8] - 8001ef4: f003 0301 and.w r3, r3, #1 - 8001ef8: 2b01 cmp r3, #1 - 8001efa: d101 bne.n 8001f00 - 8001efc: 2301 movs r3, #1 - 8001efe: e000 b.n 8001f02 - 8001f00: 2300 movs r3, #0 + 8001f38: 687b ldr r3, [r7, #4] + 8001f3a: 689b ldr r3, [r3, #8] + 8001f3c: f003 0301 and.w r3, r3, #1 + 8001f40: 2b01 cmp r3, #1 + 8001f42: d101 bne.n 8001f48 + 8001f44: 2301 movs r3, #1 + 8001f46: e000 b.n 8001f4a + 8001f48: 2300 movs r3, #0 } - 8001f02: 4618 mov r0, r3 - 8001f04: 370c adds r7, #12 - 8001f06: 46bd mov sp, r7 - 8001f08: f85d 7b04 ldr.w r7, [sp], #4 - 8001f0c: 4770 bx lr + 8001f4a: 4618 mov r0, r3 + 8001f4c: 370c adds r7, #12 + 8001f4e: 46bd mov sp, r7 + 8001f50: f85d 7b04 ldr.w r7, [sp], #4 + 8001f54: 4770 bx lr -08001f0e : +08001f56 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { - 8001f0e: b480 push {r7} - 8001f10: b083 sub sp, #12 - 8001f12: af00 add r7, sp, #0 - 8001f14: 6078 str r0, [r7, #4] + 8001f56: b480 push {r7} + 8001f58: b083 sub sp, #12 + 8001f5a: af00 add r7, sp, #0 + 8001f5c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); - 8001f16: 687b ldr r3, [r7, #4] - 8001f18: 689b ldr r3, [r3, #8] - 8001f1a: f003 0302 and.w r3, r3, #2 - 8001f1e: 2b02 cmp r3, #2 - 8001f20: d101 bne.n 8001f26 - 8001f22: 2301 movs r3, #1 - 8001f24: e000 b.n 8001f28 - 8001f26: 2300 movs r3, #0 + 8001f5e: 687b ldr r3, [r7, #4] + 8001f60: 689b ldr r3, [r3, #8] + 8001f62: f003 0302 and.w r3, r3, #2 + 8001f66: 2b02 cmp r3, #2 + 8001f68: d101 bne.n 8001f6e + 8001f6a: 2301 movs r3, #1 + 8001f6c: e000 b.n 8001f70 + 8001f6e: 2300 movs r3, #0 } - 8001f28: 4618 mov r0, r3 - 8001f2a: 370c adds r7, #12 - 8001f2c: 46bd mov sp, r7 - 8001f2e: f85d 7b04 ldr.w r7, [sp], #4 - 8001f32: 4770 bx lr + 8001f70: 4618 mov r0, r3 + 8001f72: 370c adds r7, #12 + 8001f74: 46bd mov sp, r7 + 8001f76: f85d 7b04 ldr.w r7, [sp], #4 + 8001f7a: 4770 bx lr -08001f34 : +08001f7c : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { - 8001f34: b480 push {r7} - 8001f36: b083 sub sp, #12 - 8001f38: af00 add r7, sp, #0 - 8001f3a: 6078 str r0, [r7, #4] + 8001f7c: b480 push {r7} + 8001f7e: b083 sub sp, #12 + 8001f80: af00 add r7, sp, #0 + 8001f82: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8001f3c: 687b ldr r3, [r7, #4] - 8001f3e: 689b ldr r3, [r3, #8] - 8001f40: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 - 8001f44: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001f48: f043 0204 orr.w r2, r3, #4 - 8001f4c: 687b ldr r3, [r7, #4] - 8001f4e: 609a str r2, [r3, #8] + 8001f84: 687b ldr r3, [r7, #4] + 8001f86: 689b ldr r3, [r3, #8] + 8001f88: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8001f8c: f023 033f bic.w r3, r3, #63 @ 0x3f + 8001f90: f043 0204 orr.w r2, r3, #4 + 8001f94: 687b ldr r3, [r7, #4] + 8001f96: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } - 8001f50: bf00 nop - 8001f52: 370c adds r7, #12 - 8001f54: 46bd mov sp, r7 - 8001f56: f85d 7b04 ldr.w r7, [sp], #4 - 8001f5a: 4770 bx lr + 8001f98: bf00 nop + 8001f9a: 370c adds r7, #12 + 8001f9c: 46bd mov sp, r7 + 8001f9e: f85d 7b04 ldr.w r7, [sp], #4 + 8001fa2: 4770 bx lr -08001f5c : +08001fa4 : * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) { - 8001f5c: b480 push {r7} - 8001f5e: b083 sub sp, #12 - 8001f60: af00 add r7, sp, #0 - 8001f62: 6078 str r0, [r7, #4] + 8001fa4: b480 push {r7} + 8001fa6: b083 sub sp, #12 + 8001fa8: af00 add r7, sp, #0 + 8001faa: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8001f64: 687b ldr r3, [r7, #4] - 8001f66: 689b ldr r3, [r3, #8] - 8001f68: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 - 8001f6c: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001f70: f043 0210 orr.w r2, r3, #16 - 8001f74: 687b ldr r3, [r7, #4] - 8001f76: 609a str r2, [r3, #8] + 8001fac: 687b ldr r3, [r7, #4] + 8001fae: 689b ldr r3, [r3, #8] + 8001fb0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8001fb4: f023 033f bic.w r3, r3, #63 @ 0x3f + 8001fb8: f043 0210 orr.w r2, r3, #16 + 8001fbc: 687b ldr r3, [r7, #4] + 8001fbe: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTP); } - 8001f78: bf00 nop - 8001f7a: 370c adds r7, #12 - 8001f7c: 46bd mov sp, r7 - 8001f7e: f85d 7b04 ldr.w r7, [sp], #4 - 8001f82: 4770 bx lr + 8001fc0: bf00 nop + 8001fc2: 370c adds r7, #12 + 8001fc4: 46bd mov sp, r7 + 8001fc6: f85d 7b04 ldr.w r7, [sp], #4 + 8001fca: 4770 bx lr -08001f84 : +08001fcc : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { - 8001f84: b480 push {r7} - 8001f86: b083 sub sp, #12 - 8001f88: af00 add r7, sp, #0 - 8001f8a: 6078 str r0, [r7, #4] + 8001fcc: b480 push {r7} + 8001fce: b083 sub sp, #12 + 8001fd0: af00 add r7, sp, #0 + 8001fd2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); - 8001f8c: 687b ldr r3, [r7, #4] - 8001f8e: 689b ldr r3, [r3, #8] - 8001f90: f003 0304 and.w r3, r3, #4 - 8001f94: 2b04 cmp r3, #4 - 8001f96: d101 bne.n 8001f9c - 8001f98: 2301 movs r3, #1 - 8001f9a: e000 b.n 8001f9e - 8001f9c: 2300 movs r3, #0 + 8001fd4: 687b ldr r3, [r7, #4] + 8001fd6: 689b ldr r3, [r3, #8] + 8001fd8: f003 0304 and.w r3, r3, #4 + 8001fdc: 2b04 cmp r3, #4 + 8001fde: d101 bne.n 8001fe4 + 8001fe0: 2301 movs r3, #1 + 8001fe2: e000 b.n 8001fe6 + 8001fe4: 2300 movs r3, #0 } - 8001f9e: 4618 mov r0, r3 - 8001fa0: 370c adds r7, #12 - 8001fa2: 46bd mov sp, r7 - 8001fa4: f85d 7b04 ldr.w r7, [sp], #4 - 8001fa8: 4770 bx lr + 8001fe6: 4618 mov r0, r3 + 8001fe8: 370c adds r7, #12 + 8001fea: 46bd mov sp, r7 + 8001fec: f85d 7b04 ldr.w r7, [sp], #4 + 8001ff0: 4770 bx lr -08001faa : +08001ff2 : * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) { - 8001faa: b480 push {r7} - 8001fac: b083 sub sp, #12 - 8001fae: af00 add r7, sp, #0 - 8001fb0: 6078 str r0, [r7, #4] + 8001ff2: b480 push {r7} + 8001ff4: b083 sub sp, #12 + 8001ff6: af00 add r7, sp, #0 + 8001ff8: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, - 8001fb2: 687b ldr r3, [r7, #4] - 8001fb4: 689b ldr r3, [r3, #8] - 8001fb6: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 - 8001fba: f023 033f bic.w r3, r3, #63 @ 0x3f - 8001fbe: f043 0220 orr.w r2, r3, #32 - 8001fc2: 687b ldr r3, [r7, #4] - 8001fc4: 609a str r2, [r3, #8] + 8001ffa: 687b ldr r3, [r7, #4] + 8001ffc: 689b ldr r3, [r3, #8] + 8001ffe: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 + 8002002: f023 033f bic.w r3, r3, #63 @ 0x3f + 8002006: f043 0220 orr.w r2, r3, #32 + 800200a: 687b ldr r3, [r7, #4] + 800200c: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_JADSTP); } - 8001fc6: bf00 nop - 8001fc8: 370c adds r7, #12 - 8001fca: 46bd mov sp, r7 - 8001fcc: f85d 7b04 ldr.w r7, [sp], #4 - 8001fd0: 4770 bx lr + 800200e: bf00 nop + 8002010: 370c adds r7, #12 + 8002012: 46bd mov sp, r7 + 8002014: f85d 7b04 ldr.w r7, [sp], #4 + 8002018: 4770 bx lr -08001fd2 : +0800201a : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { - 8001fd2: b480 push {r7} - 8001fd4: b083 sub sp, #12 - 8001fd6: af00 add r7, sp, #0 - 8001fd8: 6078 str r0, [r7, #4] + 800201a: b480 push {r7} + 800201c: b083 sub sp, #12 + 800201e: af00 add r7, sp, #0 + 8002020: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); - 8001fda: 687b ldr r3, [r7, #4] - 8001fdc: 689b ldr r3, [r3, #8] - 8001fde: f003 0308 and.w r3, r3, #8 - 8001fe2: 2b08 cmp r3, #8 - 8001fe4: d101 bne.n 8001fea - 8001fe6: 2301 movs r3, #1 - 8001fe8: e000 b.n 8001fec - 8001fea: 2300 movs r3, #0 + 8002022: 687b ldr r3, [r7, #4] + 8002024: 689b ldr r3, [r3, #8] + 8002026: f003 0308 and.w r3, r3, #8 + 800202a: 2b08 cmp r3, #8 + 800202c: d101 bne.n 8002032 + 800202e: 2301 movs r3, #1 + 8002030: e000 b.n 8002034 + 8002032: 2300 movs r3, #0 } - 8001fec: 4618 mov r0, r3 - 8001fee: 370c adds r7, #12 - 8001ff0: 46bd mov sp, r7 - 8001ff2: f85d 7b04 ldr.w r7, [sp], #4 - 8001ff6: 4770 bx lr + 8002034: 4618 mov r0, r3 + 8002036: 370c adds r7, #12 + 8002038: 46bd mov sp, r7 + 800203a: f85d 7b04 ldr.w r7, [sp], #4 + 800203e: 4770 bx lr -08001ff8 : +08002040 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { - 8001ff8: b590 push {r4, r7, lr} - 8001ffa: b089 sub sp, #36 @ 0x24 - 8001ffc: af00 add r7, sp, #0 - 8001ffe: 6078 str r0, [r7, #4] + 8002040: b590 push {r4, r7, lr} + 8002042: b089 sub sp, #36 @ 0x24 + 8002044: af00 add r7, sp, #0 + 8002046: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8002000: 2300 movs r3, #0 - 8002002: 77fb strb r3, [r7, #31] + 8002048: 2300 movs r3, #0 + 800204a: 77fb strb r3, [r7, #31] uint32_t tmp_cfgr; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0UL; - 8002004: 2300 movs r3, #0 - 8002006: 60fb str r3, [r7, #12] + 800204c: 2300 movs r3, #0 + 800204e: 60fb str r3, [r7, #12] /* Check ADC handle */ if (hadc == NULL) - 8002008: 687b ldr r3, [r7, #4] - 800200a: 2b00 cmp r3, #0 - 800200c: d101 bne.n 8002012 + 8002050: 687b ldr r3, [r7, #4] + 8002052: 2b00 cmp r3, #0 + 8002054: d101 bne.n 800205a { return HAL_ERROR; - 800200e: 2301 movs r3, #1 - 8002010: e167 b.n 80022e2 + 8002056: 2301 movs r3, #1 + 8002058: e167 b.n 800232a assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - 8002012: 687b ldr r3, [r7, #4] - 8002014: 695b ldr r3, [r3, #20] - 8002016: 2b00 cmp r3, #0 + 800205a: 687b ldr r3, [r7, #4] + 800205c: 695b ldr r3, [r3, #20] + 800205e: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) - 8002018: 687b ldr r3, [r7, #4] - 800201a: 6ddb ldr r3, [r3, #92] @ 0x5c - 800201c: 2b00 cmp r3, #0 - 800201e: d109 bne.n 8002034 + 8002060: 687b ldr r3, [r7, #4] + 8002062: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002064: 2b00 cmp r3, #0 + 8002066: d109 bne.n 800207c /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); - 8002020: 6878 ldr r0, [r7, #4] - 8002022: f7ff fb6f bl 8001704 + 8002068: 6878 ldr r0, [r7, #4] + 800206a: f7ff fb6f bl 800174c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - 8002026: 687b ldr r3, [r7, #4] - 8002028: 2200 movs r2, #0 - 800202a: 661a str r2, [r3, #96] @ 0x60 + 800206e: 687b ldr r3, [r7, #4] + 8002070: 2200 movs r2, #0 + 8002072: 661a str r2, [r3, #96] @ 0x60 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; - 800202c: 687b ldr r3, [r7, #4] - 800202e: 2200 movs r2, #0 - 8002030: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 8002074: 687b ldr r3, [r7, #4] + 8002076: 2200 movs r2, #0 + 8002078: f883 2058 strb.w r2, [r3, #88] @ 0x58 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) - 8002034: 687b ldr r3, [r7, #4] - 8002036: 681b ldr r3, [r3, #0] - 8002038: 4618 mov r0, r3 - 800203a: f7ff fef1 bl 8001e20 - 800203e: 4603 mov r3, r0 - 8002040: 2b00 cmp r3, #0 - 8002042: d004 beq.n 800204e + 800207c: 687b ldr r3, [r7, #4] + 800207e: 681b ldr r3, [r3, #0] + 8002080: 4618 mov r0, r3 + 8002082: f7ff fef1 bl 8001e68 + 8002086: 4603 mov r3, r0 + 8002088: 2b00 cmp r3, #0 + 800208a: d004 beq.n 8002096 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); - 8002044: 687b ldr r3, [r7, #4] - 8002046: 681b ldr r3, [r3, #0] - 8002048: 4618 mov r0, r3 - 800204a: f7ff fed7 bl 8001dfc + 800208c: 687b ldr r3, [r7, #4] + 800208e: 681b ldr r3, [r3, #0] + 8002090: 4618 mov r0, r3 + 8002092: f7ff fed7 bl 8001e44 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - 800204e: 687b ldr r3, [r7, #4] - 8002050: 681b ldr r3, [r3, #0] - 8002052: 4618 mov r0, r3 - 8002054: f7ff ff0c bl 8001e70 - 8002058: 4603 mov r3, r0 - 800205a: 2b00 cmp r3, #0 - 800205c: d115 bne.n 800208a + 8002096: 687b ldr r3, [r7, #4] + 8002098: 681b ldr r3, [r3, #0] + 800209a: 4618 mov r0, r3 + 800209c: f7ff ff0c bl 8001eb8 + 80020a0: 4603 mov r3, r0 + 80020a2: 2b00 cmp r3, #0 + 80020a4: d115 bne.n 80020d2 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - 800205e: 687b ldr r3, [r7, #4] - 8002060: 681b ldr r3, [r3, #0] - 8002062: 4618 mov r0, r3 - 8002064: f7ff fef0 bl 8001e48 + 80020a6: 687b ldr r3, [r7, #4] + 80020a8: 681b ldr r3, [r3, #0] + 80020aa: 4618 mov r0, r3 + 80020ac: f7ff fef0 bl 8001e90 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 8002068: 4ba0 ldr r3, [pc, #640] @ (80022ec ) - 800206a: 681b ldr r3, [r3, #0] - 800206c: 099b lsrs r3, r3, #6 - 800206e: 4aa0 ldr r2, [pc, #640] @ (80022f0 ) - 8002070: fba2 2303 umull r2, r3, r2, r3 - 8002074: 099b lsrs r3, r3, #6 - 8002076: 3301 adds r3, #1 - 8002078: 005b lsls r3, r3, #1 - 800207a: 60fb str r3, [r7, #12] + 80020b0: 4ba0 ldr r3, [pc, #640] @ (8002334 ) + 80020b2: 681b ldr r3, [r3, #0] + 80020b4: 099b lsrs r3, r3, #6 + 80020b6: 4aa0 ldr r2, [pc, #640] @ (8002338 ) + 80020b8: fba2 2303 umull r2, r3, r2, r3 + 80020bc: 099b lsrs r3, r3, #6 + 80020be: 3301 adds r3, #1 + 80020c0: 005b lsls r3, r3, #1 + 80020c2: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 800207c: e002 b.n 8002084 + 80020c4: e002 b.n 80020cc { wait_loop_index--; - 800207e: 68fb ldr r3, [r7, #12] - 8002080: 3b01 subs r3, #1 - 8002082: 60fb str r3, [r7, #12] + 80020c6: 68fb ldr r3, [r7, #12] + 80020c8: 3b01 subs r3, #1 + 80020ca: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8002084: 68fb ldr r3, [r7, #12] - 8002086: 2b00 cmp r3, #0 - 8002088: d1f9 bne.n 800207e + 80020cc: 68fb ldr r3, [r7, #12] + 80020ce: 2b00 cmp r3, #0 + 80020d0: d1f9 bne.n 80020c6 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - 800208a: 687b ldr r3, [r7, #4] - 800208c: 681b ldr r3, [r3, #0] - 800208e: 4618 mov r0, r3 - 8002090: f7ff feee bl 8001e70 - 8002094: 4603 mov r3, r0 - 8002096: 2b00 cmp r3, #0 - 8002098: d10d bne.n 80020b6 + 80020d2: 687b ldr r3, [r7, #4] + 80020d4: 681b ldr r3, [r3, #0] + 80020d6: 4618 mov r0, r3 + 80020d8: f7ff feee bl 8001eb8 + 80020dc: 4603 mov r3, r0 + 80020de: 2b00 cmp r3, #0 + 80020e0: d10d bne.n 80020fe { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 800209a: 687b ldr r3, [r7, #4] - 800209c: 6ddb ldr r3, [r3, #92] @ 0x5c - 800209e: f043 0210 orr.w r2, r3, #16 - 80020a2: 687b ldr r3, [r7, #4] - 80020a4: 65da str r2, [r3, #92] @ 0x5c + 80020e2: 687b ldr r3, [r7, #4] + 80020e4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80020e6: f043 0210 orr.w r2, r3, #16 + 80020ea: 687b ldr r3, [r7, #4] + 80020ec: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80020a6: 687b ldr r3, [r7, #4] - 80020a8: 6e1b ldr r3, [r3, #96] @ 0x60 - 80020aa: f043 0201 orr.w r2, r3, #1 - 80020ae: 687b ldr r3, [r7, #4] - 80020b0: 661a str r2, [r3, #96] @ 0x60 + 80020ee: 687b ldr r3, [r7, #4] + 80020f0: 6e1b ldr r3, [r3, #96] @ 0x60 + 80020f2: f043 0201 orr.w r2, r3, #1 + 80020f6: 687b ldr r3, [r7, #4] + 80020f8: 661a str r2, [r3, #96] @ 0x60 tmp_hal_status = HAL_ERROR; - 80020b2: 2301 movs r3, #1 - 80020b4: 77fb strb r3, [r7, #31] + 80020fa: 2301 movs r3, #1 + 80020fc: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - 80020b6: 687b ldr r3, [r7, #4] - 80020b8: 681b ldr r3, [r3, #0] - 80020ba: 4618 mov r0, r3 - 80020bc: f7ff ff62 bl 8001f84 - 80020c0: 6178 str r0, [r7, #20] + 80020fe: 687b ldr r3, [r7, #4] + 8002100: 681b ldr r3, [r3, #0] + 8002102: 4618 mov r0, r3 + 8002104: f7ff ff62 bl 8001fcc + 8002108: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - 80020c2: 687b ldr r3, [r7, #4] - 80020c4: 6ddb ldr r3, [r3, #92] @ 0x5c - 80020c6: f003 0310 and.w r3, r3, #16 - 80020ca: 2b00 cmp r3, #0 - 80020cc: f040 8100 bne.w 80022d0 + 800210a: 687b ldr r3, [r7, #4] + 800210c: 6ddb ldr r3, [r3, #92] @ 0x5c + 800210e: f003 0310 and.w r3, r3, #16 + 8002112: 2b00 cmp r3, #0 + 8002114: f040 8100 bne.w 8002318 && (tmp_adc_is_conversion_on_going_regular == 0UL) - 80020d0: 697b ldr r3, [r7, #20] - 80020d2: 2b00 cmp r3, #0 - 80020d4: f040 80fc bne.w 80022d0 + 8002118: 697b ldr r3, [r7, #20] + 800211a: 2b00 cmp r3, #0 + 800211c: f040 80fc bne.w 8002318 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 80020d8: 687b ldr r3, [r7, #4] - 80020da: 6ddb ldr r3, [r3, #92] @ 0x5c - 80020dc: f423 7381 bic.w r3, r3, #258 @ 0x102 - 80020e0: f043 0202 orr.w r2, r3, #2 - 80020e4: 687b ldr r3, [r7, #4] - 80020e6: 65da str r2, [r3, #92] @ 0x5c + 8002120: 687b ldr r3, [r7, #4] + 8002122: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002124: f423 7381 bic.w r3, r3, #258 @ 0x102 + 8002128: f043 0202 orr.w r2, r3, #2 + 800212c: 687b ldr r3, [r7, #4] + 800212e: 65da str r2, [r3, #92] @ 0x5c /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 80020e8: 687b ldr r3, [r7, #4] - 80020ea: 681b ldr r3, [r3, #0] - 80020ec: 4618 mov r0, r3 - 80020ee: f7ff fefb bl 8001ee8 - 80020f2: 4603 mov r3, r0 - 80020f4: 2b00 cmp r3, #0 - 80020f6: d111 bne.n 800211c + 8002130: 687b ldr r3, [r7, #4] + 8002132: 681b ldr r3, [r3, #0] + 8002134: 4618 mov r0, r3 + 8002136: f7ff fefb bl 8001f30 + 800213a: 4603 mov r3, r0 + 800213c: 2b00 cmp r3, #0 + 800213e: d111 bne.n 8002164 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - 80020f8: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 - 80020fc: f7ff fef4 bl 8001ee8 - 8002100: 4604 mov r4, r0 - 8002102: 487c ldr r0, [pc, #496] @ (80022f4 ) - 8002104: f7ff fef0 bl 8001ee8 - 8002108: 4603 mov r3, r0 - 800210a: 4323 orrs r3, r4 - 800210c: 2b00 cmp r3, #0 - 800210e: d105 bne.n 800211c + 8002140: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 + 8002144: f7ff fef4 bl 8001f30 + 8002148: 4604 mov r4, r0 + 800214a: 487c ldr r0, [pc, #496] @ (800233c ) + 800214c: f7ff fef0 bl 8001f30 + 8002150: 4603 mov r3, r0 + 8002152: 4323 orrs r3, r4 + 8002154: 2b00 cmp r3, #0 + 8002156: d105 bne.n 8002164 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); - 8002110: 687b ldr r3, [r7, #4] - 8002112: 685b ldr r3, [r3, #4] - 8002114: 4619 mov r1, r3 - 8002116: 4878 ldr r0, [pc, #480] @ (80022f8 ) - 8002118: f7ff fcf4 bl 8001b04 + 8002158: 687b ldr r3, [r7, #4] + 800215a: 685b ldr r3, [r3, #4] + 800215c: 4619 mov r1, r3 + 800215e: 4878 ldr r0, [pc, #480] @ (8002340 ) + 8002160: f7ff fcf4 bl 8001b4c /* - external trigger polarity Init.ExternalTrigConvEdge */ /* - continuous conversion mode Init.ContinuousConvMode */ /* - overrun Init.Overrun */ /* - discontinuous mode Init.DiscontinuousConvMode */ /* - discontinuous mode channel count Init.NbrOfDiscConversion */ tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 800211c: 687b ldr r3, [r7, #4] - 800211e: 7f5b ldrb r3, [r3, #29] - 8002120: 035a lsls r2, r3, #13 + 8002164: 687b ldr r3, [r7, #4] + 8002166: 7f5b ldrb r3, [r3, #29] + 8002168: 035a lsls r2, r3, #13 hadc->Init.Overrun | - 8002122: 687b ldr r3, [r7, #4] - 8002124: 6bdb ldr r3, [r3, #60] @ 0x3c + 800216a: 687b ldr r3, [r7, #4] + 800216c: 6bdb ldr r3, [r3, #60] @ 0x3c tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 8002126: 431a orrs r2, r3 + 800216e: 431a orrs r2, r3 hadc->Init.DataAlign | - 8002128: 687b ldr r3, [r7, #4] - 800212a: 68db ldr r3, [r3, #12] + 8002170: 687b ldr r3, [r7, #4] + 8002172: 68db ldr r3, [r3, #12] hadc->Init.Overrun | - 800212c: 431a orrs r2, r3 + 8002174: 431a orrs r2, r3 hadc->Init.Resolution | - 800212e: 687b ldr r3, [r7, #4] - 8002130: 689b ldr r3, [r3, #8] + 8002176: 687b ldr r3, [r7, #4] + 8002178: 689b ldr r3, [r3, #8] hadc->Init.DataAlign | - 8002132: 431a orrs r2, r3 + 800217a: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); - 8002134: 687b ldr r3, [r7, #4] - 8002136: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 - 800213a: 041b lsls r3, r3, #16 + 800217c: 687b ldr r3, [r7, #4] + 800217e: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 8002182: 041b lsls r3, r3, #16 tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - 800213c: 4313 orrs r3, r2 - 800213e: 61bb str r3, [r7, #24] + 8002184: 4313 orrs r3, r2 + 8002186: 61bb str r3, [r7, #24] if (hadc->Init.DiscontinuousConvMode == ENABLE) - 8002140: 687b ldr r3, [r7, #4] - 8002142: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 - 8002146: 2b01 cmp r3, #1 - 8002148: d106 bne.n 8002158 + 8002188: 687b ldr r3, [r7, #4] + 800218a: f893 3024 ldrb.w r3, [r3, #36] @ 0x24 + 800218e: 2b01 cmp r3, #1 + 8002190: d106 bne.n 80021a0 { tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); - 800214a: 687b ldr r3, [r7, #4] - 800214c: 6a9b ldr r3, [r3, #40] @ 0x28 - 800214e: 3b01 subs r3, #1 - 8002150: 045b lsls r3, r3, #17 - 8002152: 69ba ldr r2, [r7, #24] - 8002154: 4313 orrs r3, r2 - 8002156: 61bb str r3, [r7, #24] + 8002192: 687b ldr r3, [r7, #4] + 8002194: 6a9b ldr r3, [r3, #40] @ 0x28 + 8002196: 3b01 subs r3, #1 + 8002198: 045b lsls r3, r3, #17 + 800219a: 69ba ldr r2, [r7, #24] + 800219c: 4313 orrs r3, r2 + 800219e: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - 8002158: 687b ldr r3, [r7, #4] - 800215a: 6adb ldr r3, [r3, #44] @ 0x2c - 800215c: 2b00 cmp r3, #0 - 800215e: d009 beq.n 8002174 + 80021a0: 687b ldr r3, [r7, #4] + 80021a2: 6adb ldr r3, [r3, #44] @ 0x2c + 80021a4: 2b00 cmp r3, #0 + 80021a6: d009 beq.n 80021bc { tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) - 8002160: 687b ldr r3, [r7, #4] - 8002162: 6adb ldr r3, [r3, #44] @ 0x2c - 8002164: f403 7278 and.w r2, r3, #992 @ 0x3e0 + 80021a8: 687b ldr r3, [r7, #4] + 80021aa: 6adb ldr r3, [r3, #44] @ 0x2c + 80021ac: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge - 8002168: 687b ldr r3, [r7, #4] - 800216a: 6b1b ldr r3, [r3, #48] @ 0x30 - 800216c: 4313 orrs r3, r2 + 80021b0: 687b ldr r3, [r7, #4] + 80021b2: 6b1b ldr r3, [r3, #48] @ 0x30 + 80021b4: 4313 orrs r3, r2 tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) - 800216e: 69ba ldr r2, [r7, #24] - 8002170: 4313 orrs r3, r2 - 8002172: 61bb str r3, [r7, #24] + 80021b6: 69ba ldr r2, [r7, #24] + 80021b8: 4313 orrs r3, r2 + 80021ba: 61bb str r3, [r7, #24] ); } /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr); - 8002174: 687b ldr r3, [r7, #4] - 8002176: 681b ldr r3, [r3, #0] - 8002178: 68da ldr r2, [r3, #12] - 800217a: 4b60 ldr r3, [pc, #384] @ (80022fc ) - 800217c: 4013 ands r3, r2 - 800217e: 687a ldr r2, [r7, #4] - 8002180: 6812 ldr r2, [r2, #0] - 8002182: 69b9 ldr r1, [r7, #24] - 8002184: 430b orrs r3, r1 - 8002186: 60d3 str r3, [r2, #12] + 80021bc: 687b ldr r3, [r7, #4] + 80021be: 681b ldr r3, [r3, #0] + 80021c0: 68da ldr r2, [r3, #12] + 80021c2: 4b60 ldr r3, [pc, #384] @ (8002344 ) + 80021c4: 4013 ands r3, r2 + 80021c6: 687a ldr r2, [r7, #4] + 80021c8: 6812 ldr r2, [r2, #0] + 80021ca: 69b9 ldr r1, [r7, #24] + 80021cc: 430b orrs r3, r1 + 80021ce: 60d3 str r3, [r2, #12] /* Configuration of sampling mode */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode); - 8002188: 687b ldr r3, [r7, #4] - 800218a: 681b ldr r3, [r3, #0] - 800218c: 691b ldr r3, [r3, #16] - 800218e: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000 - 8002192: 687b ldr r3, [r7, #4] - 8002194: 6b5a ldr r2, [r3, #52] @ 0x34 - 8002196: 687b ldr r3, [r7, #4] - 8002198: 681b ldr r3, [r3, #0] - 800219a: 430a orrs r2, r1 - 800219c: 611a str r2, [r3, #16] + 80021d0: 687b ldr r3, [r7, #4] + 80021d2: 681b ldr r3, [r3, #0] + 80021d4: 691b ldr r3, [r3, #16] + 80021d6: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000 + 80021da: 687b ldr r3, [r7, #4] + 80021dc: 6b5a ldr r2, [r3, #52] @ 0x34 + 80021de: 687b ldr r3, [r7, #4] + 80021e0: 681b ldr r3, [r3, #0] + 80021e2: 430a orrs r2, r1 + 80021e4: 611a str r2, [r3, #16] /* conversion on going on regular and injected groups: */ /* - Gain Compensation Init.GainCompensation */ /* - DMA continuous request Init.DMAContinuousRequests */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - 800219e: 687b ldr r3, [r7, #4] - 80021a0: 681b ldr r3, [r3, #0] - 80021a2: 4618 mov r0, r3 - 80021a4: f7ff ff15 bl 8001fd2 - 80021a8: 6138 str r0, [r7, #16] + 80021e6: 687b ldr r3, [r7, #4] + 80021e8: 681b ldr r3, [r3, #0] + 80021ea: 4618 mov r0, r3 + 80021ec: f7ff ff15 bl 800201a + 80021f0: 6138 str r0, [r7, #16] if ((tmp_adc_is_conversion_on_going_regular == 0UL) - 80021aa: 697b ldr r3, [r7, #20] - 80021ac: 2b00 cmp r3, #0 - 80021ae: d16d bne.n 800228c + 80021f2: 697b ldr r3, [r7, #20] + 80021f4: 2b00 cmp r3, #0 + 80021f6: d16d bne.n 80022d4 && (tmp_adc_is_conversion_on_going_injected == 0UL) - 80021b0: 693b ldr r3, [r7, #16] - 80021b2: 2b00 cmp r3, #0 - 80021b4: d16a bne.n 800228c + 80021f8: 693b ldr r3, [r7, #16] + 80021fa: 2b00 cmp r3, #0 + 80021fc: d16a bne.n 80022d4 ) { tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - 80021b6: 687b ldr r3, [r7, #4] - 80021b8: 7f1b ldrb r3, [r3, #28] + 80021fe: 687b ldr r3, [r7, #4] + 8002200: 7f1b ldrb r3, [r3, #28] tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | - 80021ba: 039a lsls r2, r3, #14 + 8002202: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - 80021bc: 687b ldr r3, [r7, #4] - 80021be: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 - 80021c2: 005b lsls r3, r3, #1 + 8002204: 687b ldr r3, [r7, #4] + 8002206: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800220a: 005b lsls r3, r3, #1 tmp_cfgr = (ADC_CFGR_DFSDM(hadc) | - 80021c4: 4313 orrs r3, r2 - 80021c6: 61bb str r3, [r7, #24] + 800220c: 4313 orrs r3, r2 + 800220e: 61bb str r3, [r7, #24] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr); - 80021c8: 687b ldr r3, [r7, #4] - 80021ca: 681b ldr r3, [r3, #0] - 80021cc: 68db ldr r3, [r3, #12] - 80021ce: f423 4380 bic.w r3, r3, #16384 @ 0x4000 - 80021d2: f023 0302 bic.w r3, r3, #2 - 80021d6: 687a ldr r2, [r7, #4] - 80021d8: 6812 ldr r2, [r2, #0] - 80021da: 69b9 ldr r1, [r7, #24] - 80021dc: 430b orrs r3, r1 - 80021de: 60d3 str r3, [r2, #12] + 8002210: 687b ldr r3, [r7, #4] + 8002212: 681b ldr r3, [r3, #0] + 8002214: 68db ldr r3, [r3, #12] + 8002216: f423 4380 bic.w r3, r3, #16384 @ 0x4000 + 800221a: f023 0302 bic.w r3, r3, #2 + 800221e: 687a ldr r2, [r7, #4] + 8002220: 6812 ldr r2, [r2, #0] + 8002222: 69b9 ldr r1, [r7, #24] + 8002224: 430b orrs r3, r1 + 8002226: 60d3 str r3, [r2, #12] if (hadc->Init.GainCompensation != 0UL) - 80021e0: 687b ldr r3, [r7, #4] - 80021e2: 691b ldr r3, [r3, #16] - 80021e4: 2b00 cmp r3, #0 - 80021e6: d017 beq.n 8002218 + 8002228: 687b ldr r3, [r7, #4] + 800222a: 691b ldr r3, [r3, #16] + 800222c: 2b00 cmp r3, #0 + 800222e: d017 beq.n 8002260 { SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); - 80021e8: 687b ldr r3, [r7, #4] - 80021ea: 681b ldr r3, [r3, #0] - 80021ec: 691a ldr r2, [r3, #16] - 80021ee: 687b ldr r3, [r7, #4] - 80021f0: 681b ldr r3, [r3, #0] - 80021f2: f442 3280 orr.w r2, r2, #65536 @ 0x10000 - 80021f6: 611a str r2, [r3, #16] + 8002230: 687b ldr r3, [r7, #4] + 8002232: 681b ldr r3, [r3, #0] + 8002234: 691a ldr r2, [r3, #16] + 8002236: 687b ldr r3, [r7, #4] + 8002238: 681b ldr r3, [r3, #0] + 800223a: f442 3280 orr.w r2, r2, #65536 @ 0x10000 + 800223e: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation); - 80021f8: 687b ldr r3, [r7, #4] - 80021fa: 681b ldr r3, [r3, #0] - 80021fc: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 - 8002200: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 - 8002204: f023 033f bic.w r3, r3, #63 @ 0x3f - 8002208: 687a ldr r2, [r7, #4] - 800220a: 6911 ldr r1, [r2, #16] - 800220c: 687a ldr r2, [r7, #4] - 800220e: 6812 ldr r2, [r2, #0] - 8002210: 430b orrs r3, r1 - 8002212: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 - 8002216: e013 b.n 8002240 + 8002240: 687b ldr r3, [r7, #4] + 8002242: 681b ldr r3, [r3, #0] + 8002244: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 + 8002248: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 + 800224c: f023 033f bic.w r3, r3, #63 @ 0x3f + 8002250: 687a ldr r2, [r7, #4] + 8002252: 6911 ldr r1, [r2, #16] + 8002254: 687a ldr r2, [r7, #4] + 8002256: 6812 ldr r2, [r2, #0] + 8002258: 430b orrs r3, r1 + 800225a: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 + 800225e: e013 b.n 8002288 } else { CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP); - 8002218: 687b ldr r3, [r7, #4] - 800221a: 681b ldr r3, [r3, #0] - 800221c: 691a ldr r2, [r3, #16] - 800221e: 687b ldr r3, [r7, #4] - 8002220: 681b ldr r3, [r3, #0] - 8002222: f422 3280 bic.w r2, r2, #65536 @ 0x10000 - 8002226: 611a str r2, [r3, #16] + 8002260: 687b ldr r3, [r7, #4] + 8002262: 681b ldr r3, [r3, #0] + 8002264: 691a ldr r2, [r3, #16] + 8002266: 687b ldr r3, [r7, #4] + 8002268: 681b ldr r3, [r3, #0] + 800226a: f422 3280 bic.w r2, r2, #65536 @ 0x10000 + 800226e: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL); - 8002228: 687b ldr r3, [r7, #4] - 800222a: 681b ldr r3, [r3, #0] - 800222c: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 - 8002230: 687a ldr r2, [r7, #4] - 8002232: 6812 ldr r2, [r2, #0] - 8002234: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 - 8002238: f023 033f bic.w r3, r3, #63 @ 0x3f - 800223c: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 + 8002270: 687b ldr r3, [r7, #4] + 8002272: 681b ldr r3, [r3, #0] + 8002274: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0 + 8002278: 687a ldr r2, [r7, #4] + 800227a: 6812 ldr r2, [r2, #0] + 800227c: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 + 8002280: f023 033f bic.w r3, r3, #63 @ 0x3f + 8002284: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0 } if (hadc->Init.OversamplingMode == ENABLE) - 8002240: 687b ldr r3, [r7, #4] - 8002242: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 - 8002246: 2b01 cmp r3, #1 - 8002248: d118 bne.n 800227c + 8002288: 687b ldr r3, [r7, #4] + 800228a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 + 800228e: 2b01 cmp r3, #1 + 8002290: d118 bne.n 80022c4 /* Configuration of Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, - 800224a: 687b ldr r3, [r7, #4] - 800224c: 681b ldr r3, [r3, #0] - 800224e: 691b ldr r3, [r3, #16] - 8002250: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 - 8002254: f023 0304 bic.w r3, r3, #4 - 8002258: 687a ldr r2, [r7, #4] - 800225a: 6c51 ldr r1, [r2, #68] @ 0x44 - 800225c: 687a ldr r2, [r7, #4] - 800225e: 6c92 ldr r2, [r2, #72] @ 0x48 - 8002260: 4311 orrs r1, r2 - 8002262: 687a ldr r2, [r7, #4] - 8002264: 6cd2 ldr r2, [r2, #76] @ 0x4c - 8002266: 4311 orrs r1, r2 - 8002268: 687a ldr r2, [r7, #4] - 800226a: 6d12 ldr r2, [r2, #80] @ 0x50 - 800226c: 430a orrs r2, r1 - 800226e: 431a orrs r2, r3 - 8002270: 687b ldr r3, [r7, #4] - 8002272: 681b ldr r3, [r3, #0] - 8002274: f042 0201 orr.w r2, r2, #1 - 8002278: 611a str r2, [r3, #16] - 800227a: e007 b.n 800228c + 8002292: 687b ldr r3, [r7, #4] + 8002294: 681b ldr r3, [r3, #0] + 8002296: 691b ldr r3, [r3, #16] + 8002298: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 + 800229c: f023 0304 bic.w r3, r3, #4 + 80022a0: 687a ldr r2, [r7, #4] + 80022a2: 6c51 ldr r1, [r2, #68] @ 0x44 + 80022a4: 687a ldr r2, [r7, #4] + 80022a6: 6c92 ldr r2, [r2, #72] @ 0x48 + 80022a8: 4311 orrs r1, r2 + 80022aa: 687a ldr r2, [r7, #4] + 80022ac: 6cd2 ldr r2, [r2, #76] @ 0x4c + 80022ae: 4311 orrs r1, r2 + 80022b0: 687a ldr r2, [r7, #4] + 80022b2: 6d12 ldr r2, [r2, #80] @ 0x50 + 80022b4: 430a orrs r2, r1 + 80022b6: 431a orrs r2, r3 + 80022b8: 687b ldr r3, [r7, #4] + 80022ba: 681b ldr r3, [r3, #0] + 80022bc: f042 0201 orr.w r2, r2, #1 + 80022c0: 611a str r2, [r3, #16] + 80022c2: e007 b.n 80022d4 ); } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); - 800227c: 687b ldr r3, [r7, #4] - 800227e: 681b ldr r3, [r3, #0] - 8002280: 691a ldr r2, [r3, #16] - 8002282: 687b ldr r3, [r7, #4] - 8002284: 681b ldr r3, [r3, #0] - 8002286: f022 0201 bic.w r2, r2, #1 - 800228a: 611a str r2, [r3, #16] + 80022c4: 687b ldr r3, [r7, #4] + 80022c6: 681b ldr r3, [r3, #0] + 80022c8: 691a ldr r2, [r3, #16] + 80022ca: 687b ldr r3, [r7, #4] + 80022cc: 681b ldr r3, [r3, #0] + 80022ce: f022 0201 bic.w r2, r2, #1 + 80022d2: 611a str r2, [r3, #16] /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - 800228c: 687b ldr r3, [r7, #4] - 800228e: 695b ldr r3, [r3, #20] - 8002290: 2b01 cmp r3, #1 - 8002292: d10c bne.n 80022ae + 80022d4: 687b ldr r3, [r7, #4] + 80022d6: 695b ldr r3, [r3, #20] + 80022d8: 2b01 cmp r3, #1 + 80022da: d10c bne.n 80022f6 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); - 8002294: 687b ldr r3, [r7, #4] - 8002296: 681b ldr r3, [r3, #0] - 8002298: 6b1b ldr r3, [r3, #48] @ 0x30 - 800229a: f023 010f bic.w r1, r3, #15 - 800229e: 687b ldr r3, [r7, #4] - 80022a0: 6a1b ldr r3, [r3, #32] - 80022a2: 1e5a subs r2, r3, #1 - 80022a4: 687b ldr r3, [r7, #4] - 80022a6: 681b ldr r3, [r3, #0] - 80022a8: 430a orrs r2, r1 - 80022aa: 631a str r2, [r3, #48] @ 0x30 - 80022ac: e007 b.n 80022be + 80022dc: 687b ldr r3, [r7, #4] + 80022de: 681b ldr r3, [r3, #0] + 80022e0: 6b1b ldr r3, [r3, #48] @ 0x30 + 80022e2: f023 010f bic.w r1, r3, #15 + 80022e6: 687b ldr r3, [r7, #4] + 80022e8: 6a1b ldr r3, [r3, #32] + 80022ea: 1e5a subs r2, r3, #1 + 80022ec: 687b ldr r3, [r7, #4] + 80022ee: 681b ldr r3, [r3, #0] + 80022f0: 430a orrs r2, r1 + 80022f2: 631a str r2, [r3, #48] @ 0x30 + 80022f4: e007 b.n 8002306 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); - 80022ae: 687b ldr r3, [r7, #4] - 80022b0: 681b ldr r3, [r3, #0] - 80022b2: 6b1a ldr r2, [r3, #48] @ 0x30 - 80022b4: 687b ldr r3, [r7, #4] - 80022b6: 681b ldr r3, [r3, #0] - 80022b8: f022 020f bic.w r2, r2, #15 - 80022bc: 631a str r2, [r3, #48] @ 0x30 + 80022f6: 687b ldr r3, [r7, #4] + 80022f8: 681b ldr r3, [r3, #0] + 80022fa: 6b1a ldr r2, [r3, #48] @ 0x30 + 80022fc: 687b ldr r3, [r7, #4] + 80022fe: 681b ldr r3, [r3, #0] + 8002300: f022 020f bic.w r2, r2, #15 + 8002304: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); - 80022be: 687b ldr r3, [r7, #4] - 80022c0: 6ddb ldr r3, [r3, #92] @ 0x5c - 80022c2: f023 0303 bic.w r3, r3, #3 - 80022c6: f043 0201 orr.w r2, r3, #1 - 80022ca: 687b ldr r3, [r7, #4] - 80022cc: 65da str r2, [r3, #92] @ 0x5c - 80022ce: e007 b.n 80022e0 + 8002306: 687b ldr r3, [r7, #4] + 8002308: 6ddb ldr r3, [r3, #92] @ 0x5c + 800230a: f023 0303 bic.w r3, r3, #3 + 800230e: f043 0201 orr.w r2, r3, #1 + 8002312: 687b ldr r3, [r7, #4] + 8002314: 65da str r2, [r3, #92] @ 0x5c + 8002316: e007 b.n 8002328 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 80022d0: 687b ldr r3, [r7, #4] - 80022d2: 6ddb ldr r3, [r3, #92] @ 0x5c - 80022d4: f043 0210 orr.w r2, r3, #16 - 80022d8: 687b ldr r3, [r7, #4] - 80022da: 65da str r2, [r3, #92] @ 0x5c + 8002318: 687b ldr r3, [r7, #4] + 800231a: 6ddb ldr r3, [r3, #92] @ 0x5c + 800231c: f043 0210 orr.w r2, r3, #16 + 8002320: 687b ldr r3, [r7, #4] + 8002322: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; - 80022dc: 2301 movs r3, #1 - 80022de: 77fb strb r3, [r7, #31] + 8002324: 2301 movs r3, #1 + 8002326: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; - 80022e0: 7ffb ldrb r3, [r7, #31] + 8002328: 7ffb ldrb r3, [r7, #31] } - 80022e2: 4618 mov r0, r3 - 80022e4: 3724 adds r7, #36 @ 0x24 - 80022e6: 46bd mov sp, r7 - 80022e8: bd90 pop {r4, r7, pc} - 80022ea: bf00 nop - 80022ec: 20000014 .word 0x20000014 - 80022f0: 053e2d63 .word 0x053e2d63 - 80022f4: 50000100 .word 0x50000100 - 80022f8: 50000300 .word 0x50000300 - 80022fc: fff04007 .word 0xfff04007 + 800232a: 4618 mov r0, r3 + 800232c: 3724 adds r7, #36 @ 0x24 + 800232e: 46bd mov sp, r7 + 8002330: bd90 pop {r4, r7, pc} + 8002332: bf00 nop + 8002334: 20000018 .word 0x20000018 + 8002338: 053e2d63 .word 0x053e2d63 + 800233c: 50000100 .word 0x50000100 + 8002340: 50000300 .word 0x50000300 + 8002344: fff04007 .word 0xfff04007 -08002300 : +08002348 : * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { - 8002300: b580 push {r7, lr} - 8002302: b086 sub sp, #24 - 8002304: af00 add r7, sp, #0 - 8002306: 6078 str r0, [r7, #4] + 8002348: b580 push {r7, lr} + 800234a: b086 sub sp, #24 + 800234c: af00 add r7, sp, #0 + 800234e: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - 8002308: 4859 ldr r0, [pc, #356] @ (8002470 ) - 800230a: f7ff fd5b bl 8001dc4 - 800230e: 6138 str r0, [r7, #16] + 8002350: 4859 ldr r0, [pc, #356] @ (80024b8 ) + 8002352: f7ff fd5b bl 8001e0c + 8002356: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - 8002310: 687b ldr r3, [r7, #4] - 8002312: 681b ldr r3, [r3, #0] - 8002314: 4618 mov r0, r3 - 8002316: f7ff fe35 bl 8001f84 - 800231a: 4603 mov r3, r0 - 800231c: 2b00 cmp r3, #0 - 800231e: f040 809f bne.w 8002460 + 8002358: 687b ldr r3, [r7, #4] + 800235a: 681b ldr r3, [r3, #0] + 800235c: 4618 mov r0, r3 + 800235e: f7ff fe35 bl 8001fcc + 8002362: 4603 mov r3, r0 + 8002364: 2b00 cmp r3, #0 + 8002366: f040 809f bne.w 80024a8 { /* Process locked */ __HAL_LOCK(hadc); - 8002322: 687b ldr r3, [r7, #4] - 8002324: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 - 8002328: 2b01 cmp r3, #1 - 800232a: d101 bne.n 8002330 - 800232c: 2302 movs r3, #2 - 800232e: e09a b.n 8002466 - 8002330: 687b ldr r3, [r7, #4] - 8002332: 2201 movs r2, #1 - 8002334: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 800236a: 687b ldr r3, [r7, #4] + 800236c: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 + 8002370: 2b01 cmp r3, #1 + 8002372: d101 bne.n 8002378 + 8002374: 2302 movs r3, #2 + 8002376: e09a b.n 80024ae + 8002378: 687b ldr r3, [r7, #4] + 800237a: 2201 movs r2, #1 + 800237c: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - 8002338: 6878 ldr r0, [r7, #4] - 800233a: f000 fe63 bl 8003004 - 800233e: 4603 mov r3, r0 - 8002340: 75fb strb r3, [r7, #23] + 8002380: 6878 ldr r0, [r7, #4] + 8002382: f000 fe63 bl 800304c + 8002386: 4603 mov r3, r0 + 8002388: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) - 8002342: 7dfb ldrb r3, [r7, #23] - 8002344: 2b00 cmp r3, #0 - 8002346: f040 8086 bne.w 8002456 + 800238a: 7dfb ldrb r3, [r7, #23] + 800238c: 2b00 cmp r3, #0 + 800238e: f040 8086 bne.w 800249e { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, - 800234a: 687b ldr r3, [r7, #4] - 800234c: 6ddb ldr r3, [r3, #92] @ 0x5c - 800234e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 - 8002352: f023 0301 bic.w r3, r3, #1 - 8002356: f443 7280 orr.w r2, r3, #256 @ 0x100 - 800235a: 687b ldr r3, [r7, #4] - 800235c: 65da str r2, [r3, #92] @ 0x5c + 8002392: 687b ldr r3, [r7, #4] + 8002394: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002396: f423 6370 bic.w r3, r3, #3840 @ 0xf00 + 800239a: f023 0301 bic.w r3, r3, #1 + 800239e: f443 7280 orr.w r2, r3, #256 @ 0x100 + 80023a2: 687b ldr r3, [r7, #4] + 80023a4: 65da str r2, [r3, #92] @ 0x5c #if defined(ADC_MULTIMODE_SUPPORT) /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - 800235e: 687b ldr r3, [r7, #4] - 8002360: 681b ldr r3, [r3, #0] - 8002362: 4a44 ldr r2, [pc, #272] @ (8002474 ) - 8002364: 4293 cmp r3, r2 - 8002366: d002 beq.n 800236e - 8002368: 687b ldr r3, [r7, #4] - 800236a: 681b ldr r3, [r3, #0] - 800236c: e001 b.n 8002372 - 800236e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8002372: 687a ldr r2, [r7, #4] - 8002374: 6812 ldr r2, [r2, #0] - 8002376: 4293 cmp r3, r2 - 8002378: d002 beq.n 8002380 + 80023a6: 687b ldr r3, [r7, #4] + 80023a8: 681b ldr r3, [r3, #0] + 80023aa: 4a44 ldr r2, [pc, #272] @ (80024bc ) + 80023ac: 4293 cmp r3, r2 + 80023ae: d002 beq.n 80023b6 + 80023b0: 687b ldr r3, [r7, #4] + 80023b2: 681b ldr r3, [r3, #0] + 80023b4: e001 b.n 80023ba + 80023b6: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 80023ba: 687a ldr r2, [r7, #4] + 80023bc: 6812 ldr r2, [r2, #0] + 80023be: 4293 cmp r3, r2 + 80023c0: d002 beq.n 80023c8 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - 800237a: 693b ldr r3, [r7, #16] - 800237c: 2b00 cmp r3, #0 - 800237e: d105 bne.n 800238c + 80023c2: 693b ldr r3, [r7, #16] + 80023c4: 2b00 cmp r3, #0 + 80023c6: d105 bne.n 80023d4 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - 8002380: 687b ldr r3, [r7, #4] - 8002382: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002384: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 - 8002388: 687b ldr r3, [r7, #4] - 800238a: 65da str r2, [r3, #92] @ 0x5c + 80023c8: 687b ldr r3, [r7, #4] + 80023ca: 6ddb ldr r3, [r3, #92] @ 0x5c + 80023cc: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 + 80023d0: 687b ldr r3, [r7, #4] + 80023d2: 65da str r2, [r3, #92] @ 0x5c } #endif /* ADC_MULTIMODE_SUPPORT */ /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - 800238c: 687b ldr r3, [r7, #4] - 800238e: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002390: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8002394: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8002398: d106 bne.n 80023a8 + 80023d4: 687b ldr r3, [r7, #4] + 80023d6: 6ddb ldr r3, [r3, #92] @ 0x5c + 80023d8: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 80023dc: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80023e0: d106 bne.n 80023f0 { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - 800239a: 687b ldr r3, [r7, #4] - 800239c: 6e1b ldr r3, [r3, #96] @ 0x60 - 800239e: f023 0206 bic.w r2, r3, #6 - 80023a2: 687b ldr r3, [r7, #4] - 80023a4: 661a str r2, [r3, #96] @ 0x60 - 80023a6: e002 b.n 80023ae + 80023e2: 687b ldr r3, [r7, #4] + 80023e4: 6e1b ldr r3, [r3, #96] @ 0x60 + 80023e6: f023 0206 bic.w r2, r3, #6 + 80023ea: 687b ldr r3, [r7, #4] + 80023ec: 661a str r2, [r3, #96] @ 0x60 + 80023ee: e002 b.n 80023f6 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); - 80023a8: 687b ldr r3, [r7, #4] - 80023aa: 2200 movs r2, #0 - 80023ac: 661a str r2, [r3, #96] @ 0x60 + 80023f0: 687b ldr r3, [r7, #4] + 80023f2: 2200 movs r2, #0 + 80023f4: 661a str r2, [r3, #96] @ 0x60 } /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - 80023ae: 687b ldr r3, [r7, #4] - 80023b0: 681b ldr r3, [r3, #0] - 80023b2: 221c movs r2, #28 - 80023b4: 601a str r2, [r3, #0] + 80023f6: 687b ldr r3, [r7, #4] + 80023f8: 681b ldr r3, [r3, #0] + 80023fa: 221c movs r2, #28 + 80023fc: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - 80023b6: 687b ldr r3, [r7, #4] - 80023b8: 2200 movs r2, #0 - 80023ba: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80023fe: 687b ldr r3, [r7, #4] + 8002400: 2200 movs r2, #0 + 8002402: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - 80023be: 687b ldr r3, [r7, #4] - 80023c0: 681b ldr r3, [r3, #0] - 80023c2: 4a2c ldr r2, [pc, #176] @ (8002474 ) - 80023c4: 4293 cmp r3, r2 - 80023c6: d002 beq.n 80023ce - 80023c8: 687b ldr r3, [r7, #4] - 80023ca: 681b ldr r3, [r3, #0] - 80023cc: e001 b.n 80023d2 - 80023ce: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 80023d2: 687a ldr r2, [r7, #4] - 80023d4: 6812 ldr r2, [r2, #0] - 80023d6: 4293 cmp r3, r2 - 80023d8: d008 beq.n 80023ec + 8002406: 687b ldr r3, [r7, #4] + 8002408: 681b ldr r3, [r3, #0] + 800240a: 4a2c ldr r2, [pc, #176] @ (80024bc ) + 800240c: 4293 cmp r3, r2 + 800240e: d002 beq.n 8002416 + 8002410: 687b ldr r3, [r7, #4] + 8002412: 681b ldr r3, [r3, #0] + 8002414: e001 b.n 800241a + 8002416: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 800241a: 687a ldr r2, [r7, #4] + 800241c: 6812 ldr r2, [r2, #0] + 800241e: 4293 cmp r3, r2 + 8002420: d008 beq.n 8002434 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - 80023da: 693b ldr r3, [r7, #16] - 80023dc: 2b00 cmp r3, #0 - 80023de: d005 beq.n 80023ec + 8002422: 693b ldr r3, [r7, #16] + 8002424: 2b00 cmp r3, #0 + 8002426: d005 beq.n 8002434 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - 80023e0: 693b ldr r3, [r7, #16] - 80023e2: 2b05 cmp r3, #5 - 80023e4: d002 beq.n 80023ec + 8002428: 693b ldr r3, [r7, #16] + 800242a: 2b05 cmp r3, #5 + 800242c: d002 beq.n 8002434 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - 80023e6: 693b ldr r3, [r7, #16] - 80023e8: 2b09 cmp r3, #9 - 80023ea: d114 bne.n 8002416 + 800242e: 693b ldr r3, [r7, #16] + 8002430: 2b09 cmp r3, #9 + 8002432: d114 bne.n 800245e ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) - 80023ec: 687b ldr r3, [r7, #4] - 80023ee: 681b ldr r3, [r3, #0] - 80023f0: 68db ldr r3, [r3, #12] - 80023f2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 80023f6: 2b00 cmp r3, #0 - 80023f8: d007 beq.n 800240a + 8002434: 687b ldr r3, [r7, #4] + 8002436: 681b ldr r3, [r3, #0] + 8002438: 68db ldr r3, [r3, #12] + 800243a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800243e: 2b00 cmp r3, #0 + 8002440: d007 beq.n 8002452 { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - 80023fa: 687b ldr r3, [r7, #4] - 80023fc: 6ddb ldr r3, [r3, #92] @ 0x5c - 80023fe: f423 5340 bic.w r3, r3, #12288 @ 0x3000 - 8002402: f443 5280 orr.w r2, r3, #4096 @ 0x1000 - 8002406: 687b ldr r3, [r7, #4] - 8002408: 65da str r2, [r3, #92] @ 0x5c + 8002442: 687b ldr r3, [r7, #4] + 8002444: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002446: f423 5340 bic.w r3, r3, #12288 @ 0x3000 + 800244a: f443 5280 orr.w r2, r3, #4096 @ 0x1000 + 800244e: 687b ldr r3, [r7, #4] + 8002450: 65da str r2, [r3, #92] @ 0x5c } /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); - 800240a: 687b ldr r3, [r7, #4] - 800240c: 681b ldr r3, [r3, #0] - 800240e: 4618 mov r0, r3 - 8002410: f7ff fd90 bl 8001f34 - 8002414: e026 b.n 8002464 + 8002452: 687b ldr r3, [r7, #4] + 8002454: 681b ldr r3, [r3, #0] + 8002456: 4618 mov r0, r3 + 8002458: f7ff fd90 bl 8001f7c + 800245c: e026 b.n 80024ac } else { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - 8002416: 687b ldr r3, [r7, #4] - 8002418: 6ddb ldr r3, [r3, #92] @ 0x5c - 800241a: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 - 800241e: 687b ldr r3, [r7, #4] - 8002420: 65da str r2, [r3, #92] @ 0x5c + 800245e: 687b ldr r3, [r7, #4] + 8002460: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002462: f443 1280 orr.w r2, r3, #1048576 @ 0x100000 + 8002466: 687b ldr r3, [r7, #4] + 8002468: 65da str r2, [r3, #92] @ 0x5c /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - 8002422: 687b ldr r3, [r7, #4] - 8002424: 681b ldr r3, [r3, #0] - 8002426: 4a13 ldr r2, [pc, #76] @ (8002474 ) - 8002428: 4293 cmp r3, r2 - 800242a: d002 beq.n 8002432 - 800242c: 687b ldr r3, [r7, #4] - 800242e: 681b ldr r3, [r3, #0] - 8002430: e001 b.n 8002436 - 8002432: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8002436: 60fb str r3, [r7, #12] + 800246a: 687b ldr r3, [r7, #4] + 800246c: 681b ldr r3, [r3, #0] + 800246e: 4a13 ldr r2, [pc, #76] @ (80024bc ) + 8002470: 4293 cmp r3, r2 + 8002472: d002 beq.n 800247a + 8002474: 687b ldr r3, [r7, #4] + 8002476: 681b ldr r3, [r3, #0] + 8002478: e001 b.n 800247e + 800247a: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 800247e: 60fb str r3, [r7, #12] if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) - 8002438: 68fb ldr r3, [r7, #12] - 800243a: 68db ldr r3, [r3, #12] - 800243c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8002440: 2b00 cmp r3, #0 - 8002442: d00f beq.n 8002464 + 8002480: 68fb ldr r3, [r7, #12] + 8002482: 68db ldr r3, [r3, #12] + 8002484: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002488: 2b00 cmp r3, #0 + 800248a: d00f beq.n 80024ac { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - 8002444: 687b ldr r3, [r7, #4] - 8002446: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002448: f423 5340 bic.w r3, r3, #12288 @ 0x3000 - 800244c: f443 5280 orr.w r2, r3, #4096 @ 0x1000 - 8002450: 687b ldr r3, [r7, #4] - 8002452: 65da str r2, [r3, #92] @ 0x5c - 8002454: e006 b.n 8002464 + 800248c: 687b ldr r3, [r7, #4] + 800248e: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002490: f423 5340 bic.w r3, r3, #12288 @ 0x3000 + 8002494: f443 5280 orr.w r2, r3, #4096 @ 0x1000 + 8002498: 687b ldr r3, [r7, #4] + 800249a: 65da str r2, [r3, #92] @ 0x5c + 800249c: e006 b.n 80024ac #endif /* ADC_MULTIMODE_SUPPORT */ } else { /* Process unlocked */ __HAL_UNLOCK(hadc); - 8002456: 687b ldr r3, [r7, #4] - 8002458: 2200 movs r2, #0 - 800245a: f883 2058 strb.w r2, [r3, #88] @ 0x58 - 800245e: e001 b.n 8002464 + 800249e: 687b ldr r3, [r7, #4] + 80024a0: 2200 movs r2, #0 + 80024a2: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80024a6: e001 b.n 80024ac } } else { tmp_hal_status = HAL_BUSY; - 8002460: 2302 movs r3, #2 - 8002462: 75fb strb r3, [r7, #23] + 80024a8: 2302 movs r3, #2 + 80024aa: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; - 8002464: 7dfb ldrb r3, [r7, #23] + 80024ac: 7dfb ldrb r3, [r7, #23] } - 8002466: 4618 mov r0, r3 - 8002468: 3718 adds r7, #24 - 800246a: 46bd mov sp, r7 - 800246c: bd80 pop {r7, pc} - 800246e: bf00 nop - 8002470: 50000300 .word 0x50000300 - 8002474: 50000100 .word 0x50000100 + 80024ae: 4618 mov r0, r3 + 80024b0: 3718 adds r7, #24 + 80024b2: 46bd mov sp, r7 + 80024b4: bd80 pop {r7, pc} + 80024b6: bf00 nop + 80024b8: 50000300 .word 0x50000300 + 80024bc: 50000100 .word 0x50000100 -08002478 : +080024c0 : * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { - 8002478: b580 push {r7, lr} - 800247a: b084 sub sp, #16 - 800247c: af00 add r7, sp, #0 - 800247e: 6078 str r0, [r7, #4] + 80024c0: b580 push {r7, lr} + 80024c2: b084 sub sp, #16 + 80024c4: af00 add r7, sp, #0 + 80024c6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); - 8002480: 687b ldr r3, [r7, #4] - 8002482: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 - 8002486: 2b01 cmp r3, #1 - 8002488: d101 bne.n 800248e - 800248a: 2302 movs r3, #2 - 800248c: e023 b.n 80024d6 - 800248e: 687b ldr r3, [r7, #4] - 8002490: 2201 movs r2, #1 - 8002492: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80024c8: 687b ldr r3, [r7, #4] + 80024ca: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 + 80024ce: 2b01 cmp r3, #1 + 80024d0: d101 bne.n 80024d6 + 80024d2: 2302 movs r3, #2 + 80024d4: e023 b.n 800251e + 80024d6: 687b ldr r3, [r7, #4] + 80024d8: 2201 movs r2, #1 + 80024da: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - 8002496: 2103 movs r1, #3 - 8002498: 6878 ldr r0, [r7, #4] - 800249a: f000 fcf7 bl 8002e8c - 800249e: 4603 mov r3, r0 - 80024a0: 73fb strb r3, [r7, #15] + 80024de: 2103 movs r1, #3 + 80024e0: 6878 ldr r0, [r7, #4] + 80024e2: f000 fcf7 bl 8002ed4 + 80024e6: 4603 mov r3, r0 + 80024e8: 73fb strb r3, [r7, #15] /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) - 80024a2: 7bfb ldrb r3, [r7, #15] - 80024a4: 2b00 cmp r3, #0 - 80024a6: d111 bne.n 80024cc + 80024ea: 7bfb ldrb r3, [r7, #15] + 80024ec: 2b00 cmp r3, #0 + 80024ee: d111 bne.n 8002514 { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - 80024a8: 6878 ldr r0, [r7, #4] - 80024aa: f000 fe31 bl 8003110 - 80024ae: 4603 mov r3, r0 - 80024b0: 73fb strb r3, [r7, #15] + 80024f0: 6878 ldr r0, [r7, #4] + 80024f2: f000 fe31 bl 8003158 + 80024f6: 4603 mov r3, r0 + 80024f8: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) - 80024b2: 7bfb ldrb r3, [r7, #15] - 80024b4: 2b00 cmp r3, #0 - 80024b6: d109 bne.n 80024cc + 80024fa: 7bfb ldrb r3, [r7, #15] + 80024fc: 2b00 cmp r3, #0 + 80024fe: d109 bne.n 8002514 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 80024b8: 687b ldr r3, [r7, #4] - 80024ba: 6ddb ldr r3, [r3, #92] @ 0x5c - 80024bc: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 80024c0: f023 0301 bic.w r3, r3, #1 - 80024c4: f043 0201 orr.w r2, r3, #1 - 80024c8: 687b ldr r3, [r7, #4] - 80024ca: 65da str r2, [r3, #92] @ 0x5c + 8002500: 687b ldr r3, [r7, #4] + 8002502: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002504: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 8002508: f023 0301 bic.w r3, r3, #1 + 800250c: f043 0201 orr.w r2, r3, #1 + 8002510: 687b ldr r3, [r7, #4] + 8002512: 65da str r2, [r3, #92] @ 0x5c HAL_ADC_STATE_READY); } } /* Process unlocked */ __HAL_UNLOCK(hadc); - 80024cc: 687b ldr r3, [r7, #4] - 80024ce: 2200 movs r2, #0 - 80024d0: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 8002514: 687b ldr r3, [r7, #4] + 8002516: 2200 movs r2, #0 + 8002518: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; - 80024d4: 7bfb ldrb r3, [r7, #15] + 800251c: 7bfb ldrb r3, [r7, #15] } - 80024d6: 4618 mov r0, r3 - 80024d8: 3710 adds r7, #16 - 80024da: 46bd mov sp, r7 - 80024dc: bd80 pop {r7, pc} + 800251e: 4618 mov r0, r3 + 8002520: 3710 adds r7, #16 + 8002522: 46bd mov sp, r7 + 8002524: bd80 pop {r7, pc} ... -080024e0 : +08002528 : * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { - 80024e0: b580 push {r7, lr} - 80024e2: b088 sub sp, #32 - 80024e4: af00 add r7, sp, #0 - 80024e6: 6078 str r0, [r7, #4] - 80024e8: 6039 str r1, [r7, #0] + 8002528: b580 push {r7, lr} + 800252a: b088 sub sp, #32 + 800252c: af00 add r7, sp, #0 + 800252e: 6078 str r0, [r7, #4] + 8002530: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_cfgr; #if defined(ADC_MULTIMODE_SUPPORT) const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - 80024ea: 4867 ldr r0, [pc, #412] @ (8002688 ) - 80024ec: f7ff fc6a bl 8001dc4 - 80024f0: 6178 str r0, [r7, #20] + 8002532: 4867 ldr r0, [pc, #412] @ (80026d0 ) + 8002534: f7ff fc6a bl 8001e0c + 8002538: 6178 str r0, [r7, #20] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) - 80024f2: 687b ldr r3, [r7, #4] - 80024f4: 699b ldr r3, [r3, #24] - 80024f6: 2b08 cmp r3, #8 - 80024f8: d102 bne.n 8002500 + 800253a: 687b ldr r3, [r7, #4] + 800253c: 699b ldr r3, [r3, #24] + 800253e: 2b08 cmp r3, #8 + 8002540: d102 bne.n 8002548 { tmp_Flag_End = ADC_FLAG_EOS; - 80024fa: 2308 movs r3, #8 - 80024fc: 61fb str r3, [r7, #28] - 80024fe: e02a b.n 8002556 + 8002542: 2308 movs r3, #8 + 8002544: 61fb str r3, [r7, #28] + 8002546: e02a b.n 800259e /* Particular case is ADC configured in DMA mode and ADC sequencer with */ /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ #if defined(ADC_MULTIMODE_SUPPORT) if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - 8002500: 697b ldr r3, [r7, #20] - 8002502: 2b00 cmp r3, #0 - 8002504: d005 beq.n 8002512 + 8002548: 697b ldr r3, [r7, #20] + 800254a: 2b00 cmp r3, #0 + 800254c: d005 beq.n 800255a || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - 8002506: 697b ldr r3, [r7, #20] - 8002508: 2b05 cmp r3, #5 - 800250a: d002 beq.n 8002512 + 800254e: 697b ldr r3, [r7, #20] + 8002550: 2b05 cmp r3, #5 + 8002552: d002 beq.n 800255a || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - 800250c: 697b ldr r3, [r7, #20] - 800250e: 2b09 cmp r3, #9 - 8002510: d111 bne.n 8002536 + 8002554: 697b ldr r3, [r7, #20] + 8002556: 2b09 cmp r3, #9 + 8002558: d111 bne.n 800257e ) { /* Check ADC DMA mode in independent mode on ADC group regular */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) - 8002512: 687b ldr r3, [r7, #4] - 8002514: 681b ldr r3, [r3, #0] - 8002516: 68db ldr r3, [r3, #12] - 8002518: f003 0301 and.w r3, r3, #1 - 800251c: 2b00 cmp r3, #0 - 800251e: d007 beq.n 8002530 + 800255a: 687b ldr r3, [r7, #4] + 800255c: 681b ldr r3, [r3, #0] + 800255e: 68db ldr r3, [r3, #12] + 8002560: f003 0301 and.w r3, r3, #1 + 8002564: 2b00 cmp r3, #0 + 8002566: d007 beq.n 8002578 { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8002520: 687b ldr r3, [r7, #4] - 8002522: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002524: f043 0220 orr.w r2, r3, #32 - 8002528: 687b ldr r3, [r7, #4] - 800252a: 65da str r2, [r3, #92] @ 0x5c + 8002568: 687b ldr r3, [r7, #4] + 800256a: 6ddb ldr r3, [r3, #92] @ 0x5c + 800256c: f043 0220 orr.w r2, r3, #32 + 8002570: 687b ldr r3, [r7, #4] + 8002572: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; - 800252c: 2301 movs r3, #1 - 800252e: e0a6 b.n 800267e + 8002574: 2301 movs r3, #1 + 8002576: e0a6 b.n 80026c6 } else { tmp_Flag_End = (ADC_FLAG_EOC); - 8002530: 2304 movs r3, #4 - 8002532: 61fb str r3, [r7, #28] + 8002578: 2304 movs r3, #4 + 800257a: 61fb str r3, [r7, #28] if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL) - 8002534: e00f b.n 8002556 + 800257c: e00f b.n 800259e } } else { /* Check ADC DMA mode in multimode on ADC group regular */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) - 8002536: 4854 ldr r0, [pc, #336] @ (8002688 ) - 8002538: f7ff fc52 bl 8001de0 - 800253c: 4603 mov r3, r0 - 800253e: 2b00 cmp r3, #0 - 8002540: d007 beq.n 8002552 + 800257e: 4854 ldr r0, [pc, #336] @ (80026d0 ) + 8002580: f7ff fc52 bl 8001e28 + 8002584: 4603 mov r3, r0 + 8002586: 2b00 cmp r3, #0 + 8002588: d007 beq.n 800259a { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8002542: 687b ldr r3, [r7, #4] - 8002544: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002546: f043 0220 orr.w r2, r3, #32 - 800254a: 687b ldr r3, [r7, #4] - 800254c: 65da str r2, [r3, #92] @ 0x5c + 800258a: 687b ldr r3, [r7, #4] + 800258c: 6ddb ldr r3, [r3, #92] @ 0x5c + 800258e: f043 0220 orr.w r2, r3, #32 + 8002592: 687b ldr r3, [r7, #4] + 8002594: 65da str r2, [r3, #92] @ 0x5c return HAL_ERROR; - 800254e: 2301 movs r3, #1 - 8002550: e095 b.n 800267e + 8002596: 2301 movs r3, #1 + 8002598: e095 b.n 80026c6 } else { tmp_Flag_End = (ADC_FLAG_EOC); - 8002552: 2304 movs r3, #4 - 8002554: 61fb str r3, [r7, #28] + 800259a: 2304 movs r3, #4 + 800259c: 61fb str r3, [r7, #28] } #endif /* ADC_MULTIMODE_SUPPORT */ } /* Get tick count */ tickstart = HAL_GetTick(); - 8002556: f7ff fac9 bl 8001aec - 800255a: 6138 str r0, [r7, #16] + 800259e: f7ff fac9 bl 8001b34 + 80025a2: 6138 str r0, [r7, #16] /* Wait until End of unitary conversion or sequence conversions flag is raised */ while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - 800255c: e021 b.n 80025a2 + 80025a4: e021 b.n 80025ea { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) - 800255e: 683b ldr r3, [r7, #0] - 8002560: f1b3 3fff cmp.w r3, #4294967295 - 8002564: d01d beq.n 80025a2 + 80025a6: 683b ldr r3, [r7, #0] + 80025a8: f1b3 3fff cmp.w r3, #4294967295 + 80025ac: d01d beq.n 80025ea { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - 8002566: f7ff fac1 bl 8001aec - 800256a: 4602 mov r2, r0 - 800256c: 693b ldr r3, [r7, #16] - 800256e: 1ad3 subs r3, r2, r3 - 8002570: 683a ldr r2, [r7, #0] - 8002572: 429a cmp r2, r3 - 8002574: d302 bcc.n 800257c - 8002576: 683b ldr r3, [r7, #0] - 8002578: 2b00 cmp r3, #0 - 800257a: d112 bne.n 80025a2 + 80025ae: f7ff fac1 bl 8001b34 + 80025b2: 4602 mov r2, r0 + 80025b4: 693b ldr r3, [r7, #16] + 80025b6: 1ad3 subs r3, r2, r3 + 80025b8: 683a ldr r2, [r7, #0] + 80025ba: 429a cmp r2, r3 + 80025bc: d302 bcc.n 80025c4 + 80025be: 683b ldr r3, [r7, #0] + 80025c0: 2b00 cmp r3, #0 + 80025c2: d112 bne.n 80025ea { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - 800257c: 687b ldr r3, [r7, #4] - 800257e: 681b ldr r3, [r3, #0] - 8002580: 681a ldr r2, [r3, #0] - 8002582: 69fb ldr r3, [r7, #28] - 8002584: 4013 ands r3, r2 - 8002586: 2b00 cmp r3, #0 - 8002588: d10b bne.n 80025a2 + 80025c4: 687b ldr r3, [r7, #4] + 80025c6: 681b ldr r3, [r3, #0] + 80025c8: 681a ldr r2, [r3, #0] + 80025ca: 69fb ldr r3, [r7, #28] + 80025cc: 4013 ands r3, r2 + 80025ce: 2b00 cmp r3, #0 + 80025d0: d10b bne.n 80025ea { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - 800258a: 687b ldr r3, [r7, #4] - 800258c: 6ddb ldr r3, [r3, #92] @ 0x5c - 800258e: f043 0204 orr.w r2, r3, #4 - 8002592: 687b ldr r3, [r7, #4] - 8002594: 65da str r2, [r3, #92] @ 0x5c + 80025d2: 687b ldr r3, [r7, #4] + 80025d4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025d6: f043 0204 orr.w r2, r3, #4 + 80025da: 687b ldr r3, [r7, #4] + 80025dc: 65da str r2, [r3, #92] @ 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); - 8002596: 687b ldr r3, [r7, #4] - 8002598: 2200 movs r2, #0 - 800259a: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80025de: 687b ldr r3, [r7, #4] + 80025e0: 2200 movs r2, #0 + 80025e2: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_TIMEOUT; - 800259e: 2303 movs r3, #3 - 80025a0: e06d b.n 800267e + 80025e6: 2303 movs r3, #3 + 80025e8: e06d b.n 80026c6 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - 80025a2: 687b ldr r3, [r7, #4] - 80025a4: 681b ldr r3, [r3, #0] - 80025a6: 681a ldr r2, [r3, #0] - 80025a8: 69fb ldr r3, [r7, #28] - 80025aa: 4013 ands r3, r2 - 80025ac: 2b00 cmp r3, #0 - 80025ae: d0d6 beq.n 800255e + 80025ea: 687b ldr r3, [r7, #4] + 80025ec: 681b ldr r3, [r3, #0] + 80025ee: 681a ldr r2, [r3, #0] + 80025f0: 69fb ldr r3, [r7, #28] + 80025f2: 4013 ands r3, r2 + 80025f4: 2b00 cmp r3, #0 + 80025f6: d0d6 beq.n 80025a6 } } } /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - 80025b0: 687b ldr r3, [r7, #4] - 80025b2: 6ddb ldr r3, [r3, #92] @ 0x5c - 80025b4: f443 7200 orr.w r2, r3, #512 @ 0x200 - 80025b8: 687b ldr r3, [r7, #4] - 80025ba: 65da str r2, [r3, #92] @ 0x5c + 80025f8: 687b ldr r3, [r7, #4] + 80025fa: 6ddb ldr r3, [r3, #92] @ 0x5c + 80025fc: f443 7200 orr.w r2, r3, #512 @ 0x200 + 8002600: 687b ldr r3, [r7, #4] + 8002602: 65da str r2, [r3, #92] @ 0x5c /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - 80025bc: 687b ldr r3, [r7, #4] - 80025be: 681b ldr r3, [r3, #0] - 80025c0: 4618 mov r0, r3 - 80025c2: f7ff fb71 bl 8001ca8 - 80025c6: 4603 mov r3, r0 - 80025c8: 2b00 cmp r3, #0 - 80025ca: d01c beq.n 8002606 + 8002604: 687b ldr r3, [r7, #4] + 8002606: 681b ldr r3, [r3, #0] + 8002608: 4618 mov r0, r3 + 800260a: f7ff fb71 bl 8001cf0 + 800260e: 4603 mov r3, r0 + 8002610: 2b00 cmp r3, #0 + 8002612: d01c beq.n 800264e && (hadc->Init.ContinuousConvMode == DISABLE) - 80025cc: 687b ldr r3, [r7, #4] - 80025ce: 7f5b ldrb r3, [r3, #29] - 80025d0: 2b00 cmp r3, #0 - 80025d2: d118 bne.n 8002606 + 8002614: 687b ldr r3, [r7, #4] + 8002616: 7f5b ldrb r3, [r3, #29] + 8002618: 2b00 cmp r3, #0 + 800261a: d118 bne.n 800264e ) { /* Check whether end of sequence is reached */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - 80025d4: 687b ldr r3, [r7, #4] - 80025d6: 681b ldr r3, [r3, #0] - 80025d8: 681b ldr r3, [r3, #0] - 80025da: f003 0308 and.w r3, r3, #8 - 80025de: 2b08 cmp r3, #8 - 80025e0: d111 bne.n 8002606 + 800261c: 687b ldr r3, [r7, #4] + 800261e: 681b ldr r3, [r3, #0] + 8002620: 681b ldr r3, [r3, #0] + 8002622: f003 0308 and.w r3, r3, #8 + 8002626: 2b08 cmp r3, #8 + 8002628: d111 bne.n 800264e { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - 80025e2: 687b ldr r3, [r7, #4] - 80025e4: 6ddb ldr r3, [r3, #92] @ 0x5c - 80025e6: f423 7280 bic.w r2, r3, #256 @ 0x100 - 80025ea: 687b ldr r3, [r7, #4] - 80025ec: 65da str r2, [r3, #92] @ 0x5c + 800262a: 687b ldr r3, [r7, #4] + 800262c: 6ddb ldr r3, [r3, #92] @ 0x5c + 800262e: f423 7280 bic.w r2, r3, #256 @ 0x100 + 8002632: 687b ldr r3, [r7, #4] + 8002634: 65da str r2, [r3, #92] @ 0x5c if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - 80025ee: 687b ldr r3, [r7, #4] - 80025f0: 6ddb ldr r3, [r3, #92] @ 0x5c - 80025f2: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 80025f6: 2b00 cmp r3, #0 - 80025f8: d105 bne.n 8002606 + 8002636: 687b ldr r3, [r7, #4] + 8002638: 6ddb ldr r3, [r3, #92] @ 0x5c + 800263a: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 800263e: 2b00 cmp r3, #0 + 8002640: d105 bne.n 800264e { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - 80025fa: 687b ldr r3, [r7, #4] - 80025fc: 6ddb ldr r3, [r3, #92] @ 0x5c - 80025fe: f043 0201 orr.w r2, r3, #1 - 8002602: 687b ldr r3, [r7, #4] - 8002604: 65da str r2, [r3, #92] @ 0x5c + 8002642: 687b ldr r3, [r7, #4] + 8002644: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002646: f043 0201 orr.w r2, r3, #1 + 800264a: 687b ldr r3, [r7, #4] + 800264c: 65da str r2, [r3, #92] @ 0x5c /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ #if defined(ADC_MULTIMODE_SUPPORT) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - 8002606: 687b ldr r3, [r7, #4] - 8002608: 681b ldr r3, [r3, #0] - 800260a: 4a20 ldr r2, [pc, #128] @ (800268c ) - 800260c: 4293 cmp r3, r2 - 800260e: d002 beq.n 8002616 - 8002610: 687b ldr r3, [r7, #4] - 8002612: 681b ldr r3, [r3, #0] - 8002614: e001 b.n 800261a - 8002616: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 800261a: 687a ldr r2, [r7, #4] - 800261c: 6812 ldr r2, [r2, #0] - 800261e: 4293 cmp r3, r2 - 8002620: d008 beq.n 8002634 + 800264e: 687b ldr r3, [r7, #4] + 8002650: 681b ldr r3, [r3, #0] + 8002652: 4a20 ldr r2, [pc, #128] @ (80026d4 ) + 8002654: 4293 cmp r3, r2 + 8002656: d002 beq.n 800265e + 8002658: 687b ldr r3, [r7, #4] + 800265a: 681b ldr r3, [r3, #0] + 800265c: e001 b.n 8002662 + 800265e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 8002662: 687a ldr r2, [r7, #4] + 8002664: 6812 ldr r2, [r2, #0] + 8002666: 4293 cmp r3, r2 + 8002668: d008 beq.n 800267c || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - 8002622: 697b ldr r3, [r7, #20] - 8002624: 2b00 cmp r3, #0 - 8002626: d005 beq.n 8002634 + 800266a: 697b ldr r3, [r7, #20] + 800266c: 2b00 cmp r3, #0 + 800266e: d005 beq.n 800267c || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - 8002628: 697b ldr r3, [r7, #20] - 800262a: 2b05 cmp r3, #5 - 800262c: d002 beq.n 8002634 + 8002670: 697b ldr r3, [r7, #20] + 8002672: 2b05 cmp r3, #5 + 8002674: d002 beq.n 800267c || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) - 800262e: 697b ldr r3, [r7, #20] - 8002630: 2b09 cmp r3, #9 - 8002632: d104 bne.n 800263e + 8002676: 697b ldr r3, [r7, #20] + 8002678: 2b09 cmp r3, #9 + 800267a: d104 bne.n 8002686 ) { /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); - 8002634: 687b ldr r3, [r7, #4] - 8002636: 681b ldr r3, [r3, #0] - 8002638: 68db ldr r3, [r3, #12] - 800263a: 61bb str r3, [r7, #24] - 800263c: e00d b.n 800265a + 800267c: 687b ldr r3, [r7, #4] + 800267e: 681b ldr r3, [r3, #0] + 8002680: 68db ldr r3, [r3, #12] + 8002682: 61bb str r3, [r7, #24] + 8002684: e00d b.n 80026a2 } else { /* Retrieve Master ADC CFGR register */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); - 800263e: 687b ldr r3, [r7, #4] - 8002640: 681b ldr r3, [r3, #0] - 8002642: 4a12 ldr r2, [pc, #72] @ (800268c ) - 8002644: 4293 cmp r3, r2 - 8002646: d002 beq.n 800264e - 8002648: 687b ldr r3, [r7, #4] - 800264a: 681b ldr r3, [r3, #0] - 800264c: e001 b.n 8002652 - 800264e: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 - 8002652: 60fb str r3, [r7, #12] + 8002686: 687b ldr r3, [r7, #4] + 8002688: 681b ldr r3, [r3, #0] + 800268a: 4a12 ldr r2, [pc, #72] @ (80026d4 ) + 800268c: 4293 cmp r3, r2 + 800268e: d002 beq.n 8002696 + 8002690: 687b ldr r3, [r7, #4] + 8002692: 681b ldr r3, [r3, #0] + 8002694: e001 b.n 800269a + 8002696: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000 + 800269a: 60fb str r3, [r7, #12] tmp_cfgr = READ_REG(tmpADC_Master->CFGR); - 8002654: 68fb ldr r3, [r7, #12] - 8002656: 68db ldr r3, [r3, #12] - 8002658: 61bb str r3, [r7, #24] + 800269c: 68fb ldr r3, [r7, #12] + 800269e: 68db ldr r3, [r3, #12] + 80026a0: 61bb str r3, [r7, #24] /* Retrieve handle ADC CFGR register */ tmp_cfgr = READ_REG(hadc->Instance->CFGR); #endif /* ADC_MULTIMODE_SUPPORT */ /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) - 800265a: 69fb ldr r3, [r7, #28] - 800265c: 2b08 cmp r3, #8 - 800265e: d104 bne.n 800266a + 80026a2: 69fb ldr r3, [r7, #28] + 80026a4: 2b08 cmp r3, #8 + 80026a6: d104 bne.n 80026b2 { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); - 8002660: 687b ldr r3, [r7, #4] - 8002662: 681b ldr r3, [r3, #0] - 8002664: 2208 movs r2, #8 - 8002666: 601a str r2, [r3, #0] - 8002668: e008 b.n 800267c + 80026a8: 687b ldr r3, [r7, #4] + 80026aa: 681b ldr r3, [r3, #0] + 80026ac: 2208 movs r2, #8 + 80026ae: 601a str r2, [r3, #0] + 80026b0: e008 b.n 80026c4 else { /* Clear end of conversion EOC flag of regular group if low power feature */ /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ /* until data register is read using function HAL_ADC_GetValue(). */ if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) - 800266a: 69bb ldr r3, [r7, #24] - 800266c: f403 4380 and.w r3, r3, #16384 @ 0x4000 - 8002670: 2b00 cmp r3, #0 - 8002672: d103 bne.n 800267c + 80026b2: 69bb ldr r3, [r7, #24] + 80026b4: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 80026b8: 2b00 cmp r3, #0 + 80026ba: d103 bne.n 80026c4 { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - 8002674: 687b ldr r3, [r7, #4] - 8002676: 681b ldr r3, [r3, #0] - 8002678: 220c movs r2, #12 - 800267a: 601a str r2, [r3, #0] + 80026bc: 687b ldr r3, [r7, #4] + 80026be: 681b ldr r3, [r3, #0] + 80026c0: 220c movs r2, #12 + 80026c2: 601a str r2, [r3, #0] } } /* Return function status */ return HAL_OK; - 800267c: 2300 movs r3, #0 + 80026c4: 2300 movs r3, #0 } - 800267e: 4618 mov r0, r3 - 8002680: 3720 adds r7, #32 - 8002682: 46bd mov sp, r7 - 8002684: bd80 pop {r7, pc} - 8002686: bf00 nop - 8002688: 50000300 .word 0x50000300 - 800268c: 50000100 .word 0x50000100 + 80026c6: 4618 mov r0, r3 + 80026c8: 3720 adds r7, #32 + 80026ca: 46bd mov sp, r7 + 80026cc: bd80 pop {r7, pc} + 80026ce: bf00 nop + 80026d0: 50000300 .word 0x50000300 + 80026d4: 50000100 .word 0x50000100 -08002690 : +080026d8 : * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). * @param hadc ADC handle * @retval ADC group regular conversion data */ uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) { - 8002690: b480 push {r7} - 8002692: b083 sub sp, #12 - 8002694: af00 add r7, sp, #0 - 8002696: 6078 str r0, [r7, #4] + 80026d8: b480 push {r7} + 80026da: b083 sub sp, #12 + 80026dc: af00 add r7, sp, #0 + 80026de: 6078 str r0, [r7, #4] /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ /* Return ADC converted value */ return hadc->Instance->DR; - 8002698: 687b ldr r3, [r7, #4] - 800269a: 681b ldr r3, [r3, #0] - 800269c: 6c1b ldr r3, [r3, #64] @ 0x40 + 80026e0: 687b ldr r3, [r7, #4] + 80026e2: 681b ldr r3, [r3, #0] + 80026e4: 6c1b ldr r3, [r3, #64] @ 0x40 } - 800269e: 4618 mov r0, r3 - 80026a0: 370c adds r7, #12 - 80026a2: 46bd mov sp, r7 - 80026a4: f85d 7b04 ldr.w r7, [sp], #4 - 80026a8: 4770 bx lr + 80026e6: 4618 mov r0, r3 + 80026e8: 370c adds r7, #12 + 80026ea: 46bd mov sp, r7 + 80026ec: f85d 7b04 ldr.w r7, [sp], #4 + 80026f0: 4770 bx lr ... -080026ac : +080026f4 : * @param hadc ADC handle * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) { - 80026ac: b580 push {r7, lr} - 80026ae: b0b6 sub sp, #216 @ 0xd8 - 80026b0: af00 add r7, sp, #0 - 80026b2: 6078 str r0, [r7, #4] - 80026b4: 6039 str r1, [r7, #0] + 80026f4: b580 push {r7, lr} + 80026f6: b0b6 sub sp, #216 @ 0xd8 + 80026f8: af00 add r7, sp, #0 + 80026fa: 6078 str r0, [r7, #4] + 80026fc: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 80026b6: 2300 movs r3, #0 - 80026b8: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 + 80026fe: 2300 movs r3, #0 + 8002700: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0UL; - 80026bc: 2300 movs r3, #0 - 80026be: 60fb str r3, [r7, #12] + 8002704: 2300 movs r3, #0 + 8002706: 60fb str r3, [r7, #12] { assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel)); } /* Process locked */ __HAL_LOCK(hadc); - 80026c0: 687b ldr r3, [r7, #4] - 80026c2: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 - 80026c6: 2b01 cmp r3, #1 - 80026c8: d101 bne.n 80026ce - 80026ca: 2302 movs r3, #2 - 80026cc: e3c8 b.n 8002e60 - 80026ce: 687b ldr r3, [r7, #4] - 80026d0: 2201 movs r2, #1 - 80026d2: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 8002708: 687b ldr r3, [r7, #4] + 800270a: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 + 800270e: 2b01 cmp r3, #1 + 8002710: d101 bne.n 8002716 + 8002712: 2302 movs r3, #2 + 8002714: e3c8 b.n 8002ea8 + 8002716: 687b ldr r3, [r7, #4] + 8002718: 2201 movs r2, #1 + 800271a: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - 80026d6: 687b ldr r3, [r7, #4] - 80026d8: 681b ldr r3, [r3, #0] - 80026da: 4618 mov r0, r3 - 80026dc: f7ff fc52 bl 8001f84 - 80026e0: 4603 mov r3, r0 - 80026e2: 2b00 cmp r3, #0 - 80026e4: f040 83ad bne.w 8002e42 + 800271e: 687b ldr r3, [r7, #4] + 8002720: 681b ldr r3, [r3, #0] + 8002722: 4618 mov r0, r3 + 8002724: f7ff fc52 bl 8001fcc + 8002728: 4603 mov r3, r0 + 800272a: 2b00 cmp r3, #0 + 800272c: f040 83ad bne.w 8002e8a { /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); - 80026e8: 687b ldr r3, [r7, #4] - 80026ea: 6818 ldr r0, [r3, #0] - 80026ec: 683b ldr r3, [r7, #0] - 80026ee: 6859 ldr r1, [r3, #4] - 80026f0: 683b ldr r3, [r7, #0] - 80026f2: 681b ldr r3, [r3, #0] - 80026f4: 461a mov r2, r3 - 80026f6: f7ff faea bl 8001cce + 8002730: 687b ldr r3, [r7, #4] + 8002732: 6818 ldr r0, [r3, #0] + 8002734: 683b ldr r3, [r7, #0] + 8002736: 6859 ldr r1, [r3, #4] + 8002738: 683b ldr r3, [r7, #0] + 800273a: 681b ldr r3, [r3, #0] + 800273c: 461a mov r2, r3 + 800273e: f7ff faea bl 8001d16 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - 80026fa: 687b ldr r3, [r7, #4] - 80026fc: 681b ldr r3, [r3, #0] - 80026fe: 4618 mov r0, r3 - 8002700: f7ff fc40 bl 8001f84 - 8002704: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0 + 8002742: 687b ldr r3, [r7, #4] + 8002744: 681b ldr r3, [r3, #0] + 8002746: 4618 mov r0, r3 + 8002748: f7ff fc40 bl 8001fcc + 800274c: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - 8002708: 687b ldr r3, [r7, #4] - 800270a: 681b ldr r3, [r3, #0] - 800270c: 4618 mov r0, r3 - 800270e: f7ff fc60 bl 8001fd2 - 8002712: f8c7 00cc str.w r0, [r7, #204] @ 0xcc + 8002750: 687b ldr r3, [r7, #4] + 8002752: 681b ldr r3, [r3, #0] + 8002754: 4618 mov r0, r3 + 8002756: f7ff fc60 bl 800201a + 800275a: f8c7 00cc str.w r0, [r7, #204] @ 0xcc if ((tmp_adc_is_conversion_on_going_regular == 0UL) - 8002716: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 - 800271a: 2b00 cmp r3, #0 - 800271c: f040 81d9 bne.w 8002ad2 + 800275e: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 + 8002762: 2b00 cmp r3, #0 + 8002764: f040 81d9 bne.w 8002b1a && (tmp_adc_is_conversion_on_going_injected == 0UL) - 8002720: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc - 8002724: 2b00 cmp r3, #0 - 8002726: f040 81d4 bne.w 8002ad2 + 8002768: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc + 800276c: 2b00 cmp r3, #0 + 800276e: f040 81d4 bne.w 8002b1a ) { /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) - 800272a: 683b ldr r3, [r7, #0] - 800272c: 689b ldr r3, [r3, #8] - 800272e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 - 8002732: d10f bne.n 8002754 + 8002772: 683b ldr r3, [r7, #0] + 8002774: 689b ldr r3, [r3, #8] + 8002776: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 800277a: d10f bne.n 800279c { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); - 8002734: 687b ldr r3, [r7, #4] - 8002736: 6818 ldr r0, [r3, #0] - 8002738: 683b ldr r3, [r7, #0] - 800273a: 681b ldr r3, [r3, #0] - 800273c: 2200 movs r2, #0 - 800273e: 4619 mov r1, r3 - 8002740: f7ff faf1 bl 8001d26 + 800277c: 687b ldr r3, [r7, #4] + 800277e: 6818 ldr r0, [r3, #0] + 8002780: 683b ldr r3, [r7, #0] + 8002782: 681b ldr r3, [r3, #0] + 8002784: 2200 movs r2, #0 + 8002786: 4619 mov r1, r3 + 8002788: f7ff faf1 bl 8001d6e /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); - 8002744: 687b ldr r3, [r7, #4] - 8002746: 681b ldr r3, [r3, #0] - 8002748: f04f 4100 mov.w r1, #2147483648 @ 0x80000000 - 800274c: 4618 mov r0, r3 - 800274e: f7ff fa98 bl 8001c82 - 8002752: e00e b.n 8002772 + 800278c: 687b ldr r3, [r7, #4] + 800278e: 681b ldr r3, [r3, #0] + 8002790: f04f 4100 mov.w r1, #2147483648 @ 0x80000000 + 8002794: 4618 mov r0, r3 + 8002796: f7ff fa98 bl 8001cca + 800279a: e00e b.n 80027ba } else { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); - 8002754: 687b ldr r3, [r7, #4] - 8002756: 6818 ldr r0, [r3, #0] - 8002758: 683b ldr r3, [r7, #0] - 800275a: 6819 ldr r1, [r3, #0] - 800275c: 683b ldr r3, [r7, #0] - 800275e: 689b ldr r3, [r3, #8] - 8002760: 461a mov r2, r3 - 8002762: f7ff fae0 bl 8001d26 + 800279c: 687b ldr r3, [r7, #4] + 800279e: 6818 ldr r0, [r3, #0] + 80027a0: 683b ldr r3, [r7, #0] + 80027a2: 6819 ldr r1, [r3, #0] + 80027a4: 683b ldr r3, [r7, #0] + 80027a6: 689b ldr r3, [r3, #8] + 80027a8: 461a mov r2, r3 + 80027aa: f7ff fae0 bl 8001d6e /* Set ADC sampling time common configuration */ LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); - 8002766: 687b ldr r3, [r7, #4] - 8002768: 681b ldr r3, [r3, #0] - 800276a: 2100 movs r1, #0 - 800276c: 4618 mov r0, r3 - 800276e: f7ff fa88 bl 8001c82 + 80027ae: 687b ldr r3, [r7, #4] + 80027b0: 681b ldr r3, [r3, #0] + 80027b2: 2100 movs r1, #0 + 80027b4: 4618 mov r0, r3 + 80027b6: f7ff fa88 bl 8001cca /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset); - 8002772: 683b ldr r3, [r7, #0] - 8002774: 695a ldr r2, [r3, #20] - 8002776: 687b ldr r3, [r7, #4] - 8002778: 681b ldr r3, [r3, #0] - 800277a: 68db ldr r3, [r3, #12] - 800277c: 08db lsrs r3, r3, #3 - 800277e: f003 0303 and.w r3, r3, #3 - 8002782: 005b lsls r3, r3, #1 - 8002784: fa02 f303 lsl.w r3, r2, r3 - 8002788: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 80027ba: 683b ldr r3, [r7, #0] + 80027bc: 695a ldr r2, [r3, #20] + 80027be: 687b ldr r3, [r7, #4] + 80027c0: 681b ldr r3, [r3, #0] + 80027c2: 68db ldr r3, [r3, #12] + 80027c4: 08db lsrs r3, r3, #3 + 80027c6: f003 0303 and.w r3, r3, #3 + 80027ca: 005b lsls r3, r3, #1 + 80027cc: fa02 f303 lsl.w r3, r2, r3 + 80027d0: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 if (pConfig->OffsetNumber != ADC_OFFSET_NONE) - 800278c: 683b ldr r3, [r7, #0] - 800278e: 691b ldr r3, [r3, #16] - 8002790: 2b04 cmp r3, #4 - 8002792: d022 beq.n 80027da + 80027d4: 683b ldr r3, [r7, #0] + 80027d6: 691b ldr r3, [r3, #16] + 80027d8: 2b04 cmp r3, #4 + 80027da: d022 beq.n 8002822 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted); - 8002794: 687b ldr r3, [r7, #4] - 8002796: 6818 ldr r0, [r3, #0] - 8002798: 683b ldr r3, [r7, #0] - 800279a: 6919 ldr r1, [r3, #16] - 800279c: 683b ldr r3, [r7, #0] - 800279e: 681a ldr r2, [r3, #0] - 80027a0: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 - 80027a4: f7ff f9e2 bl 8001b6c + 80027dc: 687b ldr r3, [r7, #4] + 80027de: 6818 ldr r0, [r3, #0] + 80027e0: 683b ldr r3, [r7, #0] + 80027e2: 6919 ldr r1, [r3, #16] + 80027e4: 683b ldr r3, [r7, #0] + 80027e6: 681a ldr r2, [r3, #0] + 80027e8: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 + 80027ec: f7ff f9e2 bl 8001bb4 assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign)); assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation)); /* Set ADC selected offset sign & saturation */ LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign); - 80027a8: 687b ldr r3, [r7, #4] - 80027aa: 6818 ldr r0, [r3, #0] - 80027ac: 683b ldr r3, [r7, #0] - 80027ae: 6919 ldr r1, [r3, #16] - 80027b0: 683b ldr r3, [r7, #0] - 80027b2: 699b ldr r3, [r3, #24] - 80027b4: 461a mov r2, r3 - 80027b6: f7ff fa2e bl 8001c16 + 80027f0: 687b ldr r3, [r7, #4] + 80027f2: 6818 ldr r0, [r3, #0] + 80027f4: 683b ldr r3, [r7, #0] + 80027f6: 6919 ldr r1, [r3, #16] + 80027f8: 683b ldr r3, [r7, #0] + 80027fa: 699b ldr r3, [r3, #24] + 80027fc: 461a mov r2, r3 + 80027fe: f7ff fa2e bl 8001c5e LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, - 80027ba: 687b ldr r3, [r7, #4] - 80027bc: 6818 ldr r0, [r3, #0] - 80027be: 683b ldr r3, [r7, #0] - 80027c0: 6919 ldr r1, [r3, #16] + 8002802: 687b ldr r3, [r7, #4] + 8002804: 6818 ldr r0, [r3, #0] + 8002806: 683b ldr r3, [r7, #0] + 8002808: 6919 ldr r1, [r3, #16] (pConfig->OffsetSaturation == ENABLE) ? - 80027c2: 683b ldr r3, [r7, #0] - 80027c4: 7f1b ldrb r3, [r3, #28] + 800280a: 683b ldr r3, [r7, #0] + 800280c: 7f1b ldrb r3, [r3, #28] LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber, - 80027c6: 2b01 cmp r3, #1 - 80027c8: d102 bne.n 80027d0 - 80027ca: f04f 7300 mov.w r3, #33554432 @ 0x2000000 - 80027ce: e000 b.n 80027d2 - 80027d0: 2300 movs r3, #0 - 80027d2: 461a mov r2, r3 - 80027d4: f7ff fa3a bl 8001c4c - 80027d8: e17b b.n 8002ad2 + 800280e: 2b01 cmp r3, #1 + 8002810: d102 bne.n 8002818 + 8002812: f04f 7300 mov.w r3, #33554432 @ 0x2000000 + 8002816: e000 b.n 800281a + 8002818: 2300 movs r3, #0 + 800281a: 461a mov r2, r3 + 800281c: f7ff fa3a bl 8001c94 + 8002820: e17b b.n 8002b1a } else { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - 80027da: 687b ldr r3, [r7, #4] - 80027dc: 681b ldr r3, [r3, #0] - 80027de: 2100 movs r1, #0 - 80027e0: 4618 mov r0, r3 - 80027e2: f7ff f9e7 bl 8001bb4 - 80027e6: 4603 mov r3, r0 - 80027e8: f3c3 0312 ubfx r3, r3, #0, #19 - 80027ec: 2b00 cmp r3, #0 - 80027ee: d10a bne.n 8002806 - 80027f0: 687b ldr r3, [r7, #4] - 80027f2: 681b ldr r3, [r3, #0] - 80027f4: 2100 movs r1, #0 - 80027f6: 4618 mov r0, r3 - 80027f8: f7ff f9dc bl 8001bb4 - 80027fc: 4603 mov r3, r0 - 80027fe: 0e9b lsrs r3, r3, #26 - 8002800: f003 021f and.w r2, r3, #31 - 8002804: e01e b.n 8002844 - 8002806: 687b ldr r3, [r7, #4] - 8002808: 681b ldr r3, [r3, #0] - 800280a: 2100 movs r1, #0 - 800280c: 4618 mov r0, r3 - 800280e: f7ff f9d1 bl 8001bb4 - 8002812: 4603 mov r3, r0 - 8002814: f8c7 30bc str.w r3, [r7, #188] @ 0xbc + 8002822: 687b ldr r3, [r7, #4] + 8002824: 681b ldr r3, [r3, #0] + 8002826: 2100 movs r1, #0 + 8002828: 4618 mov r0, r3 + 800282a: f7ff f9e7 bl 8001bfc + 800282e: 4603 mov r3, r0 + 8002830: f3c3 0312 ubfx r3, r3, #0, #19 + 8002834: 2b00 cmp r3, #0 + 8002836: d10a bne.n 800284e + 8002838: 687b ldr r3, [r7, #4] + 800283a: 681b ldr r3, [r3, #0] + 800283c: 2100 movs r1, #0 + 800283e: 4618 mov r0, r3 + 8002840: f7ff f9dc bl 8001bfc + 8002844: 4603 mov r3, r0 + 8002846: 0e9b lsrs r3, r3, #26 + 8002848: f003 021f and.w r2, r3, #31 + 800284c: e01e b.n 800288c + 800284e: 687b ldr r3, [r7, #4] + 8002850: 681b ldr r3, [r3, #0] + 8002852: 2100 movs r1, #0 + 8002854: 4618 mov r0, r3 + 8002856: f7ff f9d1 bl 8001bfc + 800285a: 4603 mov r3, r0 + 800285c: f8c7 30bc str.w r3, [r7, #188] @ 0xbc uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002818: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc - 800281c: fa93 f3a3 rbit r3, r3 - 8002820: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8002860: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc + 8002864: fa93 f3a3 rbit r3, r3 + 8002868: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; - 8002824: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 - 8002828: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 800286c: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 + 8002870: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) - 800282c: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 - 8002830: 2b00 cmp r3, #0 - 8002832: d101 bne.n 8002838 + 8002874: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 + 8002878: 2b00 cmp r3, #0 + 800287a: d101 bne.n 8002880 { return 32U; - 8002834: 2320 movs r3, #32 - 8002836: e004 b.n 8002842 + 800287c: 2320 movs r3, #32 + 800287e: e004 b.n 800288a } return __builtin_clz(value); - 8002838: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 - 800283c: fab3 f383 clz r3, r3 - 8002840: b2db uxtb r3, r3 - 8002842: 461a mov r2, r3 + 8002880: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 + 8002884: fab3 f383 clz r3, r3 + 8002888: b2db uxtb r3, r3 + 800288a: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 8002844: 683b ldr r3, [r7, #0] - 8002846: 681b ldr r3, [r3, #0] - 8002848: f3c3 0312 ubfx r3, r3, #0, #19 - 800284c: 2b00 cmp r3, #0 - 800284e: d105 bne.n 800285c - 8002850: 683b ldr r3, [r7, #0] - 8002852: 681b ldr r3, [r3, #0] - 8002854: 0e9b lsrs r3, r3, #26 - 8002856: f003 031f and.w r3, r3, #31 - 800285a: e018 b.n 800288e - 800285c: 683b ldr r3, [r7, #0] - 800285e: 681b ldr r3, [r3, #0] - 8002860: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 800288c: 683b ldr r3, [r7, #0] + 800288e: 681b ldr r3, [r3, #0] + 8002890: f3c3 0312 ubfx r3, r3, #0, #19 + 8002894: 2b00 cmp r3, #0 + 8002896: d105 bne.n 80028a4 + 8002898: 683b ldr r3, [r7, #0] + 800289a: 681b ldr r3, [r3, #0] + 800289c: 0e9b lsrs r3, r3, #26 + 800289e: f003 031f and.w r3, r3, #31 + 80028a2: e018 b.n 80028d6 + 80028a4: 683b ldr r3, [r7, #0] + 80028a6: 681b ldr r3, [r3, #0] + 80028a8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002864: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 - 8002868: fa93 f3a3 rbit r3, r3 - 800286c: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 80028ac: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0 + 80028b0: fa93 f3a3 rbit r3, r3 + 80028b4: f8c7 30ac str.w r3, [r7, #172] @ 0xac return result; - 8002870: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 8002874: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 80028b8: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 80028bc: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 if (value == 0U) - 8002878: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 800287c: 2b00 cmp r3, #0 - 800287e: d101 bne.n 8002884 + 80028c0: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 80028c4: 2b00 cmp r3, #0 + 80028c6: d101 bne.n 80028cc return 32U; - 8002880: 2320 movs r3, #32 - 8002882: e004 b.n 800288e + 80028c8: 2320 movs r3, #32 + 80028ca: e004 b.n 80028d6 return __builtin_clz(value); - 8002884: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 8002888: fab3 f383 clz r3, r3 - 800288c: b2db uxtb r3, r3 + 80028cc: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 80028d0: fab3 f383 clz r3, r3 + 80028d4: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) - 800288e: 429a cmp r2, r3 - 8002890: d106 bne.n 80028a0 + 80028d6: 429a cmp r2, r3 + 80028d8: d106 bne.n 80028e8 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); - 8002892: 687b ldr r3, [r7, #4] - 8002894: 681b ldr r3, [r3, #0] - 8002896: 2200 movs r2, #0 - 8002898: 2100 movs r1, #0 - 800289a: 4618 mov r0, r3 - 800289c: f7ff f9a0 bl 8001be0 + 80028da: 687b ldr r3, [r7, #4] + 80028dc: 681b ldr r3, [r3, #0] + 80028de: 2200 movs r2, #0 + 80028e0: 2100 movs r1, #0 + 80028e2: 4618 mov r0, r3 + 80028e4: f7ff f9a0 bl 8001c28 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - 80028a0: 687b ldr r3, [r7, #4] - 80028a2: 681b ldr r3, [r3, #0] - 80028a4: 2101 movs r1, #1 - 80028a6: 4618 mov r0, r3 - 80028a8: f7ff f984 bl 8001bb4 - 80028ac: 4603 mov r3, r0 - 80028ae: f3c3 0312 ubfx r3, r3, #0, #19 - 80028b2: 2b00 cmp r3, #0 - 80028b4: d10a bne.n 80028cc - 80028b6: 687b ldr r3, [r7, #4] - 80028b8: 681b ldr r3, [r3, #0] - 80028ba: 2101 movs r1, #1 - 80028bc: 4618 mov r0, r3 - 80028be: f7ff f979 bl 8001bb4 - 80028c2: 4603 mov r3, r0 - 80028c4: 0e9b lsrs r3, r3, #26 - 80028c6: f003 021f and.w r2, r3, #31 - 80028ca: e01e b.n 800290a - 80028cc: 687b ldr r3, [r7, #4] - 80028ce: 681b ldr r3, [r3, #0] - 80028d0: 2101 movs r1, #1 - 80028d2: 4618 mov r0, r3 - 80028d4: f7ff f96e bl 8001bb4 - 80028d8: 4603 mov r3, r0 - 80028da: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + 80028e8: 687b ldr r3, [r7, #4] + 80028ea: 681b ldr r3, [r3, #0] + 80028ec: 2101 movs r1, #1 + 80028ee: 4618 mov r0, r3 + 80028f0: f7ff f984 bl 8001bfc + 80028f4: 4603 mov r3, r0 + 80028f6: f3c3 0312 ubfx r3, r3, #0, #19 + 80028fa: 2b00 cmp r3, #0 + 80028fc: d10a bne.n 8002914 + 80028fe: 687b ldr r3, [r7, #4] + 8002900: 681b ldr r3, [r3, #0] + 8002902: 2101 movs r1, #1 + 8002904: 4618 mov r0, r3 + 8002906: f7ff f979 bl 8001bfc + 800290a: 4603 mov r3, r0 + 800290c: 0e9b lsrs r3, r3, #26 + 800290e: f003 021f and.w r2, r3, #31 + 8002912: e01e b.n 8002952 + 8002914: 687b ldr r3, [r7, #4] + 8002916: 681b ldr r3, [r3, #0] + 8002918: 2101 movs r1, #1 + 800291a: 4618 mov r0, r3 + 800291c: f7ff f96e bl 8001bfc + 8002920: 4603 mov r3, r0 + 8002922: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80028de: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 - 80028e2: fa93 f3a3 rbit r3, r3 - 80028e6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + 8002926: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 + 800292a: fa93 f3a3 rbit r3, r3 + 800292e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return result; - 80028ea: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 - 80028ee: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + 8002932: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8002936: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 if (value == 0U) - 80028f2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 - 80028f6: 2b00 cmp r3, #0 - 80028f8: d101 bne.n 80028fe + 800293a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 800293e: 2b00 cmp r3, #0 + 8002940: d101 bne.n 8002946 return 32U; - 80028fa: 2320 movs r3, #32 - 80028fc: e004 b.n 8002908 + 8002942: 2320 movs r3, #32 + 8002944: e004 b.n 8002950 return __builtin_clz(value); - 80028fe: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 - 8002902: fab3 f383 clz r3, r3 - 8002906: b2db uxtb r3, r3 - 8002908: 461a mov r2, r3 + 8002946: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 800294a: fab3 f383 clz r3, r3 + 800294e: b2db uxtb r3, r3 + 8002950: 461a mov r2, r3 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 800290a: 683b ldr r3, [r7, #0] - 800290c: 681b ldr r3, [r3, #0] - 800290e: f3c3 0312 ubfx r3, r3, #0, #19 - 8002912: 2b00 cmp r3, #0 - 8002914: d105 bne.n 8002922 - 8002916: 683b ldr r3, [r7, #0] - 8002918: 681b ldr r3, [r3, #0] - 800291a: 0e9b lsrs r3, r3, #26 - 800291c: f003 031f and.w r3, r3, #31 - 8002920: e018 b.n 8002954 - 8002922: 683b ldr r3, [r7, #0] - 8002924: 681b ldr r3, [r3, #0] - 8002926: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8002952: 683b ldr r3, [r7, #0] + 8002954: 681b ldr r3, [r3, #0] + 8002956: f3c3 0312 ubfx r3, r3, #0, #19 + 800295a: 2b00 cmp r3, #0 + 800295c: d105 bne.n 800296a + 800295e: 683b ldr r3, [r7, #0] + 8002960: 681b ldr r3, [r3, #0] + 8002962: 0e9b lsrs r3, r3, #26 + 8002964: f003 031f and.w r3, r3, #31 + 8002968: e018 b.n 800299c + 800296a: 683b ldr r3, [r7, #0] + 800296c: 681b ldr r3, [r3, #0] + 800296e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 800292a: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 - 800292e: fa93 f3a3 rbit r3, r3 - 8002932: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8002972: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8002976: fa93 f3a3 rbit r3, r3 + 800297a: f8c7 3094 str.w r3, [r7, #148] @ 0x94 return result; - 8002936: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 - 800293a: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 800297e: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 + 8002982: f8c7 309c str.w r3, [r7, #156] @ 0x9c if (value == 0U) - 800293e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c - 8002942: 2b00 cmp r3, #0 - 8002944: d101 bne.n 800294a + 8002986: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 800298a: 2b00 cmp r3, #0 + 800298c: d101 bne.n 8002992 return 32U; - 8002946: 2320 movs r3, #32 - 8002948: e004 b.n 8002954 + 800298e: 2320 movs r3, #32 + 8002990: e004 b.n 800299c return __builtin_clz(value); - 800294a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c - 800294e: fab3 f383 clz r3, r3 - 8002952: b2db uxtb r3, r3 + 8002992: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 8002996: fab3 f383 clz r3, r3 + 800299a: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) - 8002954: 429a cmp r2, r3 - 8002956: d106 bne.n 8002966 + 800299c: 429a cmp r2, r3 + 800299e: d106 bne.n 80029ae { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); - 8002958: 687b ldr r3, [r7, #4] - 800295a: 681b ldr r3, [r3, #0] - 800295c: 2200 movs r2, #0 - 800295e: 2101 movs r1, #1 - 8002960: 4618 mov r0, r3 - 8002962: f7ff f93d bl 8001be0 + 80029a0: 687b ldr r3, [r7, #4] + 80029a2: 681b ldr r3, [r3, #0] + 80029a4: 2200 movs r2, #0 + 80029a6: 2101 movs r1, #1 + 80029a8: 4618 mov r0, r3 + 80029aa: f7ff f93d bl 8001c28 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - 8002966: 687b ldr r3, [r7, #4] - 8002968: 681b ldr r3, [r3, #0] - 800296a: 2102 movs r1, #2 - 800296c: 4618 mov r0, r3 - 800296e: f7ff f921 bl 8001bb4 - 8002972: 4603 mov r3, r0 - 8002974: f3c3 0312 ubfx r3, r3, #0, #19 - 8002978: 2b00 cmp r3, #0 - 800297a: d10a bne.n 8002992 - 800297c: 687b ldr r3, [r7, #4] - 800297e: 681b ldr r3, [r3, #0] - 8002980: 2102 movs r1, #2 - 8002982: 4618 mov r0, r3 - 8002984: f7ff f916 bl 8001bb4 - 8002988: 4603 mov r3, r0 - 800298a: 0e9b lsrs r3, r3, #26 - 800298c: f003 021f and.w r2, r3, #31 - 8002990: e01e b.n 80029d0 - 8002992: 687b ldr r3, [r7, #4] - 8002994: 681b ldr r3, [r3, #0] - 8002996: 2102 movs r1, #2 - 8002998: 4618 mov r0, r3 - 800299a: f7ff f90b bl 8001bb4 - 800299e: 4603 mov r3, r0 - 80029a0: f8c7 308c str.w r3, [r7, #140] @ 0x8c + 80029ae: 687b ldr r3, [r7, #4] + 80029b0: 681b ldr r3, [r3, #0] + 80029b2: 2102 movs r1, #2 + 80029b4: 4618 mov r0, r3 + 80029b6: f7ff f921 bl 8001bfc + 80029ba: 4603 mov r3, r0 + 80029bc: f3c3 0312 ubfx r3, r3, #0, #19 + 80029c0: 2b00 cmp r3, #0 + 80029c2: d10a bne.n 80029da + 80029c4: 687b ldr r3, [r7, #4] + 80029c6: 681b ldr r3, [r3, #0] + 80029c8: 2102 movs r1, #2 + 80029ca: 4618 mov r0, r3 + 80029cc: f7ff f916 bl 8001bfc + 80029d0: 4603 mov r3, r0 + 80029d2: 0e9b lsrs r3, r3, #26 + 80029d4: f003 021f and.w r2, r3, #31 + 80029d8: e01e b.n 8002a18 + 80029da: 687b ldr r3, [r7, #4] + 80029dc: 681b ldr r3, [r3, #0] + 80029de: 2102 movs r1, #2 + 80029e0: 4618 mov r0, r3 + 80029e2: f7ff f90b bl 8001bfc + 80029e6: 4603 mov r3, r0 + 80029e8: f8c7 308c str.w r3, [r7, #140] @ 0x8c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80029a4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c - 80029a8: fa93 f3a3 rbit r3, r3 - 80029ac: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 80029ec: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 80029f0: fa93 f3a3 rbit r3, r3 + 80029f4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 return result; - 80029b0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 - 80029b4: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 80029f8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 + 80029fc: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (value == 0U) - 80029b8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 - 80029bc: 2b00 cmp r3, #0 - 80029be: d101 bne.n 80029c4 - return 32U; - 80029c0: 2320 movs r3, #32 - 80029c2: e004 b.n 80029ce - return __builtin_clz(value); - 80029c4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 - 80029c8: fab3 f383 clz r3, r3 - 80029cc: b2db uxtb r3, r3 - 80029ce: 461a mov r2, r3 - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 80029d0: 683b ldr r3, [r7, #0] - 80029d2: 681b ldr r3, [r3, #0] - 80029d4: f3c3 0312 ubfx r3, r3, #0, #19 - 80029d8: 2b00 cmp r3, #0 - 80029da: d105 bne.n 80029e8 - 80029dc: 683b ldr r3, [r7, #0] - 80029de: 681b ldr r3, [r3, #0] - 80029e0: 0e9b lsrs r3, r3, #26 - 80029e2: f003 031f and.w r3, r3, #31 - 80029e6: e016 b.n 8002a16 - 80029e8: 683b ldr r3, [r7, #0] - 80029ea: 681b ldr r3, [r3, #0] - 80029ec: f8c7 3080 str.w r3, [r7, #128] @ 0x80 - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 80029f0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 - 80029f4: fa93 f3a3 rbit r3, r3 - 80029f8: 67fb str r3, [r7, #124] @ 0x7c - return result; - 80029fa: 6ffb ldr r3, [r7, #124] @ 0x7c - 80029fc: f8c7 3084 str.w r3, [r7, #132] @ 0x84 - if (value == 0U) - 8002a00: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8002a00: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8002a04: 2b00 cmp r3, #0 - 8002a06: d101 bne.n 8002a0c + 8002a06: d101 bne.n 8002a0c return 32U; 8002a08: 2320 movs r3, #32 - 8002a0a: e004 b.n 8002a16 + 8002a0a: e004 b.n 8002a16 return __builtin_clz(value); - 8002a0c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8002a0c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8002a10: fab3 f383 clz r3, r3 8002a14: b2db uxtb r3, r3 + 8002a16: 461a mov r2, r3 + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) + 8002a18: 683b ldr r3, [r7, #0] + 8002a1a: 681b ldr r3, [r3, #0] + 8002a1c: f3c3 0312 ubfx r3, r3, #0, #19 + 8002a20: 2b00 cmp r3, #0 + 8002a22: d105 bne.n 8002a30 + 8002a24: 683b ldr r3, [r7, #0] + 8002a26: 681b ldr r3, [r3, #0] + 8002a28: 0e9b lsrs r3, r3, #26 + 8002a2a: f003 031f and.w r3, r3, #31 + 8002a2e: e016 b.n 8002a5e + 8002a30: 683b ldr r3, [r7, #0] + 8002a32: 681b ldr r3, [r3, #0] + 8002a34: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8002a38: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 8002a3c: fa93 f3a3 rbit r3, r3 + 8002a40: 67fb str r3, [r7, #124] @ 0x7c + return result; + 8002a42: 6ffb ldr r3, [r7, #124] @ 0x7c + 8002a44: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + if (value == 0U) + 8002a48: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8002a4c: 2b00 cmp r3, #0 + 8002a4e: d101 bne.n 8002a54 + return 32U; + 8002a50: 2320 movs r3, #32 + 8002a52: e004 b.n 8002a5e + return __builtin_clz(value); + 8002a54: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8002a58: fab3 f383 clz r3, r3 + 8002a5c: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) - 8002a16: 429a cmp r2, r3 - 8002a18: d106 bne.n 8002a28 + 8002a5e: 429a cmp r2, r3 + 8002a60: d106 bne.n 8002a70 { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); - 8002a1a: 687b ldr r3, [r7, #4] - 8002a1c: 681b ldr r3, [r3, #0] - 8002a1e: 2200 movs r2, #0 - 8002a20: 2102 movs r1, #2 - 8002a22: 4618 mov r0, r3 - 8002a24: f7ff f8dc bl 8001be0 + 8002a62: 687b ldr r3, [r7, #4] + 8002a64: 681b ldr r3, [r3, #0] + 8002a66: 2200 movs r2, #0 + 8002a68: 2102 movs r1, #2 + 8002a6a: 4618 mov r0, r3 + 8002a6c: f7ff f8dc bl 8001c28 } if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - 8002a28: 687b ldr r3, [r7, #4] - 8002a2a: 681b ldr r3, [r3, #0] - 8002a2c: 2103 movs r1, #3 - 8002a2e: 4618 mov r0, r3 - 8002a30: f7ff f8c0 bl 8001bb4 - 8002a34: 4603 mov r3, r0 - 8002a36: f3c3 0312 ubfx r3, r3, #0, #19 - 8002a3a: 2b00 cmp r3, #0 - 8002a3c: d10a bne.n 8002a54 - 8002a3e: 687b ldr r3, [r7, #4] - 8002a40: 681b ldr r3, [r3, #0] - 8002a42: 2103 movs r1, #3 - 8002a44: 4618 mov r0, r3 - 8002a46: f7ff f8b5 bl 8001bb4 - 8002a4a: 4603 mov r3, r0 - 8002a4c: 0e9b lsrs r3, r3, #26 - 8002a4e: f003 021f and.w r2, r3, #31 - 8002a52: e017 b.n 8002a84 - 8002a54: 687b ldr r3, [r7, #4] - 8002a56: 681b ldr r3, [r3, #0] - 8002a58: 2103 movs r1, #3 - 8002a5a: 4618 mov r0, r3 - 8002a5c: f7ff f8aa bl 8001bb4 - 8002a60: 4603 mov r3, r0 - 8002a62: 677b str r3, [r7, #116] @ 0x74 - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002a64: 6f7b ldr r3, [r7, #116] @ 0x74 - 8002a66: fa93 f3a3 rbit r3, r3 - 8002a6a: 673b str r3, [r7, #112] @ 0x70 - return result; - 8002a6c: 6f3b ldr r3, [r7, #112] @ 0x70 - 8002a6e: 67bb str r3, [r7, #120] @ 0x78 - if (value == 0U) - 8002a70: 6fbb ldr r3, [r7, #120] @ 0x78 - 8002a72: 2b00 cmp r3, #0 - 8002a74: d101 bne.n 8002a7a - return 32U; - 8002a76: 2320 movs r3, #32 - 8002a78: e003 b.n 8002a82 - return __builtin_clz(value); - 8002a7a: 6fbb ldr r3, [r7, #120] @ 0x78 - 8002a7c: fab3 f383 clz r3, r3 - 8002a80: b2db uxtb r3, r3 - 8002a82: 461a mov r2, r3 - == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) - 8002a84: 683b ldr r3, [r7, #0] - 8002a86: 681b ldr r3, [r3, #0] - 8002a88: f3c3 0312 ubfx r3, r3, #0, #19 - 8002a8c: 2b00 cmp r3, #0 - 8002a8e: d105 bne.n 8002a9c - 8002a90: 683b ldr r3, [r7, #0] - 8002a92: 681b ldr r3, [r3, #0] + 8002a70: 687b ldr r3, [r7, #4] + 8002a72: 681b ldr r3, [r3, #0] + 8002a74: 2103 movs r1, #3 + 8002a76: 4618 mov r0, r3 + 8002a78: f7ff f8c0 bl 8001bfc + 8002a7c: 4603 mov r3, r0 + 8002a7e: f3c3 0312 ubfx r3, r3, #0, #19 + 8002a82: 2b00 cmp r3, #0 + 8002a84: d10a bne.n 8002a9c + 8002a86: 687b ldr r3, [r7, #4] + 8002a88: 681b ldr r3, [r3, #0] + 8002a8a: 2103 movs r1, #3 + 8002a8c: 4618 mov r0, r3 + 8002a8e: f7ff f8b5 bl 8001bfc + 8002a92: 4603 mov r3, r0 8002a94: 0e9b lsrs r3, r3, #26 - 8002a96: f003 031f and.w r3, r3, #31 - 8002a9a: e011 b.n 8002ac0 - 8002a9c: 683b ldr r3, [r7, #0] + 8002a96: f003 021f and.w r2, r3, #31 + 8002a9a: e017 b.n 8002acc + 8002a9c: 687b ldr r3, [r7, #4] 8002a9e: 681b ldr r3, [r3, #0] - 8002aa0: 66bb str r3, [r7, #104] @ 0x68 + 8002aa0: 2103 movs r1, #3 + 8002aa2: 4618 mov r0, r3 + 8002aa4: f7ff f8aa bl 8001bfc + 8002aa8: 4603 mov r3, r0 + 8002aaa: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002aa2: 6ebb ldr r3, [r7, #104] @ 0x68 - 8002aa4: fa93 f3a3 rbit r3, r3 - 8002aa8: 667b str r3, [r7, #100] @ 0x64 + 8002aac: 6f7b ldr r3, [r7, #116] @ 0x74 + 8002aae: fa93 f3a3 rbit r3, r3 + 8002ab2: 673b str r3, [r7, #112] @ 0x70 return result; - 8002aaa: 6e7b ldr r3, [r7, #100] @ 0x64 - 8002aac: 66fb str r3, [r7, #108] @ 0x6c + 8002ab4: 6f3b ldr r3, [r7, #112] @ 0x70 + 8002ab6: 67bb str r3, [r7, #120] @ 0x78 if (value == 0U) - 8002aae: 6efb ldr r3, [r7, #108] @ 0x6c - 8002ab0: 2b00 cmp r3, #0 - 8002ab2: d101 bne.n 8002ab8 + 8002ab8: 6fbb ldr r3, [r7, #120] @ 0x78 + 8002aba: 2b00 cmp r3, #0 + 8002abc: d101 bne.n 8002ac2 return 32U; - 8002ab4: 2320 movs r3, #32 - 8002ab6: e003 b.n 8002ac0 + 8002abe: 2320 movs r3, #32 + 8002ac0: e003 b.n 8002aca return __builtin_clz(value); - 8002ab8: 6efb ldr r3, [r7, #108] @ 0x6c - 8002aba: fab3 f383 clz r3, r3 - 8002abe: b2db uxtb r3, r3 + 8002ac2: 6fbb ldr r3, [r7, #120] @ 0x78 + 8002ac4: fab3 f383 clz r3, r3 + 8002ac8: b2db uxtb r3, r3 + 8002aca: 461a mov r2, r3 + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel)) + 8002acc: 683b ldr r3, [r7, #0] + 8002ace: 681b ldr r3, [r3, #0] + 8002ad0: f3c3 0312 ubfx r3, r3, #0, #19 + 8002ad4: 2b00 cmp r3, #0 + 8002ad6: d105 bne.n 8002ae4 + 8002ad8: 683b ldr r3, [r7, #0] + 8002ada: 681b ldr r3, [r3, #0] + 8002adc: 0e9b lsrs r3, r3, #26 + 8002ade: f003 031f and.w r3, r3, #31 + 8002ae2: e011 b.n 8002b08 + 8002ae4: 683b ldr r3, [r7, #0] + 8002ae6: 681b ldr r3, [r3, #0] + 8002ae8: 66bb str r3, [r7, #104] @ 0x68 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8002aea: 6ebb ldr r3, [r7, #104] @ 0x68 + 8002aec: fa93 f3a3 rbit r3, r3 + 8002af0: 667b str r3, [r7, #100] @ 0x64 + return result; + 8002af2: 6e7b ldr r3, [r7, #100] @ 0x64 + 8002af4: 66fb str r3, [r7, #108] @ 0x6c + if (value == 0U) + 8002af6: 6efb ldr r3, [r7, #108] @ 0x6c + 8002af8: 2b00 cmp r3, #0 + 8002afa: d101 bne.n 8002b00 + return 32U; + 8002afc: 2320 movs r3, #32 + 8002afe: e003 b.n 8002b08 + return __builtin_clz(value); + 8002b00: 6efb ldr r3, [r7, #108] @ 0x6c + 8002b02: fab3 f383 clz r3, r3 + 8002b06: b2db uxtb r3, r3 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) - 8002ac0: 429a cmp r2, r3 - 8002ac2: d106 bne.n 8002ad2 + 8002b08: 429a cmp r2, r3 + 8002b0a: d106 bne.n 8002b1a { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); - 8002ac4: 687b ldr r3, [r7, #4] - 8002ac6: 681b ldr r3, [r3, #0] - 8002ac8: 2200 movs r2, #0 - 8002aca: 2103 movs r1, #3 - 8002acc: 4618 mov r0, r3 - 8002ace: f7ff f887 bl 8001be0 + 8002b0c: 687b ldr r3, [r7, #4] + 8002b0e: 681b ldr r3, [r3, #0] + 8002b10: 2200 movs r2, #0 + 8002b12: 2103 movs r1, #3 + 8002b14: 4618 mov r0, r3 + 8002b16: f7ff f887 bl 8001c28 } /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8002ad2: 687b ldr r3, [r7, #4] - 8002ad4: 681b ldr r3, [r3, #0] - 8002ad6: 4618 mov r0, r3 - 8002ad8: f7ff fa06 bl 8001ee8 - 8002adc: 4603 mov r3, r0 - 8002ade: 2b00 cmp r3, #0 - 8002ae0: f040 8140 bne.w 8002d64 + 8002b1a: 687b ldr r3, [r7, #4] + 8002b1c: 681b ldr r3, [r3, #0] + 8002b1e: 4618 mov r0, r3 + 8002b20: f7ff fa06 bl 8001f30 + 8002b24: 4603 mov r3, r0 + 8002b26: 2b00 cmp r3, #0 + 8002b28: f040 8140 bne.w 8002dac { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff); - 8002ae4: 687b ldr r3, [r7, #4] - 8002ae6: 6818 ldr r0, [r3, #0] - 8002ae8: 683b ldr r3, [r7, #0] - 8002aea: 6819 ldr r1, [r3, #0] - 8002aec: 683b ldr r3, [r7, #0] - 8002aee: 68db ldr r3, [r3, #12] - 8002af0: 461a mov r2, r3 - 8002af2: f7ff f943 bl 8001d7c + 8002b2c: 687b ldr r3, [r7, #4] + 8002b2e: 6818 ldr r0, [r3, #0] + 8002b30: 683b ldr r3, [r7, #0] + 8002b32: 6819 ldr r1, [r3, #0] + 8002b34: 683b ldr r3, [r7, #0] + 8002b36: 68db ldr r3, [r3, #12] + 8002b38: 461a mov r2, r3 + 8002b3a: f7ff f943 bl 8001dc4 /* Configuration of differential mode */ if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) - 8002af6: 683b ldr r3, [r7, #0] - 8002af8: 68db ldr r3, [r3, #12] - 8002afa: 4a8f ldr r2, [pc, #572] @ (8002d38 ) - 8002afc: 4293 cmp r3, r2 - 8002afe: f040 8131 bne.w 8002d64 + 8002b3e: 683b ldr r3, [r7, #0] + 8002b40: 68db ldr r3, [r3, #12] + 8002b42: 4a8f ldr r2, [pc, #572] @ (8002d80 ) + 8002b44: 4293 cmp r3, r2 + 8002b46: f040 8131 bne.w 8002dac { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8002b02: 687b ldr r3, [r7, #4] - 8002b04: 6818 ldr r0, [r3, #0] + 8002b4a: 687b ldr r3, [r7, #4] + 8002b4c: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( - 8002b06: 683b ldr r3, [r7, #0] - 8002b08: 681b ldr r3, [r3, #0] - 8002b0a: f3c3 0312 ubfx r3, r3, #0, #19 - 8002b0e: 2b00 cmp r3, #0 - 8002b10: d10b bne.n 8002b2a - 8002b12: 683b ldr r3, [r7, #0] - 8002b14: 681b ldr r3, [r3, #0] - 8002b16: 0e9b lsrs r3, r3, #26 - 8002b18: 3301 adds r3, #1 - 8002b1a: f003 031f and.w r3, r3, #31 - 8002b1e: 2b09 cmp r3, #9 - 8002b20: bf94 ite ls - 8002b22: 2301 movls r3, #1 - 8002b24: 2300 movhi r3, #0 - 8002b26: b2db uxtb r3, r3 - 8002b28: e019 b.n 8002b5e - 8002b2a: 683b ldr r3, [r7, #0] - 8002b2c: 681b ldr r3, [r3, #0] - 8002b2e: 65fb str r3, [r7, #92] @ 0x5c + 8002b4e: 683b ldr r3, [r7, #0] + 8002b50: 681b ldr r3, [r3, #0] + 8002b52: f3c3 0312 ubfx r3, r3, #0, #19 + 8002b56: 2b00 cmp r3, #0 + 8002b58: d10b bne.n 8002b72 + 8002b5a: 683b ldr r3, [r7, #0] + 8002b5c: 681b ldr r3, [r3, #0] + 8002b5e: 0e9b lsrs r3, r3, #26 + 8002b60: 3301 adds r3, #1 + 8002b62: f003 031f and.w r3, r3, #31 + 8002b66: 2b09 cmp r3, #9 + 8002b68: bf94 ite ls + 8002b6a: 2301 movls r3, #1 + 8002b6c: 2300 movhi r3, #0 + 8002b6e: b2db uxtb r3, r3 + 8002b70: e019 b.n 8002ba6 + 8002b72: 683b ldr r3, [r7, #0] + 8002b74: 681b ldr r3, [r3, #0] + 8002b76: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002b30: 6dfb ldr r3, [r7, #92] @ 0x5c - 8002b32: fa93 f3a3 rbit r3, r3 - 8002b36: 65bb str r3, [r7, #88] @ 0x58 + 8002b78: 6dfb ldr r3, [r7, #92] @ 0x5c + 8002b7a: fa93 f3a3 rbit r3, r3 + 8002b7e: 65bb str r3, [r7, #88] @ 0x58 return result; - 8002b38: 6dbb ldr r3, [r7, #88] @ 0x58 - 8002b3a: 663b str r3, [r7, #96] @ 0x60 + 8002b80: 6dbb ldr r3, [r7, #88] @ 0x58 + 8002b82: 663b str r3, [r7, #96] @ 0x60 if (value == 0U) - 8002b3c: 6e3b ldr r3, [r7, #96] @ 0x60 - 8002b3e: 2b00 cmp r3, #0 - 8002b40: d101 bne.n 8002b46 + 8002b84: 6e3b ldr r3, [r7, #96] @ 0x60 + 8002b86: 2b00 cmp r3, #0 + 8002b88: d101 bne.n 8002b8e return 32U; - 8002b42: 2320 movs r3, #32 - 8002b44: e003 b.n 8002b4e + 8002b8a: 2320 movs r3, #32 + 8002b8c: e003 b.n 8002b96 return __builtin_clz(value); - 8002b46: 6e3b ldr r3, [r7, #96] @ 0x60 - 8002b48: fab3 f383 clz r3, r3 - 8002b4c: b2db uxtb r3, r3 - 8002b4e: 3301 adds r3, #1 - 8002b50: f003 031f and.w r3, r3, #31 - 8002b54: 2b09 cmp r3, #9 - 8002b56: bf94 ite ls - 8002b58: 2301 movls r3, #1 - 8002b5a: 2300 movhi r3, #0 - 8002b5c: b2db uxtb r3, r3 + 8002b8e: 6e3b ldr r3, [r7, #96] @ 0x60 + 8002b90: fab3 f383 clz r3, r3 + 8002b94: b2db uxtb r3, r3 + 8002b96: 3301 adds r3, #1 + 8002b98: f003 031f and.w r3, r3, #31 + 8002b9c: 2b09 cmp r3, #9 + 8002b9e: bf94 ite ls + 8002ba0: 2301 movls r3, #1 + 8002ba2: 2300 movhi r3, #0 + 8002ba4: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8002b5e: 2b00 cmp r3, #0 - 8002b60: d079 beq.n 8002c56 + 8002ba6: 2b00 cmp r3, #0 + 8002ba8: d079 beq.n 8002c9e (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( - 8002b62: 683b ldr r3, [r7, #0] - 8002b64: 681b ldr r3, [r3, #0] - 8002b66: f3c3 0312 ubfx r3, r3, #0, #19 - 8002b6a: 2b00 cmp r3, #0 - 8002b6c: d107 bne.n 8002b7e - 8002b6e: 683b ldr r3, [r7, #0] - 8002b70: 681b ldr r3, [r3, #0] - 8002b72: 0e9b lsrs r3, r3, #26 - 8002b74: 3301 adds r3, #1 - 8002b76: 069b lsls r3, r3, #26 - 8002b78: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8002b7c: e015 b.n 8002baa - 8002b7e: 683b ldr r3, [r7, #0] - 8002b80: 681b ldr r3, [r3, #0] - 8002b82: 653b str r3, [r7, #80] @ 0x50 - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002b84: 6d3b ldr r3, [r7, #80] @ 0x50 - 8002b86: fa93 f3a3 rbit r3, r3 - 8002b8a: 64fb str r3, [r7, #76] @ 0x4c - return result; - 8002b8c: 6cfb ldr r3, [r7, #76] @ 0x4c - 8002b8e: 657b str r3, [r7, #84] @ 0x54 - if (value == 0U) - 8002b90: 6d7b ldr r3, [r7, #84] @ 0x54 - 8002b92: 2b00 cmp r3, #0 - 8002b94: d101 bne.n 8002b9a - return 32U; - 8002b96: 2320 movs r3, #32 - 8002b98: e003 b.n 8002ba2 - return __builtin_clz(value); - 8002b9a: 6d7b ldr r3, [r7, #84] @ 0x54 - 8002b9c: fab3 f383 clz r3, r3 - 8002ba0: b2db uxtb r3, r3 - 8002ba2: 3301 adds r3, #1 - 8002ba4: 069b lsls r3, r3, #26 - 8002ba6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002baa: 683b ldr r3, [r7, #0] 8002bac: 681b ldr r3, [r3, #0] 8002bae: f3c3 0312 ubfx r3, r3, #0, #19 8002bb2: 2b00 cmp r3, #0 - 8002bb4: d109 bne.n 8002bca + 8002bb4: d107 bne.n 8002bc6 8002bb6: 683b ldr r3, [r7, #0] 8002bb8: 681b ldr r3, [r3, #0] 8002bba: 0e9b lsrs r3, r3, #26 8002bbc: 3301 adds r3, #1 - 8002bbe: f003 031f and.w r3, r3, #31 - 8002bc2: 2101 movs r1, #1 - 8002bc4: fa01 f303 lsl.w r3, r1, r3 - 8002bc8: e017 b.n 8002bfa - 8002bca: 683b ldr r3, [r7, #0] - 8002bcc: 681b ldr r3, [r3, #0] - 8002bce: 647b str r3, [r7, #68] @ 0x44 + 8002bbe: 069b lsls r3, r3, #26 + 8002bc0: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002bc4: e015 b.n 8002bf2 + 8002bc6: 683b ldr r3, [r7, #0] + 8002bc8: 681b ldr r3, [r3, #0] + 8002bca: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002bd0: 6c7b ldr r3, [r7, #68] @ 0x44 - 8002bd2: fa93 f3a3 rbit r3, r3 - 8002bd6: 643b str r3, [r7, #64] @ 0x40 + 8002bcc: 6d3b ldr r3, [r7, #80] @ 0x50 + 8002bce: fa93 f3a3 rbit r3, r3 + 8002bd2: 64fb str r3, [r7, #76] @ 0x4c return result; - 8002bd8: 6c3b ldr r3, [r7, #64] @ 0x40 - 8002bda: 64bb str r3, [r7, #72] @ 0x48 + 8002bd4: 6cfb ldr r3, [r7, #76] @ 0x4c + 8002bd6: 657b str r3, [r7, #84] @ 0x54 if (value == 0U) - 8002bdc: 6cbb ldr r3, [r7, #72] @ 0x48 - 8002bde: 2b00 cmp r3, #0 - 8002be0: d101 bne.n 8002be6 + 8002bd8: 6d7b ldr r3, [r7, #84] @ 0x54 + 8002bda: 2b00 cmp r3, #0 + 8002bdc: d101 bne.n 8002be2 return 32U; - 8002be2: 2320 movs r3, #32 - 8002be4: e003 b.n 8002bee + 8002bde: 2320 movs r3, #32 + 8002be0: e003 b.n 8002bea return __builtin_clz(value); - 8002be6: 6cbb ldr r3, [r7, #72] @ 0x48 - 8002be8: fab3 f383 clz r3, r3 - 8002bec: b2db uxtb r3, r3 - 8002bee: 3301 adds r3, #1 - 8002bf0: f003 031f and.w r3, r3, #31 - 8002bf4: 2101 movs r1, #1 - 8002bf6: fa01 f303 lsl.w r3, r1, r3 - 8002bfa: ea42 0103 orr.w r1, r2, r3 + 8002be2: 6d7b ldr r3, [r7, #84] @ 0x54 + 8002be4: fab3 f383 clz r3, r3 + 8002be8: b2db uxtb r3, r3 + 8002bea: 3301 adds r3, #1 + 8002bec: 069b lsls r3, r3, #26 + 8002bee: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002bf2: 683b ldr r3, [r7, #0] + 8002bf4: 681b ldr r3, [r3, #0] + 8002bf6: f3c3 0312 ubfx r3, r3, #0, #19 + 8002bfa: 2b00 cmp r3, #0 + 8002bfc: d109 bne.n 8002c12 8002bfe: 683b ldr r3, [r7, #0] 8002c00: 681b ldr r3, [r3, #0] - 8002c02: f3c3 0312 ubfx r3, r3, #0, #19 - 8002c06: 2b00 cmp r3, #0 - 8002c08: d10a bne.n 8002c20 - 8002c0a: 683b ldr r3, [r7, #0] - 8002c0c: 681b ldr r3, [r3, #0] - 8002c0e: 0e9b lsrs r3, r3, #26 - 8002c10: 3301 adds r3, #1 - 8002c12: f003 021f and.w r2, r3, #31 - 8002c16: 4613 mov r3, r2 - 8002c18: 005b lsls r3, r3, #1 - 8002c1a: 4413 add r3, r2 - 8002c1c: 051b lsls r3, r3, #20 - 8002c1e: e018 b.n 8002c52 - 8002c20: 683b ldr r3, [r7, #0] - 8002c22: 681b ldr r3, [r3, #0] - 8002c24: 63bb str r3, [r7, #56] @ 0x38 + 8002c02: 0e9b lsrs r3, r3, #26 + 8002c04: 3301 adds r3, #1 + 8002c06: f003 031f and.w r3, r3, #31 + 8002c0a: 2101 movs r1, #1 + 8002c0c: fa01 f303 lsl.w r3, r1, r3 + 8002c10: e017 b.n 8002c42 + 8002c12: 683b ldr r3, [r7, #0] + 8002c14: 681b ldr r3, [r3, #0] + 8002c16: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002c26: 6bbb ldr r3, [r7, #56] @ 0x38 - 8002c28: fa93 f3a3 rbit r3, r3 - 8002c2c: 637b str r3, [r7, #52] @ 0x34 + 8002c18: 6c7b ldr r3, [r7, #68] @ 0x44 + 8002c1a: fa93 f3a3 rbit r3, r3 + 8002c1e: 643b str r3, [r7, #64] @ 0x40 return result; - 8002c2e: 6b7b ldr r3, [r7, #52] @ 0x34 - 8002c30: 63fb str r3, [r7, #60] @ 0x3c + 8002c20: 6c3b ldr r3, [r7, #64] @ 0x40 + 8002c22: 64bb str r3, [r7, #72] @ 0x48 if (value == 0U) - 8002c32: 6bfb ldr r3, [r7, #60] @ 0x3c - 8002c34: 2b00 cmp r3, #0 - 8002c36: d101 bne.n 8002c3c + 8002c24: 6cbb ldr r3, [r7, #72] @ 0x48 + 8002c26: 2b00 cmp r3, #0 + 8002c28: d101 bne.n 8002c2e return 32U; - 8002c38: 2320 movs r3, #32 - 8002c3a: e003 b.n 8002c44 + 8002c2a: 2320 movs r3, #32 + 8002c2c: e003 b.n 8002c36 return __builtin_clz(value); - 8002c3c: 6bfb ldr r3, [r7, #60] @ 0x3c - 8002c3e: fab3 f383 clz r3, r3 - 8002c42: b2db uxtb r3, r3 - 8002c44: 3301 adds r3, #1 - 8002c46: f003 021f and.w r2, r3, #31 - 8002c4a: 4613 mov r3, r2 - 8002c4c: 005b lsls r3, r3, #1 - 8002c4e: 4413 add r3, r2 - 8002c50: 051b lsls r3, r3, #20 + 8002c2e: 6cbb ldr r3, [r7, #72] @ 0x48 + 8002c30: fab3 f383 clz r3, r3 + 8002c34: b2db uxtb r3, r3 + 8002c36: 3301 adds r3, #1 + 8002c38: f003 031f and.w r3, r3, #31 + 8002c3c: 2101 movs r1, #1 + 8002c3e: fa01 f303 lsl.w r3, r1, r3 + 8002c42: ea42 0103 orr.w r1, r2, r3 + 8002c46: 683b ldr r3, [r7, #0] + 8002c48: 681b ldr r3, [r3, #0] + 8002c4a: f3c3 0312 ubfx r3, r3, #0, #19 + 8002c4e: 2b00 cmp r3, #0 + 8002c50: d10a bne.n 8002c68 + 8002c52: 683b ldr r3, [r7, #0] + 8002c54: 681b ldr r3, [r3, #0] + 8002c56: 0e9b lsrs r3, r3, #26 + 8002c58: 3301 adds r3, #1 + 8002c5a: f003 021f and.w r2, r3, #31 + 8002c5e: 4613 mov r3, r2 + 8002c60: 005b lsls r3, r3, #1 + 8002c62: 4413 add r3, r2 + 8002c64: 051b lsls r3, r3, #20 + 8002c66: e018 b.n 8002c9a + 8002c68: 683b ldr r3, [r7, #0] + 8002c6a: 681b ldr r3, [r3, #0] + 8002c6c: 63bb str r3, [r7, #56] @ 0x38 + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8002c6e: 6bbb ldr r3, [r7, #56] @ 0x38 + 8002c70: fa93 f3a3 rbit r3, r3 + 8002c74: 637b str r3, [r7, #52] @ 0x34 + return result; + 8002c76: 6b7b ldr r3, [r7, #52] @ 0x34 + 8002c78: 63fb str r3, [r7, #60] @ 0x3c + if (value == 0U) + 8002c7a: 6bfb ldr r3, [r7, #60] @ 0x3c + 8002c7c: 2b00 cmp r3, #0 + 8002c7e: d101 bne.n 8002c84 + return 32U; + 8002c80: 2320 movs r3, #32 + 8002c82: e003 b.n 8002c8c + return __builtin_clz(value); + 8002c84: 6bfb ldr r3, [r7, #60] @ 0x3c + 8002c86: fab3 f383 clz r3, r3 + 8002c8a: b2db uxtb r3, r3 + 8002c8c: 3301 adds r3, #1 + 8002c8e: f003 021f and.w r2, r3, #31 + 8002c92: 4613 mov r3, r2 + 8002c94: 005b lsls r3, r3, #1 + 8002c96: 4413 add r3, r2 + 8002c98: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8002c52: 430b orrs r3, r1 - 8002c54: e081 b.n 8002d5a + 8002c9a: 430b orrs r3, r1 + 8002c9c: e081 b.n 8002da2 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL( - 8002c56: 683b ldr r3, [r7, #0] - 8002c58: 681b ldr r3, [r3, #0] - 8002c5a: f3c3 0312 ubfx r3, r3, #0, #19 - 8002c5e: 2b00 cmp r3, #0 - 8002c60: d107 bne.n 8002c72 - 8002c62: 683b ldr r3, [r7, #0] - 8002c64: 681b ldr r3, [r3, #0] - 8002c66: 0e9b lsrs r3, r3, #26 - 8002c68: 3301 adds r3, #1 - 8002c6a: 069b lsls r3, r3, #26 - 8002c6c: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 - 8002c70: e015 b.n 8002c9e - 8002c72: 683b ldr r3, [r7, #0] - 8002c74: 681b ldr r3, [r3, #0] - 8002c76: 62fb str r3, [r7, #44] @ 0x2c - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002c78: 6afb ldr r3, [r7, #44] @ 0x2c - 8002c7a: fa93 f3a3 rbit r3, r3 - 8002c7e: 62bb str r3, [r7, #40] @ 0x28 - return result; - 8002c80: 6abb ldr r3, [r7, #40] @ 0x28 - 8002c82: 633b str r3, [r7, #48] @ 0x30 - if (value == 0U) - 8002c84: 6b3b ldr r3, [r7, #48] @ 0x30 - 8002c86: 2b00 cmp r3, #0 - 8002c88: d101 bne.n 8002c8e - return 32U; - 8002c8a: 2320 movs r3, #32 - 8002c8c: e003 b.n 8002c96 - return __builtin_clz(value); - 8002c8e: 6b3b ldr r3, [r7, #48] @ 0x30 - 8002c90: fab3 f383 clz r3, r3 - 8002c94: b2db uxtb r3, r3 - 8002c96: 3301 adds r3, #1 - 8002c98: 069b lsls r3, r3, #26 - 8002c9a: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8002c9e: 683b ldr r3, [r7, #0] 8002ca0: 681b ldr r3, [r3, #0] 8002ca2: f3c3 0312 ubfx r3, r3, #0, #19 8002ca6: 2b00 cmp r3, #0 - 8002ca8: d109 bne.n 8002cbe + 8002ca8: d107 bne.n 8002cba 8002caa: 683b ldr r3, [r7, #0] 8002cac: 681b ldr r3, [r3, #0] 8002cae: 0e9b lsrs r3, r3, #26 8002cb0: 3301 adds r3, #1 - 8002cb2: f003 031f and.w r3, r3, #31 - 8002cb6: 2101 movs r1, #1 - 8002cb8: fa01 f303 lsl.w r3, r1, r3 - 8002cbc: e017 b.n 8002cee - 8002cbe: 683b ldr r3, [r7, #0] - 8002cc0: 681b ldr r3, [r3, #0] - 8002cc2: 623b str r3, [r7, #32] + 8002cb2: 069b lsls r3, r3, #26 + 8002cb4: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002cb8: e015 b.n 8002ce6 + 8002cba: 683b ldr r3, [r7, #0] + 8002cbc: 681b ldr r3, [r3, #0] + 8002cbe: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002cc4: 6a3b ldr r3, [r7, #32] - 8002cc6: fa93 f3a3 rbit r3, r3 - 8002cca: 61fb str r3, [r7, #28] + 8002cc0: 6afb ldr r3, [r7, #44] @ 0x2c + 8002cc2: fa93 f3a3 rbit r3, r3 + 8002cc6: 62bb str r3, [r7, #40] @ 0x28 return result; - 8002ccc: 69fb ldr r3, [r7, #28] - 8002cce: 627b str r3, [r7, #36] @ 0x24 + 8002cc8: 6abb ldr r3, [r7, #40] @ 0x28 + 8002cca: 633b str r3, [r7, #48] @ 0x30 if (value == 0U) - 8002cd0: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002cd2: 2b00 cmp r3, #0 - 8002cd4: d101 bne.n 8002cda + 8002ccc: 6b3b ldr r3, [r7, #48] @ 0x30 + 8002cce: 2b00 cmp r3, #0 + 8002cd0: d101 bne.n 8002cd6 return 32U; - 8002cd6: 2320 movs r3, #32 - 8002cd8: e003 b.n 8002ce2 + 8002cd2: 2320 movs r3, #32 + 8002cd4: e003 b.n 8002cde return __builtin_clz(value); - 8002cda: 6a7b ldr r3, [r7, #36] @ 0x24 - 8002cdc: fab3 f383 clz r3, r3 - 8002ce0: b2db uxtb r3, r3 - 8002ce2: 3301 adds r3, #1 - 8002ce4: f003 031f and.w r3, r3, #31 - 8002ce8: 2101 movs r1, #1 - 8002cea: fa01 f303 lsl.w r3, r1, r3 - 8002cee: ea42 0103 orr.w r1, r2, r3 + 8002cd6: 6b3b ldr r3, [r7, #48] @ 0x30 + 8002cd8: fab3 f383 clz r3, r3 + 8002cdc: b2db uxtb r3, r3 + 8002cde: 3301 adds r3, #1 + 8002ce0: 069b lsls r3, r3, #26 + 8002ce2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 + 8002ce6: 683b ldr r3, [r7, #0] + 8002ce8: 681b ldr r3, [r3, #0] + 8002cea: f3c3 0312 ubfx r3, r3, #0, #19 + 8002cee: 2b00 cmp r3, #0 + 8002cf0: d109 bne.n 8002d06 8002cf2: 683b ldr r3, [r7, #0] 8002cf4: 681b ldr r3, [r3, #0] - 8002cf6: f3c3 0312 ubfx r3, r3, #0, #19 - 8002cfa: 2b00 cmp r3, #0 - 8002cfc: d10d bne.n 8002d1a - 8002cfe: 683b ldr r3, [r7, #0] - 8002d00: 681b ldr r3, [r3, #0] - 8002d02: 0e9b lsrs r3, r3, #26 - 8002d04: 3301 adds r3, #1 - 8002d06: f003 021f and.w r2, r3, #31 - 8002d0a: 4613 mov r3, r2 - 8002d0c: 005b lsls r3, r3, #1 - 8002d0e: 4413 add r3, r2 - 8002d10: 3b1e subs r3, #30 - 8002d12: 051b lsls r3, r3, #20 - 8002d14: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 - 8002d18: e01e b.n 8002d58 - 8002d1a: 683b ldr r3, [r7, #0] - 8002d1c: 681b ldr r3, [r3, #0] - 8002d1e: 617b str r3, [r7, #20] + 8002cf6: 0e9b lsrs r3, r3, #26 + 8002cf8: 3301 adds r3, #1 + 8002cfa: f003 031f and.w r3, r3, #31 + 8002cfe: 2101 movs r1, #1 + 8002d00: fa01 f303 lsl.w r3, r1, r3 + 8002d04: e017 b.n 8002d36 + 8002d06: 683b ldr r3, [r7, #0] + 8002d08: 681b ldr r3, [r3, #0] + 8002d0a: 623b str r3, [r7, #32] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - 8002d20: 697b ldr r3, [r7, #20] - 8002d22: fa93 f3a3 rbit r3, r3 - 8002d26: 613b str r3, [r7, #16] + 8002d0c: 6a3b ldr r3, [r7, #32] + 8002d0e: fa93 f3a3 rbit r3, r3 + 8002d12: 61fb str r3, [r7, #28] return result; - 8002d28: 693b ldr r3, [r7, #16] - 8002d2a: 61bb str r3, [r7, #24] + 8002d14: 69fb ldr r3, [r7, #28] + 8002d16: 627b str r3, [r7, #36] @ 0x24 if (value == 0U) - 8002d2c: 69bb ldr r3, [r7, #24] - 8002d2e: 2b00 cmp r3, #0 - 8002d30: d104 bne.n 8002d3c + 8002d18: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d1a: 2b00 cmp r3, #0 + 8002d1c: d101 bne.n 8002d22 return 32U; - 8002d32: 2320 movs r3, #32 - 8002d34: e006 b.n 8002d44 - 8002d36: bf00 nop - 8002d38: 407f0000 .word 0x407f0000 + 8002d1e: 2320 movs r3, #32 + 8002d20: e003 b.n 8002d2a return __builtin_clz(value); - 8002d3c: 69bb ldr r3, [r7, #24] - 8002d3e: fab3 f383 clz r3, r3 - 8002d42: b2db uxtb r3, r3 - 8002d44: 3301 adds r3, #1 - 8002d46: f003 021f and.w r2, r3, #31 - 8002d4a: 4613 mov r3, r2 - 8002d4c: 005b lsls r3, r3, #1 - 8002d4e: 4413 add r3, r2 - 8002d50: 3b1e subs r3, #30 - 8002d52: 051b lsls r3, r3, #20 - 8002d54: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8002d22: 6a7b ldr r3, [r7, #36] @ 0x24 + 8002d24: fab3 f383 clz r3, r3 + 8002d28: b2db uxtb r3, r3 + 8002d2a: 3301 adds r3, #1 + 8002d2c: f003 031f and.w r3, r3, #31 + 8002d30: 2101 movs r1, #1 + 8002d32: fa01 f303 lsl.w r3, r1, r3 + 8002d36: ea42 0103 orr.w r1, r2, r3 + 8002d3a: 683b ldr r3, [r7, #0] + 8002d3c: 681b ldr r3, [r3, #0] + 8002d3e: f3c3 0312 ubfx r3, r3, #0, #19 + 8002d42: 2b00 cmp r3, #0 + 8002d44: d10d bne.n 8002d62 + 8002d46: 683b ldr r3, [r7, #0] + 8002d48: 681b ldr r3, [r3, #0] + 8002d4a: 0e9b lsrs r3, r3, #26 + 8002d4c: 3301 adds r3, #1 + 8002d4e: f003 021f and.w r2, r3, #31 + 8002d52: 4613 mov r3, r2 + 8002d54: 005b lsls r3, r3, #1 + 8002d56: 4413 add r3, r2 + 8002d58: 3b1e subs r3, #30 + 8002d5a: 051b lsls r3, r3, #20 + 8002d5c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 + 8002d60: e01e b.n 8002da0 + 8002d62: 683b ldr r3, [r7, #0] + 8002d64: 681b ldr r3, [r3, #0] + 8002d66: 617b str r3, [r7, #20] + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 8002d68: 697b ldr r3, [r7, #20] + 8002d6a: fa93 f3a3 rbit r3, r3 + 8002d6e: 613b str r3, [r7, #16] + return result; + 8002d70: 693b ldr r3, [r7, #16] + 8002d72: 61bb str r3, [r7, #24] + if (value == 0U) + 8002d74: 69bb ldr r3, [r7, #24] + 8002d76: 2b00 cmp r3, #0 + 8002d78: d104 bne.n 8002d84 + return 32U; + 8002d7a: 2320 movs r3, #32 + 8002d7c: e006 b.n 8002d8c + 8002d7e: bf00 nop + 8002d80: 407f0000 .word 0x407f0000 + return __builtin_clz(value); + 8002d84: 69bb ldr r3, [r7, #24] + 8002d86: fab3 f383 clz r3, r3 + 8002d8a: b2db uxtb r3, r3 + 8002d8c: 3301 adds r3, #1 + 8002d8e: f003 021f and.w r2, r3, #31 + 8002d92: 4613 mov r3, r2 + 8002d94: 005b lsls r3, r3, #1 + 8002d96: 4413 add r3, r2 + 8002d98: 3b1e subs r3, #30 + 8002d9a: 051b lsls r3, r3, #20 + 8002d9c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8002d58: 430b orrs r3, r1 + 8002da0: 430b orrs r3, r1 (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)), pConfig->SamplingTime); - 8002d5a: 683a ldr r2, [r7, #0] - 8002d5c: 6892 ldr r2, [r2, #8] + 8002da2: 683a ldr r2, [r7, #0] + 8002da4: 6892 ldr r2, [r2, #8] LL_ADC_SetChannelSamplingTime(hadc->Instance, - 8002d5e: 4619 mov r1, r3 - 8002d60: f7fe ffe1 bl 8001d26 + 8002da6: 4619 mov r1, r3 + 8002da8: f7fe ffe1 bl 8001d6e /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) - 8002d64: 683b ldr r3, [r7, #0] - 8002d66: 681a ldr r2, [r3, #0] - 8002d68: 4b3f ldr r3, [pc, #252] @ (8002e68 ) - 8002d6a: 4013 ands r3, r2 - 8002d6c: 2b00 cmp r3, #0 - 8002d6e: d071 beq.n 8002e54 + 8002dac: 683b ldr r3, [r7, #0] + 8002dae: 681a ldr r2, [r3, #0] + 8002db0: 4b3f ldr r3, [pc, #252] @ (8002eb0 ) + 8002db2: 4013 ands r3, r2 + 8002db4: 2b00 cmp r3, #0 + 8002db6: d071 beq.n 8002e9c { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - 8002d70: 483e ldr r0, [pc, #248] @ (8002e6c ) - 8002d72: f7fe feed bl 8001b50 - 8002d76: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4 + 8002db8: 483e ldr r0, [pc, #248] @ (8002eb4 ) + 8002dba: f7fe feed bl 8001b98 + 8002dbe: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4 /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5)) - 8002d7a: 683b ldr r3, [r7, #0] - 8002d7c: 681b ldr r3, [r3, #0] - 8002d7e: 4a3c ldr r2, [pc, #240] @ (8002e70 ) - 8002d80: 4293 cmp r3, r2 - 8002d82: d004 beq.n 8002d8e - 8002d84: 683b ldr r3, [r7, #0] - 8002d86: 681b ldr r3, [r3, #0] - 8002d88: 4a3a ldr r2, [pc, #232] @ (8002e74 ) - 8002d8a: 4293 cmp r3, r2 - 8002d8c: d127 bne.n 8002dde + 8002dc2: 683b ldr r3, [r7, #0] + 8002dc4: 681b ldr r3, [r3, #0] + 8002dc6: 4a3c ldr r2, [pc, #240] @ (8002eb8 ) + 8002dc8: 4293 cmp r3, r2 + 8002dca: d004 beq.n 8002dd6 + 8002dcc: 683b ldr r3, [r7, #0] + 8002dce: 681b ldr r3, [r3, #0] + 8002dd0: 4a3a ldr r2, [pc, #232] @ (8002ebc ) + 8002dd2: 4293 cmp r3, r2 + 8002dd4: d127 bne.n 8002e26 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) - 8002d8e: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 - 8002d92: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8002d96: 2b00 cmp r3, #0 - 8002d98: d121 bne.n 8002dde + 8002dd6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 8002dda: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8002dde: 2b00 cmp r3, #0 + 8002de0: d121 bne.n 8002e26 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - 8002d9a: 687b ldr r3, [r7, #4] - 8002d9c: 681b ldr r3, [r3, #0] - 8002d9e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 8002da2: d157 bne.n 8002e54 + 8002de2: 687b ldr r3, [r7, #4] + 8002de4: 681b ldr r3, [r3, #0] + 8002de6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 8002dea: d157 bne.n 8002e9c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - 8002da4: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 - 8002da8: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 - 8002dac: 4619 mov r1, r3 - 8002dae: 482f ldr r0, [pc, #188] @ (8002e6c ) - 8002db0: f7fe febb bl 8001b2a + 8002dec: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 8002df0: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 + 8002df4: 4619 mov r1, r3 + 8002df6: 482f ldr r0, [pc, #188] @ (8002eb4 ) + 8002df8: f7fe febb bl 8001b72 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 8002db4: 4b30 ldr r3, [pc, #192] @ (8002e78 ) - 8002db6: 681b ldr r3, [r3, #0] - 8002db8: 099b lsrs r3, r3, #6 - 8002dba: 4a30 ldr r2, [pc, #192] @ (8002e7c ) - 8002dbc: fba2 2303 umull r2, r3, r2, r3 - 8002dc0: 099b lsrs r3, r3, #6 - 8002dc2: 1c5a adds r2, r3, #1 - 8002dc4: 4613 mov r3, r2 - 8002dc6: 005b lsls r3, r3, #1 - 8002dc8: 4413 add r3, r2 - 8002dca: 009b lsls r3, r3, #2 - 8002dcc: 60fb str r3, [r7, #12] + 8002dfc: 4b30 ldr r3, [pc, #192] @ (8002ec0 ) + 8002dfe: 681b ldr r3, [r3, #0] + 8002e00: 099b lsrs r3, r3, #6 + 8002e02: 4a30 ldr r2, [pc, #192] @ (8002ec4 ) + 8002e04: fba2 2303 umull r2, r3, r2, r3 + 8002e08: 099b lsrs r3, r3, #6 + 8002e0a: 1c5a adds r2, r3, #1 + 8002e0c: 4613 mov r3, r2 + 8002e0e: 005b lsls r3, r3, #1 + 8002e10: 4413 add r3, r2 + 8002e12: 009b lsls r3, r3, #2 + 8002e14: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8002dce: e002 b.n 8002dd6 + 8002e16: e002 b.n 8002e1e { wait_loop_index--; - 8002dd0: 68fb ldr r3, [r7, #12] - 8002dd2: 3b01 subs r3, #1 - 8002dd4: 60fb str r3, [r7, #12] + 8002e18: 68fb ldr r3, [r7, #12] + 8002e1a: 3b01 subs r3, #1 + 8002e1c: 60fb str r3, [r7, #12] while (wait_loop_index != 0UL) - 8002dd6: 68fb ldr r3, [r7, #12] - 8002dd8: 2b00 cmp r3, #0 - 8002dda: d1f9 bne.n 8002dd0 + 8002e1e: 68fb ldr r3, [r7, #12] + 8002e20: 2b00 cmp r3, #0 + 8002e22: d1f9 bne.n 8002e18 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - 8002ddc: e03a b.n 8002e54 + 8002e24: e03a b.n 8002e9c } } } else if ((pConfig->Channel == ADC_CHANNEL_VBAT) - 8002dde: 683b ldr r3, [r7, #0] - 8002de0: 681b ldr r3, [r3, #0] - 8002de2: 4a27 ldr r2, [pc, #156] @ (8002e80 ) - 8002de4: 4293 cmp r3, r2 - 8002de6: d113 bne.n 8002e10 + 8002e26: 683b ldr r3, [r7, #0] + 8002e28: 681b ldr r3, [r3, #0] + 8002e2a: 4a27 ldr r2, [pc, #156] @ (8002ec8 ) + 8002e2c: 4293 cmp r3, r2 + 8002e2e: d113 bne.n 8002e58 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) - 8002de8: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 - 8002dec: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 - 8002df0: 2b00 cmp r3, #0 - 8002df2: d10d bne.n 8002e10 + 8002e30: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 8002e34: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8002e38: 2b00 cmp r3, #0 + 8002e3a: d10d bne.n 8002e58 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - 8002df4: 687b ldr r3, [r7, #4] - 8002df6: 681b ldr r3, [r3, #0] - 8002df8: 4a22 ldr r2, [pc, #136] @ (8002e84 ) - 8002dfa: 4293 cmp r3, r2 - 8002dfc: d02a beq.n 8002e54 + 8002e3c: 687b ldr r3, [r7, #4] + 8002e3e: 681b ldr r3, [r3, #0] + 8002e40: 4a22 ldr r2, [pc, #136] @ (8002ecc ) + 8002e42: 4293 cmp r3, r2 + 8002e44: d02a beq.n 8002e9c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - 8002dfe: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 - 8002e02: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 - 8002e06: 4619 mov r1, r3 - 8002e08: 4818 ldr r0, [pc, #96] @ (8002e6c ) - 8002e0a: f7fe fe8e bl 8001b2a + 8002e46: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 8002e4a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 8002e4e: 4619 mov r1, r3 + 8002e50: 4818 ldr r0, [pc, #96] @ (8002eb4 ) + 8002e52: f7fe fe8e bl 8001b72 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - 8002e0e: e021 b.n 8002e54 + 8002e56: e021 b.n 8002e9c LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) - 8002e10: 683b ldr r3, [r7, #0] - 8002e12: 681b ldr r3, [r3, #0] - 8002e14: 4a1c ldr r2, [pc, #112] @ (8002e88 ) - 8002e16: 4293 cmp r3, r2 - 8002e18: d11c bne.n 8002e54 + 8002e58: 683b ldr r3, [r7, #0] + 8002e5a: 681b ldr r3, [r3, #0] + 8002e5c: 4a1c ldr r2, [pc, #112] @ (8002ed0 ) + 8002e5e: 4293 cmp r3, r2 + 8002e60: d11c bne.n 8002e9c && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - 8002e1a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 - 8002e1e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8002e22: 2b00 cmp r3, #0 - 8002e24: d116 bne.n 8002e54 + 8002e62: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 8002e66: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8002e6a: 2b00 cmp r3, #0 + 8002e6c: d116 bne.n 8002e9c { if (ADC_VREFINT_INSTANCE(hadc)) - 8002e26: 687b ldr r3, [r7, #4] - 8002e28: 681b ldr r3, [r3, #0] - 8002e2a: 4a16 ldr r2, [pc, #88] @ (8002e84 ) - 8002e2c: 4293 cmp r3, r2 - 8002e2e: d011 beq.n 8002e54 + 8002e6e: 687b ldr r3, [r7, #4] + 8002e70: 681b ldr r3, [r3, #0] + 8002e72: 4a16 ldr r2, [pc, #88] @ (8002ecc ) + 8002e74: 4293 cmp r3, r2 + 8002e76: d011 beq.n 8002e9c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - 8002e30: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 - 8002e34: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 - 8002e38: 4619 mov r1, r3 - 8002e3a: 480c ldr r0, [pc, #48] @ (8002e6c ) - 8002e3c: f7fe fe75 bl 8001b2a - 8002e40: e008 b.n 8002e54 + 8002e78: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4 + 8002e7c: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 + 8002e80: 4619 mov r1, r3 + 8002e82: 480c ldr r0, [pc, #48] @ (8002eb4 ) + 8002e84: f7fe fe75 bl 8001b72 + 8002e88: e008 b.n 8002e9c /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8002e42: 687b ldr r3, [r7, #4] - 8002e44: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002e46: f043 0220 orr.w r2, r3, #32 - 8002e4a: 687b ldr r3, [r7, #4] - 8002e4c: 65da str r2, [r3, #92] @ 0x5c + 8002e8a: 687b ldr r3, [r7, #4] + 8002e8c: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002e8e: f043 0220 orr.w r2, r3, #32 + 8002e92: 687b ldr r3, [r7, #4] + 8002e94: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; - 8002e4e: 2301 movs r3, #1 - 8002e50: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 + 8002e96: 2301 movs r3, #1 + 8002e98: f887 30d7 strb.w r3, [r7, #215] @ 0xd7 } /* Process unlocked */ __HAL_UNLOCK(hadc); - 8002e54: 687b ldr r3, [r7, #4] - 8002e56: 2200 movs r2, #0 - 8002e58: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 8002e9c: 687b ldr r3, [r7, #4] + 8002e9e: 2200 movs r2, #0 + 8002ea0: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; - 8002e5c: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7 + 8002ea4: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7 } - 8002e60: 4618 mov r0, r3 - 8002e62: 37d8 adds r7, #216 @ 0xd8 - 8002e64: 46bd mov sp, r7 - 8002e66: bd80 pop {r7, pc} - 8002e68: 80080000 .word 0x80080000 - 8002e6c: 50000300 .word 0x50000300 - 8002e70: c3210000 .word 0xc3210000 - 8002e74: 90c00010 .word 0x90c00010 - 8002e78: 20000014 .word 0x20000014 - 8002e7c: 053e2d63 .word 0x053e2d63 - 8002e80: c7520000 .word 0xc7520000 - 8002e84: 50000100 .word 0x50000100 - 8002e88: cb840000 .word 0xcb840000 + 8002ea8: 4618 mov r0, r3 + 8002eaa: 37d8 adds r7, #216 @ 0xd8 + 8002eac: 46bd mov sp, r7 + 8002eae: bd80 pop {r7, pc} + 8002eb0: 80080000 .word 0x80080000 + 8002eb4: 50000300 .word 0x50000300 + 8002eb8: c3210000 .word 0xc3210000 + 8002ebc: 90c00010 .word 0x90c00010 + 8002ec0: 20000018 .word 0x20000018 + 8002ec4: 053e2d63 .word 0x053e2d63 + 8002ec8: c7520000 .word 0xc7520000 + 8002ecc: 50000100 .word 0x50000100 + 8002ed0: cb840000 .word 0xcb840000 -08002e8c : +08002ed4 : * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { - 8002e8c: b580 push {r7, lr} - 8002e8e: b088 sub sp, #32 - 8002e90: af00 add r7, sp, #0 - 8002e92: 6078 str r0, [r7, #4] - 8002e94: 6039 str r1, [r7, #0] + 8002ed4: b580 push {r7, lr} + 8002ed6: b088 sub sp, #32 + 8002ed8: af00 add r7, sp, #0 + 8002eda: 6078 str r0, [r7, #4] + 8002edc: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; - 8002e96: 2300 movs r3, #0 - 8002e98: 61fb str r3, [r7, #28] + 8002ede: 2300 movs r3, #0 + 8002ee0: 61fb str r3, [r7, #28] uint32_t conversion_group_reassigned = ConversionGroup; - 8002e9a: 683b ldr r3, [r7, #0] - 8002e9c: 61bb str r3, [r7, #24] + 8002ee2: 683b ldr r3, [r7, #0] + 8002ee4: 61bb str r3, [r7, #24] assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - 8002e9e: 687b ldr r3, [r7, #4] - 8002ea0: 681b ldr r3, [r3, #0] - 8002ea2: 4618 mov r0, r3 - 8002ea4: f7ff f86e bl 8001f84 - 8002ea8: 6138 str r0, [r7, #16] + 8002ee6: 687b ldr r3, [r7, #4] + 8002ee8: 681b ldr r3, [r3, #0] + 8002eea: 4618 mov r0, r3 + 8002eec: f7ff f86e bl 8001fcc + 8002ef0: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - 8002eaa: 687b ldr r3, [r7, #4] - 8002eac: 681b ldr r3, [r3, #0] - 8002eae: 4618 mov r0, r3 - 8002eb0: f7ff f88f bl 8001fd2 - 8002eb4: 60f8 str r0, [r7, #12] + 8002ef2: 687b ldr r3, [r7, #4] + 8002ef4: 681b ldr r3, [r3, #0] + 8002ef6: 4618 mov r0, r3 + 8002ef8: f7ff f88f bl 800201a + 8002efc: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular != 0UL) - 8002eb6: 693b ldr r3, [r7, #16] - 8002eb8: 2b00 cmp r3, #0 - 8002eba: d103 bne.n 8002ec4 + 8002efe: 693b ldr r3, [r7, #16] + 8002f00: 2b00 cmp r3, #0 + 8002f02: d103 bne.n 8002f0c || (tmp_adc_is_conversion_on_going_injected != 0UL) - 8002ebc: 68fb ldr r3, [r7, #12] - 8002ebe: 2b00 cmp r3, #0 - 8002ec0: f000 8098 beq.w 8002ff4 + 8002f04: 68fb ldr r3, [r7, #12] + 8002f06: 2b00 cmp r3, #0 + 8002f08: f000 8098 beq.w 800303c /* auto-delay mode. */ /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) - 8002ec4: 687b ldr r3, [r7, #4] - 8002ec6: 681b ldr r3, [r3, #0] - 8002ec8: 68db ldr r3, [r3, #12] - 8002eca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8002ece: 2b00 cmp r3, #0 - 8002ed0: d02a beq.n 8002f28 + 8002f0c: 687b ldr r3, [r7, #4] + 8002f0e: 681b ldr r3, [r3, #0] + 8002f10: 68db ldr r3, [r3, #12] + 8002f12: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8002f16: 2b00 cmp r3, #0 + 8002f18: d02a beq.n 8002f70 && (hadc->Init.ContinuousConvMode == ENABLE) - 8002ed2: 687b ldr r3, [r7, #4] - 8002ed4: 7f5b ldrb r3, [r3, #29] - 8002ed6: 2b01 cmp r3, #1 - 8002ed8: d126 bne.n 8002f28 + 8002f1a: 687b ldr r3, [r7, #4] + 8002f1c: 7f5b ldrb r3, [r3, #29] + 8002f1e: 2b01 cmp r3, #1 + 8002f20: d126 bne.n 8002f70 && (hadc->Init.LowPowerAutoWait == ENABLE) - 8002eda: 687b ldr r3, [r7, #4] - 8002edc: 7f1b ldrb r3, [r3, #28] - 8002ede: 2b01 cmp r3, #1 - 8002ee0: d122 bne.n 8002f28 + 8002f22: 687b ldr r3, [r7, #4] + 8002f24: 7f1b ldrb r3, [r3, #28] + 8002f26: 2b01 cmp r3, #1 + 8002f28: d122 bne.n 8002f70 ) { /* Use stop of regular group */ conversion_group_reassigned = ADC_REGULAR_GROUP; - 8002ee2: 2301 movs r3, #1 - 8002ee4: 61bb str r3, [r7, #24] + 8002f2a: 2301 movs r3, #1 + 8002f2c: 61bb str r3, [r7, #24] /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) - 8002ee6: e014 b.n 8002f12 + 8002f2e: e014 b.n 8002f5a { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) - 8002ee8: 69fb ldr r3, [r7, #28] - 8002eea: 4a45 ldr r2, [pc, #276] @ (8003000 ) - 8002eec: 4293 cmp r3, r2 - 8002eee: d90d bls.n 8002f0c + 8002f30: 69fb ldr r3, [r7, #28] + 8002f32: 4a45 ldr r2, [pc, #276] @ (8003048 ) + 8002f34: 4293 cmp r3, r2 + 8002f36: d90d bls.n 8002f54 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8002ef0: 687b ldr r3, [r7, #4] - 8002ef2: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002ef4: f043 0210 orr.w r2, r3, #16 - 8002ef8: 687b ldr r3, [r7, #4] - 8002efa: 65da str r2, [r3, #92] @ 0x5c + 8002f38: 687b ldr r3, [r7, #4] + 8002f3a: 6ddb ldr r3, [r3, #92] @ 0x5c + 8002f3c: f043 0210 orr.w r2, r3, #16 + 8002f40: 687b ldr r3, [r7, #4] + 8002f42: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8002efc: 687b ldr r3, [r7, #4] - 8002efe: 6e1b ldr r3, [r3, #96] @ 0x60 - 8002f00: f043 0201 orr.w r2, r3, #1 - 8002f04: 687b ldr r3, [r7, #4] - 8002f06: 661a str r2, [r3, #96] @ 0x60 + 8002f44: 687b ldr r3, [r7, #4] + 8002f46: 6e1b ldr r3, [r3, #96] @ 0x60 + 8002f48: f043 0201 orr.w r2, r3, #1 + 8002f4c: 687b ldr r3, [r7, #4] + 8002f4e: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; - 8002f08: 2301 movs r3, #1 - 8002f0a: e074 b.n 8002ff6 + 8002f50: 2301 movs r3, #1 + 8002f52: e074 b.n 800303e } Conversion_Timeout_CPU_cycles ++; - 8002f0c: 69fb ldr r3, [r7, #28] - 8002f0e: 3301 adds r3, #1 - 8002f10: 61fb str r3, [r7, #28] + 8002f54: 69fb ldr r3, [r7, #28] + 8002f56: 3301 adds r3, #1 + 8002f58: 61fb str r3, [r7, #28] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) - 8002f12: 687b ldr r3, [r7, #4] - 8002f14: 681b ldr r3, [r3, #0] - 8002f16: 681b ldr r3, [r3, #0] - 8002f18: f003 0340 and.w r3, r3, #64 @ 0x40 - 8002f1c: 2b40 cmp r3, #64 @ 0x40 - 8002f1e: d1e3 bne.n 8002ee8 + 8002f5a: 687b ldr r3, [r7, #4] + 8002f5c: 681b ldr r3, [r3, #0] + 8002f5e: 681b ldr r3, [r3, #0] + 8002f60: f003 0340 and.w r3, r3, #64 @ 0x40 + 8002f64: 2b40 cmp r3, #64 @ 0x40 + 8002f66: d1e3 bne.n 8002f30 } /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); - 8002f20: 687b ldr r3, [r7, #4] - 8002f22: 681b ldr r3, [r3, #0] - 8002f24: 2240 movs r2, #64 @ 0x40 - 8002f26: 601a str r2, [r3, #0] + 8002f68: 687b ldr r3, [r7, #4] + 8002f6a: 681b ldr r3, [r3, #0] + 8002f6c: 2240 movs r2, #64 @ 0x40 + 8002f6e: 601a str r2, [r3, #0] } /* Stop potential conversion on going on ADC group regular */ if (conversion_group_reassigned != ADC_INJECTED_GROUP) - 8002f28: 69bb ldr r3, [r7, #24] - 8002f2a: 2b02 cmp r3, #2 - 8002f2c: d014 beq.n 8002f58 + 8002f70: 69bb ldr r3, [r7, #24] + 8002f72: 2b02 cmp r3, #2 + 8002f74: d014 beq.n 8002fa0 { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) - 8002f2e: 687b ldr r3, [r7, #4] - 8002f30: 681b ldr r3, [r3, #0] - 8002f32: 4618 mov r0, r3 - 8002f34: f7ff f826 bl 8001f84 - 8002f38: 4603 mov r3, r0 - 8002f3a: 2b00 cmp r3, #0 - 8002f3c: d00c beq.n 8002f58 + 8002f76: 687b ldr r3, [r7, #4] + 8002f78: 681b ldr r3, [r3, #0] + 8002f7a: 4618 mov r0, r3 + 8002f7c: f7ff f826 bl 8001fcc + 8002f80: 4603 mov r3, r0 + 8002f82: 2b00 cmp r3, #0 + 8002f84: d00c beq.n 8002fa0 { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) - 8002f3e: 687b ldr r3, [r7, #4] - 8002f40: 681b ldr r3, [r3, #0] - 8002f42: 4618 mov r0, r3 - 8002f44: f7fe ffe3 bl 8001f0e - 8002f48: 4603 mov r3, r0 - 8002f4a: 2b00 cmp r3, #0 - 8002f4c: d104 bne.n 8002f58 + 8002f86: 687b ldr r3, [r7, #4] + 8002f88: 681b ldr r3, [r3, #0] + 8002f8a: 4618 mov r0, r3 + 8002f8c: f7fe ffe3 bl 8001f56 + 8002f90: 4603 mov r3, r0 + 8002f92: 2b00 cmp r3, #0 + 8002f94: d104 bne.n 8002fa0 { /* Stop ADC group regular conversion */ LL_ADC_REG_StopConversion(hadc->Instance); - 8002f4e: 687b ldr r3, [r7, #4] - 8002f50: 681b ldr r3, [r3, #0] - 8002f52: 4618 mov r0, r3 - 8002f54: f7ff f802 bl 8001f5c + 8002f96: 687b ldr r3, [r7, #4] + 8002f98: 681b ldr r3, [r3, #0] + 8002f9a: 4618 mov r0, r3 + 8002f9c: f7ff f802 bl 8001fa4 } } } /* Stop potential conversion on going on ADC group injected */ if (conversion_group_reassigned != ADC_REGULAR_GROUP) - 8002f58: 69bb ldr r3, [r7, #24] - 8002f5a: 2b01 cmp r3, #1 - 8002f5c: d014 beq.n 8002f88 + 8002fa0: 69bb ldr r3, [r7, #24] + 8002fa2: 2b01 cmp r3, #1 + 8002fa4: d014 beq.n 8002fd0 { /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) - 8002f5e: 687b ldr r3, [r7, #4] - 8002f60: 681b ldr r3, [r3, #0] - 8002f62: 4618 mov r0, r3 - 8002f64: f7ff f835 bl 8001fd2 - 8002f68: 4603 mov r3, r0 - 8002f6a: 2b00 cmp r3, #0 - 8002f6c: d00c beq.n 8002f88 + 8002fa6: 687b ldr r3, [r7, #4] + 8002fa8: 681b ldr r3, [r3, #0] + 8002faa: 4618 mov r0, r3 + 8002fac: f7ff f835 bl 800201a + 8002fb0: 4603 mov r3, r0 + 8002fb2: 2b00 cmp r3, #0 + 8002fb4: d00c beq.n 8002fd0 { if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) - 8002f6e: 687b ldr r3, [r7, #4] - 8002f70: 681b ldr r3, [r3, #0] - 8002f72: 4618 mov r0, r3 - 8002f74: f7fe ffcb bl 8001f0e - 8002f78: 4603 mov r3, r0 - 8002f7a: 2b00 cmp r3, #0 - 8002f7c: d104 bne.n 8002f88 + 8002fb6: 687b ldr r3, [r7, #4] + 8002fb8: 681b ldr r3, [r3, #0] + 8002fba: 4618 mov r0, r3 + 8002fbc: f7fe ffcb bl 8001f56 + 8002fc0: 4603 mov r3, r0 + 8002fc2: 2b00 cmp r3, #0 + 8002fc4: d104 bne.n 8002fd0 { /* Stop ADC group injected conversion */ LL_ADC_INJ_StopConversion(hadc->Instance); - 8002f7e: 687b ldr r3, [r7, #4] - 8002f80: 681b ldr r3, [r3, #0] - 8002f82: 4618 mov r0, r3 - 8002f84: f7ff f811 bl 8001faa + 8002fc6: 687b ldr r3, [r7, #4] + 8002fc8: 681b ldr r3, [r3, #0] + 8002fca: 4618 mov r0, r3 + 8002fcc: f7ff f811 bl 8001ff2 } } } /* Selection of start and stop bits with respect to the regular or injected group */ switch (conversion_group_reassigned) - 8002f88: 69bb ldr r3, [r7, #24] - 8002f8a: 2b02 cmp r3, #2 - 8002f8c: d005 beq.n 8002f9a - 8002f8e: 69bb ldr r3, [r7, #24] - 8002f90: 2b03 cmp r3, #3 - 8002f92: d105 bne.n 8002fa0 + 8002fd0: 69bb ldr r3, [r7, #24] + 8002fd2: 2b02 cmp r3, #2 + 8002fd4: d005 beq.n 8002fe2 + 8002fd6: 69bb ldr r3, [r7, #24] + 8002fd8: 2b03 cmp r3, #3 + 8002fda: d105 bne.n 8002fe8 { case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); - 8002f94: 230c movs r3, #12 - 8002f96: 617b str r3, [r7, #20] + 8002fdc: 230c movs r3, #12 + 8002fde: 617b str r3, [r7, #20] break; - 8002f98: e005 b.n 8002fa6 + 8002fe0: e005 b.n 8002fee case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; - 8002f9a: 2308 movs r3, #8 - 8002f9c: 617b str r3, [r7, #20] + 8002fe2: 2308 movs r3, #8 + 8002fe4: 617b str r3, [r7, #20] break; - 8002f9e: e002 b.n 8002fa6 + 8002fe6: e002 b.n 8002fee /* Case ADC_REGULAR_GROUP only*/ default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; - 8002fa0: 2304 movs r3, #4 - 8002fa2: 617b str r3, [r7, #20] + 8002fe8: 2304 movs r3, #4 + 8002fea: 617b str r3, [r7, #20] break; - 8002fa4: bf00 nop + 8002fec: bf00 nop } /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); - 8002fa6: f7fe fda1 bl 8001aec - 8002faa: 60b8 str r0, [r7, #8] + 8002fee: f7fe fda1 bl 8001b34 + 8002ff2: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) - 8002fac: e01b b.n 8002fe6 + 8002ff4: e01b b.n 800302e { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) - 8002fae: f7fe fd9d bl 8001aec - 8002fb2: 4602 mov r2, r0 - 8002fb4: 68bb ldr r3, [r7, #8] - 8002fb6: 1ad3 subs r3, r2, r3 - 8002fb8: 2b05 cmp r3, #5 - 8002fba: d914 bls.n 8002fe6 + 8002ff6: f7fe fd9d bl 8001b34 + 8002ffa: 4602 mov r2, r0 + 8002ffc: 68bb ldr r3, [r7, #8] + 8002ffe: 1ad3 subs r3, r2, r3 + 8003000: 2b05 cmp r3, #5 + 8003002: d914 bls.n 800302e { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) - 8002fbc: 687b ldr r3, [r7, #4] - 8002fbe: 681b ldr r3, [r3, #0] - 8002fc0: 689a ldr r2, [r3, #8] - 8002fc2: 697b ldr r3, [r7, #20] - 8002fc4: 4013 ands r3, r2 - 8002fc6: 2b00 cmp r3, #0 - 8002fc8: d00d beq.n 8002fe6 + 8003004: 687b ldr r3, [r7, #4] + 8003006: 681b ldr r3, [r3, #0] + 8003008: 689a ldr r2, [r3, #8] + 800300a: 697b ldr r3, [r7, #20] + 800300c: 4013 ands r3, r2 + 800300e: 2b00 cmp r3, #0 + 8003010: d00d beq.n 800302e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8002fca: 687b ldr r3, [r7, #4] - 8002fcc: 6ddb ldr r3, [r3, #92] @ 0x5c - 8002fce: f043 0210 orr.w r2, r3, #16 - 8002fd2: 687b ldr r3, [r7, #4] - 8002fd4: 65da str r2, [r3, #92] @ 0x5c + 8003012: 687b ldr r3, [r7, #4] + 8003014: 6ddb ldr r3, [r3, #92] @ 0x5c + 8003016: f043 0210 orr.w r2, r3, #16 + 800301a: 687b ldr r3, [r7, #4] + 800301c: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 8002fd6: 687b ldr r3, [r7, #4] - 8002fd8: 6e1b ldr r3, [r3, #96] @ 0x60 - 8002fda: f043 0201 orr.w r2, r3, #1 - 8002fde: 687b ldr r3, [r7, #4] - 8002fe0: 661a str r2, [r3, #96] @ 0x60 + 800301e: 687b ldr r3, [r7, #4] + 8003020: 6e1b ldr r3, [r3, #96] @ 0x60 + 8003022: f043 0201 orr.w r2, r3, #1 + 8003026: 687b ldr r3, [r7, #4] + 8003028: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; - 8002fe2: 2301 movs r3, #1 - 8002fe4: e007 b.n 8002ff6 + 800302a: 2301 movs r3, #1 + 800302c: e007 b.n 800303e while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) - 8002fe6: 687b ldr r3, [r7, #4] - 8002fe8: 681b ldr r3, [r3, #0] - 8002fea: 689a ldr r2, [r3, #8] - 8002fec: 697b ldr r3, [r7, #20] - 8002fee: 4013 ands r3, r2 - 8002ff0: 2b00 cmp r3, #0 - 8002ff2: d1dc bne.n 8002fae + 800302e: 687b ldr r3, [r7, #4] + 8003030: 681b ldr r3, [r3, #0] + 8003032: 689a ldr r2, [r3, #8] + 8003034: 697b ldr r3, [r7, #20] + 8003036: 4013 ands r3, r2 + 8003038: 2b00 cmp r3, #0 + 800303a: d1dc bne.n 8002ff6 } } /* Return HAL status */ return HAL_OK; - 8002ff4: 2300 movs r3, #0 + 800303c: 2300 movs r3, #0 } - 8002ff6: 4618 mov r0, r3 - 8002ff8: 3720 adds r7, #32 - 8002ffa: 46bd mov sp, r7 - 8002ffc: bd80 pop {r7, pc} - 8002ffe: bf00 nop - 8003000: a33fffff .word 0xa33fffff + 800303e: 4618 mov r0, r3 + 8003040: 3720 adds r7, #32 + 8003042: 46bd mov sp, r7 + 8003044: bd80 pop {r7, pc} + 8003046: bf00 nop + 8003048: a33fffff .word 0xa33fffff -08003004 : +0800304c : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { - 8003004: b580 push {r7, lr} - 8003006: b084 sub sp, #16 - 8003008: af00 add r7, sp, #0 - 800300a: 6078 str r0, [r7, #4] + 800304c: b580 push {r7, lr} + 800304e: b084 sub sp, #16 + 8003050: af00 add r7, sp, #0 + 8003052: 6078 str r0, [r7, #4] uint32_t tickstart; __IO uint32_t wait_loop_index = 0UL; - 800300c: 2300 movs r3, #0 - 800300e: 60bb str r3, [r7, #8] + 8003054: 2300 movs r3, #0 + 8003056: 60bb str r3, [r7, #8] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8003010: 687b ldr r3, [r7, #4] - 8003012: 681b ldr r3, [r3, #0] - 8003014: 4618 mov r0, r3 - 8003016: f7fe ff67 bl 8001ee8 - 800301a: 4603 mov r3, r0 - 800301c: 2b00 cmp r3, #0 - 800301e: d169 bne.n 80030f4 + 8003058: 687b ldr r3, [r7, #4] + 800305a: 681b ldr r3, [r3, #0] + 800305c: 4618 mov r0, r3 + 800305e: f7fe ff67 bl 8001f30 + 8003062: 4603 mov r3, r0 + 8003064: 2b00 cmp r3, #0 + 8003066: d169 bne.n 800313c { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - 8003020: 687b ldr r3, [r7, #4] - 8003022: 681b ldr r3, [r3, #0] - 8003024: 689a ldr r2, [r3, #8] - 8003026: 4b36 ldr r3, [pc, #216] @ (8003100 ) - 8003028: 4013 ands r3, r2 - 800302a: 2b00 cmp r3, #0 - 800302c: d00d beq.n 800304a + 8003068: 687b ldr r3, [r7, #4] + 800306a: 681b ldr r3, [r3, #0] + 800306c: 689a ldr r2, [r3, #8] + 800306e: 4b36 ldr r3, [pc, #216] @ (8003148 ) + 8003070: 4013 ands r3, r2 + 8003072: 2b00 cmp r3, #0 + 8003074: d00d beq.n 8003092 | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 800302e: 687b ldr r3, [r7, #4] - 8003030: 6ddb ldr r3, [r3, #92] @ 0x5c - 8003032: f043 0210 orr.w r2, r3, #16 - 8003036: 687b ldr r3, [r7, #4] - 8003038: 65da str r2, [r3, #92] @ 0x5c + 8003076: 687b ldr r3, [r7, #4] + 8003078: 6ddb ldr r3, [r3, #92] @ 0x5c + 800307a: f043 0210 orr.w r2, r3, #16 + 800307e: 687b ldr r3, [r7, #4] + 8003080: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 800303a: 687b ldr r3, [r7, #4] - 800303c: 6e1b ldr r3, [r3, #96] @ 0x60 - 800303e: f043 0201 orr.w r2, r3, #1 - 8003042: 687b ldr r3, [r7, #4] - 8003044: 661a str r2, [r3, #96] @ 0x60 + 8003082: 687b ldr r3, [r7, #4] + 8003084: 6e1b ldr r3, [r3, #96] @ 0x60 + 8003086: f043 0201 orr.w r2, r3, #1 + 800308a: 687b ldr r3, [r7, #4] + 800308c: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; - 8003046: 2301 movs r3, #1 - 8003048: e055 b.n 80030f6 + 800308e: 2301 movs r3, #1 + 8003090: e055 b.n 800313e } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - 800304a: 687b ldr r3, [r7, #4] - 800304c: 681b ldr r3, [r3, #0] - 800304e: 4618 mov r0, r3 - 8003050: f7fe ff22 bl 8001e98 + 8003092: 687b ldr r3, [r7, #4] + 8003094: 681b ldr r3, [r3, #0] + 8003096: 4618 mov r0, r3 + 8003098: f7fe ff22 bl 8001ee0 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) - 8003054: 482b ldr r0, [pc, #172] @ (8003104 ) - 8003056: f7fe fd7b bl 8001b50 - 800305a: 4603 mov r3, r0 + 800309c: 482b ldr r0, [pc, #172] @ (800314c ) + 800309e: f7fe fd7b bl 8001b98 + 80030a2: 4603 mov r3, r0 & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) - 800305c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 80030a4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) - 8003060: 2b00 cmp r3, #0 - 8003062: d013 beq.n 800308c + 80030a8: 2b00 cmp r3, #0 + 80030aa: d013 beq.n 80030d4 /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - 8003064: 4b28 ldr r3, [pc, #160] @ (8003108 ) - 8003066: 681b ldr r3, [r3, #0] - 8003068: 099b lsrs r3, r3, #6 - 800306a: 4a28 ldr r2, [pc, #160] @ (800310c ) - 800306c: fba2 2303 umull r2, r3, r2, r3 - 8003070: 099b lsrs r3, r3, #6 - 8003072: 1c5a adds r2, r3, #1 - 8003074: 4613 mov r3, r2 - 8003076: 005b lsls r3, r3, #1 - 8003078: 4413 add r3, r2 - 800307a: 009b lsls r3, r3, #2 - 800307c: 60bb str r3, [r7, #8] + 80030ac: 4b28 ldr r3, [pc, #160] @ (8003150 ) + 80030ae: 681b ldr r3, [r3, #0] + 80030b0: 099b lsrs r3, r3, #6 + 80030b2: 4a28 ldr r2, [pc, #160] @ (8003154 ) + 80030b4: fba2 2303 umull r2, r3, r2, r3 + 80030b8: 099b lsrs r3, r3, #6 + 80030ba: 1c5a adds r2, r3, #1 + 80030bc: 4613 mov r3, r2 + 80030be: 005b lsls r3, r3, #1 + 80030c0: 4413 add r3, r2 + 80030c2: 009b lsls r3, r3, #2 + 80030c4: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) - 800307e: e002 b.n 8003086 + 80030c6: e002 b.n 80030ce { wait_loop_index--; - 8003080: 68bb ldr r3, [r7, #8] - 8003082: 3b01 subs r3, #1 - 8003084: 60bb str r3, [r7, #8] + 80030c8: 68bb ldr r3, [r7, #8] + 80030ca: 3b01 subs r3, #1 + 80030cc: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) - 8003086: 68bb ldr r3, [r7, #8] - 8003088: 2b00 cmp r3, #0 - 800308a: d1f9 bne.n 8003080 + 80030ce: 68bb ldr r3, [r7, #8] + 80030d0: 2b00 cmp r3, #0 + 80030d2: d1f9 bne.n 80030c8 } } /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - 800308c: f7fe fd2e bl 8001aec - 8003090: 60f8 str r0, [r7, #12] + 80030d4: f7fe fd2e bl 8001b34 + 80030d8: 60f8 str r0, [r7, #12] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - 8003092: e028 b.n 80030e6 + 80030da: e028 b.n 800312e The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - 8003094: 687b ldr r3, [r7, #4] - 8003096: 681b ldr r3, [r3, #0] - 8003098: 4618 mov r0, r3 - 800309a: f7fe ff25 bl 8001ee8 - 800309e: 4603 mov r3, r0 - 80030a0: 2b00 cmp r3, #0 - 80030a2: d104 bne.n 80030ae + 80030dc: 687b ldr r3, [r7, #4] + 80030de: 681b ldr r3, [r3, #0] + 80030e0: 4618 mov r0, r3 + 80030e2: f7fe ff25 bl 8001f30 + 80030e6: 4603 mov r3, r0 + 80030e8: 2b00 cmp r3, #0 + 80030ea: d104 bne.n 80030f6 { LL_ADC_Enable(hadc->Instance); - 80030a4: 687b ldr r3, [r7, #4] - 80030a6: 681b ldr r3, [r3, #0] - 80030a8: 4618 mov r0, r3 - 80030aa: f7fe fef5 bl 8001e98 + 80030ec: 687b ldr r3, [r7, #4] + 80030ee: 681b ldr r3, [r3, #0] + 80030f0: 4618 mov r0, r3 + 80030f2: f7fe fef5 bl 8001ee0 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - 80030ae: f7fe fd1d bl 8001aec - 80030b2: 4602 mov r2, r0 - 80030b4: 68fb ldr r3, [r7, #12] - 80030b6: 1ad3 subs r3, r2, r3 - 80030b8: 2b02 cmp r3, #2 - 80030ba: d914 bls.n 80030e6 + 80030f6: f7fe fd1d bl 8001b34 + 80030fa: 4602 mov r2, r0 + 80030fc: 68fb ldr r3, [r7, #12] + 80030fe: 1ad3 subs r3, r2, r3 + 8003100: 2b02 cmp r3, #2 + 8003102: d914 bls.n 800312e { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - 80030bc: 687b ldr r3, [r7, #4] - 80030be: 681b ldr r3, [r3, #0] - 80030c0: 681b ldr r3, [r3, #0] - 80030c2: f003 0301 and.w r3, r3, #1 - 80030c6: 2b01 cmp r3, #1 - 80030c8: d00d beq.n 80030e6 + 8003104: 687b ldr r3, [r7, #4] + 8003106: 681b ldr r3, [r3, #0] + 8003108: 681b ldr r3, [r3, #0] + 800310a: f003 0301 and.w r3, r3, #1 + 800310e: 2b01 cmp r3, #1 + 8003110: d00d beq.n 800312e { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 80030ca: 687b ldr r3, [r7, #4] - 80030cc: 6ddb ldr r3, [r3, #92] @ 0x5c - 80030ce: f043 0210 orr.w r2, r3, #16 - 80030d2: 687b ldr r3, [r7, #4] - 80030d4: 65da str r2, [r3, #92] @ 0x5c + 8003112: 687b ldr r3, [r7, #4] + 8003114: 6ddb ldr r3, [r3, #92] @ 0x5c + 8003116: f043 0210 orr.w r2, r3, #16 + 800311a: 687b ldr r3, [r7, #4] + 800311c: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80030d6: 687b ldr r3, [r7, #4] - 80030d8: 6e1b ldr r3, [r3, #96] @ 0x60 - 80030da: f043 0201 orr.w r2, r3, #1 - 80030de: 687b ldr r3, [r7, #4] - 80030e0: 661a str r2, [r3, #96] @ 0x60 + 800311e: 687b ldr r3, [r7, #4] + 8003120: 6e1b ldr r3, [r3, #96] @ 0x60 + 8003122: f043 0201 orr.w r2, r3, #1 + 8003126: 687b ldr r3, [r7, #4] + 8003128: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; - 80030e2: 2301 movs r3, #1 - 80030e4: e007 b.n 80030f6 + 800312a: 2301 movs r3, #1 + 800312c: e007 b.n 800313e while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - 80030e6: 687b ldr r3, [r7, #4] - 80030e8: 681b ldr r3, [r3, #0] - 80030ea: 681b ldr r3, [r3, #0] - 80030ec: f003 0301 and.w r3, r3, #1 - 80030f0: 2b01 cmp r3, #1 - 80030f2: d1cf bne.n 8003094 + 800312e: 687b ldr r3, [r7, #4] + 8003130: 681b ldr r3, [r3, #0] + 8003132: 681b ldr r3, [r3, #0] + 8003134: f003 0301 and.w r3, r3, #1 + 8003138: 2b01 cmp r3, #1 + 800313a: d1cf bne.n 80030dc } } } /* Return HAL status */ return HAL_OK; - 80030f4: 2300 movs r3, #0 + 800313c: 2300 movs r3, #0 } - 80030f6: 4618 mov r0, r3 - 80030f8: 3710 adds r7, #16 - 80030fa: 46bd mov sp, r7 - 80030fc: bd80 pop {r7, pc} - 80030fe: bf00 nop - 8003100: 8000003f .word 0x8000003f - 8003104: 50000300 .word 0x50000300 - 8003108: 20000014 .word 0x20000014 - 800310c: 053e2d63 .word 0x053e2d63 + 800313e: 4618 mov r0, r3 + 8003140: 3710 adds r7, #16 + 8003142: 46bd mov sp, r7 + 8003144: bd80 pop {r7, pc} + 8003146: bf00 nop + 8003148: 8000003f .word 0x8000003f + 800314c: 50000300 .word 0x50000300 + 8003150: 20000018 .word 0x20000018 + 8003154: 053e2d63 .word 0x053e2d63 -08003110 : +08003158 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { - 8003110: b580 push {r7, lr} - 8003112: b084 sub sp, #16 - 8003114: af00 add r7, sp, #0 - 8003116: 6078 str r0, [r7, #4] + 8003158: b580 push {r7, lr} + 800315a: b084 sub sp, #16 + 800315c: af00 add r7, sp, #0 + 800315e: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); - 8003118: 687b ldr r3, [r7, #4] - 800311a: 681b ldr r3, [r3, #0] - 800311c: 4618 mov r0, r3 - 800311e: f7fe fef6 bl 8001f0e - 8003122: 60f8 str r0, [r7, #12] + 8003160: 687b ldr r3, [r7, #4] + 8003162: 681b ldr r3, [r3, #0] + 8003164: 4618 mov r0, r3 + 8003166: f7fe fef6 bl 8001f56 + 800316a: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) - 8003124: 687b ldr r3, [r7, #4] - 8003126: 681b ldr r3, [r3, #0] - 8003128: 4618 mov r0, r3 - 800312a: f7fe fedd bl 8001ee8 - 800312e: 4603 mov r3, r0 - 8003130: 2b00 cmp r3, #0 - 8003132: d047 beq.n 80031c4 + 800316c: 687b ldr r3, [r7, #4] + 800316e: 681b ldr r3, [r3, #0] + 8003170: 4618 mov r0, r3 + 8003172: f7fe fedd bl 8001f30 + 8003176: 4603 mov r3, r0 + 8003178: 2b00 cmp r3, #0 + 800317a: d047 beq.n 800320c && (tmp_adc_is_disable_on_going == 0UL) - 8003134: 68fb ldr r3, [r7, #12] - 8003136: 2b00 cmp r3, #0 - 8003138: d144 bne.n 80031c4 + 800317c: 68fb ldr r3, [r7, #12] + 800317e: 2b00 cmp r3, #0 + 8003180: d144 bne.n 800320c ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) - 800313a: 687b ldr r3, [r7, #4] - 800313c: 681b ldr r3, [r3, #0] - 800313e: 689b ldr r3, [r3, #8] - 8003140: f003 030d and.w r3, r3, #13 - 8003144: 2b01 cmp r3, #1 - 8003146: d10c bne.n 8003162 + 8003182: 687b ldr r3, [r7, #4] + 8003184: 681b ldr r3, [r3, #0] + 8003186: 689b ldr r3, [r3, #8] + 8003188: f003 030d and.w r3, r3, #13 + 800318c: 2b01 cmp r3, #1 + 800318e: d10c bne.n 80031aa { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); - 8003148: 687b ldr r3, [r7, #4] - 800314a: 681b ldr r3, [r3, #0] - 800314c: 4618 mov r0, r3 - 800314e: f7fe feb7 bl 8001ec0 + 8003190: 687b ldr r3, [r7, #4] + 8003192: 681b ldr r3, [r3, #0] + 8003194: 4618 mov r0, r3 + 8003196: f7fe feb7 bl 8001f08 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); - 8003152: 687b ldr r3, [r7, #4] - 8003154: 681b ldr r3, [r3, #0] - 8003156: 2203 movs r2, #3 - 8003158: 601a str r2, [r3, #0] + 800319a: 687b ldr r3, [r7, #4] + 800319c: 681b ldr r3, [r3, #0] + 800319e: 2203 movs r2, #3 + 80031a0: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); - 800315a: f7fe fcc7 bl 8001aec - 800315e: 60b8 str r0, [r7, #8] + 80031a2: f7fe fcc7 bl 8001b34 + 80031a6: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) - 8003160: e029 b.n 80031b6 + 80031a8: e029 b.n 80031fe SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8003162: 687b ldr r3, [r7, #4] - 8003164: 6ddb ldr r3, [r3, #92] @ 0x5c - 8003166: f043 0210 orr.w r2, r3, #16 - 800316a: 687b ldr r3, [r7, #4] - 800316c: 65da str r2, [r3, #92] @ 0x5c + 80031aa: 687b ldr r3, [r7, #4] + 80031ac: 6ddb ldr r3, [r3, #92] @ 0x5c + 80031ae: f043 0210 orr.w r2, r3, #16 + 80031b2: 687b ldr r3, [r7, #4] + 80031b4: 65da str r2, [r3, #92] @ 0x5c SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 800316e: 687b ldr r3, [r7, #4] - 8003170: 6e1b ldr r3, [r3, #96] @ 0x60 - 8003172: f043 0201 orr.w r2, r3, #1 - 8003176: 687b ldr r3, [r7, #4] - 8003178: 661a str r2, [r3, #96] @ 0x60 + 80031b6: 687b ldr r3, [r7, #4] + 80031b8: 6e1b ldr r3, [r3, #96] @ 0x60 + 80031ba: f043 0201 orr.w r2, r3, #1 + 80031be: 687b ldr r3, [r7, #4] + 80031c0: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; - 800317a: 2301 movs r3, #1 - 800317c: e023 b.n 80031c6 + 80031c2: 2301 movs r3, #1 + 80031c4: e023 b.n 800320e { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - 800317e: f7fe fcb5 bl 8001aec - 8003182: 4602 mov r2, r0 - 8003184: 68bb ldr r3, [r7, #8] - 8003186: 1ad3 subs r3, r2, r3 - 8003188: 2b02 cmp r3, #2 - 800318a: d914 bls.n 80031b6 + 80031c6: f7fe fcb5 bl 8001b34 + 80031ca: 4602 mov r2, r0 + 80031cc: 68bb ldr r3, [r7, #8] + 80031ce: 1ad3 subs r3, r2, r3 + 80031d0: 2b02 cmp r3, #2 + 80031d2: d914 bls.n 80031fe { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) - 800318c: 687b ldr r3, [r7, #4] - 800318e: 681b ldr r3, [r3, #0] - 8003190: 689b ldr r3, [r3, #8] - 8003192: f003 0301 and.w r3, r3, #1 - 8003196: 2b00 cmp r3, #0 - 8003198: d00d beq.n 80031b6 + 80031d4: 687b ldr r3, [r7, #4] + 80031d6: 681b ldr r3, [r3, #0] + 80031d8: 689b ldr r3, [r3, #8] + 80031da: f003 0301 and.w r3, r3, #1 + 80031de: 2b00 cmp r3, #0 + 80031e0: d00d beq.n 80031fe { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 800319a: 687b ldr r3, [r7, #4] - 800319c: 6ddb ldr r3, [r3, #92] @ 0x5c - 800319e: f043 0210 orr.w r2, r3, #16 - 80031a2: 687b ldr r3, [r7, #4] - 80031a4: 65da str r2, [r3, #92] @ 0x5c + 80031e2: 687b ldr r3, [r7, #4] + 80031e4: 6ddb ldr r3, [r3, #92] @ 0x5c + 80031e6: f043 0210 orr.w r2, r3, #16 + 80031ea: 687b ldr r3, [r7, #4] + 80031ec: 65da str r2, [r3, #92] @ 0x5c /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - 80031a6: 687b ldr r3, [r7, #4] - 80031a8: 6e1b ldr r3, [r3, #96] @ 0x60 - 80031aa: f043 0201 orr.w r2, r3, #1 - 80031ae: 687b ldr r3, [r7, #4] - 80031b0: 661a str r2, [r3, #96] @ 0x60 + 80031ee: 687b ldr r3, [r7, #4] + 80031f0: 6e1b ldr r3, [r3, #96] @ 0x60 + 80031f2: f043 0201 orr.w r2, r3, #1 + 80031f6: 687b ldr r3, [r7, #4] + 80031f8: 661a str r2, [r3, #96] @ 0x60 return HAL_ERROR; - 80031b2: 2301 movs r3, #1 - 80031b4: e007 b.n 80031c6 + 80031fa: 2301 movs r3, #1 + 80031fc: e007 b.n 800320e while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) - 80031b6: 687b ldr r3, [r7, #4] - 80031b8: 681b ldr r3, [r3, #0] - 80031ba: 689b ldr r3, [r3, #8] - 80031bc: f003 0301 and.w r3, r3, #1 - 80031c0: 2b00 cmp r3, #0 - 80031c2: d1dc bne.n 800317e + 80031fe: 687b ldr r3, [r7, #4] + 8003200: 681b ldr r3, [r3, #0] + 8003202: 689b ldr r3, [r3, #8] + 8003204: f003 0301 and.w r3, r3, #1 + 8003208: 2b00 cmp r3, #0 + 800320a: d1dc bne.n 80031c6 } } } /* Return HAL status */ return HAL_OK; - 80031c4: 2300 movs r3, #0 + 800320c: 2300 movs r3, #0 } - 80031c6: 4618 mov r0, r3 - 80031c8: 3710 adds r7, #16 - 80031ca: 46bd mov sp, r7 - 80031cc: bd80 pop {r7, pc} + 800320e: 4618 mov r0, r3 + 8003210: 3710 adds r7, #16 + 8003212: 46bd mov sp, r7 + 8003214: bd80 pop {r7, pc} -080031ce : +08003216 : { - 80031ce: b480 push {r7} - 80031d0: b083 sub sp, #12 - 80031d2: af00 add r7, sp, #0 - 80031d4: 6078 str r0, [r7, #4] + 8003216: b480 push {r7} + 8003218: b083 sub sp, #12 + 800321a: af00 add r7, sp, #0 + 800321c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); - 80031d6: 687b ldr r3, [r7, #4] - 80031d8: 689b ldr r3, [r3, #8] - 80031da: f003 0301 and.w r3, r3, #1 - 80031de: 2b01 cmp r3, #1 - 80031e0: d101 bne.n 80031e6 - 80031e2: 2301 movs r3, #1 - 80031e4: e000 b.n 80031e8 - 80031e6: 2300 movs r3, #0 + 800321e: 687b ldr r3, [r7, #4] + 8003220: 689b ldr r3, [r3, #8] + 8003222: f003 0301 and.w r3, r3, #1 + 8003226: 2b01 cmp r3, #1 + 8003228: d101 bne.n 800322e + 800322a: 2301 movs r3, #1 + 800322c: e000 b.n 8003230 + 800322e: 2300 movs r3, #0 } - 80031e8: 4618 mov r0, r3 - 80031ea: 370c adds r7, #12 - 80031ec: 46bd mov sp, r7 - 80031ee: f85d 7b04 ldr.w r7, [sp], #4 - 80031f2: 4770 bx lr + 8003230: 4618 mov r0, r3 + 8003232: 370c adds r7, #12 + 8003234: 46bd mov sp, r7 + 8003236: f85d 7b04 ldr.w r7, [sp], #4 + 800323a: 4770 bx lr -080031f4 : +0800323c : { - 80031f4: b480 push {r7} - 80031f6: b083 sub sp, #12 - 80031f8: af00 add r7, sp, #0 - 80031fa: 6078 str r0, [r7, #4] - 80031fc: 6039 str r1, [r7, #0] + 800323c: b480 push {r7} + 800323e: b083 sub sp, #12 + 8003240: af00 add r7, sp, #0 + 8003242: 6078 str r0, [r7, #4] + 8003244: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CR, - 80031fe: 687b ldr r3, [r7, #4] - 8003200: 689b ldr r3, [r3, #8] - 8003202: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000 - 8003206: f023 033f bic.w r3, r3, #63 @ 0x3f - 800320a: 683a ldr r2, [r7, #0] - 800320c: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 - 8003210: 4313 orrs r3, r2 - 8003212: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 - 8003216: 687b ldr r3, [r7, #4] - 8003218: 609a str r2, [r3, #8] + 8003246: 687b ldr r3, [r7, #4] + 8003248: 689b ldr r3, [r3, #8] + 800324a: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000 + 800324e: f023 033f bic.w r3, r3, #63 @ 0x3f + 8003252: 683a ldr r2, [r7, #0] + 8003254: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 + 8003258: 4313 orrs r3, r2 + 800325a: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 + 800325e: 687b ldr r3, [r7, #4] + 8003260: 609a str r2, [r3, #8] } - 800321a: bf00 nop - 800321c: 370c adds r7, #12 - 800321e: 46bd mov sp, r7 - 8003220: f85d 7b04 ldr.w r7, [sp], #4 - 8003224: 4770 bx lr + 8003262: bf00 nop + 8003264: 370c adds r7, #12 + 8003266: 46bd mov sp, r7 + 8003268: f85d 7b04 ldr.w r7, [sp], #4 + 800326c: 4770 bx lr -08003226 : +0800326e : { - 8003226: b480 push {r7} - 8003228: b083 sub sp, #12 - 800322a: af00 add r7, sp, #0 - 800322c: 6078 str r0, [r7, #4] + 800326e: b480 push {r7} + 8003270: b083 sub sp, #12 + 8003272: af00 add r7, sp, #0 + 8003274: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); - 800322e: 687b ldr r3, [r7, #4] - 8003230: 689b ldr r3, [r3, #8] - 8003232: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 - 8003236: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 - 800323a: d101 bne.n 8003240 - 800323c: 2301 movs r3, #1 - 800323e: e000 b.n 8003242 - 8003240: 2300 movs r3, #0 + 8003276: 687b ldr r3, [r7, #4] + 8003278: 689b ldr r3, [r3, #8] + 800327a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 + 800327e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 + 8003282: d101 bne.n 8003288 + 8003284: 2301 movs r3, #1 + 8003286: e000 b.n 800328a + 8003288: 2300 movs r3, #0 } - 8003242: 4618 mov r0, r3 - 8003244: 370c adds r7, #12 - 8003246: 46bd mov sp, r7 - 8003248: f85d 7b04 ldr.w r7, [sp], #4 - 800324c: 4770 bx lr + 800328a: 4618 mov r0, r3 + 800328c: 370c adds r7, #12 + 800328e: 46bd mov sp, r7 + 8003290: f85d 7b04 ldr.w r7, [sp], #4 + 8003294: 4770 bx lr -0800324e : +08003296 : { - 800324e: b480 push {r7} - 8003250: b083 sub sp, #12 - 8003252: af00 add r7, sp, #0 - 8003254: 6078 str r0, [r7, #4] + 8003296: b480 push {r7} + 8003298: b083 sub sp, #12 + 800329a: af00 add r7, sp, #0 + 800329c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); - 8003256: 687b ldr r3, [r7, #4] - 8003258: 689b ldr r3, [r3, #8] - 800325a: f003 0304 and.w r3, r3, #4 - 800325e: 2b04 cmp r3, #4 - 8003260: d101 bne.n 8003266 - 8003262: 2301 movs r3, #1 - 8003264: e000 b.n 8003268 - 8003266: 2300 movs r3, #0 + 800329e: 687b ldr r3, [r7, #4] + 80032a0: 689b ldr r3, [r3, #8] + 80032a2: f003 0304 and.w r3, r3, #4 + 80032a6: 2b04 cmp r3, #4 + 80032a8: d101 bne.n 80032ae + 80032aa: 2301 movs r3, #1 + 80032ac: e000 b.n 80032b0 + 80032ae: 2300 movs r3, #0 } - 8003268: 4618 mov r0, r3 - 800326a: 370c adds r7, #12 - 800326c: 46bd mov sp, r7 - 800326e: f85d 7b04 ldr.w r7, [sp], #4 - 8003272: 4770 bx lr + 80032b0: 4618 mov r0, r3 + 80032b2: 370c adds r7, #12 + 80032b4: 46bd mov sp, r7 + 80032b6: f85d 7b04 ldr.w r7, [sp], #4 + 80032ba: 4770 bx lr -08003274 : +080032bc : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { - 8003274: b580 push {r7, lr} - 8003276: b084 sub sp, #16 - 8003278: af00 add r7, sp, #0 - 800327a: 6078 str r0, [r7, #4] - 800327c: 6039 str r1, [r7, #0] + 80032bc: b580 push {r7, lr} + 80032be: b084 sub sp, #16 + 80032c0: af00 add r7, sp, #0 + 80032c2: 6078 str r0, [r7, #4] + 80032c4: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; - 800327e: 2300 movs r3, #0 - 8003280: 60bb str r3, [r7, #8] + 80032c6: 2300 movs r3, #0 + 80032c8: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); - 8003282: 687b ldr r3, [r7, #4] - 8003284: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 - 8003288: 2b01 cmp r3, #1 - 800328a: d101 bne.n 8003290 - 800328c: 2302 movs r3, #2 - 800328e: e04d b.n 800332c - 8003290: 687b ldr r3, [r7, #4] - 8003292: 2201 movs r2, #1 - 8003294: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80032ca: 687b ldr r3, [r7, #4] + 80032cc: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 + 80032d0: 2b01 cmp r3, #1 + 80032d2: d101 bne.n 80032d8 + 80032d4: 2302 movs r3, #2 + 80032d6: e04d b.n 8003374 + 80032d8: 687b ldr r3, [r7, #4] + 80032da: 2201 movs r2, #1 + 80032dc: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); - 8003298: 6878 ldr r0, [r7, #4] - 800329a: f7ff ff39 bl 8003110 - 800329e: 4603 mov r3, r0 - 80032a0: 73fb strb r3, [r7, #15] + 80032e0: 6878 ldr r0, [r7, #4] + 80032e2: f7ff ff39 bl 8003158 + 80032e6: 4603 mov r3, r0 + 80032e8: 73fb strb r3, [r7, #15] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) - 80032a2: 7bfb ldrb r3, [r7, #15] - 80032a4: 2b00 cmp r3, #0 - 80032a6: d136 bne.n 8003316 + 80032ea: 7bfb ldrb r3, [r7, #15] + 80032ec: 2b00 cmp r3, #0 + 80032ee: d136 bne.n 800335e { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 80032a8: 687b ldr r3, [r7, #4] - 80032aa: 6ddb ldr r3, [r3, #92] @ 0x5c - 80032ac: f423 5388 bic.w r3, r3, #4352 @ 0x1100 - 80032b0: f023 0302 bic.w r3, r3, #2 - 80032b4: f043 0202 orr.w r2, r3, #2 - 80032b8: 687b ldr r3, [r7, #4] - 80032ba: 65da str r2, [r3, #92] @ 0x5c + 80032f0: 687b ldr r3, [r7, #4] + 80032f2: 6ddb ldr r3, [r3, #92] @ 0x5c + 80032f4: f423 5388 bic.w r3, r3, #4352 @ 0x1100 + 80032f8: f023 0302 bic.w r3, r3, #2 + 80032fc: f043 0202 orr.w r2, r3, #2 + 8003300: 687b ldr r3, [r7, #4] + 8003302: 65da str r2, [r3, #92] @ 0x5c HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, SingleDiff); - 80032bc: 687b ldr r3, [r7, #4] - 80032be: 681b ldr r3, [r3, #0] - 80032c0: 6839 ldr r1, [r7, #0] - 80032c2: 4618 mov r0, r3 - 80032c4: f7ff ff96 bl 80031f4 + 8003304: 687b ldr r3, [r7, #4] + 8003306: 681b ldr r3, [r3, #0] + 8003308: 6839 ldr r1, [r7, #0] + 800330a: 4618 mov r0, r3 + 800330c: f7ff ff96 bl 800323c /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) - 80032c8: e014 b.n 80032f4 + 8003310: e014 b.n 800333c { wait_loop_index++; - 80032ca: 68bb ldr r3, [r7, #8] - 80032cc: 3301 adds r3, #1 - 80032ce: 60bb str r3, [r7, #8] + 8003312: 68bb ldr r3, [r7, #8] + 8003314: 3301 adds r3, #1 + 8003316: 60bb str r3, [r7, #8] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) - 80032d0: 68bb ldr r3, [r7, #8] - 80032d2: 4a18 ldr r2, [pc, #96] @ (8003334 ) - 80032d4: 4293 cmp r3, r2 - 80032d6: d90d bls.n 80032f4 + 8003318: 68bb ldr r3, [r7, #8] + 800331a: 4a18 ldr r2, [pc, #96] @ (800337c ) + 800331c: 4293 cmp r3, r2 + 800331e: d90d bls.n 800333c { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, - 80032d8: 687b ldr r3, [r7, #4] - 80032da: 6ddb ldr r3, [r3, #92] @ 0x5c - 80032dc: f023 0312 bic.w r3, r3, #18 - 80032e0: f043 0210 orr.w r2, r3, #16 - 80032e4: 687b ldr r3, [r7, #4] - 80032e6: 65da str r2, [r3, #92] @ 0x5c + 8003320: 687b ldr r3, [r7, #4] + 8003322: 6ddb ldr r3, [r3, #92] @ 0x5c + 8003324: f023 0312 bic.w r3, r3, #18 + 8003328: f043 0210 orr.w r2, r3, #16 + 800332c: 687b ldr r3, [r7, #4] + 800332e: 65da str r2, [r3, #92] @ 0x5c HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); - 80032e8: 687b ldr r3, [r7, #4] - 80032ea: 2200 movs r2, #0 - 80032ec: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 8003330: 687b ldr r3, [r7, #4] + 8003332: 2200 movs r2, #0 + 8003334: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_ERROR; - 80032f0: 2301 movs r3, #1 - 80032f2: e01b b.n 800332c + 8003338: 2301 movs r3, #1 + 800333a: e01b b.n 8003374 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) - 80032f4: 687b ldr r3, [r7, #4] - 80032f6: 681b ldr r3, [r3, #0] - 80032f8: 4618 mov r0, r3 - 80032fa: f7ff ff94 bl 8003226 - 80032fe: 4603 mov r3, r0 - 8003300: 2b00 cmp r3, #0 - 8003302: d1e2 bne.n 80032ca + 800333c: 687b ldr r3, [r7, #4] + 800333e: 681b ldr r3, [r3, #0] + 8003340: 4618 mov r0, r3 + 8003342: f7ff ff94 bl 800326e + 8003346: 4603 mov r3, r0 + 8003348: 2b00 cmp r3, #0 + 800334a: d1e2 bne.n 8003312 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, - 8003304: 687b ldr r3, [r7, #4] - 8003306: 6ddb ldr r3, [r3, #92] @ 0x5c - 8003308: f023 0303 bic.w r3, r3, #3 - 800330c: f043 0201 orr.w r2, r3, #1 - 8003310: 687b ldr r3, [r7, #4] - 8003312: 65da str r2, [r3, #92] @ 0x5c - 8003314: e005 b.n 8003322 + 800334c: 687b ldr r3, [r7, #4] + 800334e: 6ddb ldr r3, [r3, #92] @ 0x5c + 8003350: f023 0303 bic.w r3, r3, #3 + 8003354: f043 0201 orr.w r2, r3, #1 + 8003358: 687b ldr r3, [r7, #4] + 800335a: 65da str r2, [r3, #92] @ 0x5c + 800335c: e005 b.n 800336a HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - 8003316: 687b ldr r3, [r7, #4] - 8003318: 6ddb ldr r3, [r3, #92] @ 0x5c - 800331a: f043 0210 orr.w r2, r3, #16 - 800331e: 687b ldr r3, [r7, #4] - 8003320: 65da str r2, [r3, #92] @ 0x5c + 800335e: 687b ldr r3, [r7, #4] + 8003360: 6ddb ldr r3, [r3, #92] @ 0x5c + 8003362: f043 0210 orr.w r2, r3, #16 + 8003366: 687b ldr r3, [r7, #4] + 8003368: 65da str r2, [r3, #92] @ 0x5c /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); - 8003322: 687b ldr r3, [r7, #4] - 8003324: 2200 movs r2, #0 - 8003326: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 800336a: 687b ldr r3, [r7, #4] + 800336c: 2200 movs r2, #0 + 800336e: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; - 800332a: 7bfb ldrb r3, [r7, #15] + 8003372: 7bfb ldrb r3, [r7, #15] } - 800332c: 4618 mov r0, r3 - 800332e: 3710 adds r7, #16 - 8003330: 46bd mov sp, r7 - 8003332: bd80 pop {r7, pc} - 8003334: 0004de01 .word 0x0004de01 + 8003374: 4618 mov r0, r3 + 8003376: 3710 adds r7, #16 + 8003378: 46bd mov sp, r7 + 800337a: bd80 pop {r7, pc} + 800337c: 0004de01 .word 0x0004de01 -08003338 : +08003380 : * @param hadc Master ADC handle * @param pMultimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode) { - 8003338: b590 push {r4, r7, lr} - 800333a: b0a1 sub sp, #132 @ 0x84 - 800333c: af00 add r7, sp, #0 - 800333e: 6078 str r0, [r7, #4] - 8003340: 6039 str r1, [r7, #0] + 8003380: b590 push {r4, r7, lr} + 8003382: b0a1 sub sp, #132 @ 0x84 + 8003384: af00 add r7, sp, #0 + 8003386: 6078 str r0, [r7, #4] + 8003388: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; - 8003342: 2300 movs r3, #0 - 8003344: f887 307f strb.w r3, [r7, #127] @ 0x7f + 800338a: 2300 movs r3, #0 + 800338c: f887 307f strb.w r3, [r7, #127] @ 0x7f assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); - 8003348: 687b ldr r3, [r7, #4] - 800334a: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 - 800334e: 2b01 cmp r3, #1 - 8003350: d101 bne.n 8003356 - 8003352: 2302 movs r3, #2 - 8003354: e08b b.n 800346e - 8003356: 687b ldr r3, [r7, #4] - 8003358: 2201 movs r2, #1 - 800335a: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 8003390: 687b ldr r3, [r7, #4] + 8003392: f893 3058 ldrb.w r3, [r3, #88] @ 0x58 + 8003396: 2b01 cmp r3, #1 + 8003398: d101 bne.n 800339e + 800339a: 2302 movs r3, #2 + 800339c: e08b b.n 80034b6 + 800339e: 687b ldr r3, [r7, #4] + 80033a0: 2201 movs r2, #1 + 80033a2: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Temporary handle minimum initialization */ __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave); - 800335e: 2300 movs r3, #0 - 8003360: 667b str r3, [r7, #100] @ 0x64 + 80033a6: 2300 movs r3, #0 + 80033a8: 667b str r3, [r7, #100] @ 0x64 ADC_CLEAR_ERRORCODE(&tmp_hadc_slave); - 8003362: 2300 movs r3, #0 - 8003364: 66bb str r3, [r7, #104] @ 0x68 + 80033aa: 2300 movs r3, #0 + 80033ac: 66bb str r3, [r7, #104] @ 0x68 ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave); - 8003366: 687b ldr r3, [r7, #4] - 8003368: 681b ldr r3, [r3, #0] - 800336a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 - 800336e: d102 bne.n 8003376 - 8003370: 4b41 ldr r3, [pc, #260] @ (8003478 ) - 8003372: 60bb str r3, [r7, #8] - 8003374: e001 b.n 800337a - 8003376: 2300 movs r3, #0 - 8003378: 60bb str r3, [r7, #8] + 80033ae: 687b ldr r3, [r7, #4] + 80033b0: 681b ldr r3, [r3, #0] + 80033b2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 + 80033b6: d102 bne.n 80033be + 80033b8: 4b41 ldr r3, [pc, #260] @ (80034c0 ) + 80033ba: 60bb str r3, [r7, #8] + 80033bc: e001 b.n 80033c2 + 80033be: 2300 movs r3, #0 + 80033c0: 60bb str r3, [r7, #8] if (tmp_hadc_slave.Instance == NULL) - 800337a: 68bb ldr r3, [r7, #8] - 800337c: 2b00 cmp r3, #0 - 800337e: d10b bne.n 8003398 + 80033c2: 68bb ldr r3, [r7, #8] + 80033c4: 2b00 cmp r3, #0 + 80033c6: d10b bne.n 80033e0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 8003380: 687b ldr r3, [r7, #4] - 8003382: 6ddb ldr r3, [r3, #92] @ 0x5c - 8003384: f043 0220 orr.w r2, r3, #32 - 8003388: 687b ldr r3, [r7, #4] - 800338a: 65da str r2, [r3, #92] @ 0x5c + 80033c8: 687b ldr r3, [r7, #4] + 80033ca: 6ddb ldr r3, [r3, #92] @ 0x5c + 80033cc: f043 0220 orr.w r2, r3, #32 + 80033d0: 687b ldr r3, [r7, #4] + 80033d2: 65da str r2, [r3, #92] @ 0x5c /* Process unlocked */ __HAL_UNLOCK(hadc); - 800338c: 687b ldr r3, [r7, #4] - 800338e: 2200 movs r2, #0 - 8003390: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80033d4: 687b ldr r3, [r7, #4] + 80033d6: 2200 movs r2, #0 + 80033d8: f883 2058 strb.w r2, [r3, #88] @ 0x58 return HAL_ERROR; - 8003394: 2301 movs r3, #1 - 8003396: e06a b.n 800346e + 80033dc: 2301 movs r3, #1 + 80033de: e06a b.n 80034b6 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DMA configuration */ /* - Multimode DMA mode */ tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance); - 8003398: 68bb ldr r3, [r7, #8] - 800339a: 4618 mov r0, r3 - 800339c: f7ff ff57 bl 800324e - 80033a0: 67b8 str r0, [r7, #120] @ 0x78 + 80033e0: 68bb ldr r3, [r7, #8] + 80033e2: 4618 mov r0, r3 + 80033e4: f7ff ff57 bl 8003296 + 80033e8: 67b8 str r0, [r7, #120] @ 0x78 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - 80033a2: 687b ldr r3, [r7, #4] - 80033a4: 681b ldr r3, [r3, #0] - 80033a6: 4618 mov r0, r3 - 80033a8: f7ff ff51 bl 800324e - 80033ac: 4603 mov r3, r0 - 80033ae: 2b00 cmp r3, #0 - 80033b0: d14c bne.n 800344c + 80033ea: 687b ldr r3, [r7, #4] + 80033ec: 681b ldr r3, [r3, #0] + 80033ee: 4618 mov r0, r3 + 80033f0: f7ff ff51 bl 8003296 + 80033f4: 4603 mov r3, r0 + 80033f6: 2b00 cmp r3, #0 + 80033f8: d14c bne.n 8003494 && (tmp_hadc_slave_conversion_on_going == 0UL)) - 80033b2: 6fbb ldr r3, [r7, #120] @ 0x78 - 80033b4: 2b00 cmp r3, #0 - 80033b6: d149 bne.n 800344c + 80033fa: 6fbb ldr r3, [r7, #120] @ 0x78 + 80033fc: 2b00 cmp r3, #0 + 80033fe: d149 bne.n 8003494 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - 80033b8: 4b30 ldr r3, [pc, #192] @ (800347c ) - 80033ba: 677b str r3, [r7, #116] @ 0x74 + 8003400: 4b30 ldr r3, [pc, #192] @ (80034c4 ) + 8003402: 677b str r3, [r7, #116] @ 0x74 /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (pMultimode->Mode != ADC_MODE_INDEPENDENT) - 80033bc: 683b ldr r3, [r7, #0] - 80033be: 681b ldr r3, [r3, #0] - 80033c0: 2b00 cmp r3, #0 - 80033c2: d028 beq.n 8003416 + 8003404: 683b ldr r3, [r7, #0] + 8003406: 681b ldr r3, [r3, #0] + 8003408: 2b00 cmp r3, #0 + 800340a: d028 beq.n 800345e { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, - 80033c4: 6f7b ldr r3, [r7, #116] @ 0x74 - 80033c6: 689b ldr r3, [r3, #8] - 80033c8: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 80033cc: 683b ldr r3, [r7, #0] - 80033ce: 6859 ldr r1, [r3, #4] - 80033d0: 687b ldr r3, [r7, #4] - 80033d2: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 - 80033d6: 035b lsls r3, r3, #13 - 80033d8: 430b orrs r3, r1 - 80033da: 431a orrs r2, r3 - 80033dc: 6f7b ldr r3, [r7, #116] @ 0x74 - 80033de: 609a str r2, [r3, #8] + 800340c: 6f7b ldr r3, [r7, #116] @ 0x74 + 800340e: 689b ldr r3, [r3, #8] + 8003410: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8003414: 683b ldr r3, [r7, #0] + 8003416: 6859 ldr r1, [r3, #4] + 8003418: 687b ldr r3, [r7, #4] + 800341a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 + 800341e: 035b lsls r3, r3, #13 + 8003420: 430b orrs r3, r1 + 8003422: 431a orrs r2, r3 + 8003424: 6f7b ldr r3, [r7, #116] @ 0x74 + 8003426: 609a str r2, [r3, #8] /* from 1 to 10 clock cycles for 10 bits, */ /* from 1 to 8 clock cycles for 8 bits */ /* from 1 to 6 clock cycles for 6 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - 80033e0: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 - 80033e4: f7ff fef3 bl 80031ce - 80033e8: 4604 mov r4, r0 - 80033ea: 4823 ldr r0, [pc, #140] @ (8003478 ) - 80033ec: f7ff feef bl 80031ce - 80033f0: 4603 mov r3, r0 - 80033f2: 4323 orrs r3, r4 - 80033f4: 2b00 cmp r3, #0 - 80033f6: d133 bne.n 8003460 + 8003428: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 + 800342c: f7ff fef3 bl 8003216 + 8003430: 4604 mov r4, r0 + 8003432: 4823 ldr r0, [pc, #140] @ (80034c0 ) + 8003434: f7ff feef bl 8003216 + 8003438: 4603 mov r3, r0 + 800343a: 4323 orrs r3, r4 + 800343c: 2b00 cmp r3, #0 + 800343e: d133 bne.n 80034a8 { MODIFY_REG(tmpADC_Common->CCR, - 80033f8: 6f7b ldr r3, [r7, #116] @ 0x74 - 80033fa: 689b ldr r3, [r3, #8] - 80033fc: f423 6371 bic.w r3, r3, #3856 @ 0xf10 - 8003400: f023 030f bic.w r3, r3, #15 - 8003404: 683a ldr r2, [r7, #0] - 8003406: 6811 ldr r1, [r2, #0] - 8003408: 683a ldr r2, [r7, #0] - 800340a: 6892 ldr r2, [r2, #8] - 800340c: 430a orrs r2, r1 - 800340e: 431a orrs r2, r3 - 8003410: 6f7b ldr r3, [r7, #116] @ 0x74 - 8003412: 609a str r2, [r3, #8] + 8003440: 6f7b ldr r3, [r7, #116] @ 0x74 + 8003442: 689b ldr r3, [r3, #8] + 8003444: f423 6371 bic.w r3, r3, #3856 @ 0xf10 + 8003448: f023 030f bic.w r3, r3, #15 + 800344c: 683a ldr r2, [r7, #0] + 800344e: 6811 ldr r1, [r2, #0] + 8003450: 683a ldr r2, [r7, #0] + 8003452: 6892 ldr r2, [r2, #8] + 8003454: 430a orrs r2, r1 + 8003456: 431a orrs r2, r3 + 8003458: 6f7b ldr r3, [r7, #116] @ 0x74 + 800345a: 609a str r2, [r3, #8] if (pMultimode->Mode != ADC_MODE_INDEPENDENT) - 8003414: e024 b.n 8003460 + 800345c: e024 b.n 80034a8 ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG); - 8003416: 6f7b ldr r3, [r7, #116] @ 0x74 - 8003418: 689b ldr r3, [r3, #8] - 800341a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 - 800341e: 6f7b ldr r3, [r7, #116] @ 0x74 - 8003420: 609a str r2, [r3, #8] + 800345e: 6f7b ldr r3, [r7, #116] @ 0x74 + 8003460: 689b ldr r3, [r3, #8] + 8003462: f423 4260 bic.w r2, r3, #57344 @ 0xe000 + 8003466: 6f7b ldr r3, [r7, #116] @ 0x74 + 8003468: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) - 8003422: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 - 8003426: f7ff fed2 bl 80031ce - 800342a: 4604 mov r4, r0 - 800342c: 4812 ldr r0, [pc, #72] @ (8003478 ) - 800342e: f7ff fece bl 80031ce - 8003432: 4603 mov r3, r0 - 8003434: 4323 orrs r3, r4 - 8003436: 2b00 cmp r3, #0 - 8003438: d112 bne.n 8003460 + 800346a: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000 + 800346e: f7ff fed2 bl 8003216 + 8003472: 4604 mov r4, r0 + 8003474: 4812 ldr r0, [pc, #72] @ (80034c0 ) + 8003476: f7ff fece bl 8003216 + 800347a: 4603 mov r3, r0 + 800347c: 4323 orrs r3, r4 + 800347e: 2b00 cmp r3, #0 + 8003480: d112 bne.n 80034a8 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); - 800343a: 6f7b ldr r3, [r7, #116] @ 0x74 - 800343c: 689b ldr r3, [r3, #8] - 800343e: f423 6371 bic.w r3, r3, #3856 @ 0xf10 - 8003442: f023 030f bic.w r3, r3, #15 - 8003446: 6f7a ldr r2, [r7, #116] @ 0x74 - 8003448: 6093 str r3, [r2, #8] + 8003482: 6f7b ldr r3, [r7, #116] @ 0x74 + 8003484: 689b ldr r3, [r3, #8] + 8003486: f423 6371 bic.w r3, r3, #3856 @ 0xf10 + 800348a: f023 030f bic.w r3, r3, #15 + 800348e: 6f7a ldr r2, [r7, #116] @ 0x74 + 8003490: 6093 str r3, [r2, #8] if (pMultimode->Mode != ADC_MODE_INDEPENDENT) - 800344a: e009 b.n 8003460 + 8003492: e009 b.n 80034a8 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - 800344c: 687b ldr r3, [r7, #4] - 800344e: 6ddb ldr r3, [r3, #92] @ 0x5c - 8003450: f043 0220 orr.w r2, r3, #32 - 8003454: 687b ldr r3, [r7, #4] - 8003456: 65da str r2, [r3, #92] @ 0x5c + 8003494: 687b ldr r3, [r7, #4] + 8003496: 6ddb ldr r3, [r3, #92] @ 0x5c + 8003498: f043 0220 orr.w r2, r3, #32 + 800349c: 687b ldr r3, [r7, #4] + 800349e: 65da str r2, [r3, #92] @ 0x5c tmp_hal_status = HAL_ERROR; - 8003458: 2301 movs r3, #1 - 800345a: f887 307f strb.w r3, [r7, #127] @ 0x7f - 800345e: e000 b.n 8003462 + 80034a0: 2301 movs r3, #1 + 80034a2: f887 307f strb.w r3, [r7, #127] @ 0x7f + 80034a6: e000 b.n 80034aa if (pMultimode->Mode != ADC_MODE_INDEPENDENT) - 8003460: bf00 nop + 80034a8: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); - 8003462: 687b ldr r3, [r7, #4] - 8003464: 2200 movs r2, #0 - 8003466: f883 2058 strb.w r2, [r3, #88] @ 0x58 + 80034aa: 687b ldr r3, [r7, #4] + 80034ac: 2200 movs r2, #0 + 80034ae: f883 2058 strb.w r2, [r3, #88] @ 0x58 /* Return function status */ return tmp_hal_status; - 800346a: f897 307f ldrb.w r3, [r7, #127] @ 0x7f + 80034b2: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } - 800346e: 4618 mov r0, r3 - 8003470: 3784 adds r7, #132 @ 0x84 - 8003472: 46bd mov sp, r7 - 8003474: bd90 pop {r4, r7, pc} - 8003476: bf00 nop - 8003478: 50000100 .word 0x50000100 - 800347c: 50000300 .word 0x50000300 + 80034b6: 4618 mov r0, r3 + 80034b8: 3784 adds r7, #132 @ 0x84 + 80034ba: 46bd mov sp, r7 + 80034bc: bd90 pop {r4, r7, pc} + 80034be: bf00 nop + 80034c0: 50000100 .word 0x50000100 + 80034c4: 50000300 .word 0x50000300 -08003480 <__NVIC_SetPriorityGrouping>: +080034c8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8003480: b480 push {r7} - 8003482: b085 sub sp, #20 - 8003484: af00 add r7, sp, #0 - 8003486: 6078 str r0, [r7, #4] + 80034c8: b480 push {r7} + 80034ca: b085 sub sp, #20 + 80034cc: af00 add r7, sp, #0 + 80034ce: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8003488: 687b ldr r3, [r7, #4] - 800348a: f003 0307 and.w r3, r3, #7 - 800348e: 60fb str r3, [r7, #12] + 80034d0: 687b ldr r3, [r7, #4] + 80034d2: f003 0307 and.w r3, r3, #7 + 80034d6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8003490: 4b0c ldr r3, [pc, #48] @ (80034c4 <__NVIC_SetPriorityGrouping+0x44>) - 8003492: 68db ldr r3, [r3, #12] - 8003494: 60bb str r3, [r7, #8] + 80034d8: 4b0c ldr r3, [pc, #48] @ (800350c <__NVIC_SetPriorityGrouping+0x44>) + 80034da: 68db ldr r3, [r3, #12] + 80034dc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8003496: 68ba ldr r2, [r7, #8] - 8003498: f64f 03ff movw r3, #63743 @ 0xf8ff - 800349c: 4013 ands r3, r2 - 800349e: 60bb str r3, [r7, #8] + 80034de: 68ba ldr r2, [r7, #8] + 80034e0: f64f 03ff movw r3, #63743 @ 0xf8ff + 80034e4: 4013 ands r3, r2 + 80034e6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 80034a0: 68fb ldr r3, [r7, #12] - 80034a2: 021a lsls r2, r3, #8 + 80034e8: 68fb ldr r3, [r7, #12] + 80034ea: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 80034a4: 68bb ldr r3, [r7, #8] - 80034a6: 4313 orrs r3, r2 + 80034ec: 68bb ldr r3, [r7, #8] + 80034ee: 4313 orrs r3, r2 reg_value = (reg_value | - 80034a8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 - 80034ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 - 80034b0: 60bb str r3, [r7, #8] + 80034f0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 + 80034f4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 + 80034f8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 80034b2: 4a04 ldr r2, [pc, #16] @ (80034c4 <__NVIC_SetPriorityGrouping+0x44>) - 80034b4: 68bb ldr r3, [r7, #8] - 80034b6: 60d3 str r3, [r2, #12] + 80034fa: 4a04 ldr r2, [pc, #16] @ (800350c <__NVIC_SetPriorityGrouping+0x44>) + 80034fc: 68bb ldr r3, [r7, #8] + 80034fe: 60d3 str r3, [r2, #12] } - 80034b8: bf00 nop - 80034ba: 3714 adds r7, #20 - 80034bc: 46bd mov sp, r7 - 80034be: f85d 7b04 ldr.w r7, [sp], #4 - 80034c2: 4770 bx lr - 80034c4: e000ed00 .word 0xe000ed00 + 8003500: bf00 nop + 8003502: 3714 adds r7, #20 + 8003504: 46bd mov sp, r7 + 8003506: f85d 7b04 ldr.w r7, [sp], #4 + 800350a: 4770 bx lr + 800350c: e000ed00 .word 0xe000ed00 -080034c8 <__NVIC_GetPriorityGrouping>: +08003510 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 80034c8: b480 push {r7} - 80034ca: af00 add r7, sp, #0 + 8003510: b480 push {r7} + 8003512: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 80034cc: 4b04 ldr r3, [pc, #16] @ (80034e0 <__NVIC_GetPriorityGrouping+0x18>) - 80034ce: 68db ldr r3, [r3, #12] - 80034d0: 0a1b lsrs r3, r3, #8 - 80034d2: f003 0307 and.w r3, r3, #7 + 8003514: 4b04 ldr r3, [pc, #16] @ (8003528 <__NVIC_GetPriorityGrouping+0x18>) + 8003516: 68db ldr r3, [r3, #12] + 8003518: 0a1b lsrs r3, r3, #8 + 800351a: f003 0307 and.w r3, r3, #7 } - 80034d6: 4618 mov r0, r3 - 80034d8: 46bd mov sp, r7 - 80034da: f85d 7b04 ldr.w r7, [sp], #4 - 80034de: 4770 bx lr - 80034e0: e000ed00 .word 0xe000ed00 + 800351e: 4618 mov r0, r3 + 8003520: 46bd mov sp, r7 + 8003522: f85d 7b04 ldr.w r7, [sp], #4 + 8003526: 4770 bx lr + 8003528: e000ed00 .word 0xe000ed00 -080034e4 <__NVIC_EnableIRQ>: +0800352c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 80034e4: b480 push {r7} - 80034e6: b083 sub sp, #12 - 80034e8: af00 add r7, sp, #0 - 80034ea: 4603 mov r3, r0 - 80034ec: 71fb strb r3, [r7, #7] + 800352c: b480 push {r7} + 800352e: b083 sub sp, #12 + 8003530: af00 add r7, sp, #0 + 8003532: 4603 mov r3, r0 + 8003534: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 80034ee: f997 3007 ldrsb.w r3, [r7, #7] - 80034f2: 2b00 cmp r3, #0 - 80034f4: db0b blt.n 800350e <__NVIC_EnableIRQ+0x2a> + 8003536: f997 3007 ldrsb.w r3, [r7, #7] + 800353a: 2b00 cmp r3, #0 + 800353c: db0b blt.n 8003556 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 80034f6: 79fb ldrb r3, [r7, #7] - 80034f8: f003 021f and.w r2, r3, #31 - 80034fc: 4907 ldr r1, [pc, #28] @ (800351c <__NVIC_EnableIRQ+0x38>) - 80034fe: f997 3007 ldrsb.w r3, [r7, #7] - 8003502: 095b lsrs r3, r3, #5 - 8003504: 2001 movs r0, #1 - 8003506: fa00 f202 lsl.w r2, r0, r2 - 800350a: f841 2023 str.w r2, [r1, r3, lsl #2] + 800353e: 79fb ldrb r3, [r7, #7] + 8003540: f003 021f and.w r2, r3, #31 + 8003544: 4907 ldr r1, [pc, #28] @ (8003564 <__NVIC_EnableIRQ+0x38>) + 8003546: f997 3007 ldrsb.w r3, [r7, #7] + 800354a: 095b lsrs r3, r3, #5 + 800354c: 2001 movs r0, #1 + 800354e: fa00 f202 lsl.w r2, r0, r2 + 8003552: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } - 800350e: bf00 nop - 8003510: 370c adds r7, #12 - 8003512: 46bd mov sp, r7 - 8003514: f85d 7b04 ldr.w r7, [sp], #4 - 8003518: 4770 bx lr - 800351a: bf00 nop - 800351c: e000e100 .word 0xe000e100 + 8003556: bf00 nop + 8003558: 370c adds r7, #12 + 800355a: 46bd mov sp, r7 + 800355c: f85d 7b04 ldr.w r7, [sp], #4 + 8003560: 4770 bx lr + 8003562: bf00 nop + 8003564: e000e100 .word 0xe000e100 -08003520 <__NVIC_SetPriority>: +08003568 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8003520: b480 push {r7} - 8003522: b083 sub sp, #12 - 8003524: af00 add r7, sp, #0 - 8003526: 4603 mov r3, r0 - 8003528: 6039 str r1, [r7, #0] - 800352a: 71fb strb r3, [r7, #7] + 8003568: b480 push {r7} + 800356a: b083 sub sp, #12 + 800356c: af00 add r7, sp, #0 + 800356e: 4603 mov r3, r0 + 8003570: 6039 str r1, [r7, #0] + 8003572: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 800352c: f997 3007 ldrsb.w r3, [r7, #7] - 8003530: 2b00 cmp r3, #0 - 8003532: db0a blt.n 800354a <__NVIC_SetPriority+0x2a> + 8003574: f997 3007 ldrsb.w r3, [r7, #7] + 8003578: 2b00 cmp r3, #0 + 800357a: db0a blt.n 8003592 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8003534: 683b ldr r3, [r7, #0] - 8003536: b2da uxtb r2, r3 - 8003538: 490c ldr r1, [pc, #48] @ (800356c <__NVIC_SetPriority+0x4c>) - 800353a: f997 3007 ldrsb.w r3, [r7, #7] - 800353e: 0112 lsls r2, r2, #4 - 8003540: b2d2 uxtb r2, r2 - 8003542: 440b add r3, r1 - 8003544: f883 2300 strb.w r2, [r3, #768] @ 0x300 + 800357c: 683b ldr r3, [r7, #0] + 800357e: b2da uxtb r2, r3 + 8003580: 490c ldr r1, [pc, #48] @ (80035b4 <__NVIC_SetPriority+0x4c>) + 8003582: f997 3007 ldrsb.w r3, [r7, #7] + 8003586: 0112 lsls r2, r2, #4 + 8003588: b2d2 uxtb r2, r2 + 800358a: 440b add r3, r1 + 800358c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8003548: e00a b.n 8003560 <__NVIC_SetPriority+0x40> + 8003590: e00a b.n 80035a8 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 800354a: 683b ldr r3, [r7, #0] - 800354c: b2da uxtb r2, r3 - 800354e: 4908 ldr r1, [pc, #32] @ (8003570 <__NVIC_SetPriority+0x50>) - 8003550: 79fb ldrb r3, [r7, #7] - 8003552: f003 030f and.w r3, r3, #15 - 8003556: 3b04 subs r3, #4 - 8003558: 0112 lsls r2, r2, #4 - 800355a: b2d2 uxtb r2, r2 - 800355c: 440b add r3, r1 - 800355e: 761a strb r2, [r3, #24] + 8003592: 683b ldr r3, [r7, #0] + 8003594: b2da uxtb r2, r3 + 8003596: 4908 ldr r1, [pc, #32] @ (80035b8 <__NVIC_SetPriority+0x50>) + 8003598: 79fb ldrb r3, [r7, #7] + 800359a: f003 030f and.w r3, r3, #15 + 800359e: 3b04 subs r3, #4 + 80035a0: 0112 lsls r2, r2, #4 + 80035a2: b2d2 uxtb r2, r2 + 80035a4: 440b add r3, r1 + 80035a6: 761a strb r2, [r3, #24] } - 8003560: bf00 nop - 8003562: 370c adds r7, #12 - 8003564: 46bd mov sp, r7 - 8003566: f85d 7b04 ldr.w r7, [sp], #4 - 800356a: 4770 bx lr - 800356c: e000e100 .word 0xe000e100 - 8003570: e000ed00 .word 0xe000ed00 + 80035a8: bf00 nop + 80035aa: 370c adds r7, #12 + 80035ac: 46bd mov sp, r7 + 80035ae: f85d 7b04 ldr.w r7, [sp], #4 + 80035b2: 4770 bx lr + 80035b4: e000e100 .word 0xe000e100 + 80035b8: e000ed00 .word 0xe000ed00 -08003574 : +080035bc : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8003574: b480 push {r7} - 8003576: b089 sub sp, #36 @ 0x24 - 8003578: af00 add r7, sp, #0 - 800357a: 60f8 str r0, [r7, #12] - 800357c: 60b9 str r1, [r7, #8] - 800357e: 607a str r2, [r7, #4] + 80035bc: b480 push {r7} + 80035be: b089 sub sp, #36 @ 0x24 + 80035c0: af00 add r7, sp, #0 + 80035c2: 60f8 str r0, [r7, #12] + 80035c4: 60b9 str r1, [r7, #8] + 80035c6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8003580: 68fb ldr r3, [r7, #12] - 8003582: f003 0307 and.w r3, r3, #7 - 8003586: 61fb str r3, [r7, #28] + 80035c8: 68fb ldr r3, [r7, #12] + 80035ca: f003 0307 and.w r3, r3, #7 + 80035ce: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8003588: 69fb ldr r3, [r7, #28] - 800358a: f1c3 0307 rsb r3, r3, #7 - 800358e: 2b04 cmp r3, #4 - 8003590: bf28 it cs - 8003592: 2304 movcs r3, #4 - 8003594: 61bb str r3, [r7, #24] + 80035d0: 69fb ldr r3, [r7, #28] + 80035d2: f1c3 0307 rsb r3, r3, #7 + 80035d6: 2b04 cmp r3, #4 + 80035d8: bf28 it cs + 80035da: 2304 movcs r3, #4 + 80035dc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8003596: 69fb ldr r3, [r7, #28] - 8003598: 3304 adds r3, #4 - 800359a: 2b06 cmp r3, #6 - 800359c: d902 bls.n 80035a4 - 800359e: 69fb ldr r3, [r7, #28] - 80035a0: 3b03 subs r3, #3 - 80035a2: e000 b.n 80035a6 - 80035a4: 2300 movs r3, #0 - 80035a6: 617b str r3, [r7, #20] + 80035de: 69fb ldr r3, [r7, #28] + 80035e0: 3304 adds r3, #4 + 80035e2: 2b06 cmp r3, #6 + 80035e4: d902 bls.n 80035ec + 80035e6: 69fb ldr r3, [r7, #28] + 80035e8: 3b03 subs r3, #3 + 80035ea: e000 b.n 80035ee + 80035ec: 2300 movs r3, #0 + 80035ee: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 80035a8: f04f 32ff mov.w r2, #4294967295 - 80035ac: 69bb ldr r3, [r7, #24] - 80035ae: fa02 f303 lsl.w r3, r2, r3 - 80035b2: 43da mvns r2, r3 - 80035b4: 68bb ldr r3, [r7, #8] - 80035b6: 401a ands r2, r3 - 80035b8: 697b ldr r3, [r7, #20] - 80035ba: 409a lsls r2, r3 + 80035f0: f04f 32ff mov.w r2, #4294967295 + 80035f4: 69bb ldr r3, [r7, #24] + 80035f6: fa02 f303 lsl.w r3, r2, r3 + 80035fa: 43da mvns r2, r3 + 80035fc: 68bb ldr r3, [r7, #8] + 80035fe: 401a ands r2, r3 + 8003600: 697b ldr r3, [r7, #20] + 8003602: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 80035bc: f04f 31ff mov.w r1, #4294967295 - 80035c0: 697b ldr r3, [r7, #20] - 80035c2: fa01 f303 lsl.w r3, r1, r3 - 80035c6: 43d9 mvns r1, r3 - 80035c8: 687b ldr r3, [r7, #4] - 80035ca: 400b ands r3, r1 + 8003604: f04f 31ff mov.w r1, #4294967295 + 8003608: 697b ldr r3, [r7, #20] + 800360a: fa01 f303 lsl.w r3, r1, r3 + 800360e: 43d9 mvns r1, r3 + 8003610: 687b ldr r3, [r7, #4] + 8003612: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 80035cc: 4313 orrs r3, r2 + 8003614: 4313 orrs r3, r2 ); } - 80035ce: 4618 mov r0, r3 - 80035d0: 3724 adds r7, #36 @ 0x24 - 80035d2: 46bd mov sp, r7 - 80035d4: f85d 7b04 ldr.w r7, [sp], #4 - 80035d8: 4770 bx lr + 8003616: 4618 mov r0, r3 + 8003618: 3724 adds r7, #36 @ 0x24 + 800361a: 46bd mov sp, r7 + 800361c: f85d 7b04 ldr.w r7, [sp], #4 + 8003620: 4770 bx lr ... -080035dc : +08003624 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 80035dc: b580 push {r7, lr} - 80035de: b082 sub sp, #8 - 80035e0: af00 add r7, sp, #0 - 80035e2: 6078 str r0, [r7, #4] + 8003624: b580 push {r7, lr} + 8003626: b082 sub sp, #8 + 8003628: af00 add r7, sp, #0 + 800362a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 80035e4: 687b ldr r3, [r7, #4] - 80035e6: 3b01 subs r3, #1 - 80035e8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 80035ec: d301 bcc.n 80035f2 + 800362c: 687b ldr r3, [r7, #4] + 800362e: 3b01 subs r3, #1 + 8003630: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8003634: d301 bcc.n 800363a { return (1UL); /* Reload value impossible */ - 80035ee: 2301 movs r3, #1 - 80035f0: e00f b.n 8003612 + 8003636: 2301 movs r3, #1 + 8003638: e00f b.n 800365a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80035f2: 4a0a ldr r2, [pc, #40] @ (800361c ) - 80035f4: 687b ldr r3, [r7, #4] - 80035f6: 3b01 subs r3, #1 - 80035f8: 6053 str r3, [r2, #4] + 800363a: 4a0a ldr r2, [pc, #40] @ (8003664 ) + 800363c: 687b ldr r3, [r7, #4] + 800363e: 3b01 subs r3, #1 + 8003640: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80035fa: 210f movs r1, #15 - 80035fc: f04f 30ff mov.w r0, #4294967295 - 8003600: f7ff ff8e bl 8003520 <__NVIC_SetPriority> + 8003642: 210f movs r1, #15 + 8003644: f04f 30ff mov.w r0, #4294967295 + 8003648: f7ff ff8e bl 8003568 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 8003604: 4b05 ldr r3, [pc, #20] @ (800361c ) - 8003606: 2200 movs r2, #0 - 8003608: 609a str r2, [r3, #8] + 800364c: 4b05 ldr r3, [pc, #20] @ (8003664 ) + 800364e: 2200 movs r2, #0 + 8003650: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 800360a: 4b04 ldr r3, [pc, #16] @ (800361c ) - 800360c: 2207 movs r2, #7 - 800360e: 601a str r2, [r3, #0] + 8003652: 4b04 ldr r3, [pc, #16] @ (8003664 ) + 8003654: 2207 movs r2, #7 + 8003656: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8003610: 2300 movs r3, #0 + 8003658: 2300 movs r3, #0 } - 8003612: 4618 mov r0, r3 - 8003614: 3708 adds r7, #8 - 8003616: 46bd mov sp, r7 - 8003618: bd80 pop {r7, pc} - 800361a: bf00 nop - 800361c: e000e010 .word 0xe000e010 + 800365a: 4618 mov r0, r3 + 800365c: 3708 adds r7, #8 + 800365e: 46bd mov sp, r7 + 8003660: bd80 pop {r7, pc} + 8003662: bf00 nop + 8003664: e000e010 .word 0xe000e010 -08003620 : +08003668 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8003620: b580 push {r7, lr} - 8003622: b082 sub sp, #8 - 8003624: af00 add r7, sp, #0 - 8003626: 6078 str r0, [r7, #4] + 8003668: b580 push {r7, lr} + 800366a: b082 sub sp, #8 + 800366c: af00 add r7, sp, #0 + 800366e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8003628: 6878 ldr r0, [r7, #4] - 800362a: f7ff ff29 bl 8003480 <__NVIC_SetPriorityGrouping> + 8003670: 6878 ldr r0, [r7, #4] + 8003672: f7ff ff29 bl 80034c8 <__NVIC_SetPriorityGrouping> } - 800362e: bf00 nop - 8003630: 3708 adds r7, #8 - 8003632: 46bd mov sp, r7 - 8003634: bd80 pop {r7, pc} + 8003676: bf00 nop + 8003678: 3708 adds r7, #8 + 800367a: 46bd mov sp, r7 + 800367c: bd80 pop {r7, pc} -08003636 : +0800367e : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8003636: b580 push {r7, lr} - 8003638: b086 sub sp, #24 - 800363a: af00 add r7, sp, #0 - 800363c: 4603 mov r3, r0 - 800363e: 60b9 str r1, [r7, #8] - 8003640: 607a str r2, [r7, #4] - 8003642: 73fb strb r3, [r7, #15] + 800367e: b580 push {r7, lr} + 8003680: b086 sub sp, #24 + 8003682: af00 add r7, sp, #0 + 8003684: 4603 mov r3, r0 + 8003686: 60b9 str r1, [r7, #8] + 8003688: 607a str r2, [r7, #4] + 800368a: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8003644: f7ff ff40 bl 80034c8 <__NVIC_GetPriorityGrouping> - 8003648: 6178 str r0, [r7, #20] + 800368c: f7ff ff40 bl 8003510 <__NVIC_GetPriorityGrouping> + 8003690: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 800364a: 687a ldr r2, [r7, #4] - 800364c: 68b9 ldr r1, [r7, #8] - 800364e: 6978 ldr r0, [r7, #20] - 8003650: f7ff ff90 bl 8003574 - 8003654: 4602 mov r2, r0 - 8003656: f997 300f ldrsb.w r3, [r7, #15] - 800365a: 4611 mov r1, r2 - 800365c: 4618 mov r0, r3 - 800365e: f7ff ff5f bl 8003520 <__NVIC_SetPriority> + 8003692: 687a ldr r2, [r7, #4] + 8003694: 68b9 ldr r1, [r7, #8] + 8003696: 6978 ldr r0, [r7, #20] + 8003698: f7ff ff90 bl 80035bc + 800369c: 4602 mov r2, r0 + 800369e: f997 300f ldrsb.w r3, [r7, #15] + 80036a2: 4611 mov r1, r2 + 80036a4: 4618 mov r0, r3 + 80036a6: f7ff ff5f bl 8003568 <__NVIC_SetPriority> } - 8003662: bf00 nop - 8003664: 3718 adds r7, #24 - 8003666: 46bd mov sp, r7 - 8003668: bd80 pop {r7, pc} + 80036aa: bf00 nop + 80036ac: 3718 adds r7, #24 + 80036ae: 46bd mov sp, r7 + 80036b0: bd80 pop {r7, pc} -0800366a : +080036b2 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 800366a: b580 push {r7, lr} - 800366c: b082 sub sp, #8 - 800366e: af00 add r7, sp, #0 - 8003670: 4603 mov r3, r0 - 8003672: 71fb strb r3, [r7, #7] + 80036b2: b580 push {r7, lr} + 80036b4: b082 sub sp, #8 + 80036b6: af00 add r7, sp, #0 + 80036b8: 4603 mov r3, r0 + 80036ba: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8003674: f997 3007 ldrsb.w r3, [r7, #7] - 8003678: 4618 mov r0, r3 - 800367a: f7ff ff33 bl 80034e4 <__NVIC_EnableIRQ> + 80036bc: f997 3007 ldrsb.w r3, [r7, #7] + 80036c0: 4618 mov r0, r3 + 80036c2: f7ff ff33 bl 800352c <__NVIC_EnableIRQ> } - 800367e: bf00 nop - 8003680: 3708 adds r7, #8 - 8003682: 46bd mov sp, r7 - 8003684: bd80 pop {r7, pc} + 80036c6: bf00 nop + 80036c8: 3708 adds r7, #8 + 80036ca: 46bd mov sp, r7 + 80036cc: bd80 pop {r7, pc} -08003686 : +080036ce : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8003686: b580 push {r7, lr} - 8003688: b082 sub sp, #8 - 800368a: af00 add r7, sp, #0 - 800368c: 6078 str r0, [r7, #4] + 80036ce: b580 push {r7, lr} + 80036d0: b082 sub sp, #8 + 80036d2: af00 add r7, sp, #0 + 80036d4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 800368e: 6878 ldr r0, [r7, #4] - 8003690: f7ff ffa4 bl 80035dc - 8003694: 4603 mov r3, r0 + 80036d6: 6878 ldr r0, [r7, #4] + 80036d8: f7ff ffa4 bl 8003624 + 80036dc: 4603 mov r3, r0 } - 8003696: 4618 mov r0, r3 - 8003698: 3708 adds r7, #8 - 800369a: 46bd mov sp, r7 - 800369c: bd80 pop {r7, pc} + 80036de: 4618 mov r0, r3 + 80036e0: 3708 adds r7, #8 + 80036e2: 46bd mov sp, r7 + 80036e4: bd80 pop {r7, pc} -0800369e : +080036e6 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - 800369e: b480 push {r7} - 80036a0: b085 sub sp, #20 - 80036a2: af00 add r7, sp, #0 - 80036a4: 6078 str r0, [r7, #4] + 80036e6: b480 push {r7} + 80036e8: b085 sub sp, #20 + 80036ea: af00 add r7, sp, #0 + 80036ec: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 80036a6: 2300 movs r3, #0 - 80036a8: 73fb strb r3, [r7, #15] + 80036ee: 2300 movs r3, #0 + 80036f0: 73fb strb r3, [r7, #15] if(hdma->State != HAL_DMA_STATE_BUSY) - 80036aa: 687b ldr r3, [r7, #4] - 80036ac: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 - 80036b0: b2db uxtb r3, r3 - 80036b2: 2b02 cmp r3, #2 - 80036b4: d005 beq.n 80036c2 + 80036f2: 687b ldr r3, [r7, #4] + 80036f4: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 80036f8: b2db uxtb r3, r3 + 80036fa: 2b02 cmp r3, #2 + 80036fc: d005 beq.n 800370a { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - 80036b6: 687b ldr r3, [r7, #4] - 80036b8: 2204 movs r2, #4 - 80036ba: 63da str r2, [r3, #60] @ 0x3c + 80036fe: 687b ldr r3, [r7, #4] + 8003700: 2204 movs r2, #4 + 8003702: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; - 80036bc: 2301 movs r3, #1 - 80036be: 73fb strb r3, [r7, #15] - 80036c0: e037 b.n 8003732 + 8003704: 2301 movs r3, #1 + 8003706: 73fb strb r3, [r7, #15] + 8003708: e037 b.n 800377a } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 80036c2: 687b ldr r3, [r7, #4] - 80036c4: 681b ldr r3, [r3, #0] - 80036c6: 681a ldr r2, [r3, #0] - 80036c8: 687b ldr r3, [r7, #4] - 80036ca: 681b ldr r3, [r3, #0] - 80036cc: f022 020e bic.w r2, r2, #14 - 80036d0: 601a str r2, [r3, #0] + 800370a: 687b ldr r3, [r7, #4] + 800370c: 681b ldr r3, [r3, #0] + 800370e: 681a ldr r2, [r3, #0] + 8003710: 687b ldr r3, [r7, #4] + 8003712: 681b ldr r3, [r3, #0] + 8003714: f022 020e bic.w r2, r2, #14 + 8003718: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - 80036d2: 687b ldr r3, [r7, #4] - 80036d4: 6c9b ldr r3, [r3, #72] @ 0x48 - 80036d6: 681a ldr r2, [r3, #0] - 80036d8: 687b ldr r3, [r7, #4] - 80036da: 6c9b ldr r3, [r3, #72] @ 0x48 - 80036dc: f422 7280 bic.w r2, r2, #256 @ 0x100 - 80036e0: 601a str r2, [r3, #0] + 800371a: 687b ldr r3, [r7, #4] + 800371c: 6c9b ldr r3, [r3, #72] @ 0x48 + 800371e: 681a ldr r2, [r3, #0] + 8003720: 687b ldr r3, [r7, #4] + 8003722: 6c9b ldr r3, [r3, #72] @ 0x48 + 8003724: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8003728: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - 80036e2: 687b ldr r3, [r7, #4] - 80036e4: 681b ldr r3, [r3, #0] - 80036e6: 681a ldr r2, [r3, #0] - 80036e8: 687b ldr r3, [r7, #4] - 80036ea: 681b ldr r3, [r3, #0] - 80036ec: f022 0201 bic.w r2, r2, #1 - 80036f0: 601a str r2, [r3, #0] + 800372a: 687b ldr r3, [r7, #4] + 800372c: 681b ldr r3, [r3, #0] + 800372e: 681a ldr r2, [r3, #0] + 8003730: 687b ldr r3, [r7, #4] + 8003732: 681b ldr r3, [r3, #0] + 8003734: f022 0201 bic.w r2, r2, #1 + 8003738: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); - 80036f2: 687b ldr r3, [r7, #4] - 80036f4: 6c5b ldr r3, [r3, #68] @ 0x44 - 80036f6: f003 021f and.w r2, r3, #31 - 80036fa: 687b ldr r3, [r7, #4] - 80036fc: 6c1b ldr r3, [r3, #64] @ 0x40 - 80036fe: 2101 movs r1, #1 - 8003700: fa01 f202 lsl.w r2, r1, r2 - 8003704: 605a str r2, [r3, #4] + 800373a: 687b ldr r3, [r7, #4] + 800373c: 6c5b ldr r3, [r3, #68] @ 0x44 + 800373e: f003 021f and.w r2, r3, #31 + 8003742: 687b ldr r3, [r7, #4] + 8003744: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003746: 2101 movs r1, #1 + 8003748: fa01 f202 lsl.w r2, r1, r2 + 800374c: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - 8003706: 687b ldr r3, [r7, #4] - 8003708: 6cdb ldr r3, [r3, #76] @ 0x4c - 800370a: 687a ldr r2, [r7, #4] - 800370c: 6d12 ldr r2, [r2, #80] @ 0x50 - 800370e: 605a str r2, [r3, #4] + 800374e: 687b ldr r3, [r7, #4] + 8003750: 6cdb ldr r3, [r3, #76] @ 0x4c + 8003752: 687a ldr r2, [r7, #4] + 8003754: 6d12 ldr r2, [r2, #80] @ 0x50 + 8003756: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) - 8003710: 687b ldr r3, [r7, #4] - 8003712: 6d5b ldr r3, [r3, #84] @ 0x54 - 8003714: 2b00 cmp r3, #0 - 8003716: d00c beq.n 8003732 + 8003758: 687b ldr r3, [r7, #4] + 800375a: 6d5b ldr r3, [r3, #84] @ 0x54 + 800375c: 2b00 cmp r3, #0 + 800375e: d00c beq.n 800377a { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - 8003718: 687b ldr r3, [r7, #4] - 800371a: 6d5b ldr r3, [r3, #84] @ 0x54 - 800371c: 681a ldr r2, [r3, #0] - 800371e: 687b ldr r3, [r7, #4] - 8003720: 6d5b ldr r3, [r3, #84] @ 0x54 - 8003722: f422 7280 bic.w r2, r2, #256 @ 0x100 - 8003726: 601a str r2, [r3, #0] + 8003760: 687b ldr r3, [r7, #4] + 8003762: 6d5b ldr r3, [r3, #84] @ 0x54 + 8003764: 681a ldr r2, [r3, #0] + 8003766: 687b ldr r3, [r7, #4] + 8003768: 6d5b ldr r3, [r3, #84] @ 0x54 + 800376a: f422 7280 bic.w r2, r2, #256 @ 0x100 + 800376e: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - 8003728: 687b ldr r3, [r7, #4] - 800372a: 6d9b ldr r3, [r3, #88] @ 0x58 - 800372c: 687a ldr r2, [r7, #4] - 800372e: 6dd2 ldr r2, [r2, #92] @ 0x5c - 8003730: 605a str r2, [r3, #4] + 8003770: 687b ldr r3, [r7, #4] + 8003772: 6d9b ldr r3, [r3, #88] @ 0x58 + 8003774: 687a ldr r2, [r7, #4] + 8003776: 6dd2 ldr r2, [r2, #92] @ 0x5c + 8003778: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 8003732: 687b ldr r3, [r7, #4] - 8003734: 2201 movs r2, #1 - 8003736: f883 2025 strb.w r2, [r3, #37] @ 0x25 + 800377a: 687b ldr r3, [r7, #4] + 800377c: 2201 movs r2, #1 + 800377e: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 800373a: 687b ldr r3, [r7, #4] - 800373c: 2200 movs r2, #0 - 800373e: f883 2024 strb.w r2, [r3, #36] @ 0x24 + 8003782: 687b ldr r3, [r7, #4] + 8003784: 2200 movs r2, #0 + 8003786: f883 2024 strb.w r2, [r3, #36] @ 0x24 return status; - 8003742: 7bfb ldrb r3, [r7, #15] + 800378a: 7bfb ldrb r3, [r7, #15] } - 8003744: 4618 mov r0, r3 - 8003746: 3714 adds r7, #20 - 8003748: 46bd mov sp, r7 - 800374a: f85d 7b04 ldr.w r7, [sp], #4 - 800374e: 4770 bx lr + 800378c: 4618 mov r0, r3 + 800378e: 3714 adds r7, #20 + 8003790: 46bd mov sp, r7 + 8003792: f85d 7b04 ldr.w r7, [sp], #4 + 8003796: 4770 bx lr -08003750 : +08003798 : * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { - 8003750: b580 push {r7, lr} - 8003752: b084 sub sp, #16 - 8003754: af00 add r7, sp, #0 - 8003756: 6078 str r0, [r7, #4] + 8003798: b580 push {r7, lr} + 800379a: b084 sub sp, #16 + 800379c: af00 add r7, sp, #0 + 800379e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; - 8003758: 2300 movs r3, #0 - 800375a: 73fb strb r3, [r7, #15] + 80037a0: 2300 movs r3, #0 + 80037a2: 73fb strb r3, [r7, #15] if (HAL_DMA_STATE_BUSY != hdma->State) - 800375c: 687b ldr r3, [r7, #4] - 800375e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 - 8003762: b2db uxtb r3, r3 - 8003764: 2b02 cmp r3, #2 - 8003766: d00d beq.n 8003784 + 80037a4: 687b ldr r3, [r7, #4] + 80037a6: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 + 80037aa: b2db uxtb r3, r3 + 80037ac: 2b02 cmp r3, #2 + 80037ae: d00d beq.n 80037cc { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - 8003768: 687b ldr r3, [r7, #4] - 800376a: 2204 movs r2, #4 - 800376c: 63da str r2, [r3, #60] @ 0x3c + 80037b0: 687b ldr r3, [r7, #4] + 80037b2: 2204 movs r2, #4 + 80037b4: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 800376e: 687b ldr r3, [r7, #4] - 8003770: 2201 movs r2, #1 - 8003772: f883 2025 strb.w r2, [r3, #37] @ 0x25 + 80037b6: 687b ldr r3, [r7, #4] + 80037b8: 2201 movs r2, #1 + 80037ba: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 8003776: 687b ldr r3, [r7, #4] - 8003778: 2200 movs r2, #0 - 800377a: f883 2024 strb.w r2, [r3, #36] @ 0x24 + 80037be: 687b ldr r3, [r7, #4] + 80037c0: 2200 movs r2, #0 + 80037c2: f883 2024 strb.w r2, [r3, #36] @ 0x24 status = HAL_ERROR; - 800377e: 2301 movs r3, #1 - 8003780: 73fb strb r3, [r7, #15] - 8003782: e047 b.n 8003814 + 80037c6: 2301 movs r3, #1 + 80037c8: 73fb strb r3, [r7, #15] + 80037ca: e047 b.n 800385c } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - 8003784: 687b ldr r3, [r7, #4] - 8003786: 681b ldr r3, [r3, #0] - 8003788: 681a ldr r2, [r3, #0] - 800378a: 687b ldr r3, [r7, #4] - 800378c: 681b ldr r3, [r3, #0] - 800378e: f022 020e bic.w r2, r2, #14 - 8003792: 601a str r2, [r3, #0] + 80037cc: 687b ldr r3, [r7, #4] + 80037ce: 681b ldr r3, [r3, #0] + 80037d0: 681a ldr r2, [r3, #0] + 80037d2: 687b ldr r3, [r7, #4] + 80037d4: 681b ldr r3, [r3, #0] + 80037d6: f022 020e bic.w r2, r2, #14 + 80037da: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); - 8003794: 687b ldr r3, [r7, #4] - 8003796: 681b ldr r3, [r3, #0] - 8003798: 681a ldr r2, [r3, #0] - 800379a: 687b ldr r3, [r7, #4] - 800379c: 681b ldr r3, [r3, #0] - 800379e: f022 0201 bic.w r2, r2, #1 - 80037a2: 601a str r2, [r3, #0] + 80037dc: 687b ldr r3, [r7, #4] + 80037de: 681b ldr r3, [r3, #0] + 80037e0: 681a ldr r2, [r3, #0] + 80037e2: 687b ldr r3, [r7, #4] + 80037e4: 681b ldr r3, [r3, #0] + 80037e6: f022 0201 bic.w r2, r2, #1 + 80037ea: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - 80037a4: 687b ldr r3, [r7, #4] - 80037a6: 6c9b ldr r3, [r3, #72] @ 0x48 - 80037a8: 681a ldr r2, [r3, #0] - 80037aa: 687b ldr r3, [r7, #4] - 80037ac: 6c9b ldr r3, [r3, #72] @ 0x48 - 80037ae: f422 7280 bic.w r2, r2, #256 @ 0x100 - 80037b2: 601a str r2, [r3, #0] + 80037ec: 687b ldr r3, [r7, #4] + 80037ee: 6c9b ldr r3, [r3, #72] @ 0x48 + 80037f0: 681a ldr r2, [r3, #0] + 80037f2: 687b ldr r3, [r7, #4] + 80037f4: 6c9b ldr r3, [r3, #72] @ 0x48 + 80037f6: f422 7280 bic.w r2, r2, #256 @ 0x100 + 80037fa: 601a str r2, [r3, #0] /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU)); - 80037b4: 687b ldr r3, [r7, #4] - 80037b6: 6c5b ldr r3, [r3, #68] @ 0x44 - 80037b8: f003 021f and.w r2, r3, #31 - 80037bc: 687b ldr r3, [r7, #4] - 80037be: 6c1b ldr r3, [r3, #64] @ 0x40 - 80037c0: 2101 movs r1, #1 - 80037c2: fa01 f202 lsl.w r2, r1, r2 - 80037c6: 605a str r2, [r3, #4] + 80037fc: 687b ldr r3, [r7, #4] + 80037fe: 6c5b ldr r3, [r3, #68] @ 0x44 + 8003800: f003 021f and.w r2, r3, #31 + 8003804: 687b ldr r3, [r7, #4] + 8003806: 6c1b ldr r3, [r3, #64] @ 0x40 + 8003808: 2101 movs r1, #1 + 800380a: fa01 f202 lsl.w r2, r1, r2 + 800380e: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - 80037c8: 687b ldr r3, [r7, #4] - 80037ca: 6cdb ldr r3, [r3, #76] @ 0x4c - 80037cc: 687a ldr r2, [r7, #4] - 80037ce: 6d12 ldr r2, [r2, #80] @ 0x50 - 80037d0: 605a str r2, [r3, #4] + 8003810: 687b ldr r3, [r7, #4] + 8003812: 6cdb ldr r3, [r3, #76] @ 0x4c + 8003814: 687a ldr r2, [r7, #4] + 8003816: 6d12 ldr r2, [r2, #80] @ 0x50 + 8003818: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) - 80037d2: 687b ldr r3, [r7, #4] - 80037d4: 6d5b ldr r3, [r3, #84] @ 0x54 - 80037d6: 2b00 cmp r3, #0 - 80037d8: d00c beq.n 80037f4 + 800381a: 687b ldr r3, [r7, #4] + 800381c: 6d5b ldr r3, [r3, #84] @ 0x54 + 800381e: 2b00 cmp r3, #0 + 8003820: d00c beq.n 800383c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - 80037da: 687b ldr r3, [r7, #4] - 80037dc: 6d5b ldr r3, [r3, #84] @ 0x54 - 80037de: 681a ldr r2, [r3, #0] - 80037e0: 687b ldr r3, [r7, #4] - 80037e2: 6d5b ldr r3, [r3, #84] @ 0x54 - 80037e4: f422 7280 bic.w r2, r2, #256 @ 0x100 - 80037e8: 601a str r2, [r3, #0] + 8003822: 687b ldr r3, [r7, #4] + 8003824: 6d5b ldr r3, [r3, #84] @ 0x54 + 8003826: 681a ldr r2, [r3, #0] + 8003828: 687b ldr r3, [r7, #4] + 800382a: 6d5b ldr r3, [r3, #84] @ 0x54 + 800382c: f422 7280 bic.w r2, r2, #256 @ 0x100 + 8003830: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - 80037ea: 687b ldr r3, [r7, #4] - 80037ec: 6d9b ldr r3, [r3, #88] @ 0x58 - 80037ee: 687a ldr r2, [r7, #4] - 80037f0: 6dd2 ldr r2, [r2, #92] @ 0x5c - 80037f2: 605a str r2, [r3, #4] + 8003832: 687b ldr r3, [r7, #4] + 8003834: 6d9b ldr r3, [r3, #88] @ 0x58 + 8003836: 687a ldr r2, [r7, #4] + 8003838: 6dd2 ldr r2, [r2, #92] @ 0x5c + 800383a: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - 80037f4: 687b ldr r3, [r7, #4] - 80037f6: 2201 movs r2, #1 - 80037f8: f883 2025 strb.w r2, [r3, #37] @ 0x25 + 800383c: 687b ldr r3, [r7, #4] + 800383e: 2201 movs r2, #1 + 8003840: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Process Unlocked */ __HAL_UNLOCK(hdma); - 80037fc: 687b ldr r3, [r7, #4] - 80037fe: 2200 movs r2, #0 - 8003800: f883 2024 strb.w r2, [r3, #36] @ 0x24 + 8003844: 687b ldr r3, [r7, #4] + 8003846: 2200 movs r2, #0 + 8003848: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) - 8003804: 687b ldr r3, [r7, #4] - 8003806: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003808: 2b00 cmp r3, #0 - 800380a: d003 beq.n 8003814 + 800384c: 687b ldr r3, [r7, #4] + 800384e: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003850: 2b00 cmp r3, #0 + 8003852: d003 beq.n 800385c { hdma->XferAbortCallback(hdma); - 800380c: 687b ldr r3, [r7, #4] - 800380e: 6b9b ldr r3, [r3, #56] @ 0x38 - 8003810: 6878 ldr r0, [r7, #4] - 8003812: 4798 blx r3 + 8003854: 687b ldr r3, [r7, #4] + 8003856: 6b9b ldr r3, [r3, #56] @ 0x38 + 8003858: 6878 ldr r0, [r7, #4] + 800385a: 4798 blx r3 } } return status; - 8003814: 7bfb ldrb r3, [r7, #15] + 800385c: 7bfb ldrb r3, [r7, #15] } - 8003816: 4618 mov r0, r3 - 8003818: 3710 adds r7, #16 - 800381a: 46bd mov sp, r7 - 800381c: bd80 pop {r7, pc} + 800385e: 4618 mov r0, r3 + 8003860: 3710 adds r7, #16 + 8003862: 46bd mov sp, r7 + 8003864: bd80 pop {r7, pc} ... -08003820 : +08003868 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 8003820: b480 push {r7} - 8003822: b087 sub sp, #28 - 8003824: af00 add r7, sp, #0 - 8003826: 6078 str r0, [r7, #4] - 8003828: 6039 str r1, [r7, #0] + 8003868: b480 push {r7} + 800386a: b087 sub sp, #28 + 800386c: af00 add r7, sp, #0 + 800386e: 6078 str r0, [r7, #4] + 8003870: 6039 str r1, [r7, #0] uint32_t position = 0x00U; - 800382a: 2300 movs r3, #0 - 800382c: 617b str r3, [r7, #20] + 8003872: 2300 movs r3, #0 + 8003874: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0U) - 800382e: e15a b.n 8003ae6 + 8003876: e15a b.n 8003b2e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); - 8003830: 683b ldr r3, [r7, #0] - 8003832: 681a ldr r2, [r3, #0] - 8003834: 2101 movs r1, #1 - 8003836: 697b ldr r3, [r7, #20] - 8003838: fa01 f303 lsl.w r3, r1, r3 - 800383c: 4013 ands r3, r2 - 800383e: 60fb str r3, [r7, #12] + 8003878: 683b ldr r3, [r7, #0] + 800387a: 681a ldr r2, [r3, #0] + 800387c: 2101 movs r1, #1 + 800387e: 697b ldr r3, [r7, #20] + 8003880: fa01 f303 lsl.w r3, r1, r3 + 8003884: 4013 ands r3, r2 + 8003886: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) - 8003840: 68fb ldr r3, [r7, #12] - 8003842: 2b00 cmp r3, #0 - 8003844: f000 814c beq.w 8003ae0 + 8003888: 68fb ldr r3, [r7, #12] + 800388a: 2b00 cmp r3, #0 + 800388c: f000 814c beq.w 8003b28 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || - 8003848: 683b ldr r3, [r7, #0] - 800384a: 685b ldr r3, [r3, #4] - 800384c: f003 0303 and.w r3, r3, #3 - 8003850: 2b01 cmp r3, #1 - 8003852: d005 beq.n 8003860 + 8003890: 683b ldr r3, [r7, #0] + 8003892: 685b ldr r3, [r3, #4] + 8003894: f003 0303 and.w r3, r3, #3 + 8003898: 2b01 cmp r3, #1 + 800389a: d005 beq.n 80038a8 ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - 8003854: 683b ldr r3, [r7, #0] - 8003856: 685b ldr r3, [r3, #4] - 8003858: f003 0303 and.w r3, r3, #3 + 800389c: 683b ldr r3, [r7, #0] + 800389e: 685b ldr r3, [r3, #4] + 80038a0: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || - 800385c: 2b02 cmp r3, #2 - 800385e: d130 bne.n 80038c2 + 80038a4: 2b02 cmp r3, #2 + 80038a6: d130 bne.n 800390a { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8003860: 687b ldr r3, [r7, #4] - 8003862: 689b ldr r3, [r3, #8] - 8003864: 613b str r3, [r7, #16] + 80038a8: 687b ldr r3, [r7, #4] + 80038aa: 689b ldr r3, [r3, #8] + 80038ac: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); - 8003866: 697b ldr r3, [r7, #20] - 8003868: 005b lsls r3, r3, #1 - 800386a: 2203 movs r2, #3 - 800386c: fa02 f303 lsl.w r3, r2, r3 - 8003870: 43db mvns r3, r3 - 8003872: 693a ldr r2, [r7, #16] - 8003874: 4013 ands r3, r2 - 8003876: 613b str r3, [r7, #16] + 80038ae: 697b ldr r3, [r7, #20] + 80038b0: 005b lsls r3, r3, #1 + 80038b2: 2203 movs r2, #3 + 80038b4: fa02 f303 lsl.w r3, r2, r3 + 80038b8: 43db mvns r3, r3 + 80038ba: 693a ldr r2, [r7, #16] + 80038bc: 4013 ands r3, r2 + 80038be: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2U)); - 8003878: 683b ldr r3, [r7, #0] - 800387a: 68da ldr r2, [r3, #12] - 800387c: 697b ldr r3, [r7, #20] - 800387e: 005b lsls r3, r3, #1 - 8003880: fa02 f303 lsl.w r3, r2, r3 - 8003884: 693a ldr r2, [r7, #16] - 8003886: 4313 orrs r3, r2 - 8003888: 613b str r3, [r7, #16] + 80038c0: 683b ldr r3, [r7, #0] + 80038c2: 68da ldr r2, [r3, #12] + 80038c4: 697b ldr r3, [r7, #20] + 80038c6: 005b lsls r3, r3, #1 + 80038c8: fa02 f303 lsl.w r3, r2, r3 + 80038cc: 693a ldr r2, [r7, #16] + 80038ce: 4313 orrs r3, r2 + 80038d0: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; - 800388a: 687b ldr r3, [r7, #4] - 800388c: 693a ldr r2, [r7, #16] - 800388e: 609a str r2, [r3, #8] + 80038d2: 687b ldr r3, [r7, #4] + 80038d4: 693a ldr r2, [r7, #16] + 80038d6: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8003890: 687b ldr r3, [r7, #4] - 8003892: 685b ldr r3, [r3, #4] - 8003894: 613b str r3, [r7, #16] + 80038d8: 687b ldr r3, [r7, #4] + 80038da: 685b ldr r3, [r3, #4] + 80038dc: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; - 8003896: 2201 movs r2, #1 - 8003898: 697b ldr r3, [r7, #20] - 800389a: fa02 f303 lsl.w r3, r2, r3 - 800389e: 43db mvns r3, r3 - 80038a0: 693a ldr r2, [r7, #16] - 80038a2: 4013 ands r3, r2 - 80038a4: 613b str r3, [r7, #16] + 80038de: 2201 movs r2, #1 + 80038e0: 697b ldr r3, [r7, #20] + 80038e2: fa02 f303 lsl.w r3, r2, r3 + 80038e6: 43db mvns r3, r3 + 80038e8: 693a ldr r2, [r7, #16] + 80038ea: 4013 ands r3, r2 + 80038ec: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 80038a6: 683b ldr r3, [r7, #0] - 80038a8: 685b ldr r3, [r3, #4] - 80038aa: 091b lsrs r3, r3, #4 - 80038ac: f003 0201 and.w r2, r3, #1 - 80038b0: 697b ldr r3, [r7, #20] - 80038b2: fa02 f303 lsl.w r3, r2, r3 - 80038b6: 693a ldr r2, [r7, #16] - 80038b8: 4313 orrs r3, r2 - 80038ba: 613b str r3, [r7, #16] + 80038ee: 683b ldr r3, [r7, #0] + 80038f0: 685b ldr r3, [r3, #4] + 80038f2: 091b lsrs r3, r3, #4 + 80038f4: f003 0201 and.w r2, r3, #1 + 80038f8: 697b ldr r3, [r7, #20] + 80038fa: fa02 f303 lsl.w r3, r2, r3 + 80038fe: 693a ldr r2, [r7, #16] + 8003900: 4313 orrs r3, r2 + 8003902: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; - 80038bc: 687b ldr r3, [r7, #4] - 80038be: 693a ldr r2, [r7, #16] - 80038c0: 605a str r2, [r3, #4] + 8003904: 687b ldr r3, [r7, #4] + 8003906: 693a ldr r2, [r7, #16] + 8003908: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 80038c2: 683b ldr r3, [r7, #0] - 80038c4: 685b ldr r3, [r3, #4] - 80038c6: f003 0303 and.w r3, r3, #3 - 80038ca: 2b03 cmp r3, #3 - 80038cc: d017 beq.n 80038fe + 800390a: 683b ldr r3, [r7, #0] + 800390c: 685b ldr r3, [r3, #4] + 800390e: f003 0303 and.w r3, r3, #3 + 8003912: 2b03 cmp r3, #3 + 8003914: d017 beq.n 8003946 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 80038ce: 687b ldr r3, [r7, #4] - 80038d0: 68db ldr r3, [r3, #12] - 80038d2: 613b str r3, [r7, #16] + 8003916: 687b ldr r3, [r7, #4] + 8003918: 68db ldr r3, [r3, #12] + 800391a: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); - 80038d4: 697b ldr r3, [r7, #20] - 80038d6: 005b lsls r3, r3, #1 - 80038d8: 2203 movs r2, #3 - 80038da: fa02 f303 lsl.w r3, r2, r3 - 80038de: 43db mvns r3, r3 - 80038e0: 693a ldr r2, [r7, #16] - 80038e2: 4013 ands r3, r2 - 80038e4: 613b str r3, [r7, #16] + 800391c: 697b ldr r3, [r7, #20] + 800391e: 005b lsls r3, r3, #1 + 8003920: 2203 movs r2, #3 + 8003922: fa02 f303 lsl.w r3, r2, r3 + 8003926: 43db mvns r3, r3 + 8003928: 693a ldr r2, [r7, #16] + 800392a: 4013 ands r3, r2 + 800392c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2U)); - 80038e6: 683b ldr r3, [r7, #0] - 80038e8: 689a ldr r2, [r3, #8] - 80038ea: 697b ldr r3, [r7, #20] - 80038ec: 005b lsls r3, r3, #1 - 80038ee: fa02 f303 lsl.w r3, r2, r3 - 80038f2: 693a ldr r2, [r7, #16] - 80038f4: 4313 orrs r3, r2 - 80038f6: 613b str r3, [r7, #16] + 800392e: 683b ldr r3, [r7, #0] + 8003930: 689a ldr r2, [r3, #8] + 8003932: 697b ldr r3, [r7, #20] + 8003934: 005b lsls r3, r3, #1 + 8003936: fa02 f303 lsl.w r3, r2, r3 + 800393a: 693a ldr r2, [r7, #16] + 800393c: 4313 orrs r3, r2 + 800393e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; - 80038f8: 687b ldr r3, [r7, #4] - 80038fa: 693a ldr r2, [r7, #16] - 80038fc: 60da str r2, [r3, #12] + 8003940: 687b ldr r3, [r7, #4] + 8003942: 693a ldr r2, [r7, #16] + 8003944: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 80038fe: 683b ldr r3, [r7, #0] - 8003900: 685b ldr r3, [r3, #4] - 8003902: f003 0303 and.w r3, r3, #3 - 8003906: 2b02 cmp r3, #2 - 8003908: d123 bne.n 8003952 + 8003946: 683b ldr r3, [r7, #0] + 8003948: 685b ldr r3, [r3, #4] + 800394a: f003 0303 and.w r3, r3, #3 + 800394e: 2b02 cmp r3, #2 + 8003950: d123 bne.n 800399a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; - 800390a: 697b ldr r3, [r7, #20] - 800390c: 08da lsrs r2, r3, #3 - 800390e: 687b ldr r3, [r7, #4] - 8003910: 3208 adds r2, #8 - 8003912: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8003916: 613b str r3, [r7, #16] + 8003952: 697b ldr r3, [r7, #20] + 8003954: 08da lsrs r2, r3, #3 + 8003956: 687b ldr r3, [r7, #4] + 8003958: 3208 adds r2, #8 + 800395a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800395e: 613b str r3, [r7, #16] temp &= ~(0xFU << ((position & 0x07U) * 4U)); - 8003918: 697b ldr r3, [r7, #20] - 800391a: f003 0307 and.w r3, r3, #7 - 800391e: 009b lsls r3, r3, #2 - 8003920: 220f movs r2, #15 - 8003922: fa02 f303 lsl.w r3, r2, r3 - 8003926: 43db mvns r3, r3 - 8003928: 693a ldr r2, [r7, #16] - 800392a: 4013 ands r3, r2 - 800392c: 613b str r3, [r7, #16] + 8003960: 697b ldr r3, [r7, #20] + 8003962: f003 0307 and.w r3, r3, #7 + 8003966: 009b lsls r3, r3, #2 + 8003968: 220f movs r2, #15 + 800396a: fa02 f303 lsl.w r3, r2, r3 + 800396e: 43db mvns r3, r3 + 8003970: 693a ldr r2, [r7, #16] + 8003972: 4013 ands r3, r2 + 8003974: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); - 800392e: 683b ldr r3, [r7, #0] - 8003930: 691a ldr r2, [r3, #16] - 8003932: 697b ldr r3, [r7, #20] - 8003934: f003 0307 and.w r3, r3, #7 - 8003938: 009b lsls r3, r3, #2 - 800393a: fa02 f303 lsl.w r3, r2, r3 - 800393e: 693a ldr r2, [r7, #16] - 8003940: 4313 orrs r3, r2 - 8003942: 613b str r3, [r7, #16] + 8003976: 683b ldr r3, [r7, #0] + 8003978: 691a ldr r2, [r3, #16] + 800397a: 697b ldr r3, [r7, #20] + 800397c: f003 0307 and.w r3, r3, #7 + 8003980: 009b lsls r3, r3, #2 + 8003982: fa02 f303 lsl.w r3, r2, r3 + 8003986: 693a ldr r2, [r7, #16] + 8003988: 4313 orrs r3, r2 + 800398a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3U] = temp; - 8003944: 697b ldr r3, [r7, #20] - 8003946: 08da lsrs r2, r3, #3 - 8003948: 687b ldr r3, [r7, #4] - 800394a: 3208 adds r2, #8 - 800394c: 6939 ldr r1, [r7, #16] - 800394e: f843 1022 str.w r1, [r3, r2, lsl #2] + 800398c: 697b ldr r3, [r7, #20] + 800398e: 08da lsrs r2, r3, #3 + 8003990: 687b ldr r3, [r7, #4] + 8003992: 3208 adds r2, #8 + 8003994: 6939 ldr r1, [r7, #16] + 8003996: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8003952: 687b ldr r3, [r7, #4] - 8003954: 681b ldr r3, [r3, #0] - 8003956: 613b str r3, [r7, #16] + 800399a: 687b ldr r3, [r7, #4] + 800399c: 681b ldr r3, [r3, #0] + 800399e: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); - 8003958: 697b ldr r3, [r7, #20] - 800395a: 005b lsls r3, r3, #1 - 800395c: 2203 movs r2, #3 - 800395e: fa02 f303 lsl.w r3, r2, r3 - 8003962: 43db mvns r3, r3 - 8003964: 693a ldr r2, [r7, #16] - 8003966: 4013 ands r3, r2 - 8003968: 613b str r3, [r7, #16] + 80039a0: 697b ldr r3, [r7, #20] + 80039a2: 005b lsls r3, r3, #1 + 80039a4: 2203 movs r2, #3 + 80039a6: fa02 f303 lsl.w r3, r2, r3 + 80039aa: 43db mvns r3, r3 + 80039ac: 693a ldr r2, [r7, #16] + 80039ae: 4013 ands r3, r2 + 80039b0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - 800396a: 683b ldr r3, [r7, #0] - 800396c: 685b ldr r3, [r3, #4] - 800396e: f003 0203 and.w r2, r3, #3 - 8003972: 697b ldr r3, [r7, #20] - 8003974: 005b lsls r3, r3, #1 - 8003976: fa02 f303 lsl.w r3, r2, r3 - 800397a: 693a ldr r2, [r7, #16] - 800397c: 4313 orrs r3, r2 - 800397e: 613b str r3, [r7, #16] + 80039b2: 683b ldr r3, [r7, #0] + 80039b4: 685b ldr r3, [r3, #4] + 80039b6: f003 0203 and.w r2, r3, #3 + 80039ba: 697b ldr r3, [r7, #20] + 80039bc: 005b lsls r3, r3, #1 + 80039be: fa02 f303 lsl.w r3, r2, r3 + 80039c2: 693a ldr r2, [r7, #16] + 80039c4: 4313 orrs r3, r2 + 80039c6: 613b str r3, [r7, #16] GPIOx->MODER = temp; - 8003980: 687b ldr r3, [r7, #4] - 8003982: 693a ldr r2, [r7, #16] - 8003984: 601a str r2, [r3, #0] + 80039c8: 687b ldr r3, [r7, #4] + 80039ca: 693a ldr r2, [r7, #16] + 80039cc: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) - 8003986: 683b ldr r3, [r7, #0] - 8003988: 685b ldr r3, [r3, #4] - 800398a: f403 3340 and.w r3, r3, #196608 @ 0x30000 - 800398e: 2b00 cmp r3, #0 - 8003990: f000 80a6 beq.w 8003ae0 + 80039ce: 683b ldr r3, [r7, #0] + 80039d0: 685b ldr r3, [r3, #4] + 80039d2: f403 3340 and.w r3, r3, #196608 @ 0x30000 + 80039d6: 2b00 cmp r3, #0 + 80039d8: f000 80a6 beq.w 8003b28 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8003994: 4b5b ldr r3, [pc, #364] @ (8003b04 ) - 8003996: 6e1b ldr r3, [r3, #96] @ 0x60 - 8003998: 4a5a ldr r2, [pc, #360] @ (8003b04 ) - 800399a: f043 0301 orr.w r3, r3, #1 - 800399e: 6613 str r3, [r2, #96] @ 0x60 - 80039a0: 4b58 ldr r3, [pc, #352] @ (8003b04 ) - 80039a2: 6e1b ldr r3, [r3, #96] @ 0x60 - 80039a4: f003 0301 and.w r3, r3, #1 - 80039a8: 60bb str r3, [r7, #8] - 80039aa: 68bb ldr r3, [r7, #8] + 80039dc: 4b5b ldr r3, [pc, #364] @ (8003b4c ) + 80039de: 6e1b ldr r3, [r3, #96] @ 0x60 + 80039e0: 4a5a ldr r2, [pc, #360] @ (8003b4c ) + 80039e2: f043 0301 orr.w r3, r3, #1 + 80039e6: 6613 str r3, [r2, #96] @ 0x60 + 80039e8: 4b58 ldr r3, [pc, #352] @ (8003b4c ) + 80039ea: 6e1b ldr r3, [r3, #96] @ 0x60 + 80039ec: f003 0301 and.w r3, r3, #1 + 80039f0: 60bb str r3, [r7, #8] + 80039f2: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2U]; - 80039ac: 4a56 ldr r2, [pc, #344] @ (8003b08 ) - 80039ae: 697b ldr r3, [r7, #20] - 80039b0: 089b lsrs r3, r3, #2 - 80039b2: 3302 adds r3, #2 - 80039b4: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 80039b8: 613b str r3, [r7, #16] + 80039f4: 4a56 ldr r2, [pc, #344] @ (8003b50 ) + 80039f6: 697b ldr r3, [r7, #20] + 80039f8: 089b lsrs r3, r3, #2 + 80039fa: 3302 adds r3, #2 + 80039fc: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8003a00: 613b str r3, [r7, #16] temp &= ~(0x0FUL << (4U * (position & 0x03U))); - 80039ba: 697b ldr r3, [r7, #20] - 80039bc: f003 0303 and.w r3, r3, #3 - 80039c0: 009b lsls r3, r3, #2 - 80039c2: 220f movs r2, #15 - 80039c4: fa02 f303 lsl.w r3, r2, r3 - 80039c8: 43db mvns r3, r3 - 80039ca: 693a ldr r2, [r7, #16] - 80039cc: 4013 ands r3, r2 - 80039ce: 613b str r3, [r7, #16] + 8003a02: 697b ldr r3, [r7, #20] + 8003a04: f003 0303 and.w r3, r3, #3 + 8003a08: 009b lsls r3, r3, #2 + 8003a0a: 220f movs r2, #15 + 8003a0c: fa02 f303 lsl.w r3, r2, r3 + 8003a10: 43db mvns r3, r3 + 8003a12: 693a ldr r2, [r7, #16] + 8003a14: 4013 ands r3, r2 + 8003a16: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); - 80039d0: 687b ldr r3, [r7, #4] - 80039d2: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 - 80039d6: d01f beq.n 8003a18 - 80039d8: 687b ldr r3, [r7, #4] - 80039da: 4a4c ldr r2, [pc, #304] @ (8003b0c ) - 80039dc: 4293 cmp r3, r2 - 80039de: d019 beq.n 8003a14 - 80039e0: 687b ldr r3, [r7, #4] - 80039e2: 4a4b ldr r2, [pc, #300] @ (8003b10 ) - 80039e4: 4293 cmp r3, r2 - 80039e6: d013 beq.n 8003a10 - 80039e8: 687b ldr r3, [r7, #4] - 80039ea: 4a4a ldr r2, [pc, #296] @ (8003b14 ) - 80039ec: 4293 cmp r3, r2 - 80039ee: d00d beq.n 8003a0c - 80039f0: 687b ldr r3, [r7, #4] - 80039f2: 4a49 ldr r2, [pc, #292] @ (8003b18 ) - 80039f4: 4293 cmp r3, r2 - 80039f6: d007 beq.n 8003a08 - 80039f8: 687b ldr r3, [r7, #4] - 80039fa: 4a48 ldr r2, [pc, #288] @ (8003b1c ) - 80039fc: 4293 cmp r3, r2 - 80039fe: d101 bne.n 8003a04 - 8003a00: 2305 movs r3, #5 - 8003a02: e00a b.n 8003a1a - 8003a04: 2306 movs r3, #6 - 8003a06: e008 b.n 8003a1a - 8003a08: 2304 movs r3, #4 - 8003a0a: e006 b.n 8003a1a - 8003a0c: 2303 movs r3, #3 - 8003a0e: e004 b.n 8003a1a - 8003a10: 2302 movs r3, #2 - 8003a12: e002 b.n 8003a1a - 8003a14: 2301 movs r3, #1 - 8003a16: e000 b.n 8003a1a - 8003a18: 2300 movs r3, #0 - 8003a1a: 697a ldr r2, [r7, #20] - 8003a1c: f002 0203 and.w r2, r2, #3 - 8003a20: 0092 lsls r2, r2, #2 - 8003a22: 4093 lsls r3, r2 - 8003a24: 693a ldr r2, [r7, #16] - 8003a26: 4313 orrs r3, r2 - 8003a28: 613b str r3, [r7, #16] + 8003a18: 687b ldr r3, [r7, #4] + 8003a1a: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000 + 8003a1e: d01f beq.n 8003a60 + 8003a20: 687b ldr r3, [r7, #4] + 8003a22: 4a4c ldr r2, [pc, #304] @ (8003b54 ) + 8003a24: 4293 cmp r3, r2 + 8003a26: d019 beq.n 8003a5c + 8003a28: 687b ldr r3, [r7, #4] + 8003a2a: 4a4b ldr r2, [pc, #300] @ (8003b58 ) + 8003a2c: 4293 cmp r3, r2 + 8003a2e: d013 beq.n 8003a58 + 8003a30: 687b ldr r3, [r7, #4] + 8003a32: 4a4a ldr r2, [pc, #296] @ (8003b5c ) + 8003a34: 4293 cmp r3, r2 + 8003a36: d00d beq.n 8003a54 + 8003a38: 687b ldr r3, [r7, #4] + 8003a3a: 4a49 ldr r2, [pc, #292] @ (8003b60 ) + 8003a3c: 4293 cmp r3, r2 + 8003a3e: d007 beq.n 8003a50 + 8003a40: 687b ldr r3, [r7, #4] + 8003a42: 4a48 ldr r2, [pc, #288] @ (8003b64 ) + 8003a44: 4293 cmp r3, r2 + 8003a46: d101 bne.n 8003a4c + 8003a48: 2305 movs r3, #5 + 8003a4a: e00a b.n 8003a62 + 8003a4c: 2306 movs r3, #6 + 8003a4e: e008 b.n 8003a62 + 8003a50: 2304 movs r3, #4 + 8003a52: e006 b.n 8003a62 + 8003a54: 2303 movs r3, #3 + 8003a56: e004 b.n 8003a62 + 8003a58: 2302 movs r3, #2 + 8003a5a: e002 b.n 8003a62 + 8003a5c: 2301 movs r3, #1 + 8003a5e: e000 b.n 8003a62 + 8003a60: 2300 movs r3, #0 + 8003a62: 697a ldr r2, [r7, #20] + 8003a64: f002 0203 and.w r2, r2, #3 + 8003a68: 0092 lsls r2, r2, #2 + 8003a6a: 4093 lsls r3, r2 + 8003a6c: 693a ldr r2, [r7, #16] + 8003a6e: 4313 orrs r3, r2 + 8003a70: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2U] = temp; - 8003a2a: 4937 ldr r1, [pc, #220] @ (8003b08 ) - 8003a2c: 697b ldr r3, [r7, #20] - 8003a2e: 089b lsrs r3, r3, #2 - 8003a30: 3302 adds r3, #2 - 8003a32: 693a ldr r2, [r7, #16] - 8003a34: f841 2023 str.w r2, [r1, r3, lsl #2] + 8003a72: 4937 ldr r1, [pc, #220] @ (8003b50 ) + 8003a74: 697b ldr r3, [r7, #20] + 8003a76: 089b lsrs r3, r3, #2 + 8003a78: 3302 adds r3, #2 + 8003a7a: 693a ldr r2, [r7, #16] + 8003a7c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; - 8003a38: 4b39 ldr r3, [pc, #228] @ (8003b20 ) - 8003a3a: 689b ldr r3, [r3, #8] - 8003a3c: 613b str r3, [r7, #16] + 8003a80: 4b39 ldr r3, [pc, #228] @ (8003b68 ) + 8003a82: 689b ldr r3, [r3, #8] + 8003a84: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8003a3e: 68fb ldr r3, [r7, #12] - 8003a40: 43db mvns r3, r3 - 8003a42: 693a ldr r2, [r7, #16] - 8003a44: 4013 ands r3, r2 - 8003a46: 613b str r3, [r7, #16] + 8003a86: 68fb ldr r3, [r7, #12] + 8003a88: 43db mvns r3, r3 + 8003a8a: 693a ldr r2, [r7, #16] + 8003a8c: 4013 ands r3, r2 + 8003a8e: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) - 8003a48: 683b ldr r3, [r7, #0] - 8003a4a: 685b ldr r3, [r3, #4] - 8003a4c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8003a50: 2b00 cmp r3, #0 - 8003a52: d003 beq.n 8003a5c + 8003a90: 683b ldr r3, [r7, #0] + 8003a92: 685b ldr r3, [r3, #4] + 8003a94: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8003a98: 2b00 cmp r3, #0 + 8003a9a: d003 beq.n 8003aa4 { temp |= iocurrent; - 8003a54: 693a ldr r2, [r7, #16] - 8003a56: 68fb ldr r3, [r7, #12] - 8003a58: 4313 orrs r3, r2 - 8003a5a: 613b str r3, [r7, #16] + 8003a9c: 693a ldr r2, [r7, #16] + 8003a9e: 68fb ldr r3, [r7, #12] + 8003aa0: 4313 orrs r3, r2 + 8003aa2: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; - 8003a5c: 4a30 ldr r2, [pc, #192] @ (8003b20 ) - 8003a5e: 693b ldr r3, [r7, #16] - 8003a60: 6093 str r3, [r2, #8] + 8003aa4: 4a30 ldr r2, [pc, #192] @ (8003b68 ) + 8003aa6: 693b ldr r3, [r7, #16] + 8003aa8: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; - 8003a62: 4b2f ldr r3, [pc, #188] @ (8003b20 ) - 8003a64: 68db ldr r3, [r3, #12] - 8003a66: 613b str r3, [r7, #16] + 8003aaa: 4b2f ldr r3, [pc, #188] @ (8003b68 ) + 8003aac: 68db ldr r3, [r3, #12] + 8003aae: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8003a68: 68fb ldr r3, [r7, #12] - 8003a6a: 43db mvns r3, r3 - 8003a6c: 693a ldr r2, [r7, #16] - 8003a6e: 4013 ands r3, r2 - 8003a70: 613b str r3, [r7, #16] + 8003ab0: 68fb ldr r3, [r7, #12] + 8003ab2: 43db mvns r3, r3 + 8003ab4: 693a ldr r2, [r7, #16] + 8003ab6: 4013 ands r3, r2 + 8003ab8: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) - 8003a72: 683b ldr r3, [r7, #0] - 8003a74: 685b ldr r3, [r3, #4] - 8003a76: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 8003a7a: 2b00 cmp r3, #0 - 8003a7c: d003 beq.n 8003a86 + 8003aba: 683b ldr r3, [r7, #0] + 8003abc: 685b ldr r3, [r3, #4] + 8003abe: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8003ac2: 2b00 cmp r3, #0 + 8003ac4: d003 beq.n 8003ace { temp |= iocurrent; - 8003a7e: 693a ldr r2, [r7, #16] - 8003a80: 68fb ldr r3, [r7, #12] - 8003a82: 4313 orrs r3, r2 - 8003a84: 613b str r3, [r7, #16] + 8003ac6: 693a ldr r2, [r7, #16] + 8003ac8: 68fb ldr r3, [r7, #12] + 8003aca: 4313 orrs r3, r2 + 8003acc: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; - 8003a86: 4a26 ldr r2, [pc, #152] @ (8003b20 ) - 8003a88: 693b ldr r3, [r7, #16] - 8003a8a: 60d3 str r3, [r2, #12] + 8003ace: 4a26 ldr r2, [pc, #152] @ (8003b68 ) + 8003ad0: 693b ldr r3, [r7, #16] + 8003ad2: 60d3 str r3, [r2, #12] temp = EXTI->EMR1; - 8003a8c: 4b24 ldr r3, [pc, #144] @ (8003b20 ) - 8003a8e: 685b ldr r3, [r3, #4] - 8003a90: 613b str r3, [r7, #16] + 8003ad4: 4b24 ldr r3, [pc, #144] @ (8003b68 ) + 8003ad6: 685b ldr r3, [r3, #4] + 8003ad8: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8003a92: 68fb ldr r3, [r7, #12] - 8003a94: 43db mvns r3, r3 - 8003a96: 693a ldr r2, [r7, #16] - 8003a98: 4013 ands r3, r2 - 8003a9a: 613b str r3, [r7, #16] + 8003ada: 68fb ldr r3, [r7, #12] + 8003adc: 43db mvns r3, r3 + 8003ade: 693a ldr r2, [r7, #16] + 8003ae0: 4013 ands r3, r2 + 8003ae2: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) - 8003a9c: 683b ldr r3, [r7, #0] - 8003a9e: 685b ldr r3, [r3, #4] - 8003aa0: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003aa4: 2b00 cmp r3, #0 - 8003aa6: d003 beq.n 8003ab0 + 8003ae4: 683b ldr r3, [r7, #0] + 8003ae6: 685b ldr r3, [r3, #4] + 8003ae8: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003aec: 2b00 cmp r3, #0 + 8003aee: d003 beq.n 8003af8 { temp |= iocurrent; - 8003aa8: 693a ldr r2, [r7, #16] - 8003aaa: 68fb ldr r3, [r7, #12] - 8003aac: 4313 orrs r3, r2 - 8003aae: 613b str r3, [r7, #16] + 8003af0: 693a ldr r2, [r7, #16] + 8003af2: 68fb ldr r3, [r7, #12] + 8003af4: 4313 orrs r3, r2 + 8003af6: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; - 8003ab0: 4a1b ldr r2, [pc, #108] @ (8003b20 ) - 8003ab2: 693b ldr r3, [r7, #16] - 8003ab4: 6053 str r3, [r2, #4] + 8003af8: 4a1b ldr r2, [pc, #108] @ (8003b68 ) + 8003afa: 693b ldr r3, [r7, #16] + 8003afc: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR1; - 8003ab6: 4b1a ldr r3, [pc, #104] @ (8003b20 ) - 8003ab8: 681b ldr r3, [r3, #0] - 8003aba: 613b str r3, [r7, #16] + 8003afe: 4b1a ldr r3, [pc, #104] @ (8003b68 ) + 8003b00: 681b ldr r3, [r3, #0] + 8003b02: 613b str r3, [r7, #16] temp &= ~(iocurrent); - 8003abc: 68fb ldr r3, [r7, #12] - 8003abe: 43db mvns r3, r3 - 8003ac0: 693a ldr r2, [r7, #16] - 8003ac2: 4013 ands r3, r2 - 8003ac4: 613b str r3, [r7, #16] + 8003b04: 68fb ldr r3, [r7, #12] + 8003b06: 43db mvns r3, r3 + 8003b08: 693a ldr r2, [r7, #16] + 8003b0a: 4013 ands r3, r2 + 8003b0c: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) - 8003ac6: 683b ldr r3, [r7, #0] - 8003ac8: 685b ldr r3, [r3, #4] - 8003aca: f403 3380 and.w r3, r3, #65536 @ 0x10000 - 8003ace: 2b00 cmp r3, #0 - 8003ad0: d003 beq.n 8003ada + 8003b0e: 683b ldr r3, [r7, #0] + 8003b10: 685b ldr r3, [r3, #4] + 8003b12: f403 3380 and.w r3, r3, #65536 @ 0x10000 + 8003b16: 2b00 cmp r3, #0 + 8003b18: d003 beq.n 8003b22 { temp |= iocurrent; - 8003ad2: 693a ldr r2, [r7, #16] - 8003ad4: 68fb ldr r3, [r7, #12] - 8003ad6: 4313 orrs r3, r2 - 8003ad8: 613b str r3, [r7, #16] + 8003b1a: 693a ldr r2, [r7, #16] + 8003b1c: 68fb ldr r3, [r7, #12] + 8003b1e: 4313 orrs r3, r2 + 8003b20: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; - 8003ada: 4a11 ldr r2, [pc, #68] @ (8003b20 ) - 8003adc: 693b ldr r3, [r7, #16] - 8003ade: 6013 str r3, [r2, #0] + 8003b22: 4a11 ldr r2, [pc, #68] @ (8003b68 ) + 8003b24: 693b ldr r3, [r7, #16] + 8003b26: 6013 str r3, [r2, #0] } } position++; - 8003ae0: 697b ldr r3, [r7, #20] - 8003ae2: 3301 adds r3, #1 - 8003ae4: 617b str r3, [r7, #20] + 8003b28: 697b ldr r3, [r7, #20] + 8003b2a: 3301 adds r3, #1 + 8003b2c: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0U) - 8003ae6: 683b ldr r3, [r7, #0] - 8003ae8: 681a ldr r2, [r3, #0] - 8003aea: 697b ldr r3, [r7, #20] - 8003aec: fa22 f303 lsr.w r3, r2, r3 - 8003af0: 2b00 cmp r3, #0 - 8003af2: f47f ae9d bne.w 8003830 + 8003b2e: 683b ldr r3, [r7, #0] + 8003b30: 681a ldr r2, [r3, #0] + 8003b32: 697b ldr r3, [r7, #20] + 8003b34: fa22 f303 lsr.w r3, r2, r3 + 8003b38: 2b00 cmp r3, #0 + 8003b3a: f47f ae9d bne.w 8003878 } } - 8003af6: bf00 nop - 8003af8: bf00 nop - 8003afa: 371c adds r7, #28 - 8003afc: 46bd mov sp, r7 - 8003afe: f85d 7b04 ldr.w r7, [sp], #4 - 8003b02: 4770 bx lr - 8003b04: 40021000 .word 0x40021000 - 8003b08: 40010000 .word 0x40010000 - 8003b0c: 48000400 .word 0x48000400 - 8003b10: 48000800 .word 0x48000800 - 8003b14: 48000c00 .word 0x48000c00 - 8003b18: 48001000 .word 0x48001000 - 8003b1c: 48001400 .word 0x48001400 - 8003b20: 40010400 .word 0x40010400 + 8003b3e: bf00 nop + 8003b40: bf00 nop + 8003b42: 371c adds r7, #28 + 8003b44: 46bd mov sp, r7 + 8003b46: f85d 7b04 ldr.w r7, [sp], #4 + 8003b4a: 4770 bx lr + 8003b4c: 40021000 .word 0x40021000 + 8003b50: 40010000 .word 0x40010000 + 8003b54: 48000400 .word 0x48000400 + 8003b58: 48000800 .word 0x48000800 + 8003b5c: 48000c00 .word 0x48000c00 + 8003b60: 48001000 .word 0x48001000 + 8003b64: 48001400 .word 0x48001400 + 8003b68: 40010400 .word 0x40010400 -08003b24 : +08003b6c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8003b24: b480 push {r7} - 8003b26: b083 sub sp, #12 - 8003b28: af00 add r7, sp, #0 - 8003b2a: 6078 str r0, [r7, #4] - 8003b2c: 460b mov r3, r1 - 8003b2e: 807b strh r3, [r7, #2] - 8003b30: 4613 mov r3, r2 - 8003b32: 707b strb r3, [r7, #1] + 8003b6c: b480 push {r7} + 8003b6e: b083 sub sp, #12 + 8003b70: af00 add r7, sp, #0 + 8003b72: 6078 str r0, [r7, #4] + 8003b74: 460b mov r3, r1 + 8003b76: 807b strh r3, [r7, #2] + 8003b78: 4613 mov r3, r2 + 8003b7a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) - 8003b34: 787b ldrb r3, [r7, #1] - 8003b36: 2b00 cmp r3, #0 - 8003b38: d003 beq.n 8003b42 + 8003b7c: 787b ldrb r3, [r7, #1] + 8003b7e: 2b00 cmp r3, #0 + 8003b80: d003 beq.n 8003b8a { GPIOx->BSRR = (uint32_t)GPIO_Pin; - 8003b3a: 887a ldrh r2, [r7, #2] - 8003b3c: 687b ldr r3, [r7, #4] - 8003b3e: 619a str r2, [r3, #24] + 8003b82: 887a ldrh r2, [r7, #2] + 8003b84: 687b ldr r3, [r7, #4] + 8003b86: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } - 8003b40: e002 b.n 8003b48 + 8003b88: e002 b.n 8003b90 GPIOx->BRR = (uint32_t)GPIO_Pin; - 8003b42: 887a ldrh r2, [r7, #2] - 8003b44: 687b ldr r3, [r7, #4] - 8003b46: 629a str r2, [r3, #40] @ 0x28 + 8003b8a: 887a ldrh r2, [r7, #2] + 8003b8c: 687b ldr r3, [r7, #4] + 8003b8e: 629a str r2, [r3, #40] @ 0x28 } - 8003b48: bf00 nop - 8003b4a: 370c adds r7, #12 - 8003b4c: 46bd mov sp, r7 - 8003b4e: f85d 7b04 ldr.w r7, [sp], #4 - 8003b52: 4770 bx lr + 8003b90: bf00 nop + 8003b92: 370c adds r7, #12 + 8003b94: 46bd mov sp, r7 + 8003b96: f85d 7b04 ldr.w r7, [sp], #4 + 8003b9a: 4770 bx lr -08003b54 : +08003b9c : * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { - 8003b54: b480 push {r7} - 8003b56: b085 sub sp, #20 - 8003b58: af00 add r7, sp, #0 - 8003b5a: 6078 str r0, [r7, #4] + 8003b9c: b480 push {r7} + 8003b9e: b085 sub sp, #20 + 8003ba0: af00 add r7, sp, #0 + 8003ba2: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) - 8003b5c: 687b ldr r3, [r7, #4] - 8003b5e: 2b00 cmp r3, #0 - 8003b60: d141 bne.n 8003be6 + 8003ba4: 687b ldr r3, [r7, #4] + 8003ba6: 2b00 cmp r3, #0 + 8003ba8: d141 bne.n 8003c2e { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - 8003b62: 4b4b ldr r3, [pc, #300] @ (8003c90 ) - 8003b64: 681b ldr r3, [r3, #0] - 8003b66: f403 63c0 and.w r3, r3, #1536 @ 0x600 - 8003b6a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8003b6e: d131 bne.n 8003bd4 + 8003baa: 4b4b ldr r3, [pc, #300] @ (8003cd8 ) + 8003bac: 681b ldr r3, [r3, #0] + 8003bae: f403 63c0 and.w r3, r3, #1536 @ 0x600 + 8003bb2: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003bb6: d131 bne.n 8003c1c { /* Make sure Range 1 Boost is enabled */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - 8003b70: 4b47 ldr r3, [pc, #284] @ (8003c90 ) - 8003b72: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8003b76: 4a46 ldr r2, [pc, #280] @ (8003c90 ) - 8003b78: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8003b7c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + 8003bb8: 4b47 ldr r3, [pc, #284] @ (8003cd8 ) + 8003bba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8003bbe: 4a46 ldr r2, [pc, #280] @ (8003cd8 ) + 8003bc0: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8003bc4: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - 8003b80: 4b43 ldr r3, [pc, #268] @ (8003c90 ) - 8003b82: 681b ldr r3, [r3, #0] - 8003b84: f423 63c0 bic.w r3, r3, #1536 @ 0x600 - 8003b88: 4a41 ldr r2, [pc, #260] @ (8003c90 ) - 8003b8a: f443 7300 orr.w r3, r3, #512 @ 0x200 - 8003b8e: 6013 str r3, [r2, #0] + 8003bc8: 4b43 ldr r3, [pc, #268] @ (8003cd8 ) + 8003bca: 681b ldr r3, [r3, #0] + 8003bcc: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8003bd0: 4a41 ldr r2, [pc, #260] @ (8003cd8 ) + 8003bd2: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8003bd6: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; - 8003b90: 4b40 ldr r3, [pc, #256] @ (8003c94 ) - 8003b92: 681b ldr r3, [r3, #0] - 8003b94: 2232 movs r2, #50 @ 0x32 - 8003b96: fb02 f303 mul.w r3, r2, r3 - 8003b9a: 4a3f ldr r2, [pc, #252] @ (8003c98 ) - 8003b9c: fba2 2303 umull r2, r3, r2, r3 - 8003ba0: 0c9b lsrs r3, r3, #18 - 8003ba2: 3301 adds r3, #1 - 8003ba4: 60fb str r3, [r7, #12] + 8003bd8: 4b40 ldr r3, [pc, #256] @ (8003cdc ) + 8003bda: 681b ldr r3, [r3, #0] + 8003bdc: 2232 movs r2, #50 @ 0x32 + 8003bde: fb02 f303 mul.w r3, r2, r3 + 8003be2: 4a3f ldr r2, [pc, #252] @ (8003ce0 ) + 8003be4: fba2 2303 umull r2, r3, r2, r3 + 8003be8: 0c9b lsrs r3, r3, #18 + 8003bea: 3301 adds r3, #1 + 8003bec: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) - 8003ba6: e002 b.n 8003bae + 8003bee: e002 b.n 8003bf6 { wait_loop_index--; - 8003ba8: 68fb ldr r3, [r7, #12] - 8003baa: 3b01 subs r3, #1 - 8003bac: 60fb str r3, [r7, #12] + 8003bf0: 68fb ldr r3, [r7, #12] + 8003bf2: 3b01 subs r3, #1 + 8003bf4: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) - 8003bae: 4b38 ldr r3, [pc, #224] @ (8003c90 ) - 8003bb0: 695b ldr r3, [r3, #20] - 8003bb2: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003bb6: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8003bba: d102 bne.n 8003bc2 - 8003bbc: 68fb ldr r3, [r7, #12] - 8003bbe: 2b00 cmp r3, #0 - 8003bc0: d1f2 bne.n 8003ba8 + 8003bf6: 4b38 ldr r3, [pc, #224] @ (8003cd8 ) + 8003bf8: 695b ldr r3, [r3, #20] + 8003bfa: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003bfe: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003c02: d102 bne.n 8003c0a + 8003c04: 68fb ldr r3, [r7, #12] + 8003c06: 2b00 cmp r3, #0 + 8003c08: d1f2 bne.n 8003bf0 } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - 8003bc2: 4b33 ldr r3, [pc, #204] @ (8003c90 ) - 8003bc4: 695b ldr r3, [r3, #20] - 8003bc6: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003bca: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8003bce: d158 bne.n 8003c82 + 8003c0a: 4b33 ldr r3, [pc, #204] @ (8003cd8 ) + 8003c0c: 695b ldr r3, [r3, #20] + 8003c0e: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003c12: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003c16: d158 bne.n 8003cca { return HAL_TIMEOUT; - 8003bd0: 2303 movs r3, #3 - 8003bd2: e057 b.n 8003c84 + 8003c18: 2303 movs r3, #3 + 8003c1a: e057 b.n 8003ccc } /* If current range is range 1 normal or boost mode */ else { /* Enable Range 1 Boost (no issue if bit already reset) */ CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - 8003bd4: 4b2e ldr r3, [pc, #184] @ (8003c90 ) - 8003bd6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8003bda: 4a2d ldr r2, [pc, #180] @ (8003c90 ) - 8003bdc: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8003be0: f8c2 3080 str.w r3, [r2, #128] @ 0x80 - 8003be4: e04d b.n 8003c82 + 8003c1c: 4b2e ldr r3, [pc, #184] @ (8003cd8 ) + 8003c1e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8003c22: 4a2d ldr r2, [pc, #180] @ (8003cd8 ) + 8003c24: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8003c28: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + 8003c2c: e04d b.n 8003cca } } else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) - 8003be6: 687b ldr r3, [r7, #4] - 8003be8: f5b3 7f00 cmp.w r3, #512 @ 0x200 - 8003bec: d141 bne.n 8003c72 + 8003c2e: 687b ldr r3, [r7, #4] + 8003c30: f5b3 7f00 cmp.w r3, #512 @ 0x200 + 8003c34: d141 bne.n 8003cba { /* If current range is range 2 */ if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - 8003bee: 4b28 ldr r3, [pc, #160] @ (8003c90 ) - 8003bf0: 681b ldr r3, [r3, #0] - 8003bf2: f403 63c0 and.w r3, r3, #1536 @ 0x600 - 8003bf6: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8003bfa: d131 bne.n 8003c60 + 8003c36: 4b28 ldr r3, [pc, #160] @ (8003cd8 ) + 8003c38: 681b ldr r3, [r3, #0] + 8003c3a: f403 63c0 and.w r3, r3, #1536 @ 0x600 + 8003c3e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003c42: d131 bne.n 8003ca8 { /* Make sure Range 1 Boost is disabled */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - 8003bfc: 4b24 ldr r3, [pc, #144] @ (8003c90 ) - 8003bfe: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8003c02: 4a23 ldr r2, [pc, #140] @ (8003c90 ) - 8003c04: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8003c08: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + 8003c44: 4b24 ldr r3, [pc, #144] @ (8003cd8 ) + 8003c46: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8003c4a: 4a23 ldr r2, [pc, #140] @ (8003cd8 ) + 8003c4c: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8003c50: f8c2 3080 str.w r3, [r2, #128] @ 0x80 /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - 8003c0c: 4b20 ldr r3, [pc, #128] @ (8003c90 ) - 8003c0e: 681b ldr r3, [r3, #0] - 8003c10: f423 63c0 bic.w r3, r3, #1536 @ 0x600 - 8003c14: 4a1e ldr r2, [pc, #120] @ (8003c90 ) - 8003c16: f443 7300 orr.w r3, r3, #512 @ 0x200 - 8003c1a: 6013 str r3, [r2, #0] + 8003c54: 4b20 ldr r3, [pc, #128] @ (8003cd8 ) + 8003c56: 681b ldr r3, [r3, #0] + 8003c58: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8003c5c: 4a1e ldr r2, [pc, #120] @ (8003cd8 ) + 8003c5e: f443 7300 orr.w r3, r3, #512 @ 0x200 + 8003c62: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U; - 8003c1c: 4b1d ldr r3, [pc, #116] @ (8003c94 ) - 8003c1e: 681b ldr r3, [r3, #0] - 8003c20: 2232 movs r2, #50 @ 0x32 - 8003c22: fb02 f303 mul.w r3, r2, r3 - 8003c26: 4a1c ldr r2, [pc, #112] @ (8003c98 ) - 8003c28: fba2 2303 umull r2, r3, r2, r3 - 8003c2c: 0c9b lsrs r3, r3, #18 - 8003c2e: 3301 adds r3, #1 - 8003c30: 60fb str r3, [r7, #12] + 8003c64: 4b1d ldr r3, [pc, #116] @ (8003cdc ) + 8003c66: 681b ldr r3, [r3, #0] + 8003c68: 2232 movs r2, #50 @ 0x32 + 8003c6a: fb02 f303 mul.w r3, r2, r3 + 8003c6e: 4a1c ldr r2, [pc, #112] @ (8003ce0 ) + 8003c70: fba2 2303 umull r2, r3, r2, r3 + 8003c74: 0c9b lsrs r3, r3, #18 + 8003c76: 3301 adds r3, #1 + 8003c78: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) - 8003c32: e002 b.n 8003c3a + 8003c7a: e002 b.n 8003c82 { wait_loop_index--; - 8003c34: 68fb ldr r3, [r7, #12] - 8003c36: 3b01 subs r3, #1 - 8003c38: 60fb str r3, [r7, #12] + 8003c7c: 68fb ldr r3, [r7, #12] + 8003c7e: 3b01 subs r3, #1 + 8003c80: 60fb str r3, [r7, #12] while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U)) - 8003c3a: 4b15 ldr r3, [pc, #84] @ (8003c90 ) - 8003c3c: 695b ldr r3, [r3, #20] - 8003c3e: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003c42: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8003c46: d102 bne.n 8003c4e - 8003c48: 68fb ldr r3, [r7, #12] - 8003c4a: 2b00 cmp r3, #0 - 8003c4c: d1f2 bne.n 8003c34 + 8003c82: 4b15 ldr r3, [pc, #84] @ (8003cd8 ) + 8003c84: 695b ldr r3, [r3, #20] + 8003c86: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003c8a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003c8e: d102 bne.n 8003c96 + 8003c90: 68fb ldr r3, [r7, #12] + 8003c92: 2b00 cmp r3, #0 + 8003c94: d1f2 bne.n 8003c7c } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - 8003c4e: 4b10 ldr r3, [pc, #64] @ (8003c90 ) - 8003c50: 695b ldr r3, [r3, #20] - 8003c52: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003c56: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8003c5a: d112 bne.n 8003c82 + 8003c96: 4b10 ldr r3, [pc, #64] @ (8003cd8 ) + 8003c98: 695b ldr r3, [r3, #20] + 8003c9a: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003c9e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8003ca2: d112 bne.n 8003cca { return HAL_TIMEOUT; - 8003c5c: 2303 movs r3, #3 - 8003c5e: e011 b.n 8003c84 + 8003ca4: 2303 movs r3, #3 + 8003ca6: e011 b.n 8003ccc } /* If current range is range 1 normal or boost mode */ else { /* Disable Range 1 Boost (no issue if bit already set) */ SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - 8003c60: 4b0b ldr r3, [pc, #44] @ (8003c90 ) - 8003c62: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8003c66: 4a0a ldr r2, [pc, #40] @ (8003c90 ) - 8003c68: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8003c6c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 - 8003c70: e007 b.n 8003c82 + 8003ca8: 4b0b ldr r3, [pc, #44] @ (8003cd8 ) + 8003caa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8003cae: 4a0a ldr r2, [pc, #40] @ (8003cd8 ) + 8003cb0: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8003cb4: f8c2 3080 str.w r3, [r2, #128] @ 0x80 + 8003cb8: e007 b.n 8003cca } } else { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); - 8003c72: 4b07 ldr r3, [pc, #28] @ (8003c90 ) - 8003c74: 681b ldr r3, [r3, #0] - 8003c76: f423 63c0 bic.w r3, r3, #1536 @ 0x600 - 8003c7a: 4a05 ldr r2, [pc, #20] @ (8003c90 ) - 8003c7c: f443 6380 orr.w r3, r3, #1024 @ 0x400 - 8003c80: 6013 str r3, [r2, #0] + 8003cba: 4b07 ldr r3, [pc, #28] @ (8003cd8 ) + 8003cbc: 681b ldr r3, [r3, #0] + 8003cbe: f423 63c0 bic.w r3, r3, #1536 @ 0x600 + 8003cc2: 4a05 ldr r2, [pc, #20] @ (8003cd8 ) + 8003cc4: f443 6380 orr.w r3, r3, #1024 @ 0x400 + 8003cc8: 6013 str r3, [r2, #0] /* No need to wait for VOSF to be cleared for this transition */ /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ } return HAL_OK; - 8003c82: 2300 movs r3, #0 + 8003cca: 2300 movs r3, #0 } - 8003c84: 4618 mov r0, r3 - 8003c86: 3714 adds r7, #20 - 8003c88: 46bd mov sp, r7 - 8003c8a: f85d 7b04 ldr.w r7, [sp], #4 - 8003c8e: 4770 bx lr - 8003c90: 40007000 .word 0x40007000 - 8003c94: 20000014 .word 0x20000014 - 8003c98: 431bde83 .word 0x431bde83 + 8003ccc: 4618 mov r0, r3 + 8003cce: 3714 adds r7, #20 + 8003cd0: 46bd mov sp, r7 + 8003cd2: f85d 7b04 ldr.w r7, [sp], #4 + 8003cd6: 4770 bx lr + 8003cd8: 40007000 .word 0x40007000 + 8003cdc: 20000018 .word 0x20000018 + 8003ce0: 431bde83 .word 0x431bde83 -08003c9c : +08003ce4 : * or to hand over control to the UCPD (which should therefore be * initialized before doing the disable). * @retval None */ void HAL_PWREx_DisableUCPDDeadBattery(void) { - 8003c9c: b480 push {r7} - 8003c9e: af00 add r7, sp, #0 + 8003ce4: b480 push {r7} + 8003ce6: af00 add r7, sp, #0 /* Write 1 to disable the USB Type-C dead battery pull-down behavior */ SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS); - 8003ca0: 4b05 ldr r3, [pc, #20] @ (8003cb8 ) - 8003ca2: 689b ldr r3, [r3, #8] - 8003ca4: 4a04 ldr r2, [pc, #16] @ (8003cb8 ) - 8003ca6: f443 4380 orr.w r3, r3, #16384 @ 0x4000 - 8003caa: 6093 str r3, [r2, #8] + 8003ce8: 4b05 ldr r3, [pc, #20] @ (8003d00 ) + 8003cea: 689b ldr r3, [r3, #8] + 8003cec: 4a04 ldr r2, [pc, #16] @ (8003d00 ) + 8003cee: f443 4380 orr.w r3, r3, #16384 @ 0x4000 + 8003cf2: 6093 str r3, [r2, #8] } - 8003cac: bf00 nop - 8003cae: 46bd mov sp, r7 - 8003cb0: f85d 7b04 ldr.w r7, [sp], #4 - 8003cb4: 4770 bx lr - 8003cb6: bf00 nop - 8003cb8: 40007000 .word 0x40007000 + 8003cf4: bf00 nop + 8003cf6: 46bd mov sp, r7 + 8003cf8: f85d 7b04 ldr.w r7, [sp], #4 + 8003cfc: 4770 bx lr + 8003cfe: bf00 nop + 8003d00: 40007000 .word 0x40007000 -08003cbc : +08003d04 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8003cbc: b580 push {r7, lr} - 8003cbe: b088 sub sp, #32 - 8003cc0: af00 add r7, sp, #0 - 8003cc2: 6078 str r0, [r7, #4] + 8003d04: b580 push {r7, lr} + 8003d06: b088 sub sp, #32 + 8003d08: af00 add r7, sp, #0 + 8003d0a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 8003cc4: 687b ldr r3, [r7, #4] - 8003cc6: 2b00 cmp r3, #0 - 8003cc8: d101 bne.n 8003cce + 8003d0c: 687b ldr r3, [r7, #4] + 8003d0e: 2b00 cmp r3, #0 + 8003d10: d101 bne.n 8003d16 { return HAL_ERROR; - 8003cca: 2301 movs r3, #1 - 8003ccc: e2fe b.n 80042cc + 8003d12: 2301 movs r3, #1 + 8003d14: e2fe b.n 8004314 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8003cce: 687b ldr r3, [r7, #4] - 8003cd0: 681b ldr r3, [r3, #0] - 8003cd2: f003 0301 and.w r3, r3, #1 - 8003cd6: 2b00 cmp r3, #0 - 8003cd8: d075 beq.n 8003dc6 + 8003d16: 687b ldr r3, [r7, #4] + 8003d18: 681b ldr r3, [r3, #0] + 8003d1a: f003 0301 and.w r3, r3, #1 + 8003d1e: 2b00 cmp r3, #0 + 8003d20: d075 beq.n 8003e0e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8003cda: 4b97 ldr r3, [pc, #604] @ (8003f38 ) - 8003cdc: 689b ldr r3, [r3, #8] - 8003cde: f003 030c and.w r3, r3, #12 - 8003ce2: 61bb str r3, [r7, #24] + 8003d22: 4b97 ldr r3, [pc, #604] @ (8003f80 ) + 8003d24: 689b ldr r3, [r3, #8] + 8003d26: f003 030c and.w r3, r3, #12 + 8003d2a: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8003ce4: 4b94 ldr r3, [pc, #592] @ (8003f38 ) - 8003ce6: 68db ldr r3, [r3, #12] - 8003ce8: f003 0303 and.w r3, r3, #3 - 8003cec: 617b str r3, [r7, #20] + 8003d2c: 4b94 ldr r3, [pc, #592] @ (8003f80 ) + 8003d2e: 68db ldr r3, [r3, #12] + 8003d30: f003 0303 and.w r3, r3, #3 + 8003d34: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE)) - 8003cee: 69bb ldr r3, [r7, #24] - 8003cf0: 2b0c cmp r3, #12 - 8003cf2: d102 bne.n 8003cfa - 8003cf4: 697b ldr r3, [r7, #20] - 8003cf6: 2b03 cmp r3, #3 - 8003cf8: d002 beq.n 8003d00 - 8003cfa: 69bb ldr r3, [r7, #24] - 8003cfc: 2b08 cmp r3, #8 - 8003cfe: d10b bne.n 8003d18 + 8003d36: 69bb ldr r3, [r7, #24] + 8003d38: 2b0c cmp r3, #12 + 8003d3a: d102 bne.n 8003d42 + 8003d3c: 697b ldr r3, [r7, #20] + 8003d3e: 2b03 cmp r3, #3 + 8003d40: d002 beq.n 8003d48 + 8003d42: 69bb ldr r3, [r7, #24] + 8003d44: 2b08 cmp r3, #8 + 8003d46: d10b bne.n 8003d60 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8003d00: 4b8d ldr r3, [pc, #564] @ (8003f38 ) - 8003d02: 681b ldr r3, [r3, #0] - 8003d04: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003d08: 2b00 cmp r3, #0 - 8003d0a: d05b beq.n 8003dc4 - 8003d0c: 687b ldr r3, [r7, #4] - 8003d0e: 685b ldr r3, [r3, #4] - 8003d10: 2b00 cmp r3, #0 - 8003d12: d157 bne.n 8003dc4 + 8003d48: 4b8d ldr r3, [pc, #564] @ (8003f80 ) + 8003d4a: 681b ldr r3, [r3, #0] + 8003d4c: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003d50: 2b00 cmp r3, #0 + 8003d52: d05b beq.n 8003e0c + 8003d54: 687b ldr r3, [r7, #4] + 8003d56: 685b ldr r3, [r3, #4] + 8003d58: 2b00 cmp r3, #0 + 8003d5a: d157 bne.n 8003e0c { return HAL_ERROR; - 8003d14: 2301 movs r3, #1 - 8003d16: e2d9 b.n 80042cc + 8003d5c: 2301 movs r3, #1 + 8003d5e: e2d9 b.n 8004314 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8003d18: 687b ldr r3, [r7, #4] - 8003d1a: 685b ldr r3, [r3, #4] - 8003d1c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8003d20: d106 bne.n 8003d30 - 8003d22: 4b85 ldr r3, [pc, #532] @ (8003f38 ) - 8003d24: 681b ldr r3, [r3, #0] - 8003d26: 4a84 ldr r2, [pc, #528] @ (8003f38 ) - 8003d28: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8003d2c: 6013 str r3, [r2, #0] - 8003d2e: e01d b.n 8003d6c - 8003d30: 687b ldr r3, [r7, #4] - 8003d32: 685b ldr r3, [r3, #4] - 8003d34: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 - 8003d38: d10c bne.n 8003d54 - 8003d3a: 4b7f ldr r3, [pc, #508] @ (8003f38 ) - 8003d3c: 681b ldr r3, [r3, #0] - 8003d3e: 4a7e ldr r2, [pc, #504] @ (8003f38 ) - 8003d40: f443 2380 orr.w r3, r3, #262144 @ 0x40000 - 8003d44: 6013 str r3, [r2, #0] - 8003d46: 4b7c ldr r3, [pc, #496] @ (8003f38 ) - 8003d48: 681b ldr r3, [r3, #0] - 8003d4a: 4a7b ldr r2, [pc, #492] @ (8003f38 ) - 8003d4c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8003d50: 6013 str r3, [r2, #0] - 8003d52: e00b b.n 8003d6c - 8003d54: 4b78 ldr r3, [pc, #480] @ (8003f38 ) - 8003d56: 681b ldr r3, [r3, #0] - 8003d58: 4a77 ldr r2, [pc, #476] @ (8003f38 ) - 8003d5a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 8003d5e: 6013 str r3, [r2, #0] - 8003d60: 4b75 ldr r3, [pc, #468] @ (8003f38 ) - 8003d62: 681b ldr r3, [r3, #0] - 8003d64: 4a74 ldr r2, [pc, #464] @ (8003f38 ) - 8003d66: f423 2380 bic.w r3, r3, #262144 @ 0x40000 - 8003d6a: 6013 str r3, [r2, #0] + 8003d60: 687b ldr r3, [r7, #4] + 8003d62: 685b ldr r3, [r3, #4] + 8003d64: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8003d68: d106 bne.n 8003d78 + 8003d6a: 4b85 ldr r3, [pc, #532] @ (8003f80 ) + 8003d6c: 681b ldr r3, [r3, #0] + 8003d6e: 4a84 ldr r2, [pc, #528] @ (8003f80 ) + 8003d70: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003d74: 6013 str r3, [r2, #0] + 8003d76: e01d b.n 8003db4 + 8003d78: 687b ldr r3, [r7, #4] + 8003d7a: 685b ldr r3, [r3, #4] + 8003d7c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 + 8003d80: d10c bne.n 8003d9c + 8003d82: 4b7f ldr r3, [pc, #508] @ (8003f80 ) + 8003d84: 681b ldr r3, [r3, #0] + 8003d86: 4a7e ldr r2, [pc, #504] @ (8003f80 ) + 8003d88: f443 2380 orr.w r3, r3, #262144 @ 0x40000 + 8003d8c: 6013 str r3, [r2, #0] + 8003d8e: 4b7c ldr r3, [pc, #496] @ (8003f80 ) + 8003d90: 681b ldr r3, [r3, #0] + 8003d92: 4a7b ldr r2, [pc, #492] @ (8003f80 ) + 8003d94: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8003d98: 6013 str r3, [r2, #0] + 8003d9a: e00b b.n 8003db4 + 8003d9c: 4b78 ldr r3, [pc, #480] @ (8003f80 ) + 8003d9e: 681b ldr r3, [r3, #0] + 8003da0: 4a77 ldr r2, [pc, #476] @ (8003f80 ) + 8003da2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8003da6: 6013 str r3, [r2, #0] + 8003da8: 4b75 ldr r3, [pc, #468] @ (8003f80 ) + 8003daa: 681b ldr r3, [r3, #0] + 8003dac: 4a74 ldr r2, [pc, #464] @ (8003f80 ) + 8003dae: f423 2380 bic.w r3, r3, #262144 @ 0x40000 + 8003db2: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8003d6c: 687b ldr r3, [r7, #4] - 8003d6e: 685b ldr r3, [r3, #4] - 8003d70: 2b00 cmp r3, #0 - 8003d72: d013 beq.n 8003d9c + 8003db4: 687b ldr r3, [r7, #4] + 8003db6: 685b ldr r3, [r3, #4] + 8003db8: 2b00 cmp r3, #0 + 8003dba: d013 beq.n 8003de4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003d74: f7fd feba bl 8001aec - 8003d78: 6138 str r0, [r7, #16] + 8003dbc: f7fd feba bl 8001b34 + 8003dc0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8003d7a: e008 b.n 8003d8e + 8003dc2: e008 b.n 8003dd6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8003d7c: f7fd feb6 bl 8001aec - 8003d80: 4602 mov r2, r0 - 8003d82: 693b ldr r3, [r7, #16] - 8003d84: 1ad3 subs r3, r2, r3 - 8003d86: 2b64 cmp r3, #100 @ 0x64 - 8003d88: d901 bls.n 8003d8e + 8003dc4: f7fd feb6 bl 8001b34 + 8003dc8: 4602 mov r2, r0 + 8003dca: 693b ldr r3, [r7, #16] + 8003dcc: 1ad3 subs r3, r2, r3 + 8003dce: 2b64 cmp r3, #100 @ 0x64 + 8003dd0: d901 bls.n 8003dd6 { return HAL_TIMEOUT; - 8003d8a: 2303 movs r3, #3 - 8003d8c: e29e b.n 80042cc + 8003dd2: 2303 movs r3, #3 + 8003dd4: e29e b.n 8004314 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8003d8e: 4b6a ldr r3, [pc, #424] @ (8003f38 ) - 8003d90: 681b ldr r3, [r3, #0] - 8003d92: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003d96: 2b00 cmp r3, #0 - 8003d98: d0f0 beq.n 8003d7c - 8003d9a: e014 b.n 8003dc6 + 8003dd6: 4b6a ldr r3, [pc, #424] @ (8003f80 ) + 8003dd8: 681b ldr r3, [r3, #0] + 8003dda: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003dde: 2b00 cmp r3, #0 + 8003de0: d0f0 beq.n 8003dc4 + 8003de2: e014 b.n 8003e0e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003d9c: f7fd fea6 bl 8001aec - 8003da0: 6138 str r0, [r7, #16] + 8003de4: f7fd fea6 bl 8001b34 + 8003de8: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 8003da2: e008 b.n 8003db6 + 8003dea: e008 b.n 8003dfe { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8003da4: f7fd fea2 bl 8001aec - 8003da8: 4602 mov r2, r0 - 8003daa: 693b ldr r3, [r7, #16] - 8003dac: 1ad3 subs r3, r2, r3 - 8003dae: 2b64 cmp r3, #100 @ 0x64 - 8003db0: d901 bls.n 8003db6 + 8003dec: f7fd fea2 bl 8001b34 + 8003df0: 4602 mov r2, r0 + 8003df2: 693b ldr r3, [r7, #16] + 8003df4: 1ad3 subs r3, r2, r3 + 8003df6: 2b64 cmp r3, #100 @ 0x64 + 8003df8: d901 bls.n 8003dfe { return HAL_TIMEOUT; - 8003db2: 2303 movs r3, #3 - 8003db4: e28a b.n 80042cc + 8003dfa: 2303 movs r3, #3 + 8003dfc: e28a b.n 8004314 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - 8003db6: 4b60 ldr r3, [pc, #384] @ (8003f38 ) - 8003db8: 681b ldr r3, [r3, #0] - 8003dba: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 8003dbe: 2b00 cmp r3, #0 - 8003dc0: d1f0 bne.n 8003da4 - 8003dc2: e000 b.n 8003dc6 + 8003dfe: 4b60 ldr r3, [pc, #384] @ (8003f80 ) + 8003e00: 681b ldr r3, [r3, #0] + 8003e02: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 8003e06: 2b00 cmp r3, #0 + 8003e08: d1f0 bne.n 8003dec + 8003e0a: e000 b.n 8003e0e if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8003dc4: bf00 nop + 8003e0c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8003dc6: 687b ldr r3, [r7, #4] - 8003dc8: 681b ldr r3, [r3, #0] - 8003dca: f003 0302 and.w r3, r3, #2 - 8003dce: 2b00 cmp r3, #0 - 8003dd0: d075 beq.n 8003ebe + 8003e0e: 687b ldr r3, [r7, #4] + 8003e10: 681b ldr r3, [r3, #0] + 8003e12: f003 0302 and.w r3, r3, #2 + 8003e16: 2b00 cmp r3, #0 + 8003e18: d075 beq.n 8003f06 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8003dd2: 4b59 ldr r3, [pc, #356] @ (8003f38 ) - 8003dd4: 689b ldr r3, [r3, #8] - 8003dd6: f003 030c and.w r3, r3, #12 - 8003dda: 61bb str r3, [r7, #24] + 8003e1a: 4b59 ldr r3, [pc, #356] @ (8003f80 ) + 8003e1c: 689b ldr r3, [r3, #8] + 8003e1e: f003 030c and.w r3, r3, #12 + 8003e22: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8003ddc: 4b56 ldr r3, [pc, #344] @ (8003f38 ) - 8003dde: 68db ldr r3, [r3, #12] - 8003de0: f003 0303 and.w r3, r3, #3 - 8003de4: 617b str r3, [r7, #20] + 8003e24: 4b56 ldr r3, [pc, #344] @ (8003f80 ) + 8003e26: 68db ldr r3, [r3, #12] + 8003e28: f003 0303 and.w r3, r3, #3 + 8003e2c: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI)) - 8003de6: 69bb ldr r3, [r7, #24] - 8003de8: 2b0c cmp r3, #12 - 8003dea: d102 bne.n 8003df2 - 8003dec: 697b ldr r3, [r7, #20] - 8003dee: 2b02 cmp r3, #2 - 8003df0: d002 beq.n 8003df8 - 8003df2: 69bb ldr r3, [r7, #24] - 8003df4: 2b04 cmp r3, #4 - 8003df6: d11f bne.n 8003e38 + 8003e2e: 69bb ldr r3, [r7, #24] + 8003e30: 2b0c cmp r3, #12 + 8003e32: d102 bne.n 8003e3a + 8003e34: 697b ldr r3, [r7, #20] + 8003e36: 2b02 cmp r3, #2 + 8003e38: d002 beq.n 8003e40 + 8003e3a: 69bb ldr r3, [r7, #24] + 8003e3c: 2b04 cmp r3, #4 + 8003e3e: d11f bne.n 8003e80 { /* When HSI is used as system clock it will not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) - 8003df8: 4b4f ldr r3, [pc, #316] @ (8003f38 ) - 8003dfa: 681b ldr r3, [r3, #0] - 8003dfc: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003e00: 2b00 cmp r3, #0 - 8003e02: d005 beq.n 8003e10 - 8003e04: 687b ldr r3, [r7, #4] - 8003e06: 68db ldr r3, [r3, #12] - 8003e08: 2b00 cmp r3, #0 - 8003e0a: d101 bne.n 8003e10 + 8003e40: 4b4f ldr r3, [pc, #316] @ (8003f80 ) + 8003e42: 681b ldr r3, [r3, #0] + 8003e44: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003e48: 2b00 cmp r3, #0 + 8003e4a: d005 beq.n 8003e58 + 8003e4c: 687b ldr r3, [r7, #4] + 8003e4e: 68db ldr r3, [r3, #12] + 8003e50: 2b00 cmp r3, #0 + 8003e52: d101 bne.n 8003e58 { return HAL_ERROR; - 8003e0c: 2301 movs r3, #1 - 8003e0e: e25d b.n 80042cc + 8003e54: 2301 movs r3, #1 + 8003e56: e25d b.n 8004314 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8003e10: 4b49 ldr r3, [pc, #292] @ (8003f38 ) - 8003e12: 685b ldr r3, [r3, #4] - 8003e14: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 - 8003e18: 687b ldr r3, [r7, #4] - 8003e1a: 691b ldr r3, [r3, #16] - 8003e1c: 061b lsls r3, r3, #24 - 8003e1e: 4946 ldr r1, [pc, #280] @ (8003f38 ) - 8003e20: 4313 orrs r3, r2 - 8003e22: 604b str r3, [r1, #4] + 8003e58: 4b49 ldr r3, [pc, #292] @ (8003f80 ) + 8003e5a: 685b ldr r3, [r3, #4] + 8003e5c: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 + 8003e60: 687b ldr r3, [r7, #4] + 8003e62: 691b ldr r3, [r3, #16] + 8003e64: 061b lsls r3, r3, #24 + 8003e66: 4946 ldr r1, [pc, #280] @ (8003f80 ) + 8003e68: 4313 orrs r3, r2 + 8003e6a: 604b str r3, [r1, #4] /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) - 8003e24: 4b45 ldr r3, [pc, #276] @ (8003f3c ) - 8003e26: 681b ldr r3, [r3, #0] - 8003e28: 4618 mov r0, r3 - 8003e2a: f7fd fe13 bl 8001a54 - 8003e2e: 4603 mov r3, r0 - 8003e30: 2b00 cmp r3, #0 - 8003e32: d043 beq.n 8003ebc + 8003e6c: 4b45 ldr r3, [pc, #276] @ (8003f84 ) + 8003e6e: 681b ldr r3, [r3, #0] + 8003e70: 4618 mov r0, r3 + 8003e72: f7fd fe13 bl 8001a9c + 8003e76: 4603 mov r3, r0 + 8003e78: 2b00 cmp r3, #0 + 8003e7a: d043 beq.n 8003f04 { return HAL_ERROR; - 8003e34: 2301 movs r3, #1 - 8003e36: e249 b.n 80042cc + 8003e7c: 2301 movs r3, #1 + 8003e7e: e249 b.n 8004314 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8003e38: 687b ldr r3, [r7, #4] - 8003e3a: 68db ldr r3, [r3, #12] - 8003e3c: 2b00 cmp r3, #0 - 8003e3e: d023 beq.n 8003e88 + 8003e80: 687b ldr r3, [r7, #4] + 8003e82: 68db ldr r3, [r3, #12] + 8003e84: 2b00 cmp r3, #0 + 8003e86: d023 beq.n 8003ed0 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8003e40: 4b3d ldr r3, [pc, #244] @ (8003f38 ) - 8003e42: 681b ldr r3, [r3, #0] - 8003e44: 4a3c ldr r2, [pc, #240] @ (8003f38 ) - 8003e46: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8003e4a: 6013 str r3, [r2, #0] + 8003e88: 4b3d ldr r3, [pc, #244] @ (8003f80 ) + 8003e8a: 681b ldr r3, [r3, #0] + 8003e8c: 4a3c ldr r2, [pc, #240] @ (8003f80 ) + 8003e8e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8003e92: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003e4c: f7fd fe4e bl 8001aec - 8003e50: 6138 str r0, [r7, #16] + 8003e94: f7fd fe4e bl 8001b34 + 8003e98: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8003e52: e008 b.n 8003e66 + 8003e9a: e008 b.n 8003eae { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8003e54: f7fd fe4a bl 8001aec - 8003e58: 4602 mov r2, r0 - 8003e5a: 693b ldr r3, [r7, #16] - 8003e5c: 1ad3 subs r3, r2, r3 - 8003e5e: 2b02 cmp r3, #2 - 8003e60: d901 bls.n 8003e66 + 8003e9c: f7fd fe4a bl 8001b34 + 8003ea0: 4602 mov r2, r0 + 8003ea2: 693b ldr r3, [r7, #16] + 8003ea4: 1ad3 subs r3, r2, r3 + 8003ea6: 2b02 cmp r3, #2 + 8003ea8: d901 bls.n 8003eae { return HAL_TIMEOUT; - 8003e62: 2303 movs r3, #3 - 8003e64: e232 b.n 80042cc + 8003eaa: 2303 movs r3, #3 + 8003eac: e232 b.n 8004314 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 8003e66: 4b34 ldr r3, [pc, #208] @ (8003f38 ) - 8003e68: 681b ldr r3, [r3, #0] - 8003e6a: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003e6e: 2b00 cmp r3, #0 - 8003e70: d0f0 beq.n 8003e54 + 8003eae: 4b34 ldr r3, [pc, #208] @ (8003f80 ) + 8003eb0: 681b ldr r3, [r3, #0] + 8003eb2: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003eb6: 2b00 cmp r3, #0 + 8003eb8: d0f0 beq.n 8003e9c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8003e72: 4b31 ldr r3, [pc, #196] @ (8003f38 ) - 8003e74: 685b ldr r3, [r3, #4] - 8003e76: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 - 8003e7a: 687b ldr r3, [r7, #4] - 8003e7c: 691b ldr r3, [r3, #16] - 8003e7e: 061b lsls r3, r3, #24 - 8003e80: 492d ldr r1, [pc, #180] @ (8003f38 ) - 8003e82: 4313 orrs r3, r2 - 8003e84: 604b str r3, [r1, #4] - 8003e86: e01a b.n 8003ebe + 8003eba: 4b31 ldr r3, [pc, #196] @ (8003f80 ) + 8003ebc: 685b ldr r3, [r3, #4] + 8003ebe: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 + 8003ec2: 687b ldr r3, [r7, #4] + 8003ec4: 691b ldr r3, [r3, #16] + 8003ec6: 061b lsls r3, r3, #24 + 8003ec8: 492d ldr r1, [pc, #180] @ (8003f80 ) + 8003eca: 4313 orrs r3, r2 + 8003ecc: 604b str r3, [r1, #4] + 8003ece: e01a b.n 8003f06 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 8003e88: 4b2b ldr r3, [pc, #172] @ (8003f38 ) - 8003e8a: 681b ldr r3, [r3, #0] - 8003e8c: 4a2a ldr r2, [pc, #168] @ (8003f38 ) - 8003e8e: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8003e92: 6013 str r3, [r2, #0] + 8003ed0: 4b2b ldr r3, [pc, #172] @ (8003f80 ) + 8003ed2: 681b ldr r3, [r3, #0] + 8003ed4: 4a2a ldr r2, [pc, #168] @ (8003f80 ) + 8003ed6: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8003eda: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003e94: f7fd fe2a bl 8001aec - 8003e98: 6138 str r0, [r7, #16] + 8003edc: f7fd fe2a bl 8001b34 + 8003ee0: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 8003e9a: e008 b.n 8003eae + 8003ee2: e008 b.n 8003ef6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8003e9c: f7fd fe26 bl 8001aec - 8003ea0: 4602 mov r2, r0 - 8003ea2: 693b ldr r3, [r7, #16] - 8003ea4: 1ad3 subs r3, r2, r3 - 8003ea6: 2b02 cmp r3, #2 - 8003ea8: d901 bls.n 8003eae + 8003ee4: f7fd fe26 bl 8001b34 + 8003ee8: 4602 mov r2, r0 + 8003eea: 693b ldr r3, [r7, #16] + 8003eec: 1ad3 subs r3, r2, r3 + 8003eee: 2b02 cmp r3, #2 + 8003ef0: d901 bls.n 8003ef6 { return HAL_TIMEOUT; - 8003eaa: 2303 movs r3, #3 - 8003eac: e20e b.n 80042cc + 8003ef2: 2303 movs r3, #3 + 8003ef4: e20e b.n 8004314 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - 8003eae: 4b22 ldr r3, [pc, #136] @ (8003f38 ) - 8003eb0: 681b ldr r3, [r3, #0] - 8003eb2: f403 6380 and.w r3, r3, #1024 @ 0x400 - 8003eb6: 2b00 cmp r3, #0 - 8003eb8: d1f0 bne.n 8003e9c - 8003eba: e000 b.n 8003ebe + 8003ef6: 4b22 ldr r3, [pc, #136] @ (8003f80 ) + 8003ef8: 681b ldr r3, [r3, #0] + 8003efa: f403 6380 and.w r3, r3, #1024 @ 0x400 + 8003efe: 2b00 cmp r3, #0 + 8003f00: d1f0 bne.n 8003ee4 + 8003f02: e000 b.n 8003f06 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) - 8003ebc: bf00 nop + 8003f04: bf00 nop } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8003ebe: 687b ldr r3, [r7, #4] - 8003ec0: 681b ldr r3, [r3, #0] - 8003ec2: f003 0308 and.w r3, r3, #8 - 8003ec6: 2b00 cmp r3, #0 - 8003ec8: d041 beq.n 8003f4e + 8003f06: 687b ldr r3, [r7, #4] + 8003f08: 681b ldr r3, [r3, #0] + 8003f0a: f003 0308 and.w r3, r3, #8 + 8003f0e: 2b00 cmp r3, #0 + 8003f10: d041 beq.n 8003f96 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8003eca: 687b ldr r3, [r7, #4] - 8003ecc: 695b ldr r3, [r3, #20] - 8003ece: 2b00 cmp r3, #0 - 8003ed0: d01c beq.n 8003f0c + 8003f12: 687b ldr r3, [r7, #4] + 8003f14: 695b ldr r3, [r3, #20] + 8003f16: 2b00 cmp r3, #0 + 8003f18: d01c beq.n 8003f54 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8003ed2: 4b19 ldr r3, [pc, #100] @ (8003f38 ) - 8003ed4: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 - 8003ed8: 4a17 ldr r2, [pc, #92] @ (8003f38 ) - 8003eda: f043 0301 orr.w r3, r3, #1 - 8003ede: f8c2 3094 str.w r3, [r2, #148] @ 0x94 + 8003f1a: 4b19 ldr r3, [pc, #100] @ (8003f80 ) + 8003f1c: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003f20: 4a17 ldr r2, [pc, #92] @ (8003f80 ) + 8003f22: f043 0301 orr.w r3, r3, #1 + 8003f26: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003ee2: f7fd fe03 bl 8001aec - 8003ee6: 6138 str r0, [r7, #16] + 8003f2a: f7fd fe03 bl 8001b34 + 8003f2e: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) - 8003ee8: e008 b.n 8003efc + 8003f30: e008 b.n 8003f44 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8003eea: f7fd fdff bl 8001aec - 8003eee: 4602 mov r2, r0 - 8003ef0: 693b ldr r3, [r7, #16] - 8003ef2: 1ad3 subs r3, r2, r3 - 8003ef4: 2b02 cmp r3, #2 - 8003ef6: d901 bls.n 8003efc + 8003f32: f7fd fdff bl 8001b34 + 8003f36: 4602 mov r2, r0 + 8003f38: 693b ldr r3, [r7, #16] + 8003f3a: 1ad3 subs r3, r2, r3 + 8003f3c: 2b02 cmp r3, #2 + 8003f3e: d901 bls.n 8003f44 { return HAL_TIMEOUT; - 8003ef8: 2303 movs r3, #3 - 8003efa: e1e7 b.n 80042cc + 8003f40: 2303 movs r3, #3 + 8003f42: e1e7 b.n 8004314 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) - 8003efc: 4b0e ldr r3, [pc, #56] @ (8003f38 ) - 8003efe: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 - 8003f02: f003 0302 and.w r3, r3, #2 - 8003f06: 2b00 cmp r3, #0 - 8003f08: d0ef beq.n 8003eea - 8003f0a: e020 b.n 8003f4e + 8003f44: 4b0e ldr r3, [pc, #56] @ (8003f80 ) + 8003f46: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003f4a: f003 0302 and.w r3, r3, #2 + 8003f4e: 2b00 cmp r3, #0 + 8003f50: d0ef beq.n 8003f32 + 8003f52: e020 b.n 8003f96 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8003f0c: 4b0a ldr r3, [pc, #40] @ (8003f38 ) - 8003f0e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 - 8003f12: 4a09 ldr r2, [pc, #36] @ (8003f38 ) - 8003f14: f023 0301 bic.w r3, r3, #1 - 8003f18: f8c2 3094 str.w r3, [r2, #148] @ 0x94 + 8003f54: 4b0a ldr r3, [pc, #40] @ (8003f80 ) + 8003f56: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003f5a: 4a09 ldr r2, [pc, #36] @ (8003f80 ) + 8003f5c: f023 0301 bic.w r3, r3, #1 + 8003f60: f8c2 3094 str.w r3, [r2, #148] @ 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8003f1c: f7fd fde6 bl 8001aec - 8003f20: 6138 str r0, [r7, #16] + 8003f64: f7fd fde6 bl 8001b34 + 8003f68: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) - 8003f22: e00d b.n 8003f40 + 8003f6a: e00d b.n 8003f88 { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8003f24: f7fd fde2 bl 8001aec - 8003f28: 4602 mov r2, r0 - 8003f2a: 693b ldr r3, [r7, #16] - 8003f2c: 1ad3 subs r3, r2, r3 - 8003f2e: 2b02 cmp r3, #2 - 8003f30: d906 bls.n 8003f40 + 8003f6c: f7fd fde2 bl 8001b34 + 8003f70: 4602 mov r2, r0 + 8003f72: 693b ldr r3, [r7, #16] + 8003f74: 1ad3 subs r3, r2, r3 + 8003f76: 2b02 cmp r3, #2 + 8003f78: d906 bls.n 8003f88 { return HAL_TIMEOUT; - 8003f32: 2303 movs r3, #3 - 8003f34: e1ca b.n 80042cc - 8003f36: bf00 nop - 8003f38: 40021000 .word 0x40021000 - 8003f3c: 20000018 .word 0x20000018 + 8003f7a: 2303 movs r3, #3 + 8003f7c: e1ca b.n 8004314 + 8003f7e: bf00 nop + 8003f80: 40021000 .word 0x40021000 + 8003f84: 2000001c .word 0x2000001c while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) - 8003f40: 4b8c ldr r3, [pc, #560] @ (8004174 ) - 8003f42: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 - 8003f46: f003 0302 and.w r3, r3, #2 - 8003f4a: 2b00 cmp r3, #0 - 8003f4c: d1ea bne.n 8003f24 + 8003f88: 4b8c ldr r3, [pc, #560] @ (80041bc ) + 8003f8a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 + 8003f8e: f003 0302 and.w r3, r3, #2 + 8003f92: 2b00 cmp r3, #0 + 8003f94: d1ea bne.n 8003f6c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8003f4e: 687b ldr r3, [r7, #4] - 8003f50: 681b ldr r3, [r3, #0] - 8003f52: f003 0304 and.w r3, r3, #4 - 8003f56: 2b00 cmp r3, #0 - 8003f58: f000 80a6 beq.w 80040a8 + 8003f96: 687b ldr r3, [r7, #4] + 8003f98: 681b ldr r3, [r3, #0] + 8003f9a: f003 0304 and.w r3, r3, #4 + 8003f9e: 2b00 cmp r3, #0 + 8003fa0: f000 80a6 beq.w 80040f0 { FlagStatus pwrclkchanged = RESET; - 8003f5c: 2300 movs r3, #0 - 8003f5e: 77fb strb r3, [r7, #31] + 8003fa4: 2300 movs r3, #0 + 8003fa6: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain if necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) - 8003f60: 4b84 ldr r3, [pc, #528] @ (8004174 ) - 8003f62: 6d9b ldr r3, [r3, #88] @ 0x58 - 8003f64: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8003f68: 2b00 cmp r3, #0 - 8003f6a: d101 bne.n 8003f70 - 8003f6c: 2301 movs r3, #1 - 8003f6e: e000 b.n 8003f72 - 8003f70: 2300 movs r3, #0 - 8003f72: 2b00 cmp r3, #0 - 8003f74: d00d beq.n 8003f92 + 8003fa8: 4b84 ldr r3, [pc, #528] @ (80041bc ) + 8003faa: 6d9b ldr r3, [r3, #88] @ 0x58 + 8003fac: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8003fb0: 2b00 cmp r3, #0 + 8003fb2: d101 bne.n 8003fb8 + 8003fb4: 2301 movs r3, #1 + 8003fb6: e000 b.n 8003fba + 8003fb8: 2300 movs r3, #0 + 8003fba: 2b00 cmp r3, #0 + 8003fbc: d00d beq.n 8003fda { __HAL_RCC_PWR_CLK_ENABLE(); - 8003f76: 4b7f ldr r3, [pc, #508] @ (8004174 ) - 8003f78: 6d9b ldr r3, [r3, #88] @ 0x58 - 8003f7a: 4a7e ldr r2, [pc, #504] @ (8004174 ) - 8003f7c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8003f80: 6593 str r3, [r2, #88] @ 0x58 - 8003f82: 4b7c ldr r3, [pc, #496] @ (8004174 ) - 8003f84: 6d9b ldr r3, [r3, #88] @ 0x58 - 8003f86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8003f8a: 60fb str r3, [r7, #12] - 8003f8c: 68fb ldr r3, [r7, #12] + 8003fbe: 4b7f ldr r3, [pc, #508] @ (80041bc ) + 8003fc0: 6d9b ldr r3, [r3, #88] @ 0x58 + 8003fc2: 4a7e ldr r2, [pc, #504] @ (80041bc ) + 8003fc4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8003fc8: 6593 str r3, [r2, #88] @ 0x58 + 8003fca: 4b7c ldr r3, [pc, #496] @ (80041bc ) + 8003fcc: 6d9b ldr r3, [r3, #88] @ 0x58 + 8003fce: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8003fd2: 60fb str r3, [r7, #12] + 8003fd4: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; - 8003f8e: 2301 movs r3, #1 - 8003f90: 77fb strb r3, [r7, #31] + 8003fd6: 2301 movs r3, #1 + 8003fd8: 77fb strb r3, [r7, #31] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8003f92: 4b79 ldr r3, [pc, #484] @ (8004178 ) - 8003f94: 681b ldr r3, [r3, #0] - 8003f96: f403 7380 and.w r3, r3, #256 @ 0x100 - 8003f9a: 2b00 cmp r3, #0 - 8003f9c: d118 bne.n 8003fd0 + 8003fda: 4b79 ldr r3, [pc, #484] @ (80041c0 ) + 8003fdc: 681b ldr r3, [r3, #0] + 8003fde: f403 7380 and.w r3, r3, #256 @ 0x100 + 8003fe2: 2b00 cmp r3, #0 + 8003fe4: d118 bne.n 8004018 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); - 8003f9e: 4b76 ldr r3, [pc, #472] @ (8004178 ) - 8003fa0: 681b ldr r3, [r3, #0] - 8003fa2: 4a75 ldr r2, [pc, #468] @ (8004178 ) - 8003fa4: f443 7380 orr.w r3, r3, #256 @ 0x100 - 8003fa8: 6013 str r3, [r2, #0] + 8003fe6: 4b76 ldr r3, [pc, #472] @ (80041c0 ) + 8003fe8: 681b ldr r3, [r3, #0] + 8003fea: 4a75 ldr r2, [pc, #468] @ (80041c0 ) + 8003fec: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8003ff0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 8003faa: f7fd fd9f bl 8001aec - 8003fae: 6138 str r0, [r7, #16] + 8003ff2: f7fd fd9f bl 8001b34 + 8003ff6: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8003fb0: e008 b.n 8003fc4 + 8003ff8: e008 b.n 800400c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8003fb2: f7fd fd9b bl 8001aec - 8003fb6: 4602 mov r2, r0 - 8003fb8: 693b ldr r3, [r7, #16] - 8003fba: 1ad3 subs r3, r2, r3 - 8003fbc: 2b02 cmp r3, #2 - 8003fbe: d901 bls.n 8003fc4 + 8003ffa: f7fd fd9b bl 8001b34 + 8003ffe: 4602 mov r2, r0 + 8004000: 693b ldr r3, [r7, #16] + 8004002: 1ad3 subs r3, r2, r3 + 8004004: 2b02 cmp r3, #2 + 8004006: d901 bls.n 800400c { return HAL_TIMEOUT; - 8003fc0: 2303 movs r3, #3 - 8003fc2: e183 b.n 80042cc + 8004008: 2303 movs r3, #3 + 800400a: e183 b.n 8004314 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8003fc4: 4b6c ldr r3, [pc, #432] @ (8004178 ) - 8003fc6: 681b ldr r3, [r3, #0] - 8003fc8: f403 7380 and.w r3, r3, #256 @ 0x100 - 8003fcc: 2b00 cmp r3, #0 - 8003fce: d0f0 beq.n 8003fb2 + 800400c: 4b6c ldr r3, [pc, #432] @ (80041c0 ) + 800400e: 681b ldr r3, [r3, #0] + 8004010: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004014: 2b00 cmp r3, #0 + 8004016: d0f0 beq.n 8003ffa } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8003fd0: 687b ldr r3, [r7, #4] - 8003fd2: 689b ldr r3, [r3, #8] - 8003fd4: 2b01 cmp r3, #1 - 8003fd6: d108 bne.n 8003fea - 8003fd8: 4b66 ldr r3, [pc, #408] @ (8004174 ) - 8003fda: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8003fde: 4a65 ldr r2, [pc, #404] @ (8004174 ) - 8003fe0: f043 0301 orr.w r3, r3, #1 - 8003fe4: f8c2 3090 str.w r3, [r2, #144] @ 0x90 - 8003fe8: e024 b.n 8004034 - 8003fea: 687b ldr r3, [r7, #4] - 8003fec: 689b ldr r3, [r3, #8] - 8003fee: 2b05 cmp r3, #5 - 8003ff0: d110 bne.n 8004014 - 8003ff2: 4b60 ldr r3, [pc, #384] @ (8004174 ) - 8003ff4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8003ff8: 4a5e ldr r2, [pc, #376] @ (8004174 ) - 8003ffa: f043 0304 orr.w r3, r3, #4 - 8003ffe: f8c2 3090 str.w r3, [r2, #144] @ 0x90 - 8004002: 4b5c ldr r3, [pc, #368] @ (8004174 ) - 8004004: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8004008: 4a5a ldr r2, [pc, #360] @ (8004174 ) - 800400a: f043 0301 orr.w r3, r3, #1 - 800400e: f8c2 3090 str.w r3, [r2, #144] @ 0x90 - 8004012: e00f b.n 8004034 - 8004014: 4b57 ldr r3, [pc, #348] @ (8004174 ) - 8004016: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800401a: 4a56 ldr r2, [pc, #344] @ (8004174 ) - 800401c: f023 0301 bic.w r3, r3, #1 - 8004020: f8c2 3090 str.w r3, [r2, #144] @ 0x90 - 8004024: 4b53 ldr r3, [pc, #332] @ (8004174 ) - 8004026: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800402a: 4a52 ldr r2, [pc, #328] @ (8004174 ) - 800402c: f023 0304 bic.w r3, r3, #4 - 8004030: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 8004018: 687b ldr r3, [r7, #4] + 800401a: 689b ldr r3, [r3, #8] + 800401c: 2b01 cmp r3, #1 + 800401e: d108 bne.n 8004032 + 8004020: 4b66 ldr r3, [pc, #408] @ (80041bc ) + 8004022: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004026: 4a65 ldr r2, [pc, #404] @ (80041bc ) + 8004028: f043 0301 orr.w r3, r3, #1 + 800402c: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 8004030: e024 b.n 800407c + 8004032: 687b ldr r3, [r7, #4] + 8004034: 689b ldr r3, [r3, #8] + 8004036: 2b05 cmp r3, #5 + 8004038: d110 bne.n 800405c + 800403a: 4b60 ldr r3, [pc, #384] @ (80041bc ) + 800403c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004040: 4a5e ldr r2, [pc, #376] @ (80041bc ) + 8004042: f043 0304 orr.w r3, r3, #4 + 8004046: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 800404a: 4b5c ldr r3, [pc, #368] @ (80041bc ) + 800404c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004050: 4a5a ldr r2, [pc, #360] @ (80041bc ) + 8004052: f043 0301 orr.w r3, r3, #1 + 8004056: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 800405a: e00f b.n 800407c + 800405c: 4b57 ldr r3, [pc, #348] @ (80041bc ) + 800405e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004062: 4a56 ldr r2, [pc, #344] @ (80041bc ) + 8004064: f023 0301 bic.w r3, r3, #1 + 8004068: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 800406c: 4b53 ldr r3, [pc, #332] @ (80041bc ) + 800406e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004072: 4a52 ldr r2, [pc, #328] @ (80041bc ) + 8004074: f023 0304 bic.w r3, r3, #4 + 8004078: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 8004034: 687b ldr r3, [r7, #4] - 8004036: 689b ldr r3, [r3, #8] - 8004038: 2b00 cmp r3, #0 - 800403a: d016 beq.n 800406a + 800407c: 687b ldr r3, [r7, #4] + 800407e: 689b ldr r3, [r3, #8] + 8004080: 2b00 cmp r3, #0 + 8004082: d016 beq.n 80040b2 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800403c: f7fd fd56 bl 8001aec - 8004040: 6138 str r0, [r7, #16] + 8004084: f7fd fd56 bl 8001b34 + 8004088: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 8004042: e00a b.n 800405a + 800408a: e00a b.n 80040a2 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8004044: f7fd fd52 bl 8001aec - 8004048: 4602 mov r2, r0 - 800404a: 693b ldr r3, [r7, #16] - 800404c: 1ad3 subs r3, r2, r3 - 800404e: f241 3288 movw r2, #5000 @ 0x1388 - 8004052: 4293 cmp r3, r2 - 8004054: d901 bls.n 800405a + 800408c: f7fd fd52 bl 8001b34 + 8004090: 4602 mov r2, r0 + 8004092: 693b ldr r3, [r7, #16] + 8004094: 1ad3 subs r3, r2, r3 + 8004096: f241 3288 movw r2, #5000 @ 0x1388 + 800409a: 4293 cmp r3, r2 + 800409c: d901 bls.n 80040a2 { return HAL_TIMEOUT; - 8004056: 2303 movs r3, #3 - 8004058: e138 b.n 80042cc + 800409e: 2303 movs r3, #3 + 80040a0: e138 b.n 8004314 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 800405a: 4b46 ldr r3, [pc, #280] @ (8004174 ) - 800405c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8004060: f003 0302 and.w r3, r3, #2 - 8004064: 2b00 cmp r3, #0 - 8004066: d0ed beq.n 8004044 - 8004068: e015 b.n 8004096 + 80040a2: 4b46 ldr r3, [pc, #280] @ (80041bc ) + 80040a4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80040a8: f003 0302 and.w r3, r3, #2 + 80040ac: 2b00 cmp r3, #0 + 80040ae: d0ed beq.n 800408c + 80040b0: e015 b.n 80040de } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800406a: f7fd fd3f bl 8001aec - 800406e: 6138 str r0, [r7, #16] + 80040b2: f7fd fd3f bl 8001b34 + 80040b6: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) - 8004070: e00a b.n 8004088 + 80040b8: e00a b.n 80040d0 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8004072: f7fd fd3b bl 8001aec - 8004076: 4602 mov r2, r0 - 8004078: 693b ldr r3, [r7, #16] - 800407a: 1ad3 subs r3, r2, r3 - 800407c: f241 3288 movw r2, #5000 @ 0x1388 - 8004080: 4293 cmp r3, r2 - 8004082: d901 bls.n 8004088 + 80040ba: f7fd fd3b bl 8001b34 + 80040be: 4602 mov r2, r0 + 80040c0: 693b ldr r3, [r7, #16] + 80040c2: 1ad3 subs r3, r2, r3 + 80040c4: f241 3288 movw r2, #5000 @ 0x1388 + 80040c8: 4293 cmp r3, r2 + 80040ca: d901 bls.n 80040d0 { return HAL_TIMEOUT; - 8004084: 2303 movs r3, #3 - 8004086: e121 b.n 80042cc + 80040cc: 2303 movs r3, #3 + 80040ce: e121 b.n 8004314 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) - 8004088: 4b3a ldr r3, [pc, #232] @ (8004174 ) - 800408a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800408e: f003 0302 and.w r3, r3, #2 - 8004092: 2b00 cmp r3, #0 - 8004094: d1ed bne.n 8004072 + 80040d0: 4b3a ldr r3, [pc, #232] @ (80041bc ) + 80040d2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80040d6: f003 0302 and.w r3, r3, #2 + 80040da: 2b00 cmp r3, #0 + 80040dc: d1ed bne.n 80040ba } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 8004096: 7ffb ldrb r3, [r7, #31] - 8004098: 2b01 cmp r3, #1 - 800409a: d105 bne.n 80040a8 + 80040de: 7ffb ldrb r3, [r7, #31] + 80040e0: 2b01 cmp r3, #1 + 80040e2: d105 bne.n 80040f0 { __HAL_RCC_PWR_CLK_DISABLE(); - 800409c: 4b35 ldr r3, [pc, #212] @ (8004174 ) - 800409e: 6d9b ldr r3, [r3, #88] @ 0x58 - 80040a0: 4a34 ldr r2, [pc, #208] @ (8004174 ) - 80040a2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 80040a6: 6593 str r3, [r2, #88] @ 0x58 + 80040e4: 4b35 ldr r3, [pc, #212] @ (80041bc ) + 80040e6: 6d9b ldr r3, [r3, #88] @ 0x58 + 80040e8: 4a34 ldr r2, [pc, #208] @ (80041bc ) + 80040ea: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80040ee: 6593 str r3, [r2, #88] @ 0x58 } } /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - 80040a8: 687b ldr r3, [r7, #4] - 80040aa: 681b ldr r3, [r3, #0] - 80040ac: f003 0320 and.w r3, r3, #32 - 80040b0: 2b00 cmp r3, #0 - 80040b2: d03c beq.n 800412e + 80040f0: 687b ldr r3, [r7, #4] + 80040f2: 681b ldr r3, [r3, #0] + 80040f4: f003 0320 and.w r3, r3, #32 + 80040f8: 2b00 cmp r3, #0 + 80040fa: d03c beq.n 8004176 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - 80040b4: 687b ldr r3, [r7, #4] - 80040b6: 699b ldr r3, [r3, #24] - 80040b8: 2b00 cmp r3, #0 - 80040ba: d01c beq.n 80040f6 + 80040fc: 687b ldr r3, [r7, #4] + 80040fe: 699b ldr r3, [r3, #24] + 8004100: 2b00 cmp r3, #0 + 8004102: d01c beq.n 800413e { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); - 80040bc: 4b2d ldr r3, [pc, #180] @ (8004174 ) - 80040be: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 - 80040c2: 4a2c ldr r2, [pc, #176] @ (8004174 ) - 80040c4: f043 0301 orr.w r3, r3, #1 - 80040c8: f8c2 3098 str.w r3, [r2, #152] @ 0x98 + 8004104: 4b2d ldr r3, [pc, #180] @ (80041bc ) + 8004106: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 800410a: 4a2c ldr r2, [pc, #176] @ (80041bc ) + 800410c: f043 0301 orr.w r3, r3, #1 + 8004110: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80040cc: f7fd fd0e bl 8001aec - 80040d0: 6138 str r0, [r7, #16] + 8004114: f7fd fd0e bl 8001b34 + 8004118: 6138 str r0, [r7, #16] /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) - 80040d2: e008 b.n 80040e6 + 800411a: e008 b.n 800412e { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - 80040d4: f7fd fd0a bl 8001aec - 80040d8: 4602 mov r2, r0 - 80040da: 693b ldr r3, [r7, #16] - 80040dc: 1ad3 subs r3, r2, r3 - 80040de: 2b02 cmp r3, #2 - 80040e0: d901 bls.n 80040e6 + 800411c: f7fd fd0a bl 8001b34 + 8004120: 4602 mov r2, r0 + 8004122: 693b ldr r3, [r7, #16] + 8004124: 1ad3 subs r3, r2, r3 + 8004126: 2b02 cmp r3, #2 + 8004128: d901 bls.n 800412e { return HAL_TIMEOUT; - 80040e2: 2303 movs r3, #3 - 80040e4: e0f2 b.n 80042cc + 800412a: 2303 movs r3, #3 + 800412c: e0f2 b.n 8004314 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) - 80040e6: 4b23 ldr r3, [pc, #140] @ (8004174 ) - 80040e8: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 - 80040ec: f003 0302 and.w r3, r3, #2 - 80040f0: 2b00 cmp r3, #0 - 80040f2: d0ef beq.n 80040d4 - 80040f4: e01b b.n 800412e + 800412e: 4b23 ldr r3, [pc, #140] @ (80041bc ) + 8004130: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 8004134: f003 0302 and.w r3, r3, #2 + 8004138: 2b00 cmp r3, #0 + 800413a: d0ef beq.n 800411c + 800413c: e01b b.n 8004176 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); - 80040f6: 4b1f ldr r3, [pc, #124] @ (8004174 ) - 80040f8: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 - 80040fc: 4a1d ldr r2, [pc, #116] @ (8004174 ) - 80040fe: f023 0301 bic.w r3, r3, #1 - 8004102: f8c2 3098 str.w r3, [r2, #152] @ 0x98 + 800413e: 4b1f ldr r3, [pc, #124] @ (80041bc ) + 8004140: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 8004144: 4a1d ldr r2, [pc, #116] @ (80041bc ) + 8004146: f023 0301 bic.w r3, r3, #1 + 800414a: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8004106: f7fd fcf1 bl 8001aec - 800410a: 6138 str r0, [r7, #16] + 800414e: f7fd fcf1 bl 8001b34 + 8004152: 6138 str r0, [r7, #16] /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) - 800410c: e008 b.n 8004120 + 8004154: e008 b.n 8004168 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - 800410e: f7fd fced bl 8001aec - 8004112: 4602 mov r2, r0 - 8004114: 693b ldr r3, [r7, #16] - 8004116: 1ad3 subs r3, r2, r3 - 8004118: 2b02 cmp r3, #2 - 800411a: d901 bls.n 8004120 + 8004156: f7fd fced bl 8001b34 + 800415a: 4602 mov r2, r0 + 800415c: 693b ldr r3, [r7, #16] + 800415e: 1ad3 subs r3, r2, r3 + 8004160: 2b02 cmp r3, #2 + 8004162: d901 bls.n 8004168 { return HAL_TIMEOUT; - 800411c: 2303 movs r3, #3 - 800411e: e0d5 b.n 80042cc + 8004164: 2303 movs r3, #3 + 8004166: e0d5 b.n 8004314 while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) - 8004120: 4b14 ldr r3, [pc, #80] @ (8004174 ) - 8004122: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 - 8004126: f003 0302 and.w r3, r3, #2 - 800412a: 2b00 cmp r3, #0 - 800412c: d1ef bne.n 800410e + 8004168: 4b14 ldr r3, [pc, #80] @ (80041bc ) + 800416a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 + 800416e: f003 0302 and.w r3, r3, #2 + 8004172: 2b00 cmp r3, #0 + 8004174: d1ef bne.n 8004156 /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) - 800412e: 687b ldr r3, [r7, #4] - 8004130: 69db ldr r3, [r3, #28] - 8004132: 2b00 cmp r3, #0 - 8004134: f000 80c9 beq.w 80042ca + 8004176: 687b ldr r3, [r7, #4] + 8004178: 69db ldr r3, [r3, #28] + 800417a: 2b00 cmp r3, #0 + 800417c: f000 80c9 beq.w 8004312 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - 8004138: 4b0e ldr r3, [pc, #56] @ (8004174 ) - 800413a: 689b ldr r3, [r3, #8] - 800413c: f003 030c and.w r3, r3, #12 - 8004140: 2b0c cmp r3, #12 - 8004142: f000 8083 beq.w 800424c + 8004180: 4b0e ldr r3, [pc, #56] @ (80041bc ) + 8004182: 689b ldr r3, [r3, #8] + 8004184: f003 030c and.w r3, r3, #12 + 8004188: 2b0c cmp r3, #12 + 800418a: f000 8083 beq.w 8004294 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) - 8004146: 687b ldr r3, [r7, #4] - 8004148: 69db ldr r3, [r3, #28] - 800414a: 2b02 cmp r3, #2 - 800414c: d15e bne.n 800420c + 800418e: 687b ldr r3, [r7, #4] + 8004190: 69db ldr r3, [r3, #28] + 8004192: 2b02 cmp r3, #2 + 8004194: d15e bne.n 8004254 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800414e: 4b09 ldr r3, [pc, #36] @ (8004174 ) - 8004150: 681b ldr r3, [r3, #0] - 8004152: 4a08 ldr r2, [pc, #32] @ (8004174 ) - 8004154: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 - 8004158: 6013 str r3, [r2, #0] + 8004196: 4b09 ldr r3, [pc, #36] @ (80041bc ) + 8004198: 681b ldr r3, [r3, #0] + 800419a: 4a08 ldr r2, [pc, #32] @ (80041bc ) + 800419c: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 80041a0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800415a: f7fd fcc7 bl 8001aec - 800415e: 6138 str r0, [r7, #16] + 80041a2: f7fd fcc7 bl 8001b34 + 80041a6: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 8004160: e00c b.n 800417c + 80041a8: e00c b.n 80041c4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8004162: f7fd fcc3 bl 8001aec - 8004166: 4602 mov r2, r0 - 8004168: 693b ldr r3, [r7, #16] - 800416a: 1ad3 subs r3, r2, r3 - 800416c: 2b02 cmp r3, #2 - 800416e: d905 bls.n 800417c + 80041aa: f7fd fcc3 bl 8001b34 + 80041ae: 4602 mov r2, r0 + 80041b0: 693b ldr r3, [r7, #16] + 80041b2: 1ad3 subs r3, r2, r3 + 80041b4: 2b02 cmp r3, #2 + 80041b6: d905 bls.n 80041c4 { return HAL_TIMEOUT; - 8004170: 2303 movs r3, #3 - 8004172: e0ab b.n 80042cc - 8004174: 40021000 .word 0x40021000 - 8004178: 40007000 .word 0x40007000 + 80041b8: 2303 movs r3, #3 + 80041ba: e0ab b.n 8004314 + 80041bc: 40021000 .word 0x40021000 + 80041c0: 40007000 .word 0x40007000 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 800417c: 4b55 ldr r3, [pc, #340] @ (80042d4 ) - 800417e: 681b ldr r3, [r3, #0] - 8004180: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8004184: 2b00 cmp r3, #0 - 8004186: d1ec bne.n 8004162 + 80041c4: 4b55 ldr r3, [pc, #340] @ (800431c ) + 80041c6: 681b ldr r3, [r3, #0] + 80041c8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 80041cc: 2b00 cmp r3, #0 + 80041ce: d1ec bne.n 80041aa } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 8004188: 4b52 ldr r3, [pc, #328] @ (80042d4 ) - 800418a: 68da ldr r2, [r3, #12] - 800418c: 4b52 ldr r3, [pc, #328] @ (80042d8 ) - 800418e: 4013 ands r3, r2 - 8004190: 687a ldr r2, [r7, #4] - 8004192: 6a11 ldr r1, [r2, #32] - 8004194: 687a ldr r2, [r7, #4] - 8004196: 6a52 ldr r2, [r2, #36] @ 0x24 - 8004198: 3a01 subs r2, #1 - 800419a: 0112 lsls r2, r2, #4 - 800419c: 4311 orrs r1, r2 - 800419e: 687a ldr r2, [r7, #4] - 80041a0: 6a92 ldr r2, [r2, #40] @ 0x28 - 80041a2: 0212 lsls r2, r2, #8 - 80041a4: 4311 orrs r1, r2 - 80041a6: 687a ldr r2, [r7, #4] - 80041a8: 6b12 ldr r2, [r2, #48] @ 0x30 - 80041aa: 0852 lsrs r2, r2, #1 - 80041ac: 3a01 subs r2, #1 - 80041ae: 0552 lsls r2, r2, #21 - 80041b0: 4311 orrs r1, r2 - 80041b2: 687a ldr r2, [r7, #4] - 80041b4: 6b52 ldr r2, [r2, #52] @ 0x34 - 80041b6: 0852 lsrs r2, r2, #1 - 80041b8: 3a01 subs r2, #1 - 80041ba: 0652 lsls r2, r2, #25 - 80041bc: 4311 orrs r1, r2 - 80041be: 687a ldr r2, [r7, #4] - 80041c0: 6ad2 ldr r2, [r2, #44] @ 0x2c - 80041c2: 06d2 lsls r2, r2, #27 - 80041c4: 430a orrs r2, r1 - 80041c6: 4943 ldr r1, [pc, #268] @ (80042d4 ) - 80041c8: 4313 orrs r3, r2 - 80041ca: 60cb str r3, [r1, #12] + 80041d0: 4b52 ldr r3, [pc, #328] @ (800431c ) + 80041d2: 68da ldr r2, [r3, #12] + 80041d4: 4b52 ldr r3, [pc, #328] @ (8004320 ) + 80041d6: 4013 ands r3, r2 + 80041d8: 687a ldr r2, [r7, #4] + 80041da: 6a11 ldr r1, [r2, #32] + 80041dc: 687a ldr r2, [r7, #4] + 80041de: 6a52 ldr r2, [r2, #36] @ 0x24 + 80041e0: 3a01 subs r2, #1 + 80041e2: 0112 lsls r2, r2, #4 + 80041e4: 4311 orrs r1, r2 + 80041e6: 687a ldr r2, [r7, #4] + 80041e8: 6a92 ldr r2, [r2, #40] @ 0x28 + 80041ea: 0212 lsls r2, r2, #8 + 80041ec: 4311 orrs r1, r2 + 80041ee: 687a ldr r2, [r7, #4] + 80041f0: 6b12 ldr r2, [r2, #48] @ 0x30 + 80041f2: 0852 lsrs r2, r2, #1 + 80041f4: 3a01 subs r2, #1 + 80041f6: 0552 lsls r2, r2, #21 + 80041f8: 4311 orrs r1, r2 + 80041fa: 687a ldr r2, [r7, #4] + 80041fc: 6b52 ldr r2, [r2, #52] @ 0x34 + 80041fe: 0852 lsrs r2, r2, #1 + 8004200: 3a01 subs r2, #1 + 8004202: 0652 lsls r2, r2, #25 + 8004204: 4311 orrs r1, r2 + 8004206: 687a ldr r2, [r7, #4] + 8004208: 6ad2 ldr r2, [r2, #44] @ 0x2c + 800420a: 06d2 lsls r2, r2, #27 + 800420c: 430a orrs r2, r1 + 800420e: 4943 ldr r1, [pc, #268] @ (800431c ) + 8004210: 4313 orrs r3, r2 + 8004212: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 80041cc: 4b41 ldr r3, [pc, #260] @ (80042d4 ) - 80041ce: 681b ldr r3, [r3, #0] - 80041d0: 4a40 ldr r2, [pc, #256] @ (80042d4 ) - 80041d2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 - 80041d6: 6013 str r3, [r2, #0] + 8004214: 4b41 ldr r3, [pc, #260] @ (800431c ) + 8004216: 681b ldr r3, [r3, #0] + 8004218: 4a40 ldr r2, [pc, #256] @ (800431c ) + 800421a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 800421e: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - 80041d8: 4b3e ldr r3, [pc, #248] @ (80042d4 ) - 80041da: 68db ldr r3, [r3, #12] - 80041dc: 4a3d ldr r2, [pc, #244] @ (80042d4 ) - 80041de: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 - 80041e2: 60d3 str r3, [r2, #12] + 8004220: 4b3e ldr r3, [pc, #248] @ (800431c ) + 8004222: 68db ldr r3, [r3, #12] + 8004224: 4a3d ldr r2, [pc, #244] @ (800431c ) + 8004226: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 + 800422a: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80041e4: f7fd fc82 bl 8001aec - 80041e8: 6138 str r0, [r7, #16] + 800422c: f7fd fc82 bl 8001b34 + 8004230: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 80041ea: e008 b.n 80041fe + 8004232: e008 b.n 8004246 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 80041ec: f7fd fc7e bl 8001aec - 80041f0: 4602 mov r2, r0 - 80041f2: 693b ldr r3, [r7, #16] - 80041f4: 1ad3 subs r3, r2, r3 - 80041f6: 2b02 cmp r3, #2 - 80041f8: d901 bls.n 80041fe + 8004234: f7fd fc7e bl 8001b34 + 8004238: 4602 mov r2, r0 + 800423a: 693b ldr r3, [r7, #16] + 800423c: 1ad3 subs r3, r2, r3 + 800423e: 2b02 cmp r3, #2 + 8004240: d901 bls.n 8004246 { return HAL_TIMEOUT; - 80041fa: 2303 movs r3, #3 - 80041fc: e066 b.n 80042cc + 8004242: 2303 movs r3, #3 + 8004244: e066 b.n 8004314 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 80041fe: 4b35 ldr r3, [pc, #212] @ (80042d4 ) - 8004200: 681b ldr r3, [r3, #0] - 8004202: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8004206: 2b00 cmp r3, #0 - 8004208: d0f0 beq.n 80041ec - 800420a: e05e b.n 80042ca + 8004246: 4b35 ldr r3, [pc, #212] @ (800431c ) + 8004248: 681b ldr r3, [r3, #0] + 800424a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800424e: 2b00 cmp r3, #0 + 8004250: d0f0 beq.n 8004234 + 8004252: e05e b.n 8004312 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800420c: 4b31 ldr r3, [pc, #196] @ (80042d4 ) - 800420e: 681b ldr r3, [r3, #0] - 8004210: 4a30 ldr r2, [pc, #192] @ (80042d4 ) - 8004212: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 - 8004216: 6013 str r3, [r2, #0] + 8004254: 4b31 ldr r3, [pc, #196] @ (800431c ) + 8004256: 681b ldr r3, [r3, #0] + 8004258: 4a30 ldr r2, [pc, #192] @ (800431c ) + 800425a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 + 800425e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8004218: f7fd fc68 bl 8001aec - 800421c: 6138 str r0, [r7, #16] + 8004260: f7fd fc68 bl 8001b34 + 8004264: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 800421e: e008 b.n 8004232 + 8004266: e008 b.n 800427a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8004220: f7fd fc64 bl 8001aec - 8004224: 4602 mov r2, r0 - 8004226: 693b ldr r3, [r7, #16] - 8004228: 1ad3 subs r3, r2, r3 - 800422a: 2b02 cmp r3, #2 - 800422c: d901 bls.n 8004232 + 8004268: f7fd fc64 bl 8001b34 + 800426c: 4602 mov r2, r0 + 800426e: 693b ldr r3, [r7, #16] + 8004270: 1ad3 subs r3, r2, r3 + 8004272: 2b02 cmp r3, #2 + 8004274: d901 bls.n 800427a { return HAL_TIMEOUT; - 800422e: 2303 movs r3, #3 - 8004230: e04c b.n 80042cc + 8004276: 2303 movs r3, #3 + 8004278: e04c b.n 8004314 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - 8004232: 4b28 ldr r3, [pc, #160] @ (80042d4 ) - 8004234: 681b ldr r3, [r3, #0] - 8004236: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 800423a: 2b00 cmp r3, #0 - 800423c: d1f0 bne.n 8004220 + 800427a: 4b28 ldr r3, [pc, #160] @ (800431c ) + 800427c: 681b ldr r3, [r3, #0] + 800427e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 8004282: 2b00 cmp r3, #0 + 8004284: d1f0 bne.n 8004268 } } /* Unselect PLL clock source and disable outputs to save power */ RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK); - 800423e: 4b25 ldr r3, [pc, #148] @ (80042d4 ) - 8004240: 68da ldr r2, [r3, #12] - 8004242: 4924 ldr r1, [pc, #144] @ (80042d4 ) - 8004244: 4b25 ldr r3, [pc, #148] @ (80042dc ) - 8004246: 4013 ands r3, r2 - 8004248: 60cb str r3, [r1, #12] - 800424a: e03e b.n 80042ca + 8004286: 4b25 ldr r3, [pc, #148] @ (800431c ) + 8004288: 68da ldr r2, [r3, #12] + 800428a: 4924 ldr r1, [pc, #144] @ (800431c ) + 800428c: 4b25 ldr r3, [pc, #148] @ (8004324 ) + 800428e: 4013 ands r3, r2 + 8004290: 60cb str r3, [r1, #12] + 8004292: e03e b.n 8004312 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 800424c: 687b ldr r3, [r7, #4] - 800424e: 69db ldr r3, [r3, #28] - 8004250: 2b01 cmp r3, #1 - 8004252: d101 bne.n 8004258 + 8004294: 687b ldr r3, [r7, #4] + 8004296: 69db ldr r3, [r3, #28] + 8004298: 2b01 cmp r3, #1 + 800429a: d101 bne.n 80042a0 { return HAL_ERROR; - 8004254: 2301 movs r3, #1 - 8004256: e039 b.n 80042cc + 800429c: 2301 movs r3, #1 + 800429e: e039 b.n 8004314 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; - 8004258: 4b1e ldr r3, [pc, #120] @ (80042d4 ) - 800425a: 68db ldr r3, [r3, #12] - 800425c: 617b str r3, [r7, #20] + 80042a0: 4b1e ldr r3, [pc, #120] @ (800431c ) + 80042a2: 68db ldr r3, [r3, #12] + 80042a4: 617b str r3, [r7, #20] if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 800425e: 697b ldr r3, [r7, #20] - 8004260: f003 0203 and.w r2, r3, #3 - 8004264: 687b ldr r3, [r7, #4] - 8004266: 6a1b ldr r3, [r3, #32] - 8004268: 429a cmp r2, r3 - 800426a: d12c bne.n 80042c6 + 80042a6: 697b ldr r3, [r7, #20] + 80042a8: f003 0203 and.w r2, r3, #3 + 80042ac: 687b ldr r3, [r7, #4] + 80042ae: 6a1b ldr r3, [r3, #32] + 80042b0: 429a cmp r2, r3 + 80042b2: d12c bne.n 800430e (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || - 800426c: 697b ldr r3, [r7, #20] - 800426e: f003 02f0 and.w r2, r3, #240 @ 0xf0 - 8004272: 687b ldr r3, [r7, #4] - 8004274: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004276: 3b01 subs r3, #1 - 8004278: 011b lsls r3, r3, #4 - if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 800427a: 429a cmp r2, r3 - 800427c: d123 bne.n 80042c6 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || - 800427e: 697b ldr r3, [r7, #20] - 8004280: f403 42fe and.w r2, r3, #32512 @ 0x7f00 - 8004284: 687b ldr r3, [r7, #4] - 8004286: 6a9b ldr r3, [r3, #40] @ 0x28 - 8004288: 021b lsls r3, r3, #8 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || - 800428a: 429a cmp r2, r3 - 800428c: d11b bne.n 80042c6 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || - 800428e: 697b ldr r3, [r7, #20] - 8004290: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000 - 8004294: 687b ldr r3, [r7, #4] - 8004296: 6adb ldr r3, [r3, #44] @ 0x2c - 8004298: 06db lsls r3, r3, #27 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || - 800429a: 429a cmp r2, r3 - 800429c: d113 bne.n 80042c6 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || - 800429e: 697b ldr r3, [r7, #20] - 80042a0: f403 02c0 and.w r2, r3, #6291456 @ 0x600000 - 80042a4: 687b ldr r3, [r7, #4] - 80042a6: 6b1b ldr r3, [r3, #48] @ 0x30 - 80042a8: 085b lsrs r3, r3, #1 - 80042aa: 3b01 subs r3, #1 - 80042ac: 055b lsls r3, r3, #21 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || - 80042ae: 429a cmp r2, r3 - 80042b0: d109 bne.n 80042c6 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) - 80042b2: 697b ldr r3, [r7, #20] - 80042b4: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000 - 80042b8: 687b ldr r3, [r7, #4] - 80042ba: 6b5b ldr r3, [r3, #52] @ 0x34 - 80042bc: 085b lsrs r3, r3, #1 + 80042b4: 697b ldr r3, [r7, #20] + 80042b6: f003 02f0 and.w r2, r3, #240 @ 0xf0 + 80042ba: 687b ldr r3, [r7, #4] + 80042bc: 6a5b ldr r3, [r3, #36] @ 0x24 80042be: 3b01 subs r3, #1 - 80042c0: 065b lsls r3, r3, #25 - (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + 80042c0: 011b lsls r3, r3, #4 + if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80042c2: 429a cmp r2, r3 - 80042c4: d001 beq.n 80042ca + 80042c4: d123 bne.n 800430e + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || + 80042c6: 697b ldr r3, [r7, #20] + 80042c8: f403 42fe and.w r2, r3, #32512 @ 0x7f00 + 80042cc: 687b ldr r3, [r7, #4] + 80042ce: 6a9b ldr r3, [r3, #40] @ 0x28 + 80042d0: 021b lsls r3, r3, #8 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) || + 80042d2: 429a cmp r2, r3 + 80042d4: d11b bne.n 800430e + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || + 80042d6: 697b ldr r3, [r7, #20] + 80042d8: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000 + 80042dc: 687b ldr r3, [r7, #4] + 80042de: 6adb ldr r3, [r3, #44] @ 0x2c + 80042e0: 06db lsls r3, r3, #27 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) || + 80042e2: 429a cmp r2, r3 + 80042e4: d113 bne.n 800430e + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + 80042e6: 697b ldr r3, [r7, #20] + 80042e8: f403 02c0 and.w r2, r3, #6291456 @ 0x600000 + 80042ec: 687b ldr r3, [r7, #4] + 80042ee: 6b1b ldr r3, [r3, #48] @ 0x30 + 80042f0: 085b lsrs r3, r3, #1 + 80042f2: 3b01 subs r3, #1 + 80042f4: 055b lsls r3, r3, #21 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) || + 80042f6: 429a cmp r2, r3 + 80042f8: d109 bne.n 800430e + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos))) + 80042fa: 697b ldr r3, [r7, #20] + 80042fc: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000 + 8004300: 687b ldr r3, [r7, #4] + 8004302: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004304: 085b lsrs r3, r3, #1 + 8004306: 3b01 subs r3, #1 + 8004308: 065b lsls r3, r3, #25 + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) || + 800430a: 429a cmp r2, r3 + 800430c: d001 beq.n 8004312 { return HAL_ERROR; - 80042c6: 2301 movs r3, #1 - 80042c8: e000 b.n 80042cc + 800430e: 2301 movs r3, #1 + 8004310: e000 b.n 8004314 } } } } return HAL_OK; - 80042ca: 2300 movs r3, #0 + 8004312: 2300 movs r3, #0 } - 80042cc: 4618 mov r0, r3 - 80042ce: 3720 adds r7, #32 - 80042d0: 46bd mov sp, r7 - 80042d2: bd80 pop {r7, pc} - 80042d4: 40021000 .word 0x40021000 - 80042d8: 019f800c .word 0x019f800c - 80042dc: feeefffc .word 0xfeeefffc + 8004314: 4618 mov r0, r3 + 8004316: 3720 adds r7, #32 + 8004318: 46bd mov sp, r7 + 800431a: bd80 pop {r7, pc} + 800431c: 40021000 .word 0x40021000 + 8004320: 019f800c .word 0x019f800c + 8004324: feeefffc .word 0xfeeefffc -080042e0 : +08004328 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 80042e0: b580 push {r7, lr} - 80042e2: b086 sub sp, #24 - 80042e4: af00 add r7, sp, #0 - 80042e6: 6078 str r0, [r7, #4] - 80042e8: 6039 str r1, [r7, #0] + 8004328: b580 push {r7, lr} + 800432a: b086 sub sp, #24 + 800432c: af00 add r7, sp, #0 + 800432e: 6078 str r0, [r7, #4] + 8004330: 6039 str r1, [r7, #0] uint32_t tickstart; uint32_t pllfreq; uint32_t hpre = RCC_SYSCLK_DIV1; - 80042ea: 2300 movs r3, #0 - 80042ec: 617b str r3, [r7, #20] + 8004332: 2300 movs r3, #0 + 8004334: 617b str r3, [r7, #20] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 80042ee: 687b ldr r3, [r7, #4] - 80042f0: 2b00 cmp r3, #0 - 80042f2: d101 bne.n 80042f8 + 8004336: 687b ldr r3, [r7, #4] + 8004338: 2b00 cmp r3, #0 + 800433a: d101 bne.n 8004340 { return HAL_ERROR; - 80042f4: 2301 movs r3, #1 - 80042f6: e11e b.n 8004536 + 800433c: 2301 movs r3, #1 + 800433e: e11e b.n 800457e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 80042f8: 4b91 ldr r3, [pc, #580] @ (8004540 ) - 80042fa: 681b ldr r3, [r3, #0] - 80042fc: f003 030f and.w r3, r3, #15 - 8004300: 683a ldr r2, [r7, #0] - 8004302: 429a cmp r2, r3 - 8004304: d910 bls.n 8004328 + 8004340: 4b91 ldr r3, [pc, #580] @ (8004588 ) + 8004342: 681b ldr r3, [r3, #0] + 8004344: f003 030f and.w r3, r3, #15 + 8004348: 683a ldr r2, [r7, #0] + 800434a: 429a cmp r2, r3 + 800434c: d910 bls.n 8004370 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8004306: 4b8e ldr r3, [pc, #568] @ (8004540 ) - 8004308: 681b ldr r3, [r3, #0] - 800430a: f023 020f bic.w r2, r3, #15 - 800430e: 498c ldr r1, [pc, #560] @ (8004540 ) - 8004310: 683b ldr r3, [r7, #0] - 8004312: 4313 orrs r3, r2 - 8004314: 600b str r3, [r1, #0] + 800434e: 4b8e ldr r3, [pc, #568] @ (8004588 ) + 8004350: 681b ldr r3, [r3, #0] + 8004352: f023 020f bic.w r2, r3, #15 + 8004356: 498c ldr r1, [pc, #560] @ (8004588 ) + 8004358: 683b ldr r3, [r7, #0] + 800435a: 4313 orrs r3, r2 + 800435c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 8004316: 4b8a ldr r3, [pc, #552] @ (8004540 ) - 8004318: 681b ldr r3, [r3, #0] - 800431a: f003 030f and.w r3, r3, #15 - 800431e: 683a ldr r2, [r7, #0] - 8004320: 429a cmp r2, r3 - 8004322: d001 beq.n 8004328 + 800435e: 4b8a ldr r3, [pc, #552] @ (8004588 ) + 8004360: 681b ldr r3, [r3, #0] + 8004362: f003 030f and.w r3, r3, #15 + 8004366: 683a ldr r2, [r7, #0] + 8004368: 429a cmp r2, r3 + 800436a: d001 beq.n 8004370 { return HAL_ERROR; - 8004324: 2301 movs r3, #1 - 8004326: e106 b.n 8004536 + 800436c: 2301 movs r3, #1 + 800436e: e106 b.n 800457e } } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8004328: 687b ldr r3, [r7, #4] - 800432a: 681b ldr r3, [r3, #0] - 800432c: f003 0301 and.w r3, r3, #1 - 8004330: 2b00 cmp r3, #0 - 8004332: d073 beq.n 800441c + 8004370: 687b ldr r3, [r7, #4] + 8004372: 681b ldr r3, [r3, #0] + 8004374: f003 0301 and.w r3, r3, #1 + 8004378: 2b00 cmp r3, #0 + 800437a: d073 beq.n 8004464 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* PLL is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8004334: 687b ldr r3, [r7, #4] - 8004336: 685b ldr r3, [r3, #4] - 8004338: 2b03 cmp r3, #3 - 800433a: d129 bne.n 8004390 + 800437c: 687b ldr r3, [r7, #4] + 800437e: 685b ldr r3, [r3, #4] + 8004380: 2b03 cmp r3, #3 + 8004382: d129 bne.n 80043d8 { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) - 800433c: 4b81 ldr r3, [pc, #516] @ (8004544 ) - 800433e: 681b ldr r3, [r3, #0] - 8004340: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 - 8004344: 2b00 cmp r3, #0 - 8004346: d101 bne.n 800434c + 8004384: 4b81 ldr r3, [pc, #516] @ (800458c ) + 8004386: 681b ldr r3, [r3, #0] + 8004388: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 + 800438c: 2b00 cmp r3, #0 + 800438e: d101 bne.n 8004394 { return HAL_ERROR; - 8004348: 2301 movs r3, #1 - 800434a: e0f4 b.n 8004536 + 8004390: 2301 movs r3, #1 + 8004392: e0f4 b.n 800457e } /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ /* Compute target PLL output frequency */ pllfreq = RCC_GetSysClockFreqFromPLLSource(); - 800434c: f000 f99e bl 800468c - 8004350: 6138 str r0, [r7, #16] + 8004394: f000 f99e bl 80046d4 + 8004398: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ if(pllfreq > 80000000U) - 8004352: 693b ldr r3, [r7, #16] - 8004354: 4a7c ldr r2, [pc, #496] @ (8004548 ) - 8004356: 4293 cmp r3, r2 - 8004358: d93f bls.n 80043da + 800439a: 693b ldr r3, [r7, #16] + 800439c: 4a7c ldr r2, [pc, #496] @ (8004590 ) + 800439e: 4293 cmp r3, r2 + 80043a0: d93f bls.n 8004422 { if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || - 800435a: 4b7a ldr r3, [pc, #488] @ (8004544 ) - 800435c: 689b ldr r3, [r3, #8] - 800435e: f003 03f0 and.w r3, r3, #240 @ 0xf0 - 8004362: 2b00 cmp r3, #0 - 8004364: d009 beq.n 800437a + 80043a2: 4b7a ldr r3, [pc, #488] @ (800458c ) + 80043a4: 689b ldr r3, [r3, #8] + 80043a6: f003 03f0 and.w r3, r3, #240 @ 0xf0 + 80043aa: 2b00 cmp r3, #0 + 80043ac: d009 beq.n 80043c2 (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && - 8004366: 687b ldr r3, [r7, #4] - 8004368: 681b ldr r3, [r3, #0] - 800436a: f003 0302 and.w r3, r3, #2 + 80043ae: 687b ldr r3, [r7, #4] + 80043b0: 681b ldr r3, [r3, #0] + 80043b2: f003 0302 and.w r3, r3, #2 if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) || - 800436e: 2b00 cmp r3, #0 - 8004370: d033 beq.n 80043da + 80043b6: 2b00 cmp r3, #0 + 80043b8: d033 beq.n 8004422 (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)))) - 8004372: 687b ldr r3, [r7, #4] - 8004374: 689b ldr r3, [r3, #8] + 80043ba: 687b ldr r3, [r7, #4] + 80043bc: 689b ldr r3, [r3, #8] (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && - 8004376: 2b00 cmp r3, #0 - 8004378: d12f bne.n 80043da + 80043be: 2b00 cmp r3, #0 + 80043c0: d12f bne.n 8004422 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - 800437a: 4b72 ldr r3, [pc, #456] @ (8004544 ) - 800437c: 689b ldr r3, [r3, #8] - 800437e: f023 03f0 bic.w r3, r3, #240 @ 0xf0 - 8004382: 4a70 ldr r2, [pc, #448] @ (8004544 ) - 8004384: f043 0380 orr.w r3, r3, #128 @ 0x80 - 8004388: 6093 str r3, [r2, #8] + 80043c2: 4b72 ldr r3, [pc, #456] @ (800458c ) + 80043c4: 689b ldr r3, [r3, #8] + 80043c6: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 80043ca: 4a70 ldr r2, [pc, #448] @ (800458c ) + 80043cc: f043 0380 orr.w r3, r3, #128 @ 0x80 + 80043d0: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; - 800438a: 2380 movs r3, #128 @ 0x80 - 800438c: 617b str r3, [r7, #20] - 800438e: e024 b.n 80043da + 80043d2: 2380 movs r3, #128 @ 0x80 + 80043d4: 617b str r3, [r7, #20] + 80043d6: e024 b.n 8004422 } } else { /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 8004390: 687b ldr r3, [r7, #4] - 8004392: 685b ldr r3, [r3, #4] - 8004394: 2b02 cmp r3, #2 - 8004396: d107 bne.n 80043a8 + 80043d8: 687b ldr r3, [r7, #4] + 80043da: 685b ldr r3, [r3, #4] + 80043dc: 2b02 cmp r3, #2 + 80043de: d107 bne.n 80043f0 { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - 8004398: 4b6a ldr r3, [pc, #424] @ (8004544 ) - 800439a: 681b ldr r3, [r3, #0] - 800439c: f403 3300 and.w r3, r3, #131072 @ 0x20000 - 80043a0: 2b00 cmp r3, #0 - 80043a2: d109 bne.n 80043b8 + 80043e0: 4b6a ldr r3, [pc, #424] @ (800458c ) + 80043e2: 681b ldr r3, [r3, #0] + 80043e4: f403 3300 and.w r3, r3, #131072 @ 0x20000 + 80043e8: 2b00 cmp r3, #0 + 80043ea: d109 bne.n 8004400 { return HAL_ERROR; - 80043a4: 2301 movs r3, #1 - 80043a6: e0c6 b.n 8004536 + 80043ec: 2301 movs r3, #1 + 80043ee: e0c6 b.n 800457e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - 80043a8: 4b66 ldr r3, [pc, #408] @ (8004544 ) - 80043aa: 681b ldr r3, [r3, #0] - 80043ac: f403 6380 and.w r3, r3, #1024 @ 0x400 - 80043b0: 2b00 cmp r3, #0 - 80043b2: d101 bne.n 80043b8 + 80043f0: 4b66 ldr r3, [pc, #408] @ (800458c ) + 80043f2: 681b ldr r3, [r3, #0] + 80043f4: f403 6380 and.w r3, r3, #1024 @ 0x400 + 80043f8: 2b00 cmp r3, #0 + 80043fa: d101 bne.n 8004400 { return HAL_ERROR; - 80043b4: 2301 movs r3, #1 - 80043b6: e0be b.n 8004536 + 80043fc: 2301 movs r3, #1 + 80043fe: e0be b.n 800457e } } /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ pllfreq = HAL_RCC_GetSysClockFreq(); - 80043b8: f000 f8ce bl 8004558 - 80043bc: 6138 str r0, [r7, #16] + 8004400: f000 f8ce bl 80045a0 + 8004404: 6138 str r0, [r7, #16] /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ if(pllfreq > 80000000U) - 80043be: 693b ldr r3, [r7, #16] - 80043c0: 4a61 ldr r2, [pc, #388] @ (8004548 ) - 80043c2: 4293 cmp r3, r2 - 80043c4: d909 bls.n 80043da + 8004406: 693b ldr r3, [r7, #16] + 8004408: 4a61 ldr r2, [pc, #388] @ (8004590 ) + 800440a: 4293 cmp r3, r2 + 800440c: d909 bls.n 8004422 { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - 80043c6: 4b5f ldr r3, [pc, #380] @ (8004544 ) - 80043c8: 689b ldr r3, [r3, #8] - 80043ca: f023 03f0 bic.w r3, r3, #240 @ 0xf0 - 80043ce: 4a5d ldr r2, [pc, #372] @ (8004544 ) - 80043d0: f043 0380 orr.w r3, r3, #128 @ 0x80 - 80043d4: 6093 str r3, [r2, #8] + 800440e: 4b5f ldr r3, [pc, #380] @ (800458c ) + 8004410: 689b ldr r3, [r3, #8] + 8004412: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8004416: 4a5d ldr r2, [pc, #372] @ (800458c ) + 8004418: f043 0380 orr.w r3, r3, #128 @ 0x80 + 800441c: 6093 str r3, [r2, #8] hpre = RCC_SYSCLK_DIV2; - 80043d6: 2380 movs r3, #128 @ 0x80 - 80043d8: 617b str r3, [r7, #20] + 800441e: 2380 movs r3, #128 @ 0x80 + 8004420: 617b str r3, [r7, #20] } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - 80043da: 4b5a ldr r3, [pc, #360] @ (8004544 ) - 80043dc: 689b ldr r3, [r3, #8] - 80043de: f023 0203 bic.w r2, r3, #3 - 80043e2: 687b ldr r3, [r7, #4] - 80043e4: 685b ldr r3, [r3, #4] - 80043e6: 4957 ldr r1, [pc, #348] @ (8004544 ) - 80043e8: 4313 orrs r3, r2 - 80043ea: 608b str r3, [r1, #8] + 8004422: 4b5a ldr r3, [pc, #360] @ (800458c ) + 8004424: 689b ldr r3, [r3, #8] + 8004426: f023 0203 bic.w r2, r3, #3 + 800442a: 687b ldr r3, [r7, #4] + 800442c: 685b ldr r3, [r3, #4] + 800442e: 4957 ldr r1, [pc, #348] @ (800458c ) + 8004430: 4313 orrs r3, r2 + 8004432: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80043ec: f7fd fb7e bl 8001aec - 80043f0: 60f8 str r0, [r7, #12] + 8004434: f7fd fb7e bl 8001b34 + 8004438: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80043f2: e00a b.n 800440a + 800443a: e00a b.n 8004452 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 80043f4: f7fd fb7a bl 8001aec - 80043f8: 4602 mov r2, r0 - 80043fa: 68fb ldr r3, [r7, #12] - 80043fc: 1ad3 subs r3, r2, r3 - 80043fe: f241 3288 movw r2, #5000 @ 0x1388 - 8004402: 4293 cmp r3, r2 - 8004404: d901 bls.n 800440a + 800443c: f7fd fb7a bl 8001b34 + 8004440: 4602 mov r2, r0 + 8004442: 68fb ldr r3, [r7, #12] + 8004444: 1ad3 subs r3, r2, r3 + 8004446: f241 3288 movw r2, #5000 @ 0x1388 + 800444a: 4293 cmp r3, r2 + 800444c: d901 bls.n 8004452 { return HAL_TIMEOUT; - 8004406: 2303 movs r3, #3 - 8004408: e095 b.n 8004536 + 800444e: 2303 movs r3, #3 + 8004450: e095 b.n 800457e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 800440a: 4b4e ldr r3, [pc, #312] @ (8004544 ) - 800440c: 689b ldr r3, [r3, #8] - 800440e: f003 020c and.w r2, r3, #12 - 8004412: 687b ldr r3, [r7, #4] - 8004414: 685b ldr r3, [r3, #4] - 8004416: 009b lsls r3, r3, #2 - 8004418: 429a cmp r2, r3 - 800441a: d1eb bne.n 80043f4 + 8004452: 4b4e ldr r3, [pc, #312] @ (800458c ) + 8004454: 689b ldr r3, [r3, #8] + 8004456: f003 020c and.w r2, r3, #12 + 800445a: 687b ldr r3, [r7, #4] + 800445c: 685b ldr r3, [r3, #4] + 800445e: 009b lsls r3, r3, #2 + 8004460: 429a cmp r2, r3 + 8004462: d1eb bne.n 800443c } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 800441c: 687b ldr r3, [r7, #4] - 800441e: 681b ldr r3, [r3, #0] - 8004420: f003 0302 and.w r3, r3, #2 - 8004424: 2b00 cmp r3, #0 - 8004426: d023 beq.n 8004470 + 8004464: 687b ldr r3, [r7, #4] + 8004466: 681b ldr r3, [r3, #0] + 8004468: f003 0302 and.w r3, r3, #2 + 800446c: 2b00 cmp r3, #0 + 800446e: d023 beq.n 80044b8 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8004428: 687b ldr r3, [r7, #4] - 800442a: 681b ldr r3, [r3, #0] - 800442c: f003 0304 and.w r3, r3, #4 - 8004430: 2b00 cmp r3, #0 - 8004432: d005 beq.n 8004440 + 8004470: 687b ldr r3, [r7, #4] + 8004472: 681b ldr r3, [r3, #0] + 8004474: f003 0304 and.w r3, r3, #4 + 8004478: 2b00 cmp r3, #0 + 800447a: d005 beq.n 8004488 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 8004434: 4b43 ldr r3, [pc, #268] @ (8004544 ) - 8004436: 689b ldr r3, [r3, #8] - 8004438: 4a42 ldr r2, [pc, #264] @ (8004544 ) - 800443a: f443 63e0 orr.w r3, r3, #1792 @ 0x700 - 800443e: 6093 str r3, [r2, #8] + 800447c: 4b43 ldr r3, [pc, #268] @ (800458c ) + 800447e: 689b ldr r3, [r3, #8] + 8004480: 4a42 ldr r2, [pc, #264] @ (800458c ) + 8004482: f443 63e0 orr.w r3, r3, #1792 @ 0x700 + 8004486: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8004440: 687b ldr r3, [r7, #4] - 8004442: 681b ldr r3, [r3, #0] - 8004444: f003 0308 and.w r3, r3, #8 - 8004448: 2b00 cmp r3, #0 - 800444a: d007 beq.n 800445c + 8004488: 687b ldr r3, [r7, #4] + 800448a: 681b ldr r3, [r3, #0] + 800448c: f003 0308 and.w r3, r3, #8 + 8004490: 2b00 cmp r3, #0 + 8004492: d007 beq.n 80044a4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16); - 800444c: 4b3d ldr r3, [pc, #244] @ (8004544 ) - 800444e: 689b ldr r3, [r3, #8] - 8004450: f423 537c bic.w r3, r3, #16128 @ 0x3f00 - 8004454: 4a3b ldr r2, [pc, #236] @ (8004544 ) - 8004456: f443 63e0 orr.w r3, r3, #1792 @ 0x700 - 800445a: 6093 str r3, [r2, #8] + 8004494: 4b3d ldr r3, [pc, #244] @ (800458c ) + 8004496: 689b ldr r3, [r3, #8] + 8004498: f423 537c bic.w r3, r3, #16128 @ 0x3f00 + 800449c: 4a3b ldr r2, [pc, #236] @ (800458c ) + 800449e: f443 63e0 orr.w r3, r3, #1792 @ 0x700 + 80044a2: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 800445c: 4b39 ldr r3, [pc, #228] @ (8004544 ) - 800445e: 689b ldr r3, [r3, #8] - 8004460: f023 02f0 bic.w r2, r3, #240 @ 0xf0 - 8004464: 687b ldr r3, [r7, #4] - 8004466: 689b ldr r3, [r3, #8] - 8004468: 4936 ldr r1, [pc, #216] @ (8004544 ) - 800446a: 4313 orrs r3, r2 - 800446c: 608b str r3, [r1, #8] - 800446e: e008 b.n 8004482 + 80044a4: 4b39 ldr r3, [pc, #228] @ (800458c ) + 80044a6: 689b ldr r3, [r3, #8] + 80044a8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 + 80044ac: 687b ldr r3, [r7, #4] + 80044ae: 689b ldr r3, [r3, #8] + 80044b0: 4936 ldr r1, [pc, #216] @ (800458c ) + 80044b2: 4313 orrs r3, r2 + 80044b4: 608b str r3, [r1, #8] + 80044b6: e008 b.n 80044ca } else { /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ if(hpre == RCC_SYSCLK_DIV2) - 8004470: 697b ldr r3, [r7, #20] - 8004472: 2b80 cmp r3, #128 @ 0x80 - 8004474: d105 bne.n 8004482 + 80044b8: 697b ldr r3, [r7, #20] + 80044ba: 2b80 cmp r3, #128 @ 0x80 + 80044bc: d105 bne.n 80044ca { MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); - 8004476: 4b33 ldr r3, [pc, #204] @ (8004544 ) - 8004478: 689b ldr r3, [r3, #8] - 800447a: 4a32 ldr r2, [pc, #200] @ (8004544 ) - 800447c: f023 03f0 bic.w r3, r3, #240 @ 0xf0 - 8004480: 6093 str r3, [r2, #8] + 80044be: 4b33 ldr r3, [pc, #204] @ (800458c ) + 80044c0: 689b ldr r3, [r3, #8] + 80044c2: 4a32 ldr r2, [pc, #200] @ (800458c ) + 80044c4: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 80044c8: 6093 str r3, [r2, #8] } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 8004482: 4b2f ldr r3, [pc, #188] @ (8004540 ) - 8004484: 681b ldr r3, [r3, #0] - 8004486: f003 030f and.w r3, r3, #15 - 800448a: 683a ldr r2, [r7, #0] - 800448c: 429a cmp r2, r3 - 800448e: d21d bcs.n 80044cc + 80044ca: 4b2f ldr r3, [pc, #188] @ (8004588 ) + 80044cc: 681b ldr r3, [r3, #0] + 80044ce: f003 030f and.w r3, r3, #15 + 80044d2: 683a ldr r2, [r7, #0] + 80044d4: 429a cmp r2, r3 + 80044d6: d21d bcs.n 8004514 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8004490: 4b2b ldr r3, [pc, #172] @ (8004540 ) - 8004492: 681b ldr r3, [r3, #0] - 8004494: f023 020f bic.w r2, r3, #15 - 8004498: 4929 ldr r1, [pc, #164] @ (8004540 ) - 800449a: 683b ldr r3, [r7, #0] - 800449c: 4313 orrs r3, r2 - 800449e: 600b str r3, [r1, #0] + 80044d8: 4b2b ldr r3, [pc, #172] @ (8004588 ) + 80044da: 681b ldr r3, [r3, #0] + 80044dc: f023 020f bic.w r2, r3, #15 + 80044e0: 4929 ldr r1, [pc, #164] @ (8004588 ) + 80044e2: 683b ldr r3, [r7, #0] + 80044e4: 4313 orrs r3, r2 + 80044e6: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); - 80044a0: f7fd fb24 bl 8001aec - 80044a4: 60f8 str r0, [r7, #12] + 80044e8: f7fd fb24 bl 8001b34 + 80044ec: 60f8 str r0, [r7, #12] while (__HAL_FLASH_GET_LATENCY() != FLatency) - 80044a6: e00a b.n 80044be + 80044ee: e00a b.n 8004506 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 80044a8: f7fd fb20 bl 8001aec - 80044ac: 4602 mov r2, r0 - 80044ae: 68fb ldr r3, [r7, #12] - 80044b0: 1ad3 subs r3, r2, r3 - 80044b2: f241 3288 movw r2, #5000 @ 0x1388 - 80044b6: 4293 cmp r3, r2 - 80044b8: d901 bls.n 80044be + 80044f0: f7fd fb20 bl 8001b34 + 80044f4: 4602 mov r2, r0 + 80044f6: 68fb ldr r3, [r7, #12] + 80044f8: 1ad3 subs r3, r2, r3 + 80044fa: f241 3288 movw r2, #5000 @ 0x1388 + 80044fe: 4293 cmp r3, r2 + 8004500: d901 bls.n 8004506 { return HAL_TIMEOUT; - 80044ba: 2303 movs r3, #3 - 80044bc: e03b b.n 8004536 + 8004502: 2303 movs r3, #3 + 8004504: e03b b.n 800457e while (__HAL_FLASH_GET_LATENCY() != FLatency) - 80044be: 4b20 ldr r3, [pc, #128] @ (8004540 ) - 80044c0: 681b ldr r3, [r3, #0] - 80044c2: f003 030f and.w r3, r3, #15 - 80044c6: 683a ldr r2, [r7, #0] - 80044c8: 429a cmp r2, r3 - 80044ca: d1ed bne.n 80044a8 + 8004506: 4b20 ldr r3, [pc, #128] @ (8004588 ) + 8004508: 681b ldr r3, [r3, #0] + 800450a: f003 030f and.w r3, r3, #15 + 800450e: 683a ldr r2, [r7, #0] + 8004510: 429a cmp r2, r3 + 8004512: d1ed bne.n 80044f0 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 80044cc: 687b ldr r3, [r7, #4] - 80044ce: 681b ldr r3, [r3, #0] - 80044d0: f003 0304 and.w r3, r3, #4 - 80044d4: 2b00 cmp r3, #0 - 80044d6: d008 beq.n 80044ea + 8004514: 687b ldr r3, [r7, #4] + 8004516: 681b ldr r3, [r3, #0] + 8004518: f003 0304 and.w r3, r3, #4 + 800451c: 2b00 cmp r3, #0 + 800451e: d008 beq.n 8004532 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 80044d8: 4b1a ldr r3, [pc, #104] @ (8004544 ) - 80044da: 689b ldr r3, [r3, #8] - 80044dc: f423 62e0 bic.w r2, r3, #1792 @ 0x700 - 80044e0: 687b ldr r3, [r7, #4] - 80044e2: 68db ldr r3, [r3, #12] - 80044e4: 4917 ldr r1, [pc, #92] @ (8004544 ) - 80044e6: 4313 orrs r3, r2 - 80044e8: 608b str r3, [r1, #8] + 8004520: 4b1a ldr r3, [pc, #104] @ (800458c ) + 8004522: 689b ldr r3, [r3, #8] + 8004524: f423 62e0 bic.w r2, r3, #1792 @ 0x700 + 8004528: 687b ldr r3, [r7, #4] + 800452a: 68db ldr r3, [r3, #12] + 800452c: 4917 ldr r1, [pc, #92] @ (800458c ) + 800452e: 4313 orrs r3, r2 + 8004530: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 80044ea: 687b ldr r3, [r7, #4] - 80044ec: 681b ldr r3, [r3, #0] - 80044ee: f003 0308 and.w r3, r3, #8 - 80044f2: 2b00 cmp r3, #0 - 80044f4: d009 beq.n 800450a + 8004532: 687b ldr r3, [r7, #4] + 8004534: 681b ldr r3, [r3, #0] + 8004536: f003 0308 and.w r3, r3, #8 + 800453a: 2b00 cmp r3, #0 + 800453c: d009 beq.n 8004552 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 80044f6: 4b13 ldr r3, [pc, #76] @ (8004544 ) - 80044f8: 689b ldr r3, [r3, #8] - 80044fa: f423 5260 bic.w r2, r3, #14336 @ 0x3800 - 80044fe: 687b ldr r3, [r7, #4] - 8004500: 691b ldr r3, [r3, #16] - 8004502: 00db lsls r3, r3, #3 - 8004504: 490f ldr r1, [pc, #60] @ (8004544 ) - 8004506: 4313 orrs r3, r2 - 8004508: 608b str r3, [r1, #8] + 800453e: 4b13 ldr r3, [pc, #76] @ (800458c ) + 8004540: 689b ldr r3, [r3, #8] + 8004542: f423 5260 bic.w r2, r3, #14336 @ 0x3800 + 8004546: 687b ldr r3, [r7, #4] + 8004548: 691b ldr r3, [r3, #16] + 800454a: 00db lsls r3, r3, #3 + 800454c: 490f ldr r1, [pc, #60] @ (800458c ) + 800454e: 4313 orrs r3, r2 + 8004550: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU); - 800450a: f000 f825 bl 8004558 - 800450e: 4602 mov r2, r0 - 8004510: 4b0c ldr r3, [pc, #48] @ (8004544 ) - 8004512: 689b ldr r3, [r3, #8] - 8004514: 091b lsrs r3, r3, #4 - 8004516: f003 030f and.w r3, r3, #15 - 800451a: 490c ldr r1, [pc, #48] @ (800454c ) - 800451c: 5ccb ldrb r3, [r1, r3] - 800451e: f003 031f and.w r3, r3, #31 - 8004522: fa22 f303 lsr.w r3, r2, r3 - 8004526: 4a0a ldr r2, [pc, #40] @ (8004550 ) - 8004528: 6013 str r3, [r2, #0] + 8004552: f000 f825 bl 80045a0 + 8004556: 4602 mov r2, r0 + 8004558: 4b0c ldr r3, [pc, #48] @ (800458c ) + 800455a: 689b ldr r3, [r3, #8] + 800455c: 091b lsrs r3, r3, #4 + 800455e: f003 030f and.w r3, r3, #15 + 8004562: 490c ldr r1, [pc, #48] @ (8004594 ) + 8004564: 5ccb ldrb r3, [r1, r3] + 8004566: f003 031f and.w r3, r3, #31 + 800456a: fa22 f303 lsr.w r3, r2, r3 + 800456e: 4a0a ldr r2, [pc, #40] @ (8004598 ) + 8004570: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); - 800452a: 4b0a ldr r3, [pc, #40] @ (8004554 ) - 800452c: 681b ldr r3, [r3, #0] - 800452e: 4618 mov r0, r3 - 8004530: f7fd fa90 bl 8001a54 - 8004534: 4603 mov r3, r0 + 8004572: 4b0a ldr r3, [pc, #40] @ (800459c ) + 8004574: 681b ldr r3, [r3, #0] + 8004576: 4618 mov r0, r3 + 8004578: f7fd fa90 bl 8001a9c + 800457c: 4603 mov r3, r0 } - 8004536: 4618 mov r0, r3 - 8004538: 3718 adds r7, #24 - 800453a: 46bd mov sp, r7 - 800453c: bd80 pop {r7, pc} - 800453e: bf00 nop - 8004540: 40022000 .word 0x40022000 - 8004544: 40021000 .word 0x40021000 - 8004548: 04c4b400 .word 0x04c4b400 - 800454c: 0800772c .word 0x0800772c - 8004550: 20000014 .word 0x20000014 - 8004554: 20000018 .word 0x20000018 + 800457e: 4618 mov r0, r3 + 8004580: 3718 adds r7, #24 + 8004582: 46bd mov sp, r7 + 8004584: bd80 pop {r7, pc} + 8004586: bf00 nop + 8004588: 40022000 .word 0x40022000 + 800458c: 40021000 .word 0x40021000 + 8004590: 04c4b400 .word 0x04c4b400 + 8004594: 08007774 .word 0x08007774 + 8004598: 20000018 .word 0x20000018 + 800459c: 2000001c .word 0x2000001c -08004558 : +080045a0 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 8004558: b480 push {r7} - 800455a: b087 sub sp, #28 - 800455c: af00 add r7, sp, #0 + 80045a0: b480 push {r7} + 80045a2: b087 sub sp, #28 + 80045a4: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - 800455e: 4b2c ldr r3, [pc, #176] @ (8004610 ) - 8004560: 689b ldr r3, [r3, #8] - 8004562: f003 030c and.w r3, r3, #12 - 8004566: 2b04 cmp r3, #4 - 8004568: d102 bne.n 8004570 + 80045a6: 4b2c ldr r3, [pc, #176] @ (8004658 ) + 80045a8: 689b ldr r3, [r3, #8] + 80045aa: f003 030c and.w r3, r3, #12 + 80045ae: 2b04 cmp r3, #4 + 80045b0: d102 bne.n 80045b8 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; - 800456a: 4b2a ldr r3, [pc, #168] @ (8004614 ) - 800456c: 613b str r3, [r7, #16] - 800456e: e047 b.n 8004600 + 80045b2: 4b2a ldr r3, [pc, #168] @ (800465c ) + 80045b4: 613b str r3, [r7, #16] + 80045b6: e047 b.n 8004648 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - 8004570: 4b27 ldr r3, [pc, #156] @ (8004610 ) - 8004572: 689b ldr r3, [r3, #8] - 8004574: f003 030c and.w r3, r3, #12 - 8004578: 2b08 cmp r3, #8 - 800457a: d102 bne.n 8004582 + 80045b8: 4b27 ldr r3, [pc, #156] @ (8004658 ) + 80045ba: 689b ldr r3, [r3, #8] + 80045bc: f003 030c and.w r3, r3, #12 + 80045c0: 2b08 cmp r3, #8 + 80045c2: d102 bne.n 80045ca { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; - 800457c: 4b26 ldr r3, [pc, #152] @ (8004618 ) - 800457e: 613b str r3, [r7, #16] - 8004580: e03e b.n 8004600 + 80045c4: 4b26 ldr r3, [pc, #152] @ (8004660 ) + 80045c6: 613b str r3, [r7, #16] + 80045c8: e03e b.n 8004648 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) - 8004582: 4b23 ldr r3, [pc, #140] @ (8004610 ) - 8004584: 689b ldr r3, [r3, #8] - 8004586: f003 030c and.w r3, r3, #12 - 800458a: 2b0c cmp r3, #12 - 800458c: d136 bne.n 80045fc + 80045ca: 4b23 ldr r3, [pc, #140] @ (8004658 ) + 80045cc: 689b ldr r3, [r3, #8] + 80045ce: f003 030c and.w r3, r3, #12 + 80045d2: 2b0c cmp r3, #12 + 80045d4: d136 bne.n 8004644 /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - 800458e: 4b20 ldr r3, [pc, #128] @ (8004610 ) - 8004590: 68db ldr r3, [r3, #12] - 8004592: f003 0303 and.w r3, r3, #3 - 8004596: 60fb str r3, [r7, #12] + 80045d6: 4b20 ldr r3, [pc, #128] @ (8004658 ) + 80045d8: 68db ldr r3, [r3, #12] + 80045da: f003 0303 and.w r3, r3, #3 + 80045de: 60fb str r3, [r7, #12] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - 8004598: 4b1d ldr r3, [pc, #116] @ (8004610 ) - 800459a: 68db ldr r3, [r3, #12] - 800459c: 091b lsrs r3, r3, #4 - 800459e: f003 030f and.w r3, r3, #15 - 80045a2: 3301 adds r3, #1 - 80045a4: 60bb str r3, [r7, #8] + 80045e0: 4b1d ldr r3, [pc, #116] @ (8004658 ) + 80045e2: 68db ldr r3, [r3, #12] + 80045e4: 091b lsrs r3, r3, #4 + 80045e6: f003 030f and.w r3, r3, #15 + 80045ea: 3301 adds r3, #1 + 80045ec: 60bb str r3, [r7, #8] switch (pllsource) - 80045a6: 68fb ldr r3, [r7, #12] - 80045a8: 2b03 cmp r3, #3 - 80045aa: d10c bne.n 80045c6 + 80045ee: 68fb ldr r3, [r7, #12] + 80045f0: 2b03 cmp r3, #3 + 80045f2: d10c bne.n 800460e { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - 80045ac: 4a1a ldr r2, [pc, #104] @ (8004618 ) - 80045ae: 68bb ldr r3, [r7, #8] - 80045b0: fbb2 f3f3 udiv r3, r2, r3 - 80045b4: 4a16 ldr r2, [pc, #88] @ (8004610 ) - 80045b6: 68d2 ldr r2, [r2, #12] - 80045b8: 0a12 lsrs r2, r2, #8 - 80045ba: f002 027f and.w r2, r2, #127 @ 0x7f - 80045be: fb02 f303 mul.w r3, r2, r3 - 80045c2: 617b str r3, [r7, #20] + 80045f4: 4a1a ldr r2, [pc, #104] @ (8004660 ) + 80045f6: 68bb ldr r3, [r7, #8] + 80045f8: fbb2 f3f3 udiv r3, r2, r3 + 80045fc: 4a16 ldr r2, [pc, #88] @ (8004658 ) + 80045fe: 68d2 ldr r2, [r2, #12] + 8004600: 0a12 lsrs r2, r2, #8 + 8004602: f002 027f and.w r2, r2, #127 @ 0x7f + 8004606: fb02 f303 mul.w r3, r2, r3 + 800460a: 617b str r3, [r7, #20] break; - 80045c4: e00c b.n 80045e0 + 800460c: e00c b.n 8004628 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - 80045c6: 4a13 ldr r2, [pc, #76] @ (8004614 ) - 80045c8: 68bb ldr r3, [r7, #8] - 80045ca: fbb2 f3f3 udiv r3, r2, r3 - 80045ce: 4a10 ldr r2, [pc, #64] @ (8004610 ) - 80045d0: 68d2 ldr r2, [r2, #12] - 80045d2: 0a12 lsrs r2, r2, #8 - 80045d4: f002 027f and.w r2, r2, #127 @ 0x7f - 80045d8: fb02 f303 mul.w r3, r2, r3 - 80045dc: 617b str r3, [r7, #20] + 800460e: 4a13 ldr r2, [pc, #76] @ (800465c ) + 8004610: 68bb ldr r3, [r7, #8] + 8004612: fbb2 f3f3 udiv r3, r2, r3 + 8004616: 4a10 ldr r2, [pc, #64] @ (8004658 ) + 8004618: 68d2 ldr r2, [r2, #12] + 800461a: 0a12 lsrs r2, r2, #8 + 800461c: f002 027f and.w r2, r2, #127 @ 0x7f + 8004620: fb02 f303 mul.w r3, r2, r3 + 8004624: 617b str r3, [r7, #20] break; - 80045de: bf00 nop + 8004626: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - 80045e0: 4b0b ldr r3, [pc, #44] @ (8004610 ) - 80045e2: 68db ldr r3, [r3, #12] - 80045e4: 0e5b lsrs r3, r3, #25 - 80045e6: f003 0303 and.w r3, r3, #3 - 80045ea: 3301 adds r3, #1 - 80045ec: 005b lsls r3, r3, #1 - 80045ee: 607b str r3, [r7, #4] + 8004628: 4b0b ldr r3, [pc, #44] @ (8004658 ) + 800462a: 68db ldr r3, [r3, #12] + 800462c: 0e5b lsrs r3, r3, #25 + 800462e: f003 0303 and.w r3, r3, #3 + 8004632: 3301 adds r3, #1 + 8004634: 005b lsls r3, r3, #1 + 8004636: 607b str r3, [r7, #4] sysclockfreq = pllvco/pllr; - 80045f0: 697a ldr r2, [r7, #20] - 80045f2: 687b ldr r3, [r7, #4] - 80045f4: fbb2 f3f3 udiv r3, r2, r3 - 80045f8: 613b str r3, [r7, #16] - 80045fa: e001 b.n 8004600 + 8004638: 697a ldr r2, [r7, #20] + 800463a: 687b ldr r3, [r7, #4] + 800463c: fbb2 f3f3 udiv r3, r2, r3 + 8004640: 613b str r3, [r7, #16] + 8004642: e001 b.n 8004648 } else { sysclockfreq = 0U; - 80045fc: 2300 movs r3, #0 - 80045fe: 613b str r3, [r7, #16] + 8004644: 2300 movs r3, #0 + 8004646: 613b str r3, [r7, #16] } return sysclockfreq; - 8004600: 693b ldr r3, [r7, #16] + 8004648: 693b ldr r3, [r7, #16] } - 8004602: 4618 mov r0, r3 - 8004604: 371c adds r7, #28 - 8004606: 46bd mov sp, r7 - 8004608: f85d 7b04 ldr.w r7, [sp], #4 - 800460c: 4770 bx lr - 800460e: bf00 nop - 8004610: 40021000 .word 0x40021000 - 8004614: 00f42400 .word 0x00f42400 - 8004618: 007a1200 .word 0x007a1200 + 800464a: 4618 mov r0, r3 + 800464c: 371c adds r7, #28 + 800464e: 46bd mov sp, r7 + 8004650: f85d 7b04 ldr.w r7, [sp], #4 + 8004654: 4770 bx lr + 8004656: bf00 nop + 8004658: 40021000 .word 0x40021000 + 800465c: 00f42400 .word 0x00f42400 + 8004660: 007a1200 .word 0x007a1200 -0800461c : +08004664 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 800461c: b480 push {r7} - 800461e: af00 add r7, sp, #0 + 8004664: b480 push {r7} + 8004666: af00 add r7, sp, #0 return SystemCoreClock; - 8004620: 4b03 ldr r3, [pc, #12] @ (8004630 ) - 8004622: 681b ldr r3, [r3, #0] + 8004668: 4b03 ldr r3, [pc, #12] @ (8004678 ) + 800466a: 681b ldr r3, [r3, #0] } - 8004624: 4618 mov r0, r3 - 8004626: 46bd mov sp, r7 - 8004628: f85d 7b04 ldr.w r7, [sp], #4 - 800462c: 4770 bx lr - 800462e: bf00 nop - 8004630: 20000014 .word 0x20000014 + 800466c: 4618 mov r0, r3 + 800466e: 46bd mov sp, r7 + 8004670: f85d 7b04 ldr.w r7, [sp], #4 + 8004674: 4770 bx lr + 8004676: bf00 nop + 8004678: 20000018 .word 0x20000018 -08004634 : +0800467c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8004634: b580 push {r7, lr} - 8004636: af00 add r7, sp, #0 + 800467c: b580 push {r7, lr} + 800467e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU)); - 8004638: f7ff fff0 bl 800461c - 800463c: 4602 mov r2, r0 - 800463e: 4b06 ldr r3, [pc, #24] @ (8004658 ) - 8004640: 689b ldr r3, [r3, #8] - 8004642: 0a1b lsrs r3, r3, #8 - 8004644: f003 0307 and.w r3, r3, #7 - 8004648: 4904 ldr r1, [pc, #16] @ (800465c ) - 800464a: 5ccb ldrb r3, [r1, r3] - 800464c: f003 031f and.w r3, r3, #31 - 8004650: fa22 f303 lsr.w r3, r2, r3 + 8004680: f7ff fff0 bl 8004664 + 8004684: 4602 mov r2, r0 + 8004686: 4b06 ldr r3, [pc, #24] @ (80046a0 ) + 8004688: 689b ldr r3, [r3, #8] + 800468a: 0a1b lsrs r3, r3, #8 + 800468c: f003 0307 and.w r3, r3, #7 + 8004690: 4904 ldr r1, [pc, #16] @ (80046a4 ) + 8004692: 5ccb ldrb r3, [r1, r3] + 8004694: f003 031f and.w r3, r3, #31 + 8004698: fa22 f303 lsr.w r3, r2, r3 } - 8004654: 4618 mov r0, r3 - 8004656: bd80 pop {r7, pc} - 8004658: 40021000 .word 0x40021000 - 800465c: 0800773c .word 0x0800773c + 800469c: 4618 mov r0, r3 + 800469e: bd80 pop {r7, pc} + 80046a0: 40021000 .word 0x40021000 + 80046a4: 08007784 .word 0x08007784 -08004660 : +080046a8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency in Hz */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 8004660: b580 push {r7, lr} - 8004662: af00 add r7, sp, #0 + 80046a8: b580 push {r7, lr} + 80046aa: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU)); - 8004664: f7ff ffda bl 800461c - 8004668: 4602 mov r2, r0 - 800466a: 4b06 ldr r3, [pc, #24] @ (8004684 ) - 800466c: 689b ldr r3, [r3, #8] - 800466e: 0adb lsrs r3, r3, #11 - 8004670: f003 0307 and.w r3, r3, #7 - 8004674: 4904 ldr r1, [pc, #16] @ (8004688 ) - 8004676: 5ccb ldrb r3, [r1, r3] - 8004678: f003 031f and.w r3, r3, #31 - 800467c: fa22 f303 lsr.w r3, r2, r3 + 80046ac: f7ff ffda bl 8004664 + 80046b0: 4602 mov r2, r0 + 80046b2: 4b06 ldr r3, [pc, #24] @ (80046cc ) + 80046b4: 689b ldr r3, [r3, #8] + 80046b6: 0adb lsrs r3, r3, #11 + 80046b8: f003 0307 and.w r3, r3, #7 + 80046bc: 4904 ldr r1, [pc, #16] @ (80046d0 ) + 80046be: 5ccb ldrb r3, [r1, r3] + 80046c0: f003 031f and.w r3, r3, #31 + 80046c4: fa22 f303 lsr.w r3, r2, r3 } - 8004680: 4618 mov r0, r3 - 8004682: bd80 pop {r7, pc} - 8004684: 40021000 .word 0x40021000 - 8004688: 0800773c .word 0x0800773c + 80046c8: 4618 mov r0, r3 + 80046ca: bd80 pop {r7, pc} + 80046cc: 40021000 .word 0x40021000 + 80046d0: 08007784 .word 0x08007784 -0800468c : +080046d4 : /** * @brief Compute SYSCLK frequency based on PLL SYSCLK source. * @retval SYSCLK frequency */ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { - 800468c: b480 push {r7} - 800468e: b087 sub sp, #28 - 8004690: af00 add r7, sp, #0 + 80046d4: b480 push {r7} + 80046d6: b087 sub sp, #28 + 80046d8: af00 add r7, sp, #0 uint32_t sysclockfreq; /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - 8004692: 4b1e ldr r3, [pc, #120] @ (800470c ) - 8004694: 68db ldr r3, [r3, #12] - 8004696: f003 0303 and.w r3, r3, #3 - 800469a: 613b str r3, [r7, #16] + 80046da: 4b1e ldr r3, [pc, #120] @ (8004754 ) + 80046dc: 68db ldr r3, [r3, #12] + 80046de: f003 0303 and.w r3, r3, #3 + 80046e2: 613b str r3, [r7, #16] pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - 800469c: 4b1b ldr r3, [pc, #108] @ (800470c ) - 800469e: 68db ldr r3, [r3, #12] - 80046a0: 091b lsrs r3, r3, #4 - 80046a2: f003 030f and.w r3, r3, #15 - 80046a6: 3301 adds r3, #1 - 80046a8: 60fb str r3, [r7, #12] + 80046e4: 4b1b ldr r3, [pc, #108] @ (8004754 ) + 80046e6: 68db ldr r3, [r3, #12] + 80046e8: 091b lsrs r3, r3, #4 + 80046ea: f003 030f and.w r3, r3, #15 + 80046ee: 3301 adds r3, #1 + 80046f0: 60fb str r3, [r7, #12] switch (pllsource) - 80046aa: 693b ldr r3, [r7, #16] - 80046ac: 2b03 cmp r3, #3 - 80046ae: d10c bne.n 80046ca + 80046f2: 693b ldr r3, [r7, #16] + 80046f4: 2b03 cmp r3, #3 + 80046f6: d10c bne.n 8004712 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - 80046b0: 4a17 ldr r2, [pc, #92] @ (8004710 ) - 80046b2: 68fb ldr r3, [r7, #12] - 80046b4: fbb2 f3f3 udiv r3, r2, r3 - 80046b8: 4a14 ldr r2, [pc, #80] @ (800470c ) - 80046ba: 68d2 ldr r2, [r2, #12] - 80046bc: 0a12 lsrs r2, r2, #8 - 80046be: f002 027f and.w r2, r2, #127 @ 0x7f - 80046c2: fb02 f303 mul.w r3, r2, r3 - 80046c6: 617b str r3, [r7, #20] + 80046f8: 4a17 ldr r2, [pc, #92] @ (8004758 ) + 80046fa: 68fb ldr r3, [r7, #12] + 80046fc: fbb2 f3f3 udiv r3, r2, r3 + 8004700: 4a14 ldr r2, [pc, #80] @ (8004754 ) + 8004702: 68d2 ldr r2, [r2, #12] + 8004704: 0a12 lsrs r2, r2, #8 + 8004706: f002 027f and.w r2, r2, #127 @ 0x7f + 800470a: fb02 f303 mul.w r3, r2, r3 + 800470e: 617b str r3, [r7, #20] break; - 80046c8: e00c b.n 80046e4 + 8004710: e00c b.n 800472c case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ default: pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - 80046ca: 4a12 ldr r2, [pc, #72] @ (8004714 ) - 80046cc: 68fb ldr r3, [r7, #12] - 80046ce: fbb2 f3f3 udiv r3, r2, r3 - 80046d2: 4a0e ldr r2, [pc, #56] @ (800470c ) - 80046d4: 68d2 ldr r2, [r2, #12] - 80046d6: 0a12 lsrs r2, r2, #8 - 80046d8: f002 027f and.w r2, r2, #127 @ 0x7f - 80046dc: fb02 f303 mul.w r3, r2, r3 - 80046e0: 617b str r3, [r7, #20] + 8004712: 4a12 ldr r2, [pc, #72] @ (800475c ) + 8004714: 68fb ldr r3, [r7, #12] + 8004716: fbb2 f3f3 udiv r3, r2, r3 + 800471a: 4a0e ldr r2, [pc, #56] @ (8004754 ) + 800471c: 68d2 ldr r2, [r2, #12] + 800471e: 0a12 lsrs r2, r2, #8 + 8004720: f002 027f and.w r2, r2, #127 @ 0x7f + 8004724: fb02 f303 mul.w r3, r2, r3 + 8004728: 617b str r3, [r7, #20] break; - 80046e2: bf00 nop + 800472a: bf00 nop } pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - 80046e4: 4b09 ldr r3, [pc, #36] @ (800470c ) - 80046e6: 68db ldr r3, [r3, #12] - 80046e8: 0e5b lsrs r3, r3, #25 - 80046ea: f003 0303 and.w r3, r3, #3 - 80046ee: 3301 adds r3, #1 - 80046f0: 005b lsls r3, r3, #1 - 80046f2: 60bb str r3, [r7, #8] + 800472c: 4b09 ldr r3, [pc, #36] @ (8004754 ) + 800472e: 68db ldr r3, [r3, #12] + 8004730: 0e5b lsrs r3, r3, #25 + 8004732: f003 0303 and.w r3, r3, #3 + 8004736: 3301 adds r3, #1 + 8004738: 005b lsls r3, r3, #1 + 800473a: 60bb str r3, [r7, #8] sysclockfreq = pllvco/pllr; - 80046f4: 697a ldr r2, [r7, #20] - 80046f6: 68bb ldr r3, [r7, #8] - 80046f8: fbb2 f3f3 udiv r3, r2, r3 - 80046fc: 607b str r3, [r7, #4] + 800473c: 697a ldr r2, [r7, #20] + 800473e: 68bb ldr r3, [r7, #8] + 8004740: fbb2 f3f3 udiv r3, r2, r3 + 8004744: 607b str r3, [r7, #4] return sysclockfreq; - 80046fe: 687b ldr r3, [r7, #4] + 8004746: 687b ldr r3, [r7, #4] } - 8004700: 4618 mov r0, r3 - 8004702: 371c adds r7, #28 - 8004704: 46bd mov sp, r7 - 8004706: f85d 7b04 ldr.w r7, [sp], #4 - 800470a: 4770 bx lr - 800470c: 40021000 .word 0x40021000 - 8004710: 007a1200 .word 0x007a1200 - 8004714: 00f42400 .word 0x00f42400 + 8004748: 4618 mov r0, r3 + 800474a: 371c adds r7, #28 + 800474c: 46bd mov sp, r7 + 800474e: f85d 7b04 ldr.w r7, [sp], #4 + 8004752: 4770 bx lr + 8004754: 40021000 .word 0x40021000 + 8004758: 007a1200 .word 0x007a1200 + 800475c: 00f42400 .word 0x00f42400 -08004718 : +08004760 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8004718: b580 push {r7, lr} - 800471a: b086 sub sp, #24 - 800471c: af00 add r7, sp, #0 - 800471e: 6078 str r0, [r7, #4] + 8004760: b580 push {r7, lr} + 8004762: b086 sub sp, #24 + 8004764: af00 add r7, sp, #0 + 8004766: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - 8004720: 2300 movs r3, #0 - 8004722: 74fb strb r3, [r7, #19] + 8004768: 2300 movs r3, #0 + 800476a: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ - 8004724: 2300 movs r3, #0 - 8004726: 74bb strb r3, [r7, #18] + 800476c: 2300 movs r3, #0 + 800476e: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - 8004728: 687b ldr r3, [r7, #4] - 800472a: 681b ldr r3, [r3, #0] - 800472c: f403 2300 and.w r3, r3, #524288 @ 0x80000 - 8004730: 2b00 cmp r3, #0 - 8004732: f000 8098 beq.w 8004866 + 8004770: 687b ldr r3, [r7, #4] + 8004772: 681b ldr r3, [r3, #0] + 8004774: f403 2300 and.w r3, r3, #524288 @ 0x80000 + 8004778: 2b00 cmp r3, #0 + 800477a: f000 8098 beq.w 80048ae { FlagStatus pwrclkchanged = RESET; - 8004736: 2300 movs r3, #0 - 8004738: 747b strb r3, [r7, #17] + 800477e: 2300 movs r3, #0 + 8004780: 747b strb r3, [r7, #17] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 800473a: 4b43 ldr r3, [pc, #268] @ (8004848 ) - 800473c: 6d9b ldr r3, [r3, #88] @ 0x58 - 800473e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 8004742: 2b00 cmp r3, #0 - 8004744: d10d bne.n 8004762 + 8004782: 4b43 ldr r3, [pc, #268] @ (8004890 ) + 8004784: 6d9b ldr r3, [r3, #88] @ 0x58 + 8004786: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 800478a: 2b00 cmp r3, #0 + 800478c: d10d bne.n 80047aa { __HAL_RCC_PWR_CLK_ENABLE(); - 8004746: 4b40 ldr r3, [pc, #256] @ (8004848 ) - 8004748: 6d9b ldr r3, [r3, #88] @ 0x58 - 800474a: 4a3f ldr r2, [pc, #252] @ (8004848 ) - 800474c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8004750: 6593 str r3, [r2, #88] @ 0x58 - 8004752: 4b3d ldr r3, [pc, #244] @ (8004848 ) - 8004754: 6d9b ldr r3, [r3, #88] @ 0x58 - 8004756: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 800475a: 60bb str r3, [r7, #8] - 800475c: 68bb ldr r3, [r7, #8] + 800478e: 4b40 ldr r3, [pc, #256] @ (8004890 ) + 8004790: 6d9b ldr r3, [r3, #88] @ 0x58 + 8004792: 4a3f ldr r2, [pc, #252] @ (8004890 ) + 8004794: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 8004798: 6593 str r3, [r2, #88] @ 0x58 + 800479a: 4b3d ldr r3, [pc, #244] @ (8004890 ) + 800479c: 6d9b ldr r3, [r3, #88] @ 0x58 + 800479e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80047a2: 60bb str r3, [r7, #8] + 80047a4: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 800475e: 2301 movs r3, #1 - 8004760: 747b strb r3, [r7, #17] + 80047a6: 2301 movs r3, #1 + 80047a8: 747b strb r3, [r7, #17] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); - 8004762: 4b3a ldr r3, [pc, #232] @ (800484c ) - 8004764: 681b ldr r3, [r3, #0] - 8004766: 4a39 ldr r2, [pc, #228] @ (800484c ) - 8004768: f443 7380 orr.w r3, r3, #256 @ 0x100 - 800476c: 6013 str r3, [r2, #0] + 80047aa: 4b3a ldr r3, [pc, #232] @ (8004894 ) + 80047ac: 681b ldr r3, [r3, #0] + 80047ae: 4a39 ldr r2, [pc, #228] @ (8004894 ) + 80047b0: f443 7380 orr.w r3, r3, #256 @ 0x100 + 80047b4: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 800476e: f7fd f9bd bl 8001aec - 8004772: 60f8 str r0, [r7, #12] + 80047b6: f7fd f9bd bl 8001b34 + 80047ba: 60f8 str r0, [r7, #12] while((PWR->CR1 & PWR_CR1_DBP) == 0U) - 8004774: e009 b.n 800478a + 80047bc: e009 b.n 80047d2 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8004776: f7fd f9b9 bl 8001aec - 800477a: 4602 mov r2, r0 - 800477c: 68fb ldr r3, [r7, #12] - 800477e: 1ad3 subs r3, r2, r3 - 8004780: 2b02 cmp r3, #2 - 8004782: d902 bls.n 800478a + 80047be: f7fd f9b9 bl 8001b34 + 80047c2: 4602 mov r2, r0 + 80047c4: 68fb ldr r3, [r7, #12] + 80047c6: 1ad3 subs r3, r2, r3 + 80047c8: 2b02 cmp r3, #2 + 80047ca: d902 bls.n 80047d2 { ret = HAL_TIMEOUT; - 8004784: 2303 movs r3, #3 - 8004786: 74fb strb r3, [r7, #19] + 80047cc: 2303 movs r3, #3 + 80047ce: 74fb strb r3, [r7, #19] break; - 8004788: e005 b.n 8004796 + 80047d0: e005 b.n 80047de while((PWR->CR1 & PWR_CR1_DBP) == 0U) - 800478a: 4b30 ldr r3, [pc, #192] @ (800484c ) - 800478c: 681b ldr r3, [r3, #0] - 800478e: f403 7380 and.w r3, r3, #256 @ 0x100 - 8004792: 2b00 cmp r3, #0 - 8004794: d0ef beq.n 8004776 + 80047d2: 4b30 ldr r3, [pc, #192] @ (8004894 ) + 80047d4: 681b ldr r3, [r3, #0] + 80047d6: f403 7380 and.w r3, r3, #256 @ 0x100 + 80047da: 2b00 cmp r3, #0 + 80047dc: d0ef beq.n 80047be } } if(ret == HAL_OK) - 8004796: 7cfb ldrb r3, [r7, #19] - 8004798: 2b00 cmp r3, #0 - 800479a: d159 bne.n 8004850 + 80047de: 7cfb ldrb r3, [r7, #19] + 80047e0: 2b00 cmp r3, #0 + 80047e2: d159 bne.n 8004898 { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - 800479c: 4b2a ldr r3, [pc, #168] @ (8004848 ) - 800479e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80047a2: f403 7340 and.w r3, r3, #768 @ 0x300 - 80047a6: 617b str r3, [r7, #20] + 80047e4: 4b2a ldr r3, [pc, #168] @ (8004890 ) + 80047e6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80047ea: f403 7340 and.w r3, r3, #768 @ 0x300 + 80047ee: 617b str r3, [r7, #20] if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) - 80047a8: 697b ldr r3, [r7, #20] - 80047aa: 2b00 cmp r3, #0 - 80047ac: d01e beq.n 80047ec - 80047ae: 687b ldr r3, [r7, #4] - 80047b0: 6c1b ldr r3, [r3, #64] @ 0x40 - 80047b2: 697a ldr r2, [r7, #20] - 80047b4: 429a cmp r2, r3 - 80047b6: d019 beq.n 80047ec + 80047f0: 697b ldr r3, [r7, #20] + 80047f2: 2b00 cmp r3, #0 + 80047f4: d01e beq.n 8004834 + 80047f6: 687b ldr r3, [r7, #4] + 80047f8: 6c1b ldr r3, [r3, #64] @ 0x40 + 80047fa: 697a ldr r2, [r7, #20] + 80047fc: 429a cmp r2, r3 + 80047fe: d019 beq.n 8004834 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); - 80047b8: 4b23 ldr r3, [pc, #140] @ (8004848 ) - 80047ba: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80047be: f423 7340 bic.w r3, r3, #768 @ 0x300 - 80047c2: 617b str r3, [r7, #20] + 8004800: 4b23 ldr r3, [pc, #140] @ (8004890 ) + 8004802: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004806: f423 7340 bic.w r3, r3, #768 @ 0x300 + 800480a: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 80047c4: 4b20 ldr r3, [pc, #128] @ (8004848 ) - 80047c6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80047ca: 4a1f ldr r2, [pc, #124] @ (8004848 ) - 80047cc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 80047d0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 800480c: 4b20 ldr r3, [pc, #128] @ (8004890 ) + 800480e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004812: 4a1f ldr r2, [pc, #124] @ (8004890 ) + 8004814: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8004818: f8c2 3090 str.w r3, [r2, #144] @ 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); - 80047d4: 4b1c ldr r3, [pc, #112] @ (8004848 ) - 80047d6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80047da: 4a1b ldr r2, [pc, #108] @ (8004848 ) - 80047dc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 - 80047e0: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 800481c: 4b1c ldr r3, [pc, #112] @ (8004890 ) + 800481e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004822: 4a1b ldr r2, [pc, #108] @ (8004890 ) + 8004824: f423 3380 bic.w r3, r3, #65536 @ 0x10000 + 8004828: f8c2 3090 str.w r3, [r2, #144] @ 0x90 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; - 80047e4: 4a18 ldr r2, [pc, #96] @ (8004848 ) - 80047e6: 697b ldr r3, [r7, #20] - 80047e8: f8c2 3090 str.w r3, [r2, #144] @ 0x90 + 800482c: 4a18 ldr r2, [pc, #96] @ (8004890 ) + 800482e: 697b ldr r3, [r7, #20] + 8004830: f8c2 3090 str.w r3, [r2, #144] @ 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) - 80047ec: 697b ldr r3, [r7, #20] - 80047ee: f003 0301 and.w r3, r3, #1 - 80047f2: 2b00 cmp r3, #0 - 80047f4: d016 beq.n 8004824 + 8004834: 697b ldr r3, [r7, #20] + 8004836: f003 0301 and.w r3, r3, #1 + 800483a: 2b00 cmp r3, #0 + 800483c: d016 beq.n 800486c { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80047f6: f7fd f979 bl 8001aec - 80047fa: 60f8 str r0, [r7, #12] + 800483e: f7fd f979 bl 8001b34 + 8004842: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 80047fc: e00b b.n 8004816 + 8004844: e00b b.n 800485e { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 80047fe: f7fd f975 bl 8001aec - 8004802: 4602 mov r2, r0 - 8004804: 68fb ldr r3, [r7, #12] - 8004806: 1ad3 subs r3, r2, r3 - 8004808: f241 3288 movw r2, #5000 @ 0x1388 - 800480c: 4293 cmp r3, r2 - 800480e: d902 bls.n 8004816 + 8004846: f7fd f975 bl 8001b34 + 800484a: 4602 mov r2, r0 + 800484c: 68fb ldr r3, [r7, #12] + 800484e: 1ad3 subs r3, r2, r3 + 8004850: f241 3288 movw r2, #5000 @ 0x1388 + 8004854: 4293 cmp r3, r2 + 8004856: d902 bls.n 800485e { ret = HAL_TIMEOUT; - 8004810: 2303 movs r3, #3 - 8004812: 74fb strb r3, [r7, #19] + 8004858: 2303 movs r3, #3 + 800485a: 74fb strb r3, [r7, #19] break; - 8004814: e006 b.n 8004824 + 800485c: e006 b.n 800486c while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - 8004816: 4b0c ldr r3, [pc, #48] @ (8004848 ) - 8004818: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800481c: f003 0302 and.w r3, r3, #2 - 8004820: 2b00 cmp r3, #0 - 8004822: d0ec beq.n 80047fe + 800485e: 4b0c ldr r3, [pc, #48] @ (8004890 ) + 8004860: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004864: f003 0302 and.w r3, r3, #2 + 8004868: 2b00 cmp r3, #0 + 800486a: d0ec beq.n 8004846 } } } if(ret == HAL_OK) - 8004824: 7cfb ldrb r3, [r7, #19] - 8004826: 2b00 cmp r3, #0 - 8004828: d10b bne.n 8004842 + 800486c: 7cfb ldrb r3, [r7, #19] + 800486e: 2b00 cmp r3, #0 + 8004870: d10b bne.n 800488a { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 800482a: 4b07 ldr r3, [pc, #28] @ (8004848 ) - 800482c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8004830: f423 7240 bic.w r2, r3, #768 @ 0x300 - 8004834: 687b ldr r3, [r7, #4] - 8004836: 6c1b ldr r3, [r3, #64] @ 0x40 - 8004838: 4903 ldr r1, [pc, #12] @ (8004848 ) - 800483a: 4313 orrs r3, r2 - 800483c: f8c1 3090 str.w r3, [r1, #144] @ 0x90 - 8004840: e008 b.n 8004854 + 8004872: 4b07 ldr r3, [pc, #28] @ (8004890 ) + 8004874: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8004878: f423 7240 bic.w r2, r3, #768 @ 0x300 + 800487c: 687b ldr r3, [r7, #4] + 800487e: 6c1b ldr r3, [r3, #64] @ 0x40 + 8004880: 4903 ldr r1, [pc, #12] @ (8004890 ) + 8004882: 4313 orrs r3, r2 + 8004884: f8c1 3090 str.w r3, [r1, #144] @ 0x90 + 8004888: e008 b.n 800489c } else { /* set overall return value */ status = ret; - 8004842: 7cfb ldrb r3, [r7, #19] - 8004844: 74bb strb r3, [r7, #18] - 8004846: e005 b.n 8004854 - 8004848: 40021000 .word 0x40021000 - 800484c: 40007000 .word 0x40007000 + 800488a: 7cfb ldrb r3, [r7, #19] + 800488c: 74bb strb r3, [r7, #18] + 800488e: e005 b.n 800489c + 8004890: 40021000 .word 0x40021000 + 8004894: 40007000 .word 0x40007000 } } else { /* set overall return value */ status = ret; - 8004850: 7cfb ldrb r3, [r7, #19] - 8004852: 74bb strb r3, [r7, #18] + 8004898: 7cfb ldrb r3, [r7, #19] + 800489a: 74bb strb r3, [r7, #18] } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) - 8004854: 7c7b ldrb r3, [r7, #17] - 8004856: 2b01 cmp r3, #1 - 8004858: d105 bne.n 8004866 + 800489c: 7c7b ldrb r3, [r7, #17] + 800489e: 2b01 cmp r3, #1 + 80048a0: d105 bne.n 80048ae { __HAL_RCC_PWR_CLK_DISABLE(); - 800485a: 4ba6 ldr r3, [pc, #664] @ (8004af4 ) - 800485c: 6d9b ldr r3, [r3, #88] @ 0x58 - 800485e: 4aa5 ldr r2, [pc, #660] @ (8004af4 ) - 8004860: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8004864: 6593 str r3, [r2, #88] @ 0x58 + 80048a2: 4ba6 ldr r3, [pc, #664] @ (8004b3c ) + 80048a4: 6d9b ldr r3, [r3, #88] @ 0x58 + 80048a6: 4aa5 ldr r2, [pc, #660] @ (8004b3c ) + 80048a8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80048ac: 6593 str r3, [r2, #88] @ 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8004866: 687b ldr r3, [r7, #4] - 8004868: 681b ldr r3, [r3, #0] - 800486a: f003 0301 and.w r3, r3, #1 - 800486e: 2b00 cmp r3, #0 - 8004870: d00a beq.n 8004888 + 80048ae: 687b ldr r3, [r7, #4] + 80048b0: 681b ldr r3, [r3, #0] + 80048b2: f003 0301 and.w r3, r3, #1 + 80048b6: 2b00 cmp r3, #0 + 80048b8: d00a beq.n 80048d0 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8004872: 4ba0 ldr r3, [pc, #640] @ (8004af4 ) - 8004874: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004878: f023 0203 bic.w r2, r3, #3 - 800487c: 687b ldr r3, [r7, #4] - 800487e: 685b ldr r3, [r3, #4] - 8004880: 499c ldr r1, [pc, #624] @ (8004af4 ) - 8004882: 4313 orrs r3, r2 - 8004884: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 80048ba: 4ba0 ldr r3, [pc, #640] @ (8004b3c ) + 80048bc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80048c0: f023 0203 bic.w r2, r3, #3 + 80048c4: 687b ldr r3, [r7, #4] + 80048c6: 685b ldr r3, [r3, #4] + 80048c8: 499c ldr r1, [pc, #624] @ (8004b3c ) + 80048ca: 4313 orrs r3, r2 + 80048cc: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 8004888: 687b ldr r3, [r7, #4] - 800488a: 681b ldr r3, [r3, #0] - 800488c: f003 0302 and.w r3, r3, #2 - 8004890: 2b00 cmp r3, #0 - 8004892: d00a beq.n 80048aa + 80048d0: 687b ldr r3, [r7, #4] + 80048d2: 681b ldr r3, [r3, #0] + 80048d4: f003 0302 and.w r3, r3, #2 + 80048d8: 2b00 cmp r3, #0 + 80048da: d00a beq.n 80048f2 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 8004894: 4b97 ldr r3, [pc, #604] @ (8004af4 ) - 8004896: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 800489a: f023 020c bic.w r2, r3, #12 - 800489e: 687b ldr r3, [r7, #4] - 80048a0: 689b ldr r3, [r3, #8] - 80048a2: 4994 ldr r1, [pc, #592] @ (8004af4 ) - 80048a4: 4313 orrs r3, r2 - 80048a6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 80048dc: 4b97 ldr r3, [pc, #604] @ (8004b3c ) + 80048de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80048e2: f023 020c bic.w r2, r3, #12 + 80048e6: 687b ldr r3, [r7, #4] + 80048e8: 689b ldr r3, [r3, #8] + 80048ea: 4994 ldr r1, [pc, #592] @ (8004b3c ) + 80048ec: 4313 orrs r3, r2 + 80048ee: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(USART3) /*-------------------------- USART3 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - 80048aa: 687b ldr r3, [r7, #4] - 80048ac: 681b ldr r3, [r3, #0] - 80048ae: f003 0304 and.w r3, r3, #4 - 80048b2: 2b00 cmp r3, #0 - 80048b4: d00a beq.n 80048cc + 80048f2: 687b ldr r3, [r7, #4] + 80048f4: 681b ldr r3, [r3, #0] + 80048f6: f003 0304 and.w r3, r3, #4 + 80048fa: 2b00 cmp r3, #0 + 80048fc: d00a beq.n 8004914 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - 80048b6: 4b8f ldr r3, [pc, #572] @ (8004af4 ) - 80048b8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80048bc: f023 0230 bic.w r2, r3, #48 @ 0x30 - 80048c0: 687b ldr r3, [r7, #4] - 80048c2: 68db ldr r3, [r3, #12] - 80048c4: 498b ldr r1, [pc, #556] @ (8004af4 ) - 80048c6: 4313 orrs r3, r2 - 80048c8: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 80048fe: 4b8f ldr r3, [pc, #572] @ (8004b3c ) + 8004900: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004904: f023 0230 bic.w r2, r3, #48 @ 0x30 + 8004908: 687b ldr r3, [r7, #4] + 800490a: 68db ldr r3, [r3, #12] + 800490c: 498b ldr r1, [pc, #556] @ (8004b3c ) + 800490e: 4313 orrs r3, r2 + 8004910: f8c1 3088 str.w r3, [r1, #136] @ 0x88 #endif /* USART3 */ #if defined(UART4) /*-------------------------- UART4 clock source configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - 80048cc: 687b ldr r3, [r7, #4] - 80048ce: 681b ldr r3, [r3, #0] - 80048d0: f003 0308 and.w r3, r3, #8 - 80048d4: 2b00 cmp r3, #0 - 80048d6: d00a beq.n 80048ee + 8004914: 687b ldr r3, [r7, #4] + 8004916: 681b ldr r3, [r3, #0] + 8004918: f003 0308 and.w r3, r3, #8 + 800491c: 2b00 cmp r3, #0 + 800491e: d00a beq.n 8004936 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - 80048d8: 4b86 ldr r3, [pc, #536] @ (8004af4 ) - 80048da: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80048de: f023 02c0 bic.w r2, r3, #192 @ 0xc0 - 80048e2: 687b ldr r3, [r7, #4] - 80048e4: 691b ldr r3, [r3, #16] - 80048e6: 4983 ldr r1, [pc, #524] @ (8004af4 ) - 80048e8: 4313 orrs r3, r2 - 80048ea: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004920: 4b86 ldr r3, [pc, #536] @ (8004b3c ) + 8004922: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004926: f023 02c0 bic.w r2, r3, #192 @ 0xc0 + 800492a: 687b ldr r3, [r7, #4] + 800492c: 691b ldr r3, [r3, #16] + 800492e: 4983 ldr r1, [pc, #524] @ (8004b3c ) + 8004930: 4313 orrs r3, r2 + 8004932: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) - 80048ee: 687b ldr r3, [r7, #4] - 80048f0: 681b ldr r3, [r3, #0] - 80048f2: f003 0320 and.w r3, r3, #32 - 80048f6: 2b00 cmp r3, #0 - 80048f8: d00a beq.n 8004910 + 8004936: 687b ldr r3, [r7, #4] + 8004938: 681b ldr r3, [r3, #0] + 800493a: f003 0320 and.w r3, r3, #32 + 800493e: 2b00 cmp r3, #0 + 8004940: d00a beq.n 8004958 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); - 80048fa: 4b7e ldr r3, [pc, #504] @ (8004af4 ) - 80048fc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004900: f423 6240 bic.w r2, r3, #3072 @ 0xc00 - 8004904: 687b ldr r3, [r7, #4] - 8004906: 695b ldr r3, [r3, #20] - 8004908: 497a ldr r1, [pc, #488] @ (8004af4 ) - 800490a: 4313 orrs r3, r2 - 800490c: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004942: 4b7e ldr r3, [pc, #504] @ (8004b3c ) + 8004944: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004948: f423 6240 bic.w r2, r3, #3072 @ 0xc00 + 800494c: 687b ldr r3, [r7, #4] + 800494e: 695b ldr r3, [r3, #20] + 8004950: 497a ldr r1, [pc, #488] @ (8004b3c ) + 8004952: 4313 orrs r3, r2 + 8004954: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 8004910: 687b ldr r3, [r7, #4] - 8004912: 681b ldr r3, [r3, #0] - 8004914: f003 0340 and.w r3, r3, #64 @ 0x40 - 8004918: 2b00 cmp r3, #0 - 800491a: d00a beq.n 8004932 + 8004958: 687b ldr r3, [r7, #4] + 800495a: 681b ldr r3, [r3, #0] + 800495c: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004960: 2b00 cmp r3, #0 + 8004962: d00a beq.n 800497a { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 800491c: 4b75 ldr r3, [pc, #468] @ (8004af4 ) - 800491e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004922: f423 5240 bic.w r2, r3, #12288 @ 0x3000 - 8004926: 687b ldr r3, [r7, #4] - 8004928: 699b ldr r3, [r3, #24] - 800492a: 4972 ldr r1, [pc, #456] @ (8004af4 ) - 800492c: 4313 orrs r3, r2 - 800492e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004964: 4b75 ldr r3, [pc, #468] @ (8004b3c ) + 8004966: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 800496a: f423 5240 bic.w r2, r3, #12288 @ 0x3000 + 800496e: 687b ldr r3, [r7, #4] + 8004970: 699b ldr r3, [r3, #24] + 8004972: 4972 ldr r1, [pc, #456] @ (8004b3c ) + 8004974: 4313 orrs r3, r2 + 8004976: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } /*-------------------------- I2C2 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - 8004932: 687b ldr r3, [r7, #4] - 8004934: 681b ldr r3, [r3, #0] - 8004936: f003 0380 and.w r3, r3, #128 @ 0x80 - 800493a: 2b00 cmp r3, #0 - 800493c: d00a beq.n 8004954 + 800497a: 687b ldr r3, [r7, #4] + 800497c: 681b ldr r3, [r3, #0] + 800497e: f003 0380 and.w r3, r3, #128 @ 0x80 + 8004982: 2b00 cmp r3, #0 + 8004984: d00a beq.n 800499c { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - 800493e: 4b6d ldr r3, [pc, #436] @ (8004af4 ) - 8004940: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004944: f423 4240 bic.w r2, r3, #49152 @ 0xc000 - 8004948: 687b ldr r3, [r7, #4] - 800494a: 69db ldr r3, [r3, #28] - 800494c: 4969 ldr r1, [pc, #420] @ (8004af4 ) - 800494e: 4313 orrs r3, r2 - 8004950: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004986: 4b6d ldr r3, [pc, #436] @ (8004b3c ) + 8004988: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 800498c: f423 4240 bic.w r2, r3, #49152 @ 0xc000 + 8004990: 687b ldr r3, [r7, #4] + 8004992: 69db ldr r3, [r3, #28] + 8004994: 4969 ldr r1, [pc, #420] @ (8004b3c ) + 8004996: 4313 orrs r3, r2 + 8004998: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(I2C3) /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - 8004954: 687b ldr r3, [r7, #4] - 8004956: 681b ldr r3, [r3, #0] - 8004958: f403 7380 and.w r3, r3, #256 @ 0x100 - 800495c: 2b00 cmp r3, #0 - 800495e: d00a beq.n 8004976 + 800499c: 687b ldr r3, [r7, #4] + 800499e: 681b ldr r3, [r3, #0] + 80049a0: f403 7380 and.w r3, r3, #256 @ 0x100 + 80049a4: 2b00 cmp r3, #0 + 80049a6: d00a beq.n 80049be { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - 8004960: 4b64 ldr r3, [pc, #400] @ (8004af4 ) - 8004962: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004966: f423 3240 bic.w r2, r3, #196608 @ 0x30000 - 800496a: 687b ldr r3, [r7, #4] - 800496c: 6a1b ldr r3, [r3, #32] - 800496e: 4961 ldr r1, [pc, #388] @ (8004af4 ) - 8004970: 4313 orrs r3, r2 - 8004972: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 80049a8: 4b64 ldr r3, [pc, #400] @ (8004b3c ) + 80049aa: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80049ae: f423 3240 bic.w r2, r3, #196608 @ 0x30000 + 80049b2: 687b ldr r3, [r7, #4] + 80049b4: 6a1b ldr r3, [r3, #32] + 80049b6: 4961 ldr r1, [pc, #388] @ (8004b3c ) + 80049b8: 4313 orrs r3, r2 + 80049ba: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #endif /* I2C4 */ /*-------------------------- LPTIM1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - 8004976: 687b ldr r3, [r7, #4] - 8004978: 681b ldr r3, [r3, #0] - 800497a: f403 7300 and.w r3, r3, #512 @ 0x200 - 800497e: 2b00 cmp r3, #0 - 8004980: d00a beq.n 8004998 + 80049be: 687b ldr r3, [r7, #4] + 80049c0: 681b ldr r3, [r3, #0] + 80049c2: f403 7300 and.w r3, r3, #512 @ 0x200 + 80049c6: 2b00 cmp r3, #0 + 80049c8: d00a beq.n 80049e0 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - 8004982: 4b5c ldr r3, [pc, #368] @ (8004af4 ) - 8004984: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004988: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 - 800498c: 687b ldr r3, [r7, #4] - 800498e: 6a5b ldr r3, [r3, #36] @ 0x24 - 8004990: 4958 ldr r1, [pc, #352] @ (8004af4 ) - 8004992: 4313 orrs r3, r2 - 8004994: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 80049ca: 4b5c ldr r3, [pc, #368] @ (8004b3c ) + 80049cc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80049d0: f423 2240 bic.w r2, r3, #786432 @ 0xc0000 + 80049d4: 687b ldr r3, [r7, #4] + 80049d6: 6a5b ldr r3, [r3, #36] @ 0x24 + 80049d8: 4958 ldr r1, [pc, #352] @ (8004b3c ) + 80049da: 4313 orrs r3, r2 + 80049dc: f8c1 3088 str.w r3, [r1, #136] @ 0x88 } #if defined(SAI1) /*-------------------------- SAI1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) - 8004998: 687b ldr r3, [r7, #4] - 800499a: 681b ldr r3, [r3, #0] - 800499c: f403 6380 and.w r3, r3, #1024 @ 0x400 - 80049a0: 2b00 cmp r3, #0 - 80049a2: d015 beq.n 80049d0 + 80049e0: 687b ldr r3, [r7, #4] + 80049e2: 681b ldr r3, [r3, #0] + 80049e4: f403 6380 and.w r3, r3, #1024 @ 0x400 + 80049e8: 2b00 cmp r3, #0 + 80049ea: d015 beq.n 8004a18 { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure the SAI1 interface clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - 80049a4: 4b53 ldr r3, [pc, #332] @ (8004af4 ) - 80049a6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80049aa: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 - 80049ae: 687b ldr r3, [r7, #4] - 80049b0: 6a9b ldr r3, [r3, #40] @ 0x28 - 80049b2: 4950 ldr r1, [pc, #320] @ (8004af4 ) - 80049b4: 4313 orrs r3, r2 - 80049b6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 80049ec: 4b53 ldr r3, [pc, #332] @ (8004b3c ) + 80049ee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80049f2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000 + 80049f6: 687b ldr r3, [r7, #4] + 80049f8: 6a9b ldr r3, [r3, #40] @ 0x28 + 80049fa: 4950 ldr r1, [pc, #320] @ (8004b3c ) + 80049fc: 4313 orrs r3, r2 + 80049fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL) - 80049ba: 687b ldr r3, [r7, #4] - 80049bc: 6a9b ldr r3, [r3, #40] @ 0x28 - 80049be: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 80049c2: d105 bne.n 80049d0 + 8004a02: 687b ldr r3, [r7, #4] + 8004a04: 6a9b ldr r3, [r3, #40] @ 0x28 + 8004a06: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 8004a0a: d105 bne.n 8004a18 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 80049c4: 4b4b ldr r3, [pc, #300] @ (8004af4 ) - 80049c6: 68db ldr r3, [r3, #12] - 80049c8: 4a4a ldr r2, [pc, #296] @ (8004af4 ) - 80049ca: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 80049ce: 60d3 str r3, [r2, #12] + 8004a0c: 4b4b ldr r3, [pc, #300] @ (8004b3c ) + 8004a0e: 68db ldr r3, [r3, #12] + 8004a10: 4a4a ldr r2, [pc, #296] @ (8004b3c ) + 8004a12: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8004a16: 60d3 str r3, [r2, #12] #endif /* SAI1 */ #if defined(SPI_I2S_SUPPORT) /*-------------------------- I2S clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) - 80049d0: 687b ldr r3, [r7, #4] - 80049d2: 681b ldr r3, [r3, #0] - 80049d4: f403 6300 and.w r3, r3, #2048 @ 0x800 - 80049d8: 2b00 cmp r3, #0 - 80049da: d015 beq.n 8004a08 + 8004a18: 687b ldr r3, [r7, #4] + 8004a1a: 681b ldr r3, [r3, #0] + 8004a1c: f403 6300 and.w r3, r3, #2048 @ 0x800 + 8004a20: 2b00 cmp r3, #0 + 8004a22: d015 beq.n 8004a50 { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure the I2S interface clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - 80049dc: 4b45 ldr r3, [pc, #276] @ (8004af4 ) - 80049de: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80049e2: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 - 80049e6: 687b ldr r3, [r7, #4] - 80049e8: 6adb ldr r3, [r3, #44] @ 0x2c - 80049ea: 4942 ldr r1, [pc, #264] @ (8004af4 ) - 80049ec: 4313 orrs r3, r2 - 80049ee: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004a24: 4b45 ldr r3, [pc, #276] @ (8004b3c ) + 8004a26: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004a2a: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000 + 8004a2e: 687b ldr r3, [r7, #4] + 8004a30: 6adb ldr r3, [r3, #44] @ 0x2c + 8004a32: 4942 ldr r1, [pc, #264] @ (8004b3c ) + 8004a34: 4313 orrs r3, r2 + 8004a36: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL) - 80049f2: 687b ldr r3, [r7, #4] - 80049f4: 6adb ldr r3, [r3, #44] @ 0x2c - 80049f6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 - 80049fa: d105 bne.n 8004a08 + 8004a3a: 687b ldr r3, [r7, #4] + 8004a3c: 6adb ldr r3, [r3, #44] @ 0x2c + 8004a3e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 + 8004a42: d105 bne.n 8004a50 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 80049fc: 4b3d ldr r3, [pc, #244] @ (8004af4 ) - 80049fe: 68db ldr r3, [r3, #12] - 8004a00: 4a3c ldr r2, [pc, #240] @ (8004af4 ) - 8004a02: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 8004a06: 60d3 str r3, [r2, #12] + 8004a44: 4b3d ldr r3, [pc, #244] @ (8004b3c ) + 8004a46: 68db ldr r3, [r3, #12] + 8004a48: 4a3c ldr r2, [pc, #240] @ (8004b3c ) + 8004a4a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8004a4e: 60d3 str r3, [r2, #12] #endif /* SPI_I2S_SUPPORT */ #if defined(FDCAN1) /*-------------------------- FDCAN clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) - 8004a08: 687b ldr r3, [r7, #4] - 8004a0a: 681b ldr r3, [r3, #0] - 8004a0c: f403 5380 and.w r3, r3, #4096 @ 0x1000 - 8004a10: 2b00 cmp r3, #0 - 8004a12: d015 beq.n 8004a40 + 8004a50: 687b ldr r3, [r7, #4] + 8004a52: 681b ldr r3, [r3, #0] + 8004a54: f403 5380 and.w r3, r3, #4096 @ 0x1000 + 8004a58: 2b00 cmp r3, #0 + 8004a5a: d015 beq.n 8004a88 { /* Check the parameters */ assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); /* Configure the FDCAN interface clock source */ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); - 8004a14: 4b37 ldr r3, [pc, #220] @ (8004af4 ) - 8004a16: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004a1a: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 - 8004a1e: 687b ldr r3, [r7, #4] - 8004a20: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004a22: 4934 ldr r1, [pc, #208] @ (8004af4 ) - 8004a24: 4313 orrs r3, r2 - 8004a26: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004a5c: 4b37 ldr r3, [pc, #220] @ (8004b3c ) + 8004a5e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004a62: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000 + 8004a66: 687b ldr r3, [r7, #4] + 8004a68: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004a6a: 4934 ldr r1, [pc, #208] @ (8004b3c ) + 8004a6c: 4313 orrs r3, r2 + 8004a6e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) - 8004a2a: 687b ldr r3, [r7, #4] - 8004a2c: 6b1b ldr r3, [r3, #48] @ 0x30 - 8004a2e: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 - 8004a32: d105 bne.n 8004a40 + 8004a72: 687b ldr r3, [r7, #4] + 8004a74: 6b1b ldr r3, [r3, #48] @ 0x30 + 8004a76: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 + 8004a7a: d105 bne.n 8004a88 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 8004a34: 4b2f ldr r3, [pc, #188] @ (8004af4 ) - 8004a36: 68db ldr r3, [r3, #12] - 8004a38: 4a2e ldr r2, [pc, #184] @ (8004af4 ) - 8004a3a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 8004a3e: 60d3 str r3, [r2, #12] + 8004a7c: 4b2f ldr r3, [pc, #188] @ (8004b3c ) + 8004a7e: 68db ldr r3, [r3, #12] + 8004a80: 4a2e ldr r2, [pc, #184] @ (8004b3c ) + 8004a82: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8004a86: 60d3 str r3, [r2, #12] #endif /* FDCAN1 */ #if defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) - 8004a40: 687b ldr r3, [r7, #4] - 8004a42: 681b ldr r3, [r3, #0] - 8004a44: f403 5300 and.w r3, r3, #8192 @ 0x2000 - 8004a48: 2b00 cmp r3, #0 - 8004a4a: d015 beq.n 8004a78 + 8004a88: 687b ldr r3, [r7, #4] + 8004a8a: 681b ldr r3, [r3, #0] + 8004a8c: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8004a90: 2b00 cmp r3, #0 + 8004a92: d015 beq.n 8004ac0 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - 8004a4c: 4b29 ldr r3, [pc, #164] @ (8004af4 ) - 8004a4e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004a52: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 - 8004a56: 687b ldr r3, [r7, #4] - 8004a58: 6b5b ldr r3, [r3, #52] @ 0x34 - 8004a5a: 4926 ldr r1, [pc, #152] @ (8004af4 ) - 8004a5c: 4313 orrs r3, r2 - 8004a5e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004a94: 4b29 ldr r3, [pc, #164] @ (8004b3c ) + 8004a96: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004a9a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 + 8004a9e: 687b ldr r3, [r7, #4] + 8004aa0: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004aa2: 4926 ldr r1, [pc, #152] @ (8004b3c ) + 8004aa4: 4313 orrs r3, r2 + 8004aa6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) - 8004a62: 687b ldr r3, [r7, #4] - 8004a64: 6b5b ldr r3, [r3, #52] @ 0x34 - 8004a66: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 - 8004a6a: d105 bne.n 8004a78 + 8004aaa: 687b ldr r3, [r7, #4] + 8004aac: 6b5b ldr r3, [r3, #52] @ 0x34 + 8004aae: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8004ab2: d105 bne.n 8004ac0 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 8004a6c: 4b21 ldr r3, [pc, #132] @ (8004af4 ) - 8004a6e: 68db ldr r3, [r3, #12] - 8004a70: 4a20 ldr r2, [pc, #128] @ (8004af4 ) - 8004a72: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 8004a76: 60d3 str r3, [r2, #12] + 8004ab4: 4b21 ldr r3, [pc, #132] @ (8004b3c ) + 8004ab6: 68db ldr r3, [r3, #12] + 8004ab8: 4a20 ldr r2, [pc, #128] @ (8004b3c ) + 8004aba: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8004abe: 60d3 str r3, [r2, #12] } #endif /* USB */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) - 8004a78: 687b ldr r3, [r7, #4] - 8004a7a: 681b ldr r3, [r3, #0] - 8004a7c: f403 4380 and.w r3, r3, #16384 @ 0x4000 - 8004a80: 2b00 cmp r3, #0 - 8004a82: d015 beq.n 8004ab0 + 8004ac0: 687b ldr r3, [r7, #4] + 8004ac2: 681b ldr r3, [r3, #0] + 8004ac4: f403 4380 and.w r3, r3, #16384 @ 0x4000 + 8004ac8: 2b00 cmp r3, #0 + 8004aca: d015 beq.n 8004af8 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); - 8004a84: 4b1b ldr r3, [pc, #108] @ (8004af4 ) - 8004a86: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004a8a: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 - 8004a8e: 687b ldr r3, [r7, #4] - 8004a90: 6b9b ldr r3, [r3, #56] @ 0x38 - 8004a92: 4918 ldr r1, [pc, #96] @ (8004af4 ) - 8004a94: 4313 orrs r3, r2 - 8004a96: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004acc: 4b1b ldr r3, [pc, #108] @ (8004b3c ) + 8004ace: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004ad2: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000 + 8004ad6: 687b ldr r3, [r7, #4] + 8004ad8: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004ada: 4918 ldr r1, [pc, #96] @ (8004b3c ) + 8004adc: 4313 orrs r3, r2 + 8004ade: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) - 8004a9a: 687b ldr r3, [r7, #4] - 8004a9c: 6b9b ldr r3, [r3, #56] @ 0x38 - 8004a9e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 - 8004aa2: d105 bne.n 8004ab0 + 8004ae2: 687b ldr r3, [r7, #4] + 8004ae4: 6b9b ldr r3, [r3, #56] @ 0x38 + 8004ae6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 + 8004aea: d105 bne.n 8004af8 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - 8004aa4: 4b13 ldr r3, [pc, #76] @ (8004af4 ) - 8004aa6: 68db ldr r3, [r3, #12] - 8004aa8: 4a12 ldr r2, [pc, #72] @ (8004af4 ) - 8004aaa: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 - 8004aae: 60d3 str r3, [r2, #12] + 8004aec: 4b13 ldr r3, [pc, #76] @ (8004b3c ) + 8004aee: 68db ldr r3, [r3, #12] + 8004af0: 4a12 ldr r2, [pc, #72] @ (8004b3c ) + 8004af2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 + 8004af6: 60d3 str r3, [r2, #12] } } /*-------------------------- ADC12 clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) - 8004ab0: 687b ldr r3, [r7, #4] - 8004ab2: 681b ldr r3, [r3, #0] - 8004ab4: f403 4300 and.w r3, r3, #32768 @ 0x8000 - 8004ab8: 2b00 cmp r3, #0 - 8004aba: d015 beq.n 8004ae8 + 8004af8: 687b ldr r3, [r7, #4] + 8004afa: 681b ldr r3, [r3, #0] + 8004afc: f403 4300 and.w r3, r3, #32768 @ 0x8000 + 8004b00: 2b00 cmp r3, #0 + 8004b02: d015 beq.n 8004b30 { /* Check the parameters */ assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection)); /* Configure the ADC12 interface clock source */ __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); - 8004abc: 4b0d ldr r3, [pc, #52] @ (8004af4 ) - 8004abe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8004ac2: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 - 8004ac6: 687b ldr r3, [r7, #4] - 8004ac8: 6bdb ldr r3, [r3, #60] @ 0x3c - 8004aca: 490a ldr r1, [pc, #40] @ (8004af4 ) - 8004acc: 4313 orrs r3, r2 - 8004ace: f8c1 3088 str.w r3, [r1, #136] @ 0x88 + 8004b04: 4b0d ldr r3, [pc, #52] @ (8004b3c ) + 8004b06: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8004b0a: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000 + 8004b0e: 687b ldr r3, [r7, #4] + 8004b10: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004b12: 490a ldr r1, [pc, #40] @ (8004b3c ) + 8004b14: 4313 orrs r3, r2 + 8004b16: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL) - 8004ad2: 687b ldr r3, [r7, #4] - 8004ad4: 6bdb ldr r3, [r3, #60] @ 0x3c - 8004ad6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 - 8004ada: d105 bne.n 8004ae8 + 8004b1a: 687b ldr r3, [r7, #4] + 8004b1c: 6bdb ldr r3, [r3, #60] @ 0x3c + 8004b1e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 8004b22: d105 bne.n 8004b30 { /* Enable PLLADCCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); - 8004adc: 4b05 ldr r3, [pc, #20] @ (8004af4 ) - 8004ade: 68db ldr r3, [r3, #12] - 8004ae0: 4a04 ldr r2, [pc, #16] @ (8004af4 ) - 8004ae2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 - 8004ae6: 60d3 str r3, [r2, #12] + 8004b24: 4b05 ldr r3, [pc, #20] @ (8004b3c ) + 8004b26: 68db ldr r3, [r3, #12] + 8004b28: 4a04 ldr r2, [pc, #16] @ (8004b3c ) + 8004b2a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 + 8004b2e: 60d3 str r3, [r2, #12] } } #endif /* QUADSPI */ return status; - 8004ae8: 7cbb ldrb r3, [r7, #18] + 8004b30: 7cbb ldrb r3, [r7, #18] } - 8004aea: 4618 mov r0, r3 - 8004aec: 3718 adds r7, #24 - 8004aee: 46bd mov sp, r7 - 8004af0: bd80 pop {r7, pc} - 8004af2: bf00 nop - 8004af4: 40021000 .word 0x40021000 + 8004b32: 4618 mov r0, r3 + 8004b34: 3718 adds r7, #24 + 8004b36: 46bd mov sp, r7 + 8004b38: bd80 pop {r7, pc} + 8004b3a: bf00 nop + 8004b3c: 40021000 .word 0x40021000 -08004af8 : +08004b40 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 8004af8: b580 push {r7, lr} - 8004afa: b082 sub sp, #8 - 8004afc: af00 add r7, sp, #0 - 8004afe: 6078 str r0, [r7, #4] + 8004b40: b580 push {r7, lr} + 8004b42: b082 sub sp, #8 + 8004b44: af00 add r7, sp, #0 + 8004b46: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 8004b00: 687b ldr r3, [r7, #4] - 8004b02: 2b00 cmp r3, #0 - 8004b04: d101 bne.n 8004b0a + 8004b48: 687b ldr r3, [r7, #4] + 8004b4a: 2b00 cmp r3, #0 + 8004b4c: d101 bne.n 8004b52 { return HAL_ERROR; - 8004b06: 2301 movs r3, #1 - 8004b08: e049 b.n 8004b9e + 8004b4e: 2301 movs r3, #1 + 8004b50: e049 b.n 8004be6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 8004b0a: 687b ldr r3, [r7, #4] - 8004b0c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d - 8004b10: b2db uxtb r3, r3 - 8004b12: 2b00 cmp r3, #0 - 8004b14: d106 bne.n 8004b24 + 8004b52: 687b ldr r3, [r7, #4] + 8004b54: f893 303d ldrb.w r3, [r3, #61] @ 0x3d + 8004b58: b2db uxtb r3, r3 + 8004b5a: 2b00 cmp r3, #0 + 8004b5c: d106 bne.n 8004b6c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8004b16: 687b ldr r3, [r7, #4] - 8004b18: 2200 movs r2, #0 - 8004b1a: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8004b5e: 687b ldr r3, [r7, #4] + 8004b60: 2200 movs r2, #0 + 8004b62: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 8004b1e: 6878 ldr r0, [r7, #4] - 8004b20: f7fc fe7c bl 800181c + 8004b66: 6878 ldr r0, [r7, #4] + 8004b68: f7fc fe7c bl 8001864 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8004b24: 687b ldr r3, [r7, #4] - 8004b26: 2202 movs r2, #2 - 8004b28: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8004b6c: 687b ldr r3, [r7, #4] + 8004b6e: 2202 movs r2, #2 + 8004b70: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8004b2c: 687b ldr r3, [r7, #4] - 8004b2e: 681a ldr r2, [r3, #0] - 8004b30: 687b ldr r3, [r7, #4] - 8004b32: 3304 adds r3, #4 - 8004b34: 4619 mov r1, r3 - 8004b36: 4610 mov r0, r2 - 8004b38: f000 fab0 bl 800509c + 8004b74: 687b ldr r3, [r7, #4] + 8004b76: 681a ldr r2, [r3, #0] + 8004b78: 687b ldr r3, [r7, #4] + 8004b7a: 3304 adds r3, #4 + 8004b7c: 4619 mov r1, r3 + 8004b7e: 4610 mov r0, r2 + 8004b80: f000 fab0 bl 80050e4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8004b3c: 687b ldr r3, [r7, #4] - 8004b3e: 2201 movs r2, #1 - 8004b40: f883 2048 strb.w r2, [r3, #72] @ 0x48 + 8004b84: 687b ldr r3, [r7, #4] + 8004b86: 2201 movs r2, #1 + 8004b88: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8004b44: 687b ldr r3, [r7, #4] - 8004b46: 2201 movs r2, #1 - 8004b48: f883 203e strb.w r2, [r3, #62] @ 0x3e - 8004b4c: 687b ldr r3, [r7, #4] - 8004b4e: 2201 movs r2, #1 - 8004b50: f883 203f strb.w r2, [r3, #63] @ 0x3f - 8004b54: 687b ldr r3, [r7, #4] - 8004b56: 2201 movs r2, #1 - 8004b58: f883 2040 strb.w r2, [r3, #64] @ 0x40 - 8004b5c: 687b ldr r3, [r7, #4] - 8004b5e: 2201 movs r2, #1 - 8004b60: f883 2041 strb.w r2, [r3, #65] @ 0x41 - 8004b64: 687b ldr r3, [r7, #4] - 8004b66: 2201 movs r2, #1 - 8004b68: f883 2042 strb.w r2, [r3, #66] @ 0x42 - 8004b6c: 687b ldr r3, [r7, #4] - 8004b6e: 2201 movs r2, #1 - 8004b70: f883 2043 strb.w r2, [r3, #67] @ 0x43 - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8004b74: 687b ldr r3, [r7, #4] - 8004b76: 2201 movs r2, #1 - 8004b78: f883 2044 strb.w r2, [r3, #68] @ 0x44 - 8004b7c: 687b ldr r3, [r7, #4] - 8004b7e: 2201 movs r2, #1 - 8004b80: f883 2045 strb.w r2, [r3, #69] @ 0x45 - 8004b84: 687b ldr r3, [r7, #4] - 8004b86: 2201 movs r2, #1 - 8004b88: f883 2046 strb.w r2, [r3, #70] @ 0x46 8004b8c: 687b ldr r3, [r7, #4] 8004b8e: 2201 movs r2, #1 - 8004b90: f883 2047 strb.w r2, [r3, #71] @ 0x47 + 8004b90: f883 203e strb.w r2, [r3, #62] @ 0x3e + 8004b94: 687b ldr r3, [r7, #4] + 8004b96: 2201 movs r2, #1 + 8004b98: f883 203f strb.w r2, [r3, #63] @ 0x3f + 8004b9c: 687b ldr r3, [r7, #4] + 8004b9e: 2201 movs r2, #1 + 8004ba0: f883 2040 strb.w r2, [r3, #64] @ 0x40 + 8004ba4: 687b ldr r3, [r7, #4] + 8004ba6: 2201 movs r2, #1 + 8004ba8: f883 2041 strb.w r2, [r3, #65] @ 0x41 + 8004bac: 687b ldr r3, [r7, #4] + 8004bae: 2201 movs r2, #1 + 8004bb0: f883 2042 strb.w r2, [r3, #66] @ 0x42 + 8004bb4: 687b ldr r3, [r7, #4] + 8004bb6: 2201 movs r2, #1 + 8004bb8: f883 2043 strb.w r2, [r3, #67] @ 0x43 + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 8004bbc: 687b ldr r3, [r7, #4] + 8004bbe: 2201 movs r2, #1 + 8004bc0: f883 2044 strb.w r2, [r3, #68] @ 0x44 + 8004bc4: 687b ldr r3, [r7, #4] + 8004bc6: 2201 movs r2, #1 + 8004bc8: f883 2045 strb.w r2, [r3, #69] @ 0x45 + 8004bcc: 687b ldr r3, [r7, #4] + 8004bce: 2201 movs r2, #1 + 8004bd0: f883 2046 strb.w r2, [r3, #70] @ 0x46 + 8004bd4: 687b ldr r3, [r7, #4] + 8004bd6: 2201 movs r2, #1 + 8004bd8: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8004b94: 687b ldr r3, [r7, #4] - 8004b96: 2201 movs r2, #1 - 8004b98: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8004bdc: 687b ldr r3, [r7, #4] + 8004bde: 2201 movs r2, #1 + 8004be0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; - 8004b9c: 2300 movs r3, #0 + 8004be4: 2300 movs r3, #0 } - 8004b9e: 4618 mov r0, r3 - 8004ba0: 3708 adds r7, #8 - 8004ba2: 46bd mov sp, r7 - 8004ba4: bd80 pop {r7, pc} + 8004be6: 4618 mov r0, r3 + 8004be8: 3708 adds r7, #8 + 8004bea: 46bd mov sp, r7 + 8004bec: bd80 pop {r7, pc} -08004ba6 : +08004bee : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 8004ba6: b580 push {r7, lr} - 8004ba8: b084 sub sp, #16 - 8004baa: af00 add r7, sp, #0 - 8004bac: 6078 str r0, [r7, #4] + 8004bee: b580 push {r7, lr} + 8004bf0: b084 sub sp, #16 + 8004bf2: af00 add r7, sp, #0 + 8004bf4: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; - 8004bae: 687b ldr r3, [r7, #4] - 8004bb0: 681b ldr r3, [r3, #0] - 8004bb2: 68db ldr r3, [r3, #12] - 8004bb4: 60fb str r3, [r7, #12] + 8004bf6: 687b ldr r3, [r7, #4] + 8004bf8: 681b ldr r3, [r3, #0] + 8004bfa: 68db ldr r3, [r3, #12] + 8004bfc: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; - 8004bb6: 687b ldr r3, [r7, #4] - 8004bb8: 681b ldr r3, [r3, #0] - 8004bba: 691b ldr r3, [r3, #16] - 8004bbc: 60bb str r3, [r7, #8] + 8004bfe: 687b ldr r3, [r7, #4] + 8004c00: 681b ldr r3, [r3, #0] + 8004c02: 691b ldr r3, [r3, #16] + 8004c04: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - 8004bbe: 68bb ldr r3, [r7, #8] - 8004bc0: f003 0302 and.w r3, r3, #2 - 8004bc4: 2b00 cmp r3, #0 - 8004bc6: d020 beq.n 8004c0a + 8004c06: 68bb ldr r3, [r7, #8] + 8004c08: f003 0302 and.w r3, r3, #2 + 8004c0c: 2b00 cmp r3, #0 + 8004c0e: d020 beq.n 8004c52 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - 8004bc8: 68fb ldr r3, [r7, #12] - 8004bca: f003 0302 and.w r3, r3, #2 - 8004bce: 2b00 cmp r3, #0 - 8004bd0: d01b beq.n 8004c0a + 8004c10: 68fb ldr r3, [r7, #12] + 8004c12: f003 0302 and.w r3, r3, #2 + 8004c16: 2b00 cmp r3, #0 + 8004c18: d01b beq.n 8004c52 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - 8004bd2: 687b ldr r3, [r7, #4] - 8004bd4: 681b ldr r3, [r3, #0] - 8004bd6: f06f 0202 mvn.w r2, #2 - 8004bda: 611a str r2, [r3, #16] + 8004c1a: 687b ldr r3, [r7, #4] + 8004c1c: 681b ldr r3, [r3, #0] + 8004c1e: f06f 0202 mvn.w r2, #2 + 8004c22: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 8004bdc: 687b ldr r3, [r7, #4] - 8004bde: 2201 movs r2, #1 - 8004be0: 771a strb r2, [r3, #28] + 8004c24: 687b ldr r3, [r7, #4] + 8004c26: 2201 movs r2, #1 + 8004c28: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 8004be2: 687b ldr r3, [r7, #4] - 8004be4: 681b ldr r3, [r3, #0] - 8004be6: 699b ldr r3, [r3, #24] - 8004be8: f003 0303 and.w r3, r3, #3 - 8004bec: 2b00 cmp r3, #0 - 8004bee: d003 beq.n 8004bf8 + 8004c2a: 687b ldr r3, [r7, #4] + 8004c2c: 681b ldr r3, [r3, #0] + 8004c2e: 699b ldr r3, [r3, #24] + 8004c30: f003 0303 and.w r3, r3, #3 + 8004c34: 2b00 cmp r3, #0 + 8004c36: d003 beq.n 8004c40 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8004bf0: 6878 ldr r0, [r7, #4] - 8004bf2: f000 fa35 bl 8005060 - 8004bf6: e005 b.n 8004c04 + 8004c38: 6878 ldr r0, [r7, #4] + 8004c3a: f000 fa35 bl 80050a8 + 8004c3e: e005 b.n 8004c4c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8004bf8: 6878 ldr r0, [r7, #4] - 8004bfa: f000 fa27 bl 800504c + 8004c40: 6878 ldr r0, [r7, #4] + 8004c42: f000 fa27 bl 8005094 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8004bfe: 6878 ldr r0, [r7, #4] - 8004c00: f000 fa38 bl 8005074 + 8004c46: 6878 ldr r0, [r7, #4] + 8004c48: f000 fa38 bl 80050bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8004c04: 687b ldr r3, [r7, #4] - 8004c06: 2200 movs r2, #0 - 8004c08: 771a strb r2, [r3, #28] + 8004c4c: 687b ldr r3, [r7, #4] + 8004c4e: 2200 movs r2, #0 + 8004c50: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - 8004c0a: 68bb ldr r3, [r7, #8] - 8004c0c: f003 0304 and.w r3, r3, #4 - 8004c10: 2b00 cmp r3, #0 - 8004c12: d020 beq.n 8004c56 + 8004c52: 68bb ldr r3, [r7, #8] + 8004c54: f003 0304 and.w r3, r3, #4 + 8004c58: 2b00 cmp r3, #0 + 8004c5a: d020 beq.n 8004c9e { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - 8004c14: 68fb ldr r3, [r7, #12] - 8004c16: f003 0304 and.w r3, r3, #4 - 8004c1a: 2b00 cmp r3, #0 - 8004c1c: d01b beq.n 8004c56 + 8004c5c: 68fb ldr r3, [r7, #12] + 8004c5e: f003 0304 and.w r3, r3, #4 + 8004c62: 2b00 cmp r3, #0 + 8004c64: d01b beq.n 8004c9e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - 8004c1e: 687b ldr r3, [r7, #4] - 8004c20: 681b ldr r3, [r3, #0] - 8004c22: f06f 0204 mvn.w r2, #4 - 8004c26: 611a str r2, [r3, #16] + 8004c66: 687b ldr r3, [r7, #4] + 8004c68: 681b ldr r3, [r3, #0] + 8004c6a: f06f 0204 mvn.w r2, #4 + 8004c6e: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 8004c28: 687b ldr r3, [r7, #4] - 8004c2a: 2202 movs r2, #2 - 8004c2c: 771a strb r2, [r3, #28] + 8004c70: 687b ldr r3, [r7, #4] + 8004c72: 2202 movs r2, #2 + 8004c74: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 8004c2e: 687b ldr r3, [r7, #4] - 8004c30: 681b ldr r3, [r3, #0] - 8004c32: 699b ldr r3, [r3, #24] - 8004c34: f403 7340 and.w r3, r3, #768 @ 0x300 - 8004c38: 2b00 cmp r3, #0 - 8004c3a: d003 beq.n 8004c44 + 8004c76: 687b ldr r3, [r7, #4] + 8004c78: 681b ldr r3, [r3, #0] + 8004c7a: 699b ldr r3, [r3, #24] + 8004c7c: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004c80: 2b00 cmp r3, #0 + 8004c82: d003 beq.n 8004c8c { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8004c3c: 6878 ldr r0, [r7, #4] - 8004c3e: f000 fa0f bl 8005060 - 8004c42: e005 b.n 8004c50 + 8004c84: 6878 ldr r0, [r7, #4] + 8004c86: f000 fa0f bl 80050a8 + 8004c8a: e005 b.n 8004c98 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8004c44: 6878 ldr r0, [r7, #4] - 8004c46: f000 fa01 bl 800504c + 8004c8c: 6878 ldr r0, [r7, #4] + 8004c8e: f000 fa01 bl 8005094 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8004c4a: 6878 ldr r0, [r7, #4] - 8004c4c: f000 fa12 bl 8005074 + 8004c92: 6878 ldr r0, [r7, #4] + 8004c94: f000 fa12 bl 80050bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8004c50: 687b ldr r3, [r7, #4] - 8004c52: 2200 movs r2, #0 - 8004c54: 771a strb r2, [r3, #28] + 8004c98: 687b ldr r3, [r7, #4] + 8004c9a: 2200 movs r2, #0 + 8004c9c: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - 8004c56: 68bb ldr r3, [r7, #8] - 8004c58: f003 0308 and.w r3, r3, #8 - 8004c5c: 2b00 cmp r3, #0 - 8004c5e: d020 beq.n 8004ca2 + 8004c9e: 68bb ldr r3, [r7, #8] + 8004ca0: f003 0308 and.w r3, r3, #8 + 8004ca4: 2b00 cmp r3, #0 + 8004ca6: d020 beq.n 8004cea { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - 8004c60: 68fb ldr r3, [r7, #12] - 8004c62: f003 0308 and.w r3, r3, #8 - 8004c66: 2b00 cmp r3, #0 - 8004c68: d01b beq.n 8004ca2 + 8004ca8: 68fb ldr r3, [r7, #12] + 8004caa: f003 0308 and.w r3, r3, #8 + 8004cae: 2b00 cmp r3, #0 + 8004cb0: d01b beq.n 8004cea { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - 8004c6a: 687b ldr r3, [r7, #4] - 8004c6c: 681b ldr r3, [r3, #0] - 8004c6e: f06f 0208 mvn.w r2, #8 - 8004c72: 611a str r2, [r3, #16] + 8004cb2: 687b ldr r3, [r7, #4] + 8004cb4: 681b ldr r3, [r3, #0] + 8004cb6: f06f 0208 mvn.w r2, #8 + 8004cba: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 8004c74: 687b ldr r3, [r7, #4] - 8004c76: 2204 movs r2, #4 - 8004c78: 771a strb r2, [r3, #28] + 8004cbc: 687b ldr r3, [r7, #4] + 8004cbe: 2204 movs r2, #4 + 8004cc0: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 8004c7a: 687b ldr r3, [r7, #4] - 8004c7c: 681b ldr r3, [r3, #0] - 8004c7e: 69db ldr r3, [r3, #28] - 8004c80: f003 0303 and.w r3, r3, #3 - 8004c84: 2b00 cmp r3, #0 - 8004c86: d003 beq.n 8004c90 + 8004cc2: 687b ldr r3, [r7, #4] + 8004cc4: 681b ldr r3, [r3, #0] + 8004cc6: 69db ldr r3, [r3, #28] + 8004cc8: f003 0303 and.w r3, r3, #3 + 8004ccc: 2b00 cmp r3, #0 + 8004cce: d003 beq.n 8004cd8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8004c88: 6878 ldr r0, [r7, #4] - 8004c8a: f000 f9e9 bl 8005060 - 8004c8e: e005 b.n 8004c9c + 8004cd0: 6878 ldr r0, [r7, #4] + 8004cd2: f000 f9e9 bl 80050a8 + 8004cd6: e005 b.n 8004ce4 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8004c90: 6878 ldr r0, [r7, #4] - 8004c92: f000 f9db bl 800504c + 8004cd8: 6878 ldr r0, [r7, #4] + 8004cda: f000 f9db bl 8005094 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8004c96: 6878 ldr r0, [r7, #4] - 8004c98: f000 f9ec bl 8005074 + 8004cde: 6878 ldr r0, [r7, #4] + 8004ce0: f000 f9ec bl 80050bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8004c9c: 687b ldr r3, [r7, #4] - 8004c9e: 2200 movs r2, #0 - 8004ca0: 771a strb r2, [r3, #28] + 8004ce4: 687b ldr r3, [r7, #4] + 8004ce6: 2200 movs r2, #0 + 8004ce8: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - 8004ca2: 68bb ldr r3, [r7, #8] - 8004ca4: f003 0310 and.w r3, r3, #16 - 8004ca8: 2b00 cmp r3, #0 - 8004caa: d020 beq.n 8004cee + 8004cea: 68bb ldr r3, [r7, #8] + 8004cec: f003 0310 and.w r3, r3, #16 + 8004cf0: 2b00 cmp r3, #0 + 8004cf2: d020 beq.n 8004d36 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - 8004cac: 68fb ldr r3, [r7, #12] - 8004cae: f003 0310 and.w r3, r3, #16 - 8004cb2: 2b00 cmp r3, #0 - 8004cb4: d01b beq.n 8004cee + 8004cf4: 68fb ldr r3, [r7, #12] + 8004cf6: f003 0310 and.w r3, r3, #16 + 8004cfa: 2b00 cmp r3, #0 + 8004cfc: d01b beq.n 8004d36 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - 8004cb6: 687b ldr r3, [r7, #4] - 8004cb8: 681b ldr r3, [r3, #0] - 8004cba: f06f 0210 mvn.w r2, #16 - 8004cbe: 611a str r2, [r3, #16] + 8004cfe: 687b ldr r3, [r7, #4] + 8004d00: 681b ldr r3, [r3, #0] + 8004d02: f06f 0210 mvn.w r2, #16 + 8004d06: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 8004cc0: 687b ldr r3, [r7, #4] - 8004cc2: 2208 movs r2, #8 - 8004cc4: 771a strb r2, [r3, #28] + 8004d08: 687b ldr r3, [r7, #4] + 8004d0a: 2208 movs r2, #8 + 8004d0c: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 8004cc6: 687b ldr r3, [r7, #4] - 8004cc8: 681b ldr r3, [r3, #0] - 8004cca: 69db ldr r3, [r3, #28] - 8004ccc: f403 7340 and.w r3, r3, #768 @ 0x300 - 8004cd0: 2b00 cmp r3, #0 - 8004cd2: d003 beq.n 8004cdc + 8004d0e: 687b ldr r3, [r7, #4] + 8004d10: 681b ldr r3, [r3, #0] + 8004d12: 69db ldr r3, [r3, #28] + 8004d14: f403 7340 and.w r3, r3, #768 @ 0x300 + 8004d18: 2b00 cmp r3, #0 + 8004d1a: d003 beq.n 8004d24 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8004cd4: 6878 ldr r0, [r7, #4] - 8004cd6: f000 f9c3 bl 8005060 - 8004cda: e005 b.n 8004ce8 + 8004d1c: 6878 ldr r0, [r7, #4] + 8004d1e: f000 f9c3 bl 80050a8 + 8004d22: e005 b.n 8004d30 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8004cdc: 6878 ldr r0, [r7, #4] - 8004cde: f000 f9b5 bl 800504c + 8004d24: 6878 ldr r0, [r7, #4] + 8004d26: f000 f9b5 bl 8005094 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8004ce2: 6878 ldr r0, [r7, #4] - 8004ce4: f000 f9c6 bl 8005074 + 8004d2a: 6878 ldr r0, [r7, #4] + 8004d2c: f000 f9c6 bl 80050bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8004ce8: 687b ldr r3, [r7, #4] - 8004cea: 2200 movs r2, #0 - 8004cec: 771a strb r2, [r3, #28] + 8004d30: 687b ldr r3, [r7, #4] + 8004d32: 2200 movs r2, #0 + 8004d34: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - 8004cee: 68bb ldr r3, [r7, #8] - 8004cf0: f003 0301 and.w r3, r3, #1 - 8004cf4: 2b00 cmp r3, #0 - 8004cf6: d00c beq.n 8004d12 + 8004d36: 68bb ldr r3, [r7, #8] + 8004d38: f003 0301 and.w r3, r3, #1 + 8004d3c: 2b00 cmp r3, #0 + 8004d3e: d00c beq.n 8004d5a { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - 8004cf8: 68fb ldr r3, [r7, #12] - 8004cfa: f003 0301 and.w r3, r3, #1 - 8004cfe: 2b00 cmp r3, #0 - 8004d00: d007 beq.n 8004d12 + 8004d40: 68fb ldr r3, [r7, #12] + 8004d42: f003 0301 and.w r3, r3, #1 + 8004d46: 2b00 cmp r3, #0 + 8004d48: d007 beq.n 8004d5a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); - 8004d02: 687b ldr r3, [r7, #4] - 8004d04: 681b ldr r3, [r3, #0] - 8004d06: f06f 0201 mvn.w r2, #1 - 8004d0a: 611a str r2, [r3, #16] + 8004d4a: 687b ldr r3, [r7, #4] + 8004d4c: 681b ldr r3, [r3, #0] + 8004d4e: f06f 0201 mvn.w r2, #1 + 8004d52: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 8004d0c: 6878 ldr r0, [r7, #4] - 8004d0e: f000 f993 bl 8005038 + 8004d54: 6878 ldr r0, [r7, #4] + 8004d56: f000 f993 bl 8005080 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - 8004d12: 68bb ldr r3, [r7, #8] - 8004d14: f003 0380 and.w r3, r3, #128 @ 0x80 - 8004d18: 2b00 cmp r3, #0 - 8004d1a: d104 bne.n 8004d26 + 8004d5a: 68bb ldr r3, [r7, #8] + 8004d5c: f003 0380 and.w r3, r3, #128 @ 0x80 + 8004d60: 2b00 cmp r3, #0 + 8004d62: d104 bne.n 8004d6e ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) - 8004d1c: 68bb ldr r3, [r7, #8] - 8004d1e: f403 5300 and.w r3, r3, #8192 @ 0x2000 + 8004d64: 68bb ldr r3, [r7, #8] + 8004d66: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - 8004d22: 2b00 cmp r3, #0 - 8004d24: d00c beq.n 8004d40 + 8004d6a: 2b00 cmp r3, #0 + 8004d6c: d00c beq.n 8004d88 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 8004d26: 68fb ldr r3, [r7, #12] - 8004d28: f003 0380 and.w r3, r3, #128 @ 0x80 - 8004d2c: 2b00 cmp r3, #0 - 8004d2e: d007 beq.n 8004d40 + 8004d6e: 68fb ldr r3, [r7, #12] + 8004d70: f003 0380 and.w r3, r3, #128 @ 0x80 + 8004d74: 2b00 cmp r3, #0 + 8004d76: d007 beq.n 8004d88 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); - 8004d30: 687b ldr r3, [r7, #4] - 8004d32: 681b ldr r3, [r3, #0] - 8004d34: f46f 5202 mvn.w r2, #8320 @ 0x2080 - 8004d38: 611a str r2, [r3, #16] + 8004d78: 687b ldr r3, [r7, #4] + 8004d7a: 681b ldr r3, [r3, #0] + 8004d7c: f46f 5202 mvn.w r2, #8320 @ 0x2080 + 8004d80: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 8004d3a: 6878 ldr r0, [r7, #4] - 8004d3c: f000 fb72 bl 8005424 + 8004d82: 6878 ldr r0, [r7, #4] + 8004d84: f000 fb72 bl 800546c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - 8004d40: 68bb ldr r3, [r7, #8] - 8004d42: f403 7380 and.w r3, r3, #256 @ 0x100 - 8004d46: 2b00 cmp r3, #0 - 8004d48: d00c beq.n 8004d64 + 8004d88: 68bb ldr r3, [r7, #8] + 8004d8a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8004d8e: 2b00 cmp r3, #0 + 8004d90: d00c beq.n 8004dac { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - 8004d4a: 68fb ldr r3, [r7, #12] - 8004d4c: f003 0380 and.w r3, r3, #128 @ 0x80 - 8004d50: 2b00 cmp r3, #0 - 8004d52: d007 beq.n 8004d64 + 8004d92: 68fb ldr r3, [r7, #12] + 8004d94: f003 0380 and.w r3, r3, #128 @ 0x80 + 8004d98: 2b00 cmp r3, #0 + 8004d9a: d007 beq.n 8004dac { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); - 8004d54: 687b ldr r3, [r7, #4] - 8004d56: 681b ldr r3, [r3, #0] - 8004d58: f46f 7280 mvn.w r2, #256 @ 0x100 - 8004d5c: 611a str r2, [r3, #16] + 8004d9c: 687b ldr r3, [r7, #4] + 8004d9e: 681b ldr r3, [r3, #0] + 8004da0: f46f 7280 mvn.w r2, #256 @ 0x100 + 8004da4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); - 8004d5e: 6878 ldr r0, [r7, #4] - 8004d60: f000 fb6a bl 8005438 + 8004da6: 6878 ldr r0, [r7, #4] + 8004da8: f000 fb6a bl 8005480 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - 8004d64: 68bb ldr r3, [r7, #8] - 8004d66: f003 0340 and.w r3, r3, #64 @ 0x40 - 8004d6a: 2b00 cmp r3, #0 - 8004d6c: d00c beq.n 8004d88 + 8004dac: 68bb ldr r3, [r7, #8] + 8004dae: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004db2: 2b00 cmp r3, #0 + 8004db4: d00c beq.n 8004dd0 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - 8004d6e: 68fb ldr r3, [r7, #12] - 8004d70: f003 0340 and.w r3, r3, #64 @ 0x40 - 8004d74: 2b00 cmp r3, #0 - 8004d76: d007 beq.n 8004d88 + 8004db6: 68fb ldr r3, [r7, #12] + 8004db8: f003 0340 and.w r3, r3, #64 @ 0x40 + 8004dbc: 2b00 cmp r3, #0 + 8004dbe: d007 beq.n 8004dd0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); - 8004d78: 687b ldr r3, [r7, #4] - 8004d7a: 681b ldr r3, [r3, #0] - 8004d7c: f06f 0240 mvn.w r2, #64 @ 0x40 - 8004d80: 611a str r2, [r3, #16] + 8004dc0: 687b ldr r3, [r7, #4] + 8004dc2: 681b ldr r3, [r3, #0] + 8004dc4: f06f 0240 mvn.w r2, #64 @ 0x40 + 8004dc8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 8004d82: 6878 ldr r0, [r7, #4] - 8004d84: f000 f980 bl 8005088 + 8004dca: 6878 ldr r0, [r7, #4] + 8004dcc: f000 f980 bl 80050d0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - 8004d88: 68bb ldr r3, [r7, #8] - 8004d8a: f003 0320 and.w r3, r3, #32 - 8004d8e: 2b00 cmp r3, #0 - 8004d90: d00c beq.n 8004dac + 8004dd0: 68bb ldr r3, [r7, #8] + 8004dd2: f003 0320 and.w r3, r3, #32 + 8004dd6: 2b00 cmp r3, #0 + 8004dd8: d00c beq.n 8004df4 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - 8004d92: 68fb ldr r3, [r7, #12] - 8004d94: f003 0320 and.w r3, r3, #32 - 8004d98: 2b00 cmp r3, #0 - 8004d9a: d007 beq.n 8004dac + 8004dda: 68fb ldr r3, [r7, #12] + 8004ddc: f003 0320 and.w r3, r3, #32 + 8004de0: 2b00 cmp r3, #0 + 8004de2: d007 beq.n 8004df4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); - 8004d9c: 687b ldr r3, [r7, #4] - 8004d9e: 681b ldr r3, [r3, #0] - 8004da0: f06f 0220 mvn.w r2, #32 - 8004da4: 611a str r2, [r3, #16] + 8004de4: 687b ldr r3, [r7, #4] + 8004de6: 681b ldr r3, [r3, #0] + 8004de8: f06f 0220 mvn.w r2, #32 + 8004dec: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 8004da6: 6878 ldr r0, [r7, #4] - 8004da8: f000 fb32 bl 8005410 + 8004dee: 6878 ldr r0, [r7, #4] + 8004df0: f000 fb32 bl 8005458 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Encoder index event */ if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) - 8004dac: 68bb ldr r3, [r7, #8] - 8004dae: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8004db2: 2b00 cmp r3, #0 - 8004db4: d00c beq.n 8004dd0 + 8004df4: 68bb ldr r3, [r7, #8] + 8004df6: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8004dfa: 2b00 cmp r3, #0 + 8004dfc: d00c beq.n 8004e18 { if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) - 8004db6: 68fb ldr r3, [r7, #12] - 8004db8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8004dbc: 2b00 cmp r3, #0 - 8004dbe: d007 beq.n 8004dd0 + 8004dfe: 68fb ldr r3, [r7, #12] + 8004e00: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8004e04: 2b00 cmp r3, #0 + 8004e06: d007 beq.n 8004e18 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); - 8004dc0: 687b ldr r3, [r7, #4] - 8004dc2: 681b ldr r3, [r3, #0] - 8004dc4: f46f 1280 mvn.w r2, #1048576 @ 0x100000 - 8004dc8: 611a str r2, [r3, #16] + 8004e08: 687b ldr r3, [r7, #4] + 8004e0a: 681b ldr r3, [r3, #0] + 8004e0c: f46f 1280 mvn.w r2, #1048576 @ 0x100000 + 8004e10: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->EncoderIndexCallback(htim); #else HAL_TIMEx_EncoderIndexCallback(htim); - 8004dca: 6878 ldr r0, [r7, #4] - 8004dcc: f000 fb3e bl 800544c + 8004e12: 6878 ldr r0, [r7, #4] + 8004e14: f000 fb3e bl 8005494 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Direction change event */ if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) - 8004dd0: 68bb ldr r3, [r7, #8] - 8004dd2: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 8004dd6: 2b00 cmp r3, #0 - 8004dd8: d00c beq.n 8004df4 + 8004e18: 68bb ldr r3, [r7, #8] + 8004e1a: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8004e1e: 2b00 cmp r3, #0 + 8004e20: d00c beq.n 8004e3c { if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) - 8004dda: 68fb ldr r3, [r7, #12] - 8004ddc: f403 1300 and.w r3, r3, #2097152 @ 0x200000 - 8004de0: 2b00 cmp r3, #0 - 8004de2: d007 beq.n 8004df4 + 8004e22: 68fb ldr r3, [r7, #12] + 8004e24: f403 1300 and.w r3, r3, #2097152 @ 0x200000 + 8004e28: 2b00 cmp r3, #0 + 8004e2a: d007 beq.n 8004e3c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); - 8004de4: 687b ldr r3, [r7, #4] - 8004de6: 681b ldr r3, [r3, #0] - 8004de8: f46f 1200 mvn.w r2, #2097152 @ 0x200000 - 8004dec: 611a str r2, [r3, #16] + 8004e2c: 687b ldr r3, [r7, #4] + 8004e2e: 681b ldr r3, [r3, #0] + 8004e30: f46f 1200 mvn.w r2, #2097152 @ 0x200000 + 8004e34: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->DirectionChangeCallback(htim); #else HAL_TIMEx_DirectionChangeCallback(htim); - 8004dee: 6878 ldr r0, [r7, #4] - 8004df0: f000 fb36 bl 8005460 + 8004e36: 6878 ldr r0, [r7, #4] + 8004e38: f000 fb36 bl 80054a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Index error event */ if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) - 8004df4: 68bb ldr r3, [r7, #8] - 8004df6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8004dfa: 2b00 cmp r3, #0 - 8004dfc: d00c beq.n 8004e18 + 8004e3c: 68bb ldr r3, [r7, #8] + 8004e3e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8004e42: 2b00 cmp r3, #0 + 8004e44: d00c beq.n 8004e60 { if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) - 8004dfe: 68fb ldr r3, [r7, #12] - 8004e00: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8004e04: 2b00 cmp r3, #0 - 8004e06: d007 beq.n 8004e18 + 8004e46: 68fb ldr r3, [r7, #12] + 8004e48: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8004e4c: 2b00 cmp r3, #0 + 8004e4e: d007 beq.n 8004e60 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); - 8004e08: 687b ldr r3, [r7, #4] - 8004e0a: 681b ldr r3, [r3, #0] - 8004e0c: f46f 0280 mvn.w r2, #4194304 @ 0x400000 - 8004e10: 611a str r2, [r3, #16] + 8004e50: 687b ldr r3, [r7, #4] + 8004e52: 681b ldr r3, [r3, #0] + 8004e54: f46f 0280 mvn.w r2, #4194304 @ 0x400000 + 8004e58: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IndexErrorCallback(htim); #else HAL_TIMEx_IndexErrorCallback(htim); - 8004e12: 6878 ldr r0, [r7, #4] - 8004e14: f000 fb2e bl 8005474 + 8004e5a: 6878 ldr r0, [r7, #4] + 8004e5c: f000 fb2e bl 80054bc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Transition error event */ if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) - 8004e18: 68bb ldr r3, [r7, #8] - 8004e1a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8004e1e: 2b00 cmp r3, #0 - 8004e20: d00c beq.n 8004e3c + 8004e60: 68bb ldr r3, [r7, #8] + 8004e62: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8004e66: 2b00 cmp r3, #0 + 8004e68: d00c beq.n 8004e84 { if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) - 8004e22: 68fb ldr r3, [r7, #12] - 8004e24: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8004e28: 2b00 cmp r3, #0 - 8004e2a: d007 beq.n 8004e3c + 8004e6a: 68fb ldr r3, [r7, #12] + 8004e6c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8004e70: 2b00 cmp r3, #0 + 8004e72: d007 beq.n 8004e84 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); - 8004e2c: 687b ldr r3, [r7, #4] - 8004e2e: 681b ldr r3, [r3, #0] - 8004e30: f46f 0200 mvn.w r2, #8388608 @ 0x800000 - 8004e34: 611a str r2, [r3, #16] + 8004e74: 687b ldr r3, [r7, #4] + 8004e76: 681b ldr r3, [r3, #0] + 8004e78: f46f 0200 mvn.w r2, #8388608 @ 0x800000 + 8004e7c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TransitionErrorCallback(htim); #else HAL_TIMEx_TransitionErrorCallback(htim); - 8004e36: 6878 ldr r0, [r7, #4] - 8004e38: f000 fb26 bl 8005488 + 8004e7e: 6878 ldr r0, [r7, #4] + 8004e80: f000 fb26 bl 80054d0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 8004e3c: bf00 nop - 8004e3e: 3710 adds r7, #16 - 8004e40: 46bd mov sp, r7 - 8004e42: bd80 pop {r7, pc} + 8004e84: bf00 nop + 8004e86: 3710 adds r7, #16 + 8004e88: 46bd mov sp, r7 + 8004e8a: bd80 pop {r7, pc} -08004e44 : +08004e8c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { - 8004e44: b580 push {r7, lr} - 8004e46: b084 sub sp, #16 - 8004e48: af00 add r7, sp, #0 - 8004e4a: 6078 str r0, [r7, #4] - 8004e4c: 6039 str r1, [r7, #0] + 8004e8c: b580 push {r7, lr} + 8004e8e: b084 sub sp, #16 + 8004e90: af00 add r7, sp, #0 + 8004e92: 6078 str r0, [r7, #4] + 8004e94: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; - 8004e4e: 2300 movs r3, #0 - 8004e50: 73fb strb r3, [r7, #15] + 8004e96: 2300 movs r3, #0 + 8004e98: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); - 8004e52: 687b ldr r3, [r7, #4] - 8004e54: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 8004e58: 2b01 cmp r3, #1 - 8004e5a: d101 bne.n 8004e60 - 8004e5c: 2302 movs r3, #2 - 8004e5e: e0de b.n 800501e - 8004e60: 687b ldr r3, [r7, #4] - 8004e62: 2201 movs r2, #1 - 8004e64: f883 203c strb.w r2, [r3, #60] @ 0x3c + 8004e9a: 687b ldr r3, [r7, #4] + 8004e9c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8004ea0: 2b01 cmp r3, #1 + 8004ea2: d101 bne.n 8004ea8 + 8004ea4: 2302 movs r3, #2 + 8004ea6: e0de b.n 8005066 + 8004ea8: 687b ldr r3, [r7, #4] + 8004eaa: 2201 movs r2, #1 + 8004eac: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; - 8004e68: 687b ldr r3, [r7, #4] - 8004e6a: 2202 movs r2, #2 - 8004e6c: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8004eb0: 687b ldr r3, [r7, #4] + 8004eb2: 2202 movs r2, #2 + 8004eb4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; - 8004e70: 687b ldr r3, [r7, #4] - 8004e72: 681b ldr r3, [r3, #0] - 8004e74: 689b ldr r3, [r3, #8] - 8004e76: 60bb str r3, [r7, #8] + 8004eb8: 687b ldr r3, [r7, #4] + 8004eba: 681b ldr r3, [r3, #0] + 8004ebc: 689b ldr r3, [r3, #8] + 8004ebe: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - 8004e78: 68bb ldr r3, [r7, #8] - 8004e7a: f423 1344 bic.w r3, r3, #3211264 @ 0x310000 - 8004e7e: f023 0377 bic.w r3, r3, #119 @ 0x77 - 8004e82: 60bb str r3, [r7, #8] + 8004ec0: 68bb ldr r3, [r7, #8] + 8004ec2: f423 1344 bic.w r3, r3, #3211264 @ 0x310000 + 8004ec6: f023 0377 bic.w r3, r3, #119 @ 0x77 + 8004eca: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 8004e84: 68bb ldr r3, [r7, #8] - 8004e86: f423 437f bic.w r3, r3, #65280 @ 0xff00 - 8004e8a: 60bb str r3, [r7, #8] + 8004ecc: 68bb ldr r3, [r7, #8] + 8004ece: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 8004ed2: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; - 8004e8c: 687b ldr r3, [r7, #4] - 8004e8e: 681b ldr r3, [r3, #0] - 8004e90: 68ba ldr r2, [r7, #8] - 8004e92: 609a str r2, [r3, #8] + 8004ed4: 687b ldr r3, [r7, #4] + 8004ed6: 681b ldr r3, [r3, #0] + 8004ed8: 68ba ldr r2, [r7, #8] + 8004eda: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) - 8004e94: 683b ldr r3, [r7, #0] - 8004e96: 681b ldr r3, [r3, #0] - 8004e98: 4a63 ldr r2, [pc, #396] @ (8005028 ) - 8004e9a: 4293 cmp r3, r2 - 8004e9c: f000 80a9 beq.w 8004ff2 - 8004ea0: 4a61 ldr r2, [pc, #388] @ (8005028 ) - 8004ea2: 4293 cmp r3, r2 - 8004ea4: f200 80ae bhi.w 8005004 - 8004ea8: 4a60 ldr r2, [pc, #384] @ (800502c ) - 8004eaa: 4293 cmp r3, r2 - 8004eac: f000 80a1 beq.w 8004ff2 - 8004eb0: 4a5e ldr r2, [pc, #376] @ (800502c ) - 8004eb2: 4293 cmp r3, r2 - 8004eb4: f200 80a6 bhi.w 8005004 - 8004eb8: 4a5d ldr r2, [pc, #372] @ (8005030 ) - 8004eba: 4293 cmp r3, r2 - 8004ebc: f000 8099 beq.w 8004ff2 - 8004ec0: 4a5b ldr r2, [pc, #364] @ (8005030 ) - 8004ec2: 4293 cmp r3, r2 - 8004ec4: f200 809e bhi.w 8005004 - 8004ec8: 4a5a ldr r2, [pc, #360] @ (8005034 ) - 8004eca: 4293 cmp r3, r2 - 8004ecc: f000 8091 beq.w 8004ff2 - 8004ed0: 4a58 ldr r2, [pc, #352] @ (8005034 ) - 8004ed2: 4293 cmp r3, r2 - 8004ed4: f200 8096 bhi.w 8005004 - 8004ed8: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 - 8004edc: f000 8089 beq.w 8004ff2 - 8004ee0: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 - 8004ee4: f200 808e bhi.w 8005004 - 8004ee8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 - 8004eec: d03e beq.n 8004f6c - 8004eee: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 - 8004ef2: f200 8087 bhi.w 8005004 - 8004ef6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8004efa: f000 8086 beq.w 800500a - 8004efe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8004f02: d87f bhi.n 8005004 - 8004f04: 2b70 cmp r3, #112 @ 0x70 - 8004f06: d01a beq.n 8004f3e - 8004f08: 2b70 cmp r3, #112 @ 0x70 - 8004f0a: d87b bhi.n 8005004 - 8004f0c: 2b60 cmp r3, #96 @ 0x60 - 8004f0e: d050 beq.n 8004fb2 - 8004f10: 2b60 cmp r3, #96 @ 0x60 - 8004f12: d877 bhi.n 8005004 - 8004f14: 2b50 cmp r3, #80 @ 0x50 - 8004f16: d03c beq.n 8004f92 - 8004f18: 2b50 cmp r3, #80 @ 0x50 - 8004f1a: d873 bhi.n 8005004 - 8004f1c: 2b40 cmp r3, #64 @ 0x40 - 8004f1e: d058 beq.n 8004fd2 - 8004f20: 2b40 cmp r3, #64 @ 0x40 - 8004f22: d86f bhi.n 8005004 - 8004f24: 2b30 cmp r3, #48 @ 0x30 - 8004f26: d064 beq.n 8004ff2 - 8004f28: 2b30 cmp r3, #48 @ 0x30 - 8004f2a: d86b bhi.n 8005004 - 8004f2c: 2b20 cmp r3, #32 - 8004f2e: d060 beq.n 8004ff2 - 8004f30: 2b20 cmp r3, #32 - 8004f32: d867 bhi.n 8005004 - 8004f34: 2b00 cmp r3, #0 - 8004f36: d05c beq.n 8004ff2 - 8004f38: 2b10 cmp r3, #16 - 8004f3a: d05a beq.n 8004ff2 - 8004f3c: e062 b.n 8005004 + 8004edc: 683b ldr r3, [r7, #0] + 8004ede: 681b ldr r3, [r3, #0] + 8004ee0: 4a63 ldr r2, [pc, #396] @ (8005070 ) + 8004ee2: 4293 cmp r3, r2 + 8004ee4: f000 80a9 beq.w 800503a + 8004ee8: 4a61 ldr r2, [pc, #388] @ (8005070 ) + 8004eea: 4293 cmp r3, r2 + 8004eec: f200 80ae bhi.w 800504c + 8004ef0: 4a60 ldr r2, [pc, #384] @ (8005074 ) + 8004ef2: 4293 cmp r3, r2 + 8004ef4: f000 80a1 beq.w 800503a + 8004ef8: 4a5e ldr r2, [pc, #376] @ (8005074 ) + 8004efa: 4293 cmp r3, r2 + 8004efc: f200 80a6 bhi.w 800504c + 8004f00: 4a5d ldr r2, [pc, #372] @ (8005078 ) + 8004f02: 4293 cmp r3, r2 + 8004f04: f000 8099 beq.w 800503a + 8004f08: 4a5b ldr r2, [pc, #364] @ (8005078 ) + 8004f0a: 4293 cmp r3, r2 + 8004f0c: f200 809e bhi.w 800504c + 8004f10: 4a5a ldr r2, [pc, #360] @ (800507c ) + 8004f12: 4293 cmp r3, r2 + 8004f14: f000 8091 beq.w 800503a + 8004f18: 4a58 ldr r2, [pc, #352] @ (800507c ) + 8004f1a: 4293 cmp r3, r2 + 8004f1c: f200 8096 bhi.w 800504c + 8004f20: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 + 8004f24: f000 8089 beq.w 800503a + 8004f28: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 + 8004f2c: f200 808e bhi.w 800504c + 8004f30: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8004f34: d03e beq.n 8004fb4 + 8004f36: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 + 8004f3a: f200 8087 bhi.w 800504c + 8004f3e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8004f42: f000 8086 beq.w 8005052 + 8004f46: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8004f4a: d87f bhi.n 800504c + 8004f4c: 2b70 cmp r3, #112 @ 0x70 + 8004f4e: d01a beq.n 8004f86 + 8004f50: 2b70 cmp r3, #112 @ 0x70 + 8004f52: d87b bhi.n 800504c + 8004f54: 2b60 cmp r3, #96 @ 0x60 + 8004f56: d050 beq.n 8004ffa + 8004f58: 2b60 cmp r3, #96 @ 0x60 + 8004f5a: d877 bhi.n 800504c + 8004f5c: 2b50 cmp r3, #80 @ 0x50 + 8004f5e: d03c beq.n 8004fda + 8004f60: 2b50 cmp r3, #80 @ 0x50 + 8004f62: d873 bhi.n 800504c + 8004f64: 2b40 cmp r3, #64 @ 0x40 + 8004f66: d058 beq.n 800501a + 8004f68: 2b40 cmp r3, #64 @ 0x40 + 8004f6a: d86f bhi.n 800504c + 8004f6c: 2b30 cmp r3, #48 @ 0x30 + 8004f6e: d064 beq.n 800503a + 8004f70: 2b30 cmp r3, #48 @ 0x30 + 8004f72: d86b bhi.n 800504c + 8004f74: 2b20 cmp r3, #32 + 8004f76: d060 beq.n 800503a + 8004f78: 2b20 cmp r3, #32 + 8004f7a: d867 bhi.n 800504c + 8004f7c: 2b00 cmp r3, #0 + 8004f7e: d05c beq.n 800503a + 8004f80: 2b10 cmp r3, #16 + 8004f82: d05a beq.n 800503a + 8004f84: e062 b.n 800504c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 8004f3e: 687b ldr r3, [r7, #4] - 8004f40: 6818 ldr r0, [r3, #0] + 8004f86: 687b ldr r3, [r7, #4] + 8004f88: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 8004f42: 683b ldr r3, [r7, #0] - 8004f44: 6899 ldr r1, [r3, #8] + 8004f8a: 683b ldr r3, [r7, #0] + 8004f8c: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 8004f46: 683b ldr r3, [r7, #0] - 8004f48: 685a ldr r2, [r3, #4] + 8004f8e: 683b ldr r3, [r7, #0] + 8004f90: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 8004f4a: 683b ldr r3, [r7, #0] - 8004f4c: 68db ldr r3, [r3, #12] + 8004f92: 683b ldr r3, [r7, #0] + 8004f94: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 8004f4e: f000 f9bd bl 80052cc + 8004f96: f000 f9bd bl 8005314 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; - 8004f52: 687b ldr r3, [r7, #4] - 8004f54: 681b ldr r3, [r3, #0] - 8004f56: 689b ldr r3, [r3, #8] - 8004f58: 60bb str r3, [r7, #8] + 8004f9a: 687b ldr r3, [r7, #4] + 8004f9c: 681b ldr r3, [r3, #0] + 8004f9e: 689b ldr r3, [r3, #8] + 8004fa0: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - 8004f5a: 68bb ldr r3, [r7, #8] - 8004f5c: f043 0377 orr.w r3, r3, #119 @ 0x77 - 8004f60: 60bb str r3, [r7, #8] + 8004fa2: 68bb ldr r3, [r7, #8] + 8004fa4: f043 0377 orr.w r3, r3, #119 @ 0x77 + 8004fa8: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 8004f62: 687b ldr r3, [r7, #4] - 8004f64: 681b ldr r3, [r3, #0] - 8004f66: 68ba ldr r2, [r7, #8] - 8004f68: 609a str r2, [r3, #8] + 8004faa: 687b ldr r3, [r7, #4] + 8004fac: 681b ldr r3, [r3, #0] + 8004fae: 68ba ldr r2, [r7, #8] + 8004fb0: 609a str r2, [r3, #8] break; - 8004f6a: e04f b.n 800500c + 8004fb2: e04f b.n 8005054 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, - 8004f6c: 687b ldr r3, [r7, #4] - 8004f6e: 6818 ldr r0, [r3, #0] + 8004fb4: 687b ldr r3, [r7, #4] + 8004fb6: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, - 8004f70: 683b ldr r3, [r7, #0] - 8004f72: 6899 ldr r1, [r3, #8] + 8004fb8: 683b ldr r3, [r7, #0] + 8004fba: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, - 8004f74: 683b ldr r3, [r7, #0] - 8004f76: 685a ldr r2, [r3, #4] + 8004fbc: 683b ldr r3, [r7, #0] + 8004fbe: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); - 8004f78: 683b ldr r3, [r7, #0] - 8004f7a: 68db ldr r3, [r3, #12] + 8004fc0: 683b ldr r3, [r7, #0] + 8004fc2: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, - 8004f7c: f000 f9a6 bl 80052cc + 8004fc4: f000 f9a6 bl 8005314 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; - 8004f80: 687b ldr r3, [r7, #4] - 8004f82: 681b ldr r3, [r3, #0] - 8004f84: 689a ldr r2, [r3, #8] - 8004f86: 687b ldr r3, [r7, #4] - 8004f88: 681b ldr r3, [r3, #0] - 8004f8a: f442 4280 orr.w r2, r2, #16384 @ 0x4000 - 8004f8e: 609a str r2, [r3, #8] + 8004fc8: 687b ldr r3, [r7, #4] + 8004fca: 681b ldr r3, [r3, #0] + 8004fcc: 689a ldr r2, [r3, #8] + 8004fce: 687b ldr r3, [r7, #4] + 8004fd0: 681b ldr r3, [r3, #0] + 8004fd2: f442 4280 orr.w r2, r2, #16384 @ 0x4000 + 8004fd6: 609a str r2, [r3, #8] break; - 8004f90: e03c b.n 800500c + 8004fd8: e03c b.n 8005054 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 8004f92: 687b ldr r3, [r7, #4] - 8004f94: 6818 ldr r0, [r3, #0] + 8004fda: 687b ldr r3, [r7, #4] + 8004fdc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8004f96: 683b ldr r3, [r7, #0] - 8004f98: 6859 ldr r1, [r3, #4] + 8004fde: 683b ldr r3, [r7, #0] + 8004fe0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 8004f9a: 683b ldr r3, [r7, #0] - 8004f9c: 68db ldr r3, [r3, #12] + 8004fe2: 683b ldr r3, [r7, #0] + 8004fe4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 8004f9e: 461a mov r2, r3 - 8004fa0: f000 f918 bl 80051d4 + 8004fe6: 461a mov r2, r3 + 8004fe8: f000 f918 bl 800521c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - 8004fa4: 687b ldr r3, [r7, #4] - 8004fa6: 681b ldr r3, [r3, #0] - 8004fa8: 2150 movs r1, #80 @ 0x50 - 8004faa: 4618 mov r0, r3 - 8004fac: f000 f971 bl 8005292 + 8004fec: 687b ldr r3, [r7, #4] + 8004fee: 681b ldr r3, [r3, #0] + 8004ff0: 2150 movs r1, #80 @ 0x50 + 8004ff2: 4618 mov r0, r3 + 8004ff4: f000 f971 bl 80052da break; - 8004fb0: e02c b.n 800500c + 8004ff8: e02c b.n 8005054 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, - 8004fb2: 687b ldr r3, [r7, #4] - 8004fb4: 6818 ldr r0, [r3, #0] + 8004ffa: 687b ldr r3, [r7, #4] + 8004ffc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8004fb6: 683b ldr r3, [r7, #0] - 8004fb8: 6859 ldr r1, [r3, #4] + 8004ffe: 683b ldr r3, [r7, #0] + 8005000: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 8004fba: 683b ldr r3, [r7, #0] - 8004fbc: 68db ldr r3, [r3, #12] + 8005002: 683b ldr r3, [r7, #0] + 8005004: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, - 8004fbe: 461a mov r2, r3 - 8004fc0: f000 f937 bl 8005232 + 8005006: 461a mov r2, r3 + 8005008: f000 f937 bl 800527a TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - 8004fc4: 687b ldr r3, [r7, #4] - 8004fc6: 681b ldr r3, [r3, #0] - 8004fc8: 2160 movs r1, #96 @ 0x60 - 8004fca: 4618 mov r0, r3 - 8004fcc: f000 f961 bl 8005292 + 800500c: 687b ldr r3, [r7, #4] + 800500e: 681b ldr r3, [r3, #0] + 8005010: 2160 movs r1, #96 @ 0x60 + 8005012: 4618 mov r0, r3 + 8005014: f000 f961 bl 80052da break; - 8004fd0: e01c b.n 800500c + 8005018: e01c b.n 8005054 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, - 8004fd2: 687b ldr r3, [r7, #4] - 8004fd4: 6818 ldr r0, [r3, #0] + 800501a: 687b ldr r3, [r7, #4] + 800501c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, - 8004fd6: 683b ldr r3, [r7, #0] - 8004fd8: 6859 ldr r1, [r3, #4] + 800501e: 683b ldr r3, [r7, #0] + 8005020: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); - 8004fda: 683b ldr r3, [r7, #0] - 8004fdc: 68db ldr r3, [r3, #12] + 8005022: 683b ldr r3, [r7, #0] + 8005024: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, - 8004fde: 461a mov r2, r3 - 8004fe0: f000 f8f8 bl 80051d4 + 8005026: 461a mov r2, r3 + 8005028: f000 f8f8 bl 800521c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - 8004fe4: 687b ldr r3, [r7, #4] - 8004fe6: 681b ldr r3, [r3, #0] - 8004fe8: 2140 movs r1, #64 @ 0x40 - 8004fea: 4618 mov r0, r3 - 8004fec: f000 f951 bl 8005292 + 800502c: 687b ldr r3, [r7, #4] + 800502e: 681b ldr r3, [r3, #0] + 8005030: 2140 movs r1, #64 @ 0x40 + 8005032: 4618 mov r0, r3 + 8005034: f000 f951 bl 80052da break; - 8004ff0: e00c b.n 800500c + 8005038: e00c b.n 8005054 case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - 8004ff2: 687b ldr r3, [r7, #4] - 8004ff4: 681a ldr r2, [r3, #0] - 8004ff6: 683b ldr r3, [r7, #0] - 8004ff8: 681b ldr r3, [r3, #0] - 8004ffa: 4619 mov r1, r3 - 8004ffc: 4610 mov r0, r2 - 8004ffe: f000 f948 bl 8005292 + 800503a: 687b ldr r3, [r7, #4] + 800503c: 681a ldr r2, [r3, #0] + 800503e: 683b ldr r3, [r7, #0] + 8005040: 681b ldr r3, [r3, #0] + 8005042: 4619 mov r1, r3 + 8005044: 4610 mov r0, r2 + 8005046: f000 f948 bl 80052da break; - 8005002: e003 b.n 800500c + 800504a: e003 b.n 8005054 } default: status = HAL_ERROR; - 8005004: 2301 movs r3, #1 - 8005006: 73fb strb r3, [r7, #15] + 800504c: 2301 movs r3, #1 + 800504e: 73fb strb r3, [r7, #15] break; - 8005008: e000 b.n 800500c + 8005050: e000 b.n 8005054 break; - 800500a: bf00 nop + 8005052: bf00 nop } htim->State = HAL_TIM_STATE_READY; - 800500c: 687b ldr r3, [r7, #4] - 800500e: 2201 movs r2, #1 - 8005010: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005054: 687b ldr r3, [r7, #4] + 8005056: 2201 movs r2, #1 + 8005058: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); - 8005014: 687b ldr r3, [r7, #4] - 8005016: 2200 movs r2, #0 - 8005018: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800505c: 687b ldr r3, [r7, #4] + 800505e: 2200 movs r2, #0 + 8005060: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; - 800501c: 7bfb ldrb r3, [r7, #15] + 8005064: 7bfb ldrb r3, [r7, #15] } - 800501e: 4618 mov r0, r3 - 8005020: 3710 adds r7, #16 - 8005022: 46bd mov sp, r7 - 8005024: bd80 pop {r7, pc} - 8005026: bf00 nop - 8005028: 00100070 .word 0x00100070 - 800502c: 00100040 .word 0x00100040 - 8005030: 00100030 .word 0x00100030 - 8005034: 00100020 .word 0x00100020 + 8005066: 4618 mov r0, r3 + 8005068: 3710 adds r7, #16 + 800506a: 46bd mov sp, r7 + 800506c: bd80 pop {r7, pc} + 800506e: bf00 nop + 8005070: 00100070 .word 0x00100070 + 8005074: 00100040 .word 0x00100040 + 8005078: 00100030 .word 0x00100030 + 800507c: 00100020 .word 0x00100020 -08005038 : +08005080 : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { - 8005038: b480 push {r7} - 800503a: b083 sub sp, #12 - 800503c: af00 add r7, sp, #0 - 800503e: 6078 str r0, [r7, #4] + 8005080: b480 push {r7} + 8005082: b083 sub sp, #12 + 8005084: af00 add r7, sp, #0 + 8005086: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } - 8005040: bf00 nop - 8005042: 370c adds r7, #12 - 8005044: 46bd mov sp, r7 - 8005046: f85d 7b04 ldr.w r7, [sp], #4 - 800504a: 4770 bx lr + 8005088: bf00 nop + 800508a: 370c adds r7, #12 + 800508c: 46bd mov sp, r7 + 800508e: f85d 7b04 ldr.w r7, [sp], #4 + 8005092: 4770 bx lr -0800504c : +08005094 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 800504c: b480 push {r7} - 800504e: b083 sub sp, #12 - 8005050: af00 add r7, sp, #0 - 8005052: 6078 str r0, [r7, #4] + 8005094: b480 push {r7} + 8005096: b083 sub sp, #12 + 8005098: af00 add r7, sp, #0 + 800509a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 8005054: bf00 nop - 8005056: 370c adds r7, #12 - 8005058: 46bd mov sp, r7 - 800505a: f85d 7b04 ldr.w r7, [sp], #4 - 800505e: 4770 bx lr + 800509c: bf00 nop + 800509e: 370c adds r7, #12 + 80050a0: 46bd mov sp, r7 + 80050a2: f85d 7b04 ldr.w r7, [sp], #4 + 80050a6: 4770 bx lr -08005060 : +080050a8 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8005060: b480 push {r7} - 8005062: b083 sub sp, #12 - 8005064: af00 add r7, sp, #0 - 8005066: 6078 str r0, [r7, #4] + 80050a8: b480 push {r7} + 80050aa: b083 sub sp, #12 + 80050ac: af00 add r7, sp, #0 + 80050ae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8005068: bf00 nop - 800506a: 370c adds r7, #12 - 800506c: 46bd mov sp, r7 - 800506e: f85d 7b04 ldr.w r7, [sp], #4 - 8005072: 4770 bx lr + 80050b0: bf00 nop + 80050b2: 370c adds r7, #12 + 80050b4: 46bd mov sp, r7 + 80050b6: f85d 7b04 ldr.w r7, [sp], #4 + 80050ba: 4770 bx lr -08005074 : +080050bc : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 8005074: b480 push {r7} - 8005076: b083 sub sp, #12 - 8005078: af00 add r7, sp, #0 - 800507a: 6078 str r0, [r7, #4] + 80050bc: b480 push {r7} + 80050be: b083 sub sp, #12 + 80050c0: af00 add r7, sp, #0 + 80050c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 800507c: bf00 nop - 800507e: 370c adds r7, #12 - 8005080: 46bd mov sp, r7 - 8005082: f85d 7b04 ldr.w r7, [sp], #4 - 8005086: 4770 bx lr + 80050c4: bf00 nop + 80050c6: 370c adds r7, #12 + 80050c8: 46bd mov sp, r7 + 80050ca: f85d 7b04 ldr.w r7, [sp], #4 + 80050ce: 4770 bx lr -08005088 : +080050d0 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8005088: b480 push {r7} - 800508a: b083 sub sp, #12 - 800508c: af00 add r7, sp, #0 - 800508e: 6078 str r0, [r7, #4] + 80050d0: b480 push {r7} + 80050d2: b083 sub sp, #12 + 80050d4: af00 add r7, sp, #0 + 80050d6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8005090: bf00 nop - 8005092: 370c adds r7, #12 - 8005094: 46bd mov sp, r7 - 8005096: f85d 7b04 ldr.w r7, [sp], #4 - 800509a: 4770 bx lr + 80050d8: bf00 nop + 80050da: 370c adds r7, #12 + 80050dc: 46bd mov sp, r7 + 80050de: f85d 7b04 ldr.w r7, [sp], #4 + 80050e2: 4770 bx lr -0800509c : +080050e4 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { - 800509c: b480 push {r7} - 800509e: b085 sub sp, #20 - 80050a0: af00 add r7, sp, #0 - 80050a2: 6078 str r0, [r7, #4] - 80050a4: 6039 str r1, [r7, #0] + 80050e4: b480 push {r7} + 80050e6: b085 sub sp, #20 + 80050e8: af00 add r7, sp, #0 + 80050ea: 6078 str r0, [r7, #4] + 80050ec: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 80050a6: 687b ldr r3, [r7, #4] - 80050a8: 681b ldr r3, [r3, #0] - 80050aa: 60fb str r3, [r7, #12] + 80050ee: 687b ldr r3, [r7, #4] + 80050f0: 681b ldr r3, [r3, #0] + 80050f2: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 80050ac: 687b ldr r3, [r7, #4] - 80050ae: 4a42 ldr r2, [pc, #264] @ (80051b8 ) - 80050b0: 4293 cmp r3, r2 - 80050b2: d00f beq.n 80050d4 - 80050b4: 687b ldr r3, [r7, #4] - 80050b6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80050ba: d00b beq.n 80050d4 - 80050bc: 687b ldr r3, [r7, #4] - 80050be: 4a3f ldr r2, [pc, #252] @ (80051bc ) - 80050c0: 4293 cmp r3, r2 - 80050c2: d007 beq.n 80050d4 - 80050c4: 687b ldr r3, [r7, #4] - 80050c6: 4a3e ldr r2, [pc, #248] @ (80051c0 ) - 80050c8: 4293 cmp r3, r2 - 80050ca: d003 beq.n 80050d4 - 80050cc: 687b ldr r3, [r7, #4] - 80050ce: 4a3d ldr r2, [pc, #244] @ (80051c4 ) - 80050d0: 4293 cmp r3, r2 - 80050d2: d108 bne.n 80050e6 + 80050f4: 687b ldr r3, [r7, #4] + 80050f6: 4a42 ldr r2, [pc, #264] @ (8005200 ) + 80050f8: 4293 cmp r3, r2 + 80050fa: d00f beq.n 800511c + 80050fc: 687b ldr r3, [r7, #4] + 80050fe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 8005102: d00b beq.n 800511c + 8005104: 687b ldr r3, [r7, #4] + 8005106: 4a3f ldr r2, [pc, #252] @ (8005204 ) + 8005108: 4293 cmp r3, r2 + 800510a: d007 beq.n 800511c + 800510c: 687b ldr r3, [r7, #4] + 800510e: 4a3e ldr r2, [pc, #248] @ (8005208 ) + 8005110: 4293 cmp r3, r2 + 8005112: d003 beq.n 800511c + 8005114: 687b ldr r3, [r7, #4] + 8005116: 4a3d ldr r2, [pc, #244] @ (800520c ) + 8005118: 4293 cmp r3, r2 + 800511a: d108 bne.n 800512e { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 80050d4: 68fb ldr r3, [r7, #12] - 80050d6: f023 0370 bic.w r3, r3, #112 @ 0x70 - 80050da: 60fb str r3, [r7, #12] + 800511c: 68fb ldr r3, [r7, #12] + 800511e: f023 0370 bic.w r3, r3, #112 @ 0x70 + 8005122: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 80050dc: 683b ldr r3, [r7, #0] - 80050de: 685b ldr r3, [r3, #4] - 80050e0: 68fa ldr r2, [r7, #12] - 80050e2: 4313 orrs r3, r2 - 80050e4: 60fb str r3, [r7, #12] + 8005124: 683b ldr r3, [r7, #0] + 8005126: 685b ldr r3, [r3, #4] + 8005128: 68fa ldr r2, [r7, #12] + 800512a: 4313 orrs r3, r2 + 800512c: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 80050e6: 687b ldr r3, [r7, #4] - 80050e8: 4a33 ldr r2, [pc, #204] @ (80051b8 ) - 80050ea: 4293 cmp r3, r2 - 80050ec: d01b beq.n 8005126 - 80050ee: 687b ldr r3, [r7, #4] - 80050f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 80050f4: d017 beq.n 8005126 - 80050f6: 687b ldr r3, [r7, #4] - 80050f8: 4a30 ldr r2, [pc, #192] @ (80051bc ) - 80050fa: 4293 cmp r3, r2 - 80050fc: d013 beq.n 8005126 - 80050fe: 687b ldr r3, [r7, #4] - 8005100: 4a2f ldr r2, [pc, #188] @ (80051c0 ) - 8005102: 4293 cmp r3, r2 - 8005104: d00f beq.n 8005126 - 8005106: 687b ldr r3, [r7, #4] - 8005108: 4a2e ldr r2, [pc, #184] @ (80051c4 ) - 800510a: 4293 cmp r3, r2 - 800510c: d00b beq.n 8005126 - 800510e: 687b ldr r3, [r7, #4] - 8005110: 4a2d ldr r2, [pc, #180] @ (80051c8 ) - 8005112: 4293 cmp r3, r2 - 8005114: d007 beq.n 8005126 - 8005116: 687b ldr r3, [r7, #4] - 8005118: 4a2c ldr r2, [pc, #176] @ (80051cc ) - 800511a: 4293 cmp r3, r2 - 800511c: d003 beq.n 8005126 - 800511e: 687b ldr r3, [r7, #4] - 8005120: 4a2b ldr r2, [pc, #172] @ (80051d0 ) - 8005122: 4293 cmp r3, r2 - 8005124: d108 bne.n 8005138 + 800512e: 687b ldr r3, [r7, #4] + 8005130: 4a33 ldr r2, [pc, #204] @ (8005200 ) + 8005132: 4293 cmp r3, r2 + 8005134: d01b beq.n 800516e + 8005136: 687b ldr r3, [r7, #4] + 8005138: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 800513c: d017 beq.n 800516e + 800513e: 687b ldr r3, [r7, #4] + 8005140: 4a30 ldr r2, [pc, #192] @ (8005204 ) + 8005142: 4293 cmp r3, r2 + 8005144: d013 beq.n 800516e + 8005146: 687b ldr r3, [r7, #4] + 8005148: 4a2f ldr r2, [pc, #188] @ (8005208 ) + 800514a: 4293 cmp r3, r2 + 800514c: d00f beq.n 800516e + 800514e: 687b ldr r3, [r7, #4] + 8005150: 4a2e ldr r2, [pc, #184] @ (800520c ) + 8005152: 4293 cmp r3, r2 + 8005154: d00b beq.n 800516e + 8005156: 687b ldr r3, [r7, #4] + 8005158: 4a2d ldr r2, [pc, #180] @ (8005210 ) + 800515a: 4293 cmp r3, r2 + 800515c: d007 beq.n 800516e + 800515e: 687b ldr r3, [r7, #4] + 8005160: 4a2c ldr r2, [pc, #176] @ (8005214 ) + 8005162: 4293 cmp r3, r2 + 8005164: d003 beq.n 800516e + 8005166: 687b ldr r3, [r7, #4] + 8005168: 4a2b ldr r2, [pc, #172] @ (8005218 ) + 800516a: 4293 cmp r3, r2 + 800516c: d108 bne.n 8005180 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 8005126: 68fb ldr r3, [r7, #12] - 8005128: f423 7340 bic.w r3, r3, #768 @ 0x300 - 800512c: 60fb str r3, [r7, #12] + 800516e: 68fb ldr r3, [r7, #12] + 8005170: f423 7340 bic.w r3, r3, #768 @ 0x300 + 8005174: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 800512e: 683b ldr r3, [r7, #0] - 8005130: 68db ldr r3, [r3, #12] - 8005132: 68fa ldr r2, [r7, #12] - 8005134: 4313 orrs r3, r2 - 8005136: 60fb str r3, [r7, #12] + 8005176: 683b ldr r3, [r7, #0] + 8005178: 68db ldr r3, [r3, #12] + 800517a: 68fa ldr r2, [r7, #12] + 800517c: 4313 orrs r3, r2 + 800517e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 8005138: 68fb ldr r3, [r7, #12] - 800513a: f023 0280 bic.w r2, r3, #128 @ 0x80 - 800513e: 683b ldr r3, [r7, #0] - 8005140: 695b ldr r3, [r3, #20] - 8005142: 4313 orrs r3, r2 - 8005144: 60fb str r3, [r7, #12] + 8005180: 68fb ldr r3, [r7, #12] + 8005182: f023 0280 bic.w r2, r3, #128 @ 0x80 + 8005186: 683b ldr r3, [r7, #0] + 8005188: 695b ldr r3, [r3, #20] + 800518a: 4313 orrs r3, r2 + 800518c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; - 8005146: 687b ldr r3, [r7, #4] - 8005148: 68fa ldr r2, [r7, #12] - 800514a: 601a str r2, [r3, #0] + 800518e: 687b ldr r3, [r7, #4] + 8005190: 68fa ldr r2, [r7, #12] + 8005192: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 800514c: 683b ldr r3, [r7, #0] - 800514e: 689a ldr r2, [r3, #8] - 8005150: 687b ldr r3, [r7, #4] - 8005152: 62da str r2, [r3, #44] @ 0x2c + 8005194: 683b ldr r3, [r7, #0] + 8005196: 689a ldr r2, [r3, #8] + 8005198: 687b ldr r3, [r7, #4] + 800519a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 8005154: 683b ldr r3, [r7, #0] - 8005156: 681a ldr r2, [r3, #0] - 8005158: 687b ldr r3, [r7, #4] - 800515a: 629a str r2, [r3, #40] @ 0x28 + 800519c: 683b ldr r3, [r7, #0] + 800519e: 681a ldr r2, [r3, #0] + 80051a0: 687b ldr r3, [r7, #4] + 80051a2: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 800515c: 687b ldr r3, [r7, #4] - 800515e: 4a16 ldr r2, [pc, #88] @ (80051b8 ) - 8005160: 4293 cmp r3, r2 - 8005162: d00f beq.n 8005184 - 8005164: 687b ldr r3, [r7, #4] - 8005166: 4a17 ldr r2, [pc, #92] @ (80051c4 ) - 8005168: 4293 cmp r3, r2 - 800516a: d00b beq.n 8005184 - 800516c: 687b ldr r3, [r7, #4] - 800516e: 4a16 ldr r2, [pc, #88] @ (80051c8 ) - 8005170: 4293 cmp r3, r2 - 8005172: d007 beq.n 8005184 - 8005174: 687b ldr r3, [r7, #4] - 8005176: 4a15 ldr r2, [pc, #84] @ (80051cc ) - 8005178: 4293 cmp r3, r2 - 800517a: d003 beq.n 8005184 - 800517c: 687b ldr r3, [r7, #4] - 800517e: 4a14 ldr r2, [pc, #80] @ (80051d0 ) - 8005180: 4293 cmp r3, r2 - 8005182: d103 bne.n 800518c + 80051a4: 687b ldr r3, [r7, #4] + 80051a6: 4a16 ldr r2, [pc, #88] @ (8005200 ) + 80051a8: 4293 cmp r3, r2 + 80051aa: d00f beq.n 80051cc + 80051ac: 687b ldr r3, [r7, #4] + 80051ae: 4a17 ldr r2, [pc, #92] @ (800520c ) + 80051b0: 4293 cmp r3, r2 + 80051b2: d00b beq.n 80051cc + 80051b4: 687b ldr r3, [r7, #4] + 80051b6: 4a16 ldr r2, [pc, #88] @ (8005210 ) + 80051b8: 4293 cmp r3, r2 + 80051ba: d007 beq.n 80051cc + 80051bc: 687b ldr r3, [r7, #4] + 80051be: 4a15 ldr r2, [pc, #84] @ (8005214 ) + 80051c0: 4293 cmp r3, r2 + 80051c2: d003 beq.n 80051cc + 80051c4: 687b ldr r3, [r7, #4] + 80051c6: 4a14 ldr r2, [pc, #80] @ (8005218 ) + 80051c8: 4293 cmp r3, r2 + 80051ca: d103 bne.n 80051d4 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 8005184: 683b ldr r3, [r7, #0] - 8005186: 691a ldr r2, [r3, #16] - 8005188: 687b ldr r3, [r7, #4] - 800518a: 631a str r2, [r3, #48] @ 0x30 + 80051cc: 683b ldr r3, [r7, #0] + 80051ce: 691a ldr r2, [r3, #16] + 80051d0: 687b ldr r3, [r7, #4] + 80051d2: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 800518c: 687b ldr r3, [r7, #4] - 800518e: 2201 movs r2, #1 - 8005190: 615a str r2, [r3, #20] + 80051d4: 687b ldr r3, [r7, #4] + 80051d6: 2201 movs r2, #1 + 80051d8: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - 8005192: 687b ldr r3, [r7, #4] - 8005194: 691b ldr r3, [r3, #16] - 8005196: f003 0301 and.w r3, r3, #1 - 800519a: 2b01 cmp r3, #1 - 800519c: d105 bne.n 80051aa + 80051da: 687b ldr r3, [r7, #4] + 80051dc: 691b ldr r3, [r3, #16] + 80051de: f003 0301 and.w r3, r3, #1 + 80051e2: 2b01 cmp r3, #1 + 80051e4: d105 bne.n 80051f2 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - 800519e: 687b ldr r3, [r7, #4] - 80051a0: 691b ldr r3, [r3, #16] - 80051a2: f023 0201 bic.w r2, r3, #1 - 80051a6: 687b ldr r3, [r7, #4] - 80051a8: 611a str r2, [r3, #16] + 80051e6: 687b ldr r3, [r7, #4] + 80051e8: 691b ldr r3, [r3, #16] + 80051ea: f023 0201 bic.w r2, r3, #1 + 80051ee: 687b ldr r3, [r7, #4] + 80051f0: 611a str r2, [r3, #16] } } - 80051aa: bf00 nop - 80051ac: 3714 adds r7, #20 - 80051ae: 46bd mov sp, r7 - 80051b0: f85d 7b04 ldr.w r7, [sp], #4 - 80051b4: 4770 bx lr - 80051b6: bf00 nop - 80051b8: 40012c00 .word 0x40012c00 - 80051bc: 40000400 .word 0x40000400 - 80051c0: 40000800 .word 0x40000800 - 80051c4: 40013400 .word 0x40013400 - 80051c8: 40014000 .word 0x40014000 - 80051cc: 40014400 .word 0x40014400 - 80051d0: 40014800 .word 0x40014800 + 80051f2: bf00 nop + 80051f4: 3714 adds r7, #20 + 80051f6: 46bd mov sp, r7 + 80051f8: f85d 7b04 ldr.w r7, [sp], #4 + 80051fc: 4770 bx lr + 80051fe: bf00 nop + 8005200: 40012c00 .word 0x40012c00 + 8005204: 40000400 .word 0x40000400 + 8005208: 40000800 .word 0x40000800 + 800520c: 40013400 .word 0x40013400 + 8005210: 40014000 .word 0x40014000 + 8005214: 40014400 .word 0x40014400 + 8005218: 40014800 .word 0x40014800 -080051d4 : +0800521c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 80051d4: b480 push {r7} - 80051d6: b087 sub sp, #28 - 80051d8: af00 add r7, sp, #0 - 80051da: 60f8 str r0, [r7, #12] - 80051dc: 60b9 str r1, [r7, #8] - 80051de: 607a str r2, [r7, #4] + 800521c: b480 push {r7} + 800521e: b087 sub sp, #28 + 8005220: af00 add r7, sp, #0 + 8005222: 60f8 str r0, [r7, #12] + 8005224: 60b9 str r1, [r7, #8] + 8005226: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; - 80051e0: 68fb ldr r3, [r7, #12] - 80051e2: 6a1b ldr r3, [r3, #32] - 80051e4: 617b str r3, [r7, #20] + 8005228: 68fb ldr r3, [r7, #12] + 800522a: 6a1b ldr r3, [r3, #32] + 800522c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; - 80051e6: 68fb ldr r3, [r7, #12] - 80051e8: 6a1b ldr r3, [r3, #32] - 80051ea: f023 0201 bic.w r2, r3, #1 - 80051ee: 68fb ldr r3, [r7, #12] - 80051f0: 621a str r2, [r3, #32] + 800522e: 68fb ldr r3, [r7, #12] + 8005230: 6a1b ldr r3, [r3, #32] + 8005232: f023 0201 bic.w r2, r3, #1 + 8005236: 68fb ldr r3, [r7, #12] + 8005238: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 80051f2: 68fb ldr r3, [r7, #12] - 80051f4: 699b ldr r3, [r3, #24] - 80051f6: 613b str r3, [r7, #16] + 800523a: 68fb ldr r3, [r7, #12] + 800523c: 699b ldr r3, [r3, #24] + 800523e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - 80051f8: 693b ldr r3, [r7, #16] - 80051fa: f023 03f0 bic.w r3, r3, #240 @ 0xf0 - 80051fe: 613b str r3, [r7, #16] + 8005240: 693b ldr r3, [r7, #16] + 8005242: f023 03f0 bic.w r3, r3, #240 @ 0xf0 + 8005246: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); - 8005200: 687b ldr r3, [r7, #4] - 8005202: 011b lsls r3, r3, #4 - 8005204: 693a ldr r2, [r7, #16] - 8005206: 4313 orrs r3, r2 - 8005208: 613b str r3, [r7, #16] + 8005248: 687b ldr r3, [r7, #4] + 800524a: 011b lsls r3, r3, #4 + 800524c: 693a ldr r2, [r7, #16] + 800524e: 4313 orrs r3, r2 + 8005250: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - 800520a: 697b ldr r3, [r7, #20] - 800520c: f023 030a bic.w r3, r3, #10 - 8005210: 617b str r3, [r7, #20] + 8005252: 697b ldr r3, [r7, #20] + 8005254: f023 030a bic.w r3, r3, #10 + 8005258: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; - 8005212: 697a ldr r2, [r7, #20] - 8005214: 68bb ldr r3, [r7, #8] - 8005216: 4313 orrs r3, r2 - 8005218: 617b str r3, [r7, #20] + 800525a: 697a ldr r2, [r7, #20] + 800525c: 68bb ldr r3, [r7, #8] + 800525e: 4313 orrs r3, r2 + 8005260: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; - 800521a: 68fb ldr r3, [r7, #12] - 800521c: 693a ldr r2, [r7, #16] - 800521e: 619a str r2, [r3, #24] + 8005262: 68fb ldr r3, [r7, #12] + 8005264: 693a ldr r2, [r7, #16] + 8005266: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 8005220: 68fb ldr r3, [r7, #12] - 8005222: 697a ldr r2, [r7, #20] - 8005224: 621a str r2, [r3, #32] + 8005268: 68fb ldr r3, [r7, #12] + 800526a: 697a ldr r2, [r7, #20] + 800526c: 621a str r2, [r3, #32] } - 8005226: bf00 nop - 8005228: 371c adds r7, #28 - 800522a: 46bd mov sp, r7 - 800522c: f85d 7b04 ldr.w r7, [sp], #4 - 8005230: 4770 bx lr + 800526e: bf00 nop + 8005270: 371c adds r7, #28 + 8005272: 46bd mov sp, r7 + 8005274: f85d 7b04 ldr.w r7, [sp], #4 + 8005278: 4770 bx lr -08005232 : +0800527a : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - 8005232: b480 push {r7} - 8005234: b087 sub sp, #28 - 8005236: af00 add r7, sp, #0 - 8005238: 60f8 str r0, [r7, #12] - 800523a: 60b9 str r1, [r7, #8] - 800523c: 607a str r2, [r7, #4] + 800527a: b480 push {r7} + 800527c: b087 sub sp, #28 + 800527e: af00 add r7, sp, #0 + 8005280: 60f8 str r0, [r7, #12] + 8005282: 60b9 str r1, [r7, #8] + 8005284: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; - 800523e: 68fb ldr r3, [r7, #12] - 8005240: 6a1b ldr r3, [r3, #32] - 8005242: 617b str r3, [r7, #20] + 8005286: 68fb ldr r3, [r7, #12] + 8005288: 6a1b ldr r3, [r3, #32] + 800528a: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; - 8005244: 68fb ldr r3, [r7, #12] - 8005246: 6a1b ldr r3, [r3, #32] - 8005248: f023 0210 bic.w r2, r3, #16 - 800524c: 68fb ldr r3, [r7, #12] - 800524e: 621a str r2, [r3, #32] + 800528c: 68fb ldr r3, [r7, #12] + 800528e: 6a1b ldr r3, [r3, #32] + 8005290: f023 0210 bic.w r2, r3, #16 + 8005294: 68fb ldr r3, [r7, #12] + 8005296: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; - 8005250: 68fb ldr r3, [r7, #12] - 8005252: 699b ldr r3, [r3, #24] - 8005254: 613b str r3, [r7, #16] + 8005298: 68fb ldr r3, [r7, #12] + 800529a: 699b ldr r3, [r3, #24] + 800529c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - 8005256: 693b ldr r3, [r7, #16] - 8005258: f423 4370 bic.w r3, r3, #61440 @ 0xf000 - 800525c: 613b str r3, [r7, #16] + 800529e: 693b ldr r3, [r7, #16] + 80052a0: f423 4370 bic.w r3, r3, #61440 @ 0xf000 + 80052a4: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); - 800525e: 687b ldr r3, [r7, #4] - 8005260: 031b lsls r3, r3, #12 - 8005262: 693a ldr r2, [r7, #16] - 8005264: 4313 orrs r3, r2 - 8005266: 613b str r3, [r7, #16] + 80052a6: 687b ldr r3, [r7, #4] + 80052a8: 031b lsls r3, r3, #12 + 80052aa: 693a ldr r2, [r7, #16] + 80052ac: 4313 orrs r3, r2 + 80052ae: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - 8005268: 697b ldr r3, [r7, #20] - 800526a: f023 03a0 bic.w r3, r3, #160 @ 0xa0 - 800526e: 617b str r3, [r7, #20] + 80052b0: 697b ldr r3, [r7, #20] + 80052b2: f023 03a0 bic.w r3, r3, #160 @ 0xa0 + 80052b6: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); - 8005270: 68bb ldr r3, [r7, #8] - 8005272: 011b lsls r3, r3, #4 - 8005274: 697a ldr r2, [r7, #20] - 8005276: 4313 orrs r3, r2 - 8005278: 617b str r3, [r7, #20] + 80052b8: 68bb ldr r3, [r7, #8] + 80052ba: 011b lsls r3, r3, #4 + 80052bc: 697a ldr r2, [r7, #20] + 80052be: 4313 orrs r3, r2 + 80052c0: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; - 800527a: 68fb ldr r3, [r7, #12] - 800527c: 693a ldr r2, [r7, #16] - 800527e: 619a str r2, [r3, #24] + 80052c2: 68fb ldr r3, [r7, #12] + 80052c4: 693a ldr r2, [r7, #16] + 80052c6: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; - 8005280: 68fb ldr r3, [r7, #12] - 8005282: 697a ldr r2, [r7, #20] - 8005284: 621a str r2, [r3, #32] + 80052c8: 68fb ldr r3, [r7, #12] + 80052ca: 697a ldr r2, [r7, #20] + 80052cc: 621a str r2, [r3, #32] } - 8005286: bf00 nop - 8005288: 371c adds r7, #28 - 800528a: 46bd mov sp, r7 - 800528c: f85d 7b04 ldr.w r7, [sp], #4 - 8005290: 4770 bx lr + 80052ce: bf00 nop + 80052d0: 371c adds r7, #28 + 80052d2: 46bd mov sp, r7 + 80052d4: f85d 7b04 ldr.w r7, [sp], #4 + 80052d8: 4770 bx lr -08005292 : +080052da : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { - 8005292: b480 push {r7} - 8005294: b085 sub sp, #20 - 8005296: af00 add r7, sp, #0 - 8005298: 6078 str r0, [r7, #4] - 800529a: 6039 str r1, [r7, #0] + 80052da: b480 push {r7} + 80052dc: b085 sub sp, #20 + 80052de: af00 add r7, sp, #0 + 80052e0: 6078 str r0, [r7, #4] + 80052e2: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; - 800529c: 687b ldr r3, [r7, #4] - 800529e: 689b ldr r3, [r3, #8] - 80052a0: 60fb str r3, [r7, #12] + 80052e4: 687b ldr r3, [r7, #4] + 80052e6: 689b ldr r3, [r3, #8] + 80052e8: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; - 80052a2: 68fb ldr r3, [r7, #12] - 80052a4: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 - 80052a8: f023 0370 bic.w r3, r3, #112 @ 0x70 - 80052ac: 60fb str r3, [r7, #12] + 80052ea: 68fb ldr r3, [r7, #12] + 80052ec: f423 1340 bic.w r3, r3, #3145728 @ 0x300000 + 80052f0: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80052f4: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - 80052ae: 683a ldr r2, [r7, #0] - 80052b0: 68fb ldr r3, [r7, #12] - 80052b2: 4313 orrs r3, r2 - 80052b4: f043 0307 orr.w r3, r3, #7 - 80052b8: 60fb str r3, [r7, #12] + 80052f6: 683a ldr r2, [r7, #0] + 80052f8: 68fb ldr r3, [r7, #12] + 80052fa: 4313 orrs r3, r2 + 80052fc: f043 0307 orr.w r3, r3, #7 + 8005300: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 80052ba: 687b ldr r3, [r7, #4] - 80052bc: 68fa ldr r2, [r7, #12] - 80052be: 609a str r2, [r3, #8] + 8005302: 687b ldr r3, [r7, #4] + 8005304: 68fa ldr r2, [r7, #12] + 8005306: 609a str r2, [r3, #8] } - 80052c0: bf00 nop - 80052c2: 3714 adds r7, #20 - 80052c4: 46bd mov sp, r7 - 80052c6: f85d 7b04 ldr.w r7, [sp], #4 - 80052ca: 4770 bx lr + 8005308: bf00 nop + 800530a: 3714 adds r7, #20 + 800530c: 46bd mov sp, r7 + 800530e: f85d 7b04 ldr.w r7, [sp], #4 + 8005312: 4770 bx lr -080052cc : +08005314 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - 80052cc: b480 push {r7} - 80052ce: b087 sub sp, #28 - 80052d0: af00 add r7, sp, #0 - 80052d2: 60f8 str r0, [r7, #12] - 80052d4: 60b9 str r1, [r7, #8] - 80052d6: 607a str r2, [r7, #4] - 80052d8: 603b str r3, [r7, #0] + 8005314: b480 push {r7} + 8005316: b087 sub sp, #28 + 8005318: af00 add r7, sp, #0 + 800531a: 60f8 str r0, [r7, #12] + 800531c: 60b9 str r1, [r7, #8] + 800531e: 607a str r2, [r7, #4] + 8005320: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; - 80052da: 68fb ldr r3, [r7, #12] - 80052dc: 689b ldr r3, [r3, #8] - 80052de: 617b str r3, [r7, #20] + 8005322: 68fb ldr r3, [r7, #12] + 8005324: 689b ldr r3, [r3, #8] + 8005326: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - 80052e0: 697b ldr r3, [r7, #20] - 80052e2: f423 437f bic.w r3, r3, #65280 @ 0xff00 - 80052e6: 617b str r3, [r7, #20] + 8005328: 697b ldr r3, [r7, #20] + 800532a: f423 437f bic.w r3, r3, #65280 @ 0xff00 + 800532e: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - 80052e8: 683b ldr r3, [r7, #0] - 80052ea: 021a lsls r2, r3, #8 - 80052ec: 687b ldr r3, [r7, #4] - 80052ee: 431a orrs r2, r3 - 80052f0: 68bb ldr r3, [r7, #8] - 80052f2: 4313 orrs r3, r2 - 80052f4: 697a ldr r2, [r7, #20] - 80052f6: 4313 orrs r3, r2 - 80052f8: 617b str r3, [r7, #20] + 8005330: 683b ldr r3, [r7, #0] + 8005332: 021a lsls r2, r3, #8 + 8005334: 687b ldr r3, [r7, #4] + 8005336: 431a orrs r2, r3 + 8005338: 68bb ldr r3, [r7, #8] + 800533a: 4313 orrs r3, r2 + 800533c: 697a ldr r2, [r7, #20] + 800533e: 4313 orrs r3, r2 + 8005340: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; - 80052fa: 68fb ldr r3, [r7, #12] - 80052fc: 697a ldr r2, [r7, #20] - 80052fe: 609a str r2, [r3, #8] + 8005342: 68fb ldr r3, [r7, #12] + 8005344: 697a ldr r2, [r7, #20] + 8005346: 609a str r2, [r3, #8] } - 8005300: bf00 nop - 8005302: 371c adds r7, #28 - 8005304: 46bd mov sp, r7 - 8005306: f85d 7b04 ldr.w r7, [sp], #4 - 800530a: 4770 bx lr + 8005348: bf00 nop + 800534a: 371c adds r7, #28 + 800534c: 46bd mov sp, r7 + 800534e: f85d 7b04 ldr.w r7, [sp], #4 + 8005352: 4770 bx lr -0800530c : +08005354 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { - 800530c: b480 push {r7} - 800530e: b085 sub sp, #20 - 8005310: af00 add r7, sp, #0 - 8005312: 6078 str r0, [r7, #4] - 8005314: 6039 str r1, [r7, #0] + 8005354: b480 push {r7} + 8005356: b085 sub sp, #20 + 8005358: af00 add r7, sp, #0 + 800535a: 6078 str r0, [r7, #4] + 800535c: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); - 8005316: 687b ldr r3, [r7, #4] - 8005318: f893 303c ldrb.w r3, [r3, #60] @ 0x3c - 800531c: 2b01 cmp r3, #1 - 800531e: d101 bne.n 8005324 - 8005320: 2302 movs r3, #2 - 8005322: e065 b.n 80053f0 - 8005324: 687b ldr r3, [r7, #4] - 8005326: 2201 movs r2, #1 - 8005328: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800535e: 687b ldr r3, [r7, #4] + 8005360: f893 303c ldrb.w r3, [r3, #60] @ 0x3c + 8005364: 2b01 cmp r3, #1 + 8005366: d101 bne.n 800536c + 8005368: 2302 movs r3, #2 + 800536a: e065 b.n 8005438 + 800536c: 687b ldr r3, [r7, #4] + 800536e: 2201 movs r2, #1 + 8005370: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; - 800532c: 687b ldr r3, [r7, #4] - 800532e: 2202 movs r2, #2 - 8005330: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005374: 687b ldr r3, [r7, #4] + 8005376: 2202 movs r2, #2 + 8005378: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; - 8005334: 687b ldr r3, [r7, #4] - 8005336: 681b ldr r3, [r3, #0] - 8005338: 685b ldr r3, [r3, #4] - 800533a: 60fb str r3, [r7, #12] + 800537c: 687b ldr r3, [r7, #4] + 800537e: 681b ldr r3, [r3, #0] + 8005380: 685b ldr r3, [r3, #4] + 8005382: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; - 800533c: 687b ldr r3, [r7, #4] - 800533e: 681b ldr r3, [r3, #0] - 8005340: 689b ldr r3, [r3, #8] - 8005342: 60bb str r3, [r7, #8] + 8005384: 687b ldr r3, [r7, #4] + 8005386: 681b ldr r3, [r3, #0] + 8005388: 689b ldr r3, [r3, #8] + 800538a: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - 8005344: 687b ldr r3, [r7, #4] - 8005346: 681b ldr r3, [r3, #0] - 8005348: 4a2c ldr r2, [pc, #176] @ (80053fc ) - 800534a: 4293 cmp r3, r2 - 800534c: d004 beq.n 8005358 - 800534e: 687b ldr r3, [r7, #4] - 8005350: 681b ldr r3, [r3, #0] - 8005352: 4a2b ldr r2, [pc, #172] @ (8005400 ) - 8005354: 4293 cmp r3, r2 - 8005356: d108 bne.n 800536a + 800538c: 687b ldr r3, [r7, #4] + 800538e: 681b ldr r3, [r3, #0] + 8005390: 4a2c ldr r2, [pc, #176] @ (8005444 ) + 8005392: 4293 cmp r3, r2 + 8005394: d004 beq.n 80053a0 + 8005396: 687b ldr r3, [r7, #4] + 8005398: 681b ldr r3, [r3, #0] + 800539a: 4a2b ldr r2, [pc, #172] @ (8005448 ) + 800539c: 4293 cmp r3, r2 + 800539e: d108 bne.n 80053b2 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; - 8005358: 68fb ldr r3, [r7, #12] - 800535a: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 - 800535e: 60fb str r3, [r7, #12] + 80053a0: 68fb ldr r3, [r7, #12] + 80053a2: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 + 80053a6: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - 8005360: 683b ldr r3, [r7, #0] - 8005362: 685b ldr r3, [r3, #4] - 8005364: 68fa ldr r2, [r7, #12] - 8005366: 4313 orrs r3, r2 - 8005368: 60fb str r3, [r7, #12] + 80053a8: 683b ldr r3, [r7, #0] + 80053aa: 685b ldr r3, [r3, #4] + 80053ac: 68fa ldr r2, [r7, #12] + 80053ae: 4313 orrs r3, r2 + 80053b0: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; - 800536a: 68fb ldr r3, [r7, #12] - 800536c: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000 - 8005370: f023 0370 bic.w r3, r3, #112 @ 0x70 - 8005374: 60fb str r3, [r7, #12] + 80053b2: 68fb ldr r3, [r7, #12] + 80053b4: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000 + 80053b8: f023 0370 bic.w r3, r3, #112 @ 0x70 + 80053bc: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - 8005376: 683b ldr r3, [r7, #0] - 8005378: 681b ldr r3, [r3, #0] - 800537a: 68fa ldr r2, [r7, #12] - 800537c: 4313 orrs r3, r2 - 800537e: 60fb str r3, [r7, #12] + 80053be: 683b ldr r3, [r7, #0] + 80053c0: 681b ldr r3, [r3, #0] + 80053c2: 68fa ldr r2, [r7, #12] + 80053c4: 4313 orrs r3, r2 + 80053c6: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - 8005380: 687b ldr r3, [r7, #4] - 8005382: 681b ldr r3, [r3, #0] - 8005384: 68fa ldr r2, [r7, #12] - 8005386: 605a str r2, [r3, #4] + 80053c8: 687b ldr r3, [r7, #4] + 80053ca: 681b ldr r3, [r3, #0] + 80053cc: 68fa ldr r2, [r7, #12] + 80053ce: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 8005388: 687b ldr r3, [r7, #4] - 800538a: 681b ldr r3, [r3, #0] - 800538c: 4a1b ldr r2, [pc, #108] @ (80053fc ) - 800538e: 4293 cmp r3, r2 - 8005390: d018 beq.n 80053c4 - 8005392: 687b ldr r3, [r7, #4] - 8005394: 681b ldr r3, [r3, #0] - 8005396: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 - 800539a: d013 beq.n 80053c4 - 800539c: 687b ldr r3, [r7, #4] - 800539e: 681b ldr r3, [r3, #0] - 80053a0: 4a18 ldr r2, [pc, #96] @ (8005404 ) - 80053a2: 4293 cmp r3, r2 - 80053a4: d00e beq.n 80053c4 - 80053a6: 687b ldr r3, [r7, #4] - 80053a8: 681b ldr r3, [r3, #0] - 80053aa: 4a17 ldr r2, [pc, #92] @ (8005408 ) - 80053ac: 4293 cmp r3, r2 - 80053ae: d009 beq.n 80053c4 - 80053b0: 687b ldr r3, [r7, #4] - 80053b2: 681b ldr r3, [r3, #0] - 80053b4: 4a12 ldr r2, [pc, #72] @ (8005400 ) - 80053b6: 4293 cmp r3, r2 - 80053b8: d004 beq.n 80053c4 - 80053ba: 687b ldr r3, [r7, #4] - 80053bc: 681b ldr r3, [r3, #0] - 80053be: 4a13 ldr r2, [pc, #76] @ (800540c ) - 80053c0: 4293 cmp r3, r2 - 80053c2: d10c bne.n 80053de + 80053d0: 687b ldr r3, [r7, #4] + 80053d2: 681b ldr r3, [r3, #0] + 80053d4: 4a1b ldr r2, [pc, #108] @ (8005444 ) + 80053d6: 4293 cmp r3, r2 + 80053d8: d018 beq.n 800540c + 80053da: 687b ldr r3, [r7, #4] + 80053dc: 681b ldr r3, [r3, #0] + 80053de: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 + 80053e2: d013 beq.n 800540c + 80053e4: 687b ldr r3, [r7, #4] + 80053e6: 681b ldr r3, [r3, #0] + 80053e8: 4a18 ldr r2, [pc, #96] @ (800544c ) + 80053ea: 4293 cmp r3, r2 + 80053ec: d00e beq.n 800540c + 80053ee: 687b ldr r3, [r7, #4] + 80053f0: 681b ldr r3, [r3, #0] + 80053f2: 4a17 ldr r2, [pc, #92] @ (8005450 ) + 80053f4: 4293 cmp r3, r2 + 80053f6: d009 beq.n 800540c + 80053f8: 687b ldr r3, [r7, #4] + 80053fa: 681b ldr r3, [r3, #0] + 80053fc: 4a12 ldr r2, [pc, #72] @ (8005448 ) + 80053fe: 4293 cmp r3, r2 + 8005400: d004 beq.n 800540c + 8005402: 687b ldr r3, [r7, #4] + 8005404: 681b ldr r3, [r3, #0] + 8005406: 4a13 ldr r2, [pc, #76] @ (8005454 ) + 8005408: 4293 cmp r3, r2 + 800540a: d10c bne.n 8005426 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; - 80053c4: 68bb ldr r3, [r7, #8] - 80053c6: f023 0380 bic.w r3, r3, #128 @ 0x80 - 80053ca: 60bb str r3, [r7, #8] + 800540c: 68bb ldr r3, [r7, #8] + 800540e: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8005412: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; - 80053cc: 683b ldr r3, [r7, #0] - 80053ce: 689b ldr r3, [r3, #8] - 80053d0: 68ba ldr r2, [r7, #8] - 80053d2: 4313 orrs r3, r2 - 80053d4: 60bb str r3, [r7, #8] + 8005414: 683b ldr r3, [r7, #0] + 8005416: 689b ldr r3, [r3, #8] + 8005418: 68ba ldr r2, [r7, #8] + 800541a: 4313 orrs r3, r2 + 800541c: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; - 80053d6: 687b ldr r3, [r7, #4] - 80053d8: 681b ldr r3, [r3, #0] - 80053da: 68ba ldr r2, [r7, #8] - 80053dc: 609a str r2, [r3, #8] + 800541e: 687b ldr r3, [r7, #4] + 8005420: 681b ldr r3, [r3, #0] + 8005422: 68ba ldr r2, [r7, #8] + 8005424: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - 80053de: 687b ldr r3, [r7, #4] - 80053e0: 2201 movs r2, #1 - 80053e2: f883 203d strb.w r2, [r3, #61] @ 0x3d + 8005426: 687b ldr r3, [r7, #4] + 8005428: 2201 movs r2, #1 + 800542a: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); - 80053e6: 687b ldr r3, [r7, #4] - 80053e8: 2200 movs r2, #0 - 80053ea: f883 203c strb.w r2, [r3, #60] @ 0x3c + 800542e: 687b ldr r3, [r7, #4] + 8005430: 2200 movs r2, #0 + 8005432: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; - 80053ee: 2300 movs r3, #0 + 8005436: 2300 movs r3, #0 } - 80053f0: 4618 mov r0, r3 - 80053f2: 3714 adds r7, #20 - 80053f4: 46bd mov sp, r7 - 80053f6: f85d 7b04 ldr.w r7, [sp], #4 - 80053fa: 4770 bx lr - 80053fc: 40012c00 .word 0x40012c00 - 8005400: 40013400 .word 0x40013400 - 8005404: 40000400 .word 0x40000400 - 8005408: 40000800 .word 0x40000800 - 800540c: 40014000 .word 0x40014000 + 8005438: 4618 mov r0, r3 + 800543a: 3714 adds r7, #20 + 800543c: 46bd mov sp, r7 + 800543e: f85d 7b04 ldr.w r7, [sp], #4 + 8005442: 4770 bx lr + 8005444: 40012c00 .word 0x40012c00 + 8005448: 40013400 .word 0x40013400 + 800544c: 40000400 .word 0x40000400 + 8005450: 40000800 .word 0x40000800 + 8005454: 40014000 .word 0x40014000 -08005410 : +08005458 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 8005410: b480 push {r7} - 8005412: b083 sub sp, #12 - 8005414: af00 add r7, sp, #0 - 8005416: 6078 str r0, [r7, #4] + 8005458: b480 push {r7} + 800545a: b083 sub sp, #12 + 800545c: af00 add r7, sp, #0 + 800545e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 8005418: bf00 nop - 800541a: 370c adds r7, #12 - 800541c: 46bd mov sp, r7 - 800541e: f85d 7b04 ldr.w r7, [sp], #4 - 8005422: 4770 bx lr + 8005460: bf00 nop + 8005462: 370c adds r7, #12 + 8005464: 46bd mov sp, r7 + 8005466: f85d 7b04 ldr.w r7, [sp], #4 + 800546a: 4770 bx lr -08005424 : +0800546c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 8005424: b480 push {r7} - 8005426: b083 sub sp, #12 - 8005428: af00 add r7, sp, #0 - 800542a: 6078 str r0, [r7, #4] + 800546c: b480 push {r7} + 800546e: b083 sub sp, #12 + 8005470: af00 add r7, sp, #0 + 8005472: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 800542c: bf00 nop - 800542e: 370c adds r7, #12 - 8005430: 46bd mov sp, r7 - 8005432: f85d 7b04 ldr.w r7, [sp], #4 - 8005436: 4770 bx lr + 8005474: bf00 nop + 8005476: 370c adds r7, #12 + 8005478: 46bd mov sp, r7 + 800547a: f85d 7b04 ldr.w r7, [sp], #4 + 800547e: 4770 bx lr -08005438 : +08005480 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { - 8005438: b480 push {r7} - 800543a: b083 sub sp, #12 - 800543c: af00 add r7, sp, #0 - 800543e: 6078 str r0, [r7, #4] + 8005480: b480 push {r7} + 8005482: b083 sub sp, #12 + 8005484: af00 add r7, sp, #0 + 8005486: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } - 8005440: bf00 nop - 8005442: 370c adds r7, #12 - 8005444: 46bd mov sp, r7 - 8005446: f85d 7b04 ldr.w r7, [sp], #4 - 800544a: 4770 bx lr + 8005488: bf00 nop + 800548a: 370c adds r7, #12 + 800548c: 46bd mov sp, r7 + 800548e: f85d 7b04 ldr.w r7, [sp], #4 + 8005492: 4770 bx lr -0800544c : +08005494 : * @brief Encoder index callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) { - 800544c: b480 push {r7} - 800544e: b083 sub sp, #12 - 8005450: af00 add r7, sp, #0 - 8005452: 6078 str r0, [r7, #4] + 8005494: b480 push {r7} + 8005496: b083 sub sp, #12 + 8005498: af00 add r7, sp, #0 + 800549a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file */ } - 8005454: bf00 nop - 8005456: 370c adds r7, #12 - 8005458: 46bd mov sp, r7 - 800545a: f85d 7b04 ldr.w r7, [sp], #4 - 800545e: 4770 bx lr + 800549c: bf00 nop + 800549e: 370c adds r7, #12 + 80054a0: 46bd mov sp, r7 + 80054a2: f85d 7b04 ldr.w r7, [sp], #4 + 80054a6: 4770 bx lr -08005460 : +080054a8 : * @brief Direction change callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) { - 8005460: b480 push {r7} - 8005462: b083 sub sp, #12 - 8005464: af00 add r7, sp, #0 - 8005466: 6078 str r0, [r7, #4] + 80054a8: b480 push {r7} + 80054aa: b083 sub sp, #12 + 80054ac: af00 add r7, sp, #0 + 80054ae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file */ } - 8005468: bf00 nop - 800546a: 370c adds r7, #12 - 800546c: 46bd mov sp, r7 - 800546e: f85d 7b04 ldr.w r7, [sp], #4 - 8005472: 4770 bx lr + 80054b0: bf00 nop + 80054b2: 370c adds r7, #12 + 80054b4: 46bd mov sp, r7 + 80054b6: f85d 7b04 ldr.w r7, [sp], #4 + 80054ba: 4770 bx lr -08005474 : +080054bc : * @brief Index error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) { - 8005474: b480 push {r7} - 8005476: b083 sub sp, #12 - 8005478: af00 add r7, sp, #0 - 800547a: 6078 str r0, [r7, #4] + 80054bc: b480 push {r7} + 80054be: b083 sub sp, #12 + 80054c0: af00 add r7, sp, #0 + 80054c2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_IndexErrorCallback could be implemented in the user file */ } - 800547c: bf00 nop - 800547e: 370c adds r7, #12 - 8005480: 46bd mov sp, r7 - 8005482: f85d 7b04 ldr.w r7, [sp], #4 - 8005486: 4770 bx lr + 80054c4: bf00 nop + 80054c6: 370c adds r7, #12 + 80054c8: 46bd mov sp, r7 + 80054ca: f85d 7b04 ldr.w r7, [sp], #4 + 80054ce: 4770 bx lr -08005488 : +080054d0 : * @brief Transition error callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) { - 8005488: b480 push {r7} - 800548a: b083 sub sp, #12 - 800548c: af00 add r7, sp, #0 - 800548e: 6078 str r0, [r7, #4] + 80054d0: b480 push {r7} + 80054d2: b083 sub sp, #12 + 80054d4: af00 add r7, sp, #0 + 80054d6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file */ } - 8005490: bf00 nop - 8005492: 370c adds r7, #12 - 8005494: 46bd mov sp, r7 - 8005496: f85d 7b04 ldr.w r7, [sp], #4 - 800549a: 4770 bx lr + 80054d8: bf00 nop + 80054da: 370c adds r7, #12 + 80054dc: 46bd mov sp, r7 + 80054de: f85d 7b04 ldr.w r7, [sp], #4 + 80054e2: 4770 bx lr -0800549c : +080054e4 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 800549c: b580 push {r7, lr} - 800549e: b082 sub sp, #8 - 80054a0: af00 add r7, sp, #0 - 80054a2: 6078 str r0, [r7, #4] + 80054e4: b580 push {r7, lr} + 80054e6: b082 sub sp, #8 + 80054e8: af00 add r7, sp, #0 + 80054ea: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 80054a4: 687b ldr r3, [r7, #4] - 80054a6: 2b00 cmp r3, #0 - 80054a8: d101 bne.n 80054ae + 80054ec: 687b ldr r3, [r7, #4] + 80054ee: 2b00 cmp r3, #0 + 80054f0: d101 bne.n 80054f6 { return HAL_ERROR; - 80054aa: 2301 movs r3, #1 - 80054ac: e042 b.n 8005534 + 80054f2: 2301 movs r3, #1 + 80054f4: e042 b.n 800557c { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) - 80054ae: 687b ldr r3, [r7, #4] - 80054b0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 80054b4: 2b00 cmp r3, #0 - 80054b6: d106 bne.n 80054c6 + 80054f6: 687b ldr r3, [r7, #4] + 80054f8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 80054fc: 2b00 cmp r3, #0 + 80054fe: d106 bne.n 800550e { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 80054b8: 687b ldr r3, [r7, #4] - 80054ba: 2200 movs r2, #0 - 80054bc: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 8005500: 687b ldr r3, [r7, #4] + 8005502: 2200 movs r2, #0 + 8005504: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 80054c0: 6878 ldr r0, [r7, #4] - 80054c2: f7fc f9cf bl 8001864 + 8005508: 6878 ldr r0, [r7, #4] + 800550a: f7fc f9cf bl 80018ac #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 80054c6: 687b ldr r3, [r7, #4] - 80054c8: 2224 movs r2, #36 @ 0x24 - 80054ca: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800550e: 687b ldr r3, [r7, #4] + 8005510: 2224 movs r2, #36 @ 0x24 + 8005512: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); - 80054ce: 687b ldr r3, [r7, #4] - 80054d0: 681b ldr r3, [r3, #0] - 80054d2: 681a ldr r2, [r3, #0] - 80054d4: 687b ldr r3, [r7, #4] - 80054d6: 681b ldr r3, [r3, #0] - 80054d8: f022 0201 bic.w r2, r2, #1 - 80054dc: 601a str r2, [r3, #0] + 8005516: 687b ldr r3, [r7, #4] + 8005518: 681b ldr r3, [r3, #0] + 800551a: 681a ldr r2, [r3, #0] + 800551c: 687b ldr r3, [r7, #4] + 800551e: 681b ldr r3, [r3, #0] + 8005520: f022 0201 bic.w r2, r2, #1 + 8005524: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 80054de: 687b ldr r3, [r7, #4] - 80054e0: 6a9b ldr r3, [r3, #40] @ 0x28 - 80054e2: 2b00 cmp r3, #0 - 80054e4: d002 beq.n 80054ec + 8005526: 687b ldr r3, [r7, #4] + 8005528: 6a9b ldr r3, [r3, #40] @ 0x28 + 800552a: 2b00 cmp r3, #0 + 800552c: d002 beq.n 8005534 { UART_AdvFeatureConfig(huart); - 80054e6: 6878 ldr r0, [r7, #4] - 80054e8: f000 ff26 bl 8006338 + 800552e: 6878 ldr r0, [r7, #4] + 8005530: f000 ff26 bl 8006380 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 80054ec: 6878 ldr r0, [r7, #4] - 80054ee: f000 fc57 bl 8005da0 - 80054f2: 4603 mov r3, r0 - 80054f4: 2b01 cmp r3, #1 - 80054f6: d101 bne.n 80054fc + 8005534: 6878 ldr r0, [r7, #4] + 8005536: f000 fc57 bl 8005de8 + 800553a: 4603 mov r3, r0 + 800553c: 2b01 cmp r3, #1 + 800553e: d101 bne.n 8005544 { return HAL_ERROR; - 80054f8: 2301 movs r3, #1 - 80054fa: e01b b.n 8005534 + 8005540: 2301 movs r3, #1 + 8005542: e01b b.n 800557c } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 80054fc: 687b ldr r3, [r7, #4] - 80054fe: 681b ldr r3, [r3, #0] - 8005500: 685a ldr r2, [r3, #4] - 8005502: 687b ldr r3, [r7, #4] - 8005504: 681b ldr r3, [r3, #0] - 8005506: f422 4290 bic.w r2, r2, #18432 @ 0x4800 - 800550a: 605a str r2, [r3, #4] + 8005544: 687b ldr r3, [r7, #4] + 8005546: 681b ldr r3, [r3, #0] + 8005548: 685a ldr r2, [r3, #4] + 800554a: 687b ldr r3, [r7, #4] + 800554c: 681b ldr r3, [r3, #0] + 800554e: f422 4290 bic.w r2, r2, #18432 @ 0x4800 + 8005552: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 800550c: 687b ldr r3, [r7, #4] - 800550e: 681b ldr r3, [r3, #0] - 8005510: 689a ldr r2, [r3, #8] - 8005512: 687b ldr r3, [r7, #4] - 8005514: 681b ldr r3, [r3, #0] - 8005516: f022 022a bic.w r2, r2, #42 @ 0x2a - 800551a: 609a str r2, [r3, #8] + 8005554: 687b ldr r3, [r7, #4] + 8005556: 681b ldr r3, [r3, #0] + 8005558: 689a ldr r2, [r3, #8] + 800555a: 687b ldr r3, [r7, #4] + 800555c: 681b ldr r3, [r3, #0] + 800555e: f022 022a bic.w r2, r2, #42 @ 0x2a + 8005562: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 800551c: 687b ldr r3, [r7, #4] - 800551e: 681b ldr r3, [r3, #0] - 8005520: 681a ldr r2, [r3, #0] - 8005522: 687b ldr r3, [r7, #4] - 8005524: 681b ldr r3, [r3, #0] - 8005526: f042 0201 orr.w r2, r2, #1 - 800552a: 601a str r2, [r3, #0] + 8005564: 687b ldr r3, [r7, #4] + 8005566: 681b ldr r3, [r3, #0] + 8005568: 681a ldr r2, [r3, #0] + 800556a: 687b ldr r3, [r7, #4] + 800556c: 681b ldr r3, [r3, #0] + 800556e: f042 0201 orr.w r2, r2, #1 + 8005572: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 800552c: 6878 ldr r0, [r7, #4] - 800552e: f000 ffa5 bl 800647c - 8005532: 4603 mov r3, r0 + 8005574: 6878 ldr r0, [r7, #4] + 8005576: f000 ffa5 bl 80064c4 + 800557a: 4603 mov r3, r0 } - 8005534: 4618 mov r0, r3 - 8005536: 3708 adds r7, #8 - 8005538: 46bd mov sp, r7 - 800553a: bd80 pop {r7, pc} + 800557c: 4618 mov r0, r3 + 800557e: 3708 adds r7, #8 + 8005580: 46bd mov sp, r7 + 8005582: bd80 pop {r7, pc} -0800553c : +08005584 : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 800553c: b580 push {r7, lr} - 800553e: b08a sub sp, #40 @ 0x28 - 8005540: af02 add r7, sp, #8 - 8005542: 60f8 str r0, [r7, #12] - 8005544: 60b9 str r1, [r7, #8] - 8005546: 603b str r3, [r7, #0] - 8005548: 4613 mov r3, r2 - 800554a: 80fb strh r3, [r7, #6] + 8005584: b580 push {r7, lr} + 8005586: b08a sub sp, #40 @ 0x28 + 8005588: af02 add r7, sp, #8 + 800558a: 60f8 str r0, [r7, #12] + 800558c: 60b9 str r1, [r7, #8] + 800558e: 603b str r3, [r7, #0] + 8005590: 4613 mov r3, r2 + 8005592: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) - 800554c: 68fb ldr r3, [r7, #12] - 800554e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8005552: 2b20 cmp r3, #32 - 8005554: d17b bne.n 800564e + 8005594: 68fb ldr r3, [r7, #12] + 8005596: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 800559a: 2b20 cmp r3, #32 + 800559c: d17b bne.n 8005696 { if ((pData == NULL) || (Size == 0U)) - 8005556: 68bb ldr r3, [r7, #8] - 8005558: 2b00 cmp r3, #0 - 800555a: d002 beq.n 8005562 - 800555c: 88fb ldrh r3, [r7, #6] - 800555e: 2b00 cmp r3, #0 - 8005560: d101 bne.n 8005566 + 800559e: 68bb ldr r3, [r7, #8] + 80055a0: 2b00 cmp r3, #0 + 80055a2: d002 beq.n 80055aa + 80055a4: 88fb ldrh r3, [r7, #6] + 80055a6: 2b00 cmp r3, #0 + 80055a8: d101 bne.n 80055ae { return HAL_ERROR; - 8005562: 2301 movs r3, #1 - 8005564: e074 b.n 8005650 + 80055aa: 2301 movs r3, #1 + 80055ac: e074 b.n 8005698 } huart->ErrorCode = HAL_UART_ERROR_NONE; - 8005566: 68fb ldr r3, [r7, #12] - 8005568: 2200 movs r2, #0 - 800556a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 80055ae: 68fb ldr r3, [r7, #12] + 80055b0: 2200 movs r2, #0 + 80055b2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; - 800556e: 68fb ldr r3, [r7, #12] - 8005570: 2221 movs r2, #33 @ 0x21 - 8005572: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 80055b6: 68fb ldr r3, [r7, #12] + 80055b8: 2221 movs r2, #33 @ 0x21 + 80055ba: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8005576: f7fc fab9 bl 8001aec - 800557a: 6178 str r0, [r7, #20] + 80055be: f7fc fab9 bl 8001b34 + 80055c2: 6178 str r0, [r7, #20] huart->TxXferSize = Size; - 800557c: 68fb ldr r3, [r7, #12] - 800557e: 88fa ldrh r2, [r7, #6] - 8005580: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 + 80055c4: 68fb ldr r3, [r7, #12] + 80055c6: 88fa ldrh r2, [r7, #6] + 80055c8: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; - 8005584: 68fb ldr r3, [r7, #12] - 8005586: 88fa ldrh r2, [r7, #6] - 8005588: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 + 80055cc: 68fb ldr r3, [r7, #12] + 80055ce: 88fa ldrh r2, [r7, #6] + 80055d0: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 800558c: 68fb ldr r3, [r7, #12] - 800558e: 689b ldr r3, [r3, #8] - 8005590: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 8005594: d108 bne.n 80055a8 - 8005596: 68fb ldr r3, [r7, #12] - 8005598: 691b ldr r3, [r3, #16] - 800559a: 2b00 cmp r3, #0 - 800559c: d104 bne.n 80055a8 + 80055d4: 68fb ldr r3, [r7, #12] + 80055d6: 689b ldr r3, [r3, #8] + 80055d8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80055dc: d108 bne.n 80055f0 + 80055de: 68fb ldr r3, [r7, #12] + 80055e0: 691b ldr r3, [r3, #16] + 80055e2: 2b00 cmp r3, #0 + 80055e4: d104 bne.n 80055f0 { pdata8bits = NULL; - 800559e: 2300 movs r3, #0 - 80055a0: 61fb str r3, [r7, #28] + 80055e6: 2300 movs r3, #0 + 80055e8: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; - 80055a2: 68bb ldr r3, [r7, #8] - 80055a4: 61bb str r3, [r7, #24] - 80055a6: e003 b.n 80055b0 + 80055ea: 68bb ldr r3, [r7, #8] + 80055ec: 61bb str r3, [r7, #24] + 80055ee: e003 b.n 80055f8 } else { pdata8bits = pData; - 80055a8: 68bb ldr r3, [r7, #8] - 80055aa: 61fb str r3, [r7, #28] + 80055f0: 68bb ldr r3, [r7, #8] + 80055f2: 61fb str r3, [r7, #28] pdata16bits = NULL; - 80055ac: 2300 movs r3, #0 - 80055ae: 61bb str r3, [r7, #24] + 80055f4: 2300 movs r3, #0 + 80055f6: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) - 80055b0: e030 b.n 8005614 + 80055f8: e030 b.n 800565c { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - 80055b2: 683b ldr r3, [r7, #0] - 80055b4: 9300 str r3, [sp, #0] - 80055b6: 697b ldr r3, [r7, #20] - 80055b8: 2200 movs r2, #0 - 80055ba: 2180 movs r1, #128 @ 0x80 - 80055bc: 68f8 ldr r0, [r7, #12] - 80055be: f001 f807 bl 80065d0 - 80055c2: 4603 mov r3, r0 - 80055c4: 2b00 cmp r3, #0 - 80055c6: d005 beq.n 80055d4 + 80055fa: 683b ldr r3, [r7, #0] + 80055fc: 9300 str r3, [sp, #0] + 80055fe: 697b ldr r3, [r7, #20] + 8005600: 2200 movs r2, #0 + 8005602: 2180 movs r1, #128 @ 0x80 + 8005604: 68f8 ldr r0, [r7, #12] + 8005606: f001 f807 bl 8006618 + 800560a: 4603 mov r3, r0 + 800560c: 2b00 cmp r3, #0 + 800560e: d005 beq.n 800561c { huart->gState = HAL_UART_STATE_READY; - 80055c8: 68fb ldr r3, [r7, #12] - 80055ca: 2220 movs r2, #32 - 80055cc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 8005610: 68fb ldr r3, [r7, #12] + 8005612: 2220 movs r2, #32 + 8005614: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; - 80055d0: 2303 movs r3, #3 - 80055d2: e03d b.n 8005650 + 8005618: 2303 movs r3, #3 + 800561a: e03d b.n 8005698 } if (pdata8bits == NULL) - 80055d4: 69fb ldr r3, [r7, #28] - 80055d6: 2b00 cmp r3, #0 - 80055d8: d10b bne.n 80055f2 + 800561c: 69fb ldr r3, [r7, #28] + 800561e: 2b00 cmp r3, #0 + 8005620: d10b bne.n 800563a { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - 80055da: 69bb ldr r3, [r7, #24] - 80055dc: 881b ldrh r3, [r3, #0] - 80055de: 461a mov r2, r3 - 80055e0: 68fb ldr r3, [r7, #12] - 80055e2: 681b ldr r3, [r3, #0] - 80055e4: f3c2 0208 ubfx r2, r2, #0, #9 - 80055e8: 629a str r2, [r3, #40] @ 0x28 + 8005622: 69bb ldr r3, [r7, #24] + 8005624: 881b ldrh r3, [r3, #0] + 8005626: 461a mov r2, r3 + 8005628: 68fb ldr r3, [r7, #12] + 800562a: 681b ldr r3, [r3, #0] + 800562c: f3c2 0208 ubfx r2, r2, #0, #9 + 8005630: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; - 80055ea: 69bb ldr r3, [r7, #24] - 80055ec: 3302 adds r3, #2 - 80055ee: 61bb str r3, [r7, #24] - 80055f0: e007 b.n 8005602 + 8005632: 69bb ldr r3, [r7, #24] + 8005634: 3302 adds r3, #2 + 8005636: 61bb str r3, [r7, #24] + 8005638: e007 b.n 800564a } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - 80055f2: 69fb ldr r3, [r7, #28] - 80055f4: 781a ldrb r2, [r3, #0] - 80055f6: 68fb ldr r3, [r7, #12] - 80055f8: 681b ldr r3, [r3, #0] - 80055fa: 629a str r2, [r3, #40] @ 0x28 + 800563a: 69fb ldr r3, [r7, #28] + 800563c: 781a ldrb r2, [r3, #0] + 800563e: 68fb ldr r3, [r7, #12] + 8005640: 681b ldr r3, [r3, #0] + 8005642: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; - 80055fc: 69fb ldr r3, [r7, #28] - 80055fe: 3301 adds r3, #1 - 8005600: 61fb str r3, [r7, #28] + 8005644: 69fb ldr r3, [r7, #28] + 8005646: 3301 adds r3, #1 + 8005648: 61fb str r3, [r7, #28] } huart->TxXferCount--; - 8005602: 68fb ldr r3, [r7, #12] - 8005604: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 - 8005608: b29b uxth r3, r3 - 800560a: 3b01 subs r3, #1 - 800560c: b29a uxth r2, r3 - 800560e: 68fb ldr r3, [r7, #12] - 8005610: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 + 800564a: 68fb ldr r3, [r7, #12] + 800564c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 + 8005650: b29b uxth r3, r3 + 8005652: 3b01 subs r3, #1 + 8005654: b29a uxth r2, r3 + 8005656: 68fb ldr r3, [r7, #12] + 8005658: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 while (huart->TxXferCount > 0U) - 8005614: 68fb ldr r3, [r7, #12] - 8005616: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 - 800561a: b29b uxth r3, r3 - 800561c: 2b00 cmp r3, #0 - 800561e: d1c8 bne.n 80055b2 + 800565c: 68fb ldr r3, [r7, #12] + 800565e: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 + 8005662: b29b uxth r3, r3 + 8005664: 2b00 cmp r3, #0 + 8005666: d1c8 bne.n 80055fa } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - 8005620: 683b ldr r3, [r7, #0] - 8005622: 9300 str r3, [sp, #0] - 8005624: 697b ldr r3, [r7, #20] - 8005626: 2200 movs r2, #0 - 8005628: 2140 movs r1, #64 @ 0x40 - 800562a: 68f8 ldr r0, [r7, #12] - 800562c: f000 ffd0 bl 80065d0 - 8005630: 4603 mov r3, r0 - 8005632: 2b00 cmp r3, #0 - 8005634: d005 beq.n 8005642 + 8005668: 683b ldr r3, [r7, #0] + 800566a: 9300 str r3, [sp, #0] + 800566c: 697b ldr r3, [r7, #20] + 800566e: 2200 movs r2, #0 + 8005670: 2140 movs r1, #64 @ 0x40 + 8005672: 68f8 ldr r0, [r7, #12] + 8005674: f000 ffd0 bl 8006618 + 8005678: 4603 mov r3, r0 + 800567a: 2b00 cmp r3, #0 + 800567c: d005 beq.n 800568a { huart->gState = HAL_UART_STATE_READY; - 8005636: 68fb ldr r3, [r7, #12] - 8005638: 2220 movs r2, #32 - 800563a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800567e: 68fb ldr r3, [r7, #12] + 8005680: 2220 movs r2, #32 + 8005682: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; - 800563e: 2303 movs r3, #3 - 8005640: e006 b.n 8005650 + 8005686: 2303 movs r3, #3 + 8005688: e006 b.n 8005698 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 8005642: 68fb ldr r3, [r7, #12] - 8005644: 2220 movs r2, #32 - 8005646: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800568a: 68fb ldr r3, [r7, #12] + 800568c: 2220 movs r2, #32 + 800568e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_OK; - 800564a: 2300 movs r3, #0 - 800564c: e000 b.n 8005650 + 8005692: 2300 movs r3, #0 + 8005694: e000 b.n 8005698 } else { return HAL_BUSY; - 800564e: 2302 movs r3, #2 + 8005696: 2302 movs r3, #2 } } - 8005650: 4618 mov r0, r3 - 8005652: 3720 adds r7, #32 - 8005654: 46bd mov sp, r7 - 8005656: bd80 pop {r7, pc} + 8005698: 4618 mov r0, r3 + 800569a: 3720 adds r7, #32 + 800569c: 46bd mov sp, r7 + 800569e: bd80 pop {r7, pc} -08005658 : +080056a0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - 8005658: b580 push {r7, lr} - 800565a: b08a sub sp, #40 @ 0x28 - 800565c: af00 add r7, sp, #0 - 800565e: 60f8 str r0, [r7, #12] - 8005660: 60b9 str r1, [r7, #8] - 8005662: 4613 mov r3, r2 - 8005664: 80fb strh r3, [r7, #6] + 80056a0: b580 push {r7, lr} + 80056a2: b08a sub sp, #40 @ 0x28 + 80056a4: af00 add r7, sp, #0 + 80056a6: 60f8 str r0, [r7, #12] + 80056a8: 60b9 str r1, [r7, #8] + 80056aa: 4613 mov r3, r2 + 80056ac: 80fb strh r3, [r7, #6] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) - 8005666: 68fb ldr r3, [r7, #12] - 8005668: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c - 800566c: 2b20 cmp r3, #32 - 800566e: d137 bne.n 80056e0 + 80056ae: 68fb ldr r3, [r7, #12] + 80056b0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 80056b4: 2b20 cmp r3, #32 + 80056b6: d137 bne.n 8005728 { if ((pData == NULL) || (Size == 0U)) - 8005670: 68bb ldr r3, [r7, #8] - 8005672: 2b00 cmp r3, #0 - 8005674: d002 beq.n 800567c - 8005676: 88fb ldrh r3, [r7, #6] - 8005678: 2b00 cmp r3, #0 - 800567a: d101 bne.n 8005680 + 80056b8: 68bb ldr r3, [r7, #8] + 80056ba: 2b00 cmp r3, #0 + 80056bc: d002 beq.n 80056c4 + 80056be: 88fb ldrh r3, [r7, #6] + 80056c0: 2b00 cmp r3, #0 + 80056c2: d101 bne.n 80056c8 { return HAL_ERROR; - 800567c: 2301 movs r3, #1 - 800567e: e030 b.n 80056e2 + 80056c4: 2301 movs r3, #1 + 80056c6: e030 b.n 800572a } /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8005680: 68fb ldr r3, [r7, #12] - 8005682: 2200 movs r2, #0 - 8005684: 66da str r2, [r3, #108] @ 0x6c + 80056c8: 68fb ldr r3, [r7, #12] + 80056ca: 2200 movs r2, #0 + 80056cc: 66da str r2, [r3, #108] @ 0x6c if (!(IS_LPUART_INSTANCE(huart->Instance))) - 8005686: 68fb ldr r3, [r7, #12] - 8005688: 681b ldr r3, [r3, #0] - 800568a: 4a18 ldr r2, [pc, #96] @ (80056ec ) - 800568c: 4293 cmp r3, r2 - 800568e: d01f beq.n 80056d0 + 80056ce: 68fb ldr r3, [r7, #12] + 80056d0: 681b ldr r3, [r3, #0] + 80056d2: 4a18 ldr r2, [pc, #96] @ (8005734 ) + 80056d4: 4293 cmp r3, r2 + 80056d6: d01f beq.n 8005718 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - 8005690: 68fb ldr r3, [r7, #12] - 8005692: 681b ldr r3, [r3, #0] - 8005694: 685b ldr r3, [r3, #4] - 8005696: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 800569a: 2b00 cmp r3, #0 - 800569c: d018 beq.n 80056d0 + 80056d8: 68fb ldr r3, [r7, #12] + 80056da: 681b ldr r3, [r3, #0] + 80056dc: 685b ldr r3, [r3, #4] + 80056de: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 80056e2: 2b00 cmp r3, #0 + 80056e4: d018 beq.n 8005718 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - 800569e: 68fb ldr r3, [r7, #12] - 80056a0: 681b ldr r3, [r3, #0] - 80056a2: 617b str r3, [r7, #20] + 80056e6: 68fb ldr r3, [r7, #12] + 80056e8: 681b ldr r3, [r3, #0] + 80056ea: 617b str r3, [r7, #20] */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80056a4: 697b ldr r3, [r7, #20] - 80056a6: e853 3f00 ldrex r3, [r3] - 80056aa: 613b str r3, [r7, #16] + 80056ec: 697b ldr r3, [r7, #20] + 80056ee: e853 3f00 ldrex r3, [r3] + 80056f2: 613b str r3, [r7, #16] return(result); - 80056ac: 693b ldr r3, [r7, #16] - 80056ae: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 - 80056b2: 627b str r3, [r7, #36] @ 0x24 - 80056b4: 68fb ldr r3, [r7, #12] - 80056b6: 681b ldr r3, [r3, #0] - 80056b8: 461a mov r2, r3 - 80056ba: 6a7b ldr r3, [r7, #36] @ 0x24 - 80056bc: 623b str r3, [r7, #32] - 80056be: 61fa str r2, [r7, #28] + 80056f4: 693b ldr r3, [r7, #16] + 80056f6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 + 80056fa: 627b str r3, [r7, #36] @ 0x24 + 80056fc: 68fb ldr r3, [r7, #12] + 80056fe: 681b ldr r3, [r3, #0] + 8005700: 461a mov r2, r3 + 8005702: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005704: 623b str r3, [r7, #32] + 8005706: 61fa str r2, [r7, #28] */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80056c0: 69f9 ldr r1, [r7, #28] - 80056c2: 6a3a ldr r2, [r7, #32] - 80056c4: e841 2300 strex r3, r2, [r1] - 80056c8: 61bb str r3, [r7, #24] + 8005708: 69f9 ldr r1, [r7, #28] + 800570a: 6a3a ldr r2, [r7, #32] + 800570c: e841 2300 strex r3, r2, [r1] + 8005710: 61bb str r3, [r7, #24] return(result); - 80056ca: 69bb ldr r3, [r7, #24] - 80056cc: 2b00 cmp r3, #0 - 80056ce: d1e6 bne.n 800569e + 8005712: 69bb ldr r3, [r7, #24] + 8005714: 2b00 cmp r3, #0 + 8005716: d1e6 bne.n 80056e6 } } return (UART_Start_Receive_IT(huart, pData, Size)); - 80056d0: 88fb ldrh r3, [r7, #6] - 80056d2: 461a mov r2, r3 - 80056d4: 68b9 ldr r1, [r7, #8] - 80056d6: 68f8 ldr r0, [r7, #12] - 80056d8: f000 ffe8 bl 80066ac - 80056dc: 4603 mov r3, r0 - 80056de: e000 b.n 80056e2 + 8005718: 88fb ldrh r3, [r7, #6] + 800571a: 461a mov r2, r3 + 800571c: 68b9 ldr r1, [r7, #8] + 800571e: 68f8 ldr r0, [r7, #12] + 8005720: f000 ffe8 bl 80066f4 + 8005724: 4603 mov r3, r0 + 8005726: e000 b.n 800572a } else { return HAL_BUSY; - 80056e0: 2302 movs r3, #2 + 8005728: 2302 movs r3, #2 } } - 80056e2: 4618 mov r0, r3 - 80056e4: 3728 adds r7, #40 @ 0x28 - 80056e6: 46bd mov sp, r7 - 80056e8: bd80 pop {r7, pc} - 80056ea: bf00 nop - 80056ec: 40008000 .word 0x40008000 + 800572a: 4618 mov r0, r3 + 800572c: 3728 adds r7, #40 @ 0x28 + 800572e: 46bd mov sp, r7 + 8005730: bd80 pop {r7, pc} + 8005732: bf00 nop + 8005734: 40008000 .word 0x40008000 -080056f0 : +08005738 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - 80056f0: b580 push {r7, lr} - 80056f2: b0ba sub sp, #232 @ 0xe8 - 80056f4: af00 add r7, sp, #0 - 80056f6: 6078 str r0, [r7, #4] + 8005738: b580 push {r7, lr} + 800573a: b0ba sub sp, #232 @ 0xe8 + 800573c: af00 add r7, sp, #0 + 800573e: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); - 80056f8: 687b ldr r3, [r7, #4] - 80056fa: 681b ldr r3, [r3, #0] - 80056fc: 69db ldr r3, [r3, #28] - 80056fe: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 + 8005740: 687b ldr r3, [r7, #4] + 8005742: 681b ldr r3, [r3, #0] + 8005744: 69db ldr r3, [r3, #28] + 8005746: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); - 8005702: 687b ldr r3, [r7, #4] - 8005704: 681b ldr r3, [r3, #0] - 8005706: 681b ldr r3, [r3, #0] - 8005708: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 + 800574a: 687b ldr r3, [r7, #4] + 800574c: 681b ldr r3, [r3, #0] + 800574e: 681b ldr r3, [r3, #0] + 8005750: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); - 800570c: 687b ldr r3, [r7, #4] - 800570e: 681b ldr r3, [r3, #0] - 8005710: 689b ldr r3, [r3, #8] - 8005712: f8c7 30dc str.w r3, [r7, #220] @ 0xdc + 8005754: 687b ldr r3, [r7, #4] + 8005756: 681b ldr r3, [r3, #0] + 8005758: 689b ldr r3, [r3, #8] + 800575a: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - 8005716: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 - 800571a: f640 030f movw r3, #2063 @ 0x80f - 800571e: 4013 ands r3, r2 - 8005720: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 + 800575e: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 + 8005762: f640 030f movw r3, #2063 @ 0x80f + 8005766: 4013 ands r3, r2 + 8005768: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) - 8005724: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 - 8005728: 2b00 cmp r3, #0 - 800572a: d11b bne.n 8005764 + 800576c: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 8005770: 2b00 cmp r3, #0 + 8005772: d11b bne.n 80057ac { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) - 800572c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005730: f003 0320 and.w r3, r3, #32 - 8005734: 2b00 cmp r3, #0 - 8005736: d015 beq.n 8005764 + 8005774: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005778: f003 0320 and.w r3, r3, #32 + 800577c: 2b00 cmp r3, #0 + 800577e: d015 beq.n 80057ac && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) - 8005738: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 800573c: f003 0320 and.w r3, r3, #32 - 8005740: 2b00 cmp r3, #0 - 8005742: d105 bne.n 8005750 + 8005780: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005784: f003 0320 and.w r3, r3, #32 + 8005788: 2b00 cmp r3, #0 + 800578a: d105 bne.n 8005798 || ((cr3its & USART_CR3_RXFTIE) != 0U))) - 8005744: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc - 8005748: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 800574c: 2b00 cmp r3, #0 - 800574e: d009 beq.n 8005764 + 800578c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005790: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 8005794: 2b00 cmp r3, #0 + 8005796: d009 beq.n 80057ac { if (huart->RxISR != NULL) - 8005750: 687b ldr r3, [r7, #4] - 8005752: 6f5b ldr r3, [r3, #116] @ 0x74 - 8005754: 2b00 cmp r3, #0 - 8005756: f000 8300 beq.w 8005d5a + 8005798: 687b ldr r3, [r7, #4] + 800579a: 6f5b ldr r3, [r3, #116] @ 0x74 + 800579c: 2b00 cmp r3, #0 + 800579e: f000 8300 beq.w 8005da2 { huart->RxISR(huart); - 800575a: 687b ldr r3, [r7, #4] - 800575c: 6f5b ldr r3, [r3, #116] @ 0x74 - 800575e: 6878 ldr r0, [r7, #4] - 8005760: 4798 blx r3 + 80057a2: 687b ldr r3, [r7, #4] + 80057a4: 6f5b ldr r3, [r3, #116] @ 0x74 + 80057a6: 6878 ldr r0, [r7, #4] + 80057a8: 4798 blx r3 } return; - 8005762: e2fa b.n 8005d5a + 80057aa: e2fa b.n 8005da2 } } /* If some errors occur */ if ((errorflags != 0U) - 8005764: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 - 8005768: 2b00 cmp r3, #0 - 800576a: f000 8123 beq.w 80059b4 + 80057ac: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 + 80057b0: 2b00 cmp r3, #0 + 80057b2: f000 8123 beq.w 80059fc && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) - 800576e: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc - 8005772: 4b8d ldr r3, [pc, #564] @ (80059a8 ) - 8005774: 4013 ands r3, r2 - 8005776: 2b00 cmp r3, #0 - 8005778: d106 bne.n 8005788 + 80057b6: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc + 80057ba: 4b8d ldr r3, [pc, #564] @ (80059f0 ) + 80057bc: 4013 ands r3, r2 + 80057be: 2b00 cmp r3, #0 + 80057c0: d106 bne.n 80057d0 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) - 800577a: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 - 800577e: 4b8b ldr r3, [pc, #556] @ (80059ac ) - 8005780: 4013 ands r3, r2 - 8005782: 2b00 cmp r3, #0 - 8005784: f000 8116 beq.w 80059b4 + 80057c2: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 + 80057c6: 4b8b ldr r3, [pc, #556] @ (80059f4 ) + 80057c8: 4013 ands r3, r2 + 80057ca: 2b00 cmp r3, #0 + 80057cc: f000 8116 beq.w 80059fc { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - 8005788: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 800578c: f003 0301 and.w r3, r3, #1 - 8005790: 2b00 cmp r3, #0 - 8005792: d011 beq.n 80057b8 - 8005794: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005798: f403 7380 and.w r3, r3, #256 @ 0x100 - 800579c: 2b00 cmp r3, #0 - 800579e: d00b beq.n 80057b8 + 80057d0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80057d4: f003 0301 and.w r3, r3, #1 + 80057d8: 2b00 cmp r3, #0 + 80057da: d011 beq.n 8005800 + 80057dc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80057e0: f403 7380 and.w r3, r3, #256 @ 0x100 + 80057e4: 2b00 cmp r3, #0 + 80057e6: d00b beq.n 8005800 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - 80057a0: 687b ldr r3, [r7, #4] - 80057a2: 681b ldr r3, [r3, #0] - 80057a4: 2201 movs r2, #1 - 80057a6: 621a str r2, [r3, #32] + 80057e8: 687b ldr r3, [r7, #4] + 80057ea: 681b ldr r3, [r3, #0] + 80057ec: 2201 movs r2, #1 + 80057ee: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; - 80057a8: 687b ldr r3, [r7, #4] - 80057aa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80057ae: f043 0201 orr.w r2, r3, #1 - 80057b2: 687b ldr r3, [r7, #4] - 80057b4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 80057f0: 687b ldr r3, [r7, #4] + 80057f2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80057f6: f043 0201 orr.w r2, r3, #1 + 80057fa: 687b ldr r3, [r7, #4] + 80057fc: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 80057b8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 80057bc: f003 0302 and.w r3, r3, #2 - 80057c0: 2b00 cmp r3, #0 - 80057c2: d011 beq.n 80057e8 - 80057c4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc - 80057c8: f003 0301 and.w r3, r3, #1 - 80057cc: 2b00 cmp r3, #0 - 80057ce: d00b beq.n 80057e8 + 8005800: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005804: f003 0302 and.w r3, r3, #2 + 8005808: 2b00 cmp r3, #0 + 800580a: d011 beq.n 8005830 + 800580c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005810: f003 0301 and.w r3, r3, #1 + 8005814: 2b00 cmp r3, #0 + 8005816: d00b beq.n 8005830 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - 80057d0: 687b ldr r3, [r7, #4] - 80057d2: 681b ldr r3, [r3, #0] - 80057d4: 2202 movs r2, #2 - 80057d6: 621a str r2, [r3, #32] + 8005818: 687b ldr r3, [r7, #4] + 800581a: 681b ldr r3, [r3, #0] + 800581c: 2202 movs r2, #2 + 800581e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; - 80057d8: 687b ldr r3, [r7, #4] - 80057da: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80057de: f043 0204 orr.w r2, r3, #4 - 80057e2: 687b ldr r3, [r7, #4] - 80057e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8005820: 687b ldr r3, [r7, #4] + 8005822: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005826: f043 0204 orr.w r2, r3, #4 + 800582a: 687b ldr r3, [r7, #4] + 800582c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 80057e8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 80057ec: f003 0304 and.w r3, r3, #4 - 80057f0: 2b00 cmp r3, #0 - 80057f2: d011 beq.n 8005818 - 80057f4: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc - 80057f8: f003 0301 and.w r3, r3, #1 - 80057fc: 2b00 cmp r3, #0 - 80057fe: d00b beq.n 8005818 + 8005830: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005834: f003 0304 and.w r3, r3, #4 + 8005838: 2b00 cmp r3, #0 + 800583a: d011 beq.n 8005860 + 800583c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005840: f003 0301 and.w r3, r3, #1 + 8005844: 2b00 cmp r3, #0 + 8005846: d00b beq.n 8005860 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - 8005800: 687b ldr r3, [r7, #4] - 8005802: 681b ldr r3, [r3, #0] - 8005804: 2204 movs r2, #4 - 8005806: 621a str r2, [r3, #32] + 8005848: 687b ldr r3, [r7, #4] + 800584a: 681b ldr r3, [r3, #0] + 800584c: 2204 movs r2, #4 + 800584e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; - 8005808: 687b ldr r3, [r7, #4] - 800580a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800580e: f043 0202 orr.w r2, r3, #2 - 8005812: 687b ldr r3, [r7, #4] - 8005814: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8005850: 687b ldr r3, [r7, #4] + 8005852: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005856: f043 0202 orr.w r2, r3, #2 + 800585a: 687b ldr r3, [r7, #4] + 800585c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) - 8005818: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 800581c: f003 0308 and.w r3, r3, #8 - 8005820: 2b00 cmp r3, #0 - 8005822: d017 beq.n 8005854 + 8005860: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005864: f003 0308 and.w r3, r3, #8 + 8005868: 2b00 cmp r3, #0 + 800586a: d017 beq.n 800589c && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || - 8005824: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005828: f003 0320 and.w r3, r3, #32 - 800582c: 2b00 cmp r3, #0 - 800582e: d105 bne.n 800583c + 800586c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005870: f003 0320 and.w r3, r3, #32 + 8005874: 2b00 cmp r3, #0 + 8005876: d105 bne.n 8005884 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) - 8005830: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc - 8005834: 4b5c ldr r3, [pc, #368] @ (80059a8 ) - 8005836: 4013 ands r3, r2 + 8005878: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc + 800587c: 4b5c ldr r3, [pc, #368] @ (80059f0 ) + 800587e: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || - 8005838: 2b00 cmp r3, #0 - 800583a: d00b beq.n 8005854 + 8005880: 2b00 cmp r3, #0 + 8005882: d00b beq.n 800589c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 800583c: 687b ldr r3, [r7, #4] - 800583e: 681b ldr r3, [r3, #0] - 8005840: 2208 movs r2, #8 - 8005842: 621a str r2, [r3, #32] + 8005884: 687b ldr r3, [r7, #4] + 8005886: 681b ldr r3, [r3, #0] + 8005888: 2208 movs r2, #8 + 800588a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; - 8005844: 687b ldr r3, [r7, #4] - 8005846: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800584a: f043 0208 orr.w r2, r3, #8 - 800584e: 687b ldr r3, [r7, #4] - 8005850: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 800588c: 687b ldr r3, [r7, #4] + 800588e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005892: f043 0208 orr.w r2, r3, #8 + 8005896: 687b ldr r3, [r7, #4] + 8005898: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - 8005854: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005858: f403 6300 and.w r3, r3, #2048 @ 0x800 - 800585c: 2b00 cmp r3, #0 - 800585e: d012 beq.n 8005886 - 8005860: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005864: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 - 8005868: 2b00 cmp r3, #0 - 800586a: d00c beq.n 8005886 + 800589c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80058a0: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80058a4: 2b00 cmp r3, #0 + 80058a6: d012 beq.n 80058ce + 80058a8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80058ac: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 + 80058b0: 2b00 cmp r3, #0 + 80058b2: d00c beq.n 80058ce { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 800586c: 687b ldr r3, [r7, #4] - 800586e: 681b ldr r3, [r3, #0] - 8005870: f44f 6200 mov.w r2, #2048 @ 0x800 - 8005874: 621a str r2, [r3, #32] + 80058b4: 687b ldr r3, [r7, #4] + 80058b6: 681b ldr r3, [r3, #0] + 80058b8: f44f 6200 mov.w r2, #2048 @ 0x800 + 80058bc: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; - 8005876: 687b ldr r3, [r7, #4] - 8005878: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800587c: f043 0220 orr.w r2, r3, #32 - 8005880: 687b ldr r3, [r7, #4] - 8005882: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 80058be: 687b ldr r3, [r7, #4] + 80058c0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80058c4: f043 0220 orr.w r2, r3, #32 + 80058c8: 687b ldr r3, [r7, #4] + 80058ca: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) - 8005886: 687b ldr r3, [r7, #4] - 8005888: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 800588c: 2b00 cmp r3, #0 - 800588e: f000 8266 beq.w 8005d5e + 80058ce: 687b ldr r3, [r7, #4] + 80058d0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 80058d4: 2b00 cmp r3, #0 + 80058d6: f000 8266 beq.w 8005da6 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) - 8005892: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005896: f003 0320 and.w r3, r3, #32 - 800589a: 2b00 cmp r3, #0 - 800589c: d013 beq.n 80058c6 + 80058da: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 80058de: f003 0320 and.w r3, r3, #32 + 80058e2: 2b00 cmp r3, #0 + 80058e4: d013 beq.n 800590e && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) - 800589e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 80058a2: f003 0320 and.w r3, r3, #32 - 80058a6: 2b00 cmp r3, #0 - 80058a8: d105 bne.n 80058b6 + 80058e6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 80058ea: f003 0320 and.w r3, r3, #32 + 80058ee: 2b00 cmp r3, #0 + 80058f0: d105 bne.n 80058fe || ((cr3its & USART_CR3_RXFTIE) != 0U))) - 80058aa: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc - 80058ae: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 - 80058b2: 2b00 cmp r3, #0 - 80058b4: d007 beq.n 80058c6 + 80058f2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 80058f6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 + 80058fa: 2b00 cmp r3, #0 + 80058fc: d007 beq.n 800590e { if (huart->RxISR != NULL) - 80058b6: 687b ldr r3, [r7, #4] - 80058b8: 6f5b ldr r3, [r3, #116] @ 0x74 - 80058ba: 2b00 cmp r3, #0 - 80058bc: d003 beq.n 80058c6 + 80058fe: 687b ldr r3, [r7, #4] + 8005900: 6f5b ldr r3, [r3, #116] @ 0x74 + 8005902: 2b00 cmp r3, #0 + 8005904: d003 beq.n 800590e { huart->RxISR(huart); - 80058be: 687b ldr r3, [r7, #4] - 80058c0: 6f5b ldr r3, [r3, #116] @ 0x74 - 80058c2: 6878 ldr r0, [r7, #4] - 80058c4: 4798 blx r3 + 8005906: 687b ldr r3, [r7, #4] + 8005908: 6f5b ldr r3, [r3, #116] @ 0x74 + 800590a: 6878 ldr r0, [r7, #4] + 800590c: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; - 80058c6: 687b ldr r3, [r7, #4] - 80058c8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80058cc: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 + 800590e: 687b ldr r3, [r7, #4] + 8005910: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8005914: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - 80058d0: 687b ldr r3, [r7, #4] - 80058d2: 681b ldr r3, [r3, #0] - 80058d4: 689b ldr r3, [r3, #8] - 80058d6: f003 0340 and.w r3, r3, #64 @ 0x40 - 80058da: 2b40 cmp r3, #64 @ 0x40 - 80058dc: d005 beq.n 80058ea + 8005918: 687b ldr r3, [r7, #4] + 800591a: 681b ldr r3, [r3, #0] + 800591c: 689b ldr r3, [r3, #8] + 800591e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005922: 2b40 cmp r3, #64 @ 0x40 + 8005924: d005 beq.n 8005932 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) - 80058de: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 - 80058e2: f003 0328 and.w r3, r3, #40 @ 0x28 + 8005926: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 + 800592a: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - 80058e6: 2b00 cmp r3, #0 - 80058e8: d054 beq.n 8005994 + 800592e: 2b00 cmp r3, #0 + 8005930: d054 beq.n 80059dc { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - 80058ea: 6878 ldr r0, [r7, #4] - 80058ec: f001 f800 bl 80068f0 + 8005932: 6878 ldr r0, [r7, #4] + 8005934: f001 f800 bl 8006938 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 80058f0: 687b ldr r3, [r7, #4] - 80058f2: 681b ldr r3, [r3, #0] - 80058f4: 689b ldr r3, [r3, #8] - 80058f6: f003 0340 and.w r3, r3, #64 @ 0x40 - 80058fa: 2b40 cmp r3, #64 @ 0x40 - 80058fc: d146 bne.n 800598c + 8005938: 687b ldr r3, [r7, #4] + 800593a: 681b ldr r3, [r3, #0] + 800593c: 689b ldr r3, [r3, #8] + 800593e: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005942: 2b40 cmp r3, #64 @ 0x40 + 8005944: d146 bne.n 80059d4 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 80058fe: 687b ldr r3, [r7, #4] - 8005900: 681b ldr r3, [r3, #0] - 8005902: 3308 adds r3, #8 - 8005904: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 8005946: 687b ldr r3, [r7, #4] + 8005948: 681b ldr r3, [r3, #0] + 800594a: 3308 adds r3, #8 + 800594c: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005908: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c - 800590c: e853 3f00 ldrex r3, [r3] - 8005910: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8005950: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 8005954: e853 3f00 ldrex r3, [r3] + 8005958: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); - 8005914: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 - 8005918: f023 0340 bic.w r3, r3, #64 @ 0x40 - 800591c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 - 8005920: 687b ldr r3, [r7, #4] - 8005922: 681b ldr r3, [r3, #0] - 8005924: 3308 adds r3, #8 - 8005926: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 - 800592a: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 - 800592e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + 800595c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8005960: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8005964: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 + 8005968: 687b ldr r3, [r7, #4] + 800596a: 681b ldr r3, [r3, #0] + 800596c: 3308 adds r3, #8 + 800596e: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 + 8005972: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 + 8005976: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005932: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 - 8005936: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 - 800593a: e841 2300 strex r3, r2, [r1] - 800593e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + 800597a: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 + 800597e: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 + 8005982: e841 2300 strex r3, r2, [r1] + 8005986: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); - 8005942: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 - 8005946: 2b00 cmp r3, #0 - 8005948: d1d9 bne.n 80058fe + 800598a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 800598e: 2b00 cmp r3, #0 + 8005990: d1d9 bne.n 8005946 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) - 800594a: 687b ldr r3, [r7, #4] - 800594c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8005950: 2b00 cmp r3, #0 - 8005952: d017 beq.n 8005984 + 8005992: 687b ldr r3, [r7, #4] + 8005994: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005998: 2b00 cmp r3, #0 + 800599a: d017 beq.n 80059cc { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - 8005954: 687b ldr r3, [r7, #4] - 8005956: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 800595a: 4a15 ldr r2, [pc, #84] @ (80059b0 ) - 800595c: 639a str r2, [r3, #56] @ 0x38 + 800599c: 687b ldr r3, [r7, #4] + 800599e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80059a2: 4a15 ldr r2, [pc, #84] @ (80059f8 ) + 80059a4: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - 800595e: 687b ldr r3, [r7, #4] - 8005960: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8005964: 4618 mov r0, r3 - 8005966: f7fd fef3 bl 8003750 - 800596a: 4603 mov r3, r0 - 800596c: 2b00 cmp r3, #0 - 800596e: d019 beq.n 80059a4 + 80059a6: 687b ldr r3, [r7, #4] + 80059a8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80059ac: 4618 mov r0, r3 + 80059ae: f7fd fef3 bl 8003798 + 80059b2: 4603 mov r3, r0 + 80059b4: 2b00 cmp r3, #0 + 80059b6: d019 beq.n 80059ec { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); - 8005970: 687b ldr r3, [r7, #4] - 8005972: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8005976: 6b9b ldr r3, [r3, #56] @ 0x38 - 8005978: 687a ldr r2, [r7, #4] - 800597a: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 - 800597e: 4610 mov r0, r2 - 8005980: 4798 blx r3 + 80059b8: 687b ldr r3, [r7, #4] + 80059ba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 80059be: 6b9b ldr r3, [r3, #56] @ 0x38 + 80059c0: 687a ldr r2, [r7, #4] + 80059c2: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 + 80059c6: 4610 mov r0, r2 + 80059c8: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8005982: e00f b.n 80059a4 + 80059ca: e00f b.n 80059ec #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 8005984: 6878 ldr r0, [r7, #4] - 8005986: f000 f9f5 bl 8005d74 + 80059cc: 6878 ldr r0, [r7, #4] + 80059ce: f000 f9f5 bl 8005dbc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 800598a: e00b b.n 80059a4 + 80059d2: e00b b.n 80059ec #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 800598c: 6878 ldr r0, [r7, #4] - 800598e: f000 f9f1 bl 8005d74 + 80059d4: 6878 ldr r0, [r7, #4] + 80059d6: f000 f9f1 bl 8005dbc if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 8005992: e007 b.n 80059a4 + 80059da: e007 b.n 80059ec #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 8005994: 6878 ldr r0, [r7, #4] - 8005996: f000 f9ed bl 8005d74 + 80059dc: 6878 ldr r0, [r7, #4] + 80059de: f000 f9ed bl 8005dbc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 800599a: 687b ldr r3, [r7, #4] - 800599c: 2200 movs r2, #0 - 800599e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 80059e2: 687b ldr r3, [r7, #4] + 80059e4: 2200 movs r2, #0 + 80059e6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; - 80059a2: e1dc b.n 8005d5e + 80059ea: e1dc b.n 8005da6 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 80059a4: bf00 nop + 80059ec: bf00 nop return; - 80059a6: e1da b.n 8005d5e - 80059a8: 10000001 .word 0x10000001 - 80059ac: 04000120 .word 0x04000120 - 80059b0: 080069bd .word 0x080069bd + 80059ee: e1da b.n 8005da6 + 80059f0: 10000001 .word 0x10000001 + 80059f4: 04000120 .word 0x04000120 + 80059f8: 08006a05 .word 0x08006a05 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 80059b4: 687b ldr r3, [r7, #4] - 80059b6: 6edb ldr r3, [r3, #108] @ 0x6c - 80059b8: 2b01 cmp r3, #1 - 80059ba: f040 8170 bne.w 8005c9e + 80059fc: 687b ldr r3, [r7, #4] + 80059fe: 6edb ldr r3, [r3, #108] @ 0x6c + 8005a00: 2b01 cmp r3, #1 + 8005a02: f040 8170 bne.w 8005ce6 && ((isrflags & USART_ISR_IDLE) != 0U) - 80059be: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 80059c2: f003 0310 and.w r3, r3, #16 - 80059c6: 2b00 cmp r3, #0 - 80059c8: f000 8169 beq.w 8005c9e + 8005a06: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005a0a: f003 0310 and.w r3, r3, #16 + 8005a0e: 2b00 cmp r3, #0 + 8005a10: f000 8169 beq.w 8005ce6 && ((cr1its & USART_ISR_IDLE) != 0U)) - 80059cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 80059d0: f003 0310 and.w r3, r3, #16 - 80059d4: 2b00 cmp r3, #0 - 80059d6: f000 8162 beq.w 8005c9e + 8005a14: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005a18: f003 0310 and.w r3, r3, #16 + 8005a1c: 2b00 cmp r3, #0 + 8005a1e: f000 8162 beq.w 8005ce6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 80059da: 687b ldr r3, [r7, #4] - 80059dc: 681b ldr r3, [r3, #0] - 80059de: 2210 movs r2, #16 - 80059e0: 621a str r2, [r3, #32] + 8005a22: 687b ldr r3, [r7, #4] + 8005a24: 681b ldr r3, [r3, #0] + 8005a26: 2210 movs r2, #16 + 8005a28: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - 80059e2: 687b ldr r3, [r7, #4] - 80059e4: 681b ldr r3, [r3, #0] - 80059e6: 689b ldr r3, [r3, #8] - 80059e8: f003 0340 and.w r3, r3, #64 @ 0x40 - 80059ec: 2b40 cmp r3, #64 @ 0x40 - 80059ee: f040 80d8 bne.w 8005ba2 + 8005a2a: 687b ldr r3, [r7, #4] + 8005a2c: 681b ldr r3, [r3, #0] + 8005a2e: 689b ldr r3, [r3, #8] + 8005a30: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005a34: 2b40 cmp r3, #64 @ 0x40 + 8005a36: f040 80d8 bne.w 8005bea { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - 80059f2: 687b ldr r3, [r7, #4] - 80059f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 80059f8: 681b ldr r3, [r3, #0] - 80059fa: 685b ldr r3, [r3, #4] - 80059fc: f8a7 30be strh.w r3, [r7, #190] @ 0xbe + 8005a3a: 687b ldr r3, [r7, #4] + 8005a3c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005a40: 681b ldr r3, [r3, #0] + 8005a42: 685b ldr r3, [r3, #4] + 8005a44: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) - 8005a00: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe - 8005a04: 2b00 cmp r3, #0 - 8005a06: f000 80af beq.w 8005b68 + 8005a48: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe + 8005a4c: 2b00 cmp r3, #0 + 8005a4e: f000 80af beq.w 8005bb0 && (nb_remaining_rx_data < huart->RxXferSize)) - 8005a0a: 687b ldr r3, [r7, #4] - 8005a0c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 8005a10: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe - 8005a14: 429a cmp r2, r3 - 8005a16: f080 80a7 bcs.w 8005b68 + 8005a52: 687b ldr r3, [r7, #4] + 8005a54: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005a58: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8005a5c: 429a cmp r2, r3 + 8005a5e: f080 80a7 bcs.w 8005bb0 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; - 8005a1a: 687b ldr r3, [r7, #4] - 8005a1c: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe - 8005a20: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 8005a62: 687b ldr r3, [r7, #4] + 8005a64: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8005a68: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) - 8005a24: 687b ldr r3, [r7, #4] - 8005a26: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8005a2a: 681b ldr r3, [r3, #0] - 8005a2c: 681b ldr r3, [r3, #0] - 8005a2e: f003 0320 and.w r3, r3, #32 - 8005a32: 2b00 cmp r3, #0 - 8005a34: f040 8087 bne.w 8005b46 + 8005a6c: 687b ldr r3, [r7, #4] + 8005a6e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005a72: 681b ldr r3, [r3, #0] + 8005a74: 681b ldr r3, [r3, #0] + 8005a76: f003 0320 and.w r3, r3, #32 + 8005a7a: 2b00 cmp r3, #0 + 8005a7c: f040 8087 bne.w 8005b8e { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 8005a38: 687b ldr r3, [r7, #4] - 8005a3a: 681b ldr r3, [r3, #0] - 8005a3c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 8005a80: 687b ldr r3, [r7, #4] + 8005a82: 681b ldr r3, [r3, #0] + 8005a84: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005a40: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 - 8005a44: e853 3f00 ldrex r3, [r3] - 8005a48: f8c7 3084 str.w r3, [r7, #132] @ 0x84 - return(result); - 8005a4c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 - 8005a50: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8005a54: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 - 8005a58: 687b ldr r3, [r7, #4] - 8005a5a: 681b ldr r3, [r3, #0] - 8005a5c: 461a mov r2, r3 - 8005a5e: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 - 8005a62: f8c7 3094 str.w r3, [r7, #148] @ 0x94 - 8005a66: f8c7 2090 str.w r2, [r7, #144] @ 0x90 - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005a6a: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 - 8005a6e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 - 8005a72: e841 2300 strex r3, r2, [r1] - 8005a76: f8c7 308c str.w r3, [r7, #140] @ 0x8c - return(result); - 8005a7a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c - 8005a7e: 2b00 cmp r3, #0 - 8005a80: d1da bne.n 8005a38 - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8005a82: 687b ldr r3, [r7, #4] - 8005a84: 681b ldr r3, [r3, #0] - 8005a86: 3308 adds r3, #8 - 8005a88: 677b str r3, [r7, #116] @ 0x74 - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005a8a: 6f7b ldr r3, [r7, #116] @ 0x74 + 8005a88: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005a8c: e853 3f00 ldrex r3, [r3] - 8005a90: 673b str r3, [r7, #112] @ 0x70 + 8005a90: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); - 8005a92: 6f3b ldr r3, [r7, #112] @ 0x70 - 8005a94: f023 0301 bic.w r3, r3, #1 - 8005a98: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 - 8005a9c: 687b ldr r3, [r7, #4] - 8005a9e: 681b ldr r3, [r3, #0] - 8005aa0: 3308 adds r3, #8 - 8005aa2: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 - 8005aa6: f8c7 2080 str.w r2, [r7, #128] @ 0x80 - 8005aaa: 67fb str r3, [r7, #124] @ 0x7c + 8005a94: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8005a98: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8005a9c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 + 8005aa0: 687b ldr r3, [r7, #4] + 8005aa2: 681b ldr r3, [r3, #0] + 8005aa4: 461a mov r2, r3 + 8005aa6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 + 8005aaa: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8005aae: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005aac: 6ff9 ldr r1, [r7, #124] @ 0x7c - 8005aae: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 - 8005ab2: e841 2300 strex r3, r2, [r1] - 8005ab6: 67bb str r3, [r7, #120] @ 0x78 + 8005ab2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 + 8005ab6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 8005aba: e841 2300 strex r3, r2, [r1] + 8005abe: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); - 8005ab8: 6fbb ldr r3, [r7, #120] @ 0x78 - 8005aba: 2b00 cmp r3, #0 - 8005abc: d1e1 bne.n 8005a82 + 8005ac2: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8005ac6: 2b00 cmp r3, #0 + 8005ac8: d1da bne.n 8005a80 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8005aca: 687b ldr r3, [r7, #4] + 8005acc: 681b ldr r3, [r3, #0] + 8005ace: 3308 adds r3, #8 + 8005ad0: 677b str r3, [r7, #116] @ 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005ad2: 6f7b ldr r3, [r7, #116] @ 0x74 + 8005ad4: e853 3f00 ldrex r3, [r3] + 8005ad8: 673b str r3, [r7, #112] @ 0x70 + return(result); + 8005ada: 6f3b ldr r3, [r7, #112] @ 0x70 + 8005adc: f023 0301 bic.w r3, r3, #1 + 8005ae0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8005ae4: 687b ldr r3, [r7, #4] + 8005ae6: 681b ldr r3, [r3, #0] + 8005ae8: 3308 adds r3, #8 + 8005aea: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 + 8005aee: f8c7 2080 str.w r2, [r7, #128] @ 0x80 + 8005af2: 67fb str r3, [r7, #124] @ 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005af4: 6ff9 ldr r1, [r7, #124] @ 0x7c + 8005af6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 8005afa: e841 2300 strex r3, r2, [r1] + 8005afe: 67bb str r3, [r7, #120] @ 0x78 + return(result); + 8005b00: 6fbb ldr r3, [r7, #120] @ 0x78 + 8005b02: 2b00 cmp r3, #0 + 8005b04: d1e1 bne.n 8005aca /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - 8005abe: 687b ldr r3, [r7, #4] - 8005ac0: 681b ldr r3, [r3, #0] - 8005ac2: 3308 adds r3, #8 - 8005ac4: 663b str r3, [r7, #96] @ 0x60 + 8005b06: 687b ldr r3, [r7, #4] + 8005b08: 681b ldr r3, [r3, #0] + 8005b0a: 3308 adds r3, #8 + 8005b0c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005ac6: 6e3b ldr r3, [r7, #96] @ 0x60 - 8005ac8: e853 3f00 ldrex r3, [r3] - 8005acc: 65fb str r3, [r7, #92] @ 0x5c + 8005b0e: 6e3b ldr r3, [r7, #96] @ 0x60 + 8005b10: e853 3f00 ldrex r3, [r3] + 8005b14: 65fb str r3, [r7, #92] @ 0x5c return(result); - 8005ace: 6dfb ldr r3, [r7, #92] @ 0x5c - 8005ad0: f023 0340 bic.w r3, r3, #64 @ 0x40 - 8005ad4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 - 8005ad8: 687b ldr r3, [r7, #4] - 8005ada: 681b ldr r3, [r3, #0] - 8005adc: 3308 adds r3, #8 - 8005ade: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 - 8005ae2: 66fa str r2, [r7, #108] @ 0x6c - 8005ae4: 66bb str r3, [r7, #104] @ 0x68 + 8005b16: 6dfb ldr r3, [r7, #92] @ 0x5c + 8005b18: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8005b1c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 + 8005b20: 687b ldr r3, [r7, #4] + 8005b22: 681b ldr r3, [r3, #0] + 8005b24: 3308 adds r3, #8 + 8005b26: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 + 8005b2a: 66fa str r2, [r7, #108] @ 0x6c + 8005b2c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005ae6: 6eb9 ldr r1, [r7, #104] @ 0x68 - 8005ae8: 6efa ldr r2, [r7, #108] @ 0x6c - 8005aea: e841 2300 strex r3, r2, [r1] - 8005aee: 667b str r3, [r7, #100] @ 0x64 + 8005b2e: 6eb9 ldr r1, [r7, #104] @ 0x68 + 8005b30: 6efa ldr r2, [r7, #108] @ 0x6c + 8005b32: e841 2300 strex r3, r2, [r1] + 8005b36: 667b str r3, [r7, #100] @ 0x64 return(result); - 8005af0: 6e7b ldr r3, [r7, #100] @ 0x64 - 8005af2: 2b00 cmp r3, #0 - 8005af4: d1e3 bne.n 8005abe + 8005b38: 6e7b ldr r3, [r7, #100] @ 0x64 + 8005b3a: 2b00 cmp r3, #0 + 8005b3c: d1e3 bne.n 8005b06 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8005af6: 687b ldr r3, [r7, #4] - 8005af8: 2220 movs r2, #32 - 8005afa: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 8005b3e: 687b ldr r3, [r7, #4] + 8005b40: 2220 movs r2, #32 + 8005b42: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8005afe: 687b ldr r3, [r7, #4] - 8005b00: 2200 movs r2, #0 - 8005b02: 66da str r2, [r3, #108] @ 0x6c + 8005b46: 687b ldr r3, [r7, #4] + 8005b48: 2200 movs r2, #0 + 8005b4a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8005b04: 687b ldr r3, [r7, #4] - 8005b06: 681b ldr r3, [r3, #0] - 8005b08: 64fb str r3, [r7, #76] @ 0x4c + 8005b4c: 687b ldr r3, [r7, #4] + 8005b4e: 681b ldr r3, [r3, #0] + 8005b50: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005b0a: 6cfb ldr r3, [r7, #76] @ 0x4c - 8005b0c: e853 3f00 ldrex r3, [r3] - 8005b10: 64bb str r3, [r7, #72] @ 0x48 + 8005b52: 6cfb ldr r3, [r7, #76] @ 0x4c + 8005b54: e853 3f00 ldrex r3, [r3] + 8005b58: 64bb str r3, [r7, #72] @ 0x48 return(result); - 8005b12: 6cbb ldr r3, [r7, #72] @ 0x48 - 8005b14: f023 0310 bic.w r3, r3, #16 - 8005b18: f8c7 30ac str.w r3, [r7, #172] @ 0xac - 8005b1c: 687b ldr r3, [r7, #4] - 8005b1e: 681b ldr r3, [r3, #0] - 8005b20: 461a mov r2, r3 - 8005b22: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 8005b26: 65bb str r3, [r7, #88] @ 0x58 - 8005b28: 657a str r2, [r7, #84] @ 0x54 + 8005b5a: 6cbb ldr r3, [r7, #72] @ 0x48 + 8005b5c: f023 0310 bic.w r3, r3, #16 + 8005b60: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8005b64: 687b ldr r3, [r7, #4] + 8005b66: 681b ldr r3, [r3, #0] + 8005b68: 461a mov r2, r3 + 8005b6a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8005b6e: 65bb str r3, [r7, #88] @ 0x58 + 8005b70: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005b2a: 6d79 ldr r1, [r7, #84] @ 0x54 - 8005b2c: 6dba ldr r2, [r7, #88] @ 0x58 - 8005b2e: e841 2300 strex r3, r2, [r1] - 8005b32: 653b str r3, [r7, #80] @ 0x50 + 8005b72: 6d79 ldr r1, [r7, #84] @ 0x54 + 8005b74: 6dba ldr r2, [r7, #88] @ 0x58 + 8005b76: e841 2300 strex r3, r2, [r1] + 8005b7a: 653b str r3, [r7, #80] @ 0x50 return(result); - 8005b34: 6d3b ldr r3, [r7, #80] @ 0x50 - 8005b36: 2b00 cmp r3, #0 - 8005b38: d1e4 bne.n 8005b04 + 8005b7c: 6d3b ldr r3, [r7, #80] @ 0x50 + 8005b7e: 2b00 cmp r3, #0 + 8005b80: d1e4 bne.n 8005b4c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); - 8005b3a: 687b ldr r3, [r7, #4] - 8005b3c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8005b40: 4618 mov r0, r3 - 8005b42: f7fd fdac bl 800369e + 8005b82: 687b ldr r3, [r7, #4] + 8005b84: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005b88: 4618 mov r0, r3 + 8005b8a: f7fd fdac bl 80036e6 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; - 8005b46: 687b ldr r3, [r7, #4] - 8005b48: 2202 movs r2, #2 - 8005b4a: 671a str r2, [r3, #112] @ 0x70 + 8005b8e: 687b ldr r3, [r7, #4] + 8005b90: 2202 movs r2, #2 + 8005b92: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); - 8005b4c: 687b ldr r3, [r7, #4] - 8005b4e: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c - 8005b52: 687b ldr r3, [r7, #4] - 8005b54: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8005b58: b29b uxth r3, r3 - 8005b5a: 1ad3 subs r3, r2, r3 - 8005b5c: b29b uxth r3, r3 - 8005b5e: 4619 mov r1, r3 - 8005b60: 6878 ldr r0, [r7, #4] - 8005b62: f000 f911 bl 8005d88 + 8005b94: 687b ldr r3, [r7, #4] + 8005b96: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c + 8005b9a: 687b ldr r3, [r7, #4] + 8005b9c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005ba0: b29b uxth r3, r3 + 8005ba2: 1ad3 subs r3, r2, r3 + 8005ba4: b29b uxth r3, r3 + 8005ba6: 4619 mov r1, r3 + 8005ba8: 6878 ldr r0, [r7, #4] + 8005baa: f000 f911 bl 8005dd0 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } } } return; - 8005b66: e0fc b.n 8005d62 + 8005bae: e0fc b.n 8005daa if (nb_remaining_rx_data == huart->RxXferSize) - 8005b68: 687b ldr r3, [r7, #4] - 8005b6a: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 8005b6e: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe - 8005b72: 429a cmp r2, r3 - 8005b74: f040 80f5 bne.w 8005d62 + 8005bb0: 687b ldr r3, [r7, #4] + 8005bb2: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005bb6: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe + 8005bba: 429a cmp r2, r3 + 8005bbc: f040 80f5 bne.w 8005daa if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) - 8005b78: 687b ldr r3, [r7, #4] - 8005b7a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 - 8005b7e: 681b ldr r3, [r3, #0] - 8005b80: 681b ldr r3, [r3, #0] - 8005b82: f003 0320 and.w r3, r3, #32 - 8005b86: 2b20 cmp r3, #32 - 8005b88: f040 80eb bne.w 8005d62 + 8005bc0: 687b ldr r3, [r7, #4] + 8005bc2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 + 8005bc6: 681b ldr r3, [r3, #0] + 8005bc8: 681b ldr r3, [r3, #0] + 8005bca: f003 0320 and.w r3, r3, #32 + 8005bce: 2b20 cmp r3, #32 + 8005bd0: f040 80eb bne.w 8005daa huart->RxEventType = HAL_UART_RXEVENT_IDLE; - 8005b8c: 687b ldr r3, [r7, #4] - 8005b8e: 2202 movs r2, #2 - 8005b90: 671a str r2, [r3, #112] @ 0x70 + 8005bd4: 687b ldr r3, [r7, #4] + 8005bd6: 2202 movs r2, #2 + 8005bd8: 671a str r2, [r3, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 8005b92: 687b ldr r3, [r7, #4] - 8005b94: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 8005b98: 4619 mov r1, r3 - 8005b9a: 6878 ldr r0, [r7, #4] - 8005b9c: f000 f8f4 bl 8005d88 + 8005bda: 687b ldr r3, [r7, #4] + 8005bdc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8005be0: 4619 mov r1, r3 + 8005be2: 6878 ldr r0, [r7, #4] + 8005be4: f000 f8f4 bl 8005dd0 return; - 8005ba0: e0df b.n 8005d62 + 8005be8: e0df b.n 8005daa else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - 8005ba2: 687b ldr r3, [r7, #4] - 8005ba4: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c - 8005ba8: 687b ldr r3, [r7, #4] - 8005baa: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8005bae: b29b uxth r3, r3 - 8005bb0: 1ad3 subs r3, r2, r3 - 8005bb2: f8a7 30ce strh.w r3, [r7, #206] @ 0xce + 8005bea: 687b ldr r3, [r7, #4] + 8005bec: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c + 8005bf0: 687b ldr r3, [r7, #4] + 8005bf2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005bf6: b29b uxth r3, r3 + 8005bf8: 1ad3 subs r3, r2, r3 + 8005bfa: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) - 8005bb6: 687b ldr r3, [r7, #4] - 8005bb8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8005bbc: b29b uxth r3, r3 - 8005bbe: 2b00 cmp r3, #0 - 8005bc0: f000 80d1 beq.w 8005d66 + 8005bfe: 687b ldr r3, [r7, #4] + 8005c00: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8005c04: b29b uxth r3, r3 + 8005c06: 2b00 cmp r3, #0 + 8005c08: f000 80d1 beq.w 8005dae && (nb_rx_data > 0U)) - 8005bc4: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce - 8005bc8: 2b00 cmp r3, #0 - 8005bca: f000 80cc beq.w 8005d66 + 8005c0c: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8005c10: 2b00 cmp r3, #0 + 8005c12: f000 80cc beq.w 8005dae { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 8005bce: 687b ldr r3, [r7, #4] - 8005bd0: 681b ldr r3, [r3, #0] - 8005bd2: 63bb str r3, [r7, #56] @ 0x38 + 8005c16: 687b ldr r3, [r7, #4] + 8005c18: 681b ldr r3, [r3, #0] + 8005c1a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005bd4: 6bbb ldr r3, [r7, #56] @ 0x38 - 8005bd6: e853 3f00 ldrex r3, [r3] - 8005bda: 637b str r3, [r7, #52] @ 0x34 + 8005c1c: 6bbb ldr r3, [r7, #56] @ 0x38 + 8005c1e: e853 3f00 ldrex r3, [r3] + 8005c22: 637b str r3, [r7, #52] @ 0x34 return(result); - 8005bdc: 6b7b ldr r3, [r7, #52] @ 0x34 - 8005bde: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8005be2: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 - 8005be6: 687b ldr r3, [r7, #4] - 8005be8: 681b ldr r3, [r3, #0] - 8005bea: 461a mov r2, r3 - 8005bec: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 - 8005bf0: 647b str r3, [r7, #68] @ 0x44 - 8005bf2: 643a str r2, [r7, #64] @ 0x40 + 8005c24: 6b7b ldr r3, [r7, #52] @ 0x34 + 8005c26: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8005c2a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 + 8005c2e: 687b ldr r3, [r7, #4] + 8005c30: 681b ldr r3, [r3, #0] + 8005c32: 461a mov r2, r3 + 8005c34: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 + 8005c38: 647b str r3, [r7, #68] @ 0x44 + 8005c3a: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005bf4: 6c39 ldr r1, [r7, #64] @ 0x40 - 8005bf6: 6c7a ldr r2, [r7, #68] @ 0x44 - 8005bf8: e841 2300 strex r3, r2, [r1] - 8005bfc: 63fb str r3, [r7, #60] @ 0x3c + 8005c3c: 6c39 ldr r1, [r7, #64] @ 0x40 + 8005c3e: 6c7a ldr r2, [r7, #68] @ 0x44 + 8005c40: e841 2300 strex r3, r2, [r1] + 8005c44: 63fb str r3, [r7, #60] @ 0x3c return(result); - 8005bfe: 6bfb ldr r3, [r7, #60] @ 0x3c - 8005c00: 2b00 cmp r3, #0 - 8005c02: d1e4 bne.n 8005bce + 8005c46: 6bfb ldr r3, [r7, #60] @ 0x3c + 8005c48: 2b00 cmp r3, #0 + 8005c4a: d1e4 bne.n 8005c16 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - 8005c04: 687b ldr r3, [r7, #4] - 8005c06: 681b ldr r3, [r3, #0] - 8005c08: 3308 adds r3, #8 - 8005c0a: 627b str r3, [r7, #36] @ 0x24 + 8005c4c: 687b ldr r3, [r7, #4] + 8005c4e: 681b ldr r3, [r3, #0] + 8005c50: 3308 adds r3, #8 + 8005c52: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005c0c: 6a7b ldr r3, [r7, #36] @ 0x24 - 8005c0e: e853 3f00 ldrex r3, [r3] - 8005c12: 623b str r3, [r7, #32] + 8005c54: 6a7b ldr r3, [r7, #36] @ 0x24 + 8005c56: e853 3f00 ldrex r3, [r3] + 8005c5a: 623b str r3, [r7, #32] return(result); - 8005c14: 6a3b ldr r3, [r7, #32] - 8005c16: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8005c1a: f023 0301 bic.w r3, r3, #1 - 8005c1e: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 - 8005c22: 687b ldr r3, [r7, #4] - 8005c24: 681b ldr r3, [r3, #0] - 8005c26: 3308 adds r3, #8 - 8005c28: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 - 8005c2c: 633a str r2, [r7, #48] @ 0x30 - 8005c2e: 62fb str r3, [r7, #44] @ 0x2c + 8005c5c: 6a3b ldr r3, [r7, #32] + 8005c5e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8005c62: f023 0301 bic.w r3, r3, #1 + 8005c66: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 + 8005c6a: 687b ldr r3, [r7, #4] + 8005c6c: 681b ldr r3, [r3, #0] + 8005c6e: 3308 adds r3, #8 + 8005c70: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 + 8005c74: 633a str r2, [r7, #48] @ 0x30 + 8005c76: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005c30: 6af9 ldr r1, [r7, #44] @ 0x2c - 8005c32: 6b3a ldr r2, [r7, #48] @ 0x30 - 8005c34: e841 2300 strex r3, r2, [r1] - 8005c38: 62bb str r3, [r7, #40] @ 0x28 + 8005c78: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005c7a: 6b3a ldr r2, [r7, #48] @ 0x30 + 8005c7c: e841 2300 strex r3, r2, [r1] + 8005c80: 62bb str r3, [r7, #40] @ 0x28 return(result); - 8005c3a: 6abb ldr r3, [r7, #40] @ 0x28 - 8005c3c: 2b00 cmp r3, #0 - 8005c3e: d1e1 bne.n 8005c04 + 8005c82: 6abb ldr r3, [r7, #40] @ 0x28 + 8005c84: 2b00 cmp r3, #0 + 8005c86: d1e1 bne.n 8005c4c /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8005c40: 687b ldr r3, [r7, #4] - 8005c42: 2220 movs r2, #32 - 8005c44: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 8005c88: 687b ldr r3, [r7, #4] + 8005c8a: 2220 movs r2, #32 + 8005c8c: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8005c48: 687b ldr r3, [r7, #4] - 8005c4a: 2200 movs r2, #0 - 8005c4c: 66da str r2, [r3, #108] @ 0x6c + 8005c90: 687b ldr r3, [r7, #4] + 8005c92: 2200 movs r2, #0 + 8005c94: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; - 8005c4e: 687b ldr r3, [r7, #4] - 8005c50: 2200 movs r2, #0 - 8005c52: 675a str r2, [r3, #116] @ 0x74 + 8005c96: 687b ldr r3, [r7, #4] + 8005c98: 2200 movs r2, #0 + 8005c9a: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8005c54: 687b ldr r3, [r7, #4] - 8005c56: 681b ldr r3, [r3, #0] - 8005c58: 613b str r3, [r7, #16] + 8005c9c: 687b ldr r3, [r7, #4] + 8005c9e: 681b ldr r3, [r3, #0] + 8005ca0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8005c5a: 693b ldr r3, [r7, #16] - 8005c5c: e853 3f00 ldrex r3, [r3] - 8005c60: 60fb str r3, [r7, #12] + 8005ca2: 693b ldr r3, [r7, #16] + 8005ca4: e853 3f00 ldrex r3, [r3] + 8005ca8: 60fb str r3, [r7, #12] return(result); - 8005c62: 68fb ldr r3, [r7, #12] - 8005c64: f023 0310 bic.w r3, r3, #16 - 8005c68: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 - 8005c6c: 687b ldr r3, [r7, #4] - 8005c6e: 681b ldr r3, [r3, #0] - 8005c70: 461a mov r2, r3 - 8005c72: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 - 8005c76: 61fb str r3, [r7, #28] - 8005c78: 61ba str r2, [r7, #24] + 8005caa: 68fb ldr r3, [r7, #12] + 8005cac: f023 0310 bic.w r3, r3, #16 + 8005cb0: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 + 8005cb4: 687b ldr r3, [r7, #4] + 8005cb6: 681b ldr r3, [r3, #0] + 8005cb8: 461a mov r2, r3 + 8005cba: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 + 8005cbe: 61fb str r3, [r7, #28] + 8005cc0: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8005c7a: 69b9 ldr r1, [r7, #24] - 8005c7c: 69fa ldr r2, [r7, #28] - 8005c7e: e841 2300 strex r3, r2, [r1] - 8005c82: 617b str r3, [r7, #20] + 8005cc2: 69b9 ldr r1, [r7, #24] + 8005cc4: 69fa ldr r2, [r7, #28] + 8005cc6: e841 2300 strex r3, r2, [r1] + 8005cca: 617b str r3, [r7, #20] return(result); - 8005c84: 697b ldr r3, [r7, #20] - 8005c86: 2b00 cmp r3, #0 - 8005c88: d1e4 bne.n 8005c54 + 8005ccc: 697b ldr r3, [r7, #20] + 8005cce: 2b00 cmp r3, #0 + 8005cd0: d1e4 bne.n 8005c9c /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; - 8005c8a: 687b ldr r3, [r7, #4] - 8005c8c: 2202 movs r2, #2 - 8005c8e: 671a str r2, [r3, #112] @ 0x70 + 8005cd2: 687b ldr r3, [r7, #4] + 8005cd4: 2202 movs r2, #2 + 8005cd6: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); - 8005c90: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce - 8005c94: 4619 mov r1, r3 - 8005c96: 6878 ldr r0, [r7, #4] - 8005c98: f000 f876 bl 8005d88 + 8005cd8: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce + 8005cdc: 4619 mov r1, r3 + 8005cde: 6878 ldr r0, [r7, #4] + 8005ce0: f000 f876 bl 8005dd0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; - 8005c9c: e063 b.n 8005d66 + 8005ce4: e063 b.n 8005dae } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) - 8005c9e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005ca2: f403 1380 and.w r3, r3, #1048576 @ 0x100000 - 8005ca6: 2b00 cmp r3, #0 - 8005ca8: d00e beq.n 8005cc8 - 8005caa: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc - 8005cae: f403 0380 and.w r3, r3, #4194304 @ 0x400000 - 8005cb2: 2b00 cmp r3, #0 - 8005cb4: d008 beq.n 8005cc8 + 8005ce6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005cea: f403 1380 and.w r3, r3, #1048576 @ 0x100000 + 8005cee: 2b00 cmp r3, #0 + 8005cf0: d00e beq.n 8005d10 + 8005cf2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005cf6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 + 8005cfa: 2b00 cmp r3, #0 + 8005cfc: d008 beq.n 8005d10 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - 8005cb6: 687b ldr r3, [r7, #4] - 8005cb8: 681b ldr r3, [r3, #0] - 8005cba: f44f 1280 mov.w r2, #1048576 @ 0x100000 - 8005cbe: 621a str r2, [r3, #32] + 8005cfe: 687b ldr r3, [r7, #4] + 8005d00: 681b ldr r3, [r3, #0] + 8005d02: f44f 1280 mov.w r2, #1048576 @ 0x100000 + 8005d06: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); - 8005cc0: 6878 ldr r0, [r7, #4] - 8005cc2: f001 fbd9 bl 8007478 + 8005d08: 6878 ldr r0, [r7, #4] + 8005d0a: f001 fbd9 bl 80074c0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; - 8005cc6: e051 b.n 8005d6c + 8005d0e: e051 b.n 8005db4 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) - 8005cc8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005ccc: f003 0380 and.w r3, r3, #128 @ 0x80 - 8005cd0: 2b00 cmp r3, #0 - 8005cd2: d014 beq.n 8005cfe + 8005d10: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005d14: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005d18: 2b00 cmp r3, #0 + 8005d1a: d014 beq.n 8005d46 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) - 8005cd4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005cd8: f003 0380 and.w r3, r3, #128 @ 0x80 - 8005cdc: 2b00 cmp r3, #0 - 8005cde: d105 bne.n 8005cec + 8005d1c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005d20: f003 0380 and.w r3, r3, #128 @ 0x80 + 8005d24: 2b00 cmp r3, #0 + 8005d26: d105 bne.n 8005d34 || ((cr3its & USART_CR3_TXFTIE) != 0U))) - 8005ce0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc - 8005ce4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8005ce8: 2b00 cmp r3, #0 - 8005cea: d008 beq.n 8005cfe + 8005d28: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc + 8005d2c: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8005d30: 2b00 cmp r3, #0 + 8005d32: d008 beq.n 8005d46 { if (huart->TxISR != NULL) - 8005cec: 687b ldr r3, [r7, #4] - 8005cee: 6f9b ldr r3, [r3, #120] @ 0x78 - 8005cf0: 2b00 cmp r3, #0 - 8005cf2: d03a beq.n 8005d6a + 8005d34: 687b ldr r3, [r7, #4] + 8005d36: 6f9b ldr r3, [r3, #120] @ 0x78 + 8005d38: 2b00 cmp r3, #0 + 8005d3a: d03a beq.n 8005db2 { huart->TxISR(huart); - 8005cf4: 687b ldr r3, [r7, #4] - 8005cf6: 6f9b ldr r3, [r3, #120] @ 0x78 - 8005cf8: 6878 ldr r0, [r7, #4] - 8005cfa: 4798 blx r3 + 8005d3c: 687b ldr r3, [r7, #4] + 8005d3e: 6f9b ldr r3, [r3, #120] @ 0x78 + 8005d40: 6878 ldr r0, [r7, #4] + 8005d42: 4798 blx r3 } return; - 8005cfc: e035 b.n 8005d6a + 8005d44: e035 b.n 8005db2 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - 8005cfe: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005d02: f003 0340 and.w r3, r3, #64 @ 0x40 - 8005d06: 2b00 cmp r3, #0 - 8005d08: d009 beq.n 8005d1e - 8005d0a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005d0e: f003 0340 and.w r3, r3, #64 @ 0x40 - 8005d12: 2b00 cmp r3, #0 - 8005d14: d003 beq.n 8005d1e + 8005d46: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005d4a: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005d4e: 2b00 cmp r3, #0 + 8005d50: d009 beq.n 8005d66 + 8005d52: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005d56: f003 0340 and.w r3, r3, #64 @ 0x40 + 8005d5a: 2b00 cmp r3, #0 + 8005d5c: d003 beq.n 8005d66 { UART_EndTransmit_IT(huart); - 8005d16: 6878 ldr r0, [r7, #4] - 8005d18: f000 fe62 bl 80069e0 + 8005d5e: 6878 ldr r0, [r7, #4] + 8005d60: f000 fe62 bl 8006a28 return; - 8005d1c: e026 b.n 8005d6c + 8005d64: e026 b.n 8005db4 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) - 8005d1e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005d22: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8005d26: 2b00 cmp r3, #0 - 8005d28: d009 beq.n 8005d3e - 8005d2a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005d2e: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 - 8005d32: 2b00 cmp r3, #0 - 8005d34: d003 beq.n 8005d3e + 8005d66: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005d6a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8005d6e: 2b00 cmp r3, #0 + 8005d70: d009 beq.n 8005d86 + 8005d72: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005d76: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 + 8005d7a: 2b00 cmp r3, #0 + 8005d7c: d003 beq.n 8005d86 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); - 8005d36: 6878 ldr r0, [r7, #4] - 8005d38: f001 fbb2 bl 80074a0 + 8005d7e: 6878 ldr r0, [r7, #4] + 8005d80: f001 fbb2 bl 80074e8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; - 8005d3c: e016 b.n 8005d6c + 8005d84: e016 b.n 8005db4 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) - 8005d3e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 - 8005d42: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 - 8005d46: 2b00 cmp r3, #0 - 8005d48: d010 beq.n 8005d6c - 8005d4a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 - 8005d4e: 2b00 cmp r3, #0 - 8005d50: da0c bge.n 8005d6c + 8005d86: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 + 8005d8a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 + 8005d8e: 2b00 cmp r3, #0 + 8005d90: d010 beq.n 8005db4 + 8005d92: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 + 8005d96: 2b00 cmp r3, #0 + 8005d98: da0c bge.n 8005db4 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); - 8005d52: 6878 ldr r0, [r7, #4] - 8005d54: f001 fb9a bl 800748c + 8005d9a: 6878 ldr r0, [r7, #4] + 8005d9c: f001 fb9a bl 80074d4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; - 8005d58: e008 b.n 8005d6c + 8005da0: e008 b.n 8005db4 return; - 8005d5a: bf00 nop - 8005d5c: e006 b.n 8005d6c + 8005da2: bf00 nop + 8005da4: e006 b.n 8005db4 return; - 8005d5e: bf00 nop - 8005d60: e004 b.n 8005d6c + 8005da6: bf00 nop + 8005da8: e004 b.n 8005db4 return; - 8005d62: bf00 nop - 8005d64: e002 b.n 8005d6c + 8005daa: bf00 nop + 8005dac: e002 b.n 8005db4 return; - 8005d66: bf00 nop - 8005d68: e000 b.n 8005d6c + 8005dae: bf00 nop + 8005db0: e000 b.n 8005db4 return; - 8005d6a: bf00 nop + 8005db2: bf00 nop } } - 8005d6c: 37e8 adds r7, #232 @ 0xe8 - 8005d6e: 46bd mov sp, r7 - 8005d70: bd80 pop {r7, pc} - 8005d72: bf00 nop + 8005db4: 37e8 adds r7, #232 @ 0xe8 + 8005db6: 46bd mov sp, r7 + 8005db8: bd80 pop {r7, pc} + 8005dba: bf00 nop -08005d74 : +08005dbc : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { - 8005d74: b480 push {r7} - 8005d76: b083 sub sp, #12 - 8005d78: af00 add r7, sp, #0 - 8005d7a: 6078 str r0, [r7, #4] + 8005dbc: b480 push {r7} + 8005dbe: b083 sub sp, #12 + 8005dc0: af00 add r7, sp, #0 + 8005dc2: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } - 8005d7c: bf00 nop - 8005d7e: 370c adds r7, #12 - 8005d80: 46bd mov sp, r7 - 8005d82: f85d 7b04 ldr.w r7, [sp], #4 - 8005d86: 4770 bx lr + 8005dc4: bf00 nop + 8005dc6: 370c adds r7, #12 + 8005dc8: 46bd mov sp, r7 + 8005dca: f85d 7b04 ldr.w r7, [sp], #4 + 8005dce: 4770 bx lr -08005d88 : +08005dd0 : * @param Size Number of data available in application reception buffer (indicates a position in * reception buffer until which, data are available) * @retval None */ __weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { - 8005d88: b480 push {r7} - 8005d8a: b083 sub sp, #12 - 8005d8c: af00 add r7, sp, #0 - 8005d8e: 6078 str r0, [r7, #4] - 8005d90: 460b mov r3, r1 - 8005d92: 807b strh r3, [r7, #2] + 8005dd0: b480 push {r7} + 8005dd2: b083 sub sp, #12 + 8005dd4: af00 add r7, sp, #0 + 8005dd6: 6078 str r0, [r7, #4] + 8005dd8: 460b mov r3, r1 + 8005dda: 807b strh r3, [r7, #2] UNUSED(Size); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxEventCallback can be implemented in the user file. */ } - 8005d94: bf00 nop - 8005d96: 370c adds r7, #12 - 8005d98: 46bd mov sp, r7 - 8005d9a: f85d 7b04 ldr.w r7, [sp], #4 - 8005d9e: 4770 bx lr + 8005ddc: bf00 nop + 8005dde: 370c adds r7, #12 + 8005de0: 46bd mov sp, r7 + 8005de2: f85d 7b04 ldr.w r7, [sp], #4 + 8005de6: 4770 bx lr -08005da0 : +08005de8 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8005da0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 8005da4: b08c sub sp, #48 @ 0x30 - 8005da6: af00 add r7, sp, #0 - 8005da8: 6178 str r0, [r7, #20] + 8005de8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8005dec: b08c sub sp, #48 @ 0x30 + 8005dee: af00 add r7, sp, #0 + 8005df0: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8005daa: 2300 movs r3, #0 - 8005dac: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8005df2: 2300 movs r3, #0 + 8005df4: f887 302a strb.w r3, [r7, #42] @ 0x2a * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 8005db0: 697b ldr r3, [r7, #20] - 8005db2: 689a ldr r2, [r3, #8] - 8005db4: 697b ldr r3, [r7, #20] - 8005db6: 691b ldr r3, [r3, #16] - 8005db8: 431a orrs r2, r3 - 8005dba: 697b ldr r3, [r7, #20] - 8005dbc: 695b ldr r3, [r3, #20] - 8005dbe: 431a orrs r2, r3 - 8005dc0: 697b ldr r3, [r7, #20] - 8005dc2: 69db ldr r3, [r3, #28] - 8005dc4: 4313 orrs r3, r2 - 8005dc6: 62fb str r3, [r7, #44] @ 0x2c + 8005df8: 697b ldr r3, [r7, #20] + 8005dfa: 689a ldr r2, [r3, #8] + 8005dfc: 697b ldr r3, [r7, #20] + 8005dfe: 691b ldr r3, [r3, #16] + 8005e00: 431a orrs r2, r3 + 8005e02: 697b ldr r3, [r7, #20] + 8005e04: 695b ldr r3, [r3, #20] + 8005e06: 431a orrs r2, r3 + 8005e08: 697b ldr r3, [r7, #20] + 8005e0a: 69db ldr r3, [r3, #28] + 8005e0c: 4313 orrs r3, r2 + 8005e0e: 62fb str r3, [r7, #44] @ 0x2c MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 8005dc8: 697b ldr r3, [r7, #20] - 8005dca: 681b ldr r3, [r3, #0] - 8005dcc: 681a ldr r2, [r3, #0] - 8005dce: 4bab ldr r3, [pc, #684] @ (800607c ) - 8005dd0: 4013 ands r3, r2 - 8005dd2: 697a ldr r2, [r7, #20] - 8005dd4: 6812 ldr r2, [r2, #0] - 8005dd6: 6af9 ldr r1, [r7, #44] @ 0x2c - 8005dd8: 430b orrs r3, r1 - 8005dda: 6013 str r3, [r2, #0] + 8005e10: 697b ldr r3, [r7, #20] + 8005e12: 681b ldr r3, [r3, #0] + 8005e14: 681a ldr r2, [r3, #0] + 8005e16: 4bab ldr r3, [pc, #684] @ (80060c4 ) + 8005e18: 4013 ands r3, r2 + 8005e1a: 697a ldr r2, [r7, #20] + 8005e1c: 6812 ldr r2, [r2, #0] + 8005e1e: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005e20: 430b orrs r3, r1 + 8005e22: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 8005ddc: 697b ldr r3, [r7, #20] - 8005dde: 681b ldr r3, [r3, #0] - 8005de0: 685b ldr r3, [r3, #4] - 8005de2: f423 5140 bic.w r1, r3, #12288 @ 0x3000 - 8005de6: 697b ldr r3, [r7, #20] - 8005de8: 68da ldr r2, [r3, #12] - 8005dea: 697b ldr r3, [r7, #20] - 8005dec: 681b ldr r3, [r3, #0] - 8005dee: 430a orrs r2, r1 - 8005df0: 605a str r2, [r3, #4] + 8005e24: 697b ldr r3, [r7, #20] + 8005e26: 681b ldr r3, [r3, #0] + 8005e28: 685b ldr r3, [r3, #4] + 8005e2a: f423 5140 bic.w r1, r3, #12288 @ 0x3000 + 8005e2e: 697b ldr r3, [r7, #20] + 8005e30: 68da ldr r2, [r3, #12] + 8005e32: 697b ldr r3, [r7, #20] + 8005e34: 681b ldr r3, [r3, #0] + 8005e36: 430a orrs r2, r1 + 8005e38: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 8005df2: 697b ldr r3, [r7, #20] - 8005df4: 699b ldr r3, [r3, #24] - 8005df6: 62fb str r3, [r7, #44] @ 0x2c + 8005e3a: 697b ldr r3, [r7, #20] + 8005e3c: 699b ldr r3, [r3, #24] + 8005e3e: 62fb str r3, [r7, #44] @ 0x2c if (!(UART_INSTANCE_LOWPOWER(huart))) - 8005df8: 697b ldr r3, [r7, #20] - 8005dfa: 681b ldr r3, [r3, #0] - 8005dfc: 4aa0 ldr r2, [pc, #640] @ (8006080 ) - 8005dfe: 4293 cmp r3, r2 - 8005e00: d004 beq.n 8005e0c + 8005e40: 697b ldr r3, [r7, #20] + 8005e42: 681b ldr r3, [r3, #0] + 8005e44: 4aa0 ldr r2, [pc, #640] @ (80060c8 ) + 8005e46: 4293 cmp r3, r2 + 8005e48: d004 beq.n 8005e54 { tmpreg |= huart->Init.OneBitSampling; - 8005e02: 697b ldr r3, [r7, #20] - 8005e04: 6a1b ldr r3, [r3, #32] - 8005e06: 6afa ldr r2, [r7, #44] @ 0x2c - 8005e08: 4313 orrs r3, r2 - 8005e0a: 62fb str r3, [r7, #44] @ 0x2c + 8005e4a: 697b ldr r3, [r7, #20] + 8005e4c: 6a1b ldr r3, [r3, #32] + 8005e4e: 6afa ldr r2, [r7, #44] @ 0x2c + 8005e50: 4313 orrs r3, r2 + 8005e52: 62fb str r3, [r7, #44] @ 0x2c } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 8005e0c: 697b ldr r3, [r7, #20] - 8005e0e: 681b ldr r3, [r3, #0] - 8005e10: 689b ldr r3, [r3, #8] - 8005e12: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 - 8005e16: f423 6330 bic.w r3, r3, #2816 @ 0xb00 - 8005e1a: 697a ldr r2, [r7, #20] - 8005e1c: 6812 ldr r2, [r2, #0] - 8005e1e: 6af9 ldr r1, [r7, #44] @ 0x2c - 8005e20: 430b orrs r3, r1 - 8005e22: 6093 str r3, [r2, #8] + 8005e54: 697b ldr r3, [r7, #20] + 8005e56: 681b ldr r3, [r3, #0] + 8005e58: 689b ldr r3, [r3, #8] + 8005e5a: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000 + 8005e5e: f423 6330 bic.w r3, r3, #2816 @ 0xb00 + 8005e62: 697a ldr r2, [r7, #20] + 8005e64: 6812 ldr r2, [r2, #0] + 8005e66: 6af9 ldr r1, [r7, #44] @ 0x2c + 8005e68: 430b orrs r3, r1 + 8005e6a: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); - 8005e24: 697b ldr r3, [r7, #20] - 8005e26: 681b ldr r3, [r3, #0] - 8005e28: 6adb ldr r3, [r3, #44] @ 0x2c - 8005e2a: f023 010f bic.w r1, r3, #15 - 8005e2e: 697b ldr r3, [r7, #20] - 8005e30: 6a5a ldr r2, [r3, #36] @ 0x24 - 8005e32: 697b ldr r3, [r7, #20] - 8005e34: 681b ldr r3, [r3, #0] - 8005e36: 430a orrs r2, r1 - 8005e38: 62da str r2, [r3, #44] @ 0x2c + 8005e6c: 697b ldr r3, [r7, #20] + 8005e6e: 681b ldr r3, [r3, #0] + 8005e70: 6adb ldr r3, [r3, #44] @ 0x2c + 8005e72: f023 010f bic.w r1, r3, #15 + 8005e76: 697b ldr r3, [r7, #20] + 8005e78: 6a5a ldr r2, [r3, #36] @ 0x24 + 8005e7a: 697b ldr r3, [r7, #20] + 8005e7c: 681b ldr r3, [r3, #0] + 8005e7e: 430a orrs r2, r1 + 8005e80: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 8005e3a: 697b ldr r3, [r7, #20] - 8005e3c: 681b ldr r3, [r3, #0] - 8005e3e: 4a91 ldr r2, [pc, #580] @ (8006084 ) - 8005e40: 4293 cmp r3, r2 - 8005e42: d125 bne.n 8005e90 - 8005e44: 4b90 ldr r3, [pc, #576] @ (8006088 ) - 8005e46: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8005e4a: f003 0303 and.w r3, r3, #3 - 8005e4e: 2b03 cmp r3, #3 - 8005e50: d81a bhi.n 8005e88 - 8005e52: a201 add r2, pc, #4 @ (adr r2, 8005e58 ) - 8005e54: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8005e58: 08005e69 .word 0x08005e69 - 8005e5c: 08005e79 .word 0x08005e79 - 8005e60: 08005e71 .word 0x08005e71 - 8005e64: 08005e81 .word 0x08005e81 - 8005e68: 2301 movs r3, #1 - 8005e6a: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005e6e: e0d6 b.n 800601e - 8005e70: 2302 movs r3, #2 - 8005e72: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005e76: e0d2 b.n 800601e - 8005e78: 2304 movs r3, #4 - 8005e7a: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005e7e: e0ce b.n 800601e - 8005e80: 2308 movs r3, #8 - 8005e82: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005e86: e0ca b.n 800601e - 8005e88: 2310 movs r3, #16 - 8005e8a: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005e8e: e0c6 b.n 800601e - 8005e90: 697b ldr r3, [r7, #20] - 8005e92: 681b ldr r3, [r3, #0] - 8005e94: 4a7d ldr r2, [pc, #500] @ (800608c ) - 8005e96: 4293 cmp r3, r2 - 8005e98: d138 bne.n 8005f0c - 8005e9a: 4b7b ldr r3, [pc, #492] @ (8006088 ) - 8005e9c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8005ea0: f003 030c and.w r3, r3, #12 - 8005ea4: 2b0c cmp r3, #12 - 8005ea6: d82d bhi.n 8005f04 - 8005ea8: a201 add r2, pc, #4 @ (adr r2, 8005eb0 ) - 8005eaa: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8005eae: bf00 nop - 8005eb0: 08005ee5 .word 0x08005ee5 - 8005eb4: 08005f05 .word 0x08005f05 - 8005eb8: 08005f05 .word 0x08005f05 - 8005ebc: 08005f05 .word 0x08005f05 - 8005ec0: 08005ef5 .word 0x08005ef5 - 8005ec4: 08005f05 .word 0x08005f05 - 8005ec8: 08005f05 .word 0x08005f05 - 8005ecc: 08005f05 .word 0x08005f05 - 8005ed0: 08005eed .word 0x08005eed - 8005ed4: 08005f05 .word 0x08005f05 - 8005ed8: 08005f05 .word 0x08005f05 - 8005edc: 08005f05 .word 0x08005f05 - 8005ee0: 08005efd .word 0x08005efd - 8005ee4: 2300 movs r3, #0 - 8005ee6: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005eea: e098 b.n 800601e - 8005eec: 2302 movs r3, #2 - 8005eee: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005ef2: e094 b.n 800601e - 8005ef4: 2304 movs r3, #4 - 8005ef6: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005efa: e090 b.n 800601e - 8005efc: 2308 movs r3, #8 - 8005efe: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f02: e08c b.n 800601e - 8005f04: 2310 movs r3, #16 - 8005f06: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f0a: e088 b.n 800601e - 8005f0c: 697b ldr r3, [r7, #20] - 8005f0e: 681b ldr r3, [r3, #0] - 8005f10: 4a5f ldr r2, [pc, #380] @ (8006090 ) - 8005f12: 4293 cmp r3, r2 - 8005f14: d125 bne.n 8005f62 - 8005f16: 4b5c ldr r3, [pc, #368] @ (8006088 ) - 8005f18: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8005f1c: f003 0330 and.w r3, r3, #48 @ 0x30 - 8005f20: 2b30 cmp r3, #48 @ 0x30 - 8005f22: d016 beq.n 8005f52 - 8005f24: 2b30 cmp r3, #48 @ 0x30 - 8005f26: d818 bhi.n 8005f5a - 8005f28: 2b20 cmp r3, #32 - 8005f2a: d00a beq.n 8005f42 - 8005f2c: 2b20 cmp r3, #32 - 8005f2e: d814 bhi.n 8005f5a - 8005f30: 2b00 cmp r3, #0 - 8005f32: d002 beq.n 8005f3a - 8005f34: 2b10 cmp r3, #16 - 8005f36: d008 beq.n 8005f4a - 8005f38: e00f b.n 8005f5a - 8005f3a: 2300 movs r3, #0 - 8005f3c: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f40: e06d b.n 800601e - 8005f42: 2302 movs r3, #2 - 8005f44: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f48: e069 b.n 800601e - 8005f4a: 2304 movs r3, #4 - 8005f4c: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f50: e065 b.n 800601e - 8005f52: 2308 movs r3, #8 - 8005f54: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f58: e061 b.n 800601e - 8005f5a: 2310 movs r3, #16 - 8005f5c: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f60: e05d b.n 800601e - 8005f62: 697b ldr r3, [r7, #20] - 8005f64: 681b ldr r3, [r3, #0] - 8005f66: 4a4b ldr r2, [pc, #300] @ (8006094 ) - 8005f68: 4293 cmp r3, r2 - 8005f6a: d125 bne.n 8005fb8 - 8005f6c: 4b46 ldr r3, [pc, #280] @ (8006088 ) - 8005f6e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8005f72: f003 03c0 and.w r3, r3, #192 @ 0xc0 - 8005f76: 2bc0 cmp r3, #192 @ 0xc0 - 8005f78: d016 beq.n 8005fa8 - 8005f7a: 2bc0 cmp r3, #192 @ 0xc0 - 8005f7c: d818 bhi.n 8005fb0 - 8005f7e: 2b80 cmp r3, #128 @ 0x80 - 8005f80: d00a beq.n 8005f98 - 8005f82: 2b80 cmp r3, #128 @ 0x80 - 8005f84: d814 bhi.n 8005fb0 - 8005f86: 2b00 cmp r3, #0 - 8005f88: d002 beq.n 8005f90 - 8005f8a: 2b40 cmp r3, #64 @ 0x40 - 8005f8c: d008 beq.n 8005fa0 - 8005f8e: e00f b.n 8005fb0 - 8005f90: 2300 movs r3, #0 - 8005f92: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f96: e042 b.n 800601e - 8005f98: 2302 movs r3, #2 - 8005f9a: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005f9e: e03e b.n 800601e - 8005fa0: 2304 movs r3, #4 - 8005fa2: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005fa6: e03a b.n 800601e - 8005fa8: 2308 movs r3, #8 - 8005faa: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005fae: e036 b.n 800601e - 8005fb0: 2310 movs r3, #16 - 8005fb2: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005fb6: e032 b.n 800601e - 8005fb8: 697b ldr r3, [r7, #20] - 8005fba: 681b ldr r3, [r3, #0] - 8005fbc: 4a30 ldr r2, [pc, #192] @ (8006080 ) - 8005fbe: 4293 cmp r3, r2 - 8005fc0: d12a bne.n 8006018 - 8005fc2: 4b31 ldr r3, [pc, #196] @ (8006088 ) - 8005fc4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 - 8005fc8: f403 6340 and.w r3, r3, #3072 @ 0xc00 - 8005fcc: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 - 8005fd0: d01a beq.n 8006008 - 8005fd2: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 - 8005fd6: d81b bhi.n 8006010 - 8005fd8: f5b3 6f00 cmp.w r3, #2048 @ 0x800 - 8005fdc: d00c beq.n 8005ff8 - 8005fde: f5b3 6f00 cmp.w r3, #2048 @ 0x800 - 8005fe2: d815 bhi.n 8006010 - 8005fe4: 2b00 cmp r3, #0 - 8005fe6: d003 beq.n 8005ff0 - 8005fe8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 - 8005fec: d008 beq.n 8006000 - 8005fee: e00f b.n 8006010 - 8005ff0: 2300 movs r3, #0 + 8005e82: 697b ldr r3, [r7, #20] + 8005e84: 681b ldr r3, [r3, #0] + 8005e86: 4a91 ldr r2, [pc, #580] @ (80060cc ) + 8005e88: 4293 cmp r3, r2 + 8005e8a: d125 bne.n 8005ed8 + 8005e8c: 4b90 ldr r3, [pc, #576] @ (80060d0 ) + 8005e8e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005e92: f003 0303 and.w r3, r3, #3 + 8005e96: 2b03 cmp r3, #3 + 8005e98: d81a bhi.n 8005ed0 + 8005e9a: a201 add r2, pc, #4 @ (adr r2, 8005ea0 ) + 8005e9c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005ea0: 08005eb1 .word 0x08005eb1 + 8005ea4: 08005ec1 .word 0x08005ec1 + 8005ea8: 08005eb9 .word 0x08005eb9 + 8005eac: 08005ec9 .word 0x08005ec9 + 8005eb0: 2301 movs r3, #1 + 8005eb2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005eb6: e0d6 b.n 8006066 + 8005eb8: 2302 movs r3, #2 + 8005eba: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ebe: e0d2 b.n 8006066 + 8005ec0: 2304 movs r3, #4 + 8005ec2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ec6: e0ce b.n 8006066 + 8005ec8: 2308 movs r3, #8 + 8005eca: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ece: e0ca b.n 8006066 + 8005ed0: 2310 movs r3, #16 + 8005ed2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ed6: e0c6 b.n 8006066 + 8005ed8: 697b ldr r3, [r7, #20] + 8005eda: 681b ldr r3, [r3, #0] + 8005edc: 4a7d ldr r2, [pc, #500] @ (80060d4 ) + 8005ede: 4293 cmp r3, r2 + 8005ee0: d138 bne.n 8005f54 + 8005ee2: 4b7b ldr r3, [pc, #492] @ (80060d0 ) + 8005ee4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005ee8: f003 030c and.w r3, r3, #12 + 8005eec: 2b0c cmp r3, #12 + 8005eee: d82d bhi.n 8005f4c + 8005ef0: a201 add r2, pc, #4 @ (adr r2, 8005ef8 ) + 8005ef2: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005ef6: bf00 nop + 8005ef8: 08005f2d .word 0x08005f2d + 8005efc: 08005f4d .word 0x08005f4d + 8005f00: 08005f4d .word 0x08005f4d + 8005f04: 08005f4d .word 0x08005f4d + 8005f08: 08005f3d .word 0x08005f3d + 8005f0c: 08005f4d .word 0x08005f4d + 8005f10: 08005f4d .word 0x08005f4d + 8005f14: 08005f4d .word 0x08005f4d + 8005f18: 08005f35 .word 0x08005f35 + 8005f1c: 08005f4d .word 0x08005f4d + 8005f20: 08005f4d .word 0x08005f4d + 8005f24: 08005f4d .word 0x08005f4d + 8005f28: 08005f45 .word 0x08005f45 + 8005f2c: 2300 movs r3, #0 + 8005f2e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f32: e098 b.n 8006066 + 8005f34: 2302 movs r3, #2 + 8005f36: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f3a: e094 b.n 8006066 + 8005f3c: 2304 movs r3, #4 + 8005f3e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f42: e090 b.n 8006066 + 8005f44: 2308 movs r3, #8 + 8005f46: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f4a: e08c b.n 8006066 + 8005f4c: 2310 movs r3, #16 + 8005f4e: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f52: e088 b.n 8006066 + 8005f54: 697b ldr r3, [r7, #20] + 8005f56: 681b ldr r3, [r3, #0] + 8005f58: 4a5f ldr r2, [pc, #380] @ (80060d8 ) + 8005f5a: 4293 cmp r3, r2 + 8005f5c: d125 bne.n 8005faa + 8005f5e: 4b5c ldr r3, [pc, #368] @ (80060d0 ) + 8005f60: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005f64: f003 0330 and.w r3, r3, #48 @ 0x30 + 8005f68: 2b30 cmp r3, #48 @ 0x30 + 8005f6a: d016 beq.n 8005f9a + 8005f6c: 2b30 cmp r3, #48 @ 0x30 + 8005f6e: d818 bhi.n 8005fa2 + 8005f70: 2b20 cmp r3, #32 + 8005f72: d00a beq.n 8005f8a + 8005f74: 2b20 cmp r3, #32 + 8005f76: d814 bhi.n 8005fa2 + 8005f78: 2b00 cmp r3, #0 + 8005f7a: d002 beq.n 8005f82 + 8005f7c: 2b10 cmp r3, #16 + 8005f7e: d008 beq.n 8005f92 + 8005f80: e00f b.n 8005fa2 + 8005f82: 2300 movs r3, #0 + 8005f84: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f88: e06d b.n 8006066 + 8005f8a: 2302 movs r3, #2 + 8005f8c: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f90: e069 b.n 8006066 + 8005f92: 2304 movs r3, #4 + 8005f94: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005f98: e065 b.n 8006066 + 8005f9a: 2308 movs r3, #8 + 8005f9c: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005fa0: e061 b.n 8006066 + 8005fa2: 2310 movs r3, #16 + 8005fa4: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005fa8: e05d b.n 8006066 + 8005faa: 697b ldr r3, [r7, #20] + 8005fac: 681b ldr r3, [r3, #0] + 8005fae: 4a4b ldr r2, [pc, #300] @ (80060dc ) + 8005fb0: 4293 cmp r3, r2 + 8005fb2: d125 bne.n 8006000 + 8005fb4: 4b46 ldr r3, [pc, #280] @ (80060d0 ) + 8005fb6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8005fba: f003 03c0 and.w r3, r3, #192 @ 0xc0 + 8005fbe: 2bc0 cmp r3, #192 @ 0xc0 + 8005fc0: d016 beq.n 8005ff0 + 8005fc2: 2bc0 cmp r3, #192 @ 0xc0 + 8005fc4: d818 bhi.n 8005ff8 + 8005fc6: 2b80 cmp r3, #128 @ 0x80 + 8005fc8: d00a beq.n 8005fe0 + 8005fca: 2b80 cmp r3, #128 @ 0x80 + 8005fcc: d814 bhi.n 8005ff8 + 8005fce: 2b00 cmp r3, #0 + 8005fd0: d002 beq.n 8005fd8 + 8005fd2: 2b40 cmp r3, #64 @ 0x40 + 8005fd4: d008 beq.n 8005fe8 + 8005fd6: e00f b.n 8005ff8 + 8005fd8: 2300 movs r3, #0 + 8005fda: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005fde: e042 b.n 8006066 + 8005fe0: 2302 movs r3, #2 + 8005fe2: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005fe6: e03e b.n 8006066 + 8005fe8: 2304 movs r3, #4 + 8005fea: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005fee: e03a b.n 8006066 + 8005ff0: 2308 movs r3, #8 8005ff2: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005ff6: e012 b.n 800601e - 8005ff8: 2302 movs r3, #2 + 8005ff6: e036 b.n 8006066 + 8005ff8: 2310 movs r3, #16 8005ffa: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8005ffe: e00e b.n 800601e - 8006000: 2304 movs r3, #4 - 8006002: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8006006: e00a b.n 800601e - 8006008: 2308 movs r3, #8 - 800600a: f887 302b strb.w r3, [r7, #43] @ 0x2b - 800600e: e006 b.n 800601e - 8006010: 2310 movs r3, #16 - 8006012: f887 302b strb.w r3, [r7, #43] @ 0x2b - 8006016: e002 b.n 800601e - 8006018: 2310 movs r3, #16 - 800601a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8005ffe: e032 b.n 8006066 + 8006000: 697b ldr r3, [r7, #20] + 8006002: 681b ldr r3, [r3, #0] + 8006004: 4a30 ldr r2, [pc, #192] @ (80060c8 ) + 8006006: 4293 cmp r3, r2 + 8006008: d12a bne.n 8006060 + 800600a: 4b31 ldr r3, [pc, #196] @ (80060d0 ) + 800600c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 + 8006010: f403 6340 and.w r3, r3, #3072 @ 0xc00 + 8006014: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 8006018: d01a beq.n 8006050 + 800601a: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 + 800601e: d81b bhi.n 8006058 + 8006020: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 8006024: d00c beq.n 8006040 + 8006026: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 800602a: d815 bhi.n 8006058 + 800602c: 2b00 cmp r3, #0 + 800602e: d003 beq.n 8006038 + 8006030: f5b3 6f80 cmp.w r3, #1024 @ 0x400 + 8006034: d008 beq.n 8006048 + 8006036: e00f b.n 8006058 + 8006038: 2300 movs r3, #0 + 800603a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 800603e: e012 b.n 8006066 + 8006040: 2302 movs r3, #2 + 8006042: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8006046: e00e b.n 8006066 + 8006048: 2304 movs r3, #4 + 800604a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 800604e: e00a b.n 8006066 + 8006050: 2308 movs r3, #8 + 8006052: f887 302b strb.w r3, [r7, #43] @ 0x2b + 8006056: e006 b.n 8006066 + 8006058: 2310 movs r3, #16 + 800605a: f887 302b strb.w r3, [r7, #43] @ 0x2b + 800605e: e002 b.n 8006066 + 8006060: 2310 movs r3, #16 + 8006062: f887 302b strb.w r3, [r7, #43] @ 0x2b /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) - 800601e: 697b ldr r3, [r7, #20] - 8006020: 681b ldr r3, [r3, #0] - 8006022: 4a17 ldr r2, [pc, #92] @ (8006080 ) - 8006024: 4293 cmp r3, r2 - 8006026: f040 80a8 bne.w 800617a + 8006066: 697b ldr r3, [r7, #20] + 8006068: 681b ldr r3, [r3, #0] + 800606a: 4a17 ldr r2, [pc, #92] @ (80060c8 ) + 800606c: 4293 cmp r3, r2 + 800606e: f040 80a8 bne.w 80061c2 { /* Retrieve frequency clock */ switch (clocksource) - 800602a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b - 800602e: 2b08 cmp r3, #8 - 8006030: d834 bhi.n 800609c - 8006032: a201 add r2, pc, #4 @ (adr r2, 8006038 ) - 8006034: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8006038: 0800605d .word 0x0800605d - 800603c: 0800609d .word 0x0800609d - 8006040: 08006065 .word 0x08006065 - 8006044: 0800609d .word 0x0800609d - 8006048: 0800606b .word 0x0800606b - 800604c: 0800609d .word 0x0800609d - 8006050: 0800609d .word 0x0800609d - 8006054: 0800609d .word 0x0800609d - 8006058: 08006073 .word 0x08006073 + 8006072: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 8006076: 2b08 cmp r3, #8 + 8006078: d834 bhi.n 80060e4 + 800607a: a201 add r2, pc, #4 @ (adr r2, 8006080 ) + 800607c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006080: 080060a5 .word 0x080060a5 + 8006084: 080060e5 .word 0x080060e5 + 8006088: 080060ad .word 0x080060ad + 800608c: 080060e5 .word 0x080060e5 + 8006090: 080060b3 .word 0x080060b3 + 8006094: 080060e5 .word 0x080060e5 + 8006098: 080060e5 .word 0x080060e5 + 800609c: 080060e5 .word 0x080060e5 + 80060a0: 080060bb .word 0x080060bb { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 800605c: f7fe faea bl 8004634 - 8006060: 6278 str r0, [r7, #36] @ 0x24 + 80060a4: f7fe faea bl 800467c + 80060a8: 6278 str r0, [r7, #36] @ 0x24 break; - 8006062: e021 b.n 80060a8 + 80060aa: e021 b.n 80060f0 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8006064: 4b0c ldr r3, [pc, #48] @ (8006098 ) - 8006066: 627b str r3, [r7, #36] @ 0x24 + 80060ac: 4b0c ldr r3, [pc, #48] @ (80060e0 ) + 80060ae: 627b str r3, [r7, #36] @ 0x24 break; - 8006068: e01e b.n 80060a8 + 80060b0: e01e b.n 80060f0 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 800606a: f7fe fa75 bl 8004558 - 800606e: 6278 str r0, [r7, #36] @ 0x24 + 80060b2: f7fe fa75 bl 80045a0 + 80060b6: 6278 str r0, [r7, #36] @ 0x24 break; - 8006070: e01a b.n 80060a8 + 80060b8: e01a b.n 80060f0 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8006072: f44f 4300 mov.w r3, #32768 @ 0x8000 - 8006076: 627b str r3, [r7, #36] @ 0x24 + 80060ba: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80060be: 627b str r3, [r7, #36] @ 0x24 break; - 8006078: e016 b.n 80060a8 - 800607a: bf00 nop - 800607c: cfff69f3 .word 0xcfff69f3 - 8006080: 40008000 .word 0x40008000 - 8006084: 40013800 .word 0x40013800 - 8006088: 40021000 .word 0x40021000 - 800608c: 40004400 .word 0x40004400 - 8006090: 40004800 .word 0x40004800 - 8006094: 40004c00 .word 0x40004c00 - 8006098: 00f42400 .word 0x00f42400 + 80060c0: e016 b.n 80060f0 + 80060c2: bf00 nop + 80060c4: cfff69f3 .word 0xcfff69f3 + 80060c8: 40008000 .word 0x40008000 + 80060cc: 40013800 .word 0x40013800 + 80060d0: 40021000 .word 0x40021000 + 80060d4: 40004400 .word 0x40004400 + 80060d8: 40004800 .word 0x40004800 + 80060dc: 40004c00 .word 0x40004c00 + 80060e0: 00f42400 .word 0x00f42400 default: pclk = 0U; - 800609c: 2300 movs r3, #0 - 800609e: 627b str r3, [r7, #36] @ 0x24 + 80060e4: 2300 movs r3, #0 + 80060e6: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; - 80060a0: 2301 movs r3, #1 - 80060a2: f887 302a strb.w r3, [r7, #42] @ 0x2a + 80060e8: 2301 movs r3, #1 + 80060ea: f887 302a strb.w r3, [r7, #42] @ 0x2a break; - 80060a6: bf00 nop + 80060ee: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) - 80060a8: 6a7b ldr r3, [r7, #36] @ 0x24 - 80060aa: 2b00 cmp r3, #0 - 80060ac: f000 812a beq.w 8006304 + 80060f0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80060f2: 2b00 cmp r3, #0 + 80060f4: f000 812a beq.w 800634c { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); - 80060b0: 697b ldr r3, [r7, #20] - 80060b2: 6a5b ldr r3, [r3, #36] @ 0x24 - 80060b4: 4a9e ldr r2, [pc, #632] @ (8006330 ) - 80060b6: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 80060ba: 461a mov r2, r3 - 80060bc: 6a7b ldr r3, [r7, #36] @ 0x24 - 80060be: fbb3 f3f2 udiv r3, r3, r2 - 80060c2: 61bb str r3, [r7, #24] + 80060f8: 697b ldr r3, [r7, #20] + 80060fa: 6a5b ldr r3, [r3, #36] @ 0x24 + 80060fc: 4a9e ldr r2, [pc, #632] @ (8006378 ) + 80060fe: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8006102: 461a mov r2, r3 + 8006104: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006106: fbb3 f3f2 udiv r3, r3, r2 + 800610a: 61bb str r3, [r7, #24] /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || - 80060c4: 697b ldr r3, [r7, #20] - 80060c6: 685a ldr r2, [r3, #4] - 80060c8: 4613 mov r3, r2 - 80060ca: 005b lsls r3, r3, #1 - 80060cc: 4413 add r3, r2 - 80060ce: 69ba ldr r2, [r7, #24] - 80060d0: 429a cmp r2, r3 - 80060d2: d305 bcc.n 80060e0 + 800610c: 697b ldr r3, [r7, #20] + 800610e: 685a ldr r2, [r3, #4] + 8006110: 4613 mov r3, r2 + 8006112: 005b lsls r3, r3, #1 + 8006114: 4413 add r3, r2 + 8006116: 69ba ldr r2, [r7, #24] + 8006118: 429a cmp r2, r3 + 800611a: d305 bcc.n 8006128 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) - 80060d4: 697b ldr r3, [r7, #20] - 80060d6: 685b ldr r3, [r3, #4] - 80060d8: 031b lsls r3, r3, #12 + 800611c: 697b ldr r3, [r7, #20] + 800611e: 685b ldr r3, [r3, #4] + 8006120: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || - 80060da: 69ba ldr r2, [r7, #24] - 80060dc: 429a cmp r2, r3 - 80060de: d903 bls.n 80060e8 + 8006122: 69ba ldr r2, [r7, #24] + 8006124: 429a cmp r2, r3 + 8006126: d903 bls.n 8006130 { ret = HAL_ERROR; - 80060e0: 2301 movs r3, #1 - 80060e2: f887 302a strb.w r3, [r7, #42] @ 0x2a - 80060e6: e10d b.n 8006304 + 8006128: 2301 movs r3, #1 + 800612a: f887 302a strb.w r3, [r7, #42] @ 0x2a + 800612e: e10d b.n 800634c } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 80060e8: 6a7b ldr r3, [r7, #36] @ 0x24 - 80060ea: 2200 movs r2, #0 - 80060ec: 60bb str r3, [r7, #8] - 80060ee: 60fa str r2, [r7, #12] - 80060f0: 697b ldr r3, [r7, #20] - 80060f2: 6a5b ldr r3, [r3, #36] @ 0x24 - 80060f4: 4a8e ldr r2, [pc, #568] @ (8006330 ) - 80060f6: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 80060fa: b29b uxth r3, r3 - 80060fc: 2200 movs r2, #0 - 80060fe: 603b str r3, [r7, #0] - 8006100: 607a str r2, [r7, #4] - 8006102: e9d7 2300 ldrd r2, r3, [r7] - 8006106: e9d7 0102 ldrd r0, r1, [r7, #8] - 800610a: f7fa fb8b bl 8000824 <__aeabi_uldivmod> - 800610e: 4602 mov r2, r0 - 8006110: 460b mov r3, r1 - 8006112: 4610 mov r0, r2 - 8006114: 4619 mov r1, r3 - 8006116: f04f 0200 mov.w r2, #0 - 800611a: f04f 0300 mov.w r3, #0 - 800611e: 020b lsls r3, r1, #8 - 8006120: ea43 6310 orr.w r3, r3, r0, lsr #24 - 8006124: 0202 lsls r2, r0, #8 - 8006126: 6979 ldr r1, [r7, #20] - 8006128: 6849 ldr r1, [r1, #4] - 800612a: 0849 lsrs r1, r1, #1 - 800612c: 2000 movs r0, #0 - 800612e: 460c mov r4, r1 - 8006130: 4605 mov r5, r0 - 8006132: eb12 0804 adds.w r8, r2, r4 - 8006136: eb43 0905 adc.w r9, r3, r5 - 800613a: 697b ldr r3, [r7, #20] - 800613c: 685b ldr r3, [r3, #4] - 800613e: 2200 movs r2, #0 - 8006140: 469a mov sl, r3 - 8006142: 4693 mov fp, r2 - 8006144: 4652 mov r2, sl - 8006146: 465b mov r3, fp - 8006148: 4640 mov r0, r8 - 800614a: 4649 mov r1, r9 - 800614c: f7fa fb6a bl 8000824 <__aeabi_uldivmod> - 8006150: 4602 mov r2, r0 - 8006152: 460b mov r3, r1 - 8006154: 4613 mov r3, r2 - 8006156: 623b str r3, [r7, #32] + 8006130: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006132: 2200 movs r2, #0 + 8006134: 60bb str r3, [r7, #8] + 8006136: 60fa str r2, [r7, #12] + 8006138: 697b ldr r3, [r7, #20] + 800613a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800613c: 4a8e ldr r2, [pc, #568] @ (8006378 ) + 800613e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8006142: b29b uxth r3, r3 + 8006144: 2200 movs r2, #0 + 8006146: 603b str r3, [r7, #0] + 8006148: 607a str r2, [r7, #4] + 800614a: e9d7 2300 ldrd r2, r3, [r7] + 800614e: e9d7 0102 ldrd r0, r1, [r7, #8] + 8006152: f7fa fb67 bl 8000824 <__aeabi_uldivmod> + 8006156: 4602 mov r2, r0 + 8006158: 460b mov r3, r1 + 800615a: 4610 mov r0, r2 + 800615c: 4619 mov r1, r3 + 800615e: f04f 0200 mov.w r2, #0 + 8006162: f04f 0300 mov.w r3, #0 + 8006166: 020b lsls r3, r1, #8 + 8006168: ea43 6310 orr.w r3, r3, r0, lsr #24 + 800616c: 0202 lsls r2, r0, #8 + 800616e: 6979 ldr r1, [r7, #20] + 8006170: 6849 ldr r1, [r1, #4] + 8006172: 0849 lsrs r1, r1, #1 + 8006174: 2000 movs r0, #0 + 8006176: 460c mov r4, r1 + 8006178: 4605 mov r5, r0 + 800617a: eb12 0804 adds.w r8, r2, r4 + 800617e: eb43 0905 adc.w r9, r3, r5 + 8006182: 697b ldr r3, [r7, #20] + 8006184: 685b ldr r3, [r3, #4] + 8006186: 2200 movs r2, #0 + 8006188: 469a mov sl, r3 + 800618a: 4693 mov fp, r2 + 800618c: 4652 mov r2, sl + 800618e: 465b mov r3, fp + 8006190: 4640 mov r0, r8 + 8006192: 4649 mov r1, r9 + 8006194: f7fa fb46 bl 8000824 <__aeabi_uldivmod> + 8006198: 4602 mov r2, r0 + 800619a: 460b mov r3, r1 + 800619c: 4613 mov r3, r2 + 800619e: 623b str r3, [r7, #32] if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - 8006158: 6a3b ldr r3, [r7, #32] - 800615a: f5b3 7f40 cmp.w r3, #768 @ 0x300 - 800615e: d308 bcc.n 8006172 - 8006160: 6a3b ldr r3, [r7, #32] - 8006162: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 8006166: d204 bcs.n 8006172 + 80061a0: 6a3b ldr r3, [r7, #32] + 80061a2: f5b3 7f40 cmp.w r3, #768 @ 0x300 + 80061a6: d308 bcc.n 80061ba + 80061a8: 6a3b ldr r3, [r7, #32] + 80061aa: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 80061ae: d204 bcs.n 80061ba { huart->Instance->BRR = usartdiv; - 8006168: 697b ldr r3, [r7, #20] - 800616a: 681b ldr r3, [r3, #0] - 800616c: 6a3a ldr r2, [r7, #32] - 800616e: 60da str r2, [r3, #12] - 8006170: e0c8 b.n 8006304 + 80061b0: 697b ldr r3, [r7, #20] + 80061b2: 681b ldr r3, [r3, #0] + 80061b4: 6a3a ldr r2, [r7, #32] + 80061b6: 60da str r2, [r3, #12] + 80061b8: e0c8 b.n 800634c } else { ret = HAL_ERROR; - 8006172: 2301 movs r3, #1 - 8006174: f887 302a strb.w r3, [r7, #42] @ 0x2a - 8006178: e0c4 b.n 8006304 + 80061ba: 2301 movs r3, #1 + 80061bc: f887 302a strb.w r3, [r7, #42] @ 0x2a + 80061c0: e0c4 b.n 800634c } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 800617a: 697b ldr r3, [r7, #20] - 800617c: 69db ldr r3, [r3, #28] - 800617e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 - 8006182: d167 bne.n 8006254 + 80061c2: 697b ldr r3, [r7, #20] + 80061c4: 69db ldr r3, [r3, #28] + 80061c6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 + 80061ca: d167 bne.n 800629c { switch (clocksource) - 8006184: f897 302b ldrb.w r3, [r7, #43] @ 0x2b - 8006188: 2b08 cmp r3, #8 - 800618a: d828 bhi.n 80061de - 800618c: a201 add r2, pc, #4 @ (adr r2, 8006194 ) - 800618e: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8006192: bf00 nop - 8006194: 080061b9 .word 0x080061b9 - 8006198: 080061c1 .word 0x080061c1 - 800619c: 080061c9 .word 0x080061c9 - 80061a0: 080061df .word 0x080061df - 80061a4: 080061cf .word 0x080061cf - 80061a8: 080061df .word 0x080061df - 80061ac: 080061df .word 0x080061df - 80061b0: 080061df .word 0x080061df - 80061b4: 080061d7 .word 0x080061d7 + 80061cc: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 80061d0: 2b08 cmp r3, #8 + 80061d2: d828 bhi.n 8006226 + 80061d4: a201 add r2, pc, #4 @ (adr r2, 80061dc ) + 80061d6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80061da: bf00 nop + 80061dc: 08006201 .word 0x08006201 + 80061e0: 08006209 .word 0x08006209 + 80061e4: 08006211 .word 0x08006211 + 80061e8: 08006227 .word 0x08006227 + 80061ec: 08006217 .word 0x08006217 + 80061f0: 08006227 .word 0x08006227 + 80061f4: 08006227 .word 0x08006227 + 80061f8: 08006227 .word 0x08006227 + 80061fc: 0800621f .word 0x0800621f { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80061b8: f7fe fa3c bl 8004634 - 80061bc: 6278 str r0, [r7, #36] @ 0x24 + 8006200: f7fe fa3c bl 800467c + 8006204: 6278 str r0, [r7, #36] @ 0x24 break; - 80061be: e014 b.n 80061ea + 8006206: e014 b.n 8006232 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 80061c0: f7fe fa4e bl 8004660 - 80061c4: 6278 str r0, [r7, #36] @ 0x24 + 8006208: f7fe fa4e bl 80046a8 + 800620c: 6278 str r0, [r7, #36] @ 0x24 break; - 80061c6: e010 b.n 80061ea + 800620e: e010 b.n 8006232 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 80061c8: 4b5a ldr r3, [pc, #360] @ (8006334 ) - 80061ca: 627b str r3, [r7, #36] @ 0x24 + 8006210: 4b5a ldr r3, [pc, #360] @ (800637c ) + 8006212: 627b str r3, [r7, #36] @ 0x24 break; - 80061cc: e00d b.n 80061ea + 8006214: e00d b.n 8006232 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 80061ce: f7fe f9c3 bl 8004558 - 80061d2: 6278 str r0, [r7, #36] @ 0x24 + 8006216: f7fe f9c3 bl 80045a0 + 800621a: 6278 str r0, [r7, #36] @ 0x24 break; - 80061d4: e009 b.n 80061ea + 800621c: e009 b.n 8006232 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 80061d6: f44f 4300 mov.w r3, #32768 @ 0x8000 - 80061da: 627b str r3, [r7, #36] @ 0x24 + 800621e: f44f 4300 mov.w r3, #32768 @ 0x8000 + 8006222: 627b str r3, [r7, #36] @ 0x24 break; - 80061dc: e005 b.n 80061ea + 8006224: e005 b.n 8006232 default: pclk = 0U; - 80061de: 2300 movs r3, #0 - 80061e0: 627b str r3, [r7, #36] @ 0x24 + 8006226: 2300 movs r3, #0 + 8006228: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; - 80061e2: 2301 movs r3, #1 - 80061e4: f887 302a strb.w r3, [r7, #42] @ 0x2a + 800622a: 2301 movs r3, #1 + 800622c: f887 302a strb.w r3, [r7, #42] @ 0x2a break; - 80061e8: bf00 nop + 8006230: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 80061ea: 6a7b ldr r3, [r7, #36] @ 0x24 - 80061ec: 2b00 cmp r3, #0 - 80061ee: f000 8089 beq.w 8006304 + 8006232: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006234: 2b00 cmp r3, #0 + 8006236: f000 8089 beq.w 800634c { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 80061f2: 697b ldr r3, [r7, #20] - 80061f4: 6a5b ldr r3, [r3, #36] @ 0x24 - 80061f6: 4a4e ldr r2, [pc, #312] @ (8006330 ) - 80061f8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 80061fc: 461a mov r2, r3 - 80061fe: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006200: fbb3 f3f2 udiv r3, r3, r2 - 8006204: 005a lsls r2, r3, #1 - 8006206: 697b ldr r3, [r7, #20] - 8006208: 685b ldr r3, [r3, #4] - 800620a: 085b lsrs r3, r3, #1 - 800620c: 441a add r2, r3 - 800620e: 697b ldr r3, [r7, #20] - 8006210: 685b ldr r3, [r3, #4] - 8006212: fbb2 f3f3 udiv r3, r2, r3 - 8006216: 623b str r3, [r7, #32] + 800623a: 697b ldr r3, [r7, #20] + 800623c: 6a5b ldr r3, [r3, #36] @ 0x24 + 800623e: 4a4e ldr r2, [pc, #312] @ (8006378 ) + 8006240: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8006244: 461a mov r2, r3 + 8006246: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006248: fbb3 f3f2 udiv r3, r3, r2 + 800624c: 005a lsls r2, r3, #1 + 800624e: 697b ldr r3, [r7, #20] + 8006250: 685b ldr r3, [r3, #4] + 8006252: 085b lsrs r3, r3, #1 + 8006254: 441a add r2, r3 + 8006256: 697b ldr r3, [r7, #20] + 8006258: 685b ldr r3, [r3, #4] + 800625a: fbb2 f3f3 udiv r3, r2, r3 + 800625e: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8006218: 6a3b ldr r3, [r7, #32] - 800621a: 2b0f cmp r3, #15 - 800621c: d916 bls.n 800624c - 800621e: 6a3b ldr r3, [r7, #32] - 8006220: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 8006224: d212 bcs.n 800624c + 8006260: 6a3b ldr r3, [r7, #32] + 8006262: 2b0f cmp r3, #15 + 8006264: d916 bls.n 8006294 + 8006266: 6a3b ldr r3, [r7, #32] + 8006268: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 800626c: d212 bcs.n 8006294 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 8006226: 6a3b ldr r3, [r7, #32] - 8006228: b29b uxth r3, r3 - 800622a: f023 030f bic.w r3, r3, #15 - 800622e: 83fb strh r3, [r7, #30] + 800626e: 6a3b ldr r3, [r7, #32] + 8006270: b29b uxth r3, r3 + 8006272: f023 030f bic.w r3, r3, #15 + 8006276: 83fb strh r3, [r7, #30] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 8006230: 6a3b ldr r3, [r7, #32] - 8006232: 085b lsrs r3, r3, #1 - 8006234: b29b uxth r3, r3 - 8006236: f003 0307 and.w r3, r3, #7 - 800623a: b29a uxth r2, r3 - 800623c: 8bfb ldrh r3, [r7, #30] - 800623e: 4313 orrs r3, r2 - 8006240: 83fb strh r3, [r7, #30] + 8006278: 6a3b ldr r3, [r7, #32] + 800627a: 085b lsrs r3, r3, #1 + 800627c: b29b uxth r3, r3 + 800627e: f003 0307 and.w r3, r3, #7 + 8006282: b29a uxth r2, r3 + 8006284: 8bfb ldrh r3, [r7, #30] + 8006286: 4313 orrs r3, r2 + 8006288: 83fb strh r3, [r7, #30] huart->Instance->BRR = brrtemp; - 8006242: 697b ldr r3, [r7, #20] - 8006244: 681b ldr r3, [r3, #0] - 8006246: 8bfa ldrh r2, [r7, #30] - 8006248: 60da str r2, [r3, #12] - 800624a: e05b b.n 8006304 + 800628a: 697b ldr r3, [r7, #20] + 800628c: 681b ldr r3, [r3, #0] + 800628e: 8bfa ldrh r2, [r7, #30] + 8006290: 60da str r2, [r3, #12] + 8006292: e05b b.n 800634c } else { ret = HAL_ERROR; - 800624c: 2301 movs r3, #1 - 800624e: f887 302a strb.w r3, [r7, #42] @ 0x2a - 8006252: e057 b.n 8006304 + 8006294: 2301 movs r3, #1 + 8006296: f887 302a strb.w r3, [r7, #42] @ 0x2a + 800629a: e057 b.n 800634c } } } else { switch (clocksource) - 8006254: f897 302b ldrb.w r3, [r7, #43] @ 0x2b - 8006258: 2b08 cmp r3, #8 - 800625a: d828 bhi.n 80062ae - 800625c: a201 add r2, pc, #4 @ (adr r2, 8006264 ) - 800625e: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8006262: bf00 nop - 8006264: 08006289 .word 0x08006289 - 8006268: 08006291 .word 0x08006291 - 800626c: 08006299 .word 0x08006299 - 8006270: 080062af .word 0x080062af - 8006274: 0800629f .word 0x0800629f - 8006278: 080062af .word 0x080062af - 800627c: 080062af .word 0x080062af - 8006280: 080062af .word 0x080062af - 8006284: 080062a7 .word 0x080062a7 + 800629c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b + 80062a0: 2b08 cmp r3, #8 + 80062a2: d828 bhi.n 80062f6 + 80062a4: a201 add r2, pc, #4 @ (adr r2, 80062ac ) + 80062a6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80062aa: bf00 nop + 80062ac: 080062d1 .word 0x080062d1 + 80062b0: 080062d9 .word 0x080062d9 + 80062b4: 080062e1 .word 0x080062e1 + 80062b8: 080062f7 .word 0x080062f7 + 80062bc: 080062e7 .word 0x080062e7 + 80062c0: 080062f7 .word 0x080062f7 + 80062c4: 080062f7 .word 0x080062f7 + 80062c8: 080062f7 .word 0x080062f7 + 80062cc: 080062ef .word 0x080062ef { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8006288: f7fe f9d4 bl 8004634 - 800628c: 6278 str r0, [r7, #36] @ 0x24 + 80062d0: f7fe f9d4 bl 800467c + 80062d4: 6278 str r0, [r7, #36] @ 0x24 break; - 800628e: e014 b.n 80062ba + 80062d6: e014 b.n 8006302 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8006290: f7fe f9e6 bl 8004660 - 8006294: 6278 str r0, [r7, #36] @ 0x24 + 80062d8: f7fe f9e6 bl 80046a8 + 80062dc: 6278 str r0, [r7, #36] @ 0x24 break; - 8006296: e010 b.n 80062ba + 80062de: e010 b.n 8006302 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8006298: 4b26 ldr r3, [pc, #152] @ (8006334 ) - 800629a: 627b str r3, [r7, #36] @ 0x24 + 80062e0: 4b26 ldr r3, [pc, #152] @ (800637c ) + 80062e2: 627b str r3, [r7, #36] @ 0x24 break; - 800629c: e00d b.n 80062ba + 80062e4: e00d b.n 8006302 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 800629e: f7fe f95b bl 8004558 - 80062a2: 6278 str r0, [r7, #36] @ 0x24 + 80062e6: f7fe f95b bl 80045a0 + 80062ea: 6278 str r0, [r7, #36] @ 0x24 break; - 80062a4: e009 b.n 80062ba + 80062ec: e009 b.n 8006302 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 80062a6: f44f 4300 mov.w r3, #32768 @ 0x8000 - 80062aa: 627b str r3, [r7, #36] @ 0x24 + 80062ee: f44f 4300 mov.w r3, #32768 @ 0x8000 + 80062f2: 627b str r3, [r7, #36] @ 0x24 break; - 80062ac: e005 b.n 80062ba + 80062f4: e005 b.n 8006302 default: pclk = 0U; - 80062ae: 2300 movs r3, #0 - 80062b0: 627b str r3, [r7, #36] @ 0x24 + 80062f6: 2300 movs r3, #0 + 80062f8: 627b str r3, [r7, #36] @ 0x24 ret = HAL_ERROR; - 80062b2: 2301 movs r3, #1 - 80062b4: f887 302a strb.w r3, [r7, #42] @ 0x2a + 80062fa: 2301 movs r3, #1 + 80062fc: f887 302a strb.w r3, [r7, #42] @ 0x2a break; - 80062b8: bf00 nop + 8006300: bf00 nop } if (pclk != 0U) - 80062ba: 6a7b ldr r3, [r7, #36] @ 0x24 - 80062bc: 2b00 cmp r3, #0 - 80062be: d021 beq.n 8006304 + 8006302: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006304: 2b00 cmp r3, #0 + 8006306: d021 beq.n 800634c { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - 80062c0: 697b ldr r3, [r7, #20] - 80062c2: 6a5b ldr r3, [r3, #36] @ 0x24 - 80062c4: 4a1a ldr r2, [pc, #104] @ (8006330 ) - 80062c6: f832 3013 ldrh.w r3, [r2, r3, lsl #1] - 80062ca: 461a mov r2, r3 - 80062cc: 6a7b ldr r3, [r7, #36] @ 0x24 - 80062ce: fbb3 f2f2 udiv r2, r3, r2 - 80062d2: 697b ldr r3, [r7, #20] - 80062d4: 685b ldr r3, [r3, #4] - 80062d6: 085b lsrs r3, r3, #1 - 80062d8: 441a add r2, r3 - 80062da: 697b ldr r3, [r7, #20] - 80062dc: 685b ldr r3, [r3, #4] - 80062de: fbb2 f3f3 udiv r3, r2, r3 - 80062e2: 623b str r3, [r7, #32] + 8006308: 697b ldr r3, [r7, #20] + 800630a: 6a5b ldr r3, [r3, #36] @ 0x24 + 800630c: 4a1a ldr r2, [pc, #104] @ (8006378 ) + 800630e: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8006312: 461a mov r2, r3 + 8006314: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006316: fbb3 f2f2 udiv r2, r3, r2 + 800631a: 697b ldr r3, [r7, #20] + 800631c: 685b ldr r3, [r3, #4] + 800631e: 085b lsrs r3, r3, #1 + 8006320: 441a add r2, r3 + 8006322: 697b ldr r3, [r7, #20] + 8006324: 685b ldr r3, [r3, #4] + 8006326: fbb2 f3f3 udiv r3, r2, r3 + 800632a: 623b str r3, [r7, #32] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 80062e4: 6a3b ldr r3, [r7, #32] - 80062e6: 2b0f cmp r3, #15 - 80062e8: d909 bls.n 80062fe - 80062ea: 6a3b ldr r3, [r7, #32] - 80062ec: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 - 80062f0: d205 bcs.n 80062fe + 800632c: 6a3b ldr r3, [r7, #32] + 800632e: 2b0f cmp r3, #15 + 8006330: d909 bls.n 8006346 + 8006332: 6a3b ldr r3, [r7, #32] + 8006334: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 + 8006338: d205 bcs.n 8006346 { huart->Instance->BRR = (uint16_t)usartdiv; - 80062f2: 6a3b ldr r3, [r7, #32] - 80062f4: b29a uxth r2, r3 - 80062f6: 697b ldr r3, [r7, #20] - 80062f8: 681b ldr r3, [r3, #0] - 80062fa: 60da str r2, [r3, #12] - 80062fc: e002 b.n 8006304 + 800633a: 6a3b ldr r3, [r7, #32] + 800633c: b29a uxth r2, r3 + 800633e: 697b ldr r3, [r7, #20] + 8006340: 681b ldr r3, [r3, #0] + 8006342: 60da str r2, [r3, #12] + 8006344: e002 b.n 800634c } else { ret = HAL_ERROR; - 80062fe: 2301 movs r3, #1 - 8006300: f887 302a strb.w r3, [r7, #42] @ 0x2a + 8006346: 2301 movs r3, #1 + 8006348: f887 302a strb.w r3, [r7, #42] @ 0x2a } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; - 8006304: 697b ldr r3, [r7, #20] - 8006306: 2201 movs r2, #1 - 8006308: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + 800634c: 697b ldr r3, [r7, #20] + 800634e: 2201 movs r2, #1 + 8006350: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; - 800630c: 697b ldr r3, [r7, #20] - 800630e: 2201 movs r2, #1 - 8006310: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + 8006354: 697b ldr r3, [r7, #20] + 8006356: 2201 movs r2, #1 + 8006358: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; - 8006314: 697b ldr r3, [r7, #20] - 8006316: 2200 movs r2, #0 - 8006318: 675a str r2, [r3, #116] @ 0x74 + 800635c: 697b ldr r3, [r7, #20] + 800635e: 2200 movs r2, #0 + 8006360: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; - 800631a: 697b ldr r3, [r7, #20] - 800631c: 2200 movs r2, #0 - 800631e: 679a str r2, [r3, #120] @ 0x78 + 8006362: 697b ldr r3, [r7, #20] + 8006364: 2200 movs r2, #0 + 8006366: 679a str r2, [r3, #120] @ 0x78 return ret; - 8006320: f897 302a ldrb.w r3, [r7, #42] @ 0x2a + 8006368: f897 302a ldrb.w r3, [r7, #42] @ 0x2a } - 8006324: 4618 mov r0, r3 - 8006326: 3730 adds r7, #48 @ 0x30 - 8006328: 46bd mov sp, r7 - 800632a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 800632e: bf00 nop - 8006330: 08007744 .word 0x08007744 - 8006334: 00f42400 .word 0x00f42400 + 800636c: 4618 mov r0, r3 + 800636e: 3730 adds r7, #48 @ 0x30 + 8006370: 46bd mov sp, r7 + 8006372: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8006376: bf00 nop + 8006378: 0800778c .word 0x0800778c + 800637c: 00f42400 .word 0x00f42400 -08006338 : +08006380 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 8006338: b480 push {r7} - 800633a: b083 sub sp, #12 - 800633c: af00 add r7, sp, #0 - 800633e: 6078 str r0, [r7, #4] + 8006380: b480 push {r7} + 8006382: b083 sub sp, #12 + 8006384: af00 add r7, sp, #0 + 8006386: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 8006340: 687b ldr r3, [r7, #4] - 8006342: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006344: f003 0308 and.w r3, r3, #8 - 8006348: 2b00 cmp r3, #0 - 800634a: d00a beq.n 8006362 + 8006388: 687b ldr r3, [r7, #4] + 800638a: 6a9b ldr r3, [r3, #40] @ 0x28 + 800638c: f003 0308 and.w r3, r3, #8 + 8006390: 2b00 cmp r3, #0 + 8006392: d00a beq.n 80063aa { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 800634c: 687b ldr r3, [r7, #4] - 800634e: 681b ldr r3, [r3, #0] - 8006350: 685b ldr r3, [r3, #4] - 8006352: f423 4100 bic.w r1, r3, #32768 @ 0x8000 - 8006356: 687b ldr r3, [r7, #4] - 8006358: 6b9a ldr r2, [r3, #56] @ 0x38 - 800635a: 687b ldr r3, [r7, #4] - 800635c: 681b ldr r3, [r3, #0] - 800635e: 430a orrs r2, r1 - 8006360: 605a str r2, [r3, #4] + 8006394: 687b ldr r3, [r7, #4] + 8006396: 681b ldr r3, [r3, #0] + 8006398: 685b ldr r3, [r3, #4] + 800639a: f423 4100 bic.w r1, r3, #32768 @ 0x8000 + 800639e: 687b ldr r3, [r7, #4] + 80063a0: 6b9a ldr r2, [r3, #56] @ 0x38 + 80063a2: 687b ldr r3, [r7, #4] + 80063a4: 681b ldr r3, [r3, #0] + 80063a6: 430a orrs r2, r1 + 80063a8: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 8006362: 687b ldr r3, [r7, #4] - 8006364: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006366: f003 0301 and.w r3, r3, #1 - 800636a: 2b00 cmp r3, #0 - 800636c: d00a beq.n 8006384 + 80063aa: 687b ldr r3, [r7, #4] + 80063ac: 6a9b ldr r3, [r3, #40] @ 0x28 + 80063ae: f003 0301 and.w r3, r3, #1 + 80063b2: 2b00 cmp r3, #0 + 80063b4: d00a beq.n 80063cc { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 800636e: 687b ldr r3, [r7, #4] - 8006370: 681b ldr r3, [r3, #0] - 8006372: 685b ldr r3, [r3, #4] - 8006374: f423 3100 bic.w r1, r3, #131072 @ 0x20000 - 8006378: 687b ldr r3, [r7, #4] - 800637a: 6ada ldr r2, [r3, #44] @ 0x2c - 800637c: 687b ldr r3, [r7, #4] - 800637e: 681b ldr r3, [r3, #0] - 8006380: 430a orrs r2, r1 - 8006382: 605a str r2, [r3, #4] + 80063b6: 687b ldr r3, [r7, #4] + 80063b8: 681b ldr r3, [r3, #0] + 80063ba: 685b ldr r3, [r3, #4] + 80063bc: f423 3100 bic.w r1, r3, #131072 @ 0x20000 + 80063c0: 687b ldr r3, [r7, #4] + 80063c2: 6ada ldr r2, [r3, #44] @ 0x2c + 80063c4: 687b ldr r3, [r7, #4] + 80063c6: 681b ldr r3, [r3, #0] + 80063c8: 430a orrs r2, r1 + 80063ca: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 8006384: 687b ldr r3, [r7, #4] - 8006386: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006388: f003 0302 and.w r3, r3, #2 - 800638c: 2b00 cmp r3, #0 - 800638e: d00a beq.n 80063a6 + 80063cc: 687b ldr r3, [r7, #4] + 80063ce: 6a9b ldr r3, [r3, #40] @ 0x28 + 80063d0: f003 0302 and.w r3, r3, #2 + 80063d4: 2b00 cmp r3, #0 + 80063d6: d00a beq.n 80063ee { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8006390: 687b ldr r3, [r7, #4] - 8006392: 681b ldr r3, [r3, #0] - 8006394: 685b ldr r3, [r3, #4] - 8006396: f423 3180 bic.w r1, r3, #65536 @ 0x10000 - 800639a: 687b ldr r3, [r7, #4] - 800639c: 6b1a ldr r2, [r3, #48] @ 0x30 - 800639e: 687b ldr r3, [r7, #4] - 80063a0: 681b ldr r3, [r3, #0] - 80063a2: 430a orrs r2, r1 - 80063a4: 605a str r2, [r3, #4] + 80063d8: 687b ldr r3, [r7, #4] + 80063da: 681b ldr r3, [r3, #0] + 80063dc: 685b ldr r3, [r3, #4] + 80063de: f423 3180 bic.w r1, r3, #65536 @ 0x10000 + 80063e2: 687b ldr r3, [r7, #4] + 80063e4: 6b1a ldr r2, [r3, #48] @ 0x30 + 80063e6: 687b ldr r3, [r7, #4] + 80063e8: 681b ldr r3, [r3, #0] + 80063ea: 430a orrs r2, r1 + 80063ec: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 80063a6: 687b ldr r3, [r7, #4] - 80063a8: 6a9b ldr r3, [r3, #40] @ 0x28 - 80063aa: f003 0304 and.w r3, r3, #4 - 80063ae: 2b00 cmp r3, #0 - 80063b0: d00a beq.n 80063c8 + 80063ee: 687b ldr r3, [r7, #4] + 80063f0: 6a9b ldr r3, [r3, #40] @ 0x28 + 80063f2: f003 0304 and.w r3, r3, #4 + 80063f6: 2b00 cmp r3, #0 + 80063f8: d00a beq.n 8006410 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 80063b2: 687b ldr r3, [r7, #4] - 80063b4: 681b ldr r3, [r3, #0] - 80063b6: 685b ldr r3, [r3, #4] - 80063b8: f423 2180 bic.w r1, r3, #262144 @ 0x40000 - 80063bc: 687b ldr r3, [r7, #4] - 80063be: 6b5a ldr r2, [r3, #52] @ 0x34 - 80063c0: 687b ldr r3, [r7, #4] - 80063c2: 681b ldr r3, [r3, #0] - 80063c4: 430a orrs r2, r1 - 80063c6: 605a str r2, [r3, #4] + 80063fa: 687b ldr r3, [r7, #4] + 80063fc: 681b ldr r3, [r3, #0] + 80063fe: 685b ldr r3, [r3, #4] + 8006400: f423 2180 bic.w r1, r3, #262144 @ 0x40000 + 8006404: 687b ldr r3, [r7, #4] + 8006406: 6b5a ldr r2, [r3, #52] @ 0x34 + 8006408: 687b ldr r3, [r7, #4] + 800640a: 681b ldr r3, [r3, #0] + 800640c: 430a orrs r2, r1 + 800640e: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 80063c8: 687b ldr r3, [r7, #4] - 80063ca: 6a9b ldr r3, [r3, #40] @ 0x28 - 80063cc: f003 0310 and.w r3, r3, #16 - 80063d0: 2b00 cmp r3, #0 - 80063d2: d00a beq.n 80063ea + 8006410: 687b ldr r3, [r7, #4] + 8006412: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006414: f003 0310 and.w r3, r3, #16 + 8006418: 2b00 cmp r3, #0 + 800641a: d00a beq.n 8006432 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 80063d4: 687b ldr r3, [r7, #4] - 80063d6: 681b ldr r3, [r3, #0] - 80063d8: 689b ldr r3, [r3, #8] - 80063da: f423 5180 bic.w r1, r3, #4096 @ 0x1000 - 80063de: 687b ldr r3, [r7, #4] - 80063e0: 6bda ldr r2, [r3, #60] @ 0x3c - 80063e2: 687b ldr r3, [r7, #4] - 80063e4: 681b ldr r3, [r3, #0] - 80063e6: 430a orrs r2, r1 - 80063e8: 609a str r2, [r3, #8] + 800641c: 687b ldr r3, [r7, #4] + 800641e: 681b ldr r3, [r3, #0] + 8006420: 689b ldr r3, [r3, #8] + 8006422: f423 5180 bic.w r1, r3, #4096 @ 0x1000 + 8006426: 687b ldr r3, [r7, #4] + 8006428: 6bda ldr r2, [r3, #60] @ 0x3c + 800642a: 687b ldr r3, [r7, #4] + 800642c: 681b ldr r3, [r3, #0] + 800642e: 430a orrs r2, r1 + 8006430: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 80063ea: 687b ldr r3, [r7, #4] - 80063ec: 6a9b ldr r3, [r3, #40] @ 0x28 - 80063ee: f003 0320 and.w r3, r3, #32 - 80063f2: 2b00 cmp r3, #0 - 80063f4: d00a beq.n 800640c + 8006432: 687b ldr r3, [r7, #4] + 8006434: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006436: f003 0320 and.w r3, r3, #32 + 800643a: 2b00 cmp r3, #0 + 800643c: d00a beq.n 8006454 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 80063f6: 687b ldr r3, [r7, #4] - 80063f8: 681b ldr r3, [r3, #0] - 80063fa: 689b ldr r3, [r3, #8] - 80063fc: f423 5100 bic.w r1, r3, #8192 @ 0x2000 - 8006400: 687b ldr r3, [r7, #4] - 8006402: 6c1a ldr r2, [r3, #64] @ 0x40 - 8006404: 687b ldr r3, [r7, #4] - 8006406: 681b ldr r3, [r3, #0] - 8006408: 430a orrs r2, r1 - 800640a: 609a str r2, [r3, #8] + 800643e: 687b ldr r3, [r7, #4] + 8006440: 681b ldr r3, [r3, #0] + 8006442: 689b ldr r3, [r3, #8] + 8006444: f423 5100 bic.w r1, r3, #8192 @ 0x2000 + 8006448: 687b ldr r3, [r7, #4] + 800644a: 6c1a ldr r2, [r3, #64] @ 0x40 + 800644c: 687b ldr r3, [r7, #4] + 800644e: 681b ldr r3, [r3, #0] + 8006450: 430a orrs r2, r1 + 8006452: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 800640c: 687b ldr r3, [r7, #4] - 800640e: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006410: f003 0340 and.w r3, r3, #64 @ 0x40 - 8006414: 2b00 cmp r3, #0 - 8006416: d01a beq.n 800644e + 8006454: 687b ldr r3, [r7, #4] + 8006456: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006458: f003 0340 and.w r3, r3, #64 @ 0x40 + 800645c: 2b00 cmp r3, #0 + 800645e: d01a beq.n 8006496 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 8006418: 687b ldr r3, [r7, #4] - 800641a: 681b ldr r3, [r3, #0] - 800641c: 685b ldr r3, [r3, #4] - 800641e: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 - 8006422: 687b ldr r3, [r7, #4] - 8006424: 6c5a ldr r2, [r3, #68] @ 0x44 - 8006426: 687b ldr r3, [r7, #4] - 8006428: 681b ldr r3, [r3, #0] - 800642a: 430a orrs r2, r1 - 800642c: 605a str r2, [r3, #4] + 8006460: 687b ldr r3, [r7, #4] + 8006462: 681b ldr r3, [r3, #0] + 8006464: 685b ldr r3, [r3, #4] + 8006466: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 + 800646a: 687b ldr r3, [r7, #4] + 800646c: 6c5a ldr r2, [r3, #68] @ 0x44 + 800646e: 687b ldr r3, [r7, #4] + 8006470: 681b ldr r3, [r3, #0] + 8006472: 430a orrs r2, r1 + 8006474: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 800642e: 687b ldr r3, [r7, #4] - 8006430: 6c5b ldr r3, [r3, #68] @ 0x44 - 8006432: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 - 8006436: d10a bne.n 800644e + 8006476: 687b ldr r3, [r7, #4] + 8006478: 6c5b ldr r3, [r3, #68] @ 0x44 + 800647a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 + 800647e: d10a bne.n 8006496 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 8006438: 687b ldr r3, [r7, #4] - 800643a: 681b ldr r3, [r3, #0] - 800643c: 685b ldr r3, [r3, #4] - 800643e: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 - 8006442: 687b ldr r3, [r7, #4] - 8006444: 6c9a ldr r2, [r3, #72] @ 0x48 - 8006446: 687b ldr r3, [r7, #4] - 8006448: 681b ldr r3, [r3, #0] - 800644a: 430a orrs r2, r1 - 800644c: 605a str r2, [r3, #4] + 8006480: 687b ldr r3, [r7, #4] + 8006482: 681b ldr r3, [r3, #0] + 8006484: 685b ldr r3, [r3, #4] + 8006486: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 + 800648a: 687b ldr r3, [r7, #4] + 800648c: 6c9a ldr r2, [r3, #72] @ 0x48 + 800648e: 687b ldr r3, [r7, #4] + 8006490: 681b ldr r3, [r3, #0] + 8006492: 430a orrs r2, r1 + 8006494: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 800644e: 687b ldr r3, [r7, #4] - 8006450: 6a9b ldr r3, [r3, #40] @ 0x28 - 8006452: f003 0380 and.w r3, r3, #128 @ 0x80 - 8006456: 2b00 cmp r3, #0 - 8006458: d00a beq.n 8006470 + 8006496: 687b ldr r3, [r7, #4] + 8006498: 6a9b ldr r3, [r3, #40] @ 0x28 + 800649a: f003 0380 and.w r3, r3, #128 @ 0x80 + 800649e: 2b00 cmp r3, #0 + 80064a0: d00a beq.n 80064b8 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 800645a: 687b ldr r3, [r7, #4] - 800645c: 681b ldr r3, [r3, #0] - 800645e: 685b ldr r3, [r3, #4] - 8006460: f423 2100 bic.w r1, r3, #524288 @ 0x80000 - 8006464: 687b ldr r3, [r7, #4] - 8006466: 6cda ldr r2, [r3, #76] @ 0x4c - 8006468: 687b ldr r3, [r7, #4] - 800646a: 681b ldr r3, [r3, #0] - 800646c: 430a orrs r2, r1 - 800646e: 605a str r2, [r3, #4] + 80064a2: 687b ldr r3, [r7, #4] + 80064a4: 681b ldr r3, [r3, #0] + 80064a6: 685b ldr r3, [r3, #4] + 80064a8: f423 2100 bic.w r1, r3, #524288 @ 0x80000 + 80064ac: 687b ldr r3, [r7, #4] + 80064ae: 6cda ldr r2, [r3, #76] @ 0x4c + 80064b0: 687b ldr r3, [r7, #4] + 80064b2: 681b ldr r3, [r3, #0] + 80064b4: 430a orrs r2, r1 + 80064b6: 605a str r2, [r3, #4] } } - 8006470: bf00 nop - 8006472: 370c adds r7, #12 - 8006474: 46bd mov sp, r7 - 8006476: f85d 7b04 ldr.w r7, [sp], #4 - 800647a: 4770 bx lr + 80064b8: bf00 nop + 80064ba: 370c adds r7, #12 + 80064bc: 46bd mov sp, r7 + 80064be: f85d 7b04 ldr.w r7, [sp], #4 + 80064c2: 4770 bx lr -0800647c : +080064c4 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 800647c: b580 push {r7, lr} - 800647e: b098 sub sp, #96 @ 0x60 - 8006480: af02 add r7, sp, #8 - 8006482: 6078 str r0, [r7, #4] + 80064c4: b580 push {r7, lr} + 80064c6: b098 sub sp, #96 @ 0x60 + 80064c8: af02 add r7, sp, #8 + 80064ca: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8006484: 687b ldr r3, [r7, #4] - 8006486: 2200 movs r2, #0 - 8006488: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 80064cc: 687b ldr r3, [r7, #4] + 80064ce: 2200 movs r2, #0 + 80064d0: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 800648c: f7fb fb2e bl 8001aec - 8006490: 6578 str r0, [r7, #84] @ 0x54 + 80064d4: f7fb fb2e bl 8001b34 + 80064d8: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 8006492: 687b ldr r3, [r7, #4] - 8006494: 681b ldr r3, [r3, #0] - 8006496: 681b ldr r3, [r3, #0] - 8006498: f003 0308 and.w r3, r3, #8 - 800649c: 2b08 cmp r3, #8 - 800649e: d12f bne.n 8006500 + 80064da: 687b ldr r3, [r7, #4] + 80064dc: 681b ldr r3, [r3, #0] + 80064de: 681b ldr r3, [r3, #0] + 80064e0: f003 0308 and.w r3, r3, #8 + 80064e4: 2b08 cmp r3, #8 + 80064e6: d12f bne.n 8006548 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 80064a0: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 - 80064a4: 9300 str r3, [sp, #0] - 80064a6: 6d7b ldr r3, [r7, #84] @ 0x54 - 80064a8: 2200 movs r2, #0 - 80064aa: f44f 1100 mov.w r1, #2097152 @ 0x200000 - 80064ae: 6878 ldr r0, [r7, #4] - 80064b0: f000 f88e bl 80065d0 - 80064b4: 4603 mov r3, r0 - 80064b6: 2b00 cmp r3, #0 - 80064b8: d022 beq.n 8006500 + 80064e8: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 80064ec: 9300 str r3, [sp, #0] + 80064ee: 6d7b ldr r3, [r7, #84] @ 0x54 + 80064f0: 2200 movs r2, #0 + 80064f2: f44f 1100 mov.w r1, #2097152 @ 0x200000 + 80064f6: 6878 ldr r0, [r7, #4] + 80064f8: f000 f88e bl 8006618 + 80064fc: 4603 mov r3, r0 + 80064fe: 2b00 cmp r3, #0 + 8006500: d022 beq.n 8006548 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); - 80064ba: 687b ldr r3, [r7, #4] - 80064bc: 681b ldr r3, [r3, #0] - 80064be: 63bb str r3, [r7, #56] @ 0x38 + 8006502: 687b ldr r3, [r7, #4] + 8006504: 681b ldr r3, [r3, #0] + 8006506: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80064c0: 6bbb ldr r3, [r7, #56] @ 0x38 - 80064c2: e853 3f00 ldrex r3, [r3] - 80064c6: 637b str r3, [r7, #52] @ 0x34 + 8006508: 6bbb ldr r3, [r7, #56] @ 0x38 + 800650a: e853 3f00 ldrex r3, [r3] + 800650e: 637b str r3, [r7, #52] @ 0x34 return(result); - 80064c8: 6b7b ldr r3, [r7, #52] @ 0x34 - 80064ca: f023 0380 bic.w r3, r3, #128 @ 0x80 - 80064ce: 653b str r3, [r7, #80] @ 0x50 - 80064d0: 687b ldr r3, [r7, #4] - 80064d2: 681b ldr r3, [r3, #0] - 80064d4: 461a mov r2, r3 - 80064d6: 6d3b ldr r3, [r7, #80] @ 0x50 - 80064d8: 647b str r3, [r7, #68] @ 0x44 - 80064da: 643a str r2, [r7, #64] @ 0x40 + 8006510: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006512: f023 0380 bic.w r3, r3, #128 @ 0x80 + 8006516: 653b str r3, [r7, #80] @ 0x50 + 8006518: 687b ldr r3, [r7, #4] + 800651a: 681b ldr r3, [r3, #0] + 800651c: 461a mov r2, r3 + 800651e: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006520: 647b str r3, [r7, #68] @ 0x44 + 8006522: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80064dc: 6c39 ldr r1, [r7, #64] @ 0x40 - 80064de: 6c7a ldr r2, [r7, #68] @ 0x44 - 80064e0: e841 2300 strex r3, r2, [r1] - 80064e4: 63fb str r3, [r7, #60] @ 0x3c + 8006524: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006526: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006528: e841 2300 strex r3, r2, [r1] + 800652c: 63fb str r3, [r7, #60] @ 0x3c return(result); - 80064e6: 6bfb ldr r3, [r7, #60] @ 0x3c - 80064e8: 2b00 cmp r3, #0 - 80064ea: d1e6 bne.n 80064ba + 800652e: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006530: 2b00 cmp r3, #0 + 8006532: d1e6 bne.n 8006502 huart->gState = HAL_UART_STATE_READY; - 80064ec: 687b ldr r3, [r7, #4] - 80064ee: 2220 movs r2, #32 - 80064f0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 8006534: 687b ldr r3, [r7, #4] + 8006536: 2220 movs r2, #32 + 8006538: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); - 80064f4: 687b ldr r3, [r7, #4] - 80064f6: 2200 movs r2, #0 - 80064f8: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 800653c: 687b ldr r3, [r7, #4] + 800653e: 2200 movs r2, #0 + 8006540: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; - 80064fc: 2303 movs r3, #3 - 80064fe: e063 b.n 80065c8 + 8006544: 2303 movs r3, #3 + 8006546: e063 b.n 8006610 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 8006500: 687b ldr r3, [r7, #4] - 8006502: 681b ldr r3, [r3, #0] - 8006504: 681b ldr r3, [r3, #0] - 8006506: f003 0304 and.w r3, r3, #4 - 800650a: 2b04 cmp r3, #4 - 800650c: d149 bne.n 80065a2 + 8006548: 687b ldr r3, [r7, #4] + 800654a: 681b ldr r3, [r3, #0] + 800654c: 681b ldr r3, [r3, #0] + 800654e: f003 0304 and.w r3, r3, #4 + 8006552: 2b04 cmp r3, #4 + 8006554: d149 bne.n 80065ea { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 800650e: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 - 8006512: 9300 str r3, [sp, #0] - 8006514: 6d7b ldr r3, [r7, #84] @ 0x54 - 8006516: 2200 movs r2, #0 - 8006518: f44f 0180 mov.w r1, #4194304 @ 0x400000 - 800651c: 6878 ldr r0, [r7, #4] - 800651e: f000 f857 bl 80065d0 - 8006522: 4603 mov r3, r0 - 8006524: 2b00 cmp r3, #0 - 8006526: d03c beq.n 80065a2 + 8006556: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 + 800655a: 9300 str r3, [sp, #0] + 800655c: 6d7b ldr r3, [r7, #84] @ 0x54 + 800655e: 2200 movs r2, #0 + 8006560: f44f 0180 mov.w r1, #4194304 @ 0x400000 + 8006564: 6878 ldr r0, [r7, #4] + 8006566: f000 f857 bl 8006618 + 800656a: 4603 mov r3, r0 + 800656c: 2b00 cmp r3, #0 + 800656e: d03c beq.n 80065ea { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 8006528: 687b ldr r3, [r7, #4] - 800652a: 681b ldr r3, [r3, #0] - 800652c: 627b str r3, [r7, #36] @ 0x24 + 8006570: 687b ldr r3, [r7, #4] + 8006572: 681b ldr r3, [r3, #0] + 8006574: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800652e: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006530: e853 3f00 ldrex r3, [r3] - 8006534: 623b str r3, [r7, #32] + 8006576: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006578: e853 3f00 ldrex r3, [r3] + 800657c: 623b str r3, [r7, #32] return(result); - 8006536: 6a3b ldr r3, [r7, #32] - 8006538: f423 7390 bic.w r3, r3, #288 @ 0x120 - 800653c: 64fb str r3, [r7, #76] @ 0x4c - 800653e: 687b ldr r3, [r7, #4] - 8006540: 681b ldr r3, [r3, #0] - 8006542: 461a mov r2, r3 - 8006544: 6cfb ldr r3, [r7, #76] @ 0x4c - 8006546: 633b str r3, [r7, #48] @ 0x30 - 8006548: 62fa str r2, [r7, #44] @ 0x2c + 800657e: 6a3b ldr r3, [r7, #32] + 8006580: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006584: 64fb str r3, [r7, #76] @ 0x4c + 8006586: 687b ldr r3, [r7, #4] + 8006588: 681b ldr r3, [r3, #0] + 800658a: 461a mov r2, r3 + 800658c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800658e: 633b str r3, [r7, #48] @ 0x30 + 8006590: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800654a: 6af9 ldr r1, [r7, #44] @ 0x2c - 800654c: 6b3a ldr r2, [r7, #48] @ 0x30 - 800654e: e841 2300 strex r3, r2, [r1] - 8006552: 62bb str r3, [r7, #40] @ 0x28 + 8006592: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006594: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006596: e841 2300 strex r3, r2, [r1] + 800659a: 62bb str r3, [r7, #40] @ 0x28 return(result); - 8006554: 6abb ldr r3, [r7, #40] @ 0x28 - 8006556: 2b00 cmp r3, #0 - 8006558: d1e6 bne.n 8006528 + 800659c: 6abb ldr r3, [r7, #40] @ 0x28 + 800659e: 2b00 cmp r3, #0 + 80065a0: d1e6 bne.n 8006570 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 800655a: 687b ldr r3, [r7, #4] - 800655c: 681b ldr r3, [r3, #0] - 800655e: 3308 adds r3, #8 - 8006560: 613b str r3, [r7, #16] + 80065a2: 687b ldr r3, [r7, #4] + 80065a4: 681b ldr r3, [r3, #0] + 80065a6: 3308 adds r3, #8 + 80065a8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006562: 693b ldr r3, [r7, #16] - 8006564: e853 3f00 ldrex r3, [r3] - 8006568: 60fb str r3, [r7, #12] + 80065aa: 693b ldr r3, [r7, #16] + 80065ac: e853 3f00 ldrex r3, [r3] + 80065b0: 60fb str r3, [r7, #12] return(result); - 800656a: 68fb ldr r3, [r7, #12] - 800656c: f023 0301 bic.w r3, r3, #1 - 8006570: 64bb str r3, [r7, #72] @ 0x48 - 8006572: 687b ldr r3, [r7, #4] - 8006574: 681b ldr r3, [r3, #0] - 8006576: 3308 adds r3, #8 - 8006578: 6cba ldr r2, [r7, #72] @ 0x48 - 800657a: 61fa str r2, [r7, #28] - 800657c: 61bb str r3, [r7, #24] + 80065b2: 68fb ldr r3, [r7, #12] + 80065b4: f023 0301 bic.w r3, r3, #1 + 80065b8: 64bb str r3, [r7, #72] @ 0x48 + 80065ba: 687b ldr r3, [r7, #4] + 80065bc: 681b ldr r3, [r3, #0] + 80065be: 3308 adds r3, #8 + 80065c0: 6cba ldr r2, [r7, #72] @ 0x48 + 80065c2: 61fa str r2, [r7, #28] + 80065c4: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800657e: 69b9 ldr r1, [r7, #24] - 8006580: 69fa ldr r2, [r7, #28] - 8006582: e841 2300 strex r3, r2, [r1] - 8006586: 617b str r3, [r7, #20] + 80065c6: 69b9 ldr r1, [r7, #24] + 80065c8: 69fa ldr r2, [r7, #28] + 80065ca: e841 2300 strex r3, r2, [r1] + 80065ce: 617b str r3, [r7, #20] return(result); - 8006588: 697b ldr r3, [r7, #20] - 800658a: 2b00 cmp r3, #0 - 800658c: d1e5 bne.n 800655a + 80065d0: 697b ldr r3, [r7, #20] + 80065d2: 2b00 cmp r3, #0 + 80065d4: d1e5 bne.n 80065a2 huart->RxState = HAL_UART_STATE_READY; - 800658e: 687b ldr r3, [r7, #4] - 8006590: 2220 movs r2, #32 - 8006592: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 80065d6: 687b ldr r3, [r7, #4] + 80065d8: 2220 movs r2, #32 + 80065da: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); - 8006596: 687b ldr r3, [r7, #4] - 8006598: 2200 movs r2, #0 - 800659a: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 80065de: 687b ldr r3, [r7, #4] + 80065e0: 2200 movs r2, #0 + 80065e2: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; - 800659e: 2303 movs r3, #3 - 80065a0: e012 b.n 80065c8 + 80065e6: 2303 movs r3, #3 + 80065e8: e012 b.n 8006610 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 80065a2: 687b ldr r3, [r7, #4] - 80065a4: 2220 movs r2, #32 - 80065a6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 80065ea: 687b ldr r3, [r7, #4] + 80065ec: 2220 movs r2, #32 + 80065ee: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; - 80065aa: 687b ldr r3, [r7, #4] - 80065ac: 2220 movs r2, #32 - 80065ae: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 80065f2: 687b ldr r3, [r7, #4] + 80065f4: 2220 movs r2, #32 + 80065f6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80065b2: 687b ldr r3, [r7, #4] - 80065b4: 2200 movs r2, #0 - 80065b6: 66da str r2, [r3, #108] @ 0x6c + 80065fa: 687b ldr r3, [r7, #4] + 80065fc: 2200 movs r2, #0 + 80065fe: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; - 80065b8: 687b ldr r3, [r7, #4] - 80065ba: 2200 movs r2, #0 - 80065bc: 671a str r2, [r3, #112] @ 0x70 + 8006600: 687b ldr r3, [r7, #4] + 8006602: 2200 movs r2, #0 + 8006604: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); - 80065be: 687b ldr r3, [r7, #4] - 80065c0: 2200 movs r2, #0 - 80065c2: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 8006606: 687b ldr r3, [r7, #4] + 8006608: 2200 movs r2, #0 + 800660a: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; - 80065c6: 2300 movs r3, #0 + 800660e: 2300 movs r3, #0 } - 80065c8: 4618 mov r0, r3 - 80065ca: 3758 adds r7, #88 @ 0x58 - 80065cc: 46bd mov sp, r7 - 80065ce: bd80 pop {r7, pc} + 8006610: 4618 mov r0, r3 + 8006612: 3758 adds r7, #88 @ 0x58 + 8006614: 46bd mov sp, r7 + 8006616: bd80 pop {r7, pc} -080065d0 : +08006618 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 80065d0: b580 push {r7, lr} - 80065d2: b084 sub sp, #16 - 80065d4: af00 add r7, sp, #0 - 80065d6: 60f8 str r0, [r7, #12] - 80065d8: 60b9 str r1, [r7, #8] - 80065da: 603b str r3, [r7, #0] - 80065dc: 4613 mov r3, r2 - 80065de: 71fb strb r3, [r7, #7] + 8006618: b580 push {r7, lr} + 800661a: b084 sub sp, #16 + 800661c: af00 add r7, sp, #0 + 800661e: 60f8 str r0, [r7, #12] + 8006620: 60b9 str r1, [r7, #8] + 8006622: 603b str r3, [r7, #0] + 8006624: 4613 mov r3, r2 + 8006626: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 80065e0: e04f b.n 8006682 + 8006628: e04f b.n 80066ca { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 80065e2: 69bb ldr r3, [r7, #24] - 80065e4: f1b3 3fff cmp.w r3, #4294967295 - 80065e8: d04b beq.n 8006682 + 800662a: 69bb ldr r3, [r7, #24] + 800662c: f1b3 3fff cmp.w r3, #4294967295 + 8006630: d04b beq.n 80066ca { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 80065ea: f7fb fa7f bl 8001aec - 80065ee: 4602 mov r2, r0 - 80065f0: 683b ldr r3, [r7, #0] - 80065f2: 1ad3 subs r3, r2, r3 - 80065f4: 69ba ldr r2, [r7, #24] - 80065f6: 429a cmp r2, r3 - 80065f8: d302 bcc.n 8006600 - 80065fa: 69bb ldr r3, [r7, #24] - 80065fc: 2b00 cmp r3, #0 - 80065fe: d101 bne.n 8006604 + 8006632: f7fb fa7f bl 8001b34 + 8006636: 4602 mov r2, r0 + 8006638: 683b ldr r3, [r7, #0] + 800663a: 1ad3 subs r3, r2, r3 + 800663c: 69ba ldr r2, [r7, #24] + 800663e: 429a cmp r2, r3 + 8006640: d302 bcc.n 8006648 + 8006642: 69bb ldr r3, [r7, #24] + 8006644: 2b00 cmp r3, #0 + 8006646: d101 bne.n 800664c { return HAL_TIMEOUT; - 8006600: 2303 movs r3, #3 - 8006602: e04e b.n 80066a2 + 8006648: 2303 movs r3, #3 + 800664a: e04e b.n 80066ea } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) - 8006604: 68fb ldr r3, [r7, #12] - 8006606: 681b ldr r3, [r3, #0] - 8006608: 681b ldr r3, [r3, #0] - 800660a: f003 0304 and.w r3, r3, #4 - 800660e: 2b00 cmp r3, #0 - 8006610: d037 beq.n 8006682 - 8006612: 68bb ldr r3, [r7, #8] - 8006614: 2b80 cmp r3, #128 @ 0x80 - 8006616: d034 beq.n 8006682 - 8006618: 68bb ldr r3, [r7, #8] - 800661a: 2b40 cmp r3, #64 @ 0x40 - 800661c: d031 beq.n 8006682 + 800664c: 68fb ldr r3, [r7, #12] + 800664e: 681b ldr r3, [r3, #0] + 8006650: 681b ldr r3, [r3, #0] + 8006652: f003 0304 and.w r3, r3, #4 + 8006656: 2b00 cmp r3, #0 + 8006658: d037 beq.n 80066ca + 800665a: 68bb ldr r3, [r7, #8] + 800665c: 2b80 cmp r3, #128 @ 0x80 + 800665e: d034 beq.n 80066ca + 8006660: 68bb ldr r3, [r7, #8] + 8006662: 2b40 cmp r3, #64 @ 0x40 + 8006664: d031 beq.n 80066ca { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - 800661e: 68fb ldr r3, [r7, #12] - 8006620: 681b ldr r3, [r3, #0] - 8006622: 69db ldr r3, [r3, #28] - 8006624: f003 0308 and.w r3, r3, #8 - 8006628: 2b08 cmp r3, #8 - 800662a: d110 bne.n 800664e + 8006666: 68fb ldr r3, [r7, #12] + 8006668: 681b ldr r3, [r3, #0] + 800666a: 69db ldr r3, [r3, #28] + 800666c: f003 0308 and.w r3, r3, #8 + 8006670: 2b08 cmp r3, #8 + 8006672: d110 bne.n 8006696 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - 800662c: 68fb ldr r3, [r7, #12] - 800662e: 681b ldr r3, [r3, #0] - 8006630: 2208 movs r2, #8 - 8006632: 621a str r2, [r3, #32] + 8006674: 68fb ldr r3, [r7, #12] + 8006676: 681b ldr r3, [r3, #0] + 8006678: 2208 movs r2, #8 + 800667a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8006634: 68f8 ldr r0, [r7, #12] - 8006636: f000 f95b bl 80068f0 + 800667c: 68f8 ldr r0, [r7, #12] + 800667e: f000 f95b bl 8006938 huart->ErrorCode = HAL_UART_ERROR_ORE; - 800663a: 68fb ldr r3, [r7, #12] - 800663c: 2208 movs r2, #8 - 800663e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8006682: 68fb ldr r3, [r7, #12] + 8006684: 2208 movs r2, #8 + 8006686: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8006642: 68fb ldr r3, [r7, #12] - 8006644: 2200 movs r2, #0 - 8006646: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 800668a: 68fb ldr r3, [r7, #12] + 800668c: 2200 movs r2, #0 + 800668e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; - 800664a: 2301 movs r3, #1 - 800664c: e029 b.n 80066a2 + 8006692: 2301 movs r3, #1 + 8006694: e029 b.n 80066ea } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 800664e: 68fb ldr r3, [r7, #12] - 8006650: 681b ldr r3, [r3, #0] - 8006652: 69db ldr r3, [r3, #28] - 8006654: f403 6300 and.w r3, r3, #2048 @ 0x800 - 8006658: f5b3 6f00 cmp.w r3, #2048 @ 0x800 - 800665c: d111 bne.n 8006682 + 8006696: 68fb ldr r3, [r7, #12] + 8006698: 681b ldr r3, [r3, #0] + 800669a: 69db ldr r3, [r3, #28] + 800669c: f403 6300 and.w r3, r3, #2048 @ 0x800 + 80066a0: f5b3 6f00 cmp.w r3, #2048 @ 0x800 + 80066a4: d111 bne.n 80066ca { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 800665e: 68fb ldr r3, [r7, #12] - 8006660: 681b ldr r3, [r3, #0] - 8006662: f44f 6200 mov.w r2, #2048 @ 0x800 - 8006666: 621a str r2, [r3, #32] + 80066a6: 68fb ldr r3, [r7, #12] + 80066a8: 681b ldr r3, [r3, #0] + 80066aa: f44f 6200 mov.w r2, #2048 @ 0x800 + 80066ae: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); - 8006668: 68f8 ldr r0, [r7, #12] - 800666a: f000 f941 bl 80068f0 + 80066b0: 68f8 ldr r0, [r7, #12] + 80066b2: f000 f941 bl 8006938 huart->ErrorCode = HAL_UART_ERROR_RTO; - 800666e: 68fb ldr r3, [r7, #12] - 8006670: 2220 movs r2, #32 - 8006672: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 80066b6: 68fb ldr r3, [r7, #12] + 80066b8: 2220 movs r2, #32 + 80066ba: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8006676: 68fb ldr r3, [r7, #12] - 8006678: 2200 movs r2, #0 - 800667a: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 80066be: 68fb ldr r3, [r7, #12] + 80066c0: 2200 movs r2, #0 + 80066c2: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; - 800667e: 2303 movs r3, #3 - 8006680: e00f b.n 80066a2 + 80066c6: 2303 movs r3, #3 + 80066c8: e00f b.n 80066ea while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8006682: 68fb ldr r3, [r7, #12] - 8006684: 681b ldr r3, [r3, #0] - 8006686: 69da ldr r2, [r3, #28] - 8006688: 68bb ldr r3, [r7, #8] - 800668a: 4013 ands r3, r2 - 800668c: 68ba ldr r2, [r7, #8] - 800668e: 429a cmp r2, r3 - 8006690: bf0c ite eq - 8006692: 2301 moveq r3, #1 - 8006694: 2300 movne r3, #0 - 8006696: b2db uxtb r3, r3 - 8006698: 461a mov r2, r3 - 800669a: 79fb ldrb r3, [r7, #7] - 800669c: 429a cmp r2, r3 - 800669e: d0a0 beq.n 80065e2 + 80066ca: 68fb ldr r3, [r7, #12] + 80066cc: 681b ldr r3, [r3, #0] + 80066ce: 69da ldr r2, [r3, #28] + 80066d0: 68bb ldr r3, [r7, #8] + 80066d2: 4013 ands r3, r2 + 80066d4: 68ba ldr r2, [r7, #8] + 80066d6: 429a cmp r2, r3 + 80066d8: bf0c ite eq + 80066da: 2301 moveq r3, #1 + 80066dc: 2300 movne r3, #0 + 80066de: b2db uxtb r3, r3 + 80066e0: 461a mov r2, r3 + 80066e2: 79fb ldrb r3, [r7, #7] + 80066e4: 429a cmp r2, r3 + 80066e6: d0a0 beq.n 800662a } } } } return HAL_OK; - 80066a0: 2300 movs r3, #0 + 80066e8: 2300 movs r3, #0 } - 80066a2: 4618 mov r0, r3 - 80066a4: 3710 adds r7, #16 - 80066a6: 46bd mov sp, r7 - 80066a8: bd80 pop {r7, pc} + 80066ea: 4618 mov r0, r3 + 80066ec: 3710 adds r7, #16 + 80066ee: 46bd mov sp, r7 + 80066f0: bd80 pop {r7, pc} ... -080066ac : +080066f4 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - 80066ac: b480 push {r7} - 80066ae: b0a3 sub sp, #140 @ 0x8c - 80066b0: af00 add r7, sp, #0 - 80066b2: 60f8 str r0, [r7, #12] - 80066b4: 60b9 str r1, [r7, #8] - 80066b6: 4613 mov r3, r2 - 80066b8: 80fb strh r3, [r7, #6] + 80066f4: b480 push {r7} + 80066f6: b0a3 sub sp, #140 @ 0x8c + 80066f8: af00 add r7, sp, #0 + 80066fa: 60f8 str r0, [r7, #12] + 80066fc: 60b9 str r1, [r7, #8] + 80066fe: 4613 mov r3, r2 + 8006700: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; - 80066ba: 68fb ldr r3, [r7, #12] - 80066bc: 68ba ldr r2, [r7, #8] - 80066be: 659a str r2, [r3, #88] @ 0x58 + 8006702: 68fb ldr r3, [r7, #12] + 8006704: 68ba ldr r2, [r7, #8] + 8006706: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; - 80066c0: 68fb ldr r3, [r7, #12] - 80066c2: 88fa ldrh r2, [r7, #6] - 80066c4: f8a3 205c strh.w r2, [r3, #92] @ 0x5c + 8006708: 68fb ldr r3, [r7, #12] + 800670a: 88fa ldrh r2, [r7, #6] + 800670c: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; - 80066c8: 68fb ldr r3, [r7, #12] - 80066ca: 88fa ldrh r2, [r7, #6] - 80066cc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 8006710: 68fb ldr r3, [r7, #12] + 8006712: 88fa ldrh r2, [r7, #6] + 8006714: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; - 80066d0: 68fb ldr r3, [r7, #12] - 80066d2: 2200 movs r2, #0 - 80066d4: 675a str r2, [r3, #116] @ 0x74 + 8006718: 68fb ldr r3, [r7, #12] + 800671a: 2200 movs r2, #0 + 800671c: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); - 80066d6: 68fb ldr r3, [r7, #12] - 80066d8: 689b ldr r3, [r3, #8] - 80066da: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 80066de: d10e bne.n 80066fe - 80066e0: 68fb ldr r3, [r7, #12] - 80066e2: 691b ldr r3, [r3, #16] - 80066e4: 2b00 cmp r3, #0 - 80066e6: d105 bne.n 80066f4 - 80066e8: 68fb ldr r3, [r7, #12] - 80066ea: f240 12ff movw r2, #511 @ 0x1ff - 80066ee: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 - 80066f2: e02d b.n 8006750 - 80066f4: 68fb ldr r3, [r7, #12] - 80066f6: 22ff movs r2, #255 @ 0xff - 80066f8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 - 80066fc: e028 b.n 8006750 - 80066fe: 68fb ldr r3, [r7, #12] - 8006700: 689b ldr r3, [r3, #8] - 8006702: 2b00 cmp r3, #0 - 8006704: d10d bne.n 8006722 - 8006706: 68fb ldr r3, [r7, #12] - 8006708: 691b ldr r3, [r3, #16] - 800670a: 2b00 cmp r3, #0 - 800670c: d104 bne.n 8006718 - 800670e: 68fb ldr r3, [r7, #12] - 8006710: 22ff movs r2, #255 @ 0xff - 8006712: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 - 8006716: e01b b.n 8006750 - 8006718: 68fb ldr r3, [r7, #12] - 800671a: 227f movs r2, #127 @ 0x7f - 800671c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 - 8006720: e016 b.n 8006750 - 8006722: 68fb ldr r3, [r7, #12] - 8006724: 689b ldr r3, [r3, #8] - 8006726: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 - 800672a: d10d bne.n 8006748 - 800672c: 68fb ldr r3, [r7, #12] - 800672e: 691b ldr r3, [r3, #16] - 8006730: 2b00 cmp r3, #0 - 8006732: d104 bne.n 800673e - 8006734: 68fb ldr r3, [r7, #12] - 8006736: 227f movs r2, #127 @ 0x7f - 8006738: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 - 800673c: e008 b.n 8006750 - 800673e: 68fb ldr r3, [r7, #12] - 8006740: 223f movs r2, #63 @ 0x3f - 8006742: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 - 8006746: e003 b.n 8006750 - 8006748: 68fb ldr r3, [r7, #12] - 800674a: 2200 movs r2, #0 - 800674c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 800671e: 68fb ldr r3, [r7, #12] + 8006720: 689b ldr r3, [r3, #8] + 8006722: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8006726: d10e bne.n 8006746 + 8006728: 68fb ldr r3, [r7, #12] + 800672a: 691b ldr r3, [r3, #16] + 800672c: 2b00 cmp r3, #0 + 800672e: d105 bne.n 800673c + 8006730: 68fb ldr r3, [r7, #12] + 8006732: f240 12ff movw r2, #511 @ 0x1ff + 8006736: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 800673a: e02d b.n 8006798 + 800673c: 68fb ldr r3, [r7, #12] + 800673e: 22ff movs r2, #255 @ 0xff + 8006740: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006744: e028 b.n 8006798 + 8006746: 68fb ldr r3, [r7, #12] + 8006748: 689b ldr r3, [r3, #8] + 800674a: 2b00 cmp r3, #0 + 800674c: d10d bne.n 800676a + 800674e: 68fb ldr r3, [r7, #12] + 8006750: 691b ldr r3, [r3, #16] + 8006752: 2b00 cmp r3, #0 + 8006754: d104 bne.n 8006760 + 8006756: 68fb ldr r3, [r7, #12] + 8006758: 22ff movs r2, #255 @ 0xff + 800675a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 800675e: e01b b.n 8006798 + 8006760: 68fb ldr r3, [r7, #12] + 8006762: 227f movs r2, #127 @ 0x7f + 8006764: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006768: e016 b.n 8006798 + 800676a: 68fb ldr r3, [r7, #12] + 800676c: 689b ldr r3, [r3, #8] + 800676e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 + 8006772: d10d bne.n 8006790 + 8006774: 68fb ldr r3, [r7, #12] + 8006776: 691b ldr r3, [r3, #16] + 8006778: 2b00 cmp r3, #0 + 800677a: d104 bne.n 8006786 + 800677c: 68fb ldr r3, [r7, #12] + 800677e: 227f movs r2, #127 @ 0x7f + 8006780: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 8006784: e008 b.n 8006798 + 8006786: 68fb ldr r3, [r7, #12] + 8006788: 223f movs r2, #63 @ 0x3f + 800678a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 + 800678e: e003 b.n 8006798 + 8006790: 68fb ldr r3, [r7, #12] + 8006792: 2200 movs r2, #0 + 8006794: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; - 8006750: 68fb ldr r3, [r7, #12] - 8006752: 2200 movs r2, #0 - 8006754: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8006798: 68fb ldr r3, [r7, #12] + 800679a: 2200 movs r2, #0 + 800679c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; - 8006758: 68fb ldr r3, [r7, #12] - 800675a: 2222 movs r2, #34 @ 0x22 - 800675c: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 80067a0: 68fb ldr r3, [r7, #12] + 80067a2: 2222 movs r2, #34 @ 0x22 + 80067a4: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8006760: 68fb ldr r3, [r7, #12] - 8006762: 681b ldr r3, [r3, #0] - 8006764: 3308 adds r3, #8 - 8006766: 667b str r3, [r7, #100] @ 0x64 + 80067a8: 68fb ldr r3, [r7, #12] + 80067aa: 681b ldr r3, [r3, #0] + 80067ac: 3308 adds r3, #8 + 80067ae: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006768: 6e7b ldr r3, [r7, #100] @ 0x64 - 800676a: e853 3f00 ldrex r3, [r3] - 800676e: 663b str r3, [r7, #96] @ 0x60 + 80067b0: 6e7b ldr r3, [r7, #100] @ 0x64 + 80067b2: e853 3f00 ldrex r3, [r3] + 80067b6: 663b str r3, [r7, #96] @ 0x60 return(result); - 8006770: 6e3b ldr r3, [r7, #96] @ 0x60 - 8006772: f043 0301 orr.w r3, r3, #1 - 8006776: f8c7 3084 str.w r3, [r7, #132] @ 0x84 - 800677a: 68fb ldr r3, [r7, #12] - 800677c: 681b ldr r3, [r3, #0] - 800677e: 3308 adds r3, #8 - 8006780: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 - 8006784: 673a str r2, [r7, #112] @ 0x70 - 8006786: 66fb str r3, [r7, #108] @ 0x6c + 80067b8: 6e3b ldr r3, [r7, #96] @ 0x60 + 80067ba: f043 0301 orr.w r3, r3, #1 + 80067be: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 80067c2: 68fb ldr r3, [r7, #12] + 80067c4: 681b ldr r3, [r3, #0] + 80067c6: 3308 adds r3, #8 + 80067c8: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 + 80067cc: 673a str r2, [r7, #112] @ 0x70 + 80067ce: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006788: 6ef9 ldr r1, [r7, #108] @ 0x6c - 800678a: 6f3a ldr r2, [r7, #112] @ 0x70 - 800678c: e841 2300 strex r3, r2, [r1] - 8006790: 66bb str r3, [r7, #104] @ 0x68 + 80067d0: 6ef9 ldr r1, [r7, #108] @ 0x6c + 80067d2: 6f3a ldr r2, [r7, #112] @ 0x70 + 80067d4: e841 2300 strex r3, r2, [r1] + 80067d8: 66bb str r3, [r7, #104] @ 0x68 return(result); - 8006792: 6ebb ldr r3, [r7, #104] @ 0x68 - 8006794: 2b00 cmp r3, #0 - 8006796: d1e3 bne.n 8006760 + 80067da: 6ebb ldr r3, [r7, #104] @ 0x68 + 80067dc: 2b00 cmp r3, #0 + 80067de: d1e3 bne.n 80067a8 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) - 8006798: 68fb ldr r3, [r7, #12] - 800679a: 6e5b ldr r3, [r3, #100] @ 0x64 - 800679c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 - 80067a0: d14f bne.n 8006842 - 80067a2: 68fb ldr r3, [r7, #12] - 80067a4: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 - 80067a8: 88fa ldrh r2, [r7, #6] - 80067aa: 429a cmp r2, r3 - 80067ac: d349 bcc.n 8006842 + 80067e0: 68fb ldr r3, [r7, #12] + 80067e2: 6e5b ldr r3, [r3, #100] @ 0x64 + 80067e4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 + 80067e8: d14f bne.n 800688a + 80067ea: 68fb ldr r3, [r7, #12] + 80067ec: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 80067f0: 88fa ldrh r2, [r7, #6] + 80067f2: 429a cmp r2, r3 + 80067f4: d349 bcc.n 800688a { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 80067ae: 68fb ldr r3, [r7, #12] - 80067b0: 689b ldr r3, [r3, #8] - 80067b2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 80067b6: d107 bne.n 80067c8 - 80067b8: 68fb ldr r3, [r7, #12] - 80067ba: 691b ldr r3, [r3, #16] - 80067bc: 2b00 cmp r3, #0 - 80067be: d103 bne.n 80067c8 + 80067f6: 68fb ldr r3, [r7, #12] + 80067f8: 689b ldr r3, [r3, #8] + 80067fa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 80067fe: d107 bne.n 8006810 + 8006800: 68fb ldr r3, [r7, #12] + 8006802: 691b ldr r3, [r3, #16] + 8006804: 2b00 cmp r3, #0 + 8006806: d103 bne.n 8006810 { huart->RxISR = UART_RxISR_16BIT_FIFOEN; - 80067c0: 68fb ldr r3, [r7, #12] - 80067c2: 4a47 ldr r2, [pc, #284] @ (80068e0 ) - 80067c4: 675a str r2, [r3, #116] @ 0x74 - 80067c6: e002 b.n 80067ce + 8006808: 68fb ldr r3, [r7, #12] + 800680a: 4a47 ldr r2, [pc, #284] @ (8006928 ) + 800680c: 675a str r2, [r3, #116] @ 0x74 + 800680e: e002 b.n 8006816 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; - 80067c8: 68fb ldr r3, [r7, #12] - 80067ca: 4a46 ldr r2, [pc, #280] @ (80068e4 ) - 80067cc: 675a str r2, [r3, #116] @ 0x74 + 8006810: 68fb ldr r3, [r7, #12] + 8006812: 4a46 ldr r2, [pc, #280] @ (800692c ) + 8006814: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) - 80067ce: 68fb ldr r3, [r7, #12] - 80067d0: 691b ldr r3, [r3, #16] - 80067d2: 2b00 cmp r3, #0 - 80067d4: d01a beq.n 800680c + 8006816: 68fb ldr r3, [r7, #12] + 8006818: 691b ldr r3, [r3, #16] + 800681a: 2b00 cmp r3, #0 + 800681c: d01a beq.n 8006854 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 80067d6: 68fb ldr r3, [r7, #12] - 80067d8: 681b ldr r3, [r3, #0] - 80067da: 653b str r3, [r7, #80] @ 0x50 + 800681e: 68fb ldr r3, [r7, #12] + 8006820: 681b ldr r3, [r3, #0] + 8006822: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80067dc: 6d3b ldr r3, [r7, #80] @ 0x50 - 80067de: e853 3f00 ldrex r3, [r3] - 80067e2: 64fb str r3, [r7, #76] @ 0x4c + 8006824: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006826: e853 3f00 ldrex r3, [r3] + 800682a: 64fb str r3, [r7, #76] @ 0x4c return(result); - 80067e4: 6cfb ldr r3, [r7, #76] @ 0x4c - 80067e6: f443 7380 orr.w r3, r3, #256 @ 0x100 - 80067ea: f8c7 3080 str.w r3, [r7, #128] @ 0x80 - 80067ee: 68fb ldr r3, [r7, #12] - 80067f0: 681b ldr r3, [r3, #0] - 80067f2: 461a mov r2, r3 - 80067f4: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 - 80067f8: 65fb str r3, [r7, #92] @ 0x5c - 80067fa: 65ba str r2, [r7, #88] @ 0x58 + 800682c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800682e: f443 7380 orr.w r3, r3, #256 @ 0x100 + 8006832: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 8006836: 68fb ldr r3, [r7, #12] + 8006838: 681b ldr r3, [r3, #0] + 800683a: 461a mov r2, r3 + 800683c: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 8006840: 65fb str r3, [r7, #92] @ 0x5c + 8006842: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80067fc: 6db9 ldr r1, [r7, #88] @ 0x58 - 80067fe: 6dfa ldr r2, [r7, #92] @ 0x5c - 8006800: e841 2300 strex r3, r2, [r1] - 8006804: 657b str r3, [r7, #84] @ 0x54 + 8006844: 6db9 ldr r1, [r7, #88] @ 0x58 + 8006846: 6dfa ldr r2, [r7, #92] @ 0x5c + 8006848: e841 2300 strex r3, r2, [r1] + 800684c: 657b str r3, [r7, #84] @ 0x54 return(result); - 8006806: 6d7b ldr r3, [r7, #84] @ 0x54 - 8006808: 2b00 cmp r3, #0 - 800680a: d1e4 bne.n 80067d6 + 800684e: 6d7b ldr r3, [r7, #84] @ 0x54 + 8006850: 2b00 cmp r3, #0 + 8006852: d1e4 bne.n 800681e } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - 800680c: 68fb ldr r3, [r7, #12] - 800680e: 681b ldr r3, [r3, #0] - 8006810: 3308 adds r3, #8 - 8006812: 63fb str r3, [r7, #60] @ 0x3c + 8006854: 68fb ldr r3, [r7, #12] + 8006856: 681b ldr r3, [r3, #0] + 8006858: 3308 adds r3, #8 + 800685a: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006814: 6bfb ldr r3, [r7, #60] @ 0x3c - 8006816: e853 3f00 ldrex r3, [r3] - 800681a: 63bb str r3, [r7, #56] @ 0x38 + 800685c: 6bfb ldr r3, [r7, #60] @ 0x3c + 800685e: e853 3f00 ldrex r3, [r3] + 8006862: 63bb str r3, [r7, #56] @ 0x38 return(result); - 800681c: 6bbb ldr r3, [r7, #56] @ 0x38 - 800681e: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 - 8006822: 67fb str r3, [r7, #124] @ 0x7c - 8006824: 68fb ldr r3, [r7, #12] - 8006826: 681b ldr r3, [r3, #0] - 8006828: 3308 adds r3, #8 - 800682a: 6ffa ldr r2, [r7, #124] @ 0x7c - 800682c: 64ba str r2, [r7, #72] @ 0x48 - 800682e: 647b str r3, [r7, #68] @ 0x44 + 8006864: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006866: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 + 800686a: 67fb str r3, [r7, #124] @ 0x7c + 800686c: 68fb ldr r3, [r7, #12] + 800686e: 681b ldr r3, [r3, #0] + 8006870: 3308 adds r3, #8 + 8006872: 6ffa ldr r2, [r7, #124] @ 0x7c + 8006874: 64ba str r2, [r7, #72] @ 0x48 + 8006876: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006830: 6c79 ldr r1, [r7, #68] @ 0x44 - 8006832: 6cba ldr r2, [r7, #72] @ 0x48 - 8006834: e841 2300 strex r3, r2, [r1] - 8006838: 643b str r3, [r7, #64] @ 0x40 + 8006878: 6c79 ldr r1, [r7, #68] @ 0x44 + 800687a: 6cba ldr r2, [r7, #72] @ 0x48 + 800687c: e841 2300 strex r3, r2, [r1] + 8006880: 643b str r3, [r7, #64] @ 0x40 return(result); - 800683a: 6c3b ldr r3, [r7, #64] @ 0x40 - 800683c: 2b00 cmp r3, #0 - 800683e: d1e5 bne.n 800680c - 8006840: e046 b.n 80068d0 + 8006882: 6c3b ldr r3, [r7, #64] @ 0x40 + 8006884: 2b00 cmp r3, #0 + 8006886: d1e5 bne.n 8006854 + 8006888: e046 b.n 8006918 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 8006842: 68fb ldr r3, [r7, #12] - 8006844: 689b ldr r3, [r3, #8] - 8006846: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 - 800684a: d107 bne.n 800685c - 800684c: 68fb ldr r3, [r7, #12] - 800684e: 691b ldr r3, [r3, #16] - 8006850: 2b00 cmp r3, #0 - 8006852: d103 bne.n 800685c + 800688a: 68fb ldr r3, [r7, #12] + 800688c: 689b ldr r3, [r3, #8] + 800688e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 + 8006892: d107 bne.n 80068a4 + 8006894: 68fb ldr r3, [r7, #12] + 8006896: 691b ldr r3, [r3, #16] + 8006898: 2b00 cmp r3, #0 + 800689a: d103 bne.n 80068a4 { huart->RxISR = UART_RxISR_16BIT; - 8006854: 68fb ldr r3, [r7, #12] - 8006856: 4a24 ldr r2, [pc, #144] @ (80068e8 ) - 8006858: 675a str r2, [r3, #116] @ 0x74 - 800685a: e002 b.n 8006862 + 800689c: 68fb ldr r3, [r7, #12] + 800689e: 4a24 ldr r2, [pc, #144] @ (8006930 ) + 80068a0: 675a str r2, [r3, #116] @ 0x74 + 80068a2: e002 b.n 80068aa } else { huart->RxISR = UART_RxISR_8BIT; - 800685c: 68fb ldr r3, [r7, #12] - 800685e: 4a23 ldr r2, [pc, #140] @ (80068ec ) - 8006860: 675a str r2, [r3, #116] @ 0x74 + 80068a4: 68fb ldr r3, [r7, #12] + 80068a6: 4a23 ldr r2, [pc, #140] @ (8006934 ) + 80068a8: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) - 8006862: 68fb ldr r3, [r7, #12] - 8006864: 691b ldr r3, [r3, #16] - 8006866: 2b00 cmp r3, #0 - 8006868: d019 beq.n 800689e + 80068aa: 68fb ldr r3, [r7, #12] + 80068ac: 691b ldr r3, [r3, #16] + 80068ae: 2b00 cmp r3, #0 + 80068b0: d019 beq.n 80068e6 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); - 800686a: 68fb ldr r3, [r7, #12] - 800686c: 681b ldr r3, [r3, #0] - 800686e: 62bb str r3, [r7, #40] @ 0x28 + 80068b2: 68fb ldr r3, [r7, #12] + 80068b4: 681b ldr r3, [r3, #0] + 80068b6: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006870: 6abb ldr r3, [r7, #40] @ 0x28 - 8006872: e853 3f00 ldrex r3, [r3] - 8006876: 627b str r3, [r7, #36] @ 0x24 + 80068b8: 6abb ldr r3, [r7, #40] @ 0x28 + 80068ba: e853 3f00 ldrex r3, [r3] + 80068be: 627b str r3, [r7, #36] @ 0x24 return(result); - 8006878: 6a7b ldr r3, [r7, #36] @ 0x24 - 800687a: f443 7390 orr.w r3, r3, #288 @ 0x120 - 800687e: 677b str r3, [r7, #116] @ 0x74 - 8006880: 68fb ldr r3, [r7, #12] - 8006882: 681b ldr r3, [r3, #0] - 8006884: 461a mov r2, r3 - 8006886: 6f7b ldr r3, [r7, #116] @ 0x74 - 8006888: 637b str r3, [r7, #52] @ 0x34 - 800688a: 633a str r2, [r7, #48] @ 0x30 + 80068c0: 6a7b ldr r3, [r7, #36] @ 0x24 + 80068c2: f443 7390 orr.w r3, r3, #288 @ 0x120 + 80068c6: 677b str r3, [r7, #116] @ 0x74 + 80068c8: 68fb ldr r3, [r7, #12] + 80068ca: 681b ldr r3, [r3, #0] + 80068cc: 461a mov r2, r3 + 80068ce: 6f7b ldr r3, [r7, #116] @ 0x74 + 80068d0: 637b str r3, [r7, #52] @ 0x34 + 80068d2: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800688c: 6b39 ldr r1, [r7, #48] @ 0x30 - 800688e: 6b7a ldr r2, [r7, #52] @ 0x34 - 8006890: e841 2300 strex r3, r2, [r1] - 8006894: 62fb str r3, [r7, #44] @ 0x2c + 80068d4: 6b39 ldr r1, [r7, #48] @ 0x30 + 80068d6: 6b7a ldr r2, [r7, #52] @ 0x34 + 80068d8: e841 2300 strex r3, r2, [r1] + 80068dc: 62fb str r3, [r7, #44] @ 0x2c return(result); - 8006896: 6afb ldr r3, [r7, #44] @ 0x2c - 8006898: 2b00 cmp r3, #0 - 800689a: d1e6 bne.n 800686a - 800689c: e018 b.n 80068d0 + 80068de: 6afb ldr r3, [r7, #44] @ 0x2c + 80068e0: 2b00 cmp r3, #0 + 80068e2: d1e6 bne.n 80068b2 + 80068e4: e018 b.n 8006918 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - 800689e: 68fb ldr r3, [r7, #12] - 80068a0: 681b ldr r3, [r3, #0] - 80068a2: 617b str r3, [r7, #20] + 80068e6: 68fb ldr r3, [r7, #12] + 80068e8: 681b ldr r3, [r3, #0] + 80068ea: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80068a4: 697b ldr r3, [r7, #20] - 80068a6: e853 3f00 ldrex r3, [r3] - 80068aa: 613b str r3, [r7, #16] + 80068ec: 697b ldr r3, [r7, #20] + 80068ee: e853 3f00 ldrex r3, [r3] + 80068f2: 613b str r3, [r7, #16] return(result); - 80068ac: 693b ldr r3, [r7, #16] - 80068ae: f043 0320 orr.w r3, r3, #32 - 80068b2: 67bb str r3, [r7, #120] @ 0x78 - 80068b4: 68fb ldr r3, [r7, #12] - 80068b6: 681b ldr r3, [r3, #0] - 80068b8: 461a mov r2, r3 - 80068ba: 6fbb ldr r3, [r7, #120] @ 0x78 - 80068bc: 623b str r3, [r7, #32] - 80068be: 61fa str r2, [r7, #28] + 80068f4: 693b ldr r3, [r7, #16] + 80068f6: f043 0320 orr.w r3, r3, #32 + 80068fa: 67bb str r3, [r7, #120] @ 0x78 + 80068fc: 68fb ldr r3, [r7, #12] + 80068fe: 681b ldr r3, [r3, #0] + 8006900: 461a mov r2, r3 + 8006902: 6fbb ldr r3, [r7, #120] @ 0x78 + 8006904: 623b str r3, [r7, #32] + 8006906: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80068c0: 69f9 ldr r1, [r7, #28] - 80068c2: 6a3a ldr r2, [r7, #32] - 80068c4: e841 2300 strex r3, r2, [r1] - 80068c8: 61bb str r3, [r7, #24] + 8006908: 69f9 ldr r1, [r7, #28] + 800690a: 6a3a ldr r2, [r7, #32] + 800690c: e841 2300 strex r3, r2, [r1] + 8006910: 61bb str r3, [r7, #24] return(result); - 80068ca: 69bb ldr r3, [r7, #24] - 80068cc: 2b00 cmp r3, #0 - 80068ce: d1e6 bne.n 800689e + 8006912: 69bb ldr r3, [r7, #24] + 8006914: 2b00 cmp r3, #0 + 8006916: d1e6 bne.n 80068e6 } } return HAL_OK; - 80068d0: 2300 movs r3, #0 + 8006918: 2300 movs r3, #0 } - 80068d2: 4618 mov r0, r3 - 80068d4: 378c adds r7, #140 @ 0x8c - 80068d6: 46bd mov sp, r7 - 80068d8: f85d 7b04 ldr.w r7, [sp], #4 - 80068dc: 4770 bx lr - 80068de: bf00 nop - 80068e0: 0800710d .word 0x0800710d - 80068e4: 08006da9 .word 0x08006da9 - 80068e8: 08006bf1 .word 0x08006bf1 - 80068ec: 08006a39 .word 0x08006a39 + 800691a: 4618 mov r0, r3 + 800691c: 378c adds r7, #140 @ 0x8c + 800691e: 46bd mov sp, r7 + 8006920: f85d 7b04 ldr.w r7, [sp], #4 + 8006924: 4770 bx lr + 8006926: bf00 nop + 8006928: 08007155 .word 0x08007155 + 800692c: 08006df1 .word 0x08006df1 + 8006930: 08006c39 .word 0x08006c39 + 8006934: 08006a81 .word 0x08006a81 -080068f0 : +08006938 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { - 80068f0: b480 push {r7} - 80068f2: b095 sub sp, #84 @ 0x54 - 80068f4: af00 add r7, sp, #0 - 80068f6: 6078 str r0, [r7, #4] + 8006938: b480 push {r7} + 800693a: b095 sub sp, #84 @ 0x54 + 800693c: af00 add r7, sp, #0 + 800693e: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 80068f8: 687b ldr r3, [r7, #4] - 80068fa: 681b ldr r3, [r3, #0] - 80068fc: 637b str r3, [r7, #52] @ 0x34 + 8006940: 687b ldr r3, [r7, #4] + 8006942: 681b ldr r3, [r3, #0] + 8006944: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80068fe: 6b7b ldr r3, [r7, #52] @ 0x34 - 8006900: e853 3f00 ldrex r3, [r3] - 8006904: 633b str r3, [r7, #48] @ 0x30 + 8006946: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006948: e853 3f00 ldrex r3, [r3] + 800694c: 633b str r3, [r7, #48] @ 0x30 return(result); - 8006906: 6b3b ldr r3, [r7, #48] @ 0x30 - 8006908: f423 7390 bic.w r3, r3, #288 @ 0x120 - 800690c: 64fb str r3, [r7, #76] @ 0x4c - 800690e: 687b ldr r3, [r7, #4] - 8006910: 681b ldr r3, [r3, #0] - 8006912: 461a mov r2, r3 - 8006914: 6cfb ldr r3, [r7, #76] @ 0x4c - 8006916: 643b str r3, [r7, #64] @ 0x40 - 8006918: 63fa str r2, [r7, #60] @ 0x3c + 800694e: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006950: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006954: 64fb str r3, [r7, #76] @ 0x4c + 8006956: 687b ldr r3, [r7, #4] + 8006958: 681b ldr r3, [r3, #0] + 800695a: 461a mov r2, r3 + 800695c: 6cfb ldr r3, [r7, #76] @ 0x4c + 800695e: 643b str r3, [r7, #64] @ 0x40 + 8006960: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800691a: 6bf9 ldr r1, [r7, #60] @ 0x3c - 800691c: 6c3a ldr r2, [r7, #64] @ 0x40 - 800691e: e841 2300 strex r3, r2, [r1] - 8006922: 63bb str r3, [r7, #56] @ 0x38 + 8006962: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8006964: 6c3a ldr r2, [r7, #64] @ 0x40 + 8006966: e841 2300 strex r3, r2, [r1] + 800696a: 63bb str r3, [r7, #56] @ 0x38 return(result); - 8006924: 6bbb ldr r3, [r7, #56] @ 0x38 - 8006926: 2b00 cmp r3, #0 - 8006928: d1e6 bne.n 80068f8 + 800696c: 6bbb ldr r3, [r7, #56] @ 0x38 + 800696e: 2b00 cmp r3, #0 + 8006970: d1e6 bne.n 8006940 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - 800692a: 687b ldr r3, [r7, #4] - 800692c: 681b ldr r3, [r3, #0] - 800692e: 3308 adds r3, #8 - 8006930: 623b str r3, [r7, #32] + 8006972: 687b ldr r3, [r7, #4] + 8006974: 681b ldr r3, [r3, #0] + 8006976: 3308 adds r3, #8 + 8006978: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006932: 6a3b ldr r3, [r7, #32] - 8006934: e853 3f00 ldrex r3, [r3] - 8006938: 61fb str r3, [r7, #28] + 800697a: 6a3b ldr r3, [r7, #32] + 800697c: e853 3f00 ldrex r3, [r3] + 8006980: 61fb str r3, [r7, #28] return(result); - 800693a: 69fb ldr r3, [r7, #28] - 800693c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8006940: f023 0301 bic.w r3, r3, #1 - 8006944: 64bb str r3, [r7, #72] @ 0x48 - 8006946: 687b ldr r3, [r7, #4] - 8006948: 681b ldr r3, [r3, #0] - 800694a: 3308 adds r3, #8 - 800694c: 6cba ldr r2, [r7, #72] @ 0x48 - 800694e: 62fa str r2, [r7, #44] @ 0x2c - 8006950: 62bb str r3, [r7, #40] @ 0x28 + 8006982: 69fb ldr r3, [r7, #28] + 8006984: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8006988: f023 0301 bic.w r3, r3, #1 + 800698c: 64bb str r3, [r7, #72] @ 0x48 + 800698e: 687b ldr r3, [r7, #4] + 8006990: 681b ldr r3, [r3, #0] + 8006992: 3308 adds r3, #8 + 8006994: 6cba ldr r2, [r7, #72] @ 0x48 + 8006996: 62fa str r2, [r7, #44] @ 0x2c + 8006998: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006952: 6ab9 ldr r1, [r7, #40] @ 0x28 - 8006954: 6afa ldr r2, [r7, #44] @ 0x2c - 8006956: e841 2300 strex r3, r2, [r1] - 800695a: 627b str r3, [r7, #36] @ 0x24 + 800699a: 6ab9 ldr r1, [r7, #40] @ 0x28 + 800699c: 6afa ldr r2, [r7, #44] @ 0x2c + 800699e: e841 2300 strex r3, r2, [r1] + 80069a2: 627b str r3, [r7, #36] @ 0x24 return(result); - 800695c: 6a7b ldr r3, [r7, #36] @ 0x24 - 800695e: 2b00 cmp r3, #0 - 8006960: d1e3 bne.n 800692a + 80069a4: 6a7b ldr r3, [r7, #36] @ 0x24 + 80069a6: 2b00 cmp r3, #0 + 80069a8: d1e3 bne.n 8006972 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8006962: 687b ldr r3, [r7, #4] - 8006964: 6edb ldr r3, [r3, #108] @ 0x6c - 8006966: 2b01 cmp r3, #1 - 8006968: d118 bne.n 800699c + 80069aa: 687b ldr r3, [r7, #4] + 80069ac: 6edb ldr r3, [r3, #108] @ 0x6c + 80069ae: 2b01 cmp r3, #1 + 80069b0: d118 bne.n 80069e4 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 800696a: 687b ldr r3, [r7, #4] - 800696c: 681b ldr r3, [r3, #0] - 800696e: 60fb str r3, [r7, #12] + 80069b2: 687b ldr r3, [r7, #4] + 80069b4: 681b ldr r3, [r3, #0] + 80069b6: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006970: 68fb ldr r3, [r7, #12] - 8006972: e853 3f00 ldrex r3, [r3] - 8006976: 60bb str r3, [r7, #8] + 80069b8: 68fb ldr r3, [r7, #12] + 80069ba: e853 3f00 ldrex r3, [r3] + 80069be: 60bb str r3, [r7, #8] return(result); - 8006978: 68bb ldr r3, [r7, #8] - 800697a: f023 0310 bic.w r3, r3, #16 - 800697e: 647b str r3, [r7, #68] @ 0x44 - 8006980: 687b ldr r3, [r7, #4] - 8006982: 681b ldr r3, [r3, #0] - 8006984: 461a mov r2, r3 - 8006986: 6c7b ldr r3, [r7, #68] @ 0x44 - 8006988: 61bb str r3, [r7, #24] - 800698a: 617a str r2, [r7, #20] + 80069c0: 68bb ldr r3, [r7, #8] + 80069c2: f023 0310 bic.w r3, r3, #16 + 80069c6: 647b str r3, [r7, #68] @ 0x44 + 80069c8: 687b ldr r3, [r7, #4] + 80069ca: 681b ldr r3, [r3, #0] + 80069cc: 461a mov r2, r3 + 80069ce: 6c7b ldr r3, [r7, #68] @ 0x44 + 80069d0: 61bb str r3, [r7, #24] + 80069d2: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800698c: 6979 ldr r1, [r7, #20] - 800698e: 69ba ldr r2, [r7, #24] - 8006990: e841 2300 strex r3, r2, [r1] - 8006994: 613b str r3, [r7, #16] + 80069d4: 6979 ldr r1, [r7, #20] + 80069d6: 69ba ldr r2, [r7, #24] + 80069d8: e841 2300 strex r3, r2, [r1] + 80069dc: 613b str r3, [r7, #16] return(result); - 8006996: 693b ldr r3, [r7, #16] - 8006998: 2b00 cmp r3, #0 - 800699a: d1e6 bne.n 800696a + 80069de: 693b ldr r3, [r7, #16] + 80069e0: 2b00 cmp r3, #0 + 80069e2: d1e6 bne.n 80069b2 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 800699c: 687b ldr r3, [r7, #4] - 800699e: 2220 movs r2, #32 - 80069a0: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 80069e4: 687b ldr r3, [r7, #4] + 80069e6: 2220 movs r2, #32 + 80069e8: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80069a4: 687b ldr r3, [r7, #4] - 80069a6: 2200 movs r2, #0 - 80069a8: 66da str r2, [r3, #108] @ 0x6c + 80069ec: 687b ldr r3, [r7, #4] + 80069ee: 2200 movs r2, #0 + 80069f0: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; - 80069aa: 687b ldr r3, [r7, #4] - 80069ac: 2200 movs r2, #0 - 80069ae: 675a str r2, [r3, #116] @ 0x74 + 80069f2: 687b ldr r3, [r7, #4] + 80069f4: 2200 movs r2, #0 + 80069f6: 675a str r2, [r3, #116] @ 0x74 } - 80069b0: bf00 nop - 80069b2: 3754 adds r7, #84 @ 0x54 - 80069b4: 46bd mov sp, r7 - 80069b6: f85d 7b04 ldr.w r7, [sp], #4 - 80069ba: 4770 bx lr + 80069f8: bf00 nop + 80069fa: 3754 adds r7, #84 @ 0x54 + 80069fc: 46bd mov sp, r7 + 80069fe: f85d 7b04 ldr.w r7, [sp], #4 + 8006a02: 4770 bx lr -080069bc : +08006a04 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - 80069bc: b580 push {r7, lr} - 80069be: b084 sub sp, #16 - 80069c0: af00 add r7, sp, #0 - 80069c2: 6078 str r0, [r7, #4] + 8006a04: b580 push {r7, lr} + 8006a06: b084 sub sp, #16 + 8006a08: af00 add r7, sp, #0 + 8006a0a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - 80069c4: 687b ldr r3, [r7, #4] - 80069c6: 6a9b ldr r3, [r3, #40] @ 0x28 - 80069c8: 60fb str r3, [r7, #12] + 8006a0c: 687b ldr r3, [r7, #4] + 8006a0e: 6a9b ldr r3, [r3, #40] @ 0x28 + 8006a10: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; - 80069ca: 68fb ldr r3, [r7, #12] - 80069cc: 2200 movs r2, #0 - 80069ce: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 8006a12: 68fb ldr r3, [r7, #12] + 8006a14: 2200 movs r2, #0 + 8006a16: f8a3 205e strh.w r2, [r3, #94] @ 0x5e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 80069d2: 68f8 ldr r0, [r7, #12] - 80069d4: f7ff f9ce bl 8005d74 + 8006a1a: 68f8 ldr r0, [r7, #12] + 8006a1c: f7ff f9ce bl 8005dbc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - 80069d8: bf00 nop - 80069da: 3710 adds r7, #16 - 80069dc: 46bd mov sp, r7 - 80069de: bd80 pop {r7, pc} + 8006a20: bf00 nop + 8006a22: 3710 adds r7, #16 + 8006a24: 46bd mov sp, r7 + 8006a26: bd80 pop {r7, pc} -080069e0 : +08006a28 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { - 80069e0: b580 push {r7, lr} - 80069e2: b088 sub sp, #32 - 80069e4: af00 add r7, sp, #0 - 80069e6: 6078 str r0, [r7, #4] + 8006a28: b580 push {r7, lr} + 8006a2a: b088 sub sp, #32 + 8006a2c: af00 add r7, sp, #0 + 8006a2e: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - 80069e8: 687b ldr r3, [r7, #4] - 80069ea: 681b ldr r3, [r3, #0] - 80069ec: 60fb str r3, [r7, #12] + 8006a30: 687b ldr r3, [r7, #4] + 8006a32: 681b ldr r3, [r3, #0] + 8006a34: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80069ee: 68fb ldr r3, [r7, #12] - 80069f0: e853 3f00 ldrex r3, [r3] - 80069f4: 60bb str r3, [r7, #8] + 8006a36: 68fb ldr r3, [r7, #12] + 8006a38: e853 3f00 ldrex r3, [r3] + 8006a3c: 60bb str r3, [r7, #8] return(result); - 80069f6: 68bb ldr r3, [r7, #8] - 80069f8: f023 0340 bic.w r3, r3, #64 @ 0x40 - 80069fc: 61fb str r3, [r7, #28] - 80069fe: 687b ldr r3, [r7, #4] - 8006a00: 681b ldr r3, [r3, #0] - 8006a02: 461a mov r2, r3 - 8006a04: 69fb ldr r3, [r7, #28] - 8006a06: 61bb str r3, [r7, #24] - 8006a08: 617a str r2, [r7, #20] + 8006a3e: 68bb ldr r3, [r7, #8] + 8006a40: f023 0340 bic.w r3, r3, #64 @ 0x40 + 8006a44: 61fb str r3, [r7, #28] + 8006a46: 687b ldr r3, [r7, #4] + 8006a48: 681b ldr r3, [r3, #0] + 8006a4a: 461a mov r2, r3 + 8006a4c: 69fb ldr r3, [r7, #28] + 8006a4e: 61bb str r3, [r7, #24] + 8006a50: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006a0a: 6979 ldr r1, [r7, #20] - 8006a0c: 69ba ldr r2, [r7, #24] - 8006a0e: e841 2300 strex r3, r2, [r1] - 8006a12: 613b str r3, [r7, #16] + 8006a52: 6979 ldr r1, [r7, #20] + 8006a54: 69ba ldr r2, [r7, #24] + 8006a56: e841 2300 strex r3, r2, [r1] + 8006a5a: 613b str r3, [r7, #16] return(result); - 8006a14: 693b ldr r3, [r7, #16] - 8006a16: 2b00 cmp r3, #0 - 8006a18: d1e6 bne.n 80069e8 + 8006a5c: 693b ldr r3, [r7, #16] + 8006a5e: 2b00 cmp r3, #0 + 8006a60: d1e6 bne.n 8006a30 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 8006a1a: 687b ldr r3, [r7, #4] - 8006a1c: 2220 movs r2, #32 - 8006a1e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 8006a62: 687b ldr r3, [r7, #4] + 8006a64: 2220 movs r2, #32 + 8006a66: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; - 8006a22: 687b ldr r3, [r7, #4] - 8006a24: 2200 movs r2, #0 - 8006a26: 679a str r2, [r3, #120] @ 0x78 + 8006a6a: 687b ldr r3, [r7, #4] + 8006a6c: 2200 movs r2, #0 + 8006a6e: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); - 8006a28: 6878 ldr r0, [r7, #4] - 8006a2a: f7fa fd27 bl 800147c + 8006a70: 6878 ldr r0, [r7, #4] + 8006a72: f7fa fd27 bl 80014c4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - 8006a2e: bf00 nop - 8006a30: 3720 adds r7, #32 - 8006a32: 46bd mov sp, r7 - 8006a34: bd80 pop {r7, pc} + 8006a76: bf00 nop + 8006a78: 3720 adds r7, #32 + 8006a7a: 46bd mov sp, r7 + 8006a7c: bd80 pop {r7, pc} ... -08006a38 : +08006a80 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { - 8006a38: b580 push {r7, lr} - 8006a3a: b09c sub sp, #112 @ 0x70 - 8006a3c: af00 add r7, sp, #0 - 8006a3e: 6078 str r0, [r7, #4] + 8006a80: b580 push {r7, lr} + 8006a82: b09c sub sp, #112 @ 0x70 + 8006a84: af00 add r7, sp, #0 + 8006a86: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; - 8006a40: 687b ldr r3, [r7, #4] - 8006a42: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 - 8006a46: f8a7 306e strh.w r3, [r7, #110] @ 0x6e + 8006a88: 687b ldr r3, [r7, #4] + 8006a8a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006a8e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) - 8006a4a: 687b ldr r3, [r7, #4] - 8006a4c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c - 8006a50: 2b22 cmp r3, #34 @ 0x22 - 8006a52: f040 80be bne.w 8006bd2 + 8006a92: 687b ldr r3, [r7, #4] + 8006a94: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006a98: 2b22 cmp r3, #34 @ 0x22 + 8006a9a: f040 80be bne.w 8006c1a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - 8006a56: 687b ldr r3, [r7, #4] - 8006a58: 681b ldr r3, [r3, #0] - 8006a5a: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006a5c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c + 8006a9e: 687b ldr r3, [r7, #4] + 8006aa0: 681b ldr r3, [r3, #0] + 8006aa2: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006aa4: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - 8006a60: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c - 8006a64: b2d9 uxtb r1, r3 - 8006a66: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e - 8006a6a: b2da uxtb r2, r3 - 8006a6c: 687b ldr r3, [r7, #4] - 8006a6e: 6d9b ldr r3, [r3, #88] @ 0x58 - 8006a70: 400a ands r2, r1 - 8006a72: b2d2 uxtb r2, r2 - 8006a74: 701a strb r2, [r3, #0] + 8006aa8: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c + 8006aac: b2d9 uxtb r1, r3 + 8006aae: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e + 8006ab2: b2da uxtb r2, r3 + 8006ab4: 687b ldr r3, [r7, #4] + 8006ab6: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006ab8: 400a ands r2, r1 + 8006aba: b2d2 uxtb r2, r2 + 8006abc: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; - 8006a76: 687b ldr r3, [r7, #4] - 8006a78: 6d9b ldr r3, [r3, #88] @ 0x58 - 8006a7a: 1c5a adds r2, r3, #1 - 8006a7c: 687b ldr r3, [r7, #4] - 8006a7e: 659a str r2, [r3, #88] @ 0x58 + 8006abe: 687b ldr r3, [r7, #4] + 8006ac0: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006ac2: 1c5a adds r2, r3, #1 + 8006ac4: 687b ldr r3, [r7, #4] + 8006ac6: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; - 8006a80: 687b ldr r3, [r7, #4] - 8006a82: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8006a86: b29b uxth r3, r3 - 8006a88: 3b01 subs r3, #1 - 8006a8a: b29a uxth r2, r3 - 8006a8c: 687b ldr r3, [r7, #4] - 8006a8e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 8006ac8: 687b ldr r3, [r7, #4] + 8006aca: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006ace: b29b uxth r3, r3 + 8006ad0: 3b01 subs r3, #1 + 8006ad2: b29a uxth r2, r3 + 8006ad4: 687b ldr r3, [r7, #4] + 8006ad6: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) - 8006a92: 687b ldr r3, [r7, #4] - 8006a94: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8006a98: b29b uxth r3, r3 - 8006a9a: 2b00 cmp r3, #0 - 8006a9c: f040 80a1 bne.w 8006be2 + 8006ada: 687b ldr r3, [r7, #4] + 8006adc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006ae0: b29b uxth r3, r3 + 8006ae2: 2b00 cmp r3, #0 + 8006ae4: f040 80a1 bne.w 8006c2a { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 8006aa0: 687b ldr r3, [r7, #4] - 8006aa2: 681b ldr r3, [r3, #0] - 8006aa4: 64fb str r3, [r7, #76] @ 0x4c + 8006ae8: 687b ldr r3, [r7, #4] + 8006aea: 681b ldr r3, [r3, #0] + 8006aec: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006aa6: 6cfb ldr r3, [r7, #76] @ 0x4c - 8006aa8: e853 3f00 ldrex r3, [r3] - 8006aac: 64bb str r3, [r7, #72] @ 0x48 + 8006aee: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006af0: e853 3f00 ldrex r3, [r3] + 8006af4: 64bb str r3, [r7, #72] @ 0x48 return(result); - 8006aae: 6cbb ldr r3, [r7, #72] @ 0x48 - 8006ab0: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8006ab4: 66bb str r3, [r7, #104] @ 0x68 - 8006ab6: 687b ldr r3, [r7, #4] - 8006ab8: 681b ldr r3, [r3, #0] - 8006aba: 461a mov r2, r3 - 8006abc: 6ebb ldr r3, [r7, #104] @ 0x68 - 8006abe: 65bb str r3, [r7, #88] @ 0x58 - 8006ac0: 657a str r2, [r7, #84] @ 0x54 + 8006af6: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006af8: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006afc: 66bb str r3, [r7, #104] @ 0x68 + 8006afe: 687b ldr r3, [r7, #4] + 8006b00: 681b ldr r3, [r3, #0] + 8006b02: 461a mov r2, r3 + 8006b04: 6ebb ldr r3, [r7, #104] @ 0x68 + 8006b06: 65bb str r3, [r7, #88] @ 0x58 + 8006b08: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006ac2: 6d79 ldr r1, [r7, #84] @ 0x54 - 8006ac4: 6dba ldr r2, [r7, #88] @ 0x58 - 8006ac6: e841 2300 strex r3, r2, [r1] - 8006aca: 653b str r3, [r7, #80] @ 0x50 + 8006b0a: 6d79 ldr r1, [r7, #84] @ 0x54 + 8006b0c: 6dba ldr r2, [r7, #88] @ 0x58 + 8006b0e: e841 2300 strex r3, r2, [r1] + 8006b12: 653b str r3, [r7, #80] @ 0x50 return(result); - 8006acc: 6d3b ldr r3, [r7, #80] @ 0x50 - 8006ace: 2b00 cmp r3, #0 - 8006ad0: d1e6 bne.n 8006aa0 + 8006b14: 6d3b ldr r3, [r7, #80] @ 0x50 + 8006b16: 2b00 cmp r3, #0 + 8006b18: d1e6 bne.n 8006ae8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8006ad2: 687b ldr r3, [r7, #4] - 8006ad4: 681b ldr r3, [r3, #0] - 8006ad6: 3308 adds r3, #8 - 8006ad8: 63bb str r3, [r7, #56] @ 0x38 + 8006b1a: 687b ldr r3, [r7, #4] + 8006b1c: 681b ldr r3, [r3, #0] + 8006b1e: 3308 adds r3, #8 + 8006b20: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006ada: 6bbb ldr r3, [r7, #56] @ 0x38 - 8006adc: e853 3f00 ldrex r3, [r3] - 8006ae0: 637b str r3, [r7, #52] @ 0x34 + 8006b22: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006b24: e853 3f00 ldrex r3, [r3] + 8006b28: 637b str r3, [r7, #52] @ 0x34 return(result); - 8006ae2: 6b7b ldr r3, [r7, #52] @ 0x34 - 8006ae4: f023 0301 bic.w r3, r3, #1 - 8006ae8: 667b str r3, [r7, #100] @ 0x64 - 8006aea: 687b ldr r3, [r7, #4] - 8006aec: 681b ldr r3, [r3, #0] - 8006aee: 3308 adds r3, #8 - 8006af0: 6e7a ldr r2, [r7, #100] @ 0x64 - 8006af2: 647a str r2, [r7, #68] @ 0x44 - 8006af4: 643b str r3, [r7, #64] @ 0x40 + 8006b2a: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006b2c: f023 0301 bic.w r3, r3, #1 + 8006b30: 667b str r3, [r7, #100] @ 0x64 + 8006b32: 687b ldr r3, [r7, #4] + 8006b34: 681b ldr r3, [r3, #0] + 8006b36: 3308 adds r3, #8 + 8006b38: 6e7a ldr r2, [r7, #100] @ 0x64 + 8006b3a: 647a str r2, [r7, #68] @ 0x44 + 8006b3c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006af6: 6c39 ldr r1, [r7, #64] @ 0x40 - 8006af8: 6c7a ldr r2, [r7, #68] @ 0x44 - 8006afa: e841 2300 strex r3, r2, [r1] - 8006afe: 63fb str r3, [r7, #60] @ 0x3c + 8006b3e: 6c39 ldr r1, [r7, #64] @ 0x40 + 8006b40: 6c7a ldr r2, [r7, #68] @ 0x44 + 8006b42: e841 2300 strex r3, r2, [r1] + 8006b46: 63fb str r3, [r7, #60] @ 0x3c return(result); - 8006b00: 6bfb ldr r3, [r7, #60] @ 0x3c - 8006b02: 2b00 cmp r3, #0 - 8006b04: d1e5 bne.n 8006ad2 + 8006b48: 6bfb ldr r3, [r7, #60] @ 0x3c + 8006b4a: 2b00 cmp r3, #0 + 8006b4c: d1e5 bne.n 8006b1a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8006b06: 687b ldr r3, [r7, #4] - 8006b08: 2220 movs r2, #32 - 8006b0a: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 8006b4e: 687b ldr r3, [r7, #4] + 8006b50: 2220 movs r2, #32 + 8006b52: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; - 8006b0e: 687b ldr r3, [r7, #4] - 8006b10: 2200 movs r2, #0 - 8006b12: 675a str r2, [r3, #116] @ 0x74 + 8006b56: 687b ldr r3, [r7, #4] + 8006b58: 2200 movs r2, #0 + 8006b5a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; - 8006b14: 687b ldr r3, [r7, #4] - 8006b16: 2200 movs r2, #0 - 8006b18: 671a str r2, [r3, #112] @ 0x70 + 8006b5c: 687b ldr r3, [r7, #4] + 8006b5e: 2200 movs r2, #0 + 8006b60: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) - 8006b1a: 687b ldr r3, [r7, #4] - 8006b1c: 681b ldr r3, [r3, #0] - 8006b1e: 4a33 ldr r2, [pc, #204] @ (8006bec ) - 8006b20: 4293 cmp r3, r2 - 8006b22: d01f beq.n 8006b64 + 8006b62: 687b ldr r3, [r7, #4] + 8006b64: 681b ldr r3, [r3, #0] + 8006b66: 4a33 ldr r2, [pc, #204] @ (8006c34 ) + 8006b68: 4293 cmp r3, r2 + 8006b6a: d01f beq.n 8006bac { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - 8006b24: 687b ldr r3, [r7, #4] - 8006b26: 681b ldr r3, [r3, #0] - 8006b28: 685b ldr r3, [r3, #4] - 8006b2a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8006b2e: 2b00 cmp r3, #0 - 8006b30: d018 beq.n 8006b64 + 8006b6c: 687b ldr r3, [r7, #4] + 8006b6e: 681b ldr r3, [r3, #0] + 8006b70: 685b ldr r3, [r3, #4] + 8006b72: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006b76: 2b00 cmp r3, #0 + 8006b78: d018 beq.n 8006bac { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - 8006b32: 687b ldr r3, [r7, #4] - 8006b34: 681b ldr r3, [r3, #0] - 8006b36: 627b str r3, [r7, #36] @ 0x24 + 8006b7a: 687b ldr r3, [r7, #4] + 8006b7c: 681b ldr r3, [r3, #0] + 8006b7e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006b38: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006b3a: e853 3f00 ldrex r3, [r3] - 8006b3e: 623b str r3, [r7, #32] + 8006b80: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006b82: e853 3f00 ldrex r3, [r3] + 8006b86: 623b str r3, [r7, #32] return(result); - 8006b40: 6a3b ldr r3, [r7, #32] - 8006b42: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 - 8006b46: 663b str r3, [r7, #96] @ 0x60 - 8006b48: 687b ldr r3, [r7, #4] - 8006b4a: 681b ldr r3, [r3, #0] - 8006b4c: 461a mov r2, r3 - 8006b4e: 6e3b ldr r3, [r7, #96] @ 0x60 - 8006b50: 633b str r3, [r7, #48] @ 0x30 - 8006b52: 62fa str r2, [r7, #44] @ 0x2c + 8006b88: 6a3b ldr r3, [r7, #32] + 8006b8a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006b8e: 663b str r3, [r7, #96] @ 0x60 + 8006b90: 687b ldr r3, [r7, #4] + 8006b92: 681b ldr r3, [r3, #0] + 8006b94: 461a mov r2, r3 + 8006b96: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006b98: 633b str r3, [r7, #48] @ 0x30 + 8006b9a: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006b54: 6af9 ldr r1, [r7, #44] @ 0x2c - 8006b56: 6b3a ldr r2, [r7, #48] @ 0x30 - 8006b58: e841 2300 strex r3, r2, [r1] - 8006b5c: 62bb str r3, [r7, #40] @ 0x28 + 8006b9c: 6af9 ldr r1, [r7, #44] @ 0x2c + 8006b9e: 6b3a ldr r2, [r7, #48] @ 0x30 + 8006ba0: e841 2300 strex r3, r2, [r1] + 8006ba4: 62bb str r3, [r7, #40] @ 0x28 return(result); - 8006b5e: 6abb ldr r3, [r7, #40] @ 0x28 - 8006b60: 2b00 cmp r3, #0 - 8006b62: d1e6 bne.n 8006b32 + 8006ba6: 6abb ldr r3, [r7, #40] @ 0x28 + 8006ba8: 2b00 cmp r3, #0 + 8006baa: d1e6 bne.n 8006b7a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8006b64: 687b ldr r3, [r7, #4] - 8006b66: 6edb ldr r3, [r3, #108] @ 0x6c - 8006b68: 2b01 cmp r3, #1 - 8006b6a: d12e bne.n 8006bca + 8006bac: 687b ldr r3, [r7, #4] + 8006bae: 6edb ldr r3, [r3, #108] @ 0x6c + 8006bb0: 2b01 cmp r3, #1 + 8006bb2: d12e bne.n 8006c12 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8006b6c: 687b ldr r3, [r7, #4] - 8006b6e: 2200 movs r2, #0 - 8006b70: 66da str r2, [r3, #108] @ 0x6c + 8006bb4: 687b ldr r3, [r7, #4] + 8006bb6: 2200 movs r2, #0 + 8006bb8: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8006b72: 687b ldr r3, [r7, #4] - 8006b74: 681b ldr r3, [r3, #0] - 8006b76: 613b str r3, [r7, #16] + 8006bba: 687b ldr r3, [r7, #4] + 8006bbc: 681b ldr r3, [r3, #0] + 8006bbe: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006b78: 693b ldr r3, [r7, #16] - 8006b7a: e853 3f00 ldrex r3, [r3] - 8006b7e: 60fb str r3, [r7, #12] + 8006bc0: 693b ldr r3, [r7, #16] + 8006bc2: e853 3f00 ldrex r3, [r3] + 8006bc6: 60fb str r3, [r7, #12] return(result); - 8006b80: 68fb ldr r3, [r7, #12] - 8006b82: f023 0310 bic.w r3, r3, #16 - 8006b86: 65fb str r3, [r7, #92] @ 0x5c - 8006b88: 687b ldr r3, [r7, #4] - 8006b8a: 681b ldr r3, [r3, #0] - 8006b8c: 461a mov r2, r3 - 8006b8e: 6dfb ldr r3, [r7, #92] @ 0x5c - 8006b90: 61fb str r3, [r7, #28] - 8006b92: 61ba str r2, [r7, #24] + 8006bc8: 68fb ldr r3, [r7, #12] + 8006bca: f023 0310 bic.w r3, r3, #16 + 8006bce: 65fb str r3, [r7, #92] @ 0x5c + 8006bd0: 687b ldr r3, [r7, #4] + 8006bd2: 681b ldr r3, [r3, #0] + 8006bd4: 461a mov r2, r3 + 8006bd6: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006bd8: 61fb str r3, [r7, #28] + 8006bda: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006b94: 69b9 ldr r1, [r7, #24] - 8006b96: 69fa ldr r2, [r7, #28] - 8006b98: e841 2300 strex r3, r2, [r1] - 8006b9c: 617b str r3, [r7, #20] + 8006bdc: 69b9 ldr r1, [r7, #24] + 8006bde: 69fa ldr r2, [r7, #28] + 8006be0: e841 2300 strex r3, r2, [r1] + 8006be4: 617b str r3, [r7, #20] return(result); - 8006b9e: 697b ldr r3, [r7, #20] - 8006ba0: 2b00 cmp r3, #0 - 8006ba2: d1e6 bne.n 8006b72 + 8006be6: 697b ldr r3, [r7, #20] + 8006be8: 2b00 cmp r3, #0 + 8006bea: d1e6 bne.n 8006bba if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - 8006ba4: 687b ldr r3, [r7, #4] - 8006ba6: 681b ldr r3, [r3, #0] - 8006ba8: 69db ldr r3, [r3, #28] - 8006baa: f003 0310 and.w r3, r3, #16 - 8006bae: 2b10 cmp r3, #16 - 8006bb0: d103 bne.n 8006bba + 8006bec: 687b ldr r3, [r7, #4] + 8006bee: 681b ldr r3, [r3, #0] + 8006bf0: 69db ldr r3, [r3, #28] + 8006bf2: f003 0310 and.w r3, r3, #16 + 8006bf6: 2b10 cmp r3, #16 + 8006bf8: d103 bne.n 8006c02 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 8006bb2: 687b ldr r3, [r7, #4] - 8006bb4: 681b ldr r3, [r3, #0] - 8006bb6: 2210 movs r2, #16 - 8006bb8: 621a str r2, [r3, #32] + 8006bfa: 687b ldr r3, [r7, #4] + 8006bfc: 681b ldr r3, [r3, #0] + 8006bfe: 2210 movs r2, #16 + 8006c00: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 8006bba: 687b ldr r3, [r7, #4] - 8006bbc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 8006bc0: 4619 mov r1, r3 - 8006bc2: 6878 ldr r0, [r7, #4] - 8006bc4: f7ff f8e0 bl 8005d88 + 8006c02: 687b ldr r3, [r7, #4] + 8006c04: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8006c08: 4619 mov r1, r3 + 8006c0a: 6878 ldr r0, [r7, #4] + 8006c0c: f7ff f8e0 bl 8005dd0 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } - 8006bc8: e00b b.n 8006be2 + 8006c10: e00b b.n 8006c2a HAL_UART_RxCpltCallback(huart); - 8006bca: 6878 ldr r0, [r7, #4] - 8006bcc: f7fa fc60 bl 8001490 + 8006c12: 6878 ldr r0, [r7, #4] + 8006c14: f7fa fc60 bl 80014d8 } - 8006bd0: e007 b.n 8006be2 + 8006c18: e007 b.n 8006c2a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - 8006bd2: 687b ldr r3, [r7, #4] - 8006bd4: 681b ldr r3, [r3, #0] - 8006bd6: 699a ldr r2, [r3, #24] - 8006bd8: 687b ldr r3, [r7, #4] - 8006bda: 681b ldr r3, [r3, #0] - 8006bdc: f042 0208 orr.w r2, r2, #8 - 8006be0: 619a str r2, [r3, #24] + 8006c1a: 687b ldr r3, [r7, #4] + 8006c1c: 681b ldr r3, [r3, #0] + 8006c1e: 699a ldr r2, [r3, #24] + 8006c20: 687b ldr r3, [r7, #4] + 8006c22: 681b ldr r3, [r3, #0] + 8006c24: f042 0208 orr.w r2, r2, #8 + 8006c28: 619a str r2, [r3, #24] } - 8006be2: bf00 nop - 8006be4: 3770 adds r7, #112 @ 0x70 - 8006be6: 46bd mov sp, r7 - 8006be8: bd80 pop {r7, pc} - 8006bea: bf00 nop - 8006bec: 40008000 .word 0x40008000 + 8006c2a: bf00 nop + 8006c2c: 3770 adds r7, #112 @ 0x70 + 8006c2e: 46bd mov sp, r7 + 8006c30: bd80 pop {r7, pc} + 8006c32: bf00 nop + 8006c34: 40008000 .word 0x40008000 -08006bf0 : +08006c38 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { - 8006bf0: b580 push {r7, lr} - 8006bf2: b09c sub sp, #112 @ 0x70 - 8006bf4: af00 add r7, sp, #0 - 8006bf6: 6078 str r0, [r7, #4] + 8006c38: b580 push {r7, lr} + 8006c3a: b09c sub sp, #112 @ 0x70 + 8006c3c: af00 add r7, sp, #0 + 8006c3e: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; - 8006bf8: 687b ldr r3, [r7, #4] - 8006bfa: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 - 8006bfe: f8a7 306e strh.w r3, [r7, #110] @ 0x6e + 8006c40: 687b ldr r3, [r7, #4] + 8006c42: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006c46: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) - 8006c02: 687b ldr r3, [r7, #4] - 8006c04: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c - 8006c08: 2b22 cmp r3, #34 @ 0x22 - 8006c0a: f040 80be bne.w 8006d8a + 8006c4a: 687b ldr r3, [r7, #4] + 8006c4c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006c50: 2b22 cmp r3, #34 @ 0x22 + 8006c52: f040 80be bne.w 8006dd2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - 8006c0e: 687b ldr r3, [r7, #4] - 8006c10: 681b ldr r3, [r3, #0] - 8006c12: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006c14: f8a7 306c strh.w r3, [r7, #108] @ 0x6c + 8006c56: 687b ldr r3, [r7, #4] + 8006c58: 681b ldr r3, [r3, #0] + 8006c5a: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006c5c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; - 8006c18: 687b ldr r3, [r7, #4] - 8006c1a: 6d9b ldr r3, [r3, #88] @ 0x58 - 8006c1c: 66bb str r3, [r7, #104] @ 0x68 + 8006c60: 687b ldr r3, [r7, #4] + 8006c62: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006c64: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); - 8006c1e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c - 8006c22: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e - 8006c26: 4013 ands r3, r2 - 8006c28: b29a uxth r2, r3 - 8006c2a: 6ebb ldr r3, [r7, #104] @ 0x68 - 8006c2c: 801a strh r2, [r3, #0] + 8006c66: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c + 8006c6a: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e + 8006c6e: 4013 ands r3, r2 + 8006c70: b29a uxth r2, r3 + 8006c72: 6ebb ldr r3, [r7, #104] @ 0x68 + 8006c74: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; - 8006c2e: 687b ldr r3, [r7, #4] - 8006c30: 6d9b ldr r3, [r3, #88] @ 0x58 - 8006c32: 1c9a adds r2, r3, #2 - 8006c34: 687b ldr r3, [r7, #4] - 8006c36: 659a str r2, [r3, #88] @ 0x58 + 8006c76: 687b ldr r3, [r7, #4] + 8006c78: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006c7a: 1c9a adds r2, r3, #2 + 8006c7c: 687b ldr r3, [r7, #4] + 8006c7e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; - 8006c38: 687b ldr r3, [r7, #4] - 8006c3a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8006c3e: b29b uxth r3, r3 - 8006c40: 3b01 subs r3, #1 - 8006c42: b29a uxth r2, r3 - 8006c44: 687b ldr r3, [r7, #4] - 8006c46: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 8006c80: 687b ldr r3, [r7, #4] + 8006c82: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006c86: b29b uxth r3, r3 + 8006c88: 3b01 subs r3, #1 + 8006c8a: b29a uxth r2, r3 + 8006c8c: 687b ldr r3, [r7, #4] + 8006c8e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) - 8006c4a: 687b ldr r3, [r7, #4] - 8006c4c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8006c50: b29b uxth r3, r3 - 8006c52: 2b00 cmp r3, #0 - 8006c54: f040 80a1 bne.w 8006d9a + 8006c92: 687b ldr r3, [r7, #4] + 8006c94: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006c98: b29b uxth r3, r3 + 8006c9a: 2b00 cmp r3, #0 + 8006c9c: f040 80a1 bne.w 8006de2 { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - 8006c58: 687b ldr r3, [r7, #4] - 8006c5a: 681b ldr r3, [r3, #0] - 8006c5c: 64bb str r3, [r7, #72] @ 0x48 + 8006ca0: 687b ldr r3, [r7, #4] + 8006ca2: 681b ldr r3, [r3, #0] + 8006ca4: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006c5e: 6cbb ldr r3, [r7, #72] @ 0x48 - 8006c60: e853 3f00 ldrex r3, [r3] - 8006c64: 647b str r3, [r7, #68] @ 0x44 + 8006ca6: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006ca8: e853 3f00 ldrex r3, [r3] + 8006cac: 647b str r3, [r7, #68] @ 0x44 return(result); - 8006c66: 6c7b ldr r3, [r7, #68] @ 0x44 - 8006c68: f423 7390 bic.w r3, r3, #288 @ 0x120 - 8006c6c: 667b str r3, [r7, #100] @ 0x64 - 8006c6e: 687b ldr r3, [r7, #4] - 8006c70: 681b ldr r3, [r3, #0] - 8006c72: 461a mov r2, r3 - 8006c74: 6e7b ldr r3, [r7, #100] @ 0x64 - 8006c76: 657b str r3, [r7, #84] @ 0x54 - 8006c78: 653a str r2, [r7, #80] @ 0x50 + 8006cae: 6c7b ldr r3, [r7, #68] @ 0x44 + 8006cb0: f423 7390 bic.w r3, r3, #288 @ 0x120 + 8006cb4: 667b str r3, [r7, #100] @ 0x64 + 8006cb6: 687b ldr r3, [r7, #4] + 8006cb8: 681b ldr r3, [r3, #0] + 8006cba: 461a mov r2, r3 + 8006cbc: 6e7b ldr r3, [r7, #100] @ 0x64 + 8006cbe: 657b str r3, [r7, #84] @ 0x54 + 8006cc0: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006c7a: 6d39 ldr r1, [r7, #80] @ 0x50 - 8006c7c: 6d7a ldr r2, [r7, #84] @ 0x54 - 8006c7e: e841 2300 strex r3, r2, [r1] - 8006c82: 64fb str r3, [r7, #76] @ 0x4c + 8006cc2: 6d39 ldr r1, [r7, #80] @ 0x50 + 8006cc4: 6d7a ldr r2, [r7, #84] @ 0x54 + 8006cc6: e841 2300 strex r3, r2, [r1] + 8006cca: 64fb str r3, [r7, #76] @ 0x4c return(result); - 8006c84: 6cfb ldr r3, [r7, #76] @ 0x4c - 8006c86: 2b00 cmp r3, #0 - 8006c88: d1e6 bne.n 8006c58 + 8006ccc: 6cfb ldr r3, [r7, #76] @ 0x4c + 8006cce: 2b00 cmp r3, #0 + 8006cd0: d1e6 bne.n 8006ca0 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8006c8a: 687b ldr r3, [r7, #4] - 8006c8c: 681b ldr r3, [r3, #0] - 8006c8e: 3308 adds r3, #8 - 8006c90: 637b str r3, [r7, #52] @ 0x34 + 8006cd2: 687b ldr r3, [r7, #4] + 8006cd4: 681b ldr r3, [r3, #0] + 8006cd6: 3308 adds r3, #8 + 8006cd8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006c92: 6b7b ldr r3, [r7, #52] @ 0x34 - 8006c94: e853 3f00 ldrex r3, [r3] - 8006c98: 633b str r3, [r7, #48] @ 0x30 + 8006cda: 6b7b ldr r3, [r7, #52] @ 0x34 + 8006cdc: e853 3f00 ldrex r3, [r3] + 8006ce0: 633b str r3, [r7, #48] @ 0x30 return(result); - 8006c9a: 6b3b ldr r3, [r7, #48] @ 0x30 - 8006c9c: f023 0301 bic.w r3, r3, #1 - 8006ca0: 663b str r3, [r7, #96] @ 0x60 - 8006ca2: 687b ldr r3, [r7, #4] - 8006ca4: 681b ldr r3, [r3, #0] - 8006ca6: 3308 adds r3, #8 - 8006ca8: 6e3a ldr r2, [r7, #96] @ 0x60 - 8006caa: 643a str r2, [r7, #64] @ 0x40 - 8006cac: 63fb str r3, [r7, #60] @ 0x3c + 8006ce2: 6b3b ldr r3, [r7, #48] @ 0x30 + 8006ce4: f023 0301 bic.w r3, r3, #1 + 8006ce8: 663b str r3, [r7, #96] @ 0x60 + 8006cea: 687b ldr r3, [r7, #4] + 8006cec: 681b ldr r3, [r3, #0] + 8006cee: 3308 adds r3, #8 + 8006cf0: 6e3a ldr r2, [r7, #96] @ 0x60 + 8006cf2: 643a str r2, [r7, #64] @ 0x40 + 8006cf4: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006cae: 6bf9 ldr r1, [r7, #60] @ 0x3c - 8006cb0: 6c3a ldr r2, [r7, #64] @ 0x40 - 8006cb2: e841 2300 strex r3, r2, [r1] - 8006cb6: 63bb str r3, [r7, #56] @ 0x38 + 8006cf6: 6bf9 ldr r1, [r7, #60] @ 0x3c + 8006cf8: 6c3a ldr r2, [r7, #64] @ 0x40 + 8006cfa: e841 2300 strex r3, r2, [r1] + 8006cfe: 63bb str r3, [r7, #56] @ 0x38 return(result); - 8006cb8: 6bbb ldr r3, [r7, #56] @ 0x38 - 8006cba: 2b00 cmp r3, #0 - 8006cbc: d1e5 bne.n 8006c8a + 8006d00: 6bbb ldr r3, [r7, #56] @ 0x38 + 8006d02: 2b00 cmp r3, #0 + 8006d04: d1e5 bne.n 8006cd2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8006cbe: 687b ldr r3, [r7, #4] - 8006cc0: 2220 movs r2, #32 - 8006cc2: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 8006d06: 687b ldr r3, [r7, #4] + 8006d08: 2220 movs r2, #32 + 8006d0a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; - 8006cc6: 687b ldr r3, [r7, #4] - 8006cc8: 2200 movs r2, #0 - 8006cca: 675a str r2, [r3, #116] @ 0x74 + 8006d0e: 687b ldr r3, [r7, #4] + 8006d10: 2200 movs r2, #0 + 8006d12: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; - 8006ccc: 687b ldr r3, [r7, #4] - 8006cce: 2200 movs r2, #0 - 8006cd0: 671a str r2, [r3, #112] @ 0x70 + 8006d14: 687b ldr r3, [r7, #4] + 8006d16: 2200 movs r2, #0 + 8006d18: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) - 8006cd2: 687b ldr r3, [r7, #4] - 8006cd4: 681b ldr r3, [r3, #0] - 8006cd6: 4a33 ldr r2, [pc, #204] @ (8006da4 ) - 8006cd8: 4293 cmp r3, r2 - 8006cda: d01f beq.n 8006d1c + 8006d1a: 687b ldr r3, [r7, #4] + 8006d1c: 681b ldr r3, [r3, #0] + 8006d1e: 4a33 ldr r2, [pc, #204] @ (8006dec ) + 8006d20: 4293 cmp r3, r2 + 8006d22: d01f beq.n 8006d64 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - 8006cdc: 687b ldr r3, [r7, #4] - 8006cde: 681b ldr r3, [r3, #0] - 8006ce0: 685b ldr r3, [r3, #4] - 8006ce2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8006ce6: 2b00 cmp r3, #0 - 8006ce8: d018 beq.n 8006d1c + 8006d24: 687b ldr r3, [r7, #4] + 8006d26: 681b ldr r3, [r3, #0] + 8006d28: 685b ldr r3, [r3, #4] + 8006d2a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006d2e: 2b00 cmp r3, #0 + 8006d30: d018 beq.n 8006d64 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - 8006cea: 687b ldr r3, [r7, #4] - 8006cec: 681b ldr r3, [r3, #0] - 8006cee: 623b str r3, [r7, #32] + 8006d32: 687b ldr r3, [r7, #4] + 8006d34: 681b ldr r3, [r3, #0] + 8006d36: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006cf0: 6a3b ldr r3, [r7, #32] - 8006cf2: e853 3f00 ldrex r3, [r3] - 8006cf6: 61fb str r3, [r7, #28] + 8006d38: 6a3b ldr r3, [r7, #32] + 8006d3a: e853 3f00 ldrex r3, [r3] + 8006d3e: 61fb str r3, [r7, #28] return(result); - 8006cf8: 69fb ldr r3, [r7, #28] - 8006cfa: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 - 8006cfe: 65fb str r3, [r7, #92] @ 0x5c - 8006d00: 687b ldr r3, [r7, #4] - 8006d02: 681b ldr r3, [r3, #0] - 8006d04: 461a mov r2, r3 - 8006d06: 6dfb ldr r3, [r7, #92] @ 0x5c - 8006d08: 62fb str r3, [r7, #44] @ 0x2c - 8006d0a: 62ba str r2, [r7, #40] @ 0x28 + 8006d40: 69fb ldr r3, [r7, #28] + 8006d42: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006d46: 65fb str r3, [r7, #92] @ 0x5c + 8006d48: 687b ldr r3, [r7, #4] + 8006d4a: 681b ldr r3, [r3, #0] + 8006d4c: 461a mov r2, r3 + 8006d4e: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006d50: 62fb str r3, [r7, #44] @ 0x2c + 8006d52: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006d0c: 6ab9 ldr r1, [r7, #40] @ 0x28 - 8006d0e: 6afa ldr r2, [r7, #44] @ 0x2c - 8006d10: e841 2300 strex r3, r2, [r1] - 8006d14: 627b str r3, [r7, #36] @ 0x24 + 8006d54: 6ab9 ldr r1, [r7, #40] @ 0x28 + 8006d56: 6afa ldr r2, [r7, #44] @ 0x2c + 8006d58: e841 2300 strex r3, r2, [r1] + 8006d5c: 627b str r3, [r7, #36] @ 0x24 return(result); - 8006d16: 6a7b ldr r3, [r7, #36] @ 0x24 - 8006d18: 2b00 cmp r3, #0 - 8006d1a: d1e6 bne.n 8006cea + 8006d5e: 6a7b ldr r3, [r7, #36] @ 0x24 + 8006d60: 2b00 cmp r3, #0 + 8006d62: d1e6 bne.n 8006d32 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8006d1c: 687b ldr r3, [r7, #4] - 8006d1e: 6edb ldr r3, [r3, #108] @ 0x6c - 8006d20: 2b01 cmp r3, #1 - 8006d22: d12e bne.n 8006d82 + 8006d64: 687b ldr r3, [r7, #4] + 8006d66: 6edb ldr r3, [r3, #108] @ 0x6c + 8006d68: 2b01 cmp r3, #1 + 8006d6a: d12e bne.n 8006dca { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8006d24: 687b ldr r3, [r7, #4] - 8006d26: 2200 movs r2, #0 - 8006d28: 66da str r2, [r3, #108] @ 0x6c + 8006d6c: 687b ldr r3, [r7, #4] + 8006d6e: 2200 movs r2, #0 + 8006d70: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8006d2a: 687b ldr r3, [r7, #4] - 8006d2c: 681b ldr r3, [r3, #0] - 8006d2e: 60fb str r3, [r7, #12] + 8006d72: 687b ldr r3, [r7, #4] + 8006d74: 681b ldr r3, [r3, #0] + 8006d76: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006d30: 68fb ldr r3, [r7, #12] - 8006d32: e853 3f00 ldrex r3, [r3] - 8006d36: 60bb str r3, [r7, #8] + 8006d78: 68fb ldr r3, [r7, #12] + 8006d7a: e853 3f00 ldrex r3, [r3] + 8006d7e: 60bb str r3, [r7, #8] return(result); - 8006d38: 68bb ldr r3, [r7, #8] - 8006d3a: f023 0310 bic.w r3, r3, #16 - 8006d3e: 65bb str r3, [r7, #88] @ 0x58 - 8006d40: 687b ldr r3, [r7, #4] - 8006d42: 681b ldr r3, [r3, #0] - 8006d44: 461a mov r2, r3 - 8006d46: 6dbb ldr r3, [r7, #88] @ 0x58 - 8006d48: 61bb str r3, [r7, #24] - 8006d4a: 617a str r2, [r7, #20] + 8006d80: 68bb ldr r3, [r7, #8] + 8006d82: f023 0310 bic.w r3, r3, #16 + 8006d86: 65bb str r3, [r7, #88] @ 0x58 + 8006d88: 687b ldr r3, [r7, #4] + 8006d8a: 681b ldr r3, [r3, #0] + 8006d8c: 461a mov r2, r3 + 8006d8e: 6dbb ldr r3, [r7, #88] @ 0x58 + 8006d90: 61bb str r3, [r7, #24] + 8006d92: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006d4c: 6979 ldr r1, [r7, #20] - 8006d4e: 69ba ldr r2, [r7, #24] - 8006d50: e841 2300 strex r3, r2, [r1] - 8006d54: 613b str r3, [r7, #16] + 8006d94: 6979 ldr r1, [r7, #20] + 8006d96: 69ba ldr r2, [r7, #24] + 8006d98: e841 2300 strex r3, r2, [r1] + 8006d9c: 613b str r3, [r7, #16] return(result); - 8006d56: 693b ldr r3, [r7, #16] - 8006d58: 2b00 cmp r3, #0 - 8006d5a: d1e6 bne.n 8006d2a + 8006d9e: 693b ldr r3, [r7, #16] + 8006da0: 2b00 cmp r3, #0 + 8006da2: d1e6 bne.n 8006d72 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - 8006d5c: 687b ldr r3, [r7, #4] - 8006d5e: 681b ldr r3, [r3, #0] - 8006d60: 69db ldr r3, [r3, #28] - 8006d62: f003 0310 and.w r3, r3, #16 - 8006d66: 2b10 cmp r3, #16 - 8006d68: d103 bne.n 8006d72 + 8006da4: 687b ldr r3, [r7, #4] + 8006da6: 681b ldr r3, [r3, #0] + 8006da8: 69db ldr r3, [r3, #28] + 8006daa: f003 0310 and.w r3, r3, #16 + 8006dae: 2b10 cmp r3, #16 + 8006db0: d103 bne.n 8006dba { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 8006d6a: 687b ldr r3, [r7, #4] - 8006d6c: 681b ldr r3, [r3, #0] - 8006d6e: 2210 movs r2, #16 - 8006d70: 621a str r2, [r3, #32] + 8006db2: 687b ldr r3, [r7, #4] + 8006db4: 681b ldr r3, [r3, #0] + 8006db6: 2210 movs r2, #16 + 8006db8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 8006d72: 687b ldr r3, [r7, #4] - 8006d74: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 8006d78: 4619 mov r1, r3 - 8006d7a: 6878 ldr r0, [r7, #4] - 8006d7c: f7ff f804 bl 8005d88 + 8006dba: 687b ldr r3, [r7, #4] + 8006dbc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8006dc0: 4619 mov r1, r3 + 8006dc2: 6878 ldr r0, [r7, #4] + 8006dc4: f7ff f804 bl 8005dd0 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } - 8006d80: e00b b.n 8006d9a + 8006dc8: e00b b.n 8006de2 HAL_UART_RxCpltCallback(huart); - 8006d82: 6878 ldr r0, [r7, #4] - 8006d84: f7fa fb84 bl 8001490 + 8006dca: 6878 ldr r0, [r7, #4] + 8006dcc: f7fa fb84 bl 80014d8 } - 8006d88: e007 b.n 8006d9a + 8006dd0: e007 b.n 8006de2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - 8006d8a: 687b ldr r3, [r7, #4] - 8006d8c: 681b ldr r3, [r3, #0] - 8006d8e: 699a ldr r2, [r3, #24] - 8006d90: 687b ldr r3, [r7, #4] - 8006d92: 681b ldr r3, [r3, #0] - 8006d94: f042 0208 orr.w r2, r2, #8 - 8006d98: 619a str r2, [r3, #24] + 8006dd2: 687b ldr r3, [r7, #4] + 8006dd4: 681b ldr r3, [r3, #0] + 8006dd6: 699a ldr r2, [r3, #24] + 8006dd8: 687b ldr r3, [r7, #4] + 8006dda: 681b ldr r3, [r3, #0] + 8006ddc: f042 0208 orr.w r2, r2, #8 + 8006de0: 619a str r2, [r3, #24] } - 8006d9a: bf00 nop - 8006d9c: 3770 adds r7, #112 @ 0x70 - 8006d9e: 46bd mov sp, r7 - 8006da0: bd80 pop {r7, pc} - 8006da2: bf00 nop - 8006da4: 40008000 .word 0x40008000 + 8006de2: bf00 nop + 8006de4: 3770 adds r7, #112 @ 0x70 + 8006de6: 46bd mov sp, r7 + 8006de8: bd80 pop {r7, pc} + 8006dea: bf00 nop + 8006dec: 40008000 .word 0x40008000 -08006da8 : +08006df0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { - 8006da8: b580 push {r7, lr} - 8006daa: b0ac sub sp, #176 @ 0xb0 - 8006dac: af00 add r7, sp, #0 - 8006dae: 6078 str r0, [r7, #4] + 8006df0: b580 push {r7, lr} + 8006df2: b0ac sub sp, #176 @ 0xb0 + 8006df4: af00 add r7, sp, #0 + 8006df6: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; - 8006db0: 687b ldr r3, [r7, #4] - 8006db2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 - 8006db6: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa + 8006df8: 687b ldr r3, [r7, #4] + 8006dfa: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8006dfe: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); - 8006dba: 687b ldr r3, [r7, #4] - 8006dbc: 681b ldr r3, [r3, #0] - 8006dbe: 69db ldr r3, [r3, #28] - 8006dc0: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8006e02: 687b ldr r3, [r7, #4] + 8006e04: 681b ldr r3, [r3, #0] + 8006e06: 69db ldr r3, [r3, #28] + 8006e08: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); - 8006dc4: 687b ldr r3, [r7, #4] - 8006dc6: 681b ldr r3, [r3, #0] - 8006dc8: 681b ldr r3, [r3, #0] - 8006dca: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 + 8006e0c: 687b ldr r3, [r7, #4] + 8006e0e: 681b ldr r3, [r3, #0] + 8006e10: 681b ldr r3, [r3, #0] + 8006e12: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); - 8006dce: 687b ldr r3, [r7, #4] - 8006dd0: 681b ldr r3, [r3, #0] - 8006dd2: 689b ldr r3, [r3, #8] - 8006dd4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + 8006e16: 687b ldr r3, [r7, #4] + 8006e18: 681b ldr r3, [r3, #0] + 8006e1a: 689b ldr r3, [r3, #8] + 8006e1c: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) - 8006dd8: 687b ldr r3, [r7, #4] - 8006dda: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c - 8006dde: 2b22 cmp r3, #34 @ 0x22 - 8006de0: f040 8183 bne.w 80070ea + 8006e20: 687b ldr r3, [r7, #4] + 8006e22: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 8006e26: 2b22 cmp r3, #34 @ 0x22 + 8006e28: f040 8183 bne.w 8007132 { nb_rx_data = huart->NbRxDataToProcess; - 8006de4: 687b ldr r3, [r7, #4] - 8006de6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 - 8006dea: f8a7 309e strh.w r3, [r7, #158] @ 0x9e + 8006e2c: 687b ldr r3, [r7, #4] + 8006e2e: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8006e32: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) - 8006dee: e126 b.n 800703e + 8006e36: e126 b.n 8007086 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - 8006df0: 687b ldr r3, [r7, #4] - 8006df2: 681b ldr r3, [r3, #0] - 8006df4: 6a5b ldr r3, [r3, #36] @ 0x24 - 8006df6: f8a7 309c strh.w r3, [r7, #156] @ 0x9c + 8006e38: 687b ldr r3, [r7, #4] + 8006e3a: 681b ldr r3, [r3, #0] + 8006e3c: 6a5b ldr r3, [r3, #36] @ 0x24 + 8006e3e: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - 8006dfa: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c - 8006dfe: b2d9 uxtb r1, r3 - 8006e00: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa - 8006e04: b2da uxtb r2, r3 - 8006e06: 687b ldr r3, [r7, #4] - 8006e08: 6d9b ldr r3, [r3, #88] @ 0x58 - 8006e0a: 400a ands r2, r1 - 8006e0c: b2d2 uxtb r2, r2 - 8006e0e: 701a strb r2, [r3, #0] + 8006e42: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c + 8006e46: b2d9 uxtb r1, r3 + 8006e48: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa + 8006e4c: b2da uxtb r2, r3 + 8006e4e: 687b ldr r3, [r7, #4] + 8006e50: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006e52: 400a ands r2, r1 + 8006e54: b2d2 uxtb r2, r2 + 8006e56: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; - 8006e10: 687b ldr r3, [r7, #4] - 8006e12: 6d9b ldr r3, [r3, #88] @ 0x58 - 8006e14: 1c5a adds r2, r3, #1 - 8006e16: 687b ldr r3, [r7, #4] - 8006e18: 659a str r2, [r3, #88] @ 0x58 + 8006e58: 687b ldr r3, [r7, #4] + 8006e5a: 6d9b ldr r3, [r3, #88] @ 0x58 + 8006e5c: 1c5a adds r2, r3, #1 + 8006e5e: 687b ldr r3, [r7, #4] + 8006e60: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; - 8006e1a: 687b ldr r3, [r7, #4] - 8006e1c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8006e20: b29b uxth r3, r3 - 8006e22: 3b01 subs r3, #1 - 8006e24: b29a uxth r2, r3 - 8006e26: 687b ldr r3, [r7, #4] - 8006e28: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 8006e62: 687b ldr r3, [r7, #4] + 8006e64: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006e68: b29b uxth r3, r3 + 8006e6a: 3b01 subs r3, #1 + 8006e6c: b29a uxth r2, r3 + 8006e6e: 687b ldr r3, [r7, #4] + 8006e70: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); - 8006e2c: 687b ldr r3, [r7, #4] - 8006e2e: 681b ldr r3, [r3, #0] - 8006e30: 69db ldr r3, [r3, #28] - 8006e32: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8006e74: 687b ldr r3, [r7, #4] + 8006e76: 681b ldr r3, [r3, #0] + 8006e78: 69db ldr r3, [r3, #28] + 8006e7a: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) - 8006e36: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 8006e3a: f003 0307 and.w r3, r3, #7 - 8006e3e: 2b00 cmp r3, #0 - 8006e40: d053 beq.n 8006eea + 8006e7e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006e82: f003 0307 and.w r3, r3, #7 + 8006e86: 2b00 cmp r3, #0 + 8006e88: d053 beq.n 8006f32 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - 8006e42: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 8006e46: f003 0301 and.w r3, r3, #1 - 8006e4a: 2b00 cmp r3, #0 - 8006e4c: d011 beq.n 8006e72 - 8006e4e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 - 8006e52: f403 7380 and.w r3, r3, #256 @ 0x100 - 8006e56: 2b00 cmp r3, #0 - 8006e58: d00b beq.n 8006e72 + 8006e8a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006e8e: f003 0301 and.w r3, r3, #1 + 8006e92: 2b00 cmp r3, #0 + 8006e94: d011 beq.n 8006eba + 8006e96: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 + 8006e9a: f403 7380 and.w r3, r3, #256 @ 0x100 + 8006e9e: 2b00 cmp r3, #0 + 8006ea0: d00b beq.n 8006eba { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - 8006e5a: 687b ldr r3, [r7, #4] - 8006e5c: 681b ldr r3, [r3, #0] - 8006e5e: 2201 movs r2, #1 - 8006e60: 621a str r2, [r3, #32] + 8006ea2: 687b ldr r3, [r7, #4] + 8006ea4: 681b ldr r3, [r3, #0] + 8006ea6: 2201 movs r2, #1 + 8006ea8: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; - 8006e62: 687b ldr r3, [r7, #4] - 8006e64: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8006e68: f043 0201 orr.w r2, r3, #1 - 8006e6c: 687b ldr r3, [r7, #4] - 8006e6e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8006eaa: 687b ldr r3, [r7, #4] + 8006eac: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006eb0: f043 0201 orr.w r2, r3, #1 + 8006eb4: 687b ldr r3, [r7, #4] + 8006eb6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 8006e72: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 8006e76: f003 0302 and.w r3, r3, #2 - 8006e7a: 2b00 cmp r3, #0 - 8006e7c: d011 beq.n 8006ea2 - 8006e7e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 - 8006e82: f003 0301 and.w r3, r3, #1 - 8006e86: 2b00 cmp r3, #0 - 8006e88: d00b beq.n 8006ea2 + 8006eba: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006ebe: f003 0302 and.w r3, r3, #2 + 8006ec2: 2b00 cmp r3, #0 + 8006ec4: d011 beq.n 8006eea + 8006ec6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006eca: f003 0301 and.w r3, r3, #1 + 8006ece: 2b00 cmp r3, #0 + 8006ed0: d00b beq.n 8006eea { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - 8006e8a: 687b ldr r3, [r7, #4] - 8006e8c: 681b ldr r3, [r3, #0] - 8006e8e: 2202 movs r2, #2 - 8006e90: 621a str r2, [r3, #32] + 8006ed2: 687b ldr r3, [r7, #4] + 8006ed4: 681b ldr r3, [r3, #0] + 8006ed6: 2202 movs r2, #2 + 8006ed8: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; - 8006e92: 687b ldr r3, [r7, #4] - 8006e94: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8006e98: f043 0204 orr.w r2, r3, #4 - 8006e9c: 687b ldr r3, [r7, #4] - 8006e9e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8006eda: 687b ldr r3, [r7, #4] + 8006edc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006ee0: f043 0204 orr.w r2, r3, #4 + 8006ee4: 687b ldr r3, [r7, #4] + 8006ee6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 8006ea2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 8006ea6: f003 0304 and.w r3, r3, #4 - 8006eaa: 2b00 cmp r3, #0 - 8006eac: d011 beq.n 8006ed2 - 8006eae: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 - 8006eb2: f003 0301 and.w r3, r3, #1 - 8006eb6: 2b00 cmp r3, #0 - 8006eb8: d00b beq.n 8006ed2 + 8006eea: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8006eee: f003 0304 and.w r3, r3, #4 + 8006ef2: 2b00 cmp r3, #0 + 8006ef4: d011 beq.n 8006f1a + 8006ef6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 8006efa: f003 0301 and.w r3, r3, #1 + 8006efe: 2b00 cmp r3, #0 + 8006f00: d00b beq.n 8006f1a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - 8006eba: 687b ldr r3, [r7, #4] - 8006ebc: 681b ldr r3, [r3, #0] - 8006ebe: 2204 movs r2, #4 - 8006ec0: 621a str r2, [r3, #32] + 8006f02: 687b ldr r3, [r7, #4] + 8006f04: 681b ldr r3, [r3, #0] + 8006f06: 2204 movs r2, #4 + 8006f08: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; - 8006ec2: 687b ldr r3, [r7, #4] - 8006ec4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8006ec8: f043 0202 orr.w r2, r3, #2 - 8006ecc: 687b ldr r3, [r7, #4] - 8006ece: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8006f0a: 687b ldr r3, [r7, #4] + 8006f0c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006f10: f043 0202 orr.w r2, r3, #2 + 8006f14: 687b ldr r3, [r7, #4] + 8006f16: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) - 8006ed2: 687b ldr r3, [r7, #4] - 8006ed4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8006ed8: 2b00 cmp r3, #0 - 8006eda: d006 beq.n 8006eea + 8006f1a: 687b ldr r3, [r7, #4] + 8006f1c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8006f20: 2b00 cmp r3, #0 + 8006f22: d006 beq.n 8006f32 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 8006edc: 6878 ldr r0, [r7, #4] - 8006ede: f7fe ff49 bl 8005d74 + 8006f24: 6878 ldr r0, [r7, #4] + 8006f26: f7fe ff49 bl 8005dbc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8006ee2: 687b ldr r3, [r7, #4] - 8006ee4: 2200 movs r2, #0 - 8006ee6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8006f2a: 687b ldr r3, [r7, #4] + 8006f2c: 2200 movs r2, #0 + 8006f2e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) - 8006eea: 687b ldr r3, [r7, #4] - 8006eec: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8006ef0: b29b uxth r3, r3 - 8006ef2: 2b00 cmp r3, #0 - 8006ef4: f040 80a3 bne.w 800703e + 8006f32: 687b ldr r3, [r7, #4] + 8006f34: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 8006f38: b29b uxth r3, r3 + 8006f3a: 2b00 cmp r3, #0 + 8006f3c: f040 80a3 bne.w 8007086 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 8006ef8: 687b ldr r3, [r7, #4] - 8006efa: 681b ldr r3, [r3, #0] - 8006efc: 673b str r3, [r7, #112] @ 0x70 + 8006f40: 687b ldr r3, [r7, #4] + 8006f42: 681b ldr r3, [r3, #0] + 8006f44: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006efe: 6f3b ldr r3, [r7, #112] @ 0x70 - 8006f00: e853 3f00 ldrex r3, [r3] - 8006f04: 66fb str r3, [r7, #108] @ 0x6c + 8006f46: 6f3b ldr r3, [r7, #112] @ 0x70 + 8006f48: e853 3f00 ldrex r3, [r3] + 8006f4c: 66fb str r3, [r7, #108] @ 0x6c return(result); - 8006f06: 6efb ldr r3, [r7, #108] @ 0x6c - 8006f08: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8006f0c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 - 8006f10: 687b ldr r3, [r7, #4] - 8006f12: 681b ldr r3, [r3, #0] - 8006f14: 461a mov r2, r3 - 8006f16: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 - 8006f1a: 67fb str r3, [r7, #124] @ 0x7c - 8006f1c: 67ba str r2, [r7, #120] @ 0x78 + 8006f4e: 6efb ldr r3, [r7, #108] @ 0x6c + 8006f50: f423 7380 bic.w r3, r3, #256 @ 0x100 + 8006f54: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8006f58: 687b ldr r3, [r7, #4] + 8006f5a: 681b ldr r3, [r3, #0] + 8006f5c: 461a mov r2, r3 + 8006f5e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 + 8006f62: 67fb str r3, [r7, #124] @ 0x7c + 8006f64: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006f1e: 6fb9 ldr r1, [r7, #120] @ 0x78 - 8006f20: 6ffa ldr r2, [r7, #124] @ 0x7c - 8006f22: e841 2300 strex r3, r2, [r1] - 8006f26: 677b str r3, [r7, #116] @ 0x74 + 8006f66: 6fb9 ldr r1, [r7, #120] @ 0x78 + 8006f68: 6ffa ldr r2, [r7, #124] @ 0x7c + 8006f6a: e841 2300 strex r3, r2, [r1] + 8006f6e: 677b str r3, [r7, #116] @ 0x74 return(result); - 8006f28: 6f7b ldr r3, [r7, #116] @ 0x74 - 8006f2a: 2b00 cmp r3, #0 - 8006f2c: d1e4 bne.n 8006ef8 + 8006f70: 6f7b ldr r3, [r7, #116] @ 0x74 + 8006f72: 2b00 cmp r3, #0 + 8006f74: d1e4 bne.n 8006f40 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - 8006f2e: 687b ldr r3, [r7, #4] - 8006f30: 681b ldr r3, [r3, #0] - 8006f32: 3308 adds r3, #8 - 8006f34: 65fb str r3, [r7, #92] @ 0x5c + 8006f76: 687b ldr r3, [r7, #4] + 8006f78: 681b ldr r3, [r3, #0] + 8006f7a: 3308 adds r3, #8 + 8006f7c: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006f36: 6dfb ldr r3, [r7, #92] @ 0x5c - 8006f38: e853 3f00 ldrex r3, [r3] - 8006f3c: 65bb str r3, [r7, #88] @ 0x58 + 8006f7e: 6dfb ldr r3, [r7, #92] @ 0x5c + 8006f80: e853 3f00 ldrex r3, [r3] + 8006f84: 65bb str r3, [r7, #88] @ 0x58 return(result); - 8006f3e: 6dbb ldr r3, [r7, #88] @ 0x58 - 8006f40: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 8006f44: f023 0301 bic.w r3, r3, #1 - 8006f48: f8c7 3094 str.w r3, [r7, #148] @ 0x94 - 8006f4c: 687b ldr r3, [r7, #4] - 8006f4e: 681b ldr r3, [r3, #0] - 8006f50: 3308 adds r3, #8 - 8006f52: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 - 8006f56: 66ba str r2, [r7, #104] @ 0x68 - 8006f58: 667b str r3, [r7, #100] @ 0x64 + 8006f86: 6dbb ldr r3, [r7, #88] @ 0x58 + 8006f88: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 8006f8c: f023 0301 bic.w r3, r3, #1 + 8006f90: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8006f94: 687b ldr r3, [r7, #4] + 8006f96: 681b ldr r3, [r3, #0] + 8006f98: 3308 adds r3, #8 + 8006f9a: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 + 8006f9e: 66ba str r2, [r7, #104] @ 0x68 + 8006fa0: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006f5a: 6e79 ldr r1, [r7, #100] @ 0x64 - 8006f5c: 6eba ldr r2, [r7, #104] @ 0x68 - 8006f5e: e841 2300 strex r3, r2, [r1] - 8006f62: 663b str r3, [r7, #96] @ 0x60 + 8006fa2: 6e79 ldr r1, [r7, #100] @ 0x64 + 8006fa4: 6eba ldr r2, [r7, #104] @ 0x68 + 8006fa6: e841 2300 strex r3, r2, [r1] + 8006faa: 663b str r3, [r7, #96] @ 0x60 return(result); - 8006f64: 6e3b ldr r3, [r7, #96] @ 0x60 - 8006f66: 2b00 cmp r3, #0 - 8006f68: d1e1 bne.n 8006f2e + 8006fac: 6e3b ldr r3, [r7, #96] @ 0x60 + 8006fae: 2b00 cmp r3, #0 + 8006fb0: d1e1 bne.n 8006f76 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8006f6a: 687b ldr r3, [r7, #4] - 8006f6c: 2220 movs r2, #32 - 8006f6e: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 8006fb2: 687b ldr r3, [r7, #4] + 8006fb4: 2220 movs r2, #32 + 8006fb6: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; - 8006f72: 687b ldr r3, [r7, #4] - 8006f74: 2200 movs r2, #0 - 8006f76: 675a str r2, [r3, #116] @ 0x74 + 8006fba: 687b ldr r3, [r7, #4] + 8006fbc: 2200 movs r2, #0 + 8006fbe: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; - 8006f78: 687b ldr r3, [r7, #4] - 8006f7a: 2200 movs r2, #0 - 8006f7c: 671a str r2, [r3, #112] @ 0x70 + 8006fc0: 687b ldr r3, [r7, #4] + 8006fc2: 2200 movs r2, #0 + 8006fc4: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) - 8006f7e: 687b ldr r3, [r7, #4] - 8006f80: 681b ldr r3, [r3, #0] - 8006f82: 4a60 ldr r2, [pc, #384] @ (8007104 ) - 8006f84: 4293 cmp r3, r2 - 8006f86: d021 beq.n 8006fcc + 8006fc6: 687b ldr r3, [r7, #4] + 8006fc8: 681b ldr r3, [r3, #0] + 8006fca: 4a60 ldr r2, [pc, #384] @ (800714c ) + 8006fcc: 4293 cmp r3, r2 + 8006fce: d021 beq.n 8007014 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - 8006f88: 687b ldr r3, [r7, #4] - 8006f8a: 681b ldr r3, [r3, #0] - 8006f8c: 685b ldr r3, [r3, #4] - 8006f8e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 8006f92: 2b00 cmp r3, #0 - 8006f94: d01a beq.n 8006fcc + 8006fd0: 687b ldr r3, [r7, #4] + 8006fd2: 681b ldr r3, [r3, #0] + 8006fd4: 685b ldr r3, [r3, #4] + 8006fd6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8006fda: 2b00 cmp r3, #0 + 8006fdc: d01a beq.n 8007014 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - 8006f96: 687b ldr r3, [r7, #4] - 8006f98: 681b ldr r3, [r3, #0] - 8006f9a: 64bb str r3, [r7, #72] @ 0x48 + 8006fde: 687b ldr r3, [r7, #4] + 8006fe0: 681b ldr r3, [r3, #0] + 8006fe2: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006f9c: 6cbb ldr r3, [r7, #72] @ 0x48 - 8006f9e: e853 3f00 ldrex r3, [r3] - 8006fa2: 647b str r3, [r7, #68] @ 0x44 + 8006fe4: 6cbb ldr r3, [r7, #72] @ 0x48 + 8006fe6: e853 3f00 ldrex r3, [r3] + 8006fea: 647b str r3, [r7, #68] @ 0x44 return(result); - 8006fa4: 6c7b ldr r3, [r7, #68] @ 0x44 - 8006fa6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 - 8006faa: f8c7 3090 str.w r3, [r7, #144] @ 0x90 - 8006fae: 687b ldr r3, [r7, #4] - 8006fb0: 681b ldr r3, [r3, #0] - 8006fb2: 461a mov r2, r3 - 8006fb4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 - 8006fb8: 657b str r3, [r7, #84] @ 0x54 - 8006fba: 653a str r2, [r7, #80] @ 0x50 + 8006fec: 6c7b ldr r3, [r7, #68] @ 0x44 + 8006fee: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 8006ff2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 8006ff6: 687b ldr r3, [r7, #4] + 8006ff8: 681b ldr r3, [r3, #0] + 8006ffa: 461a mov r2, r3 + 8006ffc: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 + 8007000: 657b str r3, [r7, #84] @ 0x54 + 8007002: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8006fbc: 6d39 ldr r1, [r7, #80] @ 0x50 - 8006fbe: 6d7a ldr r2, [r7, #84] @ 0x54 - 8006fc0: e841 2300 strex r3, r2, [r1] - 8006fc4: 64fb str r3, [r7, #76] @ 0x4c + 8007004: 6d39 ldr r1, [r7, #80] @ 0x50 + 8007006: 6d7a ldr r2, [r7, #84] @ 0x54 + 8007008: e841 2300 strex r3, r2, [r1] + 800700c: 64fb str r3, [r7, #76] @ 0x4c return(result); - 8006fc6: 6cfb ldr r3, [r7, #76] @ 0x4c - 8006fc8: 2b00 cmp r3, #0 - 8006fca: d1e4 bne.n 8006f96 + 800700e: 6cfb ldr r3, [r7, #76] @ 0x4c + 8007010: 2b00 cmp r3, #0 + 8007012: d1e4 bne.n 8006fde } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8006fcc: 687b ldr r3, [r7, #4] - 8006fce: 6edb ldr r3, [r3, #108] @ 0x6c - 8006fd0: 2b01 cmp r3, #1 - 8006fd2: d130 bne.n 8007036 + 8007014: 687b ldr r3, [r7, #4] + 8007016: 6edb ldr r3, [r3, #108] @ 0x6c + 8007018: 2b01 cmp r3, #1 + 800701a: d130 bne.n 800707e { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8006fd4: 687b ldr r3, [r7, #4] - 8006fd6: 2200 movs r2, #0 - 8006fd8: 66da str r2, [r3, #108] @ 0x6c + 800701c: 687b ldr r3, [r7, #4] + 800701e: 2200 movs r2, #0 + 8007020: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8006fda: 687b ldr r3, [r7, #4] - 8006fdc: 681b ldr r3, [r3, #0] - 8006fde: 637b str r3, [r7, #52] @ 0x34 + 8007022: 687b ldr r3, [r7, #4] + 8007024: 681b ldr r3, [r3, #0] + 8007026: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8006fe0: 6b7b ldr r3, [r7, #52] @ 0x34 - 8006fe2: e853 3f00 ldrex r3, [r3] - 8006fe6: 633b str r3, [r7, #48] @ 0x30 + 8007028: 6b7b ldr r3, [r7, #52] @ 0x34 + 800702a: e853 3f00 ldrex r3, [r3] + 800702e: 633b str r3, [r7, #48] @ 0x30 return(result); - 8006fe8: 6b3b ldr r3, [r7, #48] @ 0x30 - 8006fea: f023 0310 bic.w r3, r3, #16 - 8006fee: f8c7 308c str.w r3, [r7, #140] @ 0x8c - 8006ff2: 687b ldr r3, [r7, #4] - 8006ff4: 681b ldr r3, [r3, #0] - 8006ff6: 461a mov r2, r3 - 8006ff8: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c - 8006ffc: 643b str r3, [r7, #64] @ 0x40 - 8006ffe: 63fa str r2, [r7, #60] @ 0x3c + 8007030: 6b3b ldr r3, [r7, #48] @ 0x30 + 8007032: f023 0310 bic.w r3, r3, #16 + 8007036: f8c7 308c str.w r3, [r7, #140] @ 0x8c + 800703a: 687b ldr r3, [r7, #4] + 800703c: 681b ldr r3, [r3, #0] + 800703e: 461a mov r2, r3 + 8007040: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c + 8007044: 643b str r3, [r7, #64] @ 0x40 + 8007046: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8007000: 6bf9 ldr r1, [r7, #60] @ 0x3c - 8007002: 6c3a ldr r2, [r7, #64] @ 0x40 - 8007004: e841 2300 strex r3, r2, [r1] - 8007008: 63bb str r3, [r7, #56] @ 0x38 + 8007048: 6bf9 ldr r1, [r7, #60] @ 0x3c + 800704a: 6c3a ldr r2, [r7, #64] @ 0x40 + 800704c: e841 2300 strex r3, r2, [r1] + 8007050: 63bb str r3, [r7, #56] @ 0x38 return(result); - 800700a: 6bbb ldr r3, [r7, #56] @ 0x38 - 800700c: 2b00 cmp r3, #0 - 800700e: d1e4 bne.n 8006fda + 8007052: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007054: 2b00 cmp r3, #0 + 8007056: d1e4 bne.n 8007022 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - 8007010: 687b ldr r3, [r7, #4] - 8007012: 681b ldr r3, [r3, #0] - 8007014: 69db ldr r3, [r3, #28] - 8007016: f003 0310 and.w r3, r3, #16 - 800701a: 2b10 cmp r3, #16 - 800701c: d103 bne.n 8007026 + 8007058: 687b ldr r3, [r7, #4] + 800705a: 681b ldr r3, [r3, #0] + 800705c: 69db ldr r3, [r3, #28] + 800705e: f003 0310 and.w r3, r3, #16 + 8007062: 2b10 cmp r3, #16 + 8007064: d103 bne.n 800706e { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 800701e: 687b ldr r3, [r7, #4] - 8007020: 681b ldr r3, [r3, #0] - 8007022: 2210 movs r2, #16 - 8007024: 621a str r2, [r3, #32] + 8007066: 687b ldr r3, [r7, #4] + 8007068: 681b ldr r3, [r3, #0] + 800706a: 2210 movs r2, #16 + 800706c: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 8007026: 687b ldr r3, [r7, #4] - 8007028: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 800702c: 4619 mov r1, r3 - 800702e: 6878 ldr r0, [r7, #4] - 8007030: f7fe feaa bl 8005d88 + 800706e: 687b ldr r3, [r7, #4] + 8007070: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 8007074: 4619 mov r1, r3 + 8007076: 6878 ldr r0, [r7, #4] + 8007078: f7fe feaa bl 8005dd0 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; - 8007034: e00e b.n 8007054 + 800707c: e00e b.n 800709c HAL_UART_RxCpltCallback(huart); - 8007036: 6878 ldr r0, [r7, #4] - 8007038: f7fa fa2a bl 8001490 + 800707e: 6878 ldr r0, [r7, #4] + 8007080: f7fa fa2a bl 80014d8 break; - 800703c: e00a b.n 8007054 + 8007084: e00a b.n 800709c while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) - 800703e: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e - 8007042: 2b00 cmp r3, #0 - 8007044: d006 beq.n 8007054 - 8007046: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 800704a: f003 0320 and.w r3, r3, #32 - 800704e: 2b00 cmp r3, #0 - 8007050: f47f aece bne.w 8006df0 + 8007086: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e + 800708a: 2b00 cmp r3, #0 + 800708c: d006 beq.n 800709c + 800708e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8007092: f003 0320 and.w r3, r3, #32 + 8007096: 2b00 cmp r3, #0 + 8007098: f47f aece bne.w 8006e38 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; - 8007054: 687b ldr r3, [r7, #4] - 8007056: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 800705a: f8a7 308a strh.w r3, [r7, #138] @ 0x8a + 800709c: 687b ldr r3, [r7, #4] + 800709e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80070a2: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) - 800705e: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a - 8007062: 2b00 cmp r3, #0 - 8007064: d049 beq.n 80070fa - 8007066: 687b ldr r3, [r7, #4] - 8007068: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 - 800706c: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a - 8007070: 429a cmp r2, r3 - 8007072: d242 bcs.n 80070fa + 80070a6: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a + 80070aa: 2b00 cmp r3, #0 + 80070ac: d049 beq.n 8007142 + 80070ae: 687b ldr r3, [r7, #4] + 80070b0: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 80070b4: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a + 80070b8: 429a cmp r2, r3 + 80070ba: d242 bcs.n 8007142 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - 8007074: 687b ldr r3, [r7, #4] - 8007076: 681b ldr r3, [r3, #0] - 8007078: 3308 adds r3, #8 - 800707a: 623b str r3, [r7, #32] + 80070bc: 687b ldr r3, [r7, #4] + 80070be: 681b ldr r3, [r3, #0] + 80070c0: 3308 adds r3, #8 + 80070c2: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800707c: 6a3b ldr r3, [r7, #32] - 800707e: e853 3f00 ldrex r3, [r3] - 8007082: 61fb str r3, [r7, #28] + 80070c4: 6a3b ldr r3, [r7, #32] + 80070c6: e853 3f00 ldrex r3, [r3] + 80070ca: 61fb str r3, [r7, #28] return(result); - 8007084: 69fb ldr r3, [r7, #28] - 8007086: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 800708a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 - 800708e: 687b ldr r3, [r7, #4] - 8007090: 681b ldr r3, [r3, #0] - 8007092: 3308 adds r3, #8 - 8007094: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 - 8007098: 62fa str r2, [r7, #44] @ 0x2c - 800709a: 62bb str r3, [r7, #40] @ 0x28 + 80070cc: 69fb ldr r3, [r7, #28] + 80070ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80070d2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 80070d6: 687b ldr r3, [r7, #4] + 80070d8: 681b ldr r3, [r3, #0] + 80070da: 3308 adds r3, #8 + 80070dc: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 + 80070e0: 62fa str r2, [r7, #44] @ 0x2c + 80070e2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800709c: 6ab9 ldr r1, [r7, #40] @ 0x28 - 800709e: 6afa ldr r2, [r7, #44] @ 0x2c - 80070a0: e841 2300 strex r3, r2, [r1] - 80070a4: 627b str r3, [r7, #36] @ 0x24 + 80070e4: 6ab9 ldr r1, [r7, #40] @ 0x28 + 80070e6: 6afa ldr r2, [r7, #44] @ 0x2c + 80070e8: e841 2300 strex r3, r2, [r1] + 80070ec: 627b str r3, [r7, #36] @ 0x24 return(result); - 80070a6: 6a7b ldr r3, [r7, #36] @ 0x24 - 80070a8: 2b00 cmp r3, #0 - 80070aa: d1e3 bne.n 8007074 + 80070ee: 6a7b ldr r3, [r7, #36] @ 0x24 + 80070f0: 2b00 cmp r3, #0 + 80070f2: d1e3 bne.n 80070bc /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; - 80070ac: 687b ldr r3, [r7, #4] - 80070ae: 4a16 ldr r2, [pc, #88] @ (8007108 ) - 80070b0: 675a str r2, [r3, #116] @ 0x74 + 80070f4: 687b ldr r3, [r7, #4] + 80070f6: 4a16 ldr r2, [pc, #88] @ (8007150 ) + 80070f8: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - 80070b2: 687b ldr r3, [r7, #4] - 80070b4: 681b ldr r3, [r3, #0] - 80070b6: 60fb str r3, [r7, #12] + 80070fa: 687b ldr r3, [r7, #4] + 80070fc: 681b ldr r3, [r3, #0] + 80070fe: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80070b8: 68fb ldr r3, [r7, #12] - 80070ba: e853 3f00 ldrex r3, [r3] - 80070be: 60bb str r3, [r7, #8] + 8007100: 68fb ldr r3, [r7, #12] + 8007102: e853 3f00 ldrex r3, [r3] + 8007106: 60bb str r3, [r7, #8] return(result); - 80070c0: 68bb ldr r3, [r7, #8] - 80070c2: f043 0320 orr.w r3, r3, #32 - 80070c6: f8c7 3080 str.w r3, [r7, #128] @ 0x80 - 80070ca: 687b ldr r3, [r7, #4] - 80070cc: 681b ldr r3, [r3, #0] - 80070ce: 461a mov r2, r3 - 80070d0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 - 80070d4: 61bb str r3, [r7, #24] - 80070d6: 617a str r2, [r7, #20] + 8007108: 68bb ldr r3, [r7, #8] + 800710a: f043 0320 orr.w r3, r3, #32 + 800710e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 8007112: 687b ldr r3, [r7, #4] + 8007114: 681b ldr r3, [r3, #0] + 8007116: 461a mov r2, r3 + 8007118: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 + 800711c: 61bb str r3, [r7, #24] + 800711e: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80070d8: 6979 ldr r1, [r7, #20] - 80070da: 69ba ldr r2, [r7, #24] - 80070dc: e841 2300 strex r3, r2, [r1] - 80070e0: 613b str r3, [r7, #16] + 8007120: 6979 ldr r1, [r7, #20] + 8007122: 69ba ldr r2, [r7, #24] + 8007124: e841 2300 strex r3, r2, [r1] + 8007128: 613b str r3, [r7, #16] return(result); - 80070e2: 693b ldr r3, [r7, #16] - 80070e4: 2b00 cmp r3, #0 - 80070e6: d1e4 bne.n 80070b2 + 800712a: 693b ldr r3, [r7, #16] + 800712c: 2b00 cmp r3, #0 + 800712e: d1e4 bne.n 80070fa else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } - 80070e8: e007 b.n 80070fa + 8007130: e007 b.n 8007142 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - 80070ea: 687b ldr r3, [r7, #4] - 80070ec: 681b ldr r3, [r3, #0] - 80070ee: 699a ldr r2, [r3, #24] - 80070f0: 687b ldr r3, [r7, #4] - 80070f2: 681b ldr r3, [r3, #0] - 80070f4: f042 0208 orr.w r2, r2, #8 - 80070f8: 619a str r2, [r3, #24] + 8007132: 687b ldr r3, [r7, #4] + 8007134: 681b ldr r3, [r3, #0] + 8007136: 699a ldr r2, [r3, #24] + 8007138: 687b ldr r3, [r7, #4] + 800713a: 681b ldr r3, [r3, #0] + 800713c: f042 0208 orr.w r2, r2, #8 + 8007140: 619a str r2, [r3, #24] } - 80070fa: bf00 nop - 80070fc: 37b0 adds r7, #176 @ 0xb0 - 80070fe: 46bd mov sp, r7 - 8007100: bd80 pop {r7, pc} - 8007102: bf00 nop - 8007104: 40008000 .word 0x40008000 - 8007108: 08006a39 .word 0x08006a39 + 8007142: bf00 nop + 8007144: 37b0 adds r7, #176 @ 0xb0 + 8007146: 46bd mov sp, r7 + 8007148: bd80 pop {r7, pc} + 800714a: bf00 nop + 800714c: 40008000 .word 0x40008000 + 8007150: 08006a81 .word 0x08006a81 -0800710c : +08007154 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - 800710c: b580 push {r7, lr} - 800710e: b0ae sub sp, #184 @ 0xb8 - 8007110: af00 add r7, sp, #0 - 8007112: 6078 str r0, [r7, #4] + 8007154: b580 push {r7, lr} + 8007156: b0ae sub sp, #184 @ 0xb8 + 8007158: af00 add r7, sp, #0 + 800715a: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; - 8007114: 687b ldr r3, [r7, #4] - 8007116: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 - 800711a: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 + 800715c: 687b ldr r3, [r7, #4] + 800715e: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 + 8007162: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); - 800711e: 687b ldr r3, [r7, #4] - 8007120: 681b ldr r3, [r3, #0] - 8007122: 69db ldr r3, [r3, #28] - 8007124: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 8007166: 687b ldr r3, [r7, #4] + 8007168: 681b ldr r3, [r3, #0] + 800716a: 69db ldr r3, [r3, #28] + 800716c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); - 8007128: 687b ldr r3, [r7, #4] - 800712a: 681b ldr r3, [r3, #0] - 800712c: 681b ldr r3, [r3, #0] - 800712e: f8c7 30ac str.w r3, [r7, #172] @ 0xac + 8007170: 687b ldr r3, [r7, #4] + 8007172: 681b ldr r3, [r3, #0] + 8007174: 681b ldr r3, [r3, #0] + 8007176: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); - 8007132: 687b ldr r3, [r7, #4] - 8007134: 681b ldr r3, [r3, #0] - 8007136: 689b ldr r3, [r3, #8] - 8007138: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 + 800717a: 687b ldr r3, [r7, #4] + 800717c: 681b ldr r3, [r3, #0] + 800717e: 689b ldr r3, [r3, #8] + 8007180: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) - 800713c: 687b ldr r3, [r7, #4] - 800713e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c - 8007142: 2b22 cmp r3, #34 @ 0x22 - 8007144: f040 8187 bne.w 8007456 + 8007184: 687b ldr r3, [r7, #4] + 8007186: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c + 800718a: 2b22 cmp r3, #34 @ 0x22 + 800718c: f040 8187 bne.w 800749e { nb_rx_data = huart->NbRxDataToProcess; - 8007148: 687b ldr r3, [r7, #4] - 800714a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 - 800714e: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 + 8007190: 687b ldr r3, [r7, #4] + 8007192: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8007196: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) - 8007152: e12a b.n 80073aa + 800719a: e12a b.n 80073f2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - 8007154: 687b ldr r3, [r7, #4] - 8007156: 681b ldr r3, [r3, #0] - 8007158: 6a5b ldr r3, [r3, #36] @ 0x24 - 800715a: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 + 800719c: 687b ldr r3, [r7, #4] + 800719e: 681b ldr r3, [r3, #0] + 80071a0: 6a5b ldr r3, [r3, #36] @ 0x24 + 80071a2: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; - 800715e: 687b ldr r3, [r7, #4] - 8007160: 6d9b ldr r3, [r3, #88] @ 0x58 - 8007162: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 + 80071a6: 687b ldr r3, [r7, #4] + 80071a8: 6d9b ldr r3, [r3, #88] @ 0x58 + 80071aa: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); - 8007166: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 - 800716a: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 - 800716e: 4013 ands r3, r2 - 8007170: b29a uxth r2, r3 - 8007172: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 - 8007176: 801a strh r2, [r3, #0] + 80071ae: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 + 80071b2: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 + 80071b6: 4013 ands r3, r2 + 80071b8: b29a uxth r2, r3 + 80071ba: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 + 80071be: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; - 8007178: 687b ldr r3, [r7, #4] - 800717a: 6d9b ldr r3, [r3, #88] @ 0x58 - 800717c: 1c9a adds r2, r3, #2 - 800717e: 687b ldr r3, [r7, #4] - 8007180: 659a str r2, [r3, #88] @ 0x58 + 80071c0: 687b ldr r3, [r7, #4] + 80071c2: 6d9b ldr r3, [r3, #88] @ 0x58 + 80071c4: 1c9a adds r2, r3, #2 + 80071c6: 687b ldr r3, [r7, #4] + 80071c8: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; - 8007182: 687b ldr r3, [r7, #4] - 8007184: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8007188: b29b uxth r3, r3 - 800718a: 3b01 subs r3, #1 - 800718c: b29a uxth r2, r3 - 800718e: 687b ldr r3, [r7, #4] - 8007190: f8a3 205e strh.w r2, [r3, #94] @ 0x5e + 80071ca: 687b ldr r3, [r7, #4] + 80071cc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80071d0: b29b uxth r3, r3 + 80071d2: 3b01 subs r3, #1 + 80071d4: b29a uxth r2, r3 + 80071d6: 687b ldr r3, [r7, #4] + 80071d8: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); - 8007194: 687b ldr r3, [r7, #4] - 8007196: 681b ldr r3, [r3, #0] - 8007198: 69db ldr r3, [r3, #28] - 800719a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 + 80071dc: 687b ldr r3, [r7, #4] + 80071de: 681b ldr r3, [r3, #0] + 80071e0: 69db ldr r3, [r3, #28] + 80071e2: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) - 800719e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 80071a2: f003 0307 and.w r3, r3, #7 - 80071a6: 2b00 cmp r3, #0 - 80071a8: d053 beq.n 8007252 + 80071e6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 80071ea: f003 0307 and.w r3, r3, #7 + 80071ee: 2b00 cmp r3, #0 + 80071f0: d053 beq.n 800729a { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - 80071aa: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 80071ae: f003 0301 and.w r3, r3, #1 - 80071b2: 2b00 cmp r3, #0 - 80071b4: d011 beq.n 80071da - 80071b6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac - 80071ba: f403 7380 and.w r3, r3, #256 @ 0x100 - 80071be: 2b00 cmp r3, #0 - 80071c0: d00b beq.n 80071da + 80071f2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 80071f6: f003 0301 and.w r3, r3, #1 + 80071fa: 2b00 cmp r3, #0 + 80071fc: d011 beq.n 8007222 + 80071fe: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac + 8007202: f403 7380 and.w r3, r3, #256 @ 0x100 + 8007206: 2b00 cmp r3, #0 + 8007208: d00b beq.n 8007222 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - 80071c2: 687b ldr r3, [r7, #4] - 80071c4: 681b ldr r3, [r3, #0] - 80071c6: 2201 movs r2, #1 - 80071c8: 621a str r2, [r3, #32] + 800720a: 687b ldr r3, [r7, #4] + 800720c: 681b ldr r3, [r3, #0] + 800720e: 2201 movs r2, #1 + 8007210: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; - 80071ca: 687b ldr r3, [r7, #4] - 80071cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 80071d0: f043 0201 orr.w r2, r3, #1 - 80071d4: 687b ldr r3, [r7, #4] - 80071d6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8007212: 687b ldr r3, [r7, #4] + 8007214: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8007218: f043 0201 orr.w r2, r3, #1 + 800721c: 687b ldr r3, [r7, #4] + 800721e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 80071da: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 80071de: f003 0302 and.w r3, r3, #2 - 80071e2: 2b00 cmp r3, #0 - 80071e4: d011 beq.n 800720a - 80071e6: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 - 80071ea: f003 0301 and.w r3, r3, #1 - 80071ee: 2b00 cmp r3, #0 - 80071f0: d00b beq.n 800720a + 8007222: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007226: f003 0302 and.w r3, r3, #2 + 800722a: 2b00 cmp r3, #0 + 800722c: d011 beq.n 8007252 + 800722e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 8007232: f003 0301 and.w r3, r3, #1 + 8007236: 2b00 cmp r3, #0 + 8007238: d00b beq.n 8007252 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - 80071f2: 687b ldr r3, [r7, #4] - 80071f4: 681b ldr r3, [r3, #0] - 80071f6: 2202 movs r2, #2 - 80071f8: 621a str r2, [r3, #32] + 800723a: 687b ldr r3, [r7, #4] + 800723c: 681b ldr r3, [r3, #0] + 800723e: 2202 movs r2, #2 + 8007240: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; - 80071fa: 687b ldr r3, [r7, #4] - 80071fc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8007200: f043 0204 orr.w r2, r3, #4 - 8007204: 687b ldr r3, [r7, #4] - 8007206: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8007242: 687b ldr r3, [r7, #4] + 8007244: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8007248: f043 0204 orr.w r2, r3, #4 + 800724c: 687b ldr r3, [r7, #4] + 800724e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - 800720a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 800720e: f003 0304 and.w r3, r3, #4 - 8007212: 2b00 cmp r3, #0 - 8007214: d011 beq.n 800723a - 8007216: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 - 800721a: f003 0301 and.w r3, r3, #1 - 800721e: 2b00 cmp r3, #0 - 8007220: d00b beq.n 800723a + 8007252: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 8007256: f003 0304 and.w r3, r3, #4 + 800725a: 2b00 cmp r3, #0 + 800725c: d011 beq.n 8007282 + 800725e: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 + 8007262: f003 0301 and.w r3, r3, #1 + 8007266: 2b00 cmp r3, #0 + 8007268: d00b beq.n 8007282 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - 8007222: 687b ldr r3, [r7, #4] - 8007224: 681b ldr r3, [r3, #0] - 8007226: 2204 movs r2, #4 - 8007228: 621a str r2, [r3, #32] + 800726a: 687b ldr r3, [r7, #4] + 800726c: 681b ldr r3, [r3, #0] + 800726e: 2204 movs r2, #4 + 8007270: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; - 800722a: 687b ldr r3, [r7, #4] - 800722c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8007230: f043 0202 orr.w r2, r3, #2 - 8007234: 687b ldr r3, [r7, #4] - 8007236: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8007272: 687b ldr r3, [r7, #4] + 8007274: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8007278: f043 0202 orr.w r2, r3, #2 + 800727c: 687b ldr r3, [r7, #4] + 800727e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) - 800723a: 687b ldr r3, [r7, #4] - 800723c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 - 8007240: 2b00 cmp r3, #0 - 8007242: d006 beq.n 8007252 + 8007282: 687b ldr r3, [r7, #4] + 8007284: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 + 8007288: 2b00 cmp r3, #0 + 800728a: d006 beq.n 800729a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); - 8007244: 6878 ldr r0, [r7, #4] - 8007246: f7fe fd95 bl 8005d74 + 800728c: 6878 ldr r0, [r7, #4] + 800728e: f7fe fd95 bl 8005dbc #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 800724a: 687b ldr r3, [r7, #4] - 800724c: 2200 movs r2, #0 - 800724e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 + 8007292: 687b ldr r3, [r7, #4] + 8007294: 2200 movs r2, #0 + 8007296: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) - 8007252: 687b ldr r3, [r7, #4] - 8007254: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 8007258: b29b uxth r3, r3 - 800725a: 2b00 cmp r3, #0 - 800725c: f040 80a5 bne.w 80073aa + 800729a: 687b ldr r3, [r7, #4] + 800729c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 80072a0: b29b uxth r3, r3 + 80072a2: 2b00 cmp r3, #0 + 80072a4: f040 80a5 bne.w 80073f2 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - 8007260: 687b ldr r3, [r7, #4] - 8007262: 681b ldr r3, [r3, #0] - 8007264: 677b str r3, [r7, #116] @ 0x74 + 80072a8: 687b ldr r3, [r7, #4] + 80072aa: 681b ldr r3, [r3, #0] + 80072ac: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8007266: 6f7b ldr r3, [r7, #116] @ 0x74 - 8007268: e853 3f00 ldrex r3, [r3] - 800726c: 673b str r3, [r7, #112] @ 0x70 + 80072ae: 6f7b ldr r3, [r7, #116] @ 0x74 + 80072b0: e853 3f00 ldrex r3, [r3] + 80072b4: 673b str r3, [r7, #112] @ 0x70 return(result); - 800726e: 6f3b ldr r3, [r7, #112] @ 0x70 - 8007270: f423 7380 bic.w r3, r3, #256 @ 0x100 - 8007274: f8c7 309c str.w r3, [r7, #156] @ 0x9c - 8007278: 687b ldr r3, [r7, #4] - 800727a: 681b ldr r3, [r3, #0] - 800727c: 461a mov r2, r3 - 800727e: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c - 8007282: f8c7 3080 str.w r3, [r7, #128] @ 0x80 - 8007286: 67fa str r2, [r7, #124] @ 0x7c + 80072b6: 6f3b ldr r3, [r7, #112] @ 0x70 + 80072b8: f423 7380 bic.w r3, r3, #256 @ 0x100 + 80072bc: f8c7 309c str.w r3, [r7, #156] @ 0x9c + 80072c0: 687b ldr r3, [r7, #4] + 80072c2: 681b ldr r3, [r3, #0] + 80072c4: 461a mov r2, r3 + 80072c6: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c + 80072ca: f8c7 3080 str.w r3, [r7, #128] @ 0x80 + 80072ce: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8007288: 6ff9 ldr r1, [r7, #124] @ 0x7c - 800728a: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 - 800728e: e841 2300 strex r3, r2, [r1] - 8007292: 67bb str r3, [r7, #120] @ 0x78 + 80072d0: 6ff9 ldr r1, [r7, #124] @ 0x7c + 80072d2: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 + 80072d6: e841 2300 strex r3, r2, [r1] + 80072da: 67bb str r3, [r7, #120] @ 0x78 return(result); - 8007294: 6fbb ldr r3, [r7, #120] @ 0x78 - 8007296: 2b00 cmp r3, #0 - 8007298: d1e2 bne.n 8007260 + 80072dc: 6fbb ldr r3, [r7, #120] @ 0x78 + 80072de: 2b00 cmp r3, #0 + 80072e0: d1e2 bne.n 80072a8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - 800729a: 687b ldr r3, [r7, #4] - 800729c: 681b ldr r3, [r3, #0] - 800729e: 3308 adds r3, #8 - 80072a0: 663b str r3, [r7, #96] @ 0x60 + 80072e2: 687b ldr r3, [r7, #4] + 80072e4: 681b ldr r3, [r3, #0] + 80072e6: 3308 adds r3, #8 + 80072e8: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80072a2: 6e3b ldr r3, [r7, #96] @ 0x60 - 80072a4: e853 3f00 ldrex r3, [r3] - 80072a8: 65fb str r3, [r7, #92] @ 0x5c + 80072ea: 6e3b ldr r3, [r7, #96] @ 0x60 + 80072ec: e853 3f00 ldrex r3, [r3] + 80072f0: 65fb str r3, [r7, #92] @ 0x5c return(result); - 80072aa: 6dfb ldr r3, [r7, #92] @ 0x5c - 80072ac: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 80072b0: f023 0301 bic.w r3, r3, #1 - 80072b4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 - 80072b8: 687b ldr r3, [r7, #4] - 80072ba: 681b ldr r3, [r3, #0] - 80072bc: 3308 adds r3, #8 - 80072be: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 - 80072c2: 66fa str r2, [r7, #108] @ 0x6c - 80072c4: 66bb str r3, [r7, #104] @ 0x68 + 80072f2: 6dfb ldr r3, [r7, #92] @ 0x5c + 80072f4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 80072f8: f023 0301 bic.w r3, r3, #1 + 80072fc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 + 8007300: 687b ldr r3, [r7, #4] + 8007302: 681b ldr r3, [r3, #0] + 8007304: 3308 adds r3, #8 + 8007306: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 + 800730a: 66fa str r2, [r7, #108] @ 0x6c + 800730c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 80072c6: 6eb9 ldr r1, [r7, #104] @ 0x68 - 80072c8: 6efa ldr r2, [r7, #108] @ 0x6c - 80072ca: e841 2300 strex r3, r2, [r1] - 80072ce: 667b str r3, [r7, #100] @ 0x64 + 800730e: 6eb9 ldr r1, [r7, #104] @ 0x68 + 8007310: 6efa ldr r2, [r7, #108] @ 0x6c + 8007312: e841 2300 strex r3, r2, [r1] + 8007316: 667b str r3, [r7, #100] @ 0x64 return(result); - 80072d0: 6e7b ldr r3, [r7, #100] @ 0x64 - 80072d2: 2b00 cmp r3, #0 - 80072d4: d1e1 bne.n 800729a + 8007318: 6e7b ldr r3, [r7, #100] @ 0x64 + 800731a: 2b00 cmp r3, #0 + 800731c: d1e1 bne.n 80072e2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 80072d6: 687b ldr r3, [r7, #4] - 80072d8: 2220 movs r2, #32 - 80072da: f8c3 208c str.w r2, [r3, #140] @ 0x8c + 800731e: 687b ldr r3, [r7, #4] + 8007320: 2220 movs r2, #32 + 8007322: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; - 80072de: 687b ldr r3, [r7, #4] - 80072e0: 2200 movs r2, #0 - 80072e2: 675a str r2, [r3, #116] @ 0x74 + 8007326: 687b ldr r3, [r7, #4] + 8007328: 2200 movs r2, #0 + 800732a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; - 80072e4: 687b ldr r3, [r7, #4] - 80072e6: 2200 movs r2, #0 - 80072e8: 671a str r2, [r3, #112] @ 0x70 + 800732c: 687b ldr r3, [r7, #4] + 800732e: 2200 movs r2, #0 + 8007330: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) - 80072ea: 687b ldr r3, [r7, #4] - 80072ec: 681b ldr r3, [r3, #0] - 80072ee: 4a60 ldr r2, [pc, #384] @ (8007470 ) - 80072f0: 4293 cmp r3, r2 - 80072f2: d021 beq.n 8007338 + 8007332: 687b ldr r3, [r7, #4] + 8007334: 681b ldr r3, [r3, #0] + 8007336: 4a60 ldr r2, [pc, #384] @ (80074b8 ) + 8007338: 4293 cmp r3, r2 + 800733a: d021 beq.n 8007380 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - 80072f4: 687b ldr r3, [r7, #4] - 80072f6: 681b ldr r3, [r3, #0] - 80072f8: 685b ldr r3, [r3, #4] - 80072fa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 - 80072fe: 2b00 cmp r3, #0 - 8007300: d01a beq.n 8007338 + 800733c: 687b ldr r3, [r7, #4] + 800733e: 681b ldr r3, [r3, #0] + 8007340: 685b ldr r3, [r3, #4] + 8007342: f403 0300 and.w r3, r3, #8388608 @ 0x800000 + 8007346: 2b00 cmp r3, #0 + 8007348: d01a beq.n 8007380 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - 8007302: 687b ldr r3, [r7, #4] - 8007304: 681b ldr r3, [r3, #0] - 8007306: 64fb str r3, [r7, #76] @ 0x4c + 800734a: 687b ldr r3, [r7, #4] + 800734c: 681b ldr r3, [r3, #0] + 800734e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8007308: 6cfb ldr r3, [r7, #76] @ 0x4c - 800730a: e853 3f00 ldrex r3, [r3] - 800730e: 64bb str r3, [r7, #72] @ 0x48 + 8007350: 6cfb ldr r3, [r7, #76] @ 0x4c + 8007352: e853 3f00 ldrex r3, [r3] + 8007356: 64bb str r3, [r7, #72] @ 0x48 return(result); - 8007310: 6cbb ldr r3, [r7, #72] @ 0x48 - 8007312: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 - 8007316: f8c7 3094 str.w r3, [r7, #148] @ 0x94 - 800731a: 687b ldr r3, [r7, #4] - 800731c: 681b ldr r3, [r3, #0] - 800731e: 461a mov r2, r3 - 8007320: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 - 8007324: 65bb str r3, [r7, #88] @ 0x58 - 8007326: 657a str r2, [r7, #84] @ 0x54 + 8007358: 6cbb ldr r3, [r7, #72] @ 0x48 + 800735a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 + 800735e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 + 8007362: 687b ldr r3, [r7, #4] + 8007364: 681b ldr r3, [r3, #0] + 8007366: 461a mov r2, r3 + 8007368: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 + 800736c: 65bb str r3, [r7, #88] @ 0x58 + 800736e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8007328: 6d79 ldr r1, [r7, #84] @ 0x54 - 800732a: 6dba ldr r2, [r7, #88] @ 0x58 - 800732c: e841 2300 strex r3, r2, [r1] - 8007330: 653b str r3, [r7, #80] @ 0x50 + 8007370: 6d79 ldr r1, [r7, #84] @ 0x54 + 8007372: 6dba ldr r2, [r7, #88] @ 0x58 + 8007374: e841 2300 strex r3, r2, [r1] + 8007378: 653b str r3, [r7, #80] @ 0x50 return(result); - 8007332: 6d3b ldr r3, [r7, #80] @ 0x50 - 8007334: 2b00 cmp r3, #0 - 8007336: d1e4 bne.n 8007302 + 800737a: 6d3b ldr r3, [r7, #80] @ 0x50 + 800737c: 2b00 cmp r3, #0 + 800737e: d1e4 bne.n 800734a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - 8007338: 687b ldr r3, [r7, #4] - 800733a: 6edb ldr r3, [r3, #108] @ 0x6c - 800733c: 2b01 cmp r3, #1 - 800733e: d130 bne.n 80073a2 + 8007380: 687b ldr r3, [r7, #4] + 8007382: 6edb ldr r3, [r3, #108] @ 0x6c + 8007384: 2b01 cmp r3, #1 + 8007386: d130 bne.n 80073ea { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8007340: 687b ldr r3, [r7, #4] - 8007342: 2200 movs r2, #0 - 8007344: 66da str r2, [r3, #108] @ 0x6c + 8007388: 687b ldr r3, [r7, #4] + 800738a: 2200 movs r2, #0 + 800738c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - 8007346: 687b ldr r3, [r7, #4] - 8007348: 681b ldr r3, [r3, #0] - 800734a: 63bb str r3, [r7, #56] @ 0x38 + 800738e: 687b ldr r3, [r7, #4] + 8007390: 681b ldr r3, [r3, #0] + 8007392: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800734c: 6bbb ldr r3, [r7, #56] @ 0x38 - 800734e: e853 3f00 ldrex r3, [r3] - 8007352: 637b str r3, [r7, #52] @ 0x34 + 8007394: 6bbb ldr r3, [r7, #56] @ 0x38 + 8007396: e853 3f00 ldrex r3, [r3] + 800739a: 637b str r3, [r7, #52] @ 0x34 return(result); - 8007354: 6b7b ldr r3, [r7, #52] @ 0x34 - 8007356: f023 0310 bic.w r3, r3, #16 - 800735a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 - 800735e: 687b ldr r3, [r7, #4] - 8007360: 681b ldr r3, [r3, #0] - 8007362: 461a mov r2, r3 - 8007364: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 - 8007368: 647b str r3, [r7, #68] @ 0x44 - 800736a: 643a str r2, [r7, #64] @ 0x40 + 800739c: 6b7b ldr r3, [r7, #52] @ 0x34 + 800739e: f023 0310 bic.w r3, r3, #16 + 80073a2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 + 80073a6: 687b ldr r3, [r7, #4] + 80073a8: 681b ldr r3, [r3, #0] + 80073aa: 461a mov r2, r3 + 80073ac: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 + 80073b0: 647b str r3, [r7, #68] @ 0x44 + 80073b2: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 800736c: 6c39 ldr r1, [r7, #64] @ 0x40 - 800736e: 6c7a ldr r2, [r7, #68] @ 0x44 - 8007370: e841 2300 strex r3, r2, [r1] - 8007374: 63fb str r3, [r7, #60] @ 0x3c + 80073b4: 6c39 ldr r1, [r7, #64] @ 0x40 + 80073b6: 6c7a ldr r2, [r7, #68] @ 0x44 + 80073b8: e841 2300 strex r3, r2, [r1] + 80073bc: 63fb str r3, [r7, #60] @ 0x3c return(result); - 8007376: 6bfb ldr r3, [r7, #60] @ 0x3c - 8007378: 2b00 cmp r3, #0 - 800737a: d1e4 bne.n 8007346 + 80073be: 6bfb ldr r3, [r7, #60] @ 0x3c + 80073c0: 2b00 cmp r3, #0 + 80073c2: d1e4 bne.n 800738e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - 800737c: 687b ldr r3, [r7, #4] - 800737e: 681b ldr r3, [r3, #0] - 8007380: 69db ldr r3, [r3, #28] - 8007382: f003 0310 and.w r3, r3, #16 - 8007386: 2b10 cmp r3, #16 - 8007388: d103 bne.n 8007392 + 80073c4: 687b ldr r3, [r7, #4] + 80073c6: 681b ldr r3, [r3, #0] + 80073c8: 69db ldr r3, [r3, #28] + 80073ca: f003 0310 and.w r3, r3, #16 + 80073ce: 2b10 cmp r3, #16 + 80073d0: d103 bne.n 80073da { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - 800738a: 687b ldr r3, [r7, #4] - 800738c: 681b ldr r3, [r3, #0] - 800738e: 2210 movs r2, #16 - 8007390: 621a str r2, [r3, #32] + 80073d2: 687b ldr r3, [r7, #4] + 80073d4: 681b ldr r3, [r3, #0] + 80073d6: 2210 movs r2, #16 + 80073d8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); - 8007392: 687b ldr r3, [r7, #4] - 8007394: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c - 8007398: 4619 mov r1, r3 - 800739a: 6878 ldr r0, [r7, #4] - 800739c: f7fe fcf4 bl 8005d88 + 80073da: 687b ldr r3, [r7, #4] + 80073dc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c + 80073e0: 4619 mov r1, r3 + 80073e2: 6878 ldr r0, [r7, #4] + 80073e4: f7fe fcf4 bl 8005dd0 #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } break; - 80073a0: e00e b.n 80073c0 + 80073e8: e00e b.n 8007408 HAL_UART_RxCpltCallback(huart); - 80073a2: 6878 ldr r0, [r7, #4] - 80073a4: f7fa f874 bl 8001490 + 80073ea: 6878 ldr r0, [r7, #4] + 80073ec: f7fa f874 bl 80014d8 break; - 80073a8: e00a b.n 80073c0 + 80073f0: e00a b.n 8007408 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) - 80073aa: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 - 80073ae: 2b00 cmp r3, #0 - 80073b0: d006 beq.n 80073c0 - 80073b2: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 - 80073b6: f003 0320 and.w r3, r3, #32 - 80073ba: 2b00 cmp r3, #0 - 80073bc: f47f aeca bne.w 8007154 + 80073f2: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 + 80073f6: 2b00 cmp r3, #0 + 80073f8: d006 beq.n 8007408 + 80073fa: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 + 80073fe: f003 0320 and.w r3, r3, #32 + 8007402: 2b00 cmp r3, #0 + 8007404: f47f aeca bne.w 800719c /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; - 80073c0: 687b ldr r3, [r7, #4] - 80073c2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e - 80073c6: f8a7 308e strh.w r3, [r7, #142] @ 0x8e + 8007408: 687b ldr r3, [r7, #4] + 800740a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e + 800740e: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) - 80073ca: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e - 80073ce: 2b00 cmp r3, #0 - 80073d0: d049 beq.n 8007466 - 80073d2: 687b ldr r3, [r7, #4] - 80073d4: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 - 80073d8: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e - 80073dc: 429a cmp r2, r3 - 80073de: d242 bcs.n 8007466 + 8007412: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e + 8007416: 2b00 cmp r3, #0 + 8007418: d049 beq.n 80074ae + 800741a: 687b ldr r3, [r7, #4] + 800741c: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 + 8007420: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e + 8007424: 429a cmp r2, r3 + 8007426: d242 bcs.n 80074ae { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - 80073e0: 687b ldr r3, [r7, #4] - 80073e2: 681b ldr r3, [r3, #0] - 80073e4: 3308 adds r3, #8 - 80073e6: 627b str r3, [r7, #36] @ 0x24 + 8007428: 687b ldr r3, [r7, #4] + 800742a: 681b ldr r3, [r3, #0] + 800742c: 3308 adds r3, #8 + 800742e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 80073e8: 6a7b ldr r3, [r7, #36] @ 0x24 - 80073ea: e853 3f00 ldrex r3, [r3] - 80073ee: 623b str r3, [r7, #32] + 8007430: 6a7b ldr r3, [r7, #36] @ 0x24 + 8007432: e853 3f00 ldrex r3, [r3] + 8007436: 623b str r3, [r7, #32] return(result); - 80073f0: 6a3b ldr r3, [r7, #32] - 80073f2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 - 80073f6: f8c7 3088 str.w r3, [r7, #136] @ 0x88 - 80073fa: 687b ldr r3, [r7, #4] - 80073fc: 681b ldr r3, [r3, #0] - 80073fe: 3308 adds r3, #8 - 8007400: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 - 8007404: 633a str r2, [r7, #48] @ 0x30 - 8007406: 62fb str r3, [r7, #44] @ 0x2c + 8007438: 6a3b ldr r3, [r7, #32] + 800743a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 + 800743e: f8c7 3088 str.w r3, [r7, #136] @ 0x88 + 8007442: 687b ldr r3, [r7, #4] + 8007444: 681b ldr r3, [r3, #0] + 8007446: 3308 adds r3, #8 + 8007448: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 + 800744c: 633a str r2, [r7, #48] @ 0x30 + 800744e: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8007408: 6af9 ldr r1, [r7, #44] @ 0x2c - 800740a: 6b3a ldr r2, [r7, #48] @ 0x30 - 800740c: e841 2300 strex r3, r2, [r1] - 8007410: 62bb str r3, [r7, #40] @ 0x28 + 8007450: 6af9 ldr r1, [r7, #44] @ 0x2c + 8007452: 6b3a ldr r2, [r7, #48] @ 0x30 + 8007454: e841 2300 strex r3, r2, [r1] + 8007458: 62bb str r3, [r7, #40] @ 0x28 return(result); - 8007412: 6abb ldr r3, [r7, #40] @ 0x28 - 8007414: 2b00 cmp r3, #0 - 8007416: d1e3 bne.n 80073e0 + 800745a: 6abb ldr r3, [r7, #40] @ 0x28 + 800745c: 2b00 cmp r3, #0 + 800745e: d1e3 bne.n 8007428 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; - 8007418: 687b ldr r3, [r7, #4] - 800741a: 4a16 ldr r2, [pc, #88] @ (8007474 ) - 800741c: 675a str r2, [r3, #116] @ 0x74 + 8007460: 687b ldr r3, [r7, #4] + 8007462: 4a16 ldr r2, [pc, #88] @ (80074bc ) + 8007464: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - 800741e: 687b ldr r3, [r7, #4] - 8007420: 681b ldr r3, [r3, #0] - 8007422: 613b str r3, [r7, #16] + 8007466: 687b ldr r3, [r7, #4] + 8007468: 681b ldr r3, [r3, #0] + 800746a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8007424: 693b ldr r3, [r7, #16] - 8007426: e853 3f00 ldrex r3, [r3] - 800742a: 60fb str r3, [r7, #12] + 800746c: 693b ldr r3, [r7, #16] + 800746e: e853 3f00 ldrex r3, [r3] + 8007472: 60fb str r3, [r7, #12] return(result); - 800742c: 68fb ldr r3, [r7, #12] - 800742e: f043 0320 orr.w r3, r3, #32 - 8007432: f8c7 3084 str.w r3, [r7, #132] @ 0x84 - 8007436: 687b ldr r3, [r7, #4] - 8007438: 681b ldr r3, [r3, #0] - 800743a: 461a mov r2, r3 - 800743c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 - 8007440: 61fb str r3, [r7, #28] - 8007442: 61ba str r2, [r7, #24] + 8007474: 68fb ldr r3, [r7, #12] + 8007476: f043 0320 orr.w r3, r3, #32 + 800747a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 + 800747e: 687b ldr r3, [r7, #4] + 8007480: 681b ldr r3, [r3, #0] + 8007482: 461a mov r2, r3 + 8007484: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 + 8007488: 61fb str r3, [r7, #28] + 800748a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8007444: 69b9 ldr r1, [r7, #24] - 8007446: 69fa ldr r2, [r7, #28] - 8007448: e841 2300 strex r3, r2, [r1] - 800744c: 617b str r3, [r7, #20] + 800748c: 69b9 ldr r1, [r7, #24] + 800748e: 69fa ldr r2, [r7, #28] + 8007490: e841 2300 strex r3, r2, [r1] + 8007494: 617b str r3, [r7, #20] return(result); - 800744e: 697b ldr r3, [r7, #20] - 8007450: 2b00 cmp r3, #0 - 8007452: d1e4 bne.n 800741e + 8007496: 697b ldr r3, [r7, #20] + 8007498: 2b00 cmp r3, #0 + 800749a: d1e4 bne.n 8007466 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } - 8007454: e007 b.n 8007466 + 800749c: e007 b.n 80074ae __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - 8007456: 687b ldr r3, [r7, #4] - 8007458: 681b ldr r3, [r3, #0] - 800745a: 699a ldr r2, [r3, #24] - 800745c: 687b ldr r3, [r7, #4] - 800745e: 681b ldr r3, [r3, #0] - 8007460: f042 0208 orr.w r2, r2, #8 - 8007464: 619a str r2, [r3, #24] + 800749e: 687b ldr r3, [r7, #4] + 80074a0: 681b ldr r3, [r3, #0] + 80074a2: 699a ldr r2, [r3, #24] + 80074a4: 687b ldr r3, [r7, #4] + 80074a6: 681b ldr r3, [r3, #0] + 80074a8: f042 0208 orr.w r2, r2, #8 + 80074ac: 619a str r2, [r3, #24] } - 8007466: bf00 nop - 8007468: 37b8 adds r7, #184 @ 0xb8 - 800746a: 46bd mov sp, r7 - 800746c: bd80 pop {r7, pc} - 800746e: bf00 nop - 8007470: 40008000 .word 0x40008000 - 8007474: 08006bf1 .word 0x08006bf1 + 80074ae: bf00 nop + 80074b0: 37b8 adds r7, #184 @ 0xb8 + 80074b2: 46bd mov sp, r7 + 80074b4: bd80 pop {r7, pc} + 80074b6: bf00 nop + 80074b8: 40008000 .word 0x40008000 + 80074bc: 08006c39 .word 0x08006c39 -08007478 : +080074c0 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { - 8007478: b480 push {r7} - 800747a: b083 sub sp, #12 - 800747c: af00 add r7, sp, #0 - 800747e: 6078 str r0, [r7, #4] + 80074c0: b480 push {r7} + 80074c2: b083 sub sp, #12 + 80074c4: af00 add r7, sp, #0 + 80074c6: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } - 8007480: bf00 nop - 8007482: 370c adds r7, #12 - 8007484: 46bd mov sp, r7 - 8007486: f85d 7b04 ldr.w r7, [sp], #4 - 800748a: 4770 bx lr + 80074c8: bf00 nop + 80074ca: 370c adds r7, #12 + 80074cc: 46bd mov sp, r7 + 80074ce: f85d 7b04 ldr.w r7, [sp], #4 + 80074d2: 4770 bx lr -0800748c : +080074d4 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { - 800748c: b480 push {r7} - 800748e: b083 sub sp, #12 - 8007490: af00 add r7, sp, #0 - 8007492: 6078 str r0, [r7, #4] + 80074d4: b480 push {r7} + 80074d6: b083 sub sp, #12 + 80074d8: af00 add r7, sp, #0 + 80074da: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } - 8007494: bf00 nop - 8007496: 370c adds r7, #12 - 8007498: 46bd mov sp, r7 - 800749a: f85d 7b04 ldr.w r7, [sp], #4 - 800749e: 4770 bx lr + 80074dc: bf00 nop + 80074de: 370c adds r7, #12 + 80074e0: 46bd mov sp, r7 + 80074e2: f85d 7b04 ldr.w r7, [sp], #4 + 80074e6: 4770 bx lr -080074a0 : +080074e8 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { - 80074a0: b480 push {r7} - 80074a2: b083 sub sp, #12 - 80074a4: af00 add r7, sp, #0 - 80074a6: 6078 str r0, [r7, #4] + 80074e8: b480 push {r7} + 80074ea: b083 sub sp, #12 + 80074ec: af00 add r7, sp, #0 + 80074ee: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } - 80074a8: bf00 nop - 80074aa: 370c adds r7, #12 - 80074ac: 46bd mov sp, r7 - 80074ae: f85d 7b04 ldr.w r7, [sp], #4 - 80074b2: 4770 bx lr + 80074f0: bf00 nop + 80074f2: 370c adds r7, #12 + 80074f4: 46bd mov sp, r7 + 80074f6: f85d 7b04 ldr.w r7, [sp], #4 + 80074fa: 4770 bx lr -080074b4 : +080074fc : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { - 80074b4: b480 push {r7} - 80074b6: b085 sub sp, #20 - 80074b8: af00 add r7, sp, #0 - 80074ba: 6078 str r0, [r7, #4] + 80074fc: b480 push {r7} + 80074fe: b085 sub sp, #20 + 8007500: af00 add r7, sp, #0 + 8007502: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); - 80074bc: 687b ldr r3, [r7, #4] - 80074be: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 - 80074c2: 2b01 cmp r3, #1 - 80074c4: d101 bne.n 80074ca - 80074c6: 2302 movs r3, #2 - 80074c8: e027 b.n 800751a - 80074ca: 687b ldr r3, [r7, #4] - 80074cc: 2201 movs r2, #1 - 80074ce: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 8007504: 687b ldr r3, [r7, #4] + 8007506: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 800750a: 2b01 cmp r3, #1 + 800750c: d101 bne.n 8007512 + 800750e: 2302 movs r3, #2 + 8007510: e027 b.n 8007562 + 8007512: 687b ldr r3, [r7, #4] + 8007514: 2201 movs r2, #1 + 8007516: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; - 80074d2: 687b ldr r3, [r7, #4] - 80074d4: 2224 movs r2, #36 @ 0x24 - 80074d6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800751a: 687b ldr r3, [r7, #4] + 800751c: 2224 movs r2, #36 @ 0x24 + 800751e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 80074da: 687b ldr r3, [r7, #4] - 80074dc: 681b ldr r3, [r3, #0] - 80074de: 681b ldr r3, [r3, #0] - 80074e0: 60fb str r3, [r7, #12] + 8007522: 687b ldr r3, [r7, #4] + 8007524: 681b ldr r3, [r3, #0] + 8007526: 681b ldr r3, [r3, #0] + 8007528: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 80074e2: 687b ldr r3, [r7, #4] - 80074e4: 681b ldr r3, [r3, #0] - 80074e6: 681a ldr r2, [r3, #0] - 80074e8: 687b ldr r3, [r7, #4] - 80074ea: 681b ldr r3, [r3, #0] - 80074ec: f022 0201 bic.w r2, r2, #1 - 80074f0: 601a str r2, [r3, #0] + 800752a: 687b ldr r3, [r7, #4] + 800752c: 681b ldr r3, [r3, #0] + 800752e: 681a ldr r2, [r3, #0] + 8007530: 687b ldr r3, [r7, #4] + 8007532: 681b ldr r3, [r3, #0] + 8007534: f022 0201 bic.w r2, r2, #1 + 8007538: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - 80074f2: 68fb ldr r3, [r7, #12] - 80074f4: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 - 80074f8: 60fb str r3, [r7, #12] + 800753a: 68fb ldr r3, [r7, #12] + 800753c: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 + 8007540: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; - 80074fa: 687b ldr r3, [r7, #4] - 80074fc: 2200 movs r2, #0 - 80074fe: 665a str r2, [r3, #100] @ 0x64 + 8007542: 687b ldr r3, [r7, #4] + 8007544: 2200 movs r2, #0 + 8007546: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8007500: 687b ldr r3, [r7, #4] - 8007502: 681b ldr r3, [r3, #0] - 8007504: 68fa ldr r2, [r7, #12] - 8007506: 601a str r2, [r3, #0] + 8007548: 687b ldr r3, [r7, #4] + 800754a: 681b ldr r3, [r3, #0] + 800754c: 68fa ldr r2, [r7, #12] + 800754e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8007508: 687b ldr r3, [r7, #4] - 800750a: 2220 movs r2, #32 - 800750c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 8007550: 687b ldr r3, [r7, #4] + 8007552: 2220 movs r2, #32 + 8007554: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8007510: 687b ldr r3, [r7, #4] - 8007512: 2200 movs r2, #0 - 8007514: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 8007558: 687b ldr r3, [r7, #4] + 800755a: 2200 movs r2, #0 + 800755c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; - 8007518: 2300 movs r3, #0 + 8007560: 2300 movs r3, #0 } - 800751a: 4618 mov r0, r3 - 800751c: 3714 adds r7, #20 - 800751e: 46bd mov sp, r7 - 8007520: f85d 7b04 ldr.w r7, [sp], #4 - 8007524: 4770 bx lr + 8007562: 4618 mov r0, r3 + 8007564: 3714 adds r7, #20 + 8007566: 46bd mov sp, r7 + 8007568: f85d 7b04 ldr.w r7, [sp], #4 + 800756c: 4770 bx lr -08007526 : +0800756e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 8007526: b580 push {r7, lr} - 8007528: b084 sub sp, #16 - 800752a: af00 add r7, sp, #0 - 800752c: 6078 str r0, [r7, #4] - 800752e: 6039 str r1, [r7, #0] + 800756e: b580 push {r7, lr} + 8007570: b084 sub sp, #16 + 8007572: af00 add r7, sp, #0 + 8007574: 6078 str r0, [r7, #4] + 8007576: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 8007530: 687b ldr r3, [r7, #4] - 8007532: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 - 8007536: 2b01 cmp r3, #1 - 8007538: d101 bne.n 800753e - 800753a: 2302 movs r3, #2 - 800753c: e02d b.n 800759a - 800753e: 687b ldr r3, [r7, #4] - 8007540: 2201 movs r2, #1 - 8007542: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 8007578: 687b ldr r3, [r7, #4] + 800757a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 800757e: 2b01 cmp r3, #1 + 8007580: d101 bne.n 8007586 + 8007582: 2302 movs r3, #2 + 8007584: e02d b.n 80075e2 + 8007586: 687b ldr r3, [r7, #4] + 8007588: 2201 movs r2, #1 + 800758a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; - 8007546: 687b ldr r3, [r7, #4] - 8007548: 2224 movs r2, #36 @ 0x24 - 800754a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800758e: 687b ldr r3, [r7, #4] + 8007590: 2224 movs r2, #36 @ 0x24 + 8007592: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 800754e: 687b ldr r3, [r7, #4] - 8007550: 681b ldr r3, [r3, #0] - 8007552: 681b ldr r3, [r3, #0] - 8007554: 60fb str r3, [r7, #12] + 8007596: 687b ldr r3, [r7, #4] + 8007598: 681b ldr r3, [r3, #0] + 800759a: 681b ldr r3, [r3, #0] + 800759c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 8007556: 687b ldr r3, [r7, #4] - 8007558: 681b ldr r3, [r3, #0] - 800755a: 681a ldr r2, [r3, #0] - 800755c: 687b ldr r3, [r7, #4] - 800755e: 681b ldr r3, [r3, #0] - 8007560: f022 0201 bic.w r2, r2, #1 - 8007564: 601a str r2, [r3, #0] + 800759e: 687b ldr r3, [r7, #4] + 80075a0: 681b ldr r3, [r3, #0] + 80075a2: 681a ldr r2, [r3, #0] + 80075a4: 687b ldr r3, [r7, #4] + 80075a6: 681b ldr r3, [r3, #0] + 80075a8: f022 0201 bic.w r2, r2, #1 + 80075ac: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - 8007566: 687b ldr r3, [r7, #4] - 8007568: 681b ldr r3, [r3, #0] - 800756a: 689b ldr r3, [r3, #8] - 800756c: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 - 8007570: 687b ldr r3, [r7, #4] - 8007572: 681b ldr r3, [r3, #0] - 8007574: 683a ldr r2, [r7, #0] - 8007576: 430a orrs r2, r1 - 8007578: 609a str r2, [r3, #8] + 80075ae: 687b ldr r3, [r7, #4] + 80075b0: 681b ldr r3, [r3, #0] + 80075b2: 689b ldr r3, [r3, #8] + 80075b4: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 + 80075b8: 687b ldr r3, [r7, #4] + 80075ba: 681b ldr r3, [r3, #0] + 80075bc: 683a ldr r2, [r7, #0] + 80075be: 430a orrs r2, r1 + 80075c0: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 800757a: 6878 ldr r0, [r7, #4] - 800757c: f000 f850 bl 8007620 + 80075c2: 6878 ldr r0, [r7, #4] + 80075c4: f000 f850 bl 8007668 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 8007580: 687b ldr r3, [r7, #4] - 8007582: 681b ldr r3, [r3, #0] - 8007584: 68fa ldr r2, [r7, #12] - 8007586: 601a str r2, [r3, #0] + 80075c8: 687b ldr r3, [r7, #4] + 80075ca: 681b ldr r3, [r3, #0] + 80075cc: 68fa ldr r2, [r7, #12] + 80075ce: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8007588: 687b ldr r3, [r7, #4] - 800758a: 2220 movs r2, #32 - 800758c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 80075d0: 687b ldr r3, [r7, #4] + 80075d2: 2220 movs r2, #32 + 80075d4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8007590: 687b ldr r3, [r7, #4] - 8007592: 2200 movs r2, #0 - 8007594: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 80075d8: 687b ldr r3, [r7, #4] + 80075da: 2200 movs r2, #0 + 80075dc: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; - 8007598: 2300 movs r3, #0 + 80075e0: 2300 movs r3, #0 } - 800759a: 4618 mov r0, r3 - 800759c: 3710 adds r7, #16 - 800759e: 46bd mov sp, r7 - 80075a0: bd80 pop {r7, pc} + 80075e2: 4618 mov r0, r3 + 80075e4: 3710 adds r7, #16 + 80075e6: 46bd mov sp, r7 + 80075e8: bd80 pop {r7, pc} -080075a2 : +080075ea : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { - 80075a2: b580 push {r7, lr} - 80075a4: b084 sub sp, #16 - 80075a6: af00 add r7, sp, #0 - 80075a8: 6078 str r0, [r7, #4] - 80075aa: 6039 str r1, [r7, #0] + 80075ea: b580 push {r7, lr} + 80075ec: b084 sub sp, #16 + 80075ee: af00 add r7, sp, #0 + 80075f0: 6078 str r0, [r7, #4] + 80075f2: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); - 80075ac: 687b ldr r3, [r7, #4] - 80075ae: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 - 80075b2: 2b01 cmp r3, #1 - 80075b4: d101 bne.n 80075ba - 80075b6: 2302 movs r3, #2 - 80075b8: e02d b.n 8007616 - 80075ba: 687b ldr r3, [r7, #4] - 80075bc: 2201 movs r2, #1 - 80075be: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 80075f4: 687b ldr r3, [r7, #4] + 80075f6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 + 80075fa: 2b01 cmp r3, #1 + 80075fc: d101 bne.n 8007602 + 80075fe: 2302 movs r3, #2 + 8007600: e02d b.n 800765e + 8007602: 687b ldr r3, [r7, #4] + 8007604: 2201 movs r2, #1 + 8007606: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; - 80075c2: 687b ldr r3, [r7, #4] - 80075c4: 2224 movs r2, #36 @ 0x24 - 80075c6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800760a: 687b ldr r3, [r7, #4] + 800760c: 2224 movs r2, #36 @ 0x24 + 800760e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); - 80075ca: 687b ldr r3, [r7, #4] - 80075cc: 681b ldr r3, [r3, #0] - 80075ce: 681b ldr r3, [r3, #0] - 80075d0: 60fb str r3, [r7, #12] + 8007612: 687b ldr r3, [r7, #4] + 8007614: 681b ldr r3, [r3, #0] + 8007616: 681b ldr r3, [r3, #0] + 8007618: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); - 80075d2: 687b ldr r3, [r7, #4] - 80075d4: 681b ldr r3, [r3, #0] - 80075d6: 681a ldr r2, [r3, #0] - 80075d8: 687b ldr r3, [r7, #4] - 80075da: 681b ldr r3, [r3, #0] - 80075dc: f022 0201 bic.w r2, r2, #1 - 80075e0: 601a str r2, [r3, #0] + 800761a: 687b ldr r3, [r7, #4] + 800761c: 681b ldr r3, [r3, #0] + 800761e: 681a ldr r2, [r3, #0] + 8007620: 687b ldr r3, [r7, #4] + 8007622: 681b ldr r3, [r3, #0] + 8007624: f022 0201 bic.w r2, r2, #1 + 8007628: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - 80075e2: 687b ldr r3, [r7, #4] - 80075e4: 681b ldr r3, [r3, #0] - 80075e6: 689b ldr r3, [r3, #8] - 80075e8: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 - 80075ec: 687b ldr r3, [r7, #4] - 80075ee: 681b ldr r3, [r3, #0] - 80075f0: 683a ldr r2, [r7, #0] - 80075f2: 430a orrs r2, r1 - 80075f4: 609a str r2, [r3, #8] + 800762a: 687b ldr r3, [r7, #4] + 800762c: 681b ldr r3, [r3, #0] + 800762e: 689b ldr r3, [r3, #8] + 8007630: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 + 8007634: 687b ldr r3, [r7, #4] + 8007636: 681b ldr r3, [r3, #0] + 8007638: 683a ldr r2, [r7, #0] + 800763a: 430a orrs r2, r1 + 800763c: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); - 80075f6: 6878 ldr r0, [r7, #4] - 80075f8: f000 f812 bl 8007620 + 800763e: 6878 ldr r0, [r7, #4] + 8007640: f000 f812 bl 8007668 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); - 80075fc: 687b ldr r3, [r7, #4] - 80075fe: 681b ldr r3, [r3, #0] - 8007600: 68fa ldr r2, [r7, #12] - 8007602: 601a str r2, [r3, #0] + 8007644: 687b ldr r3, [r7, #4] + 8007646: 681b ldr r3, [r3, #0] + 8007648: 68fa ldr r2, [r7, #12] + 800764a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; - 8007604: 687b ldr r3, [r7, #4] - 8007606: 2220 movs r2, #32 - 8007608: f8c3 2088 str.w r2, [r3, #136] @ 0x88 + 800764c: 687b ldr r3, [r7, #4] + 800764e: 2220 movs r2, #32 + 8007650: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); - 800760c: 687b ldr r3, [r7, #4] - 800760e: 2200 movs r2, #0 - 8007610: f883 2084 strb.w r2, [r3, #132] @ 0x84 + 8007654: 687b ldr r3, [r7, #4] + 8007656: 2200 movs r2, #0 + 8007658: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; - 8007614: 2300 movs r3, #0 + 800765c: 2300 movs r3, #0 } - 8007616: 4618 mov r0, r3 - 8007618: 3710 adds r7, #16 - 800761a: 46bd mov sp, r7 - 800761c: bd80 pop {r7, pc} + 800765e: 4618 mov r0, r3 + 8007660: 3710 adds r7, #16 + 8007662: 46bd mov sp, r7 + 8007664: bd80 pop {r7, pc} ... -08007620 : +08007668 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { - 8007620: b480 push {r7} - 8007622: b085 sub sp, #20 - 8007624: af00 add r7, sp, #0 - 8007626: 6078 str r0, [r7, #4] + 8007668: b480 push {r7} + 800766a: b085 sub sp, #20 + 800766c: af00 add r7, sp, #0 + 800766e: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) - 8007628: 687b ldr r3, [r7, #4] - 800762a: 6e5b ldr r3, [r3, #100] @ 0x64 - 800762c: 2b00 cmp r3, #0 - 800762e: d108 bne.n 8007642 + 8007670: 687b ldr r3, [r7, #4] + 8007672: 6e5b ldr r3, [r3, #100] @ 0x64 + 8007674: 2b00 cmp r3, #0 + 8007676: d108 bne.n 800768a { huart->NbTxDataToProcess = 1U; - 8007630: 687b ldr r3, [r7, #4] - 8007632: 2201 movs r2, #1 - 8007634: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + 8007678: 687b ldr r3, [r7, #4] + 800767a: 2201 movs r2, #1 + 800767c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; - 8007638: 687b ldr r3, [r7, #4] - 800763a: 2201 movs r2, #1 - 800763c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + 8007680: 687b ldr r3, [r7, #4] + 8007682: 2201 movs r2, #1 + 8007684: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } - 8007640: e031 b.n 80076a6 + 8007688: e031 b.n 80076ee rx_fifo_depth = RX_FIFO_DEPTH; - 8007642: 2308 movs r3, #8 - 8007644: 73fb strb r3, [r7, #15] + 800768a: 2308 movs r3, #8 + 800768c: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; - 8007646: 2308 movs r3, #8 - 8007648: 73bb strb r3, [r7, #14] + 800768e: 2308 movs r3, #8 + 8007690: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - 800764a: 687b ldr r3, [r7, #4] - 800764c: 681b ldr r3, [r3, #0] - 800764e: 689b ldr r3, [r3, #8] - 8007650: 0e5b lsrs r3, r3, #25 - 8007652: b2db uxtb r3, r3 - 8007654: f003 0307 and.w r3, r3, #7 - 8007658: 737b strb r3, [r7, #13] + 8007692: 687b ldr r3, [r7, #4] + 8007694: 681b ldr r3, [r3, #0] + 8007696: 689b ldr r3, [r3, #8] + 8007698: 0e5b lsrs r3, r3, #25 + 800769a: b2db uxtb r3, r3 + 800769c: f003 0307 and.w r3, r3, #7 + 80076a0: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - 800765a: 687b ldr r3, [r7, #4] - 800765c: 681b ldr r3, [r3, #0] - 800765e: 689b ldr r3, [r3, #8] - 8007660: 0f5b lsrs r3, r3, #29 - 8007662: b2db uxtb r3, r3 - 8007664: f003 0307 and.w r3, r3, #7 - 8007668: 733b strb r3, [r7, #12] + 80076a2: 687b ldr r3, [r7, #4] + 80076a4: 681b ldr r3, [r3, #0] + 80076a6: 689b ldr r3, [r3, #8] + 80076a8: 0f5b lsrs r3, r3, #29 + 80076aa: b2db uxtb r3, r3 + 80076ac: f003 0307 and.w r3, r3, #7 + 80076b0: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 800766a: 7bbb ldrb r3, [r7, #14] - 800766c: 7b3a ldrb r2, [r7, #12] - 800766e: 4911 ldr r1, [pc, #68] @ (80076b4 ) - 8007670: 5c8a ldrb r2, [r1, r2] - 8007672: fb02 f303 mul.w r3, r2, r3 + 80076b2: 7bbb ldrb r3, [r7, #14] + 80076b4: 7b3a ldrb r2, [r7, #12] + 80076b6: 4911 ldr r1, [pc, #68] @ (80076fc ) + 80076b8: 5c8a ldrb r2, [r1, r2] + 80076ba: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; - 8007676: 7b3a ldrb r2, [r7, #12] - 8007678: 490f ldr r1, [pc, #60] @ (80076b8 ) - 800767a: 5c8a ldrb r2, [r1, r2] + 80076be: 7b3a ldrb r2, [r7, #12] + 80076c0: 490f ldr r1, [pc, #60] @ (8007700 ) + 80076c2: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - 800767c: fb93 f3f2 sdiv r3, r3, r2 - 8007680: b29a uxth r2, r3 - 8007682: 687b ldr r3, [r7, #4] - 8007684: f8a3 206a strh.w r2, [r3, #106] @ 0x6a + 80076c4: fb93 f3f2 sdiv r3, r3, r2 + 80076c8: b29a uxth r2, r3 + 80076ca: 687b ldr r3, [r7, #4] + 80076cc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 8007688: 7bfb ldrb r3, [r7, #15] - 800768a: 7b7a ldrb r2, [r7, #13] - 800768c: 4909 ldr r1, [pc, #36] @ (80076b4 ) - 800768e: 5c8a ldrb r2, [r1, r2] - 8007690: fb02 f303 mul.w r3, r2, r3 + 80076d0: 7bfb ldrb r3, [r7, #15] + 80076d2: 7b7a ldrb r2, [r7, #13] + 80076d4: 4909 ldr r1, [pc, #36] @ (80076fc ) + 80076d6: 5c8a ldrb r2, [r1, r2] + 80076d8: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; - 8007694: 7b7a ldrb r2, [r7, #13] - 8007696: 4908 ldr r1, [pc, #32] @ (80076b8 ) - 8007698: 5c8a ldrb r2, [r1, r2] + 80076dc: 7b7a ldrb r2, [r7, #13] + 80076de: 4908 ldr r1, [pc, #32] @ (8007700 ) + 80076e0: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - 800769a: fb93 f3f2 sdiv r3, r3, r2 - 800769e: b29a uxth r2, r3 - 80076a0: 687b ldr r3, [r7, #4] - 80076a2: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 + 80076e2: fb93 f3f2 sdiv r3, r3, r2 + 80076e6: b29a uxth r2, r3 + 80076e8: 687b ldr r3, [r7, #4] + 80076ea: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } - 80076a6: bf00 nop - 80076a8: 3714 adds r7, #20 - 80076aa: 46bd mov sp, r7 - 80076ac: f85d 7b04 ldr.w r7, [sp], #4 - 80076b0: 4770 bx lr - 80076b2: bf00 nop - 80076b4: 0800775c .word 0x0800775c - 80076b8: 08007764 .word 0x08007764 + 80076ee: bf00 nop + 80076f0: 3714 adds r7, #20 + 80076f2: 46bd mov sp, r7 + 80076f4: f85d 7b04 ldr.w r7, [sp], #4 + 80076f8: 4770 bx lr + 80076fa: bf00 nop + 80076fc: 080077a4 .word 0x080077a4 + 8007700: 080077ac .word 0x080077ac -080076bc : - 80076bc: 4402 add r2, r0 - 80076be: 4603 mov r3, r0 - 80076c0: 4293 cmp r3, r2 - 80076c2: d100 bne.n 80076c6 - 80076c4: 4770 bx lr - 80076c6: f803 1b01 strb.w r1, [r3], #1 - 80076ca: e7f9 b.n 80076c0 +08007704 : + 8007704: 4402 add r2, r0 + 8007706: 4603 mov r3, r0 + 8007708: 4293 cmp r3, r2 + 800770a: d100 bne.n 800770e + 800770c: 4770 bx lr + 800770e: f803 1b01 strb.w r1, [r3], #1 + 8007712: e7f9 b.n 8007708 -080076cc <__libc_init_array>: - 80076cc: b570 push {r4, r5, r6, lr} - 80076ce: 4d0d ldr r5, [pc, #52] @ (8007704 <__libc_init_array+0x38>) - 80076d0: 4c0d ldr r4, [pc, #52] @ (8007708 <__libc_init_array+0x3c>) - 80076d2: 1b64 subs r4, r4, r5 - 80076d4: 10a4 asrs r4, r4, #2 - 80076d6: 2600 movs r6, #0 - 80076d8: 42a6 cmp r6, r4 - 80076da: d109 bne.n 80076f0 <__libc_init_array+0x24> - 80076dc: 4d0b ldr r5, [pc, #44] @ (800770c <__libc_init_array+0x40>) - 80076de: 4c0c ldr r4, [pc, #48] @ (8007710 <__libc_init_array+0x44>) - 80076e0: f000 f818 bl 8007714 <_init> - 80076e4: 1b64 subs r4, r4, r5 - 80076e6: 10a4 asrs r4, r4, #2 - 80076e8: 2600 movs r6, #0 - 80076ea: 42a6 cmp r6, r4 - 80076ec: d105 bne.n 80076fa <__libc_init_array+0x2e> - 80076ee: bd70 pop {r4, r5, r6, pc} - 80076f0: f855 3b04 ldr.w r3, [r5], #4 - 80076f4: 4798 blx r3 - 80076f6: 3601 adds r6, #1 - 80076f8: e7ee b.n 80076d8 <__libc_init_array+0xc> - 80076fa: f855 3b04 ldr.w r3, [r5], #4 - 80076fe: 4798 blx r3 - 8007700: 3601 adds r6, #1 - 8007702: e7f2 b.n 80076ea <__libc_init_array+0x1e> - 8007704: 08007774 .word 0x08007774 - 8007708: 08007774 .word 0x08007774 - 800770c: 08007774 .word 0x08007774 - 8007710: 08007778 .word 0x08007778 +08007714 <__libc_init_array>: + 8007714: b570 push {r4, r5, r6, lr} + 8007716: 4d0d ldr r5, [pc, #52] @ (800774c <__libc_init_array+0x38>) + 8007718: 4c0d ldr r4, [pc, #52] @ (8007750 <__libc_init_array+0x3c>) + 800771a: 1b64 subs r4, r4, r5 + 800771c: 10a4 asrs r4, r4, #2 + 800771e: 2600 movs r6, #0 + 8007720: 42a6 cmp r6, r4 + 8007722: d109 bne.n 8007738 <__libc_init_array+0x24> + 8007724: 4d0b ldr r5, [pc, #44] @ (8007754 <__libc_init_array+0x40>) + 8007726: 4c0c ldr r4, [pc, #48] @ (8007758 <__libc_init_array+0x44>) + 8007728: f000 f818 bl 800775c <_init> + 800772c: 1b64 subs r4, r4, r5 + 800772e: 10a4 asrs r4, r4, #2 + 8007730: 2600 movs r6, #0 + 8007732: 42a6 cmp r6, r4 + 8007734: d105 bne.n 8007742 <__libc_init_array+0x2e> + 8007736: bd70 pop {r4, r5, r6, pc} + 8007738: f855 3b04 ldr.w r3, [r5], #4 + 800773c: 4798 blx r3 + 800773e: 3601 adds r6, #1 + 8007740: e7ee b.n 8007720 <__libc_init_array+0xc> + 8007742: f855 3b04 ldr.w r3, [r5], #4 + 8007746: 4798 blx r3 + 8007748: 3601 adds r6, #1 + 800774a: e7f2 b.n 8007732 <__libc_init_array+0x1e> + 800774c: 080077bc .word 0x080077bc + 8007750: 080077bc .word 0x080077bc + 8007754: 080077bc .word 0x080077bc + 8007758: 080077c0 .word 0x080077c0 -08007714 <_init>: - 8007714: b5f8 push {r3, r4, r5, r6, r7, lr} - 8007716: bf00 nop - 8007718: bcf8 pop {r3, r4, r5, r6, r7} - 800771a: bc08 pop {r3} - 800771c: 469e mov lr, r3 - 800771e: 4770 bx lr +0800775c <_init>: + 800775c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800775e: bf00 nop + 8007760: bcf8 pop {r3, r4, r5, r6, r7} + 8007762: bc08 pop {r3} + 8007764: 469e mov lr, r3 + 8007766: 4770 bx lr -08007720 <_fini>: - 8007720: b5f8 push {r3, r4, r5, r6, r7, lr} - 8007722: bf00 nop - 8007724: bcf8 pop {r3, r4, r5, r6, r7} - 8007726: bc08 pop {r3} - 8007728: 469e mov lr, r3 - 800772a: 4770 bx lr +08007768 <_fini>: + 8007768: b5f8 push {r3, r4, r5, r6, r7, lr} + 800776a: bf00 nop + 800776c: bcf8 pop {r3, r4, r5, r6, r7} + 800776e: bc08 pop {r3} + 8007770: 469e mov lr, r3 + 8007772: 4770 bx lr diff --git a/Debug/POWER_SWITCH.map b/Debug/POWER_SWITCH.map index 82013c5..5a57ac6 100644 --- a/Debug/POWER_SWITCH.map +++ b/Debug/POWER_SWITCH.map @@ -3650,7 +3650,7 @@ LOAD C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x08000000 g_pfnVectors 0x080001d8 . = ALIGN (0x4) -.text 0x080001d8 0x7554 +.text 0x080001d8 0x759c 0x080001d8 . = ALIGN (0x4) *(.text) .text 0x080001d8 0x40 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o @@ -3709,672 +3709,679 @@ LOAD C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x080011a0 0x148 ./Core/Src/main.o 0x080011a0 voltage_conversion_task .text.serial_number_task - 0x080012e8 0xe8 ./Core/Src/main.o + 0x080012e8 0x130 ./Core/Src/main.o 0x080012e8 serial_number_task .text.adc_task - 0x080013d0 0x58 ./Core/Src/main.o - 0x080013d0 adc_task + 0x08001418 0x58 ./Core/Src/main.o + 0x08001418 adc_task .text.power_switch - 0x08001428 0x54 ./Core/Src/main.o - 0x08001428 power_switch + 0x08001470 0x54 ./Core/Src/main.o + 0x08001470 power_switch .text.HAL_UART_TxCpltCallback - 0x0800147c 0x14 ./Core/Src/main.o - 0x0800147c HAL_UART_TxCpltCallback + 0x080014c4 0x14 ./Core/Src/main.o + 0x080014c4 HAL_UART_TxCpltCallback .text.HAL_UART_RxCpltCallback - 0x08001490 0x220 ./Core/Src/main.o - 0x08001490 HAL_UART_RxCpltCallback + 0x080014d8 0x220 ./Core/Src/main.o + 0x080014d8 HAL_UART_RxCpltCallback .text.Error_Handler - 0x080016b0 0xc ./Core/Src/main.o - 0x080016b0 Error_Handler + 0x080016f8 0xc ./Core/Src/main.o + 0x080016f8 Error_Handler .text.HAL_MspInit - 0x080016bc 0x48 ./Core/Src/stm32g4xx_hal_msp.o - 0x080016bc HAL_MspInit + 0x08001704 0x48 ./Core/Src/stm32g4xx_hal_msp.o + 0x08001704 HAL_MspInit .text.HAL_ADC_MspInit - 0x08001704 0x118 ./Core/Src/stm32g4xx_hal_msp.o - 0x08001704 HAL_ADC_MspInit + 0x0800174c 0x118 ./Core/Src/stm32g4xx_hal_msp.o + 0x0800174c HAL_ADC_MspInit .text.HAL_TIM_Base_MspInit - 0x0800181c 0x48 ./Core/Src/stm32g4xx_hal_msp.o - 0x0800181c HAL_TIM_Base_MspInit + 0x08001864 0x48 ./Core/Src/stm32g4xx_hal_msp.o + 0x08001864 HAL_TIM_Base_MspInit .text.HAL_UART_MspInit - 0x08001864 0xc0 ./Core/Src/stm32g4xx_hal_msp.o - 0x08001864 HAL_UART_MspInit + 0x080018ac 0xc0 ./Core/Src/stm32g4xx_hal_msp.o + 0x080018ac HAL_UART_MspInit .text.NMI_Handler - 0x08001924 0x8 ./Core/Src/stm32g4xx_it.o - 0x08001924 NMI_Handler + 0x0800196c 0x8 ./Core/Src/stm32g4xx_it.o + 0x0800196c NMI_Handler .text.HardFault_Handler - 0x0800192c 0x8 ./Core/Src/stm32g4xx_it.o - 0x0800192c HardFault_Handler + 0x08001974 0x8 ./Core/Src/stm32g4xx_it.o + 0x08001974 HardFault_Handler .text.MemManage_Handler - 0x08001934 0x8 ./Core/Src/stm32g4xx_it.o - 0x08001934 MemManage_Handler + 0x0800197c 0x8 ./Core/Src/stm32g4xx_it.o + 0x0800197c MemManage_Handler .text.BusFault_Handler - 0x0800193c 0x8 ./Core/Src/stm32g4xx_it.o - 0x0800193c BusFault_Handler + 0x08001984 0x8 ./Core/Src/stm32g4xx_it.o + 0x08001984 BusFault_Handler .text.UsageFault_Handler - 0x08001944 0x8 ./Core/Src/stm32g4xx_it.o - 0x08001944 UsageFault_Handler + 0x0800198c 0x8 ./Core/Src/stm32g4xx_it.o + 0x0800198c UsageFault_Handler .text.SVC_Handler - 0x0800194c 0xe ./Core/Src/stm32g4xx_it.o - 0x0800194c SVC_Handler + 0x08001994 0xe ./Core/Src/stm32g4xx_it.o + 0x08001994 SVC_Handler .text.DebugMon_Handler - 0x0800195a 0xe ./Core/Src/stm32g4xx_it.o - 0x0800195a DebugMon_Handler + 0x080019a2 0xe ./Core/Src/stm32g4xx_it.o + 0x080019a2 DebugMon_Handler .text.PendSV_Handler - 0x08001968 0xe ./Core/Src/stm32g4xx_it.o - 0x08001968 PendSV_Handler + 0x080019b0 0xe ./Core/Src/stm32g4xx_it.o + 0x080019b0 PendSV_Handler .text.SysTick_Handler - 0x08001976 0xc ./Core/Src/stm32g4xx_it.o - 0x08001976 SysTick_Handler - *fill* 0x08001982 0x2 + 0x080019be 0xc ./Core/Src/stm32g4xx_it.o + 0x080019be SysTick_Handler + *fill* 0x080019ca 0x2 .text.TIM2_IRQHandler - 0x08001984 0x14 ./Core/Src/stm32g4xx_it.o - 0x08001984 TIM2_IRQHandler + 0x080019cc 0x14 ./Core/Src/stm32g4xx_it.o + 0x080019cc TIM2_IRQHandler .text.USART2_IRQHandler - 0x08001998 0x14 ./Core/Src/stm32g4xx_it.o - 0x08001998 USART2_IRQHandler + 0x080019e0 0x14 ./Core/Src/stm32g4xx_it.o + 0x080019e0 USART2_IRQHandler .text.SystemInit - 0x080019ac 0x24 ./Core/Src/system_stm32g4xx.o - 0x080019ac SystemInit + 0x080019f4 0x24 ./Core/Src/system_stm32g4xx.o + 0x080019f4 SystemInit .text.Reset_Handler - 0x080019d0 0x50 ./Core/Startup/startup_stm32g431kbtx.o - 0x080019d0 Reset_Handler + 0x08001a18 0x50 ./Core/Startup/startup_stm32g431kbtx.o + 0x08001a18 Reset_Handler .text.Default_Handler - 0x08001a20 0x2 ./Core/Startup/startup_stm32g431kbtx.o - 0x08001a20 RTC_Alarm_IRQHandler - 0x08001a20 EXTI2_IRQHandler - 0x08001a20 TIM8_TRG_COM_IRQHandler - 0x08001a20 TIM8_CC_IRQHandler - 0x08001a20 TIM1_CC_IRQHandler - 0x08001a20 USB_HP_IRQHandler - 0x08001a20 CORDIC_IRQHandler - 0x08001a20 EXTI3_IRQHandler - 0x08001a20 I2C3_ER_IRQHandler - 0x08001a20 EXTI0_IRQHandler - 0x08001a20 I2C2_EV_IRQHandler - 0x08001a20 FPU_IRQHandler - 0x08001a20 FDCAN1_IT1_IRQHandler - 0x08001a20 TIM1_UP_TIM16_IRQHandler - 0x08001a20 ADC1_2_IRQHandler - 0x08001a20 SPI1_IRQHandler - 0x08001a20 TIM6_DAC_IRQHandler - 0x08001a20 TIM8_UP_IRQHandler - 0x08001a20 DMA2_Channel2_IRQHandler - 0x08001a20 DMA1_Channel4_IRQHandler - 0x08001a20 USART3_IRQHandler - 0x08001a20 TIM4_IRQHandler - 0x08001a20 DMA2_Channel1_IRQHandler - 0x08001a20 I2C1_EV_IRQHandler - 0x08001a20 DMA1_Channel6_IRQHandler - 0x08001a20 UART4_IRQHandler - 0x08001a20 DMA2_Channel4_IRQHandler - 0x08001a20 TIM3_IRQHandler - 0x08001a20 RCC_IRQHandler - 0x08001a20 DMA1_Channel1_IRQHandler - 0x08001a20 Default_Handler - 0x08001a20 RTC_TAMP_LSECSS_IRQHandler - 0x08001a20 FMAC_IRQHandler - 0x08001a20 EXTI15_10_IRQHandler - 0x08001a20 TIM7_IRQHandler - 0x08001a20 UCPD1_IRQHandler - 0x08001a20 I2C3_EV_IRQHandler - 0x08001a20 EXTI9_5_IRQHandler - 0x08001a20 RTC_WKUP_IRQHandler - 0x08001a20 PVD_PVM_IRQHandler - 0x08001a20 SPI2_IRQHandler - 0x08001a20 DMA2_Channel5_IRQHandler - 0x08001a20 CRS_IRQHandler - 0x08001a20 DMA1_Channel5_IRQHandler - 0x08001a20 USB_LP_IRQHandler - 0x08001a20 EXTI4_IRQHandler - 0x08001a20 RNG_IRQHandler - 0x08001a20 TIM1_TRG_COM_TIM17_IRQHandler - 0x08001a20 DMA1_Channel3_IRQHandler - 0x08001a20 WWDG_IRQHandler - 0x08001a20 LPUART1_IRQHandler - 0x08001a20 DMA2_Channel6_IRQHandler - 0x08001a20 FDCAN1_IT0_IRQHandler - 0x08001a20 COMP1_2_3_IRQHandler - 0x08001a20 EXTI1_IRQHandler - 0x08001a20 I2C2_ER_IRQHandler - 0x08001a20 DMA1_Channel2_IRQHandler - 0x08001a20 TIM8_BRK_IRQHandler - 0x08001a20 FLASH_IRQHandler - 0x08001a20 USART1_IRQHandler - 0x08001a20 SPI3_IRQHandler - 0x08001a20 I2C1_ER_IRQHandler - 0x08001a20 LPTIM1_IRQHandler - 0x08001a20 DMAMUX_OVR_IRQHandler - 0x08001a20 USBWakeUp_IRQHandler - 0x08001a20 SAI1_IRQHandler - 0x08001a20 DMA2_Channel3_IRQHandler - 0x08001a20 COMP4_IRQHandler - 0x08001a20 TIM1_BRK_TIM15_IRQHandler + 0x08001a68 0x2 ./Core/Startup/startup_stm32g431kbtx.o + 0x08001a68 RTC_Alarm_IRQHandler + 0x08001a68 EXTI2_IRQHandler + 0x08001a68 TIM8_TRG_COM_IRQHandler + 0x08001a68 TIM8_CC_IRQHandler + 0x08001a68 TIM1_CC_IRQHandler + 0x08001a68 USB_HP_IRQHandler + 0x08001a68 CORDIC_IRQHandler + 0x08001a68 EXTI3_IRQHandler + 0x08001a68 I2C3_ER_IRQHandler + 0x08001a68 EXTI0_IRQHandler + 0x08001a68 I2C2_EV_IRQHandler + 0x08001a68 FPU_IRQHandler + 0x08001a68 FDCAN1_IT1_IRQHandler + 0x08001a68 TIM1_UP_TIM16_IRQHandler + 0x08001a68 ADC1_2_IRQHandler + 0x08001a68 SPI1_IRQHandler + 0x08001a68 TIM6_DAC_IRQHandler + 0x08001a68 TIM8_UP_IRQHandler + 0x08001a68 DMA2_Channel2_IRQHandler + 0x08001a68 DMA1_Channel4_IRQHandler + 0x08001a68 USART3_IRQHandler + 0x08001a68 TIM4_IRQHandler + 0x08001a68 DMA2_Channel1_IRQHandler + 0x08001a68 I2C1_EV_IRQHandler + 0x08001a68 DMA1_Channel6_IRQHandler + 0x08001a68 UART4_IRQHandler + 0x08001a68 DMA2_Channel4_IRQHandler + 0x08001a68 TIM3_IRQHandler + 0x08001a68 RCC_IRQHandler + 0x08001a68 DMA1_Channel1_IRQHandler + 0x08001a68 Default_Handler + 0x08001a68 RTC_TAMP_LSECSS_IRQHandler + 0x08001a68 FMAC_IRQHandler + 0x08001a68 EXTI15_10_IRQHandler + 0x08001a68 TIM7_IRQHandler + 0x08001a68 UCPD1_IRQHandler + 0x08001a68 I2C3_EV_IRQHandler + 0x08001a68 EXTI9_5_IRQHandler + 0x08001a68 RTC_WKUP_IRQHandler + 0x08001a68 PVD_PVM_IRQHandler + 0x08001a68 SPI2_IRQHandler + 0x08001a68 DMA2_Channel5_IRQHandler + 0x08001a68 CRS_IRQHandler + 0x08001a68 DMA1_Channel5_IRQHandler + 0x08001a68 USB_LP_IRQHandler + 0x08001a68 EXTI4_IRQHandler + 0x08001a68 RNG_IRQHandler + 0x08001a68 TIM1_TRG_COM_TIM17_IRQHandler + 0x08001a68 DMA1_Channel3_IRQHandler + 0x08001a68 WWDG_IRQHandler + 0x08001a68 LPUART1_IRQHandler + 0x08001a68 DMA2_Channel6_IRQHandler + 0x08001a68 FDCAN1_IT0_IRQHandler + 0x08001a68 COMP1_2_3_IRQHandler + 0x08001a68 EXTI1_IRQHandler + 0x08001a68 I2C2_ER_IRQHandler + 0x08001a68 DMA1_Channel2_IRQHandler + 0x08001a68 TIM8_BRK_IRQHandler + 0x08001a68 FLASH_IRQHandler + 0x08001a68 USART1_IRQHandler + 0x08001a68 SPI3_IRQHandler + 0x08001a68 I2C1_ER_IRQHandler + 0x08001a68 LPTIM1_IRQHandler + 0x08001a68 DMAMUX_OVR_IRQHandler + 0x08001a68 USBWakeUp_IRQHandler + 0x08001a68 SAI1_IRQHandler + 0x08001a68 DMA2_Channel3_IRQHandler + 0x08001a68 COMP4_IRQHandler + 0x08001a68 TIM1_BRK_TIM15_IRQHandler .text.HAL_Init - 0x08001a22 0x30 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x08001a22 HAL_Init - *fill* 0x08001a52 0x2 + 0x08001a6a 0x30 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + 0x08001a6a HAL_Init + *fill* 0x08001a9a 0x2 .text.HAL_InitTick - 0x08001a54 0x74 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x08001a54 HAL_InitTick + 0x08001a9c 0x74 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + 0x08001a9c HAL_InitTick .text.HAL_IncTick - 0x08001ac8 0x24 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x08001ac8 HAL_IncTick + 0x08001b10 0x24 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + 0x08001b10 HAL_IncTick .text.HAL_GetTick - 0x08001aec 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x08001aec HAL_GetTick + 0x08001b34 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + 0x08001b34 HAL_GetTick .text.LL_ADC_SetCommonClock - 0x08001b04 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001b4c 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetCommonPathInternalCh - 0x08001b2a 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001b72 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_GetCommonPathInternalCh - 0x08001b50 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001b98 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetOffset - 0x08001b6c 0x48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001bb4 0x48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_GetOffsetChannel - 0x08001bb4 0x2c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001bfc 0x2c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetOffsetState - 0x08001be0 0x36 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001c28 0x36 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetOffsetSign - 0x08001c16 0x36 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001c5e 0x36 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetOffsetSaturation - 0x08001c4c 0x36 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001c94 0x36 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetSamplingTimeCommonConfig - 0x08001c82 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001cca 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_REG_IsTriggerSourceSWStart - 0x08001ca8 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001cf0 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_REG_SetSequencerRanks - 0x08001cce 0x58 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001d16 0x58 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetChannelSamplingTime - 0x08001d26 0x56 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001d6e 0x56 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_SetChannelSingleDiff - 0x08001d7c 0x48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001dc4 0x48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_GetMultimode - 0x08001dc4 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001e0c 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_GetMultiDMATransfer - 0x08001de0 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001e28 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_DisableDeepPowerDown - 0x08001dfc 0x24 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001e44 0x24 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_IsDeepPowerDownEnabled - 0x08001e20 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001e68 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_EnableInternalRegulator - 0x08001e48 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001e90 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_IsInternalRegulatorEnabled - 0x08001e70 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001eb8 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_Enable - 0x08001e98 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001ee0 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_Disable - 0x08001ec0 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001f08 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_IsEnabled - 0x08001ee8 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001f30 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_IsDisableOngoing - 0x08001f0e 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001f56 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_REG_StartConversion - 0x08001f34 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001f7c 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_REG_StopConversion - 0x08001f5c 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001fa4 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_REG_IsConversionOngoing - 0x08001f84 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001fcc 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_INJ_StopConversion - 0x08001faa 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08001ff2 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.LL_ADC_INJ_IsConversionOngoing - 0x08001fd2 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x0800201a 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o .text.HAL_ADC_Init - 0x08001ff8 0x308 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08001ff8 HAL_ADC_Init + 0x08002040 0x308 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08002040 HAL_ADC_Init .text.HAL_ADC_Start - 0x08002300 0x178 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08002300 HAL_ADC_Start + 0x08002348 0x178 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08002348 HAL_ADC_Start .text.HAL_ADC_Stop - 0x08002478 0x66 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08002478 HAL_ADC_Stop - *fill* 0x080024de 0x2 + 0x080024c0 0x66 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x080024c0 HAL_ADC_Stop + *fill* 0x08002526 0x2 .text.HAL_ADC_PollForConversion - 0x080024e0 0x1b0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x080024e0 HAL_ADC_PollForConversion + 0x08002528 0x1b0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08002528 HAL_ADC_PollForConversion .text.HAL_ADC_GetValue - 0x08002690 0x1a ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08002690 HAL_ADC_GetValue - *fill* 0x080026aa 0x2 + 0x080026d8 0x1a ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x080026d8 HAL_ADC_GetValue + *fill* 0x080026f2 0x2 .text.HAL_ADC_ConfigChannel - 0x080026ac 0x7e0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x080026ac HAL_ADC_ConfigChannel + 0x080026f4 0x7e0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x080026f4 HAL_ADC_ConfigChannel .text.ADC_ConversionStop - 0x08002e8c 0x178 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08002e8c ADC_ConversionStop + 0x08002ed4 0x178 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08002ed4 ADC_ConversionStop .text.ADC_Enable - 0x08003004 0x10c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08003004 ADC_Enable + 0x0800304c 0x10c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x0800304c ADC_Enable .text.ADC_Disable - 0x08003110 0xbe ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - 0x08003110 ADC_Disable + 0x08003158 0xbe ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + 0x08003158 ADC_Disable .text.LL_ADC_IsEnabled - 0x080031ce 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + 0x08003216 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o .text.LL_ADC_StartCalibration - 0x080031f4 0x32 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + 0x0800323c 0x32 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o .text.LL_ADC_IsCalibrationOnGoing - 0x08003226 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + 0x0800326e 0x28 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o .text.LL_ADC_REG_IsConversionOngoing - 0x0800324e 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + 0x08003296 0x26 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o .text.HAL_ADCEx_Calibration_Start - 0x08003274 0xc4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o - 0x08003274 HAL_ADCEx_Calibration_Start + 0x080032bc 0xc4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + 0x080032bc HAL_ADCEx_Calibration_Start .text.HAL_ADCEx_MultiModeConfigChannel - 0x08003338 0x148 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o - 0x08003338 HAL_ADCEx_MultiModeConfigChannel + 0x08003380 0x148 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + 0x08003380 HAL_ADCEx_MultiModeConfigChannel .text.__NVIC_SetPriorityGrouping - 0x08003480 0x48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x080034c8 0x48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o .text.__NVIC_GetPriorityGrouping - 0x080034c8 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x08003510 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o .text.__NVIC_EnableIRQ - 0x080034e4 0x3c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x0800352c 0x3c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o .text.__NVIC_SetPriority - 0x08003520 0x54 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x08003568 0x54 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o .text.NVIC_EncodePriority - 0x08003574 0x66 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - *fill* 0x080035da 0x2 + 0x080035bc 0x66 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + *fill* 0x08003622 0x2 .text.SysTick_Config - 0x080035dc 0x44 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x08003624 0x44 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o .text.HAL_NVIC_SetPriorityGrouping - 0x08003620 0x16 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - 0x08003620 HAL_NVIC_SetPriorityGrouping + 0x08003668 0x16 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x08003668 HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x08003636 0x34 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - 0x08003636 HAL_NVIC_SetPriority + 0x0800367e 0x34 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x0800367e HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x0800366a 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - 0x0800366a HAL_NVIC_EnableIRQ + 0x080036b2 0x1c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x080036b2 HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x08003686 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - 0x08003686 HAL_SYSTICK_Config + 0x080036ce 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + 0x080036ce HAL_SYSTICK_Config .text.HAL_DMA_Abort - 0x0800369e 0xb2 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o - 0x0800369e HAL_DMA_Abort + 0x080036e6 0xb2 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o + 0x080036e6 HAL_DMA_Abort .text.HAL_DMA_Abort_IT - 0x08003750 0xce ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o - 0x08003750 HAL_DMA_Abort_IT - *fill* 0x0800381e 0x2 + 0x08003798 0xce ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o + 0x08003798 HAL_DMA_Abort_IT + *fill* 0x08003866 0x2 .text.HAL_GPIO_Init - 0x08003820 0x304 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o - 0x08003820 HAL_GPIO_Init + 0x08003868 0x304 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o + 0x08003868 HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x08003b24 0x30 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o - 0x08003b24 HAL_GPIO_WritePin + 0x08003b6c 0x30 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o + 0x08003b6c HAL_GPIO_WritePin .text.HAL_PWREx_ControlVoltageScaling - 0x08003b54 0x148 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o - 0x08003b54 HAL_PWREx_ControlVoltageScaling + 0x08003b9c 0x148 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o + 0x08003b9c HAL_PWREx_ControlVoltageScaling .text.HAL_PWREx_DisableUCPDDeadBattery - 0x08003c9c 0x20 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o - 0x08003c9c HAL_PWREx_DisableUCPDDeadBattery + 0x08003ce4 0x20 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o + 0x08003ce4 HAL_PWREx_DisableUCPDDeadBattery .text.HAL_RCC_OscConfig - 0x08003cbc 0x624 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - 0x08003cbc HAL_RCC_OscConfig + 0x08003d04 0x624 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x08003d04 HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x080042e0 0x278 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - 0x080042e0 HAL_RCC_ClockConfig + 0x08004328 0x278 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x08004328 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x08004558 0xc4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - 0x08004558 HAL_RCC_GetSysClockFreq + 0x080045a0 0xc4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x080045a0 HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x0800461c 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - 0x0800461c HAL_RCC_GetHCLKFreq + 0x08004664 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x08004664 HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x08004634 0x2c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - 0x08004634 HAL_RCC_GetPCLK1Freq + 0x0800467c 0x2c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x0800467c HAL_RCC_GetPCLK1Freq .text.HAL_RCC_GetPCLK2Freq - 0x08004660 0x2c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - 0x08004660 HAL_RCC_GetPCLK2Freq + 0x080046a8 0x2c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x080046a8 HAL_RCC_GetPCLK2Freq .text.RCC_GetSysClockFreqFromPLLSource - 0x0800468c 0x8c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + 0x080046d4 0x8c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o .text.HAL_RCCEx_PeriphCLKConfig - 0x08004718 0x3e0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o - 0x08004718 HAL_RCCEx_PeriphCLKConfig + 0x08004760 0x3e0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o + 0x08004760 HAL_RCCEx_PeriphCLKConfig .text.HAL_TIM_Base_Init - 0x08004af8 0xae ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - 0x08004af8 HAL_TIM_Base_Init + 0x08004b40 0xae ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x08004b40 HAL_TIM_Base_Init .text.HAL_TIM_IRQHandler - 0x08004ba6 0x29e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - 0x08004ba6 HAL_TIM_IRQHandler + 0x08004bee 0x29e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x08004bee HAL_TIM_IRQHandler .text.HAL_TIM_ConfigClockSource - 0x08004e44 0x1f4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - 0x08004e44 HAL_TIM_ConfigClockSource + 0x08004e8c 0x1f4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x08004e8c HAL_TIM_ConfigClockSource .text.HAL_TIM_PeriodElapsedCallback - 0x08005038 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - 0x08005038 HAL_TIM_PeriodElapsedCallback + 0x08005080 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x08005080 HAL_TIM_PeriodElapsedCallback .text.HAL_TIM_OC_DelayElapsedCallback - 0x0800504c 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - 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0x0800509c TIM_Base_SetConfig + 0x080050e4 0x138 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x080050e4 TIM_Base_SetConfig .text.TIM_TI1_ConfigInputStage - 0x080051d4 0x5e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x0800521c 0x5e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o .text.TIM_TI2_ConfigInputStage - 0x08005232 0x60 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x0800527a 0x60 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o .text.TIM_ITRx_SetConfig - 0x08005292 0x3a ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x080052da 0x3a ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o .text.TIM_ETR_SetConfig - 0x080052cc 0x40 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - 0x080052cc TIM_ETR_SetConfig + 0x08005314 0x40 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + 0x08005314 TIM_ETR_SetConfig .text.HAL_TIMEx_MasterConfigSynchronization - 0x0800530c 0x104 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x0800530c HAL_TIMEx_MasterConfigSynchronization + 0x08005354 0x104 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x08005354 HAL_TIMEx_MasterConfigSynchronization .text.HAL_TIMEx_CommutCallback - 0x08005410 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x08005410 HAL_TIMEx_CommutCallback + 0x08005458 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x08005458 HAL_TIMEx_CommutCallback .text.HAL_TIMEx_BreakCallback - 0x08005424 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x08005424 HAL_TIMEx_BreakCallback + 0x0800546c 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x0800546c HAL_TIMEx_BreakCallback .text.HAL_TIMEx_Break2Callback - 0x08005438 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x08005438 HAL_TIMEx_Break2Callback + 0x08005480 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x08005480 HAL_TIMEx_Break2Callback .text.HAL_TIMEx_EncoderIndexCallback - 0x0800544c 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x0800544c HAL_TIMEx_EncoderIndexCallback + 0x08005494 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x08005494 HAL_TIMEx_EncoderIndexCallback .text.HAL_TIMEx_DirectionChangeCallback - 0x08005460 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x08005460 HAL_TIMEx_DirectionChangeCallback + 0x080054a8 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x080054a8 HAL_TIMEx_DirectionChangeCallback .text.HAL_TIMEx_IndexErrorCallback - 0x08005474 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x08005474 HAL_TIMEx_IndexErrorCallback + 0x080054bc 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x080054bc HAL_TIMEx_IndexErrorCallback .text.HAL_TIMEx_TransitionErrorCallback - 0x08005488 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - 0x08005488 HAL_TIMEx_TransitionErrorCallback + 0x080054d0 0x14 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + 0x080054d0 HAL_TIMEx_TransitionErrorCallback .text.HAL_UART_Init - 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0x08007720 _fini - .fini 0x08007724 0x8 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o - 0x0800772c . = ALIGN (0x4) - 0x0800772c _etext = . + .fini 0x08007768 0x4 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crti.o + 0x08007768 _fini + .fini 0x0800776c 0x8 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtn.o + 0x08007774 . = ALIGN (0x4) + 0x08007774 _etext = . -.vfp11_veneer 0x0800772c 0x0 - .vfp11_veneer 0x0800772c 0x0 linker stubs +.vfp11_veneer 0x08007774 0x0 + .vfp11_veneer 0x08007774 0x0 linker stubs -.v4_bx 0x0800772c 0x0 - .v4_bx 0x0800772c 0x0 linker stubs +.v4_bx 0x08007774 0x0 + .v4_bx 0x08007774 0x0 linker stubs -.iplt 0x0800772c 0x0 - .iplt 0x0800772c 0x0 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.iplt 0x08007774 0x0 + .iplt 0x08007774 0x0 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.rodata 0x0800772c 0x40 - 0x0800772c . = ALIGN (0x4) +.rodata 0x08007774 0x40 + 0x08007774 . = ALIGN (0x4) *(.rodata) *(.rodata*) .rodata.AHBPrescTable - 0x0800772c 0x10 ./Core/Src/system_stm32g4xx.o - 0x0800772c AHBPrescTable + 0x08007774 0x10 ./Core/Src/system_stm32g4xx.o + 0x08007774 AHBPrescTable .rodata.APBPrescTable - 0x0800773c 0x8 ./Core/Src/system_stm32g4xx.o - 0x0800773c APBPrescTable + 0x08007784 0x8 ./Core/Src/system_stm32g4xx.o + 0x08007784 APBPrescTable .rodata.UARTPrescTable - 0x08007744 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o - 0x08007744 UARTPrescTable + 0x0800778c 0x18 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o + 0x0800778c UARTPrescTable .rodata.numerator.1 - 0x0800775c 0x8 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o + 0x080077a4 0x8 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o .rodata.denominator.0 - 0x08007764 0x8 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o - 0x0800776c . = ALIGN (0x4) + 0x080077ac 0x8 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o + 0x080077b4 . = ALIGN (0x4) -.ARM.extab 0x0800776c 0x0 - 0x0800776c . = ALIGN (0x4) +.ARM.extab 0x080077b4 0x0 + 0x080077b4 . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x0800776c . = ALIGN (0x4) + 0x080077b4 . = ALIGN (0x4) -.ARM 0x0800776c 0x8 - 0x0800776c . = ALIGN (0x4) - 0x0800776c __exidx_start = . +.ARM 0x080077b4 0x8 + 0x080077b4 . = ALIGN (0x4) + 0x080077b4 __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x0800776c 0x8 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) - 0x08007774 __exidx_end = . - 0x08007774 . = ALIGN (0x4) + .ARM.exidx 0x080077b4 0x8 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) + 0x080077bc __exidx_end = . + 0x080077bc . = ALIGN (0x4) -.preinit_array 0x08007774 0x0 - 0x08007774 . = ALIGN (0x4) - 0x08007774 PROVIDE (__preinit_array_start = .) +.preinit_array 0x080077bc 0x0 + 0x080077bc . = ALIGN (0x4) + 0x080077bc PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08007774 PROVIDE (__preinit_array_end = .) - 0x08007774 . = ALIGN (0x4) + 0x080077bc PROVIDE (__preinit_array_end = .) + 0x080077bc . = ALIGN (0x4) -.init_array 0x08007774 0x4 - 0x08007774 . = ALIGN (0x4) - 0x08007774 PROVIDE (__init_array_start = .) +.init_array 0x080077bc 0x4 + 0x080077bc . = ALIGN (0x4) + 0x080077bc PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08007774 0x4 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x08007778 PROVIDE (__init_array_end = .) - 0x08007778 . = ALIGN (0x4) + .init_array 0x080077bc 0x4 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x080077c0 PROVIDE (__init_array_end = .) + 0x080077c0 . = ALIGN (0x4) -.fini_array 0x08007778 0x4 - 0x08007778 . = ALIGN (0x4) +.fini_array 0x080077c0 0x4 + 0x080077c0 . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x08007778 0x4 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .fini_array 0x080077c0 0x4 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x0800777c . = ALIGN (0x4) - 0x0800777c _sidata = LOADADDR (.data) + 0x080077c4 . = ALIGN (0x4) + 0x080077c4 _sidata = LOADADDR (.data) -.rel.dyn 0x0800777c 0x0 - .rel.iplt 0x0800777c 0x0 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o +.rel.dyn 0x080077c4 0x0 + .rel.iplt 0x080077c4 0x0 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o -.data 0x20000000 0x20 load address 0x0800777c +.data 0x20000000 0x24 load address 0x080077c4 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) *(.data*) + .data.fw_rev_l + 0x20000000 0x1 ./Core/Src/main.o + 0x20000000 fw_rev_l + *fill* 0x20000001 0x3 .data.serial_number - 0x20000000 0x13 ./Core/Src/main.o - 0x20000000 serial_number - *fill* 0x20000013 0x1 + 0x20000004 0x13 ./Core/Src/main.o + 0x20000004 serial_number + *fill* 0x20000017 0x1 .data.SystemCoreClock - 0x20000014 0x4 ./Core/Src/system_stm32g4xx.o - 0x20000014 SystemCoreClock + 0x20000018 0x4 ./Core/Src/system_stm32g4xx.o + 0x20000018 SystemCoreClock .data.uwTickPrio - 0x20000018 0x4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x20000018 uwTickPrio - .data.uwTickFreq 0x2000001c 0x4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x2000001c uwTickFreq + 0x2000001c uwTickPrio + .data.uwTickFreq + 0x20000020 0x4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + 0x20000020 uwTickFreq *(.RamFunc) *(.RamFunc*) - 0x20000020 . = ALIGN (0x4) - 0x20000020 _edata = . + 0x20000024 . = ALIGN (0x4) + 0x20000024 _edata = . -.igot.plt 0x20000020 0x0 load address 0x0800779c - .igot.plt 0x20000020 0x0 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o - 0x20000020 . = ALIGN (0x4) +.igot.plt 0x20000024 0x0 load address 0x080077e8 + .igot.plt 0x20000024 0x0 C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x20000024 . = ALIGN (0x4) -.bss 0x20000020 0x248 load address 0x0800779c - 0x20000020 _sbss = . - 0x20000020 __bss_start__ = _sbss +.bss 0x20000024 0x24c load address 0x080077e8 + 0x20000024 _sbss = . + 0x20000024 __bss_start__ = _sbss *(.bss) - .bss 0x20000020 0x1c C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o + .bss 0x20000024 0x1c C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard/crtbegin.o *(.bss*) - .bss.hadc1 0x2000003c 0x6c ./Core/Src/main.o - 0x2000003c hadc1 - .bss.hadc2 0x200000a8 0x6c ./Core/Src/main.o - 0x200000a8 hadc2 - .bss.htim2 0x20000114 0x4c ./Core/Src/main.o - 0x20000114 htim2 - .bss.huart2 0x20000160 0x94 ./Core/Src/main.o - 0x20000160 huart2 + .bss.hadc1 0x20000040 0x6c ./Core/Src/main.o + 0x20000040 hadc1 + .bss.hadc2 0x200000ac 0x6c ./Core/Src/main.o + 0x200000ac hadc2 + .bss.htim2 0x20000118 0x4c ./Core/Src/main.o + 0x20000118 htim2 + .bss.huart2 0x20000164 0x94 ./Core/Src/main.o + 0x20000164 huart2 + .bss.fw_rev_h 0x200001f8 0x1 ./Core/Src/main.o + 0x200001f8 fw_rev_h + *fill* 0x200001f9 0x3 .bss.rx_hold_buffer - 0x200001f4 0x2 ./Core/Src/main.o - 0x200001f4 rx_hold_buffer - *fill* 0x200001f6 0x2 + 0x200001fc 0x2 ./Core/Src/main.o + 0x200001fc rx_hold_buffer + *fill* 0x200001fe 0x2 .bss.rx_buffer - 0x200001f8 0x20 ./Core/Src/main.o - 0x200001f8 rx_buffer + 0x20000200 0x20 ./Core/Src/main.o + 0x20000200 rx_buffer .bss.tx_buffer - 0x20000218 0x20 ./Core/Src/main.o - 0x20000218 tx_buffer - .bss.tx_len 0x20000238 0x1 ./Core/Src/main.o - 0x20000238 tx_len + 0x20000220 0x20 ./Core/Src/main.o + 0x20000220 tx_buffer + .bss.tx_len 0x20000240 0x1 ./Core/Src/main.o + 0x20000240 tx_len .bss.tx_len_counter - 0x20000239 0x1 ./Core/Src/main.o - 0x20000239 tx_len_counter + 0x20000241 0x1 ./Core/Src/main.o + 0x20000241 tx_len_counter .bss.rx_counter - 0x2000023a 0x1 ./Core/Src/main.o - 0x2000023a rx_counter - .bss.rx_len 0x2000023b 0x1 ./Core/Src/main.o - 0x2000023b rx_len - .bss.rx_len_counter - 0x2000023c 0x1 ./Core/Src/main.o - 0x2000023c rx_len_counter - *fill* 0x2000023d 0x1 - .bss.rx_checksum - 0x2000023e 0x2 ./Core/Src/main.o - 0x2000023e rx_checksum - .bss.tx_checksum - 0x20000240 0x2 ./Core/Src/main.o - 0x20000240 tx_checksum - .bss.rx_checksum_hold_1 0x20000242 0x1 ./Core/Src/main.o - 0x20000242 rx_checksum_hold_1 + 0x20000242 rx_counter + .bss.rx_len 0x20000243 0x1 ./Core/Src/main.o + 0x20000243 rx_len + .bss.rx_len_counter + 0x20000244 0x1 ./Core/Src/main.o + 0x20000244 rx_len_counter + *fill* 0x20000245 0x1 + .bss.rx_checksum + 0x20000246 0x2 ./Core/Src/main.o + 0x20000246 rx_checksum + .bss.tx_checksum + 0x20000248 0x2 ./Core/Src/main.o + 0x20000248 tx_checksum + .bss.rx_checksum_hold_1 + 0x2000024a 0x1 ./Core/Src/main.o + 0x2000024a rx_checksum_hold_1 .bss.rx_checksum_hold_2 - 0x20000243 0x1 ./Core/Src/main.o - 0x20000243 rx_checksum_hold_2 + 0x2000024b 0x1 ./Core/Src/main.o + 0x2000024b rx_checksum_hold_2 .bss.rx_checksum_hold - 0x20000244 0x2 ./Core/Src/main.o - 0x20000244 rx_checksum_hold - .bss.power_state_value - 0x20000246 0x1 ./Core/Src/main.o - 0x20000246 power_state_value - .bss.command 0x20000247 0x1 ./Core/Src/main.o - 0x20000247 command - .bss.adc_task_flag - 0x20000248 0x1 ./Core/Src/main.o - 0x20000248 adc_task_flag - *fill* 0x20000249 0x1 - .bss.vin_adc_val - 0x2000024a 0x2 ./Core/Src/main.o - 0x2000024a vin_adc_val - .bss.vout_adc_val 0x2000024c 0x2 ./Core/Src/main.o - 0x2000024c vout_adc_val - *fill* 0x2000024e 0x2 - .bss.vdd_ref 0x20000250 0x4 ./Core/Src/main.o - 0x20000250 vdd_ref - .bss.vin_val 0x20000254 0x4 ./Core/Src/main.o - 0x20000254 vin_val - .bss.vout_val 0x20000258 0x4 ./Core/Src/main.o - 0x20000258 vout_val + 0x2000024c rx_checksum_hold + .bss.power_state_value + 0x2000024e 0x1 ./Core/Src/main.o + 0x2000024e power_state_value + .bss.command 0x2000024f 0x1 ./Core/Src/main.o + 0x2000024f command + .bss.adc_task_flag + 0x20000250 0x1 ./Core/Src/main.o + 0x20000250 adc_task_flag + *fill* 0x20000251 0x1 + .bss.vin_adc_val + 0x20000252 0x2 ./Core/Src/main.o + 0x20000252 vin_adc_val + .bss.vout_adc_val + 0x20000254 0x2 ./Core/Src/main.o + 0x20000254 vout_adc_val + *fill* 0x20000256 0x2 + .bss.vdd_ref 0x20000258 0x4 ./Core/Src/main.o + 0x20000258 vdd_ref + .bss.vin_val 0x2000025c 0x4 ./Core/Src/main.o + 0x2000025c vin_val + .bss.vout_val 0x20000260 0x4 ./Core/Src/main.o + 0x20000260 vout_val .bss.serial_number_flag - 0x2000025c 0x1 ./Core/Src/main.o - 0x2000025c serial_number_flag - *fill* 0x2000025d 0x3 + 0x20000264 0x1 ./Core/Src/main.o + 0x20000264 serial_number_flag + *fill* 0x20000265 0x3 .bss.HAL_RCC_ADC12_CLK_ENABLED - 0x20000260 0x4 ./Core/Src/stm32g4xx_hal_msp.o - .bss.uwTick 0x20000264 0x4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - 0x20000264 uwTick + 0x20000268 0x4 ./Core/Src/stm32g4xx_hal_msp.o + .bss.uwTick 0x2000026c 0x4 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + 0x2000026c uwTick *(COMMON) - 0x20000268 . = ALIGN (0x4) - 0x20000268 _ebss = . - 0x20000268 __bss_end__ = _ebss + 0x20000270 . = ALIGN (0x4) + 0x20000270 _ebss = . + 0x20000270 __bss_end__ = _ebss ._user_heap_stack - 0x20000268 0x600 load address 0x0800779c - 0x20000268 . = ALIGN (0x8) + 0x20000270 0x600 load address 0x080077e8 + 0x20000270 . = ALIGN (0x8) [!provide] PROVIDE (end = .) - 0x20000268 PROVIDE (_end = .) - 0x20000468 . = (. + _Min_Heap_Size) - *fill* 0x20000268 0x200 - 0x20000868 . = (. + _Min_Stack_Size) - *fill* 0x20000468 0x400 - 0x20000868 . = ALIGN (0x8) + 0x20000270 PROVIDE (_end = .) + 0x20000470 . = (. + _Min_Heap_Size) + *fill* 0x20000270 0x200 + 0x20000870 . = (. + _Min_Stack_Size) + *fill* 0x20000470 0x400 + 0x20000870 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -4448,25 +4455,25 @@ LOAD C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext LOAD C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a LOAD C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v7e-m+fp/hard\libgcc.a -.debug_info 0x00000000 0x170b0 - .debug_info 0x00000000 0x1d46 ./Core/Src/main.o - .debug_info 0x00001d46 0x18d9 ./Core/Src/stm32g4xx_hal_msp.o - .debug_info 0x0000361f 0xc5c ./Core/Src/stm32g4xx_it.o - .debug_info 0x0000427b 0x58e ./Core/Src/system_stm32g4xx.o - .debug_info 0x00004809 0x30 ./Core/Startup/startup_stm32g431kbtx.o - .debug_info 0x00004839 0xadb ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - .debug_info 0x00005314 0x2063 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - .debug_info 0x00007377 0x1d80 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o - .debug_info 0x000090f7 0xd3f ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - .debug_info 0x00009e36 0x85f ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o - .debug_info 0x0000a695 0x763 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o - .debug_info 0x0000adf8 0x93f ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o - .debug_info 0x0000b737 0xb82 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - .debug_info 0x0000c2b9 0xc15 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o - .debug_info 0x0000cece 0x2c52 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - .debug_info 0x0000fb20 0x1d95 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - .debug_info 0x000118b5 0x481e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o - .debug_info 0x000160d3 0xfdd ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o +.debug_info 0x00000000 0x170d2 + .debug_info 0x00000000 0x1d68 ./Core/Src/main.o + .debug_info 0x00001d68 0x18d9 ./Core/Src/stm32g4xx_hal_msp.o + .debug_info 0x00003641 0xc5c ./Core/Src/stm32g4xx_it.o + .debug_info 0x0000429d 0x58e ./Core/Src/system_stm32g4xx.o + .debug_info 0x0000482b 0x30 ./Core/Startup/startup_stm32g431kbtx.o + .debug_info 0x0000485b 0xadb ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + .debug_info 0x00005336 0x2063 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + .debug_info 0x00007399 0x1d80 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + .debug_info 0x00009119 0xd3f ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + .debug_info 0x00009e58 0x85f ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o + .debug_info 0x0000a6b7 0x763 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o + .debug_info 0x0000ae1a 0x93f ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o + .debug_info 0x0000b759 0xb82 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + .debug_info 0x0000c2db 0xc15 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o + .debug_info 0x0000cef0 0x2c52 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + .debug_info 0x0000fb42 0x1d95 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + .debug_info 0x000118d7 0x481e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o + .debug_info 0x000160f5 0xfdd ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o .debug_abbrev 0x00000000 0x2a3f .debug_abbrev 0x00000000 0x33a ./Core/Src/main.o @@ -4645,62 +4652,62 @@ LOAD C:/ST/STM32CubeIDE_1.15.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .debug_macro 0x0001ffee 0x21c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o .debug_macro 0x0002020a 0x1fd ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o -.debug_line 0x00000000 0x168d9 - .debug_line 0x00000000 0xed6 ./Core/Src/main.o - .debug_line 0x00000ed6 0x906 ./Core/Src/stm32g4xx_hal_msp.o - .debug_line 0x000017dc 0x88f ./Core/Src/stm32g4xx_it.o - .debug_line 0x0000206b 0x81d ./Core/Src/system_stm32g4xx.o - .debug_line 0x00002888 0x7b ./Core/Startup/startup_stm32g431kbtx.o - .debug_line 0x00002903 0xbe9 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o - .debug_line 0x000034ec 0x1ff3 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o - .debug_line 0x000054df 0x1a0a ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o - .debug_line 0x00006ee9 0xd4e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o - .debug_line 0x00007c37 0xee8 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o - .debug_line 0x00008b1f 0xbc2 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o - .debug_line 0x000096e1 0xd48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o - .debug_line 0x0000a429 0x106c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o - .debug_line 0x0000b495 0x1198 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o - .debug_line 0x0000c62d 0x3f50 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o - .debug_line 0x0001057d 0x2030 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o - .debug_line 0x000125ad 0x360e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o - .debug_line 0x00015bbb 0xd1e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o +.debug_line 0x00000000 0x16908 + .debug_line 0x00000000 0xf05 ./Core/Src/main.o + .debug_line 0x00000f05 0x906 ./Core/Src/stm32g4xx_hal_msp.o + .debug_line 0x0000180b 0x88f ./Core/Src/stm32g4xx_it.o + .debug_line 0x0000209a 0x81d ./Core/Src/system_stm32g4xx.o + .debug_line 0x000028b7 0x7b ./Core/Startup/startup_stm32g431kbtx.o + .debug_line 0x00002932 0xbe9 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + .debug_line 0x0000351b 0x1ff3 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + .debug_line 0x0000550e 0x1a0a ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + .debug_line 0x00006f18 0xd4e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + .debug_line 0x00007c66 0xee8 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o + .debug_line 0x00008b4e 0xbc2 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o + .debug_line 0x00009710 0xd48 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o + .debug_line 0x0000a458 0x106c ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + .debug_line 0x0000b4c4 0x1198 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o + .debug_line 0x0000c65c 0x3f50 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + .debug_line 0x000105ac 0x2030 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + .debug_line 0x000125dc 0x360e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o + .debug_line 0x00015bea 0xd1e ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o -.debug_str 0x00000000 0xdb63e - .debug_str 0x00000000 0xdb63e ./Core/Src/main.o - 0xd64c2 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Core/Src/stm32g4xx_hal_msp.o +.debug_str 0x00000000 0xdb650 + .debug_str 0x00000000 0xdb650 ./Core/Src/main.o + 0xd64d4 (size before relaxing) + .debug_str 0x000db650 0x0 ./Core/Src/stm32g4xx_hal_msp.o 0xd2cf7 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Core/Src/stm32g4xx_it.o + .debug_str 0x000db650 0x0 ./Core/Src/stm32g4xx_it.o 0xd2267 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Core/Src/system_stm32g4xx.o + .debug_str 0x000db650 0x0 ./Core/Src/system_stm32g4xx.o 0xd193c (size before relaxing) - .debug_str 0x000db63e 0x0 ./Core/Startup/startup_stm32g431kbtx.o + .debug_str 0x000db650 0x0 ./Core/Startup/startup_stm32g431kbtx.o 0x89 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.o 0xd247b (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.o 0xd2969 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.o 0xd290f (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_cortex.o 0xd2137 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.o 0xd1d16 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_gpio.o 0xd1ac7 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_pwr_ex.o 0xd1e2a (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc.o 0xd2035 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_rcc_ex.o 0xd2036 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.o 0xd2e3a (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.o 0xd2aae (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.o 0xd28f7 (size before relaxing) - .debug_str 0x000db63e 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o + .debug_str 0x000db650 0x0 ./Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.o 0xd20f5 (size before relaxing) .comment 0x00000000 0x43